Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains platform specific structure definitions
4 * and init function used by Meteor Lake PCH.
5 *
6 * Copyright (c) 2022, Intel Corporation.
7 * All Rights Reserved.
8 *
9 */
10
11#include <linux/cpu.h>
12#include <linux/pci.h>
13
14#include "core.h"
15
16#define SOCM_LPM_REQ_GUID 0x11594920
17
18#define PMC_DEVID_SOCM 0xa87f
19
20static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
21
22static struct pmc_info lnl_pmc_info_list[] = {
23 {
24 .guid = SOCM_LPM_REQ_GUID,
25 .devid = PMC_DEVID_SOCM,
26 .map = &lnl_socm_reg_map,
27 },
28 {}
29};
30
31const struct pmc_bit_map lnl_ltr_show_map[] = {
32 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
33 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
34 {"SATA", CNP_PMC_LTR_SATA},
35 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
36 {"XHCI", CNP_PMC_LTR_XHCI},
37 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
38 {"ME", CNP_PMC_LTR_ME},
39 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
40 {"SATA1", CNP_PMC_LTR_EVA},
41 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
42 {"HD_AUDIO", CNP_PMC_LTR_AZ},
43 {"CNV", CNP_PMC_LTR_CNV},
44 {"LPSS", CNP_PMC_LTR_LPSS},
45 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
46 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
47 {"SATA2", CNP_PMC_LTR_CAM},
48 {"ESPI", CNP_PMC_LTR_ESPI},
49 {"SCC", CNP_PMC_LTR_SCC},
50 {"ISH", CNP_PMC_LTR_ISH},
51 {"UFSX2", CNP_PMC_LTR_UFSX2},
52 {"EMMC", CNP_PMC_LTR_EMMC},
53 /*
54 * Check intel_pmc_core_ids[] users of cnp_reg_map for
55 * a list of core SoCs using this.
56 */
57 {"WIGIG", ICL_PMC_LTR_WIGIG},
58 {"THC0", TGL_PMC_LTR_THC0},
59 {"THC1", TGL_PMC_LTR_THC1},
60 {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
61
62 {"ESE", MTL_PMC_LTR_ESE},
63 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
64 {"DMI3", ARL_PMC_LTR_DMI3},
65 {"OSSE", LNL_PMC_LTR_OSSE},
66
67 /* Below two cannot be used for LTR_IGNORE */
68 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
69 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
70 {}
71};
72
73const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
74 {"PMC_PGD0_PG_STS", BIT(0)},
75 {"FUSE_OSSE_PGD0_PG_STS", BIT(1)},
76 {"ESPISPI_PGD0_PG_STS", BIT(2)},
77 {"XHCI_PGD0_PG_STS", BIT(3)},
78 {"SPA_PGD0_PG_STS", BIT(4)},
79 {"SPB_PGD0_PG_STS", BIT(5)},
80 {"SPR16B0_PGD0_PG_STS", BIT(6)},
81 {"GBE_PGD0_PG_STS", BIT(7)},
82 {"SBR8B7_PGD0_PG_STS", BIT(8)},
83 {"SBR8B6_PGD0_PG_STS", BIT(9)},
84 {"SBR16B1_PGD0_PG_STS", BIT(10)},
85 {"SBR8B8_PGD0_PG_STS", BIT(11)},
86 {"ESE_PGD3_PG_STS", BIT(12)},
87 {"D2D_DISP_PGD0_PG_STS", BIT(13)},
88 {"LPSS_PGD0_PG_STS", BIT(14)},
89 {"LPC_PGD0_PG_STS", BIT(15)},
90 {"SMB_PGD0_PG_STS", BIT(16)},
91 {"ISH_PGD0_PG_STS", BIT(17)},
92 {"SBR8B2_PGD0_PG_STS", BIT(18)},
93 {"NPK_PGD0_PG_STS", BIT(19)},
94 {"D2D_NOC_PGD0_PG_STS", BIT(20)},
95 {"SAFSS_PGD0_PG_STS", BIT(21)},
96 {"FUSE_PGD0_PG_STS", BIT(22)},
97 {"D2D_DISP_PGD1_PG_STS", BIT(23)},
98 {"MPFPW1_PGD0_PG_STS", BIT(24)},
99 {"XDCI_PGD0_PG_STS", BIT(25)},
100 {"EXI_PGD0_PG_STS", BIT(26)},
101 {"CSE_PGD0_PG_STS", BIT(27)},
102 {"KVMCC_PGD0_PG_STS", BIT(28)},
103 {"PMT_PGD0_PG_STS", BIT(29)},
104 {"CLINK_PGD0_PG_STS", BIT(30)},
105 {"PTIO_PGD0_PG_STS", BIT(31)},
106 {}
107};
108
109const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
110 {"USBR0_PGD0_PG_STS", BIT(0)},
111 {"SUSRAM_PGD0_PG_STS", BIT(1)},
112 {"SMT1_PGD0_PG_STS", BIT(2)},
113 {"U3FPW1_PGD0_PG_STS", BIT(3)},
114 {"SMS2_PGD0_PG_STS", BIT(4)},
115 {"SMS1_PGD0_PG_STS", BIT(5)},
116 {"CSMERTC_PGD0_PG_STS", BIT(6)},
117 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
118 {"FIA_PG_PGD0_PG_STS", BIT(8)},
119 {"SBR16B4_PGD0_PG_STS", BIT(9)},
120 {"P2SB8B_PGD0_PG_STS", BIT(10)},
121 {"DBG_SBR_PGD0_PG_STS", BIT(11)},
122 {"SBR8B9_PGD0_PG_STS", BIT(12)},
123 {"OSSE_SMT1_PGD0_PG_STS", BIT(13)},
124 {"SBR8B10_PGD0_PG_STS", BIT(14)},
125 {"SBR16B3_PGD0_PG_STS", BIT(15)},
126 {"G5FPW1_PGD0_PG_STS", BIT(16)},
127 {"SBRG_PGD0_PG_STS", BIT(17)},
128 {"PSF4_PGD0_PG_STS", BIT(18)},
129 {"CNVI_PGD0_PG_STS", BIT(19)},
130 {"USFX2_PGD0_PG_STS", BIT(20)},
131 {"ENDBG_PGD0_PG_STS", BIT(21)},
132 {"FIACPCB_P5X4_PGD0_PG_STS", BIT(22)},
133 {"SBR8B3_PGD0_PG_STS", BIT(23)},
134 {"SBR8B0_PGD0_PG_STS", BIT(24)},
135 {"NPK_PGD1_PG_STS", BIT(25)},
136 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(26)},
137 {"D2D_NOC_PGD2_PG_STS", BIT(27)},
138 {"SBR8B1_PGD0_PG_STS", BIT(28)},
139 {"PSF6_PGD0_PG_STS", BIT(29)},
140 {"PSF7_PGD0_PG_STS", BIT(30)},
141 {"FIA_U_PGD0_PG_STS", BIT(31)},
142 {}
143};
144
145const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
146 {"PSF8_PGD0_PG_STS", BIT(0)},
147 {"SBR16B2_PGD0_PG_STS", BIT(1)},
148 {"D2D_IPU_PGD0_PG_STS", BIT(2)},
149 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},
150 {"TAM_PGD0_PG_STS", BIT(4)},
151 {"D2D_NOC_PGD1_PG_STS", BIT(5)},
152 {"TBTLSX_PGD0_PG_STS", BIT(6)},
153 {"THC0_PGD0_PG_STS", BIT(7)},
154 {"THC1_PGD0_PG_STS", BIT(8)},
155 {"PMC_PGD0_PG_STS", BIT(9)},
156 {"SBR8B5_PGD0_PG_STS", BIT(10)},
157 {"UFSPW1_PGD0_PG_STS", BIT(11)},
158 {"DBC_PGD0_PG_STS", BIT(12)},
159 {"TCSS_PGD0_PG_STS", BIT(13)},
160 {"FIA_P5X4_PGD0_PG_STS", BIT(14)},
161 {"DISP_PGA_PGD0_PG_STS", BIT(15)},
162 {"DISP_PSF_PGD0_PG_STS", BIT(16)},
163 {"PSF0_PGD0_PG_STS", BIT(17)},
164 {"P2SB16B_PGD0_PG_STS", BIT(18)},
165 {"ACE_PGD0_PG_STS", BIT(19)},
166 {"ACE_PGD1_PG_STS", BIT(20)},
167 {"ACE_PGD2_PG_STS", BIT(21)},
168 {"ACE_PGD3_PG_STS", BIT(22)},
169 {"ACE_PGD4_PG_STS", BIT(23)},
170 {"ACE_PGD5_PG_STS", BIT(24)},
171 {"ACE_PGD6_PG_STS", BIT(25)},
172 {"ACE_PGD7_PG_STS", BIT(26)},
173 {"ACE_PGD8_PG_STS", BIT(27)},
174 {"ACE_PGD9_PG_STS", BIT(28)},
175 {"ACE_PGD10_PG_STS", BIT(29)},
176 {"FIACPCB_PG_PGD0_PG_STS", BIT(30)},
177 {"OSSE_PGD0_PG_STS", BIT(31)},
178 {}
179};
180
181const struct pmc_bit_map lnl_d3_status_0_map[] = {
182 {"LPSS_D3_STS", BIT(3)},
183 {"XDCI_D3_STS", BIT(4)},
184 {"XHCI_D3_STS", BIT(5)},
185 {"SPA_D3_STS", BIT(12)},
186 {"SPB_D3_STS", BIT(13)},
187 {"OSSE_D3_STS", BIT(15)},
188 {"ESPISPI_D3_STS", BIT(18)},
189 {"PSTH_D3_STS", BIT(21)},
190 {}
191};
192
193const struct pmc_bit_map lnl_d3_status_1_map[] = {
194 {"OSSE_SMT1_D3_STS", BIT(7)},
195 {"GBE_D3_STS", BIT(19)},
196 {"ITSS_D3_STS", BIT(23)},
197 {"CNVI_D3_STS", BIT(27)},
198 {"UFSX2_D3_STS", BIT(28)},
199 {"OSSE_HOTHAM_D3_STS", BIT(31)},
200 {}
201};
202
203const struct pmc_bit_map lnl_d3_status_2_map[] = {
204 {"ESE_D3_STS", BIT(0)},
205 {"CSMERTC_D3_STS", BIT(1)},
206 {"SUSRAM_D3_STS", BIT(2)},
207 {"CSE_D3_STS", BIT(4)},
208 {"KVMCC_D3_STS", BIT(5)},
209 {"USBR0_D3_STS", BIT(6)},
210 {"ISH_D3_STS", BIT(7)},
211 {"SMT1_D3_STS", BIT(8)},
212 {"SMT2_D3_STS", BIT(9)},
213 {"SMT3_D3_STS", BIT(10)},
214 {"OSSE_SMT2_D3_STS", BIT(13)},
215 {"CLINK_D3_STS", BIT(14)},
216 {"PTIO_D3_STS", BIT(16)},
217 {"PMT_D3_STS", BIT(17)},
218 {"SMS1_D3_STS", BIT(18)},
219 {"SMS2_D3_STS", BIT(19)},
220 {}
221};
222
223const struct pmc_bit_map lnl_d3_status_3_map[] = {
224 {"THC0_D3_STS", BIT(14)},
225 {"THC1_D3_STS", BIT(15)},
226 {"OSSE_SMT3_D3_STS", BIT(21)},
227 {"ACE_D3_STS", BIT(23)},
228 {}
229};
230
231const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
232 {"LPSS_VNN_REQ_STS", BIT(3)},
233 {"OSSE_VNN_REQ_STS", BIT(15)},
234 {"ESPISPI_VNN_REQ_STS", BIT(18)},
235 {}
236};
237
238const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
239 {"NPK_VNN_REQ_STS", BIT(4)},
240 {"OSSE_SMT1_VNN_REQ_STS", BIT(7)},
241 {"DFXAGG_VNN_REQ_STS", BIT(8)},
242 {"EXI_VNN_REQ_STS", BIT(9)},
243 {"P2D_VNN_REQ_STS", BIT(18)},
244 {"GBE_VNN_REQ_STS", BIT(19)},
245 {"SMB_VNN_REQ_STS", BIT(25)},
246 {"LPC_VNN_REQ_STS", BIT(26)},
247 {}
248};
249
250const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
251 {"eSE_VNN_REQ_STS", BIT(0)},
252 {"CSMERTC_VNN_REQ_STS", BIT(1)},
253 {"CSE_VNN_REQ_STS", BIT(4)},
254 {"ISH_VNN_REQ_STS", BIT(7)},
255 {"SMT1_VNN_REQ_STS", BIT(8)},
256 {"CLINK_VNN_REQ_STS", BIT(14)},
257 {"SMS1_VNN_REQ_STS", BIT(18)},
258 {"SMS2_VNN_REQ_STS", BIT(19)},
259 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
260 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
261 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
262 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
263 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
264 {}
265};
266
267const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
268 {"DISP_SHIM_VNN_REQ_STS", BIT(2)},
269 {"DTS0_VNN_REQ_STS", BIT(7)},
270 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
271 {}
272};
273
274const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
275 {"CPU_C10_REQ_STS", BIT(0)},
276 {"TS_OFF_REQ_STS", BIT(1)},
277 {"PNDE_MET_REQ_STS", BIT(2)},
278 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
279 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},
280 {"NPK_VNNAON_REQ_STS", BIT(5)},
281 {"VNN_SOC_REQ_STS", BIT(6)},
282 {"ISH_VNNAON_REQ_STS", BIT(7)},
283 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8)},
284 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9)},
285 {"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10)},
286 {"PLT_GREATER_REQ_STS", BIT(11)},
287 {"PCIE_CLKREQ_REQ_STS", BIT(12)},
288 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
289 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
290 {"EA_REQ_STS", BIT(15)},
291 {"MPHY_CORE_OFF_REQ_STS", BIT(16)},
292 {"BRK_EV_EN_REQ_STS", BIT(17)},
293 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
294 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
295 {"LPC_CLK_SRC_REQ_STS", BIT(20)},
296 {"ARC_IDLE_REQ_STS", BIT(21)},
297 {"MPHY_SUS_REQ_STS", BIT(22)},
298 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
299 {"UXD_CONNECTED_REQ_STS", BIT(24)},
300 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
301 {"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26)},
302 {"PRE_WAKE0_REQ_STS", BIT(27)},
303 {"PRE_WAKE1_REQ_STS", BIT(28)},
304 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
305 {"WOV_REQ_STS", BIT(30)},
306 {"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31)},
307 {}
308};
309
310const struct pmc_bit_map lnl_clocksource_status_map[] = {
311 {"AON2_OFF_STS", BIT(0)},
312 {"AON3_OFF_STS", BIT(1)},
313 {"AON4_OFF_STS", BIT(2)},
314 {"AON5_OFF_STS", BIT(3)},
315 {"AON1_OFF_STS", BIT(4)},
316 {"MPFPW1_0_PLL_OFF_STS", BIT(6)},
317 {"USB3_PLL_OFF_STS", BIT(8)},
318 {"AON3_SPL_OFF_STS", BIT(9)},
319 {"G5FPW1_PLL_OFF_STS", BIT(15)},
320 {"XTAL_AGGR_OFF_STS", BIT(17)},
321 {"USB2_PLL_OFF_STS", BIT(18)},
322 {"SAF_PLL_OFF_STS", BIT(19)},
323 {"SE_TCSS_PLL_OFF_STS", BIT(20)},
324 {"DDI_PLL_OFF_STS", BIT(21)},
325 {"FILTER_PLL_OFF_STS", BIT(22)},
326 {"ACE_PLL_OFF_STS", BIT(24)},
327 {"FABRIC_PLL_OFF_STS", BIT(25)},
328 {"SOC_PLL_OFF_STS", BIT(26)},
329 {"REF_OFF_STS", BIT(28)},
330 {"IMG_OFF_STS", BIT(29)},
331 {"RTC_PLL_OFF_STS", BIT(31)},
332 {}
333};
334
335const struct pmc_bit_map *lnl_lpm_maps[] = {
336 lnl_clocksource_status_map,
337 lnl_power_gating_status_0_map,
338 lnl_power_gating_status_1_map,
339 lnl_power_gating_status_2_map,
340 lnl_d3_status_0_map,
341 lnl_d3_status_1_map,
342 lnl_d3_status_2_map,
343 lnl_d3_status_3_map,
344 lnl_vnn_req_status_0_map,
345 lnl_vnn_req_status_1_map,
346 lnl_vnn_req_status_2_map,
347 lnl_vnn_req_status_3_map,
348 lnl_vnn_misc_status_map,
349 mtl_socm_signal_status_map,
350 NULL
351};
352
353const struct pmc_bit_map lnl_pfear_map[] = {
354 {"PMC_0", BIT(0)},
355 {"FUSE_OSSE", BIT(1)},
356 {"ESPISPI", BIT(2)},
357 {"XHCI", BIT(3)},
358 {"SPA", BIT(4)},
359 {"SPB", BIT(5)},
360 {"SBR16B0", BIT(6)},
361 {"GBE", BIT(7)},
362
363 {"SBR8B7", BIT(0)},
364 {"SBR8B6", BIT(1)},
365 {"SBR16B1", BIT(1)},
366 {"SBR8B8", BIT(2)},
367 {"ESE", BIT(3)},
368 {"SBR8B10", BIT(4)},
369 {"D2D_DISP_0", BIT(5)},
370 {"LPSS", BIT(6)},
371 {"LPC", BIT(7)},
372
373 {"SMB", BIT(0)},
374 {"ISH", BIT(1)},
375 {"SBR8B2", BIT(2)},
376 {"NPK_0", BIT(3)},
377 {"D2D_NOC_0", BIT(4)},
378 {"SAFSS", BIT(5)},
379 {"FUSE", BIT(6)},
380 {"D2D_DISP_1", BIT(7)},
381
382 {"MPFPW1", BIT(0)},
383 {"XDCI", BIT(1)},
384 {"EXI", BIT(2)},
385 {"CSE", BIT(3)},
386 {"KVMCC", BIT(4)},
387 {"PMT", BIT(5)},
388 {"CLINK", BIT(6)},
389 {"PTIO", BIT(7)},
390
391 {"USBR", BIT(0)},
392 {"SUSRAM", BIT(1)},
393 {"SMT1", BIT(2)},
394 {"U3FPW1", BIT(3)},
395 {"SMS2", BIT(4)},
396 {"SMS1", BIT(5)},
397 {"CSMERTC", BIT(6)},
398 {"CSMEPSF", BIT(7)},
399
400 {"FIA_PG", BIT(0)},
401 {"SBR16B4", BIT(1)},
402 {"P2SB8B", BIT(2)},
403 {"DBG_SBR", BIT(3)},
404 {"SBR8B9", BIT(4)},
405 {"OSSE_SMT1", BIT(5)},
406 {"SBR8B10", BIT(6)},
407 {"SBR16B3", BIT(7)},
408
409 {"G5FPW1", BIT(0)},
410 {"SBRG", BIT(1)},
411 {"PSF4", BIT(2)},
412 {"CNVI", BIT(3)},
413 {"UFSX2", BIT(4)},
414 {"ENDBG", BIT(5)},
415 {"FIACPCB_P5X4", BIT(6)},
416 {"SBR8B3", BIT(7)},
417
418 {"SBR8B0", BIT(0)},
419 {"NPK_1", BIT(1)},
420 {"OSSE_HOTHAM", BIT(2)},
421 {"D2D_NOC_2", BIT(3)},
422 {"SBR8B1", BIT(4)},
423 {"PSF6", BIT(5)},
424 {"PSF7", BIT(6)},
425 {"FIA_U", BIT(7)},
426
427 {"PSF8", BIT(0)},
428 {"SBR16B2", BIT(1)},
429 {"D2D_IPU", BIT(2)},
430 {"FIACPCB_U", BIT(3)},
431 {"TAM", BIT(4)},
432 {"D2D_NOC_1", BIT(5)},
433 {"TBTLSX", BIT(6)},
434 {"THC0", BIT(7)},
435
436 {"THC1", BIT(0)},
437 {"PMC_1", BIT(1)},
438 {"SBR8B5", BIT(2)},
439 {"UFSPW1", BIT(3)},
440 {"DBC", BIT(4)},
441 {"TCSS", BIT(5)},
442 {"FIA_P5X4", BIT(6)},
443 {"DISP_PGA", BIT(7)},
444
445 {"DBG_PSF", BIT(0)},
446 {"PSF0", BIT(1)},
447 {"P2SB16B", BIT(2)},
448 {"ACE0", BIT(3)},
449 {"ACE1", BIT(4)},
450 {"ACE2", BIT(5)},
451 {"ACE3", BIT(6)},
452 {"ACE4", BIT(7)},
453
454 {"ACE5", BIT(0)},
455 {"ACE6", BIT(1)},
456 {"ACE7", BIT(2)},
457 {"ACE8", BIT(3)},
458 {"ACE9", BIT(4)},
459 {"ACE10", BIT(5)},
460 {"FIACPCB", BIT(6)},
461 {"OSSE", BIT(7)},
462 {}
463};
464
465const struct pmc_bit_map *ext_lnl_pfear_map[] = {
466 lnl_pfear_map,
467 NULL
468};
469
470const struct pmc_reg_map lnl_socm_reg_map = {
471 .pfear_sts = ext_lnl_pfear_map,
472 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
473 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
474 .ltr_show_sts = lnl_ltr_show_map,
475 .msr_sts = msr_map,
476 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
477 .regmap_length = LNL_PMC_MMIO_REG_LEN,
478 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
479 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
480 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
481 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
482 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
483 .lpm_num_maps = ADL_LPM_NUM_MAPS,
484 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
485 .etr3_offset = ETR3_OFFSET,
486 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
487 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
488 .lpm_en_offset = MTL_LPM_EN_OFFSET,
489 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
490 .lpm_sts = lnl_lpm_maps,
491 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
492 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
493 .lpm_reg_index = LNL_LPM_REG_INDEX,
494};
495
496#define LNL_NPU_PCI_DEV 0x643e
497#define LNL_IPU_PCI_DEV 0x645d
498
499/*
500 * Set power state of select devices that do not have drivers to D3
501 * so that they do not block Package C entry.
502 */
503static void lnl_d3_fixup(void)
504{
505 pmc_core_set_device_d3(LNL_IPU_PCI_DEV);
506 pmc_core_set_device_d3(LNL_NPU_PCI_DEV);
507}
508
509static int lnl_resume(struct pmc_dev *pmcdev)
510{
511 lnl_d3_fixup();
512 pmc_core_send_ltr_ignore(pmcdev, 3, 0);
513
514 return pmc_core_resume_common(pmcdev);
515}
516
517int lnl_core_init(struct pmc_dev *pmcdev)
518{
519 int ret;
520 int func = 2;
521 bool ssram_init = true;
522 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];
523
524 lnl_d3_fixup();
525
526 pmcdev->suspend = cnl_suspend;
527 pmcdev->resume = lnl_resume;
528 pmcdev->regmap_list = lnl_pmc_info_list;
529 ret = pmc_core_ssram_init(pmcdev, func);
530
531 /* If regbase not assigned, set map and discover using legacy method */
532 if (ret) {
533 ssram_init = false;
534 pmc->map = &lnl_socm_reg_map;
535 ret = get_primary_reg_base(pmc);
536 if (ret)
537 return ret;
538 }
539
540 pmc_core_get_low_power_modes(pmcdev);
541
542 if (ssram_init) {
543 ret = pmc_core_ssram_get_lpm_reqs(pmcdev);
544 if (ret)
545 return ret;
546 }
547
548 return 0;
549}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains platform specific structure definitions
4 * and init function used by Lunar Lake PCH.
5 *
6 * Copyright (c) 2022, Intel Corporation.
7 * All Rights Reserved.
8 *
9 */
10
11#include <linux/cpu.h>
12#include <linux/pci.h>
13
14#include "core.h"
15
16const struct pmc_bit_map lnl_ltr_show_map[] = {
17 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
18 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
19 {"SATA", CNP_PMC_LTR_SATA},
20 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
21 {"XHCI", CNP_PMC_LTR_XHCI},
22 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
23 {"ME", CNP_PMC_LTR_ME},
24 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
25 {"SATA1", CNP_PMC_LTR_EVA},
26 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
27 {"HD_AUDIO", CNP_PMC_LTR_AZ},
28 {"CNV", CNP_PMC_LTR_CNV},
29 {"LPSS", CNP_PMC_LTR_LPSS},
30 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
31 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
32 {"SATA2", CNP_PMC_LTR_CAM},
33 {"ESPI", CNP_PMC_LTR_ESPI},
34 {"SCC", CNP_PMC_LTR_SCC},
35 {"ISH", CNP_PMC_LTR_ISH},
36 {"UFSX2", CNP_PMC_LTR_UFSX2},
37 {"EMMC", CNP_PMC_LTR_EMMC},
38 /*
39 * Check intel_pmc_core_ids[] users of cnp_reg_map for
40 * a list of core SoCs using this.
41 */
42 {"WIGIG", ICL_PMC_LTR_WIGIG},
43 {"THC0", TGL_PMC_LTR_THC0},
44 {"THC1", TGL_PMC_LTR_THC1},
45 {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
46
47 {"ESE", MTL_PMC_LTR_ESE},
48 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
49 {"DMI3", ARL_PMC_LTR_DMI3},
50 {"OSSE", LNL_PMC_LTR_OSSE},
51
52 /* Below two cannot be used for LTR_IGNORE */
53 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
54 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
55 {}
56};
57
58const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
59 {"PMC_PGD0_PG_STS", BIT(0), 0},
60 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
61 {"ESPISPI_PGD0_PG_STS", BIT(2), 0},
62 {"XHCI_PGD0_PG_STS", BIT(3), 1},
63 {"SPA_PGD0_PG_STS", BIT(4), 1},
64 {"SPB_PGD0_PG_STS", BIT(5), 1},
65 {"SPR16B0_PGD0_PG_STS", BIT(6), 0},
66 {"GBE_PGD0_PG_STS", BIT(7), 1},
67 {"SBR8B7_PGD0_PG_STS", BIT(8), 0},
68 {"SBR8B6_PGD0_PG_STS", BIT(9), 0},
69 {"SBR16B1_PGD0_PG_STS", BIT(10), 0},
70 {"SBR8B8_PGD0_PG_STS", BIT(11), 0},
71 {"ESE_PGD3_PG_STS", BIT(12), 1},
72 {"D2D_DISP_PGD0_PG_STS", BIT(13), 1},
73 {"LPSS_PGD0_PG_STS", BIT(14), 1},
74 {"LPC_PGD0_PG_STS", BIT(15), 0},
75 {"SMB_PGD0_PG_STS", BIT(16), 0},
76 {"ISH_PGD0_PG_STS", BIT(17), 0},
77 {"SBR8B2_PGD0_PG_STS", BIT(18), 0},
78 {"NPK_PGD0_PG_STS", BIT(19), 0},
79 {"D2D_NOC_PGD0_PG_STS", BIT(20), 0},
80 {"SAFSS_PGD0_PG_STS", BIT(21), 0},
81 {"FUSE_PGD0_PG_STS", BIT(22), 0},
82 {"D2D_DISP_PGD1_PG_STS", BIT(23), 1},
83 {"MPFPW1_PGD0_PG_STS", BIT(24), 0},
84 {"XDCI_PGD0_PG_STS", BIT(25), 1},
85 {"EXI_PGD0_PG_STS", BIT(26), 0},
86 {"CSE_PGD0_PG_STS", BIT(27), 1},
87 {"KVMCC_PGD0_PG_STS", BIT(28), 1},
88 {"PMT_PGD0_PG_STS", BIT(29), 1},
89 {"CLINK_PGD0_PG_STS", BIT(30), 1},
90 {"PTIO_PGD0_PG_STS", BIT(31), 1},
91 {}
92};
93
94const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
95 {"USBR0_PGD0_PG_STS", BIT(0), 1},
96 {"SUSRAM_PGD0_PG_STS", BIT(1), 1},
97 {"SMT1_PGD0_PG_STS", BIT(2), 1},
98 {"U3FPW1_PGD0_PG_STS", BIT(3), 0},
99 {"SMS2_PGD0_PG_STS", BIT(4), 1},
100 {"SMS1_PGD0_PG_STS", BIT(5), 1},
101 {"CSMERTC_PGD0_PG_STS", BIT(6), 0},
102 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
103 {"FIA_PG_PGD0_PG_STS", BIT(8), 0},
104 {"SBR16B4_PGD0_PG_STS", BIT(9), 0},
105 {"P2SB8B_PGD0_PG_STS", BIT(10), 1},
106 {"DBG_SBR_PGD0_PG_STS", BIT(11), 0},
107 {"SBR8B9_PGD0_PG_STS", BIT(12), 0},
108 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
109 {"SBR8B10_PGD0_PG_STS", BIT(14), 0},
110 {"SBR16B3_PGD0_PG_STS", BIT(15), 0},
111 {"G5FPW1_PGD0_PG_STS", BIT(16), 0},
112 {"SBRG_PGD0_PG_STS", BIT(17), 0},
113 {"PSF4_PGD0_PG_STS", BIT(18), 0},
114 {"CNVI_PGD0_PG_STS", BIT(19), 0},
115 {"USFX2_PGD0_PG_STS", BIT(20), 1},
116 {"ENDBG_PGD0_PG_STS", BIT(21), 0},
117 {"FIACPCB_P5X4_PGD0_PG_STS", BIT(22), 0},
118 {"SBR8B3_PGD0_PG_STS", BIT(23), 0},
119 {"SBR8B0_PGD0_PG_STS", BIT(24), 0},
120 {"NPK_PGD1_PG_STS", BIT(25), 0},
121 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(26), 1},
122 {"D2D_NOC_PGD2_PG_STS", BIT(27), 1},
123 {"SBR8B1_PGD0_PG_STS", BIT(28), 0},
124 {"PSF6_PGD0_PG_STS", BIT(29), 0},
125 {"PSF7_PGD0_PG_STS", BIT(30), 0},
126 {"FIA_U_PGD0_PG_STS", BIT(31), 0},
127 {}
128};
129
130const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
131 {"PSF8_PGD0_PG_STS", BIT(0), 0},
132 {"SBR16B2_PGD0_PG_STS", BIT(1), 0},
133 {"D2D_IPU_PGD0_PG_STS", BIT(2), 1},
134 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
135 {"TAM_PGD0_PG_STS", BIT(4), 1},
136 {"D2D_NOC_PGD1_PG_STS", BIT(5), 1},
137 {"TBTLSX_PGD0_PG_STS", BIT(6), 1},
138 {"THC0_PGD0_PG_STS", BIT(7), 1},
139 {"THC1_PGD0_PG_STS", BIT(8), 1},
140 {"PMC_PGD0_PG_STS", BIT(9), 0},
141 {"SBR8B5_PGD0_PG_STS", BIT(10), 0},
142 {"UFSPW1_PGD0_PG_STS", BIT(11), 0},
143 {"DBC_PGD0_PG_STS", BIT(12), 0},
144 {"TCSS_PGD0_PG_STS", BIT(13), 0},
145 {"FIA_P5X4_PGD0_PG_STS", BIT(14), 0},
146 {"DISP_PGA_PGD0_PG_STS", BIT(15), 0},
147 {"DISP_PSF_PGD0_PG_STS", BIT(16), 0},
148 {"PSF0_PGD0_PG_STS", BIT(17), 0},
149 {"P2SB16B_PGD0_PG_STS", BIT(18), 1},
150 {"ACE_PGD0_PG_STS", BIT(19), 0},
151 {"ACE_PGD1_PG_STS", BIT(20), 0},
152 {"ACE_PGD2_PG_STS", BIT(21), 0},
153 {"ACE_PGD3_PG_STS", BIT(22), 0},
154 {"ACE_PGD4_PG_STS", BIT(23), 0},
155 {"ACE_PGD5_PG_STS", BIT(24), 0},
156 {"ACE_PGD6_PG_STS", BIT(25), 0},
157 {"ACE_PGD7_PG_STS", BIT(26), 0},
158 {"ACE_PGD8_PG_STS", BIT(27), 0},
159 {"ACE_PGD9_PG_STS", BIT(28), 0},
160 {"ACE_PGD10_PG_STS", BIT(29), 0},
161 {"FIACPCB_PG_PGD0_PG_STS", BIT(30), 0},
162 {"OSSE_PGD0_PG_STS", BIT(31), 1},
163 {}
164};
165
166const struct pmc_bit_map lnl_d3_status_0_map[] = {
167 {"LPSS_D3_STS", BIT(3), 1},
168 {"XDCI_D3_STS", BIT(4), 1},
169 {"XHCI_D3_STS", BIT(5), 1},
170 {"SPA_D3_STS", BIT(12), 0},
171 {"SPB_D3_STS", BIT(13), 0},
172 {"OSSE_D3_STS", BIT(15), 0},
173 {"ESPISPI_D3_STS", BIT(18), 0},
174 {"PSTH_D3_STS", BIT(21), 0},
175 {}
176};
177
178const struct pmc_bit_map lnl_d3_status_1_map[] = {
179 {"OSSE_SMT1_D3_STS", BIT(7), 0},
180 {"GBE_D3_STS", BIT(19), 0},
181 {"ITSS_D3_STS", BIT(23), 0},
182 {"CNVI_D3_STS", BIT(27), 0},
183 {"UFSX2_D3_STS", BIT(28), 1},
184 {"OSSE_HOTHAM_D3_STS", BIT(31), 0},
185 {}
186};
187
188const struct pmc_bit_map lnl_d3_status_2_map[] = {
189 {"ESE_D3_STS", BIT(0), 0},
190 {"CSMERTC_D3_STS", BIT(1), 0},
191 {"SUSRAM_D3_STS", BIT(2), 0},
192 {"CSE_D3_STS", BIT(4), 0},
193 {"KVMCC_D3_STS", BIT(5), 0},
194 {"USBR0_D3_STS", BIT(6), 0},
195 {"ISH_D3_STS", BIT(7), 0},
196 {"SMT1_D3_STS", BIT(8), 0},
197 {"SMT2_D3_STS", BIT(9), 0},
198 {"SMT3_D3_STS", BIT(10), 0},
199 {"OSSE_SMT2_D3_STS", BIT(13), 0},
200 {"CLINK_D3_STS", BIT(14), 0},
201 {"PTIO_D3_STS", BIT(16), 0},
202 {"PMT_D3_STS", BIT(17), 0},
203 {"SMS1_D3_STS", BIT(18), 0},
204 {"SMS2_D3_STS", BIT(19), 0},
205 {}
206};
207
208const struct pmc_bit_map lnl_d3_status_3_map[] = {
209 {"THC0_D3_STS", BIT(14), 1},
210 {"THC1_D3_STS", BIT(15), 1},
211 {"OSSE_SMT3_D3_STS", BIT(21), 0},
212 {"ACE_D3_STS", BIT(23), 0},
213 {}
214};
215
216const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
217 {"LPSS_VNN_REQ_STS", BIT(3), 1},
218 {"OSSE_VNN_REQ_STS", BIT(15), 1},
219 {"ESPISPI_VNN_REQ_STS", BIT(18), 1},
220 {}
221};
222
223const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
224 {"NPK_VNN_REQ_STS", BIT(4), 1},
225 {"OSSE_SMT1_VNN_REQ_STS", BIT(7), 1},
226 {"DFXAGG_VNN_REQ_STS", BIT(8), 0},
227 {"EXI_VNN_REQ_STS", BIT(9), 1},
228 {"P2D_VNN_REQ_STS", BIT(18), 1},
229 {"GBE_VNN_REQ_STS", BIT(19), 1},
230 {"SMB_VNN_REQ_STS", BIT(25), 1},
231 {"LPC_VNN_REQ_STS", BIT(26), 0},
232 {}
233};
234
235const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
236 {"eSE_VNN_REQ_STS", BIT(0), 1},
237 {"CSMERTC_VNN_REQ_STS", BIT(1), 1},
238 {"CSE_VNN_REQ_STS", BIT(4), 1},
239 {"ISH_VNN_REQ_STS", BIT(7), 1},
240 {"SMT1_VNN_REQ_STS", BIT(8), 1},
241 {"CLINK_VNN_REQ_STS", BIT(14), 1},
242 {"SMS1_VNN_REQ_STS", BIT(18), 1},
243 {"SMS2_VNN_REQ_STS", BIT(19), 1},
244 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
245 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
246 {"GPIOCOM2_VNN_REQ_STS", BIT(22), 0},
247 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
248 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
249 {}
250};
251
252const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
253 {"DISP_SHIM_VNN_REQ_STS", BIT(2), 0},
254 {"DTS0_VNN_REQ_STS", BIT(7), 0},
255 {"GPIOCOM5_VNN_REQ_STS", BIT(11), 2},
256 {}
257};
258
259const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
260 {"CPU_C10_REQ_STS", BIT(0), 0},
261 {"TS_OFF_REQ_STS", BIT(1), 0},
262 {"PNDE_MET_REQ_STS", BIT(2), 1},
263 {"PCIE_DEEP_PM_REQ_STS", BIT(3), 0},
264 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4), 0},
265 {"NPK_VNNAON_REQ_STS", BIT(5), 0},
266 {"VNN_SOC_REQ_STS", BIT(6), 1},
267 {"ISH_VNNAON_REQ_STS", BIT(7), 0},
268 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
269 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
270 {"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10), 1},
271 {"PLT_GREATER_REQ_STS", BIT(11), 1},
272 {"PCIE_CLKREQ_REQ_STS", BIT(12), 0},
273 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
274 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
275 {"EA_REQ_STS", BIT(15), 0},
276 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
277 {"BRK_EV_EN_REQ_STS", BIT(17), 0},
278 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
279 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
280 {"LPC_CLK_SRC_REQ_STS", BIT(20), 0},
281 {"ARC_IDLE_REQ_STS", BIT(21), 0},
282 {"MPHY_SUS_REQ_STS", BIT(22), 0},
283 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
284 {"UXD_CONNECTED_REQ_STS", BIT(24), 1},
285 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
286 {"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
287 {"PRE_WAKE0_REQ_STS", BIT(27), 1},
288 {"PRE_WAKE1_REQ_STS", BIT(28), 1},
289 {"PRE_WAKE2_EN_REQ_STS", BIT(29), 1},
290 {"WOV_REQ_STS", BIT(30), 0},
291 {"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31), 1},
292 {}
293};
294
295const struct pmc_bit_map lnl_clocksource_status_map[] = {
296 {"AON2_OFF_STS", BIT(0), 0},
297 {"AON3_OFF_STS", BIT(1), 1},
298 {"AON4_OFF_STS", BIT(2), 1},
299 {"AON5_OFF_STS", BIT(3), 1},
300 {"AON1_OFF_STS", BIT(4), 0},
301 {"MPFPW1_0_PLL_OFF_STS", BIT(6), 1},
302 {"USB3_PLL_OFF_STS", BIT(8), 1},
303 {"AON3_SPL_OFF_STS", BIT(9), 1},
304 {"G5FPW1_PLL_OFF_STS", BIT(15), 1},
305 {"XTAL_AGGR_OFF_STS", BIT(17), 1},
306 {"USB2_PLL_OFF_STS", BIT(18), 0},
307 {"SAF_PLL_OFF_STS", BIT(19), 1},
308 {"SE_TCSS_PLL_OFF_STS", BIT(20), 1},
309 {"DDI_PLL_OFF_STS", BIT(21), 1},
310 {"FILTER_PLL_OFF_STS", BIT(22), 1},
311 {"ACE_PLL_OFF_STS", BIT(24), 0},
312 {"FABRIC_PLL_OFF_STS", BIT(25), 1},
313 {"SOC_PLL_OFF_STS", BIT(26), 1},
314 {"REF_OFF_STS", BIT(28), 1},
315 {"IMG_OFF_STS", BIT(29), 1},
316 {"RTC_PLL_OFF_STS", BIT(31), 0},
317 {}
318};
319
320const struct pmc_bit_map lnl_signal_status_map[] = {
321 {"LSX_Wake0_STS", BIT(0), 0},
322 {"LSX_Wake1_STS", BIT(1), 0},
323 {"LSX_Wake2_STS", BIT(2), 0},
324 {"LSX_Wake3_STS", BIT(3), 0},
325 {"LSX_Wake4_STS", BIT(4), 0},
326 {"LSX_Wake5_STS", BIT(5), 0},
327 {"LSX_Wake6_STS", BIT(6), 0},
328 {"LSX_Wake7_STS", BIT(7), 0},
329 {"LPSS_Wake0_STS", BIT(8), 1},
330 {"LPSS_Wake1_STS", BIT(9), 1},
331 {"Int_Timer_SS_Wake0_STS", BIT(10), 1},
332 {"Int_Timer_SS_Wake1_STS", BIT(11), 1},
333 {"Int_Timer_SS_Wake2_STS", BIT(12), 1},
334 {"Int_Timer_SS_Wake3_STS", BIT(13), 1},
335 {"Int_Timer_SS_Wake4_STS", BIT(14), 1},
336 {"Int_Timer_SS_Wake5_STS", BIT(15), 1},
337 {}
338};
339
340const struct pmc_bit_map lnl_rsc_status_map[] = {
341 {"Memory", 0, 1},
342 {"PSF0", 0, 1},
343 {"PSF4", 0, 1},
344 {"PSF6", 0, 1},
345 {"PSF7", 0, 1},
346 {"PSF8", 0, 1},
347 {"SAF_CFI_LINK", 0, 1},
348 {"SBR", 0, 1},
349 {}
350};
351
352const struct pmc_bit_map *lnl_lpm_maps[] = {
353 lnl_clocksource_status_map,
354 lnl_power_gating_status_0_map,
355 lnl_power_gating_status_1_map,
356 lnl_power_gating_status_2_map,
357 lnl_d3_status_0_map,
358 lnl_d3_status_1_map,
359 lnl_d3_status_2_map,
360 lnl_d3_status_3_map,
361 lnl_vnn_req_status_0_map,
362 lnl_vnn_req_status_1_map,
363 lnl_vnn_req_status_2_map,
364 lnl_vnn_req_status_3_map,
365 lnl_vnn_misc_status_map,
366 lnl_signal_status_map,
367 NULL
368};
369
370const struct pmc_bit_map *lnl_blk_maps[] = {
371 lnl_power_gating_status_0_map,
372 lnl_power_gating_status_1_map,
373 lnl_power_gating_status_2_map,
374 lnl_rsc_status_map,
375 lnl_vnn_req_status_0_map,
376 lnl_vnn_req_status_1_map,
377 lnl_vnn_req_status_2_map,
378 lnl_vnn_req_status_3_map,
379 lnl_d3_status_0_map,
380 lnl_d3_status_1_map,
381 lnl_d3_status_2_map,
382 lnl_d3_status_3_map,
383 lnl_clocksource_status_map,
384 lnl_vnn_misc_status_map,
385 lnl_signal_status_map,
386 NULL
387};
388
389const struct pmc_bit_map lnl_pfear_map[] = {
390 {"PMC_0", BIT(0)},
391 {"FUSE_OSSE", BIT(1)},
392 {"ESPISPI", BIT(2)},
393 {"XHCI", BIT(3)},
394 {"SPA", BIT(4)},
395 {"SPB", BIT(5)},
396 {"SBR16B0", BIT(6)},
397 {"GBE", BIT(7)},
398
399 {"SBR8B7", BIT(0)},
400 {"SBR8B6", BIT(1)},
401 {"SBR16B1", BIT(1)},
402 {"SBR8B8", BIT(2)},
403 {"ESE", BIT(3)},
404 {"SBR8B10", BIT(4)},
405 {"D2D_DISP_0", BIT(5)},
406 {"LPSS", BIT(6)},
407 {"LPC", BIT(7)},
408
409 {"SMB", BIT(0)},
410 {"ISH", BIT(1)},
411 {"SBR8B2", BIT(2)},
412 {"NPK_0", BIT(3)},
413 {"D2D_NOC_0", BIT(4)},
414 {"SAFSS", BIT(5)},
415 {"FUSE", BIT(6)},
416 {"D2D_DISP_1", BIT(7)},
417
418 {"MPFPW1", BIT(0)},
419 {"XDCI", BIT(1)},
420 {"EXI", BIT(2)},
421 {"CSE", BIT(3)},
422 {"KVMCC", BIT(4)},
423 {"PMT", BIT(5)},
424 {"CLINK", BIT(6)},
425 {"PTIO", BIT(7)},
426
427 {"USBR", BIT(0)},
428 {"SUSRAM", BIT(1)},
429 {"SMT1", BIT(2)},
430 {"U3FPW1", BIT(3)},
431 {"SMS2", BIT(4)},
432 {"SMS1", BIT(5)},
433 {"CSMERTC", BIT(6)},
434 {"CSMEPSF", BIT(7)},
435
436 {"FIA_PG", BIT(0)},
437 {"SBR16B4", BIT(1)},
438 {"P2SB8B", BIT(2)},
439 {"DBG_SBR", BIT(3)},
440 {"SBR8B9", BIT(4)},
441 {"OSSE_SMT1", BIT(5)},
442 {"SBR8B10", BIT(6)},
443 {"SBR16B3", BIT(7)},
444
445 {"G5FPW1", BIT(0)},
446 {"SBRG", BIT(1)},
447 {"PSF4", BIT(2)},
448 {"CNVI", BIT(3)},
449 {"UFSX2", BIT(4)},
450 {"ENDBG", BIT(5)},
451 {"FIACPCB_P5X4", BIT(6)},
452 {"SBR8B3", BIT(7)},
453
454 {"SBR8B0", BIT(0)},
455 {"NPK_1", BIT(1)},
456 {"OSSE_HOTHAM", BIT(2)},
457 {"D2D_NOC_2", BIT(3)},
458 {"SBR8B1", BIT(4)},
459 {"PSF6", BIT(5)},
460 {"PSF7", BIT(6)},
461 {"FIA_U", BIT(7)},
462
463 {"PSF8", BIT(0)},
464 {"SBR16B2", BIT(1)},
465 {"D2D_IPU", BIT(2)},
466 {"FIACPCB_U", BIT(3)},
467 {"TAM", BIT(4)},
468 {"D2D_NOC_1", BIT(5)},
469 {"TBTLSX", BIT(6)},
470 {"THC0", BIT(7)},
471
472 {"THC1", BIT(0)},
473 {"PMC_1", BIT(1)},
474 {"SBR8B5", BIT(2)},
475 {"UFSPW1", BIT(3)},
476 {"DBC", BIT(4)},
477 {"TCSS", BIT(5)},
478 {"FIA_P5X4", BIT(6)},
479 {"DISP_PGA", BIT(7)},
480
481 {"DBG_PSF", BIT(0)},
482 {"PSF0", BIT(1)},
483 {"P2SB16B", BIT(2)},
484 {"ACE0", BIT(3)},
485 {"ACE1", BIT(4)},
486 {"ACE2", BIT(5)},
487 {"ACE3", BIT(6)},
488 {"ACE4", BIT(7)},
489
490 {"ACE5", BIT(0)},
491 {"ACE6", BIT(1)},
492 {"ACE7", BIT(2)},
493 {"ACE8", BIT(3)},
494 {"ACE9", BIT(4)},
495 {"ACE10", BIT(5)},
496 {"FIACPCB", BIT(6)},
497 {"OSSE", BIT(7)},
498 {}
499};
500
501const struct pmc_bit_map *ext_lnl_pfear_map[] = {
502 lnl_pfear_map,
503 NULL
504};
505
506const struct pmc_reg_map lnl_socm_reg_map = {
507 .pfear_sts = ext_lnl_pfear_map,
508 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
509 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
510 .ltr_show_sts = lnl_ltr_show_map,
511 .msr_sts = msr_map,
512 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
513 .regmap_length = LNL_PMC_MMIO_REG_LEN,
514 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
515 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
516 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
517 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
518 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
519 .lpm_num_maps = ADL_LPM_NUM_MAPS,
520 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
521 .etr3_offset = ETR3_OFFSET,
522 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
523 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
524 .lpm_en_offset = MTL_LPM_EN_OFFSET,
525 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
526 .lpm_sts = lnl_lpm_maps,
527 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
528 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
529 .s0ix_blocker_maps = lnl_blk_maps,
530 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
531};
532
533#define LNL_NPU_PCI_DEV 0x643e
534#define LNL_IPU_PCI_DEV 0x645d
535
536/*
537 * Set power state of select devices that do not have drivers to D3
538 * so that they do not block Package C entry.
539 */
540static void lnl_d3_fixup(void)
541{
542 pmc_core_set_device_d3(LNL_IPU_PCI_DEV);
543 pmc_core_set_device_d3(LNL_NPU_PCI_DEV);
544}
545
546static int lnl_resume(struct pmc_dev *pmcdev)
547{
548 lnl_d3_fixup();
549
550 return cnl_resume(pmcdev);
551}
552
553int lnl_core_init(struct pmc_dev *pmcdev)
554{
555 int ret;
556 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];
557
558 lnl_d3_fixup();
559
560 pmcdev->suspend = cnl_suspend;
561 pmcdev->resume = lnl_resume;
562
563 pmc->map = &lnl_socm_reg_map;
564 ret = get_primary_reg_base(pmc);
565 if (ret)
566 return ret;
567
568 pmc_core_get_low_power_modes(pmcdev);
569
570 return 0;
571}