1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) Maxime Coquelin 2015
   4 * Copyright (C) STMicroelectronics 2017
   5 * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6 *
   7 * Heavily based on Mediatek's pinctrl driver
   8 */
   9#include <linux/clk.h>
  10#include <linux/gpio/driver.h>
  11#include <linux/hwspinlock.h>
  12#include <linux/io.h>
  13#include <linux/irq.h>
  14#include <linux/mfd/syscon.h>
  15#include <linux/module.h>
  16#include <linux/of.h>
  17#include <linux/of_address.h>
  18#include <linux/of_irq.h>
  19#include <linux/platform_device.h>
  20#include <linux/property.h>
  21#include <linux/regmap.h>
  22#include <linux/reset.h>
  23#include <linux/seq_file.h>
  24#include <linux/slab.h>
  25
  26#include <linux/pinctrl/consumer.h>
  27#include <linux/pinctrl/machine.h>
  28#include <linux/pinctrl/pinconf-generic.h>
  29#include <linux/pinctrl/pinconf.h>
  30#include <linux/pinctrl/pinctrl.h>
  31#include <linux/pinctrl/pinmux.h>
  32
  33#include "../core.h"
  34#include "../pinconf.h"
  35#include "../pinctrl-utils.h"
  36#include "pinctrl-stm32.h"
  37
  38#define STM32_GPIO_MODER	0x00
  39#define STM32_GPIO_TYPER	0x04
  40#define STM32_GPIO_SPEEDR	0x08
  41#define STM32_GPIO_PUPDR	0x0c
  42#define STM32_GPIO_IDR		0x10
  43#define STM32_GPIO_ODR		0x14
  44#define STM32_GPIO_BSRR		0x18
  45#define STM32_GPIO_LCKR		0x1c
  46#define STM32_GPIO_AFRL		0x20
  47#define STM32_GPIO_AFRH		0x24
  48#define STM32_GPIO_SECCFGR	0x30
  49
  50/* custom bitfield to backup pin status */
  51#define STM32_GPIO_BKP_MODE_SHIFT	0
  52#define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
  53#define STM32_GPIO_BKP_ALT_SHIFT	2
  54#define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
  55#define STM32_GPIO_BKP_SPEED_SHIFT	6
  56#define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
  57#define STM32_GPIO_BKP_PUPD_SHIFT	8
  58#define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
  59#define STM32_GPIO_BKP_TYPE		10
  60#define STM32_GPIO_BKP_VAL		11
  61
  62#define STM32_GPIO_PINS_PER_BANK 16
  63#define STM32_GPIO_IRQ_LINE	 16
  64
  65#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
  66
  67#define gpio_range_to_bank(chip) \
  68		container_of(chip, struct stm32_gpio_bank, range)
  69
  70#define HWSPNLCK_TIMEOUT	1000 /* usec */
  71
  72static const char * const stm32_gpio_functions[] = {
  73	"gpio", "af0", "af1",
  74	"af2", "af3", "af4",
  75	"af5", "af6", "af7",
  76	"af8", "af9", "af10",
  77	"af11", "af12", "af13",
  78	"af14", "af15", "analog",
  79};
  80
  81struct stm32_pinctrl_group {
  82	const char *name;
  83	unsigned long config;
  84	unsigned pin;
  85};
  86
  87struct stm32_gpio_bank {
  88	void __iomem *base;
  89	struct clk *clk;
  90	struct reset_control *rstc;
  91	spinlock_t lock;
  92	struct gpio_chip gpio_chip;
  93	struct pinctrl_gpio_range range;
  94	struct fwnode_handle *fwnode;
  95	struct irq_domain *domain;
  96	u32 bank_nr;
  97	u32 bank_ioport_nr;
  98	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
  99	u8 irq_type[STM32_GPIO_PINS_PER_BANK];
 100	bool secure_control;
 101};
 102
 103struct stm32_pinctrl {
 104	struct device *dev;
 105	struct pinctrl_dev *pctl_dev;
 106	struct pinctrl_desc pctl_desc;
 107	struct stm32_pinctrl_group *groups;
 108	unsigned ngroups;
 109	const char **grp_names;
 110	struct stm32_gpio_bank *banks;
 
 111	unsigned nbanks;
 112	const struct stm32_pinctrl_match_data *match_data;
 113	struct irq_domain	*domain;
 114	struct regmap		*regmap;
 115	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
 116	struct hwspinlock *hwlock;
 117	struct stm32_desc_pin *pins;
 118	u32 npins;
 119	u32 pkg;
 120	u16 irqmux_map;
 121	spinlock_t irqmux_lock;
 122};
 123
 124static inline int stm32_gpio_pin(int gpio)
 125{
 126	return gpio % STM32_GPIO_PINS_PER_BANK;
 127}
 128
 129static inline u32 stm32_gpio_get_mode(u32 function)
 130{
 131	switch (function) {
 132	case STM32_PIN_GPIO:
 133		return 0;
 134	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
 135		return 2;
 136	case STM32_PIN_ANALOG:
 137		return 3;
 138	}
 139
 140	return 0;
 141}
 142
 143static inline u32 stm32_gpio_get_alt(u32 function)
 144{
 145	switch (function) {
 146	case STM32_PIN_GPIO:
 147		return 0;
 148	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
 149		return function - 1;
 150	case STM32_PIN_ANALOG:
 151		return 0;
 152	}
 153
 154	return 0;
 155}
 156
 157static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
 158				    u32 offset, u32 value)
 159{
 160	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
 161	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
 162}
 163
 164static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
 165				   u32 mode, u32 alt)
 166{
 167	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
 168				      STM32_GPIO_BKP_ALT_MASK);
 169	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
 170	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
 171}
 172
 173static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
 174				      u32 drive)
 175{
 176	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
 177	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
 178}
 179
 180static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
 181				    u32 speed)
 182{
 183	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
 184	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
 185}
 186
 187static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
 188				   u32 bias)
 189{
 190	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
 191	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
 192}
 193
 194/* GPIO functions */
 195
 196static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
 197	unsigned offset, int value)
 198{
 199	stm32_gpio_backup_value(bank, offset, value);
 200
 201	if (!value)
 202		offset += STM32_GPIO_PINS_PER_BANK;
 203
 204	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
 205}
 206
 207static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
 208{
 209	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 210	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 211	struct pinctrl_gpio_range *range;
 212	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
 213
 214	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
 215	if (!range) {
 216		dev_err(pctl->dev, "pin %d not in range.\n", pin);
 217		return -EINVAL;
 218	}
 219
 220	return pinctrl_gpio_request(chip, offset);
 221}
 222
 223static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
 224{
 225	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 226
 227	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
 228}
 229
 230static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 231{
 232	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 233
 234	__stm32_gpio_set(bank, offset, value);
 235}
 236
 237static int stm32_gpio_direction_output(struct gpio_chip *chip,
 238	unsigned offset, int value)
 239{
 240	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 241
 242	__stm32_gpio_set(bank, offset, value);
 243
 244	return pinctrl_gpio_direction_output(chip, offset);
 245}
 246
 247
 248static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
 249{
 250	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 251	struct irq_fwspec fwspec;
 252
 253	fwspec.fwnode = bank->fwnode;
 254	fwspec.param_count = 2;
 255	fwspec.param[0] = offset;
 256	fwspec.param[1] = IRQ_TYPE_NONE;
 257
 258	return irq_create_fwspec_mapping(&fwspec);
 259}
 260
 261static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 262{
 263	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 264	int pin = stm32_gpio_pin(offset);
 265	int ret;
 266	u32 mode, alt;
 267
 268	stm32_pmx_get_mode(bank, pin, &mode, &alt);
 269	if ((alt == 0) && (mode == 0))
 270		ret = GPIO_LINE_DIRECTION_IN;
 271	else if ((alt == 0) && (mode == 1))
 272		ret = GPIO_LINE_DIRECTION_OUT;
 273	else
 274		ret = -EINVAL;
 275
 276	return ret;
 277}
 278
 279static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
 280				      unsigned long *valid_mask,
 281				      unsigned int ngpios)
 282{
 283	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 284	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 285	unsigned int i;
 286	u32 sec;
 287
 288	/* All gpio are valid per default */
 289	bitmap_fill(valid_mask, ngpios);
 290
 291	if (bank->secure_control) {
 292		/* Tag secured pins as invalid */
 293		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
 294
 295		for (i = 0; i < ngpios; i++) {
 296			if (sec & BIT(i)) {
 297				clear_bit(i, valid_mask);
 298				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
 299			}
 300		}
 301	}
 302
 303	return 0;
 304}
 305
 306static const struct gpio_chip stm32_gpio_template = {
 307	.request		= stm32_gpio_request,
 308	.free			= pinctrl_gpio_free,
 309	.get			= stm32_gpio_get,
 310	.set			= stm32_gpio_set,
 311	.direction_input	= pinctrl_gpio_direction_input,
 312	.direction_output	= stm32_gpio_direction_output,
 313	.to_irq			= stm32_gpio_to_irq,
 314	.get_direction		= stm32_gpio_get_direction,
 315	.set_config		= gpiochip_generic_config,
 316	.init_valid_mask	= stm32_gpio_init_valid_mask,
 317};
 318
 319static void stm32_gpio_irq_trigger(struct irq_data *d)
 320{
 321	struct stm32_gpio_bank *bank = d->domain->host_data;
 322	int level;
 323
 324	/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
 325	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
 326		return;
 327
 328	/* If level interrupt type then retrig */
 329	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
 330	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
 331	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
 332		irq_chip_retrigger_hierarchy(d);
 333}
 334
 335static void stm32_gpio_irq_eoi(struct irq_data *d)
 336{
 337	irq_chip_eoi_parent(d);
 338	stm32_gpio_irq_trigger(d);
 339};
 340
 341static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
 342{
 343	struct stm32_gpio_bank *bank = d->domain->host_data;
 344	u32 parent_type;
 345
 346	switch (type) {
 347	case IRQ_TYPE_EDGE_RISING:
 348	case IRQ_TYPE_EDGE_FALLING:
 349	case IRQ_TYPE_EDGE_BOTH:
 350		parent_type = type;
 351		break;
 352	case IRQ_TYPE_LEVEL_HIGH:
 353		parent_type = IRQ_TYPE_EDGE_RISING;
 354		break;
 355	case IRQ_TYPE_LEVEL_LOW:
 356		parent_type = IRQ_TYPE_EDGE_FALLING;
 357		break;
 358	default:
 359		return -EINVAL;
 360	}
 361
 362	bank->irq_type[d->hwirq] = type;
 363
 364	return irq_chip_set_type_parent(d, parent_type);
 365};
 366
 367static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
 368{
 369	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
 370	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 371	int ret;
 372
 373	ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
 374	if (ret)
 375		return ret;
 376
 377	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
 378	if (ret) {
 379		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 380			irq_data->hwirq);
 381		return ret;
 382	}
 383
 384	return 0;
 385}
 386
 387static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
 388{
 389	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
 390
 391	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
 392}
 393
 394static void stm32_gpio_irq_unmask(struct irq_data *d)
 395{
 396	irq_chip_unmask_parent(d);
 397	stm32_gpio_irq_trigger(d);
 398}
 399
 400static struct irq_chip stm32_gpio_irq_chip = {
 401	.name		= "stm32gpio",
 402	.irq_eoi	= stm32_gpio_irq_eoi,
 403	.irq_ack	= irq_chip_ack_parent,
 404	.irq_mask	= irq_chip_mask_parent,
 405	.irq_unmask	= stm32_gpio_irq_unmask,
 406	.irq_set_type	= stm32_gpio_set_type,
 407	.irq_set_wake	= irq_chip_set_wake_parent,
 408	.irq_request_resources = stm32_gpio_irq_request_resources,
 409	.irq_release_resources = stm32_gpio_irq_release_resources,
 410};
 411
 412static int stm32_gpio_domain_translate(struct irq_domain *d,
 413				       struct irq_fwspec *fwspec,
 414				       unsigned long *hwirq,
 415				       unsigned int *type)
 416{
 417	if ((fwspec->param_count != 2) ||
 418	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
 419		return -EINVAL;
 420
 421	*hwirq = fwspec->param[0];
 422	*type = fwspec->param[1];
 423	return 0;
 424}
 425
 426static int stm32_gpio_domain_activate(struct irq_domain *d,
 427				      struct irq_data *irq_data, bool reserve)
 428{
 429	struct stm32_gpio_bank *bank = d->host_data;
 430	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 431	int ret = 0;
 432
 433	if (pctl->hwlock) {
 434		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
 435						    HWSPNLCK_TIMEOUT);
 436		if (ret) {
 437			dev_err(pctl->dev, "Can't get hwspinlock\n");
 438			return ret;
 439		}
 440	}
 441
 442	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
 443
 444	if (pctl->hwlock)
 445		hwspin_unlock_in_atomic(pctl->hwlock);
 446
 447	return ret;
 448}
 449
 450static int stm32_gpio_domain_alloc(struct irq_domain *d,
 451				   unsigned int virq,
 452				   unsigned int nr_irqs, void *data)
 453{
 454	struct stm32_gpio_bank *bank = d->host_data;
 455	struct irq_fwspec *fwspec = data;
 456	struct irq_fwspec parent_fwspec;
 457	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 458	irq_hw_number_t hwirq = fwspec->param[0];
 459	unsigned long flags;
 460	int ret = 0;
 461
 462	/*
 463	 * Check first that the IRQ MUX of that line is free.
 464	 * gpio irq mux is shared between several banks, protect with a lock
 465	 */
 466	spin_lock_irqsave(&pctl->irqmux_lock, flags);
 467
 468	if (pctl->irqmux_map & BIT(hwirq)) {
 469		dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
 470		ret = -EBUSY;
 471	} else {
 472		pctl->irqmux_map |= BIT(hwirq);
 473	}
 474
 475	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
 476	if (ret)
 477		return ret;
 478
 479	parent_fwspec.fwnode = d->parent->fwnode;
 480	parent_fwspec.param_count = 2;
 481	parent_fwspec.param[0] = fwspec->param[0];
 482	parent_fwspec.param[1] = fwspec->param[1];
 483
 484	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
 485				      bank);
 486
 487	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
 488}
 489
 490static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
 491				   unsigned int nr_irqs)
 492{
 493	struct stm32_gpio_bank *bank = d->host_data;
 494	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 495	struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
 496	unsigned long flags, hwirq = irq_data->hwirq;
 497
 498	irq_domain_free_irqs_common(d, virq, nr_irqs);
 499
 500	spin_lock_irqsave(&pctl->irqmux_lock, flags);
 501	pctl->irqmux_map &= ~BIT(hwirq);
 502	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
 503}
 504
 505static const struct irq_domain_ops stm32_gpio_domain_ops = {
 506	.translate	= stm32_gpio_domain_translate,
 507	.alloc		= stm32_gpio_domain_alloc,
 508	.free		= stm32_gpio_domain_free,
 509	.activate	= stm32_gpio_domain_activate,
 510};
 511
 512/* Pinctrl functions */
 513static struct stm32_pinctrl_group *
 514stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
 515{
 516	int i;
 517
 518	for (i = 0; i < pctl->ngroups; i++) {
 519		struct stm32_pinctrl_group *grp = pctl->groups + i;
 520
 521		if (grp->pin == pin)
 522			return grp;
 523	}
 524
 525	return NULL;
 526}
 527
 528static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
 529		u32 pin_num, u32 fnum)
 530{
 531	int i, k;
 532
 533	for (i = 0; i < pctl->npins; i++) {
 534		const struct stm32_desc_pin *pin = pctl->pins + i;
 535		const struct stm32_desc_function *func = pin->functions;
 536
 537		if (pin->pin.number != pin_num)
 538			continue;
 539
 540		for (k = 0; k < STM32_CONFIG_NUM; k++) {
 541			if (func->num == fnum)
 542				return true;
 543			func++;
 544		}
 545
 546		break;
 547	}
 548
 549	dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
 550
 551	return false;
 552}
 553
 554static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
 555		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
 556		struct pinctrl_map **map, unsigned *reserved_maps,
 557		unsigned *num_maps)
 558{
 559	if (*num_maps == *reserved_maps)
 560		return -ENOSPC;
 561
 562	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
 563	(*map)[*num_maps].data.mux.group = grp->name;
 564
 565	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
 566		return -EINVAL;
 567
 568	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
 569	(*num_maps)++;
 570
 571	return 0;
 572}
 573
 574static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 575				      struct device_node *node,
 576				      struct pinctrl_map **map,
 577				      unsigned *reserved_maps,
 578				      unsigned *num_maps)
 579{
 580	struct stm32_pinctrl *pctl;
 581	struct stm32_pinctrl_group *grp;
 582	struct property *pins;
 583	u32 pinfunc, pin, func;
 584	unsigned long *configs;
 585	unsigned int num_configs;
 586	bool has_config = 0;
 587	unsigned reserve = 0;
 588	int num_pins, num_funcs, maps_per_pin, i, err = 0;
 589
 590	pctl = pinctrl_dev_get_drvdata(pctldev);
 591
 592	pins = of_find_property(node, "pinmux", NULL);
 593	if (!pins) {
 594		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
 595				node);
 596		return -EINVAL;
 597	}
 598
 599	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
 600		&num_configs);
 601	if (err)
 602		return err;
 603
 604	if (num_configs)
 605		has_config = 1;
 606
 607	num_pins = pins->length / sizeof(u32);
 608	num_funcs = num_pins;
 609	maps_per_pin = 0;
 610	if (num_funcs)
 611		maps_per_pin++;
 612	if (has_config && num_pins >= 1)
 613		maps_per_pin++;
 614
 615	if (!num_pins || !maps_per_pin) {
 616		err = -EINVAL;
 617		goto exit;
 618	}
 619
 620	reserve = num_pins * maps_per_pin;
 621
 622	err = pinctrl_utils_reserve_map(pctldev, map,
 623			reserved_maps, num_maps, reserve);
 624	if (err)
 625		goto exit;
 626
 627	for (i = 0; i < num_pins; i++) {
 628		err = of_property_read_u32_index(node, "pinmux",
 629				i, &pinfunc);
 630		if (err)
 631			goto exit;
 632
 633		pin = STM32_GET_PIN_NO(pinfunc);
 634		func = STM32_GET_PIN_FUNC(pinfunc);
 635
 636		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
 637			err = -EINVAL;
 638			goto exit;
 639		}
 640
 641		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
 642		if (!grp) {
 643			dev_err(pctl->dev, "unable to match pin %d to group\n",
 644					pin);
 645			err = -EINVAL;
 646			goto exit;
 647		}
 648
 649		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
 650				reserved_maps, num_maps);
 651		if (err)
 652			goto exit;
 653
 654		if (has_config) {
 655			err = pinctrl_utils_add_map_configs(pctldev, map,
 656					reserved_maps, num_maps, grp->name,
 657					configs, num_configs,
 658					PIN_MAP_TYPE_CONFIGS_GROUP);
 659			if (err)
 660				goto exit;
 661		}
 662	}
 663
 664exit:
 665	kfree(configs);
 666	return err;
 667}
 668
 669static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 670				 struct device_node *np_config,
 671				 struct pinctrl_map **map, unsigned *num_maps)
 672{
 673	struct device_node *np;
 674	unsigned reserved_maps;
 675	int ret;
 676
 677	*map = NULL;
 678	*num_maps = 0;
 679	reserved_maps = 0;
 680
 681	for_each_child_of_node(np_config, np) {
 682		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
 683				&reserved_maps, num_maps);
 684		if (ret < 0) {
 685			pinctrl_utils_free_map(pctldev, *map, *num_maps);
 686			of_node_put(np);
 687			return ret;
 688		}
 689	}
 690
 691	return 0;
 692}
 693
 694static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 695{
 696	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 697
 698	return pctl->ngroups;
 699}
 700
 701static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 702					      unsigned group)
 703{
 704	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 705
 706	return pctl->groups[group].name;
 707}
 708
 709static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 710				      unsigned group,
 711				      const unsigned **pins,
 712				      unsigned *num_pins)
 713{
 714	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 715
 716	*pins = (unsigned *)&pctl->groups[group].pin;
 717	*num_pins = 1;
 718
 719	return 0;
 720}
 721
 722static const struct pinctrl_ops stm32_pctrl_ops = {
 723	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
 724	.dt_free_map		= pinctrl_utils_free_map,
 725	.get_groups_count	= stm32_pctrl_get_groups_count,
 726	.get_group_name		= stm32_pctrl_get_group_name,
 727	.get_group_pins		= stm32_pctrl_get_group_pins,
 728};
 729
 730
 731/* Pinmux functions */
 732
 733static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 734{
 735	return ARRAY_SIZE(stm32_gpio_functions);
 736}
 737
 738static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
 739					   unsigned selector)
 740{
 741	return stm32_gpio_functions[selector];
 742}
 743
 744static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 745				     unsigned function,
 746				     const char * const **groups,
 747				     unsigned * const num_groups)
 748{
 749	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 750
 751	*groups = pctl->grp_names;
 752	*num_groups = pctl->ngroups;
 753
 754	return 0;
 755}
 756
 757static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
 758			      int pin, u32 mode, u32 alt)
 759{
 760	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 761	u32 val;
 762	int alt_shift = (pin % 8) * 4;
 763	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
 764	unsigned long flags;
 765	int err = 0;
 766
 767	spin_lock_irqsave(&bank->lock, flags);
 768
 769	if (pctl->hwlock) {
 770		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
 771						    HWSPNLCK_TIMEOUT);
 772		if (err) {
 773			dev_err(pctl->dev, "Can't get hwspinlock\n");
 774			goto unlock;
 775		}
 776	}
 777
 778	val = readl_relaxed(bank->base + alt_offset);
 779	val &= ~GENMASK(alt_shift + 3, alt_shift);
 780	val |= (alt << alt_shift);
 781	writel_relaxed(val, bank->base + alt_offset);
 782
 783	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
 784	val &= ~GENMASK(pin * 2 + 1, pin * 2);
 785	val |= mode << (pin * 2);
 786	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
 787
 788	if (pctl->hwlock)
 789		hwspin_unlock_in_atomic(pctl->hwlock);
 790
 791	stm32_gpio_backup_mode(bank, pin, mode, alt);
 792
 793unlock:
 794	spin_unlock_irqrestore(&bank->lock, flags);
 795
 796	return err;
 797}
 798
 799void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
 800			u32 *alt)
 801{
 802	u32 val;
 803	int alt_shift = (pin % 8) * 4;
 804	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
 805	unsigned long flags;
 806
 807	spin_lock_irqsave(&bank->lock, flags);
 808
 809	val = readl_relaxed(bank->base + alt_offset);
 810	val &= GENMASK(alt_shift + 3, alt_shift);
 811	*alt = val >> alt_shift;
 812
 813	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
 814	val &= GENMASK(pin * 2 + 1, pin * 2);
 815	*mode = val >> (pin * 2);
 816
 817	spin_unlock_irqrestore(&bank->lock, flags);
 818}
 819
 820static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
 821			    unsigned function,
 822			    unsigned group)
 823{
 824	bool ret;
 825	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 826	struct stm32_pinctrl_group *g = pctl->groups + group;
 827	struct pinctrl_gpio_range *range;
 828	struct stm32_gpio_bank *bank;
 829	u32 mode, alt;
 830	int pin;
 831
 832	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
 833	if (!ret)
 834		return -EINVAL;
 835
 836	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
 837	if (!range) {
 838		dev_err(pctl->dev, "No gpio range defined.\n");
 839		return -EINVAL;
 840	}
 841
 842	bank = gpiochip_get_data(range->gc);
 843	pin = stm32_gpio_pin(g->pin);
 844
 845	mode = stm32_gpio_get_mode(function);
 846	alt = stm32_gpio_get_alt(function);
 847
 848	return stm32_pmx_set_mode(bank, pin, mode, alt);
 849}
 850
 851static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 852			struct pinctrl_gpio_range *range, unsigned gpio,
 853			bool input)
 854{
 855	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
 856	int pin = stm32_gpio_pin(gpio);
 857
 858	return stm32_pmx_set_mode(bank, pin, !input, 0);
 859}
 860
 861static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
 862{
 863	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 864	struct pinctrl_gpio_range *range;
 865
 866	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
 867	if (!range) {
 868		dev_err(pctl->dev, "No gpio range defined.\n");
 869		return -EINVAL;
 870	}
 871
 872	if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
 873		dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
 874		return -EACCES;
 875	}
 876
 877	return 0;
 878}
 879
 880static const struct pinmux_ops stm32_pmx_ops = {
 881	.get_functions_count	= stm32_pmx_get_funcs_cnt,
 882	.get_function_name	= stm32_pmx_get_func_name,
 883	.get_function_groups	= stm32_pmx_get_func_groups,
 884	.set_mux		= stm32_pmx_set_mux,
 885	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
 886	.request		= stm32_pmx_request,
 887	.strict			= true,
 888};
 889
 890/* Pinconf functions */
 891
 892static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
 893				   unsigned offset, u32 drive)
 894{
 895	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 896	unsigned long flags;
 897	u32 val;
 898	int err = 0;
 899
 900	spin_lock_irqsave(&bank->lock, flags);
 901
 902	if (pctl->hwlock) {
 903		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
 904						    HWSPNLCK_TIMEOUT);
 905		if (err) {
 906			dev_err(pctl->dev, "Can't get hwspinlock\n");
 907			goto unlock;
 908		}
 909	}
 910
 911	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
 912	val &= ~BIT(offset);
 913	val |= drive << offset;
 914	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
 915
 916	if (pctl->hwlock)
 917		hwspin_unlock_in_atomic(pctl->hwlock);
 918
 919	stm32_gpio_backup_driving(bank, offset, drive);
 920
 921unlock:
 922	spin_unlock_irqrestore(&bank->lock, flags);
 923
 924	return err;
 925}
 926
 927static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
 928	unsigned int offset)
 929{
 930	unsigned long flags;
 931	u32 val;
 932
 933	spin_lock_irqsave(&bank->lock, flags);
 934
 935	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
 936	val &= BIT(offset);
 937
 938	spin_unlock_irqrestore(&bank->lock, flags);
 939
 940	return (val >> offset);
 941}
 942
 943static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
 944				 unsigned offset, u32 speed)
 945{
 946	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 947	unsigned long flags;
 948	u32 val;
 949	int err = 0;
 950
 951	spin_lock_irqsave(&bank->lock, flags);
 952
 953	if (pctl->hwlock) {
 954		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
 955						    HWSPNLCK_TIMEOUT);
 956		if (err) {
 957			dev_err(pctl->dev, "Can't get hwspinlock\n");
 958			goto unlock;
 959		}
 960	}
 961
 962	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
 963	val &= ~GENMASK(offset * 2 + 1, offset * 2);
 964	val |= speed << (offset * 2);
 965	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
 966
 967	if (pctl->hwlock)
 968		hwspin_unlock_in_atomic(pctl->hwlock);
 969
 970	stm32_gpio_backup_speed(bank, offset, speed);
 971
 972unlock:
 973	spin_unlock_irqrestore(&bank->lock, flags);
 974
 975	return err;
 976}
 977
 978static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
 979	unsigned int offset)
 980{
 981	unsigned long flags;
 982	u32 val;
 983
 984	spin_lock_irqsave(&bank->lock, flags);
 985
 986	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
 987	val &= GENMASK(offset * 2 + 1, offset * 2);
 988
 989	spin_unlock_irqrestore(&bank->lock, flags);
 990
 991	return (val >> (offset * 2));
 992}
 993
 994static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
 995				unsigned offset, u32 bias)
 996{
 997	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 998	unsigned long flags;
 999	u32 val;
1000	int err = 0;
1001
1002	spin_lock_irqsave(&bank->lock, flags);
1003
1004	if (pctl->hwlock) {
1005		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1006						    HWSPNLCK_TIMEOUT);
1007		if (err) {
1008			dev_err(pctl->dev, "Can't get hwspinlock\n");
1009			goto unlock;
1010		}
1011	}
1012
1013	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1014	val &= ~GENMASK(offset * 2 + 1, offset * 2);
1015	val |= bias << (offset * 2);
1016	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1017
1018	if (pctl->hwlock)
1019		hwspin_unlock_in_atomic(pctl->hwlock);
1020
1021	stm32_gpio_backup_bias(bank, offset, bias);
1022
1023unlock:
1024	spin_unlock_irqrestore(&bank->lock, flags);
1025
1026	return err;
1027}
1028
1029static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1030	unsigned int offset)
1031{
1032	unsigned long flags;
1033	u32 val;
1034
1035	spin_lock_irqsave(&bank->lock, flags);
1036
1037	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1038	val &= GENMASK(offset * 2 + 1, offset * 2);
1039
1040	spin_unlock_irqrestore(&bank->lock, flags);
1041
1042	return (val >> (offset * 2));
1043}
1044
1045static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1046	unsigned int offset, bool dir)
1047{
1048	unsigned long flags;
1049	u32 val;
1050
1051	spin_lock_irqsave(&bank->lock, flags);
1052
1053	if (dir)
1054		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1055			 BIT(offset));
1056	else
1057		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1058			 BIT(offset));
1059
1060	spin_unlock_irqrestore(&bank->lock, flags);
1061
1062	return val;
1063}
1064
1065static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1066		unsigned int pin, enum pin_config_param param,
1067		enum pin_config_param arg)
1068{
1069	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1070	struct pinctrl_gpio_range *range;
1071	struct stm32_gpio_bank *bank;
1072	int offset, ret = 0;
1073
1074	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1075	if (!range) {
1076		dev_err(pctl->dev, "No gpio range defined.\n");
1077		return -EINVAL;
1078	}
1079
1080	bank = gpiochip_get_data(range->gc);
1081	offset = stm32_gpio_pin(pin);
1082
1083	if (!gpiochip_line_is_valid(range->gc, offset)) {
1084		dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1085		return -EACCES;
1086	}
1087
1088	switch (param) {
1089	case PIN_CONFIG_DRIVE_PUSH_PULL:
1090		ret = stm32_pconf_set_driving(bank, offset, 0);
1091		break;
1092	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1093		ret = stm32_pconf_set_driving(bank, offset, 1);
1094		break;
1095	case PIN_CONFIG_SLEW_RATE:
1096		ret = stm32_pconf_set_speed(bank, offset, arg);
1097		break;
1098	case PIN_CONFIG_BIAS_DISABLE:
1099		ret = stm32_pconf_set_bias(bank, offset, 0);
1100		break;
1101	case PIN_CONFIG_BIAS_PULL_UP:
1102		ret = stm32_pconf_set_bias(bank, offset, 1);
1103		break;
1104	case PIN_CONFIG_BIAS_PULL_DOWN:
1105		ret = stm32_pconf_set_bias(bank, offset, 2);
1106		break;
1107	case PIN_CONFIG_OUTPUT:
1108		__stm32_gpio_set(bank, offset, arg);
1109		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1110		break;
1111	default:
1112		ret = -ENOTSUPP;
1113	}
1114
1115	return ret;
1116}
1117
1118static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1119				 unsigned group,
1120				 unsigned long *config)
1121{
1122	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1123
1124	*config = pctl->groups[group].config;
1125
1126	return 0;
1127}
1128
1129static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1130				 unsigned long *configs, unsigned num_configs)
1131{
1132	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1133	struct stm32_pinctrl_group *g = &pctl->groups[group];
1134	int i, ret;
1135
1136	for (i = 0; i < num_configs; i++) {
1137		mutex_lock(&pctldev->mutex);
1138		ret = stm32_pconf_parse_conf(pctldev, g->pin,
1139			pinconf_to_config_param(configs[i]),
1140			pinconf_to_config_argument(configs[i]));
1141		mutex_unlock(&pctldev->mutex);
1142		if (ret < 0)
1143			return ret;
1144
1145		g->config = configs[i];
1146	}
1147
1148	return 0;
1149}
1150
1151static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1152			   unsigned long *configs, unsigned int num_configs)
1153{
1154	int i, ret;
1155
1156	for (i = 0; i < num_configs; i++) {
1157		ret = stm32_pconf_parse_conf(pctldev, pin,
1158				pinconf_to_config_param(configs[i]),
1159				pinconf_to_config_argument(configs[i]));
1160		if (ret < 0)
1161			return ret;
1162	}
1163
1164	return 0;
1165}
1166
1167static struct stm32_desc_pin *
1168stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1169				       unsigned int pin_number)
1170{
1171	struct stm32_desc_pin *pins = pctl->pins;
1172	int i;
1173
1174	for (i = 0; i < pctl->npins; i++) {
1175		if (pins->pin.number == pin_number)
1176			return pins;
1177		pins++;
1178	}
1179	return NULL;
1180}
1181
1182static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1183				 struct seq_file *s,
1184				 unsigned int pin)
1185{
1186	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1187	const struct stm32_desc_pin *pin_desc;
1188	struct pinctrl_gpio_range *range;
1189	struct stm32_gpio_bank *bank;
1190	int offset;
1191	u32 mode, alt, drive, speed, bias;
1192	static const char * const modes[] = {
1193			"input", "output", "alternate", "analog" };
1194	static const char * const speeds[] = {
1195			"low", "medium", "high", "very high" };
1196	static const char * const biasing[] = {
1197			"floating", "pull up", "pull down", "" };
1198	bool val;
1199
1200	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1201	if (!range)
1202		return;
1203
1204	bank = gpiochip_get_data(range->gc);
1205	offset = stm32_gpio_pin(pin);
1206
1207	if (!gpiochip_line_is_valid(range->gc, offset)) {
1208		seq_puts(s, "NO ACCESS");
1209		return;
1210	}
1211
1212	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1213	bias = stm32_pconf_get_bias(bank, offset);
1214
1215	seq_printf(s, "%s ", modes[mode]);
1216
1217	switch (mode) {
1218	/* input */
1219	case 0:
1220		val = stm32_pconf_get(bank, offset, true);
1221		seq_printf(s, "- %s - %s",
1222			   val ? "high" : "low",
1223			   biasing[bias]);
1224		break;
1225
1226	/* output */
1227	case 1:
1228		drive = stm32_pconf_get_driving(bank, offset);
1229		speed = stm32_pconf_get_speed(bank, offset);
1230		val = stm32_pconf_get(bank, offset, false);
1231		seq_printf(s, "- %s - %s - %s - %s %s",
1232			   val ? "high" : "low",
1233			   drive ? "open drain" : "push pull",
1234			   biasing[bias],
1235			   speeds[speed], "speed");
1236		break;
1237
1238	/* alternate */
1239	case 2:
1240		drive = stm32_pconf_get_driving(bank, offset);
1241		speed = stm32_pconf_get_speed(bank, offset);
1242		pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1243		if (!pin_desc)
1244			return;
1245
1246		seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1247			   pin_desc->functions[alt + 1].name,
1248			   drive ? "open drain" : "push pull",
1249			   biasing[bias],
1250			   speeds[speed], "speed");
1251		break;
1252
1253	/* analog */
1254	case 3:
1255		break;
1256	}
1257}
1258
1259static const struct pinconf_ops stm32_pconf_ops = {
1260	.pin_config_group_get	= stm32_pconf_group_get,
1261	.pin_config_group_set	= stm32_pconf_group_set,
1262	.pin_config_set		= stm32_pconf_set,
1263	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1264};
1265
1266static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
1267								 struct stm32_gpio_bank *bank,
1268								 unsigned int offset)
1269{
1270	unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
1271	struct stm32_desc_pin *pin_desc;
1272	int i;
1273
1274	/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
1275	if (stm32_pin_nb < pctl->npins) {
1276		pin_desc = pctl->pins + stm32_pin_nb;
1277		if (pin_desc->pin.number == stm32_pin_nb)
1278			return pin_desc;
1279	}
1280
1281	/* Otherwise, loop all array to find the pin with the right number */
1282	for (i = 0; i < pctl->npins; i++) {
1283		pin_desc = pctl->pins + i;
1284		if (pin_desc->pin.number == stm32_pin_nb)
1285			return pin_desc;
1286	}
1287	return NULL;
1288}
1289
1290static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1291{
1292	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1293	int bank_ioport_nr;
1294	struct pinctrl_gpio_range *range = &bank->range;
1295	struct fwnode_reference_args args;
1296	struct device *dev = pctl->dev;
1297	struct resource res;
1298	int npins = STM32_GPIO_PINS_PER_BANK;
1299	int bank_nr, err, i = 0;
1300	struct stm32_desc_pin *stm32_pin;
1301	char **names;
1302
1303	if (!IS_ERR(bank->rstc))
1304		reset_control_deassert(bank->rstc);
1305
1306	if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1307		return -ENODEV;
1308
1309	bank->base = devm_ioremap_resource(dev, &res);
1310	if (IS_ERR(bank->base))
1311		return PTR_ERR(bank->base);
1312
1313	err = clk_prepare_enable(bank->clk);
1314	if (err) {
1315		dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
1316		return err;
1317	}
1318
1319	bank->gpio_chip = stm32_gpio_template;
1320
1321	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1322
1323	if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1324		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1325		bank->gpio_chip.base = args.args[1];
1326
1327		/* get the last defined gpio line (offset + nb of pins) */
1328		npins = args.args[0] + args.args[2];
1329		while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1330			npins = max(npins, (int)(args.args[0] + args.args[2]));
1331	} else {
1332		bank_nr = pctl->nbanks;
1333		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1334		range->name = bank->gpio_chip.label;
1335		range->id = bank_nr;
1336		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1337		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1338		range->npins = npins;
1339		range->gc = &bank->gpio_chip;
1340		pinctrl_add_gpio_range(pctl->pctl_dev,
1341				       &pctl->banks[bank_nr].range);
1342	}
1343
1344	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1345		bank_ioport_nr = bank_nr;
1346
1347	bank->gpio_chip.base = -1;
1348
1349	bank->gpio_chip.ngpio = npins;
1350	bank->gpio_chip.fwnode = fwnode;
1351	bank->gpio_chip.parent = dev;
1352	bank->bank_nr = bank_nr;
1353	bank->bank_ioport_nr = bank_ioport_nr;
1354	bank->secure_control = pctl->match_data->secure_control;
1355	spin_lock_init(&bank->lock);
1356
1357	if (pctl->domain) {
1358		/* create irq hierarchical domain */
1359		bank->fwnode = fwnode;
1360
1361		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1362							   bank->fwnode, &stm32_gpio_domain_ops,
1363							   bank);
1364
1365		if (!bank->domain) {
1366			err = -ENODEV;
1367			goto err_clk;
1368		}
1369	}
1370
1371	names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
1372	if (!names) {
1373		err = -ENOMEM;
1374		goto err_clk;
1375	}
1376
1377	for (i = 0; i < npins; i++) {
1378		stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1379		if (stm32_pin && stm32_pin->pin.name)
1380			names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
1381		else
 
 
1382			names[i] = NULL;
 
1383	}
1384
1385	bank->gpio_chip.names = (const char * const *)names;
1386
1387	err = gpiochip_add_data(&bank->gpio_chip, bank);
1388	if (err) {
1389		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1390		goto err_clk;
1391	}
1392
1393	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1394	return 0;
1395
1396err_clk:
1397	clk_disable_unprepare(bank->clk);
1398	return err;
1399}
1400
1401static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1402{
1403	struct device_node *np = pdev->dev.of_node;
1404	struct device_node *parent;
1405	struct irq_domain *domain;
1406
1407	if (!of_property_present(np, "interrupt-parent"))
1408		return NULL;
1409
1410	parent = of_irq_find_parent(np);
1411	if (!parent)
1412		return ERR_PTR(-ENXIO);
1413
1414	domain = irq_find_host(parent);
1415	of_node_put(parent);
1416	if (!domain)
1417		/* domain not registered yet */
1418		return ERR_PTR(-EPROBE_DEFER);
1419
1420	return domain;
1421}
1422
1423static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1424			   struct stm32_pinctrl *pctl)
1425{
1426	struct device_node *np = pdev->dev.of_node;
1427	struct device *dev = &pdev->dev;
1428	struct regmap *rm;
1429	int offset, ret, i;
1430	int mask, mask_width;
1431
1432	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1433	if (IS_ERR(pctl->regmap))
1434		return PTR_ERR(pctl->regmap);
1435
1436	rm = pctl->regmap;
1437
1438	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1439	if (ret)
1440		return ret;
1441
1442	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1443	if (ret)
1444		mask = SYSCFG_IRQMUX_MASK;
1445
1446	mask_width = fls(mask);
1447
1448	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1449		struct reg_field mux;
1450
1451		mux.reg = offset + (i / 4) * 4;
1452		mux.lsb = (i % 4) * mask_width;
1453		mux.msb = mux.lsb + mask_width - 1;
1454
1455		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1456			i, mux.reg, mux.lsb, mux.msb);
1457
1458		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1459		if (IS_ERR(pctl->irqmux[i]))
1460			return PTR_ERR(pctl->irqmux[i]);
1461	}
1462
1463	return 0;
1464}
1465
1466static int stm32_pctrl_build_state(struct platform_device *pdev)
1467{
1468	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1469	int i;
1470
1471	pctl->ngroups = pctl->npins;
1472
1473	/* Allocate groups */
1474	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1475				    sizeof(*pctl->groups), GFP_KERNEL);
1476	if (!pctl->groups)
1477		return -ENOMEM;
1478
1479	/* We assume that one pin is one group, use pin name as group name. */
1480	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1481				       sizeof(*pctl->grp_names), GFP_KERNEL);
1482	if (!pctl->grp_names)
1483		return -ENOMEM;
1484
1485	for (i = 0; i < pctl->npins; i++) {
1486		const struct stm32_desc_pin *pin = pctl->pins + i;
1487		struct stm32_pinctrl_group *group = pctl->groups + i;
1488
1489		group->name = pin->pin.name;
1490		group->pin = pin->pin.number;
1491		pctl->grp_names[i] = pin->pin.name;
1492	}
1493
1494	return 0;
1495}
1496
1497static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1498				       struct stm32_desc_pin *pins)
1499{
1500	const struct stm32_desc_pin *p;
1501	int i, nb_pins_available = 0;
1502
1503	for (i = 0; i < pctl->match_data->npins; i++) {
1504		p = pctl->match_data->pins + i;
1505		if (pctl->pkg && !(pctl->pkg & p->pkg))
1506			continue;
1507		pins->pin = p->pin;
1508		memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1509		       STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1510		pins++;
1511		nb_pins_available++;
1512	}
1513
1514	pctl->npins = nb_pins_available;
1515
1516	return 0;
1517}
1518
1519int stm32_pctl_probe(struct platform_device *pdev)
1520{
1521	const struct stm32_pinctrl_match_data *match_data;
1522	struct fwnode_handle *child;
1523	struct device *dev = &pdev->dev;
1524	struct stm32_pinctrl *pctl;
1525	struct pinctrl_pin_desc *pins;
1526	int i, ret, hwlock_id;
1527	unsigned int banks;
1528
1529	match_data = device_get_match_data(dev);
1530	if (!match_data)
1531		return -EINVAL;
1532
1533	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1534	if (!pctl)
1535		return -ENOMEM;
1536
1537	platform_set_drvdata(pdev, pctl);
1538
1539	/* check for IRQ controller (may require deferred probe) */
1540	pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1541	if (IS_ERR(pctl->domain))
1542		return PTR_ERR(pctl->domain);
1543	if (!pctl->domain)
1544		dev_warn(dev, "pinctrl without interrupt support\n");
1545
1546	/* hwspinlock is optional */
1547	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1548	if (hwlock_id < 0) {
1549		if (hwlock_id == -EPROBE_DEFER)
1550			return hwlock_id;
1551	} else {
1552		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1553	}
1554
1555	spin_lock_init(&pctl->irqmux_lock);
1556
1557	pctl->dev = dev;
1558	pctl->match_data = match_data;
1559
1560	/*  get optional package information */
1561	if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1562		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1563
1564	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1565				  sizeof(*pctl->pins), GFP_KERNEL);
1566	if (!pctl->pins)
1567		return -ENOMEM;
1568
1569	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1570	if (ret)
1571		return ret;
1572
1573	ret = stm32_pctrl_build_state(pdev);
1574	if (ret) {
1575		dev_err(dev, "build state failed: %d\n", ret);
1576		return -EINVAL;
1577	}
1578
1579	if (pctl->domain) {
1580		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1581		if (ret)
1582			return ret;
1583	}
1584
1585	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1586			    GFP_KERNEL);
1587	if (!pins)
1588		return -ENOMEM;
1589
1590	for (i = 0; i < pctl->npins; i++)
1591		pins[i] = pctl->pins[i].pin;
1592
1593	pctl->pctl_desc.name = dev_name(&pdev->dev);
1594	pctl->pctl_desc.owner = THIS_MODULE;
1595	pctl->pctl_desc.pins = pins;
1596	pctl->pctl_desc.npins = pctl->npins;
1597	pctl->pctl_desc.link_consumers = true;
1598	pctl->pctl_desc.confops = &stm32_pconf_ops;
1599	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1600	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1601	pctl->dev = &pdev->dev;
1602
1603	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1604					       pctl);
1605
1606	if (IS_ERR(pctl->pctl_dev)) {
1607		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1608		return PTR_ERR(pctl->pctl_dev);
1609	}
1610
1611	banks = gpiochip_node_count(dev);
1612	if (!banks) {
1613		dev_err(dev, "at least one GPIO bank is required\n");
1614		return -EINVAL;
1615	}
1616	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1617			GFP_KERNEL);
1618	if (!pctl->banks)
1619		return -ENOMEM;
1620
 
 
 
 
 
1621	i = 0;
1622	for_each_gpiochip_node(dev, child) {
1623		struct stm32_gpio_bank *bank = &pctl->banks[i];
1624		struct device_node *np = to_of_node(child);
1625
1626		bank->rstc = of_reset_control_get_exclusive(np, NULL);
1627		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1628			fwnode_handle_put(child);
1629			return -EPROBE_DEFER;
1630		}
1631
1632		bank->clk = of_clk_get_by_name(np, NULL);
1633		if (IS_ERR(bank->clk)) {
1634			fwnode_handle_put(child);
1635			return dev_err_probe(dev, PTR_ERR(bank->clk),
1636					     "failed to get clk\n");
1637		}
 
1638		i++;
1639	}
1640
 
 
 
 
 
 
1641	for_each_gpiochip_node(dev, child) {
1642		ret = stm32_gpiolib_register_bank(pctl, child);
1643		if (ret) {
1644			fwnode_handle_put(child);
1645
1646			for (i = 0; i < pctl->nbanks; i++)
1647				clk_disable_unprepare(pctl->banks[i].clk);
1648
1649			return ret;
1650		}
1651
1652		pctl->nbanks++;
1653	}
1654
1655	dev_info(dev, "Pinctrl STM32 initialized\n");
1656
1657	return 0;
 
 
 
 
 
 
 
 
 
1658}
1659
1660static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1661					struct stm32_pinctrl *pctl, u32 pin)
1662{
1663	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1664	u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1665	struct pinctrl_gpio_range *range;
1666	struct stm32_gpio_bank *bank;
1667	bool pin_is_irq;
1668	int ret;
1669
1670	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1671	if (!range)
1672		return 0;
1673
1674	if (!gpiochip_line_is_valid(range->gc, offset))
1675		return 0;
1676
1677	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1678
1679	if (!desc || (!pin_is_irq && !desc->gpio_owner))
1680		return 0;
1681
1682	bank = gpiochip_get_data(range->gc);
1683
1684	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1685	alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1686	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1687	mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1688
1689	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1690	if (ret)
1691		return ret;
1692
1693	if (mode == 1) {
1694		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1695		val = val >> STM32_GPIO_BKP_VAL;
1696		__stm32_gpio_set(bank, offset, val);
1697	}
1698
1699	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1700	val >>= STM32_GPIO_BKP_TYPE;
1701	ret = stm32_pconf_set_driving(bank, offset, val);
1702	if (ret)
1703		return ret;
1704
1705	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1706	val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1707	ret = stm32_pconf_set_speed(bank, offset, val);
1708	if (ret)
1709		return ret;
1710
1711	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1712	val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1713	ret = stm32_pconf_set_bias(bank, offset, val);
1714	if (ret)
1715		return ret;
1716
1717	if (pin_is_irq)
1718		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1719
1720	return 0;
1721}
1722
1723int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
1724{
1725	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1726	int i;
1727
1728	for (i = 0; i < pctl->nbanks; i++)
1729		clk_disable(pctl->banks[i].clk);
1730
1731	return 0;
1732}
1733
1734int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1735{
1736	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1737	struct stm32_pinctrl_group *g = pctl->groups;
1738	int i;
1739
1740	for (i = 0; i < pctl->nbanks; i++)
1741		clk_enable(pctl->banks[i].clk);
 
1742
1743	for (i = 0; i < pctl->ngroups; i++, g++)
1744		stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
1745
1746	return 0;
1747}