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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023 Linaro Ltd. */
4
5#include <linux/log2.h>
6
7#include "../gsi.h"
8#include "../ipa_data.h"
9#include "../ipa_endpoint.h"
10#include "../ipa_mem.h"
11
12/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */
13enum ipa_resource_type {
14 /* Source resource types; first must have value 0 */
15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20
21 /* Destination resource types; first must have value 0 */
22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
23 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24 IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
25};
26
27/* Resource groups used for an SoC having IPA v5.0 */
28enum ipa_rsrc_group_id {
29 /* Source resource group identifiers */
30 IPA_RSRC_GROUP_SRC_UL = 0,
31 IPA_RSRC_GROUP_SRC_DL,
32 IPA_RSRC_GROUP_SRC_UNUSED_2,
33 IPA_RSRC_GROUP_SRC_UNUSED_3,
34 IPA_RSRC_GROUP_SRC_URLLC,
35 IPA_RSRC_GROUP_SRC_U_RX_QC,
36 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
37
38 /* Destination resource group identifiers */
39 IPA_RSRC_GROUP_DST_UL = 0,
40 IPA_RSRC_GROUP_DST_DL,
41 IPA_RSRC_GROUP_DST_DMA,
42 IPA_RSRC_GROUP_DST_QDSS,
43 IPA_RSRC_GROUP_DST_CV2X,
44 IPA_RSRC_GROUP_DST_UC,
45 IPA_RSRC_GROUP_DST_DRB_IP,
46 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
47};
48
49/* QSB configuration data for an SoC having IPA v5.0 */
50static const struct ipa_qsb_data ipa_qsb_data[] = {
51 [IPA_QSB_MASTER_DDR] = {
52 .max_writes = 0,
53 .max_reads = 0, /* no limit (hardware max) */
54 .max_reads_beats = 0,
55 },
56 [IPA_QSB_MASTER_PCIE] = {
57 .max_writes = 0,
58 .max_reads = 0, /* no limit (hardware max) */
59 .max_reads_beats = 0,
60 },
61};
62
63/* Endpoint configuration data for an SoC having IPA v5.0 */
64static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
65 [IPA_ENDPOINT_AP_COMMAND_TX] = {
66 .ee_id = GSI_EE_AP,
67 .channel_id = 12,
68 .endpoint_id = 14,
69 .toward_ipa = true,
70 .channel = {
71 .tre_count = 256,
72 .event_count = 256,
73 .tlv_count = 20,
74 },
75 .endpoint = {
76 .config = {
77 .resource_group = IPA_RSRC_GROUP_SRC_UL,
78 .dma_mode = true,
79 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
80 .tx = {
81 .seq_type = IPA_SEQ_DMA,
82 },
83 },
84 },
85 },
86 [IPA_ENDPOINT_AP_LAN_RX] = {
87 .ee_id = GSI_EE_AP,
88 .channel_id = 13,
89 .endpoint_id = 16,
90 .toward_ipa = false,
91 .channel = {
92 .tre_count = 256,
93 .event_count = 256,
94 .tlv_count = 9,
95 },
96 .endpoint = {
97 .config = {
98 .resource_group = IPA_RSRC_GROUP_DST_UL,
99 .aggregation = true,
100 .status_enable = true,
101 .rx = {
102 .buffer_size = 8192,
103 .pad_align = ilog2(sizeof(u32)),
104 .aggr_time_limit = 500,
105 },
106 },
107 },
108 },
109 [IPA_ENDPOINT_AP_MODEM_TX] = {
110 .ee_id = GSI_EE_AP,
111 .channel_id = 11,
112 .endpoint_id = 2,
113 .toward_ipa = true,
114 .channel = {
115 .tre_count = 512,
116 .event_count = 512,
117 .tlv_count = 25,
118 },
119 .endpoint = {
120 .filter_support = true,
121 .config = {
122 .resource_group = IPA_RSRC_GROUP_SRC_UL,
123 .checksum = true,
124 .qmap = true,
125 .status_enable = true,
126 .tx = {
127 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
128 .status_endpoint =
129 IPA_ENDPOINT_MODEM_AP_RX,
130 },
131 },
132 },
133 },
134 [IPA_ENDPOINT_AP_MODEM_RX] = {
135 .ee_id = GSI_EE_AP,
136 .channel_id = 1,
137 .endpoint_id = 23,
138 .toward_ipa = false,
139 .channel = {
140 .tre_count = 256,
141 .event_count = 256,
142 .tlv_count = 9,
143 },
144 .endpoint = {
145 .config = {
146 .resource_group = IPA_RSRC_GROUP_DST_DL,
147 .checksum = true,
148 .qmap = true,
149 .aggregation = true,
150 .rx = {
151 .buffer_size = 8192,
152 .aggr_time_limit = 500,
153 .aggr_close_eof = true,
154 },
155 },
156 },
157 },
158 [IPA_ENDPOINT_MODEM_AP_TX] = {
159 .ee_id = GSI_EE_MODEM,
160 .channel_id = 0,
161 .endpoint_id = 12,
162 .toward_ipa = true,
163 .endpoint = {
164 .filter_support = true,
165 },
166 },
167 [IPA_ENDPOINT_MODEM_AP_RX] = {
168 .ee_id = GSI_EE_MODEM,
169 .channel_id = 7,
170 .endpoint_id = 21,
171 .toward_ipa = false,
172 },
173 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
174 .ee_id = GSI_EE_MODEM,
175 .channel_id = 2,
176 .endpoint_id = 15,
177 .toward_ipa = true,
178 .endpoint = {
179 .filter_support = true,
180 },
181 },
182};
183
184/* Source resource configuration data for an SoC having IPA v5.0 */
185static const struct ipa_resource ipa_resource_src[] = {
186 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
187 .limits[IPA_RSRC_GROUP_SRC_UL] = {
188 .min = 3, .max = 9,
189 },
190 .limits[IPA_RSRC_GROUP_SRC_DL] = {
191 .min = 4, .max = 10,
192 },
193 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
194 .min = 1, .max = 63,
195 },
196 .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
197 .min = 0, .max = 63,
198 },
199 },
200 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
201 .limits[IPA_RSRC_GROUP_SRC_UL] = {
202 .min = 9, .max = 9,
203 },
204 .limits[IPA_RSRC_GROUP_SRC_DL] = {
205 .min = 12, .max = 12,
206 },
207 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
208 .min = 10, .max = 10,
209 },
210 },
211 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
212 .limits[IPA_RSRC_GROUP_SRC_UL] = {
213 .min = 9, .max = 9,
214 },
215 .limits[IPA_RSRC_GROUP_SRC_DL] = {
216 .min = 24, .max = 24,
217 },
218 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
219 .min = 20, .max = 20,
220 },
221 },
222 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
223 .limits[IPA_RSRC_GROUP_SRC_UL] = {
224 .min = 0, .max = 63,
225 },
226 .limits[IPA_RSRC_GROUP_SRC_DL] = {
227 .min = 0, .max = 63,
228 },
229 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
230 .min = 1, .max = 63,
231 },
232 .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
233 .min = 0, .max = 63,
234 },
235 },
236 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
237 .limits[IPA_RSRC_GROUP_SRC_UL] = {
238 .min = 22, .max = 22,
239 },
240 .limits[IPA_RSRC_GROUP_SRC_DL] = {
241 .min = 16, .max = 16,
242 },
243 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
244 .min = 16, .max = 16,
245 },
246 },
247};
248
249/* Destination resource configuration data for an SoC having IPA v5.0 */
250static const struct ipa_resource ipa_resource_dst[] = {
251 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
252 .limits[IPA_RSRC_GROUP_DST_UL] = {
253 .min = 6, .max = 6,
254 },
255 .limits[IPA_RSRC_GROUP_DST_DL] = {
256 .min = 5, .max = 5,
257 },
258 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
259 .min = 39, .max = 39,
260 },
261 },
262 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
263 .limits[IPA_RSRC_GROUP_DST_UL] = {
264 .min = 0, .max = 3,
265 },
266 .limits[IPA_RSRC_GROUP_DST_DL] = {
267 .min = 0, .max = 3,
268 },
269 },
270 [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
271 .limits[IPA_RSRC_GROUP_DST_UL] = {
272 .min = 0, .max = 63,
273 },
274 .limits[IPA_RSRC_GROUP_DST_DL] = {
275 .min = 0, .max = 63,
276 },
277 },
278};
279
280/* Resource configuration data for an SoC having IPA v5.0 */
281static const struct ipa_resource_data ipa_resource_data = {
282 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
283 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
284 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
285 .resource_src = ipa_resource_src,
286 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
287 .resource_dst = ipa_resource_dst,
288};
289
290/* IPA-resident memory region data for an SoC having IPA v5.0 */
291static const struct ipa_mem ipa_mem_local_data[] = {
292 {
293 .id = IPA_MEM_UC_EVENT_RING,
294 .offset = 0x0000,
295 .size = 0x1000,
296 .canary_count = 0,
297 },
298 {
299 .id = IPA_MEM_UC_SHARED,
300 .offset = 0x1000,
301 .size = 0x0080,
302 .canary_count = 0,
303 },
304 {
305 .id = IPA_MEM_UC_INFO,
306 .offset = 0x1080,
307 .size = 0x0200,
308 .canary_count = 0,
309 },
310 {
311 .id = IPA_MEM_V4_FILTER_HASHED,
312 .offset = 0x1288,
313 .size = 0x0078,
314 .canary_count = 2,
315 },
316 {
317 .id = IPA_MEM_V4_FILTER,
318 .offset = 0x1308,
319 .size = 0x0078,
320 .canary_count = 2,
321 },
322 {
323 .id = IPA_MEM_V6_FILTER_HASHED,
324 .offset = 0x1388,
325 .size = 0x0078,
326 .canary_count = 2,
327 },
328 {
329 .id = IPA_MEM_V6_FILTER,
330 .offset = 0x1408,
331 .size = 0x0078,
332 .canary_count = 2,
333 },
334 {
335 .id = IPA_MEM_V4_ROUTE_HASHED,
336 .offset = 0x1488,
337 .size = 0x0098,
338 .canary_count = 2,
339 },
340 {
341 .id = IPA_MEM_V4_ROUTE,
342 .offset = 0x1528,
343 .size = 0x0098,
344 .canary_count = 2,
345 },
346 {
347 .id = IPA_MEM_V6_ROUTE_HASHED,
348 .offset = 0x15c8,
349 .size = 0x0098,
350 .canary_count = 2,
351 },
352 {
353 .id = IPA_MEM_V6_ROUTE,
354 .offset = 0x1668,
355 .size = 0x0098,
356 .canary_count = 2,
357 },
358 {
359 .id = IPA_MEM_MODEM_HEADER,
360 .offset = 0x1708,
361 .size = 0x0240,
362 .canary_count = 2,
363 },
364 {
365 .id = IPA_MEM_AP_HEADER,
366 .offset = 0x1948,
367 .size = 0x01e0,
368 .canary_count = 0,
369 },
370 {
371 .id = IPA_MEM_MODEM_PROC_CTX,
372 .offset = 0x1b40,
373 .size = 0x0b20,
374 .canary_count = 2,
375 },
376 {
377 .id = IPA_MEM_AP_PROC_CTX,
378 .offset = 0x2660,
379 .size = 0x0200,
380 .canary_count = 0,
381 },
382 {
383 .id = IPA_MEM_STATS_QUOTA_MODEM,
384 .offset = 0x2868,
385 .size = 0x0060,
386 .canary_count = 2,
387 },
388 {
389 .id = IPA_MEM_STATS_QUOTA_AP,
390 .offset = 0x28c8,
391 .size = 0x0048,
392 .canary_count = 0,
393 },
394 {
395 .id = IPA_MEM_AP_V4_FILTER,
396 .offset = 0x2918,
397 .size = 0x0118,
398 .canary_count = 2,
399 },
400 {
401 .id = IPA_MEM_AP_V6_FILTER,
402 .offset = 0x2aa0,
403 .size = 0x0228,
404 .canary_count = 0,
405 },
406 {
407 .id = IPA_MEM_STATS_FILTER_ROUTE,
408 .offset = 0x2cd0,
409 .size = 0x0ba0,
410 .canary_count = 2,
411 },
412 {
413 .id = IPA_MEM_STATS_DROP,
414 .offset = 0x3870,
415 .size = 0x0020,
416 .canary_count = 0,
417 },
418 {
419 .id = IPA_MEM_MODEM,
420 .offset = 0x3898,
421 .size = 0x0d48,
422 .canary_count = 2,
423 },
424 {
425 .id = IPA_MEM_NAT_TABLE,
426 .offset = 0x45e0,
427 .size = 0x0900,
428 .canary_count = 0,
429 },
430 {
431 .id = IPA_MEM_PDN_CONFIG,
432 .offset = 0x4ee8,
433 .size = 0x0100,
434 .canary_count = 2,
435 },
436};
437
438/* Memory configuration data for an SoC having IPA v5.0 */
439static const struct ipa_mem_data ipa_mem_data = {
440 .local_count = ARRAY_SIZE(ipa_mem_local_data),
441 .local = ipa_mem_local_data,
442 .imem_addr = 0x14688000,
443 .imem_size = 0x00003000,
444 .smem_id = 497,
445 .smem_size = 0x00009000,
446};
447
448/* Interconnect rates are in 1000 byte/second units */
449static const struct ipa_interconnect_data ipa_interconnect_data[] = {
450 {
451 .name = "memory",
452 .peak_bandwidth = 1900000, /* 1.9 GBps */
453 .average_bandwidth = 600000, /* 600 MBps */
454 },
455 /* Average rate is unused for the next interconnect */
456 {
457 .name = "config",
458 .peak_bandwidth = 76800, /* 76.8 MBps */
459 .average_bandwidth = 0, /* unused */
460 },
461};
462
463/* Clock and interconnect configuration data for an SoC having IPA v5.0 */
464static const struct ipa_power_data ipa_power_data = {
465 .core_clock_rate = 120 * 1000 * 1000, /* Hz */
466 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
467 .interconnect_data = ipa_interconnect_data,
468};
469
470/* Configuration data for an SoC having IPA v5.0. */
471const struct ipa_data ipa_data_v5_0 = {
472 .version = IPA_VERSION_5_0,
473 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
474 .qsb_data = ipa_qsb_data,
475 .modem_route_count = 11,
476 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
477 .endpoint_data = ipa_gsi_endpoint_data,
478 .resource_data = &ipa_resource_data,
479 .mem_data = &ipa_mem_data,
480 .power_data = &ipa_power_data,
481};
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023-2024 Linaro Ltd. */
4
5#include <linux/array_size.h>
6#include <linux/log2.h>
7
8#include "../ipa_data.h"
9#include "../ipa_endpoint.h"
10#include "../ipa_mem.h"
11#include "../ipa_version.h"
12
13/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */
14enum ipa_resource_type {
15 /* Source resource types; first must have value 0 */
16 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
19 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
20 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
21
22 /* Destination resource types; first must have value 0 */
23 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
24 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
25 IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
26};
27
28/* Resource groups used for an SoC having IPA v5.0 */
29enum ipa_rsrc_group_id {
30 /* Source resource group identifiers */
31 IPA_RSRC_GROUP_SRC_UL = 0,
32 IPA_RSRC_GROUP_SRC_DL,
33 IPA_RSRC_GROUP_SRC_UNUSED_2,
34 IPA_RSRC_GROUP_SRC_UNUSED_3,
35 IPA_RSRC_GROUP_SRC_URLLC,
36 IPA_RSRC_GROUP_SRC_U_RX_QC,
37 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
38
39 /* Destination resource group identifiers */
40 IPA_RSRC_GROUP_DST_UL = 0,
41 IPA_RSRC_GROUP_DST_DL,
42 IPA_RSRC_GROUP_DST_DMA,
43 IPA_RSRC_GROUP_DST_QDSS,
44 IPA_RSRC_GROUP_DST_CV2X,
45 IPA_RSRC_GROUP_DST_UC,
46 IPA_RSRC_GROUP_DST_DRB_IP,
47 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
48};
49
50/* QSB configuration data for an SoC having IPA v5.0 */
51static const struct ipa_qsb_data ipa_qsb_data[] = {
52 [IPA_QSB_MASTER_DDR] = {
53 .max_writes = 0,
54 .max_reads = 0, /* no limit (hardware max) */
55 .max_reads_beats = 0,
56 },
57 [IPA_QSB_MASTER_PCIE] = {
58 .max_writes = 0,
59 .max_reads = 0, /* no limit (hardware max) */
60 .max_reads_beats = 0,
61 },
62};
63
64/* Endpoint configuration data for an SoC having IPA v5.0 */
65static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
66 [IPA_ENDPOINT_AP_COMMAND_TX] = {
67 .ee_id = GSI_EE_AP,
68 .channel_id = 12,
69 .endpoint_id = 14,
70 .toward_ipa = true,
71 .channel = {
72 .tre_count = 256,
73 .event_count = 256,
74 .tlv_count = 20,
75 },
76 .endpoint = {
77 .config = {
78 .resource_group = IPA_RSRC_GROUP_SRC_UL,
79 .dma_mode = true,
80 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
81 .tx = {
82 .seq_type = IPA_SEQ_DMA,
83 },
84 },
85 },
86 },
87 [IPA_ENDPOINT_AP_LAN_RX] = {
88 .ee_id = GSI_EE_AP,
89 .channel_id = 13,
90 .endpoint_id = 16,
91 .toward_ipa = false,
92 .channel = {
93 .tre_count = 256,
94 .event_count = 256,
95 .tlv_count = 9,
96 },
97 .endpoint = {
98 .config = {
99 .resource_group = IPA_RSRC_GROUP_DST_UL,
100 .aggregation = true,
101 .status_enable = true,
102 .rx = {
103 .buffer_size = 8192,
104 .pad_align = ilog2(sizeof(u32)),
105 .aggr_time_limit = 500,
106 },
107 },
108 },
109 },
110 [IPA_ENDPOINT_AP_MODEM_TX] = {
111 .ee_id = GSI_EE_AP,
112 .channel_id = 11,
113 .endpoint_id = 2,
114 .toward_ipa = true,
115 .channel = {
116 .tre_count = 512,
117 .event_count = 512,
118 .tlv_count = 25,
119 },
120 .endpoint = {
121 .filter_support = true,
122 .config = {
123 .resource_group = IPA_RSRC_GROUP_SRC_UL,
124 .checksum = true,
125 .qmap = true,
126 .status_enable = true,
127 .tx = {
128 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
129 .status_endpoint =
130 IPA_ENDPOINT_MODEM_AP_RX,
131 },
132 },
133 },
134 },
135 [IPA_ENDPOINT_AP_MODEM_RX] = {
136 .ee_id = GSI_EE_AP,
137 .channel_id = 1,
138 .endpoint_id = 23,
139 .toward_ipa = false,
140 .channel = {
141 .tre_count = 256,
142 .event_count = 256,
143 .tlv_count = 9,
144 },
145 .endpoint = {
146 .config = {
147 .resource_group = IPA_RSRC_GROUP_DST_DL,
148 .checksum = true,
149 .qmap = true,
150 .aggregation = true,
151 .rx = {
152 .buffer_size = 8192,
153 .aggr_time_limit = 500,
154 .aggr_close_eof = true,
155 },
156 },
157 },
158 },
159 [IPA_ENDPOINT_MODEM_AP_TX] = {
160 .ee_id = GSI_EE_MODEM,
161 .channel_id = 0,
162 .endpoint_id = 12,
163 .toward_ipa = true,
164 .endpoint = {
165 .filter_support = true,
166 },
167 },
168 [IPA_ENDPOINT_MODEM_AP_RX] = {
169 .ee_id = GSI_EE_MODEM,
170 .channel_id = 7,
171 .endpoint_id = 21,
172 .toward_ipa = false,
173 },
174 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
175 .ee_id = GSI_EE_MODEM,
176 .channel_id = 2,
177 .endpoint_id = 15,
178 .toward_ipa = true,
179 .endpoint = {
180 .filter_support = true,
181 },
182 },
183};
184
185/* Source resource configuration data for an SoC having IPA v5.0 */
186static const struct ipa_resource ipa_resource_src[] = {
187 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
188 .limits[IPA_RSRC_GROUP_SRC_UL] = {
189 .min = 3, .max = 9,
190 },
191 .limits[IPA_RSRC_GROUP_SRC_DL] = {
192 .min = 4, .max = 10,
193 },
194 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
195 .min = 1, .max = 63,
196 },
197 .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
198 .min = 0, .max = 63,
199 },
200 },
201 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
202 .limits[IPA_RSRC_GROUP_SRC_UL] = {
203 .min = 9, .max = 9,
204 },
205 .limits[IPA_RSRC_GROUP_SRC_DL] = {
206 .min = 12, .max = 12,
207 },
208 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
209 .min = 10, .max = 10,
210 },
211 },
212 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
213 .limits[IPA_RSRC_GROUP_SRC_UL] = {
214 .min = 9, .max = 9,
215 },
216 .limits[IPA_RSRC_GROUP_SRC_DL] = {
217 .min = 24, .max = 24,
218 },
219 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
220 .min = 20, .max = 20,
221 },
222 },
223 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
224 .limits[IPA_RSRC_GROUP_SRC_UL] = {
225 .min = 0, .max = 63,
226 },
227 .limits[IPA_RSRC_GROUP_SRC_DL] = {
228 .min = 0, .max = 63,
229 },
230 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
231 .min = 1, .max = 63,
232 },
233 .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
234 .min = 0, .max = 63,
235 },
236 },
237 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
238 .limits[IPA_RSRC_GROUP_SRC_UL] = {
239 .min = 22, .max = 22,
240 },
241 .limits[IPA_RSRC_GROUP_SRC_DL] = {
242 .min = 16, .max = 16,
243 },
244 .limits[IPA_RSRC_GROUP_SRC_URLLC] = {
245 .min = 16, .max = 16,
246 },
247 },
248};
249
250/* Destination resource configuration data for an SoC having IPA v5.0 */
251static const struct ipa_resource ipa_resource_dst[] = {
252 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
253 .limits[IPA_RSRC_GROUP_DST_UL] = {
254 .min = 6, .max = 6,
255 },
256 .limits[IPA_RSRC_GROUP_DST_DL] = {
257 .min = 5, .max = 5,
258 },
259 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
260 .min = 39, .max = 39,
261 },
262 },
263 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
264 .limits[IPA_RSRC_GROUP_DST_UL] = {
265 .min = 0, .max = 3,
266 },
267 .limits[IPA_RSRC_GROUP_DST_DL] = {
268 .min = 0, .max = 3,
269 },
270 },
271 [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
272 .limits[IPA_RSRC_GROUP_DST_UL] = {
273 .min = 0, .max = 63,
274 },
275 .limits[IPA_RSRC_GROUP_DST_DL] = {
276 .min = 0, .max = 63,
277 },
278 },
279};
280
281/* Resource configuration data for an SoC having IPA v5.0 */
282static const struct ipa_resource_data ipa_resource_data = {
283 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
284 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
285 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
286 .resource_src = ipa_resource_src,
287 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
288 .resource_dst = ipa_resource_dst,
289};
290
291/* IPA-resident memory region data for an SoC having IPA v5.0 */
292static const struct ipa_mem ipa_mem_local_data[] = {
293 {
294 .id = IPA_MEM_UC_EVENT_RING,
295 .offset = 0x0000,
296 .size = 0x1000,
297 .canary_count = 0,
298 },
299 {
300 .id = IPA_MEM_UC_SHARED,
301 .offset = 0x1000,
302 .size = 0x0080,
303 .canary_count = 0,
304 },
305 {
306 .id = IPA_MEM_UC_INFO,
307 .offset = 0x1080,
308 .size = 0x0200,
309 .canary_count = 0,
310 },
311 {
312 .id = IPA_MEM_V4_FILTER_HASHED,
313 .offset = 0x1288,
314 .size = 0x0078,
315 .canary_count = 2,
316 },
317 {
318 .id = IPA_MEM_V4_FILTER,
319 .offset = 0x1308,
320 .size = 0x0078,
321 .canary_count = 2,
322 },
323 {
324 .id = IPA_MEM_V6_FILTER_HASHED,
325 .offset = 0x1388,
326 .size = 0x0078,
327 .canary_count = 2,
328 },
329 {
330 .id = IPA_MEM_V6_FILTER,
331 .offset = 0x1408,
332 .size = 0x0078,
333 .canary_count = 2,
334 },
335 {
336 .id = IPA_MEM_V4_ROUTE_HASHED,
337 .offset = 0x1488,
338 .size = 0x0098,
339 .canary_count = 2,
340 },
341 {
342 .id = IPA_MEM_V4_ROUTE,
343 .offset = 0x1528,
344 .size = 0x0098,
345 .canary_count = 2,
346 },
347 {
348 .id = IPA_MEM_V6_ROUTE_HASHED,
349 .offset = 0x15c8,
350 .size = 0x0098,
351 .canary_count = 2,
352 },
353 {
354 .id = IPA_MEM_V6_ROUTE,
355 .offset = 0x1668,
356 .size = 0x0098,
357 .canary_count = 2,
358 },
359 {
360 .id = IPA_MEM_MODEM_HEADER,
361 .offset = 0x1708,
362 .size = 0x0240,
363 .canary_count = 2,
364 },
365 {
366 .id = IPA_MEM_AP_HEADER,
367 .offset = 0x1948,
368 .size = 0x01e0,
369 .canary_count = 0,
370 },
371 {
372 .id = IPA_MEM_MODEM_PROC_CTX,
373 .offset = 0x1b40,
374 .size = 0x0b20,
375 .canary_count = 2,
376 },
377 {
378 .id = IPA_MEM_AP_PROC_CTX,
379 .offset = 0x2660,
380 .size = 0x0200,
381 .canary_count = 0,
382 },
383 {
384 .id = IPA_MEM_STATS_QUOTA_MODEM,
385 .offset = 0x2868,
386 .size = 0x0060,
387 .canary_count = 2,
388 },
389 {
390 .id = IPA_MEM_STATS_QUOTA_AP,
391 .offset = 0x28c8,
392 .size = 0x0048,
393 .canary_count = 0,
394 },
395 {
396 .id = IPA_MEM_AP_V4_FILTER,
397 .offset = 0x2918,
398 .size = 0x0118,
399 .canary_count = 2,
400 },
401 {
402 .id = IPA_MEM_AP_V6_FILTER,
403 .offset = 0x2aa0,
404 .size = 0x0228,
405 .canary_count = 0,
406 },
407 {
408 .id = IPA_MEM_STATS_FILTER_ROUTE,
409 .offset = 0x2cd0,
410 .size = 0x0ba0,
411 .canary_count = 2,
412 },
413 {
414 .id = IPA_MEM_STATS_DROP,
415 .offset = 0x3870,
416 .size = 0x0020,
417 .canary_count = 0,
418 },
419 {
420 .id = IPA_MEM_MODEM,
421 .offset = 0x3898,
422 .size = 0x0d48,
423 .canary_count = 2,
424 },
425 {
426 .id = IPA_MEM_NAT_TABLE,
427 .offset = 0x45e0,
428 .size = 0x0900,
429 .canary_count = 0,
430 },
431 {
432 .id = IPA_MEM_PDN_CONFIG,
433 .offset = 0x4ee8,
434 .size = 0x0100,
435 .canary_count = 2,
436 },
437};
438
439/* Memory configuration data for an SoC having IPA v5.0 */
440static const struct ipa_mem_data ipa_mem_data = {
441 .local_count = ARRAY_SIZE(ipa_mem_local_data),
442 .local = ipa_mem_local_data,
443 .imem_addr = 0x14688000,
444 .imem_size = 0x00003000,
445 .smem_id = 497,
446 .smem_size = 0x00009000,
447};
448
449/* Interconnect rates are in 1000 byte/second units */
450static const struct ipa_interconnect_data ipa_interconnect_data[] = {
451 {
452 .name = "memory",
453 .peak_bandwidth = 1900000, /* 1.9 GBps */
454 .average_bandwidth = 600000, /* 600 MBps */
455 },
456 /* Average rate is unused for the next interconnect */
457 {
458 .name = "config",
459 .peak_bandwidth = 76800, /* 76.8 MBps */
460 .average_bandwidth = 0, /* unused */
461 },
462};
463
464/* Clock and interconnect configuration data for an SoC having IPA v5.0 */
465static const struct ipa_power_data ipa_power_data = {
466 .core_clock_rate = 120 * 1000 * 1000, /* Hz */
467 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
468 .interconnect_data = ipa_interconnect_data,
469};
470
471/* Configuration data for an SoC having IPA v5.0. */
472const struct ipa_data ipa_data_v5_0 = {
473 .version = IPA_VERSION_5_0,
474 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
475 .qsb_data = ipa_qsb_data,
476 .modem_route_count = 11,
477 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
478 .endpoint_data = ipa_gsi_endpoint_data,
479 .resource_data = &ipa_resource_data,
480 .mem_data = &ipa_mem_data,
481 .power_data = &ipa_power_data,
482};