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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2021 Linaro Ltd. */
4
5#include <linux/log2.h>
6
7#include "../gsi.h"
8#include "../ipa_data.h"
9#include "../ipa_endpoint.h"
10#include "../ipa_mem.h"
11
12/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */
13enum ipa_resource_type {
14 /* Source resource types; first must have value 0 */
15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20
21 /* Destination resource types; first must have value 0 */
22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
23 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24};
25
26/* Resource groups used for an SoC having IPA v4.5 */
27enum ipa_rsrc_group_id {
28 /* Source resource group identifiers */
29 IPA_RSRC_GROUP_SRC_UNUSED_0 = 0,
30 IPA_RSRC_GROUP_SRC_UL_DL,
31 IPA_RSRC_GROUP_SRC_UNUSED_2,
32 IPA_RSRC_GROUP_SRC_UNUSED_3,
33 IPA_RSRC_GROUP_SRC_UC_RX_Q,
34 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
35
36 /* Destination resource group identifiers */
37 IPA_RSRC_GROUP_DST_UNUSED_0 = 0,
38 IPA_RSRC_GROUP_DST_UL_DL_DPL,
39 IPA_RSRC_GROUP_DST_UNUSED_2,
40 IPA_RSRC_GROUP_DST_UNUSED_3,
41 IPA_RSRC_GROUP_DST_UC,
42 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
43};
44
45/* QSB configuration data for an SoC having IPA v4.5 */
46static const struct ipa_qsb_data ipa_qsb_data[] = {
47 [IPA_QSB_MASTER_DDR] = {
48 .max_writes = 8,
49 .max_reads = 0, /* no limit (hardware max) */
50 .max_reads_beats = 120,
51 },
52 [IPA_QSB_MASTER_PCIE] = {
53 .max_writes = 8,
54 .max_reads = 12,
55 /* no outstanding read byte (beat) limit */
56 },
57};
58
59/* Endpoint configuration data for an SoC having IPA v4.5 */
60static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
61 [IPA_ENDPOINT_AP_COMMAND_TX] = {
62 .ee_id = GSI_EE_AP,
63 .channel_id = 9,
64 .endpoint_id = 7,
65 .toward_ipa = true,
66 .channel = {
67 .tre_count = 256,
68 .event_count = 256,
69 .tlv_count = 20,
70 },
71 .endpoint = {
72 .config = {
73 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
74 .dma_mode = true,
75 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
76 .tx = {
77 .seq_type = IPA_SEQ_DMA,
78 },
79 },
80 },
81 },
82 [IPA_ENDPOINT_AP_LAN_RX] = {
83 .ee_id = GSI_EE_AP,
84 .channel_id = 10,
85 .endpoint_id = 16,
86 .toward_ipa = false,
87 .channel = {
88 .tre_count = 256,
89 .event_count = 256,
90 .tlv_count = 9,
91 },
92 .endpoint = {
93 .config = {
94 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
95 .aggregation = true,
96 .status_enable = true,
97 .rx = {
98 .buffer_size = 8192,
99 .pad_align = ilog2(sizeof(u32)),
100 .aggr_time_limit = 500,
101 },
102 },
103 },
104 },
105 [IPA_ENDPOINT_AP_MODEM_TX] = {
106 .ee_id = GSI_EE_AP,
107 .channel_id = 7,
108 .endpoint_id = 2,
109 .toward_ipa = true,
110 .channel = {
111 .tre_count = 512,
112 .event_count = 512,
113 .tlv_count = 16,
114 },
115 .endpoint = {
116 .filter_support = true,
117 .config = {
118 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
119 .checksum = true,
120 .qmap = true,
121 .status_enable = true,
122 .tx = {
123 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
124 .status_endpoint =
125 IPA_ENDPOINT_MODEM_AP_RX,
126 },
127 },
128 },
129 },
130 [IPA_ENDPOINT_AP_MODEM_RX] = {
131 .ee_id = GSI_EE_AP,
132 .channel_id = 1,
133 .endpoint_id = 14,
134 .toward_ipa = false,
135 .channel = {
136 .tre_count = 256,
137 .event_count = 256,
138 .tlv_count = 9,
139 },
140 .endpoint = {
141 .config = {
142 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
143 .checksum = true,
144 .qmap = true,
145 .aggregation = true,
146 .rx = {
147 .buffer_size = 8192,
148 .aggr_time_limit = 500,
149 .aggr_close_eof = true,
150 },
151 },
152 },
153 },
154 [IPA_ENDPOINT_MODEM_AP_TX] = {
155 .ee_id = GSI_EE_MODEM,
156 .channel_id = 0,
157 .endpoint_id = 5,
158 .toward_ipa = true,
159 .endpoint = {
160 .filter_support = true,
161 },
162 },
163 [IPA_ENDPOINT_MODEM_AP_RX] = {
164 .ee_id = GSI_EE_MODEM,
165 .channel_id = 7,
166 .endpoint_id = 21,
167 .toward_ipa = false,
168 },
169 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
170 .ee_id = GSI_EE_MODEM,
171 .channel_id = 2,
172 .endpoint_id = 8,
173 .toward_ipa = true,
174 .endpoint = {
175 .filter_support = true,
176 },
177 },
178};
179
180/* Source resource configuration data for an SoC having IPA v4.5 */
181static const struct ipa_resource ipa_resource_src[] = {
182 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
183 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
184 .min = 1, .max = 11,
185 },
186 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
187 .min = 1, .max = 63,
188 },
189 },
190 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
191 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
192 .min = 14, .max = 14,
193 },
194 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
195 .min = 3, .max = 3,
196 },
197 },
198 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
199 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
200 .min = 18, .max = 18,
201 },
202 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
203 .min = 8, .max = 8,
204 },
205 },
206 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
207 .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {
208 .min = 0, .max = 63,
209 },
210 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
211 .min = 0, .max = 63,
212 },
213 .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {
214 .min = 0, .max = 63,
215 },
216 .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {
217 .min = 0, .max = 63,
218 },
219 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
220 .min = 0, .max = 63,
221 },
222 },
223 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
224 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
225 .min = 24, .max = 24,
226 },
227 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
228 .min = 8, .max = 8,
229 },
230 },
231};
232
233/* Destination resource configuration data for an SoC having IPA v4.5 */
234static const struct ipa_resource ipa_resource_dst[] = {
235 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
236 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
237 .min = 16, .max = 16,
238 },
239 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
240 .min = 2, .max = 2,
241 },
242 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
243 .min = 2, .max = 2,
244 },
245 },
246 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
247 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
248 .min = 2, .max = 63,
249 },
250 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
251 .min = 1, .max = 2,
252 },
253 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
254 .min = 1, .max = 2,
255 },
256 .limits[IPA_RSRC_GROUP_DST_UC] = {
257 .min = 0, .max = 2,
258 },
259 },
260};
261
262/* Resource configuration data for an SoC having IPA v4.5 */
263static const struct ipa_resource_data ipa_resource_data = {
264 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
265 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
266 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
267 .resource_src = ipa_resource_src,
268 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
269 .resource_dst = ipa_resource_dst,
270};
271
272/* IPA-resident memory region data for an SoC having IPA v4.5 */
273static const struct ipa_mem ipa_mem_local_data[] = {
274 {
275 .id = IPA_MEM_UC_SHARED,
276 .offset = 0x0000,
277 .size = 0x0080,
278 .canary_count = 0,
279 },
280 {
281 .id = IPA_MEM_UC_INFO,
282 .offset = 0x0080,
283 .size = 0x0200,
284 .canary_count = 0,
285 },
286 {
287 .id = IPA_MEM_V4_FILTER_HASHED,
288 .offset = 0x0288,
289 .size = 0x0078,
290 .canary_count = 2,
291 },
292 {
293 .id = IPA_MEM_V4_FILTER,
294 .offset = 0x0308,
295 .size = 0x0078,
296 .canary_count = 2,
297 },
298 {
299 .id = IPA_MEM_V6_FILTER_HASHED,
300 .offset = 0x0388,
301 .size = 0x0078,
302 .canary_count = 2,
303 },
304 {
305 .id = IPA_MEM_V6_FILTER,
306 .offset = 0x0408,
307 .size = 0x0078,
308 .canary_count = 2,
309 },
310 {
311 .id = IPA_MEM_V4_ROUTE_HASHED,
312 .offset = 0x0488,
313 .size = 0x0078,
314 .canary_count = 2,
315 },
316 {
317 .id = IPA_MEM_V4_ROUTE,
318 .offset = 0x0508,
319 .size = 0x0078,
320 .canary_count = 2,
321 },
322 {
323 .id = IPA_MEM_V6_ROUTE_HASHED,
324 .offset = 0x0588,
325 .size = 0x0078,
326 .canary_count = 2,
327 },
328 {
329 .id = IPA_MEM_V6_ROUTE,
330 .offset = 0x0608,
331 .size = 0x0078,
332 .canary_count = 2,
333 },
334 {
335 .id = IPA_MEM_MODEM_HEADER,
336 .offset = 0x0688,
337 .size = 0x0240,
338 .canary_count = 2,
339 },
340 {
341 .id = IPA_MEM_AP_HEADER,
342 .offset = 0x08c8,
343 .size = 0x0200,
344 .canary_count = 0,
345 },
346 {
347 .id = IPA_MEM_MODEM_PROC_CTX,
348 .offset = 0x0ad0,
349 .size = 0x0b20,
350 .canary_count = 2,
351 },
352 {
353 .id = IPA_MEM_AP_PROC_CTX,
354 .offset = 0x15f0,
355 .size = 0x0200,
356 .canary_count = 0,
357 },
358 {
359 .id = IPA_MEM_NAT_TABLE,
360 .offset = 0x1800,
361 .size = 0x0d00,
362 .canary_count = 4,
363 },
364 {
365 .id = IPA_MEM_STATS_QUOTA_MODEM,
366 .offset = 0x2510,
367 .size = 0x0030,
368 .canary_count = 4,
369 },
370 {
371 .id = IPA_MEM_STATS_QUOTA_AP,
372 .offset = 0x2540,
373 .size = 0x0048,
374 .canary_count = 0,
375 },
376 {
377 .id = IPA_MEM_STATS_TETHERING,
378 .offset = 0x2588,
379 .size = 0x0238,
380 .canary_count = 0,
381 },
382 {
383 .id = IPA_MEM_STATS_FILTER_ROUTE,
384 .offset = 0x27c0,
385 .size = 0x0800,
386 .canary_count = 0,
387 },
388 {
389 .id = IPA_MEM_STATS_DROP,
390 .offset = 0x2fc0,
391 .size = 0x0020,
392 .canary_count = 0,
393 },
394 {
395 .id = IPA_MEM_MODEM,
396 .offset = 0x2fe8,
397 .size = 0x0800,
398 .canary_count = 2,
399 },
400 {
401 .id = IPA_MEM_UC_EVENT_RING,
402 .offset = 0x3800,
403 .size = 0x1000,
404 .canary_count = 1,
405 },
406 {
407 .id = IPA_MEM_PDN_CONFIG,
408 .offset = 0x4800,
409 .size = 0x0050,
410 .canary_count = 0,
411 },
412};
413
414/* Memory configuration data for an SoC having IPA v4.5 */
415static const struct ipa_mem_data ipa_mem_data = {
416 .local_count = ARRAY_SIZE(ipa_mem_local_data),
417 .local = ipa_mem_local_data,
418 .imem_addr = 0x14688000,
419 .imem_size = 0x00003000,
420 .smem_id = 497,
421 .smem_size = 0x00009000,
422};
423
424/* Interconnect rates are in 1000 byte/second units */
425static const struct ipa_interconnect_data ipa_interconnect_data[] = {
426 {
427 .name = "memory",
428 .peak_bandwidth = 600000, /* 600 MBps */
429 .average_bandwidth = 150000, /* 150 MBps */
430 },
431 /* Average rate is unused for the next two interconnects */
432 {
433 .name = "imem",
434 .peak_bandwidth = 450000, /* 450 MBps */
435 .average_bandwidth = 75000, /* 75 MBps (unused?) */
436 },
437 {
438 .name = "config",
439 .peak_bandwidth = 171400, /* 171.4 MBps */
440 .average_bandwidth = 0, /* unused */
441 },
442};
443
444/* Clock and interconnect configuration data for an SoC having IPA v4.5 */
445static const struct ipa_power_data ipa_power_data = {
446 .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */
447 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
448 .interconnect_data = ipa_interconnect_data,
449};
450
451/* Configuration data for an SoC having IPA v4.5 */
452const struct ipa_data ipa_data_v4_5 = {
453 .version = IPA_VERSION_4_5,
454 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
455 .qsb_data = ipa_qsb_data,
456 .modem_route_count = 8,
457 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
458 .endpoint_data = ipa_gsi_endpoint_data,
459 .resource_data = &ipa_resource_data,
460 .mem_data = &ipa_mem_data,
461 .power_data = &ipa_power_data,
462};
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2021-2024 Linaro Ltd. */
4
5#include <linux/array_size.h>
6#include <linux/log2.h>
7
8#include "../ipa_data.h"
9#include "../ipa_endpoint.h"
10#include "../ipa_mem.h"
11#include "../ipa_version.h"
12
13/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */
14enum ipa_resource_type {
15 /* Source resource types; first must have value 0 */
16 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
19 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
20 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
21
22 /* Destination resource types; first must have value 0 */
23 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
24 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
25};
26
27/* Resource groups used for an SoC having IPA v4.5 */
28enum ipa_rsrc_group_id {
29 /* Source resource group identifiers */
30 IPA_RSRC_GROUP_SRC_UNUSED_0 = 0,
31 IPA_RSRC_GROUP_SRC_UL_DL,
32 IPA_RSRC_GROUP_SRC_UNUSED_2,
33 IPA_RSRC_GROUP_SRC_UNUSED_3,
34 IPA_RSRC_GROUP_SRC_UC_RX_Q,
35 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
36
37 /* Destination resource group identifiers */
38 IPA_RSRC_GROUP_DST_UNUSED_0 = 0,
39 IPA_RSRC_GROUP_DST_UL_DL_DPL,
40 IPA_RSRC_GROUP_DST_UNUSED_2,
41 IPA_RSRC_GROUP_DST_UNUSED_3,
42 IPA_RSRC_GROUP_DST_UC,
43 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
44};
45
46/* QSB configuration data for an SoC having IPA v4.5 */
47static const struct ipa_qsb_data ipa_qsb_data[] = {
48 [IPA_QSB_MASTER_DDR] = {
49 .max_writes = 8,
50 .max_reads = 0, /* no limit (hardware max) */
51 .max_reads_beats = 120,
52 },
53 [IPA_QSB_MASTER_PCIE] = {
54 .max_writes = 8,
55 .max_reads = 12,
56 /* no outstanding read byte (beat) limit */
57 },
58};
59
60/* Endpoint configuration data for an SoC having IPA v4.5 */
61static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
62 [IPA_ENDPOINT_AP_COMMAND_TX] = {
63 .ee_id = GSI_EE_AP,
64 .channel_id = 9,
65 .endpoint_id = 7,
66 .toward_ipa = true,
67 .channel = {
68 .tre_count = 256,
69 .event_count = 256,
70 .tlv_count = 20,
71 },
72 .endpoint = {
73 .config = {
74 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
75 .dma_mode = true,
76 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
77 .tx = {
78 .seq_type = IPA_SEQ_DMA,
79 },
80 },
81 },
82 },
83 [IPA_ENDPOINT_AP_LAN_RX] = {
84 .ee_id = GSI_EE_AP,
85 .channel_id = 10,
86 .endpoint_id = 16,
87 .toward_ipa = false,
88 .channel = {
89 .tre_count = 256,
90 .event_count = 256,
91 .tlv_count = 9,
92 },
93 .endpoint = {
94 .config = {
95 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
96 .aggregation = true,
97 .status_enable = true,
98 .rx = {
99 .buffer_size = 8192,
100 .pad_align = ilog2(sizeof(u32)),
101 .aggr_time_limit = 500,
102 },
103 },
104 },
105 },
106 [IPA_ENDPOINT_AP_MODEM_TX] = {
107 .ee_id = GSI_EE_AP,
108 .channel_id = 7,
109 .endpoint_id = 2,
110 .toward_ipa = true,
111 .channel = {
112 .tre_count = 512,
113 .event_count = 512,
114 .tlv_count = 16,
115 },
116 .endpoint = {
117 .filter_support = true,
118 .config = {
119 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
120 .checksum = true,
121 .qmap = true,
122 .status_enable = true,
123 .tx = {
124 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
125 .status_endpoint =
126 IPA_ENDPOINT_MODEM_AP_RX,
127 },
128 },
129 },
130 },
131 [IPA_ENDPOINT_AP_MODEM_RX] = {
132 .ee_id = GSI_EE_AP,
133 .channel_id = 1,
134 .endpoint_id = 14,
135 .toward_ipa = false,
136 .channel = {
137 .tre_count = 256,
138 .event_count = 256,
139 .tlv_count = 9,
140 },
141 .endpoint = {
142 .config = {
143 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
144 .checksum = true,
145 .qmap = true,
146 .aggregation = true,
147 .rx = {
148 .buffer_size = 8192,
149 .aggr_time_limit = 500,
150 .aggr_close_eof = true,
151 },
152 },
153 },
154 },
155 [IPA_ENDPOINT_MODEM_AP_TX] = {
156 .ee_id = GSI_EE_MODEM,
157 .channel_id = 0,
158 .endpoint_id = 5,
159 .toward_ipa = true,
160 .endpoint = {
161 .filter_support = true,
162 },
163 },
164 [IPA_ENDPOINT_MODEM_AP_RX] = {
165 .ee_id = GSI_EE_MODEM,
166 .channel_id = 7,
167 .endpoint_id = 21,
168 .toward_ipa = false,
169 },
170 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
171 .ee_id = GSI_EE_MODEM,
172 .channel_id = 2,
173 .endpoint_id = 8,
174 .toward_ipa = true,
175 .endpoint = {
176 .filter_support = true,
177 },
178 },
179};
180
181/* Source resource configuration data for an SoC having IPA v4.5 */
182static const struct ipa_resource ipa_resource_src[] = {
183 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
184 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
185 .min = 1, .max = 11,
186 },
187 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
188 .min = 1, .max = 63,
189 },
190 },
191 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
192 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
193 .min = 14, .max = 14,
194 },
195 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
196 .min = 3, .max = 3,
197 },
198 },
199 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
200 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
201 .min = 18, .max = 18,
202 },
203 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
204 .min = 8, .max = 8,
205 },
206 },
207 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
208 .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {
209 .min = 0, .max = 63,
210 },
211 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
212 .min = 0, .max = 63,
213 },
214 .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {
215 .min = 0, .max = 63,
216 },
217 .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {
218 .min = 0, .max = 63,
219 },
220 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
221 .min = 0, .max = 63,
222 },
223 },
224 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
225 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
226 .min = 24, .max = 24,
227 },
228 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
229 .min = 8, .max = 8,
230 },
231 },
232};
233
234/* Destination resource configuration data for an SoC having IPA v4.5 */
235static const struct ipa_resource ipa_resource_dst[] = {
236 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
237 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
238 .min = 16, .max = 16,
239 },
240 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
241 .min = 2, .max = 2,
242 },
243 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
244 .min = 2, .max = 2,
245 },
246 },
247 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
248 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
249 .min = 2, .max = 63,
250 },
251 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
252 .min = 1, .max = 2,
253 },
254 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
255 .min = 1, .max = 2,
256 },
257 .limits[IPA_RSRC_GROUP_DST_UC] = {
258 .min = 0, .max = 2,
259 },
260 },
261};
262
263/* Resource configuration data for an SoC having IPA v4.5 */
264static const struct ipa_resource_data ipa_resource_data = {
265 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
266 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
267 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
268 .resource_src = ipa_resource_src,
269 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
270 .resource_dst = ipa_resource_dst,
271};
272
273/* IPA-resident memory region data for an SoC having IPA v4.5 */
274static const struct ipa_mem ipa_mem_local_data[] = {
275 {
276 .id = IPA_MEM_UC_SHARED,
277 .offset = 0x0000,
278 .size = 0x0080,
279 .canary_count = 0,
280 },
281 {
282 .id = IPA_MEM_UC_INFO,
283 .offset = 0x0080,
284 .size = 0x0200,
285 .canary_count = 0,
286 },
287 {
288 .id = IPA_MEM_V4_FILTER_HASHED,
289 .offset = 0x0288,
290 .size = 0x0078,
291 .canary_count = 2,
292 },
293 {
294 .id = IPA_MEM_V4_FILTER,
295 .offset = 0x0308,
296 .size = 0x0078,
297 .canary_count = 2,
298 },
299 {
300 .id = IPA_MEM_V6_FILTER_HASHED,
301 .offset = 0x0388,
302 .size = 0x0078,
303 .canary_count = 2,
304 },
305 {
306 .id = IPA_MEM_V6_FILTER,
307 .offset = 0x0408,
308 .size = 0x0078,
309 .canary_count = 2,
310 },
311 {
312 .id = IPA_MEM_V4_ROUTE_HASHED,
313 .offset = 0x0488,
314 .size = 0x0078,
315 .canary_count = 2,
316 },
317 {
318 .id = IPA_MEM_V4_ROUTE,
319 .offset = 0x0508,
320 .size = 0x0078,
321 .canary_count = 2,
322 },
323 {
324 .id = IPA_MEM_V6_ROUTE_HASHED,
325 .offset = 0x0588,
326 .size = 0x0078,
327 .canary_count = 2,
328 },
329 {
330 .id = IPA_MEM_V6_ROUTE,
331 .offset = 0x0608,
332 .size = 0x0078,
333 .canary_count = 2,
334 },
335 {
336 .id = IPA_MEM_MODEM_HEADER,
337 .offset = 0x0688,
338 .size = 0x0240,
339 .canary_count = 2,
340 },
341 {
342 .id = IPA_MEM_AP_HEADER,
343 .offset = 0x08c8,
344 .size = 0x0200,
345 .canary_count = 0,
346 },
347 {
348 .id = IPA_MEM_MODEM_PROC_CTX,
349 .offset = 0x0ad0,
350 .size = 0x0b20,
351 .canary_count = 2,
352 },
353 {
354 .id = IPA_MEM_AP_PROC_CTX,
355 .offset = 0x15f0,
356 .size = 0x0200,
357 .canary_count = 0,
358 },
359 {
360 .id = IPA_MEM_NAT_TABLE,
361 .offset = 0x1800,
362 .size = 0x0d00,
363 .canary_count = 4,
364 },
365 {
366 .id = IPA_MEM_STATS_QUOTA_MODEM,
367 .offset = 0x2510,
368 .size = 0x0030,
369 .canary_count = 4,
370 },
371 {
372 .id = IPA_MEM_STATS_QUOTA_AP,
373 .offset = 0x2540,
374 .size = 0x0048,
375 .canary_count = 0,
376 },
377 {
378 .id = IPA_MEM_STATS_TETHERING,
379 .offset = 0x2588,
380 .size = 0x0238,
381 .canary_count = 0,
382 },
383 {
384 .id = IPA_MEM_STATS_FILTER_ROUTE,
385 .offset = 0x27c0,
386 .size = 0x0800,
387 .canary_count = 0,
388 },
389 {
390 .id = IPA_MEM_STATS_DROP,
391 .offset = 0x2fc0,
392 .size = 0x0020,
393 .canary_count = 0,
394 },
395 {
396 .id = IPA_MEM_MODEM,
397 .offset = 0x2fe8,
398 .size = 0x0800,
399 .canary_count = 2,
400 },
401 {
402 .id = IPA_MEM_UC_EVENT_RING,
403 .offset = 0x3800,
404 .size = 0x1000,
405 .canary_count = 1,
406 },
407 {
408 .id = IPA_MEM_PDN_CONFIG,
409 .offset = 0x4800,
410 .size = 0x0050,
411 .canary_count = 0,
412 },
413};
414
415/* Memory configuration data for an SoC having IPA v4.5 */
416static const struct ipa_mem_data ipa_mem_data = {
417 .local_count = ARRAY_SIZE(ipa_mem_local_data),
418 .local = ipa_mem_local_data,
419 .imem_addr = 0x14688000,
420 .imem_size = 0x00003000,
421 .smem_id = 497,
422 .smem_size = 0x00009000,
423};
424
425/* Interconnect rates are in 1000 byte/second units */
426static const struct ipa_interconnect_data ipa_interconnect_data[] = {
427 {
428 .name = "memory",
429 .peak_bandwidth = 600000, /* 600 MBps */
430 .average_bandwidth = 150000, /* 150 MBps */
431 },
432 /* Average rate is unused for the next two interconnects */
433 {
434 .name = "imem",
435 .peak_bandwidth = 450000, /* 450 MBps */
436 .average_bandwidth = 75000, /* 75 MBps (unused?) */
437 },
438 {
439 .name = "config",
440 .peak_bandwidth = 171400, /* 171.4 MBps */
441 .average_bandwidth = 0, /* unused */
442 },
443};
444
445/* Clock and interconnect configuration data for an SoC having IPA v4.5 */
446static const struct ipa_power_data ipa_power_data = {
447 .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */
448 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
449 .interconnect_data = ipa_interconnect_data,
450};
451
452/* Configuration data for an SoC having IPA v4.5 */
453const struct ipa_data ipa_data_v4_5 = {
454 .version = IPA_VERSION_4_5,
455 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
456 .qsb_data = ipa_qsb_data,
457 .modem_route_count = 8,
458 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
459 .endpoint_data = ipa_gsi_endpoint_data,
460 .resource_data = &ipa_resource_data,
461 .mem_data = &ipa_mem_data,
462 .power_data = &ipa_power_data,
463};