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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/device.h>
10#include <linux/errno.h>
11#include <linux/types.h>
12#include <linux/pci.h>
13#include <linux/dma-mapping.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16
17#include <linux/pm_domain.h>
18#include <linux/pm_runtime.h>
19
20#include <linux/mei.h>
21
22#include "mei_dev.h"
23#include "client.h"
24#include "hw-me-regs.h"
25#include "hw-me.h"
26
27/* mei_pci_tbl - PCI Device ID Table */
28static const struct pci_device_id mei_me_pci_tbl[] = {
29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
40
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
50
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
55
56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
69
70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
76
77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
79
80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
81
82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
87
88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
120
121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
124
125 /* required last entry */
126 {0, }
127};
128
129MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
130
131#ifdef CONFIG_PM
132static inline void mei_me_set_pm_domain(struct mei_device *dev);
133static inline void mei_me_unset_pm_domain(struct mei_device *dev);
134#else
135static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
136static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
137#endif /* CONFIG_PM */
138
139static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
140{
141 struct pci_dev *pdev = to_pci_dev(dev->dev);
142
143 return pci_read_config_dword(pdev, where, val);
144}
145
146/**
147 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
148 *
149 * @pdev: PCI device structure
150 * @cfg: per generation config
151 *
152 * Return: true if ME Interface is valid, false otherwise
153 */
154static bool mei_me_quirk_probe(struct pci_dev *pdev,
155 const struct mei_cfg *cfg)
156{
157 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
158 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
159 return false;
160 }
161
162 return true;
163}
164
165/**
166 * mei_me_probe - Device Initialization Routine
167 *
168 * @pdev: PCI device structure
169 * @ent: entry in kcs_pci_tbl
170 *
171 * Return: 0 on success, <0 on failure.
172 */
173static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
174{
175 const struct mei_cfg *cfg;
176 struct mei_device *dev;
177 struct mei_me_hw *hw;
178 unsigned int irqflags;
179 int err;
180
181 cfg = mei_me_get_cfg(ent->driver_data);
182 if (!cfg)
183 return -ENODEV;
184
185 if (!mei_me_quirk_probe(pdev, cfg))
186 return -ENODEV;
187
188 /* enable pci dev */
189 err = pcim_enable_device(pdev);
190 if (err) {
191 dev_err(&pdev->dev, "failed to enable pci device.\n");
192 goto end;
193 }
194 /* set PCI host mastering */
195 pci_set_master(pdev);
196 /* pci request regions and mapping IO device memory for mei driver */
197 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
198 if (err) {
199 dev_err(&pdev->dev, "failed to get pci regions.\n");
200 goto end;
201 }
202
203 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
204 if (err) {
205 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
206 goto end;
207 }
208
209 /* allocates and initializes the mei dev structure */
210 dev = mei_me_dev_init(&pdev->dev, cfg, false);
211 if (!dev) {
212 err = -ENOMEM;
213 goto end;
214 }
215 hw = to_me_hw(dev);
216 hw->mem_addr = pcim_iomap_table(pdev)[0];
217 hw->read_fws = mei_me_read_fws;
218
219 pci_enable_msi(pdev);
220
221 hw->irq = pdev->irq;
222
223 /* request and enable interrupt */
224 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
225
226 err = request_threaded_irq(pdev->irq,
227 mei_me_irq_quick_handler,
228 mei_me_irq_thread_handler,
229 irqflags, KBUILD_MODNAME, dev);
230 if (err) {
231 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
232 pdev->irq);
233 goto end;
234 }
235
236 if (mei_start(dev)) {
237 dev_err(&pdev->dev, "init hw failure.\n");
238 err = -ENODEV;
239 goto release_irq;
240 }
241
242 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
243 pm_runtime_use_autosuspend(&pdev->dev);
244
245 err = mei_register(dev, &pdev->dev);
246 if (err)
247 goto stop;
248
249 pci_set_drvdata(pdev, dev);
250
251 /*
252 * MEI requires to resume from runtime suspend mode
253 * in order to perform link reset flow upon system suspend.
254 */
255 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
256
257 /*
258 * ME maps runtime suspend/resume to D0i states,
259 * hence we need to go around native PCI runtime service which
260 * eventually brings the device into D3cold/hot state,
261 * but the mei device cannot wake up from D3 unlike from D0i3.
262 * To get around the PCI device native runtime pm,
263 * ME uses runtime pm domain handlers which take precedence
264 * over the driver's pm handlers.
265 */
266 mei_me_set_pm_domain(dev);
267
268 if (mei_pg_is_enabled(dev)) {
269 pm_runtime_put_noidle(&pdev->dev);
270 if (hw->d0i3_supported)
271 pm_runtime_allow(&pdev->dev);
272 }
273
274 dev_dbg(&pdev->dev, "initialization successful.\n");
275
276 return 0;
277
278stop:
279 mei_stop(dev);
280release_irq:
281 mei_cancel_work(dev);
282 mei_disable_interrupts(dev);
283 free_irq(pdev->irq, dev);
284end:
285 dev_err(&pdev->dev, "initialization failed.\n");
286 return err;
287}
288
289/**
290 * mei_me_shutdown - Device Removal Routine
291 *
292 * @pdev: PCI device structure
293 *
294 * mei_me_shutdown is called from the reboot notifier
295 * it's a simplified version of remove so we go down
296 * faster.
297 */
298static void mei_me_shutdown(struct pci_dev *pdev)
299{
300 struct mei_device *dev;
301
302 dev = pci_get_drvdata(pdev);
303 if (!dev)
304 return;
305
306 dev_dbg(&pdev->dev, "shutdown\n");
307 mei_stop(dev);
308
309 mei_me_unset_pm_domain(dev);
310
311 mei_disable_interrupts(dev);
312 free_irq(pdev->irq, dev);
313}
314
315/**
316 * mei_me_remove - Device Removal Routine
317 *
318 * @pdev: PCI device structure
319 *
320 * mei_me_remove is called by the PCI subsystem to alert the driver
321 * that it should release a PCI device.
322 */
323static void mei_me_remove(struct pci_dev *pdev)
324{
325 struct mei_device *dev;
326
327 dev = pci_get_drvdata(pdev);
328 if (!dev)
329 return;
330
331 if (mei_pg_is_enabled(dev))
332 pm_runtime_get_noresume(&pdev->dev);
333
334 dev_dbg(&pdev->dev, "stop\n");
335 mei_stop(dev);
336
337 mei_me_unset_pm_domain(dev);
338
339 mei_disable_interrupts(dev);
340
341 free_irq(pdev->irq, dev);
342
343 mei_deregister(dev);
344}
345
346#ifdef CONFIG_PM_SLEEP
347static int mei_me_pci_prepare(struct device *device)
348{
349 pm_runtime_resume(device);
350 return 0;
351}
352
353static int mei_me_pci_suspend(struct device *device)
354{
355 struct pci_dev *pdev = to_pci_dev(device);
356 struct mei_device *dev = pci_get_drvdata(pdev);
357
358 if (!dev)
359 return -ENODEV;
360
361 dev_dbg(&pdev->dev, "suspend\n");
362
363 mei_stop(dev);
364
365 mei_disable_interrupts(dev);
366
367 free_irq(pdev->irq, dev);
368 pci_disable_msi(pdev);
369
370 return 0;
371}
372
373static int mei_me_pci_resume(struct device *device)
374{
375 struct pci_dev *pdev = to_pci_dev(device);
376 struct mei_device *dev;
377 unsigned int irqflags;
378 int err;
379
380 dev = pci_get_drvdata(pdev);
381 if (!dev)
382 return -ENODEV;
383
384 pci_enable_msi(pdev);
385
386 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
387
388 /* request and enable interrupt */
389 err = request_threaded_irq(pdev->irq,
390 mei_me_irq_quick_handler,
391 mei_me_irq_thread_handler,
392 irqflags, KBUILD_MODNAME, dev);
393
394 if (err) {
395 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
396 pdev->irq);
397 return err;
398 }
399
400 err = mei_restart(dev);
401 if (err)
402 return err;
403
404 /* Start timer if stopped in suspend */
405 schedule_delayed_work(&dev->timer_work, HZ);
406
407 return 0;
408}
409
410static void mei_me_pci_complete(struct device *device)
411{
412 pm_runtime_suspend(device);
413}
414#else /* CONFIG_PM_SLEEP */
415
416#define mei_me_pci_prepare NULL
417#define mei_me_pci_complete NULL
418
419#endif /* !CONFIG_PM_SLEEP */
420
421#ifdef CONFIG_PM
422static int mei_me_pm_runtime_idle(struct device *device)
423{
424 struct mei_device *dev;
425
426 dev_dbg(device, "rpm: me: runtime_idle\n");
427
428 dev = dev_get_drvdata(device);
429 if (!dev)
430 return -ENODEV;
431 if (mei_write_is_idle(dev))
432 pm_runtime_autosuspend(device);
433
434 return -EBUSY;
435}
436
437static int mei_me_pm_runtime_suspend(struct device *device)
438{
439 struct mei_device *dev;
440 int ret;
441
442 dev_dbg(device, "rpm: me: runtime suspend\n");
443
444 dev = dev_get_drvdata(device);
445 if (!dev)
446 return -ENODEV;
447
448 mutex_lock(&dev->device_lock);
449
450 if (mei_write_is_idle(dev))
451 ret = mei_me_pg_enter_sync(dev);
452 else
453 ret = -EAGAIN;
454
455 mutex_unlock(&dev->device_lock);
456
457 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
458
459 if (ret && ret != -EAGAIN)
460 schedule_work(&dev->reset_work);
461
462 return ret;
463}
464
465static int mei_me_pm_runtime_resume(struct device *device)
466{
467 struct mei_device *dev;
468 int ret;
469
470 dev_dbg(device, "rpm: me: runtime resume\n");
471
472 dev = dev_get_drvdata(device);
473 if (!dev)
474 return -ENODEV;
475
476 mutex_lock(&dev->device_lock);
477
478 ret = mei_me_pg_exit_sync(dev);
479
480 mutex_unlock(&dev->device_lock);
481
482 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
483
484 if (ret)
485 schedule_work(&dev->reset_work);
486
487 return ret;
488}
489
490/**
491 * mei_me_set_pm_domain - fill and set pm domain structure for device
492 *
493 * @dev: mei_device
494 */
495static inline void mei_me_set_pm_domain(struct mei_device *dev)
496{
497 struct pci_dev *pdev = to_pci_dev(dev->dev);
498
499 if (pdev->dev.bus && pdev->dev.bus->pm) {
500 dev->pg_domain.ops = *pdev->dev.bus->pm;
501
502 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
503 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
504 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
505
506 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
507 }
508}
509
510/**
511 * mei_me_unset_pm_domain - clean pm domain structure for device
512 *
513 * @dev: mei_device
514 */
515static inline void mei_me_unset_pm_domain(struct mei_device *dev)
516{
517 /* stop using pm callbacks if any */
518 dev_pm_domain_set(dev->dev, NULL);
519}
520
521static const struct dev_pm_ops mei_me_pm_ops = {
522 .prepare = mei_me_pci_prepare,
523 .complete = mei_me_pci_complete,
524 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
525 mei_me_pci_resume)
526 SET_RUNTIME_PM_OPS(
527 mei_me_pm_runtime_suspend,
528 mei_me_pm_runtime_resume,
529 mei_me_pm_runtime_idle)
530};
531
532#define MEI_ME_PM_OPS (&mei_me_pm_ops)
533#else
534#define MEI_ME_PM_OPS NULL
535#endif /* CONFIG_PM */
536/*
537 * PCI driver structure
538 */
539static struct pci_driver mei_me_driver = {
540 .name = KBUILD_MODNAME,
541 .id_table = mei_me_pci_tbl,
542 .probe = mei_me_probe,
543 .remove = mei_me_remove,
544 .shutdown = mei_me_shutdown,
545 .driver.pm = MEI_ME_PM_OPS,
546 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
547};
548
549module_pci_driver(mei_me_driver);
550
551MODULE_AUTHOR("Intel Corporation");
552MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
553MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/device.h>
10#include <linux/errno.h>
11#include <linux/types.h>
12#include <linux/pci.h>
13#include <linux/dma-mapping.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16
17#include <linux/pm_domain.h>
18#include <linux/pm_runtime.h>
19
20#include <linux/mei.h>
21
22#include "mei_dev.h"
23#include "client.h"
24#include "hw-me-regs.h"
25#include "hw-me.h"
26
27/* mei_pci_tbl - PCI Device ID Table */
28static const struct pci_device_id mei_me_pci_tbl[] = {
29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
40
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
50
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
55
56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
69
70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
76
77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
79
80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
81
82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
87
88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
120
121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
124
125 {MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
126
127 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_P, MEI_ME_PCH15_CFG)},
128
129 /* required last entry */
130 {0, }
131};
132
133MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
134
135#ifdef CONFIG_PM
136static inline void mei_me_set_pm_domain(struct mei_device *dev);
137static inline void mei_me_unset_pm_domain(struct mei_device *dev);
138#else
139static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
140static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
141#endif /* CONFIG_PM */
142
143static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
144{
145 struct pci_dev *pdev = to_pci_dev(dev->dev);
146
147 return pci_read_config_dword(pdev, where, val);
148}
149
150/**
151 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
152 *
153 * @pdev: PCI device structure
154 * @cfg: per generation config
155 *
156 * Return: true if ME Interface is valid, false otherwise
157 */
158static bool mei_me_quirk_probe(struct pci_dev *pdev,
159 const struct mei_cfg *cfg)
160{
161 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
162 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
163 return false;
164 }
165
166 return true;
167}
168
169/**
170 * mei_me_probe - Device Initialization Routine
171 *
172 * @pdev: PCI device structure
173 * @ent: entry in kcs_pci_tbl
174 *
175 * Return: 0 on success, <0 on failure.
176 */
177static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
178{
179 const struct mei_cfg *cfg;
180 struct mei_device *dev;
181 struct mei_me_hw *hw;
182 unsigned int irqflags;
183 int err;
184
185 cfg = mei_me_get_cfg(ent->driver_data);
186 if (!cfg)
187 return -ENODEV;
188
189 if (!mei_me_quirk_probe(pdev, cfg))
190 return -ENODEV;
191
192 /* enable pci dev */
193 err = pcim_enable_device(pdev);
194 if (err) {
195 dev_err(&pdev->dev, "failed to enable pci device.\n");
196 goto end;
197 }
198 /* set PCI host mastering */
199 pci_set_master(pdev);
200 /* pci request regions and mapping IO device memory for mei driver */
201 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
202 if (err) {
203 dev_err(&pdev->dev, "failed to get pci regions.\n");
204 goto end;
205 }
206
207 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
208 if (err) {
209 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
210 goto end;
211 }
212
213 /* allocates and initializes the mei dev structure */
214 dev = mei_me_dev_init(&pdev->dev, cfg, false);
215 if (!dev) {
216 err = -ENOMEM;
217 goto end;
218 }
219 hw = to_me_hw(dev);
220 hw->mem_addr = pcim_iomap_table(pdev)[0];
221 hw->read_fws = mei_me_read_fws;
222
223 pci_enable_msi(pdev);
224
225 hw->irq = pdev->irq;
226
227 /* request and enable interrupt */
228 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
229
230 err = request_threaded_irq(pdev->irq,
231 mei_me_irq_quick_handler,
232 mei_me_irq_thread_handler,
233 irqflags, KBUILD_MODNAME, dev);
234 if (err) {
235 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
236 pdev->irq);
237 goto end;
238 }
239
240 if (mei_start(dev)) {
241 dev_err(&pdev->dev, "init hw failure.\n");
242 err = -ENODEV;
243 goto release_irq;
244 }
245
246 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
247 pm_runtime_use_autosuspend(&pdev->dev);
248
249 err = mei_register(dev, &pdev->dev);
250 if (err)
251 goto stop;
252
253 pci_set_drvdata(pdev, dev);
254
255 /*
256 * MEI requires to resume from runtime suspend mode
257 * in order to perform link reset flow upon system suspend.
258 */
259 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
260
261 /*
262 * ME maps runtime suspend/resume to D0i states,
263 * hence we need to go around native PCI runtime service which
264 * eventually brings the device into D3cold/hot state,
265 * but the mei device cannot wake up from D3 unlike from D0i3.
266 * To get around the PCI device native runtime pm,
267 * ME uses runtime pm domain handlers which take precedence
268 * over the driver's pm handlers.
269 */
270 mei_me_set_pm_domain(dev);
271
272 if (mei_pg_is_enabled(dev)) {
273 pm_runtime_put_noidle(&pdev->dev);
274 if (hw->d0i3_supported)
275 pm_runtime_allow(&pdev->dev);
276 }
277
278 dev_dbg(&pdev->dev, "initialization successful.\n");
279
280 return 0;
281
282stop:
283 mei_stop(dev);
284release_irq:
285 mei_cancel_work(dev);
286 mei_disable_interrupts(dev);
287 free_irq(pdev->irq, dev);
288end:
289 dev_err(&pdev->dev, "initialization failed.\n");
290 return err;
291}
292
293/**
294 * mei_me_shutdown - Device Removal Routine
295 *
296 * @pdev: PCI device structure
297 *
298 * mei_me_shutdown is called from the reboot notifier
299 * it's a simplified version of remove so we go down
300 * faster.
301 */
302static void mei_me_shutdown(struct pci_dev *pdev)
303{
304 struct mei_device *dev = pci_get_drvdata(pdev);
305
306 dev_dbg(&pdev->dev, "shutdown\n");
307 mei_stop(dev);
308
309 mei_me_unset_pm_domain(dev);
310
311 mei_disable_interrupts(dev);
312 free_irq(pdev->irq, dev);
313}
314
315/**
316 * mei_me_remove - Device Removal Routine
317 *
318 * @pdev: PCI device structure
319 *
320 * mei_me_remove is called by the PCI subsystem to alert the driver
321 * that it should release a PCI device.
322 */
323static void mei_me_remove(struct pci_dev *pdev)
324{
325 struct mei_device *dev = pci_get_drvdata(pdev);
326
327 if (mei_pg_is_enabled(dev))
328 pm_runtime_get_noresume(&pdev->dev);
329
330 dev_dbg(&pdev->dev, "stop\n");
331 mei_stop(dev);
332
333 mei_me_unset_pm_domain(dev);
334
335 mei_disable_interrupts(dev);
336
337 free_irq(pdev->irq, dev);
338
339 mei_deregister(dev);
340}
341
342#ifdef CONFIG_PM_SLEEP
343static int mei_me_pci_prepare(struct device *device)
344{
345 pm_runtime_resume(device);
346 return 0;
347}
348
349static int mei_me_pci_suspend(struct device *device)
350{
351 struct pci_dev *pdev = to_pci_dev(device);
352 struct mei_device *dev = pci_get_drvdata(pdev);
353
354 dev_dbg(&pdev->dev, "suspend\n");
355
356 mei_stop(dev);
357
358 mei_disable_interrupts(dev);
359
360 free_irq(pdev->irq, dev);
361 pci_disable_msi(pdev);
362
363 return 0;
364}
365
366static int mei_me_pci_resume(struct device *device)
367{
368 struct pci_dev *pdev = to_pci_dev(device);
369 struct mei_device *dev = pci_get_drvdata(pdev);
370 unsigned int irqflags;
371 int err;
372
373 pci_enable_msi(pdev);
374
375 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
376
377 /* request and enable interrupt */
378 err = request_threaded_irq(pdev->irq,
379 mei_me_irq_quick_handler,
380 mei_me_irq_thread_handler,
381 irqflags, KBUILD_MODNAME, dev);
382
383 if (err) {
384 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
385 pdev->irq);
386 return err;
387 }
388
389 err = mei_restart(dev);
390 if (err) {
391 free_irq(pdev->irq, dev);
392 return err;
393 }
394
395 /* Start timer if stopped in suspend */
396 schedule_delayed_work(&dev->timer_work, HZ);
397
398 return 0;
399}
400
401static void mei_me_pci_complete(struct device *device)
402{
403 pm_runtime_suspend(device);
404}
405#else /* CONFIG_PM_SLEEP */
406
407#define mei_me_pci_prepare NULL
408#define mei_me_pci_complete NULL
409
410#endif /* !CONFIG_PM_SLEEP */
411
412#ifdef CONFIG_PM
413static int mei_me_pm_runtime_idle(struct device *device)
414{
415 struct mei_device *dev = dev_get_drvdata(device);
416
417 dev_dbg(device, "rpm: me: runtime_idle\n");
418
419 if (mei_write_is_idle(dev))
420 pm_runtime_autosuspend(device);
421
422 return -EBUSY;
423}
424
425static int mei_me_pm_runtime_suspend(struct device *device)
426{
427 struct mei_device *dev = dev_get_drvdata(device);
428 int ret;
429
430 dev_dbg(device, "rpm: me: runtime suspend\n");
431
432 mutex_lock(&dev->device_lock);
433
434 if (mei_write_is_idle(dev))
435 ret = mei_me_pg_enter_sync(dev);
436 else
437 ret = -EAGAIN;
438
439 mutex_unlock(&dev->device_lock);
440
441 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
442
443 if (ret && ret != -EAGAIN)
444 schedule_work(&dev->reset_work);
445
446 return ret;
447}
448
449static int mei_me_pm_runtime_resume(struct device *device)
450{
451 struct mei_device *dev = dev_get_drvdata(device);
452 int ret;
453
454 dev_dbg(device, "rpm: me: runtime resume\n");
455
456 mutex_lock(&dev->device_lock);
457
458 ret = mei_me_pg_exit_sync(dev);
459
460 mutex_unlock(&dev->device_lock);
461
462 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
463
464 if (ret)
465 schedule_work(&dev->reset_work);
466
467 return ret;
468}
469
470/**
471 * mei_me_set_pm_domain - fill and set pm domain structure for device
472 *
473 * @dev: mei_device
474 */
475static inline void mei_me_set_pm_domain(struct mei_device *dev)
476{
477 struct pci_dev *pdev = to_pci_dev(dev->dev);
478
479 if (pdev->dev.bus && pdev->dev.bus->pm) {
480 dev->pg_domain.ops = *pdev->dev.bus->pm;
481
482 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
483 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
484 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
485
486 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
487 }
488}
489
490/**
491 * mei_me_unset_pm_domain - clean pm domain structure for device
492 *
493 * @dev: mei_device
494 */
495static inline void mei_me_unset_pm_domain(struct mei_device *dev)
496{
497 /* stop using pm callbacks if any */
498 dev_pm_domain_set(dev->dev, NULL);
499}
500
501static const struct dev_pm_ops mei_me_pm_ops = {
502 .prepare = mei_me_pci_prepare,
503 .complete = mei_me_pci_complete,
504 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
505 mei_me_pci_resume)
506 SET_RUNTIME_PM_OPS(
507 mei_me_pm_runtime_suspend,
508 mei_me_pm_runtime_resume,
509 mei_me_pm_runtime_idle)
510};
511
512#define MEI_ME_PM_OPS (&mei_me_pm_ops)
513#else
514#define MEI_ME_PM_OPS NULL
515#endif /* CONFIG_PM */
516/*
517 * PCI driver structure
518 */
519static struct pci_driver mei_me_driver = {
520 .name = KBUILD_MODNAME,
521 .id_table = mei_me_pci_tbl,
522 .probe = mei_me_probe,
523 .remove = mei_me_remove,
524 .shutdown = mei_me_shutdown,
525 .driver.pm = MEI_ME_PM_OPS,
526 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
527};
528
529module_pci_driver(mei_me_driver);
530
531MODULE_AUTHOR("Intel Corporation");
532MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
533MODULE_LICENSE("GPL v2");