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1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/*
3 * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved.
4 */
5
6#include <rdma/ib_user_verbs.h>
7#include <rdma/ib_verbs.h>
8#include <rdma/uverbs_types.h>
9#include <rdma/uverbs_ioctl.h>
10#include <rdma/mlx5_user_ioctl_cmds.h>
11#include <rdma/mlx5_user_ioctl_verbs.h>
12#include <rdma/ib_umem.h>
13#include <rdma/uverbs_std_types.h>
14#include <linux/mlx5/driver.h>
15#include <linux/mlx5/fs.h>
16#include "mlx5_ib.h"
17#include "devx.h"
18#include "qp.h"
19#include <linux/xarray.h>
20
21#define UVERBS_MODULE_NAME mlx5_ib
22#include <rdma/uverbs_named_ioctl.h>
23
24static void dispatch_event_fd(struct list_head *fd_list, const void *data);
25
26enum devx_obj_flags {
27 DEVX_OBJ_FLAGS_INDIRECT_MKEY = 1 << 0,
28 DEVX_OBJ_FLAGS_DCT = 1 << 1,
29 DEVX_OBJ_FLAGS_CQ = 1 << 2,
30};
31
32struct devx_async_data {
33 struct mlx5_ib_dev *mdev;
34 struct list_head list;
35 struct devx_async_cmd_event_file *ev_file;
36 struct mlx5_async_work cb_work;
37 u16 cmd_out_len;
38 /* must be last field in this structure */
39 struct mlx5_ib_uapi_devx_async_cmd_hdr hdr;
40};
41
42struct devx_async_event_data {
43 struct list_head list; /* headed in ev_file->event_list */
44 struct mlx5_ib_uapi_devx_async_event_hdr hdr;
45};
46
47/* first level XA value data structure */
48struct devx_event {
49 struct xarray object_ids; /* second XA level, Key = object id */
50 struct list_head unaffiliated_list;
51};
52
53/* second level XA value data structure */
54struct devx_obj_event {
55 struct rcu_head rcu;
56 struct list_head obj_sub_list;
57};
58
59struct devx_event_subscription {
60 struct list_head file_list; /* headed in ev_file->
61 * subscribed_events_list
62 */
63 struct list_head xa_list; /* headed in devx_event->unaffiliated_list or
64 * devx_obj_event->obj_sub_list
65 */
66 struct list_head obj_list; /* headed in devx_object */
67 struct list_head event_list; /* headed in ev_file->event_list or in
68 * temp list via subscription
69 */
70
71 u8 is_cleaned:1;
72 u32 xa_key_level1;
73 u32 xa_key_level2;
74 struct rcu_head rcu;
75 u64 cookie;
76 struct devx_async_event_file *ev_file;
77 struct eventfd_ctx *eventfd;
78};
79
80struct devx_async_event_file {
81 struct ib_uobject uobj;
82 /* Head of events that are subscribed to this FD */
83 struct list_head subscribed_events_list;
84 spinlock_t lock;
85 wait_queue_head_t poll_wait;
86 struct list_head event_list;
87 struct mlx5_ib_dev *dev;
88 u8 omit_data:1;
89 u8 is_overflow_err:1;
90 u8 is_destroyed:1;
91};
92
93struct devx_umem {
94 struct mlx5_core_dev *mdev;
95 struct ib_umem *umem;
96 u32 dinlen;
97 u32 dinbox[MLX5_ST_SZ_DW(destroy_umem_in)];
98};
99
100struct devx_umem_reg_cmd {
101 void *in;
102 u32 inlen;
103 u32 out[MLX5_ST_SZ_DW(create_umem_out)];
104};
105
106static struct mlx5_ib_ucontext *
107devx_ufile2uctx(const struct uverbs_attr_bundle *attrs)
108{
109 return to_mucontext(ib_uverbs_get_ucontext(attrs));
110}
111
112int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user)
113{
114 u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {};
115 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {};
116 void *uctx;
117 int err;
118 u16 uid;
119 u32 cap = 0;
120
121 /* 0 means not supported */
122 if (!MLX5_CAP_GEN(dev->mdev, log_max_uctx))
123 return -EINVAL;
124
125 uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx);
126 if (is_user && capable(CAP_NET_RAW) &&
127 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RAW_TX))
128 cap |= MLX5_UCTX_CAP_RAW_TX;
129 if (is_user && capable(CAP_SYS_RAWIO) &&
130 (MLX5_CAP_GEN(dev->mdev, uctx_cap) &
131 MLX5_UCTX_CAP_INTERNAL_DEV_RES))
132 cap |= MLX5_UCTX_CAP_INTERNAL_DEV_RES;
133
134 MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX);
135 MLX5_SET(uctx, uctx, cap, cap);
136
137 err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
138 if (err)
139 return err;
140
141 uid = MLX5_GET(create_uctx_out, out, uid);
142 return uid;
143}
144
145void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid)
146{
147 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {};
148 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {};
149
150 MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX);
151 MLX5_SET(destroy_uctx_in, in, uid, uid);
152
153 mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
154}
155
156static bool is_legacy_unaffiliated_event_num(u16 event_num)
157{
158 switch (event_num) {
159 case MLX5_EVENT_TYPE_PORT_CHANGE:
160 return true;
161 default:
162 return false;
163 }
164}
165
166static bool is_legacy_obj_event_num(u16 event_num)
167{
168 switch (event_num) {
169 case MLX5_EVENT_TYPE_PATH_MIG:
170 case MLX5_EVENT_TYPE_COMM_EST:
171 case MLX5_EVENT_TYPE_SQ_DRAINED:
172 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
173 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
174 case MLX5_EVENT_TYPE_CQ_ERROR:
175 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
176 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
177 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
178 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
179 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
180 case MLX5_EVENT_TYPE_DCT_DRAINED:
181 case MLX5_EVENT_TYPE_COMP:
182 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION:
183 case MLX5_EVENT_TYPE_XRQ_ERROR:
184 return true;
185 default:
186 return false;
187 }
188}
189
190static u16 get_legacy_obj_type(u16 opcode)
191{
192 switch (opcode) {
193 case MLX5_CMD_OP_CREATE_RQ:
194 return MLX5_EVENT_QUEUE_TYPE_RQ;
195 case MLX5_CMD_OP_CREATE_QP:
196 return MLX5_EVENT_QUEUE_TYPE_QP;
197 case MLX5_CMD_OP_CREATE_SQ:
198 return MLX5_EVENT_QUEUE_TYPE_SQ;
199 case MLX5_CMD_OP_CREATE_DCT:
200 return MLX5_EVENT_QUEUE_TYPE_DCT;
201 default:
202 return 0;
203 }
204}
205
206static u16 get_dec_obj_type(struct devx_obj *obj, u16 event_num)
207{
208 u16 opcode;
209
210 opcode = (obj->obj_id >> 32) & 0xffff;
211
212 if (is_legacy_obj_event_num(event_num))
213 return get_legacy_obj_type(opcode);
214
215 switch (opcode) {
216 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
217 return (obj->obj_id >> 48);
218 case MLX5_CMD_OP_CREATE_RQ:
219 return MLX5_OBJ_TYPE_RQ;
220 case MLX5_CMD_OP_CREATE_QP:
221 return MLX5_OBJ_TYPE_QP;
222 case MLX5_CMD_OP_CREATE_SQ:
223 return MLX5_OBJ_TYPE_SQ;
224 case MLX5_CMD_OP_CREATE_DCT:
225 return MLX5_OBJ_TYPE_DCT;
226 case MLX5_CMD_OP_CREATE_TIR:
227 return MLX5_OBJ_TYPE_TIR;
228 case MLX5_CMD_OP_CREATE_TIS:
229 return MLX5_OBJ_TYPE_TIS;
230 case MLX5_CMD_OP_CREATE_PSV:
231 return MLX5_OBJ_TYPE_PSV;
232 case MLX5_OBJ_TYPE_MKEY:
233 return MLX5_OBJ_TYPE_MKEY;
234 case MLX5_CMD_OP_CREATE_RMP:
235 return MLX5_OBJ_TYPE_RMP;
236 case MLX5_CMD_OP_CREATE_XRC_SRQ:
237 return MLX5_OBJ_TYPE_XRC_SRQ;
238 case MLX5_CMD_OP_CREATE_XRQ:
239 return MLX5_OBJ_TYPE_XRQ;
240 case MLX5_CMD_OP_CREATE_RQT:
241 return MLX5_OBJ_TYPE_RQT;
242 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
243 return MLX5_OBJ_TYPE_FLOW_COUNTER;
244 case MLX5_CMD_OP_CREATE_CQ:
245 return MLX5_OBJ_TYPE_CQ;
246 default:
247 return 0;
248 }
249}
250
251static u16 get_event_obj_type(unsigned long event_type, struct mlx5_eqe *eqe)
252{
253 switch (event_type) {
254 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
255 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
256 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
257 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
258 case MLX5_EVENT_TYPE_PATH_MIG:
259 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
260 case MLX5_EVENT_TYPE_COMM_EST:
261 case MLX5_EVENT_TYPE_SQ_DRAINED:
262 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
263 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
264 return eqe->data.qp_srq.type;
265 case MLX5_EVENT_TYPE_CQ_ERROR:
266 case MLX5_EVENT_TYPE_XRQ_ERROR:
267 return 0;
268 case MLX5_EVENT_TYPE_DCT_DRAINED:
269 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION:
270 return MLX5_EVENT_QUEUE_TYPE_DCT;
271 default:
272 return MLX5_GET(affiliated_event_header, &eqe->data, obj_type);
273 }
274}
275
276static u32 get_dec_obj_id(u64 obj_id)
277{
278 return (obj_id & 0xffffffff);
279}
280
281/*
282 * As the obj_id in the firmware is not globally unique the object type
283 * must be considered upon checking for a valid object id.
284 * For that the opcode of the creator command is encoded as part of the obj_id.
285 */
286static u64 get_enc_obj_id(u32 opcode, u32 obj_id)
287{
288 return ((u64)opcode << 32) | obj_id;
289}
290
291static u32 devx_get_created_obj_id(const void *in, const void *out, u16 opcode)
292{
293 switch (opcode) {
294 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
295 return MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
296 case MLX5_CMD_OP_CREATE_UMEM:
297 return MLX5_GET(create_umem_out, out, umem_id);
298 case MLX5_CMD_OP_CREATE_MKEY:
299 return MLX5_GET(create_mkey_out, out, mkey_index);
300 case MLX5_CMD_OP_CREATE_CQ:
301 return MLX5_GET(create_cq_out, out, cqn);
302 case MLX5_CMD_OP_ALLOC_PD:
303 return MLX5_GET(alloc_pd_out, out, pd);
304 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
305 return MLX5_GET(alloc_transport_domain_out, out,
306 transport_domain);
307 case MLX5_CMD_OP_CREATE_RMP:
308 return MLX5_GET(create_rmp_out, out, rmpn);
309 case MLX5_CMD_OP_CREATE_SQ:
310 return MLX5_GET(create_sq_out, out, sqn);
311 case MLX5_CMD_OP_CREATE_RQ:
312 return MLX5_GET(create_rq_out, out, rqn);
313 case MLX5_CMD_OP_CREATE_RQT:
314 return MLX5_GET(create_rqt_out, out, rqtn);
315 case MLX5_CMD_OP_CREATE_TIR:
316 return MLX5_GET(create_tir_out, out, tirn);
317 case MLX5_CMD_OP_CREATE_TIS:
318 return MLX5_GET(create_tis_out, out, tisn);
319 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
320 return MLX5_GET(alloc_q_counter_out, out, counter_set_id);
321 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
322 return MLX5_GET(create_flow_table_out, out, table_id);
323 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
324 return MLX5_GET(create_flow_group_out, out, group_id);
325 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
326 return MLX5_GET(set_fte_in, in, flow_index);
327 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
328 return MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
329 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
330 return MLX5_GET(alloc_packet_reformat_context_out, out,
331 packet_reformat_id);
332 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
333 return MLX5_GET(alloc_modify_header_context_out, out,
334 modify_header_id);
335 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
336 return MLX5_GET(create_scheduling_element_out, out,
337 scheduling_element_id);
338 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
339 return MLX5_GET(add_vxlan_udp_dport_in, in, vxlan_udp_port);
340 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
341 return MLX5_GET(set_l2_table_entry_in, in, table_index);
342 case MLX5_CMD_OP_CREATE_QP:
343 return MLX5_GET(create_qp_out, out, qpn);
344 case MLX5_CMD_OP_CREATE_SRQ:
345 return MLX5_GET(create_srq_out, out, srqn);
346 case MLX5_CMD_OP_CREATE_XRC_SRQ:
347 return MLX5_GET(create_xrc_srq_out, out, xrc_srqn);
348 case MLX5_CMD_OP_CREATE_DCT:
349 return MLX5_GET(create_dct_out, out, dctn);
350 case MLX5_CMD_OP_CREATE_XRQ:
351 return MLX5_GET(create_xrq_out, out, xrqn);
352 case MLX5_CMD_OP_ATTACH_TO_MCG:
353 return MLX5_GET(attach_to_mcg_in, in, qpn);
354 case MLX5_CMD_OP_ALLOC_XRCD:
355 return MLX5_GET(alloc_xrcd_out, out, xrcd);
356 case MLX5_CMD_OP_CREATE_PSV:
357 return MLX5_GET(create_psv_out, out, psv0_index);
358 default:
359 /* The entry must match to one of the devx_is_obj_create_cmd */
360 WARN_ON(true);
361 return 0;
362 }
363}
364
365static u64 devx_get_obj_id(const void *in)
366{
367 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
368 u64 obj_id;
369
370 switch (opcode) {
371 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
372 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
373 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_GENERAL_OBJECT |
374 MLX5_GET(general_obj_in_cmd_hdr, in,
375 obj_type) << 16,
376 MLX5_GET(general_obj_in_cmd_hdr, in,
377 obj_id));
378 break;
379 case MLX5_CMD_OP_QUERY_MKEY:
380 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_MKEY,
381 MLX5_GET(query_mkey_in, in,
382 mkey_index));
383 break;
384 case MLX5_CMD_OP_QUERY_CQ:
385 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ,
386 MLX5_GET(query_cq_in, in, cqn));
387 break;
388 case MLX5_CMD_OP_MODIFY_CQ:
389 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ,
390 MLX5_GET(modify_cq_in, in, cqn));
391 break;
392 case MLX5_CMD_OP_QUERY_SQ:
393 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ,
394 MLX5_GET(query_sq_in, in, sqn));
395 break;
396 case MLX5_CMD_OP_MODIFY_SQ:
397 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ,
398 MLX5_GET(modify_sq_in, in, sqn));
399 break;
400 case MLX5_CMD_OP_QUERY_RQ:
401 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
402 MLX5_GET(query_rq_in, in, rqn));
403 break;
404 case MLX5_CMD_OP_MODIFY_RQ:
405 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
406 MLX5_GET(modify_rq_in, in, rqn));
407 break;
408 case MLX5_CMD_OP_QUERY_RMP:
409 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP,
410 MLX5_GET(query_rmp_in, in, rmpn));
411 break;
412 case MLX5_CMD_OP_MODIFY_RMP:
413 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP,
414 MLX5_GET(modify_rmp_in, in, rmpn));
415 break;
416 case MLX5_CMD_OP_QUERY_RQT:
417 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT,
418 MLX5_GET(query_rqt_in, in, rqtn));
419 break;
420 case MLX5_CMD_OP_MODIFY_RQT:
421 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT,
422 MLX5_GET(modify_rqt_in, in, rqtn));
423 break;
424 case MLX5_CMD_OP_QUERY_TIR:
425 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR,
426 MLX5_GET(query_tir_in, in, tirn));
427 break;
428 case MLX5_CMD_OP_MODIFY_TIR:
429 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR,
430 MLX5_GET(modify_tir_in, in, tirn));
431 break;
432 case MLX5_CMD_OP_QUERY_TIS:
433 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS,
434 MLX5_GET(query_tis_in, in, tisn));
435 break;
436 case MLX5_CMD_OP_MODIFY_TIS:
437 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS,
438 MLX5_GET(modify_tis_in, in, tisn));
439 break;
440 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
441 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE,
442 MLX5_GET(query_flow_table_in, in,
443 table_id));
444 break;
445 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
446 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE,
447 MLX5_GET(modify_flow_table_in, in,
448 table_id));
449 break;
450 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
451 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_GROUP,
452 MLX5_GET(query_flow_group_in, in,
453 group_id));
454 break;
455 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
456 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY,
457 MLX5_GET(query_fte_in, in,
458 flow_index));
459 break;
460 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
461 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY,
462 MLX5_GET(set_fte_in, in, flow_index));
463 break;
464 case MLX5_CMD_OP_QUERY_Q_COUNTER:
465 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_Q_COUNTER,
466 MLX5_GET(query_q_counter_in, in,
467 counter_set_id));
468 break;
469 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
470 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_FLOW_COUNTER,
471 MLX5_GET(query_flow_counter_in, in,
472 flow_counter_id));
473 break;
474 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT:
475 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT,
476 MLX5_GET(query_modify_header_context_in,
477 in, modify_header_id));
478 break;
479 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
480 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT,
481 MLX5_GET(query_scheduling_element_in,
482 in, scheduling_element_id));
483 break;
484 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
485 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT,
486 MLX5_GET(modify_scheduling_element_in,
487 in, scheduling_element_id));
488 break;
489 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
490 obj_id = get_enc_obj_id(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT,
491 MLX5_GET(add_vxlan_udp_dport_in, in,
492 vxlan_udp_port));
493 break;
494 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
495 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY,
496 MLX5_GET(query_l2_table_entry_in, in,
497 table_index));
498 break;
499 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
500 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY,
501 MLX5_GET(set_l2_table_entry_in, in,
502 table_index));
503 break;
504 case MLX5_CMD_OP_QUERY_QP:
505 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
506 MLX5_GET(query_qp_in, in, qpn));
507 break;
508 case MLX5_CMD_OP_RST2INIT_QP:
509 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
510 MLX5_GET(rst2init_qp_in, in, qpn));
511 break;
512 case MLX5_CMD_OP_INIT2INIT_QP:
513 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
514 MLX5_GET(init2init_qp_in, in, qpn));
515 break;
516 case MLX5_CMD_OP_INIT2RTR_QP:
517 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
518 MLX5_GET(init2rtr_qp_in, in, qpn));
519 break;
520 case MLX5_CMD_OP_RTR2RTS_QP:
521 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
522 MLX5_GET(rtr2rts_qp_in, in, qpn));
523 break;
524 case MLX5_CMD_OP_RTS2RTS_QP:
525 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
526 MLX5_GET(rts2rts_qp_in, in, qpn));
527 break;
528 case MLX5_CMD_OP_SQERR2RTS_QP:
529 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
530 MLX5_GET(sqerr2rts_qp_in, in, qpn));
531 break;
532 case MLX5_CMD_OP_2ERR_QP:
533 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
534 MLX5_GET(qp_2err_in, in, qpn));
535 break;
536 case MLX5_CMD_OP_2RST_QP:
537 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
538 MLX5_GET(qp_2rst_in, in, qpn));
539 break;
540 case MLX5_CMD_OP_QUERY_DCT:
541 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
542 MLX5_GET(query_dct_in, in, dctn));
543 break;
544 case MLX5_CMD_OP_QUERY_XRQ:
545 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY:
546 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS:
547 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ,
548 MLX5_GET(query_xrq_in, in, xrqn));
549 break;
550 case MLX5_CMD_OP_QUERY_XRC_SRQ:
551 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ,
552 MLX5_GET(query_xrc_srq_in, in,
553 xrc_srqn));
554 break;
555 case MLX5_CMD_OP_ARM_XRC_SRQ:
556 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ,
557 MLX5_GET(arm_xrc_srq_in, in, xrc_srqn));
558 break;
559 case MLX5_CMD_OP_QUERY_SRQ:
560 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SRQ,
561 MLX5_GET(query_srq_in, in, srqn));
562 break;
563 case MLX5_CMD_OP_ARM_RQ:
564 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
565 MLX5_GET(arm_rq_in, in, srq_number));
566 break;
567 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
568 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
569 MLX5_GET(drain_dct_in, in, dctn));
570 break;
571 case MLX5_CMD_OP_ARM_XRQ:
572 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY:
573 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
574 case MLX5_CMD_OP_MODIFY_XRQ:
575 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ,
576 MLX5_GET(arm_xrq_in, in, xrqn));
577 break;
578 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT:
579 obj_id = get_enc_obj_id
580 (MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT,
581 MLX5_GET(query_packet_reformat_context_in,
582 in, packet_reformat_id));
583 break;
584 default:
585 obj_id = 0;
586 }
587
588 return obj_id;
589}
590
591static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs,
592 struct ib_uobject *uobj, const void *in)
593{
594 struct mlx5_ib_dev *dev = mlx5_udata_to_mdev(&attrs->driver_udata);
595 u64 obj_id = devx_get_obj_id(in);
596
597 if (!obj_id)
598 return false;
599
600 switch (uobj_get_object_id(uobj)) {
601 case UVERBS_OBJECT_CQ:
602 return get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ,
603 to_mcq(uobj->object)->mcq.cqn) ==
604 obj_id;
605
606 case UVERBS_OBJECT_SRQ:
607 {
608 struct mlx5_core_srq *srq = &(to_msrq(uobj->object)->msrq);
609 u16 opcode;
610
611 switch (srq->common.res) {
612 case MLX5_RES_XSRQ:
613 opcode = MLX5_CMD_OP_CREATE_XRC_SRQ;
614 break;
615 case MLX5_RES_XRQ:
616 opcode = MLX5_CMD_OP_CREATE_XRQ;
617 break;
618 default:
619 if (!dev->mdev->issi)
620 opcode = MLX5_CMD_OP_CREATE_SRQ;
621 else
622 opcode = MLX5_CMD_OP_CREATE_RMP;
623 }
624
625 return get_enc_obj_id(opcode,
626 to_msrq(uobj->object)->msrq.srqn) ==
627 obj_id;
628 }
629
630 case UVERBS_OBJECT_QP:
631 {
632 struct mlx5_ib_qp *qp = to_mqp(uobj->object);
633
634 if (qp->type == IB_QPT_RAW_PACKET ||
635 (qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
636 struct mlx5_ib_raw_packet_qp *raw_packet_qp =
637 &qp->raw_packet_qp;
638 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
639 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
640
641 return (get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
642 rq->base.mqp.qpn) == obj_id ||
643 get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ,
644 sq->base.mqp.qpn) == obj_id ||
645 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR,
646 rq->tirn) == obj_id ||
647 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS,
648 sq->tisn) == obj_id);
649 }
650
651 if (qp->type == MLX5_IB_QPT_DCT)
652 return get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
653 qp->dct.mdct.mqp.qpn) == obj_id;
654 return get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
655 qp->ibqp.qp_num) == obj_id;
656 }
657
658 case UVERBS_OBJECT_WQ:
659 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
660 to_mrwq(uobj->object)->core_qp.qpn) ==
661 obj_id;
662
663 case UVERBS_OBJECT_RWQ_IND_TBL:
664 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT,
665 to_mrwq_ind_table(uobj->object)->rqtn) ==
666 obj_id;
667
668 case MLX5_IB_OBJECT_DEVX_OBJ:
669 {
670 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
671 struct devx_obj *devx_uobj = uobj->object;
672
673 if (opcode == MLX5_CMD_OP_QUERY_FLOW_COUNTER &&
674 devx_uobj->flow_counter_bulk_size) {
675 u64 end;
676
677 end = devx_uobj->obj_id +
678 devx_uobj->flow_counter_bulk_size;
679 return devx_uobj->obj_id <= obj_id && end > obj_id;
680 }
681
682 return devx_uobj->obj_id == obj_id;
683 }
684
685 default:
686 return false;
687 }
688}
689
690static void devx_set_umem_valid(const void *in)
691{
692 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
693
694 switch (opcode) {
695 case MLX5_CMD_OP_CREATE_MKEY:
696 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1);
697 break;
698 case MLX5_CMD_OP_CREATE_CQ:
699 {
700 void *cqc;
701
702 MLX5_SET(create_cq_in, in, cq_umem_valid, 1);
703 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
704 MLX5_SET(cqc, cqc, dbr_umem_valid, 1);
705 break;
706 }
707 case MLX5_CMD_OP_CREATE_QP:
708 {
709 void *qpc;
710
711 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
712 MLX5_SET(qpc, qpc, dbr_umem_valid, 1);
713 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
714 break;
715 }
716
717 case MLX5_CMD_OP_CREATE_RQ:
718 {
719 void *rqc, *wq;
720
721 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
722 wq = MLX5_ADDR_OF(rqc, rqc, wq);
723 MLX5_SET(wq, wq, dbr_umem_valid, 1);
724 MLX5_SET(wq, wq, wq_umem_valid, 1);
725 break;
726 }
727
728 case MLX5_CMD_OP_CREATE_SQ:
729 {
730 void *sqc, *wq;
731
732 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
733 wq = MLX5_ADDR_OF(sqc, sqc, wq);
734 MLX5_SET(wq, wq, dbr_umem_valid, 1);
735 MLX5_SET(wq, wq, wq_umem_valid, 1);
736 break;
737 }
738
739 case MLX5_CMD_OP_MODIFY_CQ:
740 MLX5_SET(modify_cq_in, in, cq_umem_valid, 1);
741 break;
742
743 case MLX5_CMD_OP_CREATE_RMP:
744 {
745 void *rmpc, *wq;
746
747 rmpc = MLX5_ADDR_OF(create_rmp_in, in, ctx);
748 wq = MLX5_ADDR_OF(rmpc, rmpc, wq);
749 MLX5_SET(wq, wq, dbr_umem_valid, 1);
750 MLX5_SET(wq, wq, wq_umem_valid, 1);
751 break;
752 }
753
754 case MLX5_CMD_OP_CREATE_XRQ:
755 {
756 void *xrqc, *wq;
757
758 xrqc = MLX5_ADDR_OF(create_xrq_in, in, xrq_context);
759 wq = MLX5_ADDR_OF(xrqc, xrqc, wq);
760 MLX5_SET(wq, wq, dbr_umem_valid, 1);
761 MLX5_SET(wq, wq, wq_umem_valid, 1);
762 break;
763 }
764
765 case MLX5_CMD_OP_CREATE_XRC_SRQ:
766 {
767 void *xrc_srqc;
768
769 MLX5_SET(create_xrc_srq_in, in, xrc_srq_umem_valid, 1);
770 xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, in,
771 xrc_srq_context_entry);
772 MLX5_SET(xrc_srqc, xrc_srqc, dbr_umem_valid, 1);
773 break;
774 }
775
776 default:
777 return;
778 }
779}
780
781static bool devx_is_obj_create_cmd(const void *in, u16 *opcode)
782{
783 *opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
784
785 switch (*opcode) {
786 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
787 case MLX5_CMD_OP_CREATE_MKEY:
788 case MLX5_CMD_OP_CREATE_CQ:
789 case MLX5_CMD_OP_ALLOC_PD:
790 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
791 case MLX5_CMD_OP_CREATE_RMP:
792 case MLX5_CMD_OP_CREATE_SQ:
793 case MLX5_CMD_OP_CREATE_RQ:
794 case MLX5_CMD_OP_CREATE_RQT:
795 case MLX5_CMD_OP_CREATE_TIR:
796 case MLX5_CMD_OP_CREATE_TIS:
797 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
798 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
799 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
800 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
801 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
802 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
803 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
804 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
805 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
806 case MLX5_CMD_OP_CREATE_QP:
807 case MLX5_CMD_OP_CREATE_SRQ:
808 case MLX5_CMD_OP_CREATE_XRC_SRQ:
809 case MLX5_CMD_OP_CREATE_DCT:
810 case MLX5_CMD_OP_CREATE_XRQ:
811 case MLX5_CMD_OP_ATTACH_TO_MCG:
812 case MLX5_CMD_OP_ALLOC_XRCD:
813 return true;
814 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
815 {
816 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod);
817 if (op_mod == 0)
818 return true;
819 return false;
820 }
821 case MLX5_CMD_OP_CREATE_PSV:
822 {
823 u8 num_psv = MLX5_GET(create_psv_in, in, num_psv);
824
825 if (num_psv == 1)
826 return true;
827 return false;
828 }
829 default:
830 return false;
831 }
832}
833
834static bool devx_is_obj_modify_cmd(const void *in)
835{
836 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
837
838 switch (opcode) {
839 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
840 case MLX5_CMD_OP_MODIFY_CQ:
841 case MLX5_CMD_OP_MODIFY_RMP:
842 case MLX5_CMD_OP_MODIFY_SQ:
843 case MLX5_CMD_OP_MODIFY_RQ:
844 case MLX5_CMD_OP_MODIFY_RQT:
845 case MLX5_CMD_OP_MODIFY_TIR:
846 case MLX5_CMD_OP_MODIFY_TIS:
847 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
848 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
849 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
850 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
851 case MLX5_CMD_OP_RST2INIT_QP:
852 case MLX5_CMD_OP_INIT2RTR_QP:
853 case MLX5_CMD_OP_INIT2INIT_QP:
854 case MLX5_CMD_OP_RTR2RTS_QP:
855 case MLX5_CMD_OP_RTS2RTS_QP:
856 case MLX5_CMD_OP_SQERR2RTS_QP:
857 case MLX5_CMD_OP_2ERR_QP:
858 case MLX5_CMD_OP_2RST_QP:
859 case MLX5_CMD_OP_ARM_XRC_SRQ:
860 case MLX5_CMD_OP_ARM_RQ:
861 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
862 case MLX5_CMD_OP_ARM_XRQ:
863 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY:
864 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
865 case MLX5_CMD_OP_MODIFY_XRQ:
866 return true;
867 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
868 {
869 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod);
870
871 if (op_mod == 1)
872 return true;
873 return false;
874 }
875 default:
876 return false;
877 }
878}
879
880static bool devx_is_obj_query_cmd(const void *in)
881{
882 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
883
884 switch (opcode) {
885 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
886 case MLX5_CMD_OP_QUERY_MKEY:
887 case MLX5_CMD_OP_QUERY_CQ:
888 case MLX5_CMD_OP_QUERY_RMP:
889 case MLX5_CMD_OP_QUERY_SQ:
890 case MLX5_CMD_OP_QUERY_RQ:
891 case MLX5_CMD_OP_QUERY_RQT:
892 case MLX5_CMD_OP_QUERY_TIR:
893 case MLX5_CMD_OP_QUERY_TIS:
894 case MLX5_CMD_OP_QUERY_Q_COUNTER:
895 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
896 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
897 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
898 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
899 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT:
900 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
901 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
902 case MLX5_CMD_OP_QUERY_QP:
903 case MLX5_CMD_OP_QUERY_SRQ:
904 case MLX5_CMD_OP_QUERY_XRC_SRQ:
905 case MLX5_CMD_OP_QUERY_DCT:
906 case MLX5_CMD_OP_QUERY_XRQ:
907 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY:
908 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS:
909 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT:
910 return true;
911 default:
912 return false;
913 }
914}
915
916static bool devx_is_whitelist_cmd(void *in)
917{
918 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
919
920 switch (opcode) {
921 case MLX5_CMD_OP_QUERY_HCA_CAP:
922 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
923 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
924 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
925 return true;
926 default:
927 return false;
928 }
929}
930
931static int devx_get_uid(struct mlx5_ib_ucontext *c, void *cmd_in)
932{
933 if (devx_is_whitelist_cmd(cmd_in)) {
934 struct mlx5_ib_dev *dev;
935
936 if (c->devx_uid)
937 return c->devx_uid;
938
939 dev = to_mdev(c->ibucontext.device);
940 if (dev->devx_whitelist_uid)
941 return dev->devx_whitelist_uid;
942
943 return -EOPNOTSUPP;
944 }
945
946 if (!c->devx_uid)
947 return -EINVAL;
948
949 return c->devx_uid;
950}
951
952static bool devx_is_general_cmd(void *in, struct mlx5_ib_dev *dev)
953{
954 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
955
956 /* Pass all cmds for vhca_tunnel as general, tracking is done in FW */
957 if ((MLX5_CAP_GEN_64(dev->mdev, vhca_tunnel_commands) &&
958 MLX5_GET(general_obj_in_cmd_hdr, in, vhca_tunnel_id)) ||
959 (opcode >= MLX5_CMD_OP_GENERAL_START &&
960 opcode < MLX5_CMD_OP_GENERAL_END))
961 return true;
962
963 switch (opcode) {
964 case MLX5_CMD_OP_QUERY_HCA_CAP:
965 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
966 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
967 case MLX5_CMD_OP_QUERY_VPORT_STATE:
968 case MLX5_CMD_OP_QUERY_ADAPTER:
969 case MLX5_CMD_OP_QUERY_ISSI:
970 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
971 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
972 case MLX5_CMD_OP_QUERY_VNIC_ENV:
973 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
974 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
975 case MLX5_CMD_OP_NOP:
976 case MLX5_CMD_OP_QUERY_CONG_STATUS:
977 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
978 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
979 case MLX5_CMD_OP_QUERY_LAG:
980 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
981 return true;
982 default:
983 return false;
984 }
985}
986
987static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)(
988 struct uverbs_attr_bundle *attrs)
989{
990 struct mlx5_ib_ucontext *c;
991 struct mlx5_ib_dev *dev;
992 int user_vector;
993 int dev_eqn;
994 int err;
995
996 if (uverbs_copy_from(&user_vector, attrs,
997 MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC))
998 return -EFAULT;
999
1000 c = devx_ufile2uctx(attrs);
1001 if (IS_ERR(c))
1002 return PTR_ERR(c);
1003 dev = to_mdev(c->ibucontext.device);
1004
1005 err = mlx5_comp_eqn_get(dev->mdev, user_vector, &dev_eqn);
1006 if (err < 0)
1007 return err;
1008
1009 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN,
1010 &dev_eqn, sizeof(dev_eqn)))
1011 return -EFAULT;
1012
1013 return 0;
1014}
1015
1016/*
1017 *Security note:
1018 * The hardware protection mechanism works like this: Each device object that
1019 * is subject to UAR doorbells (QP/SQ/CQ) gets a UAR ID (called uar_page in
1020 * the device specification manual) upon its creation. Then upon doorbell,
1021 * hardware fetches the object context for which the doorbell was rang, and
1022 * validates that the UAR through which the DB was rang matches the UAR ID
1023 * of the object.
1024 * If no match the doorbell is silently ignored by the hardware. Of course,
1025 * the user cannot ring a doorbell on a UAR that was not mapped to it.
1026 * Now in devx, as the devx kernel does not manipulate the QP/SQ/CQ command
1027 * mailboxes (except tagging them with UID), we expose to the user its UAR
1028 * ID, so it can embed it in these objects in the expected specification
1029 * format. So the only thing the user can do is hurt itself by creating a
1030 * QP/SQ/CQ with a UAR ID other than his, and then in this case other users
1031 * may ring a doorbell on its objects.
1032 * The consequence of that will be that another user can schedule a QP/SQ
1033 * of the buggy user for execution (just insert it to the hardware schedule
1034 * queue or arm its CQ for event generation), no further harm is expected.
1035 */
1036static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_UAR)(
1037 struct uverbs_attr_bundle *attrs)
1038{
1039 struct mlx5_ib_ucontext *c;
1040 struct mlx5_ib_dev *dev;
1041 u32 user_idx;
1042 s32 dev_idx;
1043
1044 c = devx_ufile2uctx(attrs);
1045 if (IS_ERR(c))
1046 return PTR_ERR(c);
1047 dev = to_mdev(c->ibucontext.device);
1048
1049 if (uverbs_copy_from(&user_idx, attrs,
1050 MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX))
1051 return -EFAULT;
1052
1053 dev_idx = bfregn_to_uar_index(dev, &c->bfregi, user_idx, true);
1054 if (dev_idx < 0)
1055 return dev_idx;
1056
1057 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX,
1058 &dev_idx, sizeof(dev_idx)))
1059 return -EFAULT;
1060
1061 return 0;
1062}
1063
1064static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OTHER)(
1065 struct uverbs_attr_bundle *attrs)
1066{
1067 struct mlx5_ib_ucontext *c;
1068 struct mlx5_ib_dev *dev;
1069 void *cmd_in = uverbs_attr_get_alloced_ptr(
1070 attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN);
1071 int cmd_out_len = uverbs_attr_get_len(attrs,
1072 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT);
1073 void *cmd_out;
1074 int err, err2;
1075 int uid;
1076
1077 c = devx_ufile2uctx(attrs);
1078 if (IS_ERR(c))
1079 return PTR_ERR(c);
1080 dev = to_mdev(c->ibucontext.device);
1081
1082 uid = devx_get_uid(c, cmd_in);
1083 if (uid < 0)
1084 return uid;
1085
1086 /* Only white list of some general HCA commands are allowed for this method. */
1087 if (!devx_is_general_cmd(cmd_in, dev))
1088 return -EINVAL;
1089
1090 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1091 if (IS_ERR(cmd_out))
1092 return PTR_ERR(cmd_out);
1093
1094 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1095 err = mlx5_cmd_do(dev->mdev, cmd_in,
1096 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN),
1097 cmd_out, cmd_out_len);
1098 if (err && err != -EREMOTEIO)
1099 return err;
1100
1101 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, cmd_out,
1102 cmd_out_len);
1103
1104 return err2 ?: err;
1105}
1106
1107static void devx_obj_build_destroy_cmd(void *in, void *out, void *din,
1108 u32 *dinlen,
1109 u32 *obj_id)
1110{
1111 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
1112 u16 uid = MLX5_GET(general_obj_in_cmd_hdr, in, uid);
1113
1114 *obj_id = devx_get_created_obj_id(in, out, opcode);
1115 *dinlen = MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr);
1116 MLX5_SET(general_obj_in_cmd_hdr, din, uid, uid);
1117
1118 switch (opcode) {
1119 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
1120 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT);
1121 MLX5_SET(general_obj_in_cmd_hdr, din, obj_id, *obj_id);
1122 MLX5_SET(general_obj_in_cmd_hdr, din, obj_type,
1123 MLX5_GET(general_obj_in_cmd_hdr, in, obj_type));
1124 break;
1125
1126 case MLX5_CMD_OP_CREATE_UMEM:
1127 MLX5_SET(destroy_umem_in, din, opcode,
1128 MLX5_CMD_OP_DESTROY_UMEM);
1129 MLX5_SET(destroy_umem_in, din, umem_id, *obj_id);
1130 break;
1131 case MLX5_CMD_OP_CREATE_MKEY:
1132 MLX5_SET(destroy_mkey_in, din, opcode,
1133 MLX5_CMD_OP_DESTROY_MKEY);
1134 MLX5_SET(destroy_mkey_in, din, mkey_index, *obj_id);
1135 break;
1136 case MLX5_CMD_OP_CREATE_CQ:
1137 MLX5_SET(destroy_cq_in, din, opcode, MLX5_CMD_OP_DESTROY_CQ);
1138 MLX5_SET(destroy_cq_in, din, cqn, *obj_id);
1139 break;
1140 case MLX5_CMD_OP_ALLOC_PD:
1141 MLX5_SET(dealloc_pd_in, din, opcode, MLX5_CMD_OP_DEALLOC_PD);
1142 MLX5_SET(dealloc_pd_in, din, pd, *obj_id);
1143 break;
1144 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
1145 MLX5_SET(dealloc_transport_domain_in, din, opcode,
1146 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN);
1147 MLX5_SET(dealloc_transport_domain_in, din, transport_domain,
1148 *obj_id);
1149 break;
1150 case MLX5_CMD_OP_CREATE_RMP:
1151 MLX5_SET(destroy_rmp_in, din, opcode, MLX5_CMD_OP_DESTROY_RMP);
1152 MLX5_SET(destroy_rmp_in, din, rmpn, *obj_id);
1153 break;
1154 case MLX5_CMD_OP_CREATE_SQ:
1155 MLX5_SET(destroy_sq_in, din, opcode, MLX5_CMD_OP_DESTROY_SQ);
1156 MLX5_SET(destroy_sq_in, din, sqn, *obj_id);
1157 break;
1158 case MLX5_CMD_OP_CREATE_RQ:
1159 MLX5_SET(destroy_rq_in, din, opcode, MLX5_CMD_OP_DESTROY_RQ);
1160 MLX5_SET(destroy_rq_in, din, rqn, *obj_id);
1161 break;
1162 case MLX5_CMD_OP_CREATE_RQT:
1163 MLX5_SET(destroy_rqt_in, din, opcode, MLX5_CMD_OP_DESTROY_RQT);
1164 MLX5_SET(destroy_rqt_in, din, rqtn, *obj_id);
1165 break;
1166 case MLX5_CMD_OP_CREATE_TIR:
1167 MLX5_SET(destroy_tir_in, din, opcode, MLX5_CMD_OP_DESTROY_TIR);
1168 MLX5_SET(destroy_tir_in, din, tirn, *obj_id);
1169 break;
1170 case MLX5_CMD_OP_CREATE_TIS:
1171 MLX5_SET(destroy_tis_in, din, opcode, MLX5_CMD_OP_DESTROY_TIS);
1172 MLX5_SET(destroy_tis_in, din, tisn, *obj_id);
1173 break;
1174 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
1175 MLX5_SET(dealloc_q_counter_in, din, opcode,
1176 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
1177 MLX5_SET(dealloc_q_counter_in, din, counter_set_id, *obj_id);
1178 break;
1179 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
1180 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_table_in);
1181 MLX5_SET(destroy_flow_table_in, din, other_vport,
1182 MLX5_GET(create_flow_table_in, in, other_vport));
1183 MLX5_SET(destroy_flow_table_in, din, vport_number,
1184 MLX5_GET(create_flow_table_in, in, vport_number));
1185 MLX5_SET(destroy_flow_table_in, din, table_type,
1186 MLX5_GET(create_flow_table_in, in, table_type));
1187 MLX5_SET(destroy_flow_table_in, din, table_id, *obj_id);
1188 MLX5_SET(destroy_flow_table_in, din, opcode,
1189 MLX5_CMD_OP_DESTROY_FLOW_TABLE);
1190 break;
1191 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
1192 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_group_in);
1193 MLX5_SET(destroy_flow_group_in, din, other_vport,
1194 MLX5_GET(create_flow_group_in, in, other_vport));
1195 MLX5_SET(destroy_flow_group_in, din, vport_number,
1196 MLX5_GET(create_flow_group_in, in, vport_number));
1197 MLX5_SET(destroy_flow_group_in, din, table_type,
1198 MLX5_GET(create_flow_group_in, in, table_type));
1199 MLX5_SET(destroy_flow_group_in, din, table_id,
1200 MLX5_GET(create_flow_group_in, in, table_id));
1201 MLX5_SET(destroy_flow_group_in, din, group_id, *obj_id);
1202 MLX5_SET(destroy_flow_group_in, din, opcode,
1203 MLX5_CMD_OP_DESTROY_FLOW_GROUP);
1204 break;
1205 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
1206 *dinlen = MLX5_ST_SZ_BYTES(delete_fte_in);
1207 MLX5_SET(delete_fte_in, din, other_vport,
1208 MLX5_GET(set_fte_in, in, other_vport));
1209 MLX5_SET(delete_fte_in, din, vport_number,
1210 MLX5_GET(set_fte_in, in, vport_number));
1211 MLX5_SET(delete_fte_in, din, table_type,
1212 MLX5_GET(set_fte_in, in, table_type));
1213 MLX5_SET(delete_fte_in, din, table_id,
1214 MLX5_GET(set_fte_in, in, table_id));
1215 MLX5_SET(delete_fte_in, din, flow_index, *obj_id);
1216 MLX5_SET(delete_fte_in, din, opcode,
1217 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY);
1218 break;
1219 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
1220 MLX5_SET(dealloc_flow_counter_in, din, opcode,
1221 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER);
1222 MLX5_SET(dealloc_flow_counter_in, din, flow_counter_id,
1223 *obj_id);
1224 break;
1225 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
1226 MLX5_SET(dealloc_packet_reformat_context_in, din, opcode,
1227 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT);
1228 MLX5_SET(dealloc_packet_reformat_context_in, din,
1229 packet_reformat_id, *obj_id);
1230 break;
1231 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
1232 MLX5_SET(dealloc_modify_header_context_in, din, opcode,
1233 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT);
1234 MLX5_SET(dealloc_modify_header_context_in, din,
1235 modify_header_id, *obj_id);
1236 break;
1237 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
1238 *dinlen = MLX5_ST_SZ_BYTES(destroy_scheduling_element_in);
1239 MLX5_SET(destroy_scheduling_element_in, din,
1240 scheduling_hierarchy,
1241 MLX5_GET(create_scheduling_element_in, in,
1242 scheduling_hierarchy));
1243 MLX5_SET(destroy_scheduling_element_in, din,
1244 scheduling_element_id, *obj_id);
1245 MLX5_SET(destroy_scheduling_element_in, din, opcode,
1246 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
1247 break;
1248 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
1249 *dinlen = MLX5_ST_SZ_BYTES(delete_vxlan_udp_dport_in);
1250 MLX5_SET(delete_vxlan_udp_dport_in, din, vxlan_udp_port, *obj_id);
1251 MLX5_SET(delete_vxlan_udp_dport_in, din, opcode,
1252 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT);
1253 break;
1254 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
1255 *dinlen = MLX5_ST_SZ_BYTES(delete_l2_table_entry_in);
1256 MLX5_SET(delete_l2_table_entry_in, din, table_index, *obj_id);
1257 MLX5_SET(delete_l2_table_entry_in, din, opcode,
1258 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
1259 break;
1260 case MLX5_CMD_OP_CREATE_QP:
1261 MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP);
1262 MLX5_SET(destroy_qp_in, din, qpn, *obj_id);
1263 break;
1264 case MLX5_CMD_OP_CREATE_SRQ:
1265 MLX5_SET(destroy_srq_in, din, opcode, MLX5_CMD_OP_DESTROY_SRQ);
1266 MLX5_SET(destroy_srq_in, din, srqn, *obj_id);
1267 break;
1268 case MLX5_CMD_OP_CREATE_XRC_SRQ:
1269 MLX5_SET(destroy_xrc_srq_in, din, opcode,
1270 MLX5_CMD_OP_DESTROY_XRC_SRQ);
1271 MLX5_SET(destroy_xrc_srq_in, din, xrc_srqn, *obj_id);
1272 break;
1273 case MLX5_CMD_OP_CREATE_DCT:
1274 MLX5_SET(destroy_dct_in, din, opcode, MLX5_CMD_OP_DESTROY_DCT);
1275 MLX5_SET(destroy_dct_in, din, dctn, *obj_id);
1276 break;
1277 case MLX5_CMD_OP_CREATE_XRQ:
1278 MLX5_SET(destroy_xrq_in, din, opcode, MLX5_CMD_OP_DESTROY_XRQ);
1279 MLX5_SET(destroy_xrq_in, din, xrqn, *obj_id);
1280 break;
1281 case MLX5_CMD_OP_ATTACH_TO_MCG:
1282 *dinlen = MLX5_ST_SZ_BYTES(detach_from_mcg_in);
1283 MLX5_SET(detach_from_mcg_in, din, qpn,
1284 MLX5_GET(attach_to_mcg_in, in, qpn));
1285 memcpy(MLX5_ADDR_OF(detach_from_mcg_in, din, multicast_gid),
1286 MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid),
1287 MLX5_FLD_SZ_BYTES(attach_to_mcg_in, multicast_gid));
1288 MLX5_SET(detach_from_mcg_in, din, opcode,
1289 MLX5_CMD_OP_DETACH_FROM_MCG);
1290 MLX5_SET(detach_from_mcg_in, din, qpn, *obj_id);
1291 break;
1292 case MLX5_CMD_OP_ALLOC_XRCD:
1293 MLX5_SET(dealloc_xrcd_in, din, opcode,
1294 MLX5_CMD_OP_DEALLOC_XRCD);
1295 MLX5_SET(dealloc_xrcd_in, din, xrcd, *obj_id);
1296 break;
1297 case MLX5_CMD_OP_CREATE_PSV:
1298 MLX5_SET(destroy_psv_in, din, opcode,
1299 MLX5_CMD_OP_DESTROY_PSV);
1300 MLX5_SET(destroy_psv_in, din, psvn, *obj_id);
1301 break;
1302 default:
1303 /* The entry must match to one of the devx_is_obj_create_cmd */
1304 WARN_ON(true);
1305 break;
1306 }
1307}
1308
1309static int devx_handle_mkey_indirect(struct devx_obj *obj,
1310 struct mlx5_ib_dev *dev,
1311 void *in, void *out)
1312{
1313 struct mlx5_ib_mkey *mkey = &obj->mkey;
1314 void *mkc;
1315 u8 key;
1316
1317 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1318 key = MLX5_GET(mkc, mkc, mkey_7_0);
1319 mkey->key = mlx5_idx_to_mkey(
1320 MLX5_GET(create_mkey_out, out, mkey_index)) | key;
1321 mkey->type = MLX5_MKEY_INDIRECT_DEVX;
1322 mkey->ndescs = MLX5_GET(mkc, mkc, translations_octword_size);
1323 init_waitqueue_head(&mkey->wait);
1324
1325 return mlx5r_store_odp_mkey(dev, mkey);
1326}
1327
1328static int devx_handle_mkey_create(struct mlx5_ib_dev *dev,
1329 struct devx_obj *obj,
1330 void *in, int in_len)
1331{
1332 int min_len = MLX5_BYTE_OFF(create_mkey_in, memory_key_mkey_entry) +
1333 MLX5_FLD_SZ_BYTES(create_mkey_in,
1334 memory_key_mkey_entry);
1335 void *mkc;
1336 u8 access_mode;
1337
1338 if (in_len < min_len)
1339 return -EINVAL;
1340
1341 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1342
1343 access_mode = MLX5_GET(mkc, mkc, access_mode_1_0);
1344 access_mode |= MLX5_GET(mkc, mkc, access_mode_4_2) << 2;
1345
1346 if (access_mode == MLX5_MKC_ACCESS_MODE_KLMS ||
1347 access_mode == MLX5_MKC_ACCESS_MODE_KSM) {
1348 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
1349 obj->flags |= DEVX_OBJ_FLAGS_INDIRECT_MKEY;
1350 return 0;
1351 }
1352
1353 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1);
1354 return 0;
1355}
1356
1357static void devx_cleanup_subscription(struct mlx5_ib_dev *dev,
1358 struct devx_event_subscription *sub)
1359{
1360 struct devx_event *event;
1361 struct devx_obj_event *xa_val_level2;
1362
1363 if (sub->is_cleaned)
1364 return;
1365
1366 sub->is_cleaned = 1;
1367 list_del_rcu(&sub->xa_list);
1368
1369 if (list_empty(&sub->obj_list))
1370 return;
1371
1372 list_del_rcu(&sub->obj_list);
1373 /* check whether key level 1 for this obj_sub_list is empty */
1374 event = xa_load(&dev->devx_event_table.event_xa,
1375 sub->xa_key_level1);
1376 WARN_ON(!event);
1377
1378 xa_val_level2 = xa_load(&event->object_ids, sub->xa_key_level2);
1379 if (list_empty(&xa_val_level2->obj_sub_list)) {
1380 xa_erase(&event->object_ids,
1381 sub->xa_key_level2);
1382 kfree_rcu(xa_val_level2, rcu);
1383 }
1384}
1385
1386static int devx_obj_cleanup(struct ib_uobject *uobject,
1387 enum rdma_remove_reason why,
1388 struct uverbs_attr_bundle *attrs)
1389{
1390 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
1391 struct mlx5_devx_event_table *devx_event_table;
1392 struct devx_obj *obj = uobject->object;
1393 struct devx_event_subscription *sub_entry, *tmp;
1394 struct mlx5_ib_dev *dev;
1395 int ret;
1396
1397 dev = mlx5_udata_to_mdev(&attrs->driver_udata);
1398 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY &&
1399 xa_erase(&obj->ib_dev->odp_mkeys,
1400 mlx5_base_mkey(obj->mkey.key)))
1401 /*
1402 * The pagefault_single_data_segment() does commands against
1403 * the mmkey, we must wait for that to stop before freeing the
1404 * mkey, as another allocation could get the same mkey #.
1405 */
1406 mlx5r_deref_wait_odp_mkey(&obj->mkey);
1407
1408 if (obj->flags & DEVX_OBJ_FLAGS_DCT)
1409 ret = mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct);
1410 else if (obj->flags & DEVX_OBJ_FLAGS_CQ)
1411 ret = mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq);
1412 else
1413 ret = mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox,
1414 obj->dinlen, out, sizeof(out));
1415 if (ret)
1416 return ret;
1417
1418 devx_event_table = &dev->devx_event_table;
1419
1420 mutex_lock(&devx_event_table->event_xa_lock);
1421 list_for_each_entry_safe(sub_entry, tmp, &obj->event_sub, obj_list)
1422 devx_cleanup_subscription(dev, sub_entry);
1423 mutex_unlock(&devx_event_table->event_xa_lock);
1424
1425 kfree(obj);
1426 return ret;
1427}
1428
1429static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe)
1430{
1431 struct devx_obj *obj = container_of(mcq, struct devx_obj, core_cq);
1432 struct mlx5_devx_event_table *table;
1433 struct devx_event *event;
1434 struct devx_obj_event *obj_event;
1435 u32 obj_id = mcq->cqn;
1436
1437 table = &obj->ib_dev->devx_event_table;
1438 rcu_read_lock();
1439 event = xa_load(&table->event_xa, MLX5_EVENT_TYPE_COMP);
1440 if (!event)
1441 goto out;
1442
1443 obj_event = xa_load(&event->object_ids, obj_id);
1444 if (!obj_event)
1445 goto out;
1446
1447 dispatch_event_fd(&obj_event->obj_sub_list, eqe);
1448out:
1449 rcu_read_unlock();
1450}
1451
1452static bool is_apu_cq(struct mlx5_ib_dev *dev, const void *in)
1453{
1454 if (!MLX5_CAP_GEN(dev->mdev, apu) ||
1455 !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), apu_cq))
1456 return false;
1457
1458 return true;
1459}
1460
1461static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)(
1462 struct uverbs_attr_bundle *attrs)
1463{
1464 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN);
1465 int cmd_out_len = uverbs_attr_get_len(attrs,
1466 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT);
1467 int cmd_in_len = uverbs_attr_get_len(attrs,
1468 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN);
1469 void *cmd_out;
1470 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1471 attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE);
1472 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1473 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1474 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
1475 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
1476 struct devx_obj *obj;
1477 u16 obj_type = 0;
1478 int err, err2 = 0;
1479 int uid;
1480 u32 obj_id;
1481 u16 opcode;
1482
1483 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1484 return -EINVAL;
1485
1486 uid = devx_get_uid(c, cmd_in);
1487 if (uid < 0)
1488 return uid;
1489
1490 if (!devx_is_obj_create_cmd(cmd_in, &opcode))
1491 return -EINVAL;
1492
1493 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1494 if (IS_ERR(cmd_out))
1495 return PTR_ERR(cmd_out);
1496
1497 obj = kzalloc(sizeof(struct devx_obj), GFP_KERNEL);
1498 if (!obj)
1499 return -ENOMEM;
1500
1501 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1502 if (opcode == MLX5_CMD_OP_CREATE_MKEY) {
1503 err = devx_handle_mkey_create(dev, obj, cmd_in, cmd_in_len);
1504 if (err)
1505 goto obj_free;
1506 } else {
1507 devx_set_umem_valid(cmd_in);
1508 }
1509
1510 if (opcode == MLX5_CMD_OP_CREATE_DCT) {
1511 obj->flags |= DEVX_OBJ_FLAGS_DCT;
1512 err = mlx5_core_create_dct(dev, &obj->core_dct, cmd_in,
1513 cmd_in_len, cmd_out, cmd_out_len);
1514 } else if (opcode == MLX5_CMD_OP_CREATE_CQ &&
1515 !is_apu_cq(dev, cmd_in)) {
1516 obj->flags |= DEVX_OBJ_FLAGS_CQ;
1517 obj->core_cq.comp = devx_cq_comp;
1518 err = mlx5_create_cq(dev->mdev, &obj->core_cq,
1519 cmd_in, cmd_in_len, cmd_out,
1520 cmd_out_len);
1521 } else {
1522 err = mlx5_cmd_do(dev->mdev, cmd_in, cmd_in_len,
1523 cmd_out, cmd_out_len);
1524 }
1525
1526 if (err == -EREMOTEIO)
1527 err2 = uverbs_copy_to(attrs,
1528 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT,
1529 cmd_out, cmd_out_len);
1530 if (err)
1531 goto obj_free;
1532
1533 if (opcode == MLX5_CMD_OP_ALLOC_FLOW_COUNTER) {
1534 u32 bulk = MLX5_GET(alloc_flow_counter_in,
1535 cmd_in,
1536 flow_counter_bulk_log_size);
1537
1538 if (bulk)
1539 bulk = 1 << bulk;
1540 else
1541 bulk = 128UL * MLX5_GET(alloc_flow_counter_in,
1542 cmd_in,
1543 flow_counter_bulk);
1544 obj->flow_counter_bulk_size = bulk;
1545 }
1546
1547 uobj->object = obj;
1548 INIT_LIST_HEAD(&obj->event_sub);
1549 obj->ib_dev = dev;
1550 devx_obj_build_destroy_cmd(cmd_in, cmd_out, obj->dinbox, &obj->dinlen,
1551 &obj_id);
1552 WARN_ON(obj->dinlen > MLX5_MAX_DESTROY_INBOX_SIZE_DW * sizeof(u32));
1553
1554 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, cmd_out, cmd_out_len);
1555 if (err)
1556 goto obj_destroy;
1557
1558 if (opcode == MLX5_CMD_OP_CREATE_GENERAL_OBJECT)
1559 obj_type = MLX5_GET(general_obj_in_cmd_hdr, cmd_in, obj_type);
1560 obj->obj_id = get_enc_obj_id(opcode | obj_type << 16, obj_id);
1561
1562 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY) {
1563 err = devx_handle_mkey_indirect(obj, dev, cmd_in, cmd_out);
1564 if (err)
1565 goto obj_destroy;
1566 }
1567 return 0;
1568
1569obj_destroy:
1570 if (obj->flags & DEVX_OBJ_FLAGS_DCT)
1571 mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct);
1572 else if (obj->flags & DEVX_OBJ_FLAGS_CQ)
1573 mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq);
1574 else
1575 mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, obj->dinlen, out,
1576 sizeof(out));
1577obj_free:
1578 kfree(obj);
1579 return err2 ?: err;
1580}
1581
1582static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_MODIFY)(
1583 struct uverbs_attr_bundle *attrs)
1584{
1585 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN);
1586 int cmd_out_len = uverbs_attr_get_len(attrs,
1587 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT);
1588 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs,
1589 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE);
1590 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1591 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1592 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device);
1593 void *cmd_out;
1594 int err, err2;
1595 int uid;
1596
1597 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1598 return -EINVAL;
1599
1600 uid = devx_get_uid(c, cmd_in);
1601 if (uid < 0)
1602 return uid;
1603
1604 if (!devx_is_obj_modify_cmd(cmd_in))
1605 return -EINVAL;
1606
1607 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in))
1608 return -EINVAL;
1609
1610 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1611 if (IS_ERR(cmd_out))
1612 return PTR_ERR(cmd_out);
1613
1614 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1615 devx_set_umem_valid(cmd_in);
1616
1617 err = mlx5_cmd_do(mdev->mdev, cmd_in,
1618 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN),
1619 cmd_out, cmd_out_len);
1620 if (err && err != -EREMOTEIO)
1621 return err;
1622
1623 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT,
1624 cmd_out, cmd_out_len);
1625
1626 return err2 ?: err;
1627}
1628
1629static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_QUERY)(
1630 struct uverbs_attr_bundle *attrs)
1631{
1632 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN);
1633 int cmd_out_len = uverbs_attr_get_len(attrs,
1634 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT);
1635 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs,
1636 MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE);
1637 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1638 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1639 void *cmd_out;
1640 int err, err2;
1641 int uid;
1642 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device);
1643
1644 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1645 return -EINVAL;
1646
1647 uid = devx_get_uid(c, cmd_in);
1648 if (uid < 0)
1649 return uid;
1650
1651 if (!devx_is_obj_query_cmd(cmd_in))
1652 return -EINVAL;
1653
1654 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in))
1655 return -EINVAL;
1656
1657 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1658 if (IS_ERR(cmd_out))
1659 return PTR_ERR(cmd_out);
1660
1661 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1662 err = mlx5_cmd_do(mdev->mdev, cmd_in,
1663 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN),
1664 cmd_out, cmd_out_len);
1665 if (err && err != -EREMOTEIO)
1666 return err;
1667
1668 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT,
1669 cmd_out, cmd_out_len);
1670
1671 return err2 ?: err;
1672}
1673
1674struct devx_async_event_queue {
1675 spinlock_t lock;
1676 wait_queue_head_t poll_wait;
1677 struct list_head event_list;
1678 atomic_t bytes_in_use;
1679 u8 is_destroyed:1;
1680};
1681
1682struct devx_async_cmd_event_file {
1683 struct ib_uobject uobj;
1684 struct devx_async_event_queue ev_queue;
1685 struct mlx5_async_ctx async_ctx;
1686};
1687
1688static void devx_init_event_queue(struct devx_async_event_queue *ev_queue)
1689{
1690 spin_lock_init(&ev_queue->lock);
1691 INIT_LIST_HEAD(&ev_queue->event_list);
1692 init_waitqueue_head(&ev_queue->poll_wait);
1693 atomic_set(&ev_queue->bytes_in_use, 0);
1694 ev_queue->is_destroyed = 0;
1695}
1696
1697static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)(
1698 struct uverbs_attr_bundle *attrs)
1699{
1700 struct devx_async_cmd_event_file *ev_file;
1701
1702 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1703 attrs, MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE);
1704 struct mlx5_ib_dev *mdev = mlx5_udata_to_mdev(&attrs->driver_udata);
1705
1706 ev_file = container_of(uobj, struct devx_async_cmd_event_file,
1707 uobj);
1708 devx_init_event_queue(&ev_file->ev_queue);
1709 mlx5_cmd_init_async_ctx(mdev->mdev, &ev_file->async_ctx);
1710 return 0;
1711}
1712
1713static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)(
1714 struct uverbs_attr_bundle *attrs)
1715{
1716 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1717 attrs, MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE);
1718 struct devx_async_event_file *ev_file;
1719 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1720 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1721 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
1722 u32 flags;
1723 int err;
1724
1725 err = uverbs_get_flags32(&flags, attrs,
1726 MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS,
1727 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA);
1728
1729 if (err)
1730 return err;
1731
1732 ev_file = container_of(uobj, struct devx_async_event_file,
1733 uobj);
1734 spin_lock_init(&ev_file->lock);
1735 INIT_LIST_HEAD(&ev_file->event_list);
1736 init_waitqueue_head(&ev_file->poll_wait);
1737 if (flags & MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA)
1738 ev_file->omit_data = 1;
1739 INIT_LIST_HEAD(&ev_file->subscribed_events_list);
1740 ev_file->dev = dev;
1741 get_device(&dev->ib_dev.dev);
1742 return 0;
1743}
1744
1745static void devx_query_callback(int status, struct mlx5_async_work *context)
1746{
1747 struct devx_async_data *async_data =
1748 container_of(context, struct devx_async_data, cb_work);
1749 struct devx_async_cmd_event_file *ev_file = async_data->ev_file;
1750 struct devx_async_event_queue *ev_queue = &ev_file->ev_queue;
1751 unsigned long flags;
1752
1753 /*
1754 * Note that if the struct devx_async_cmd_event_file uobj begins to be
1755 * destroyed it will block at mlx5_cmd_cleanup_async_ctx() until this
1756 * routine returns, ensuring that it always remains valid here.
1757 */
1758 spin_lock_irqsave(&ev_queue->lock, flags);
1759 list_add_tail(&async_data->list, &ev_queue->event_list);
1760 spin_unlock_irqrestore(&ev_queue->lock, flags);
1761
1762 wake_up_interruptible(&ev_queue->poll_wait);
1763}
1764
1765#define MAX_ASYNC_BYTES_IN_USE (1024 * 1024) /* 1MB */
1766
1767static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)(
1768 struct uverbs_attr_bundle *attrs)
1769{
1770 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs,
1771 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN);
1772 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1773 attrs,
1774 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE);
1775 u16 cmd_out_len;
1776 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1777 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1778 struct ib_uobject *fd_uobj;
1779 int err;
1780 int uid;
1781 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device);
1782 struct devx_async_cmd_event_file *ev_file;
1783 struct devx_async_data *async_data;
1784
1785 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1786 return -EINVAL;
1787
1788 uid = devx_get_uid(c, cmd_in);
1789 if (uid < 0)
1790 return uid;
1791
1792 if (!devx_is_obj_query_cmd(cmd_in))
1793 return -EINVAL;
1794
1795 err = uverbs_get_const(&cmd_out_len, attrs,
1796 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN);
1797 if (err)
1798 return err;
1799
1800 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in))
1801 return -EINVAL;
1802
1803 fd_uobj = uverbs_attr_get_uobject(attrs,
1804 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD);
1805 if (IS_ERR(fd_uobj))
1806 return PTR_ERR(fd_uobj);
1807
1808 ev_file = container_of(fd_uobj, struct devx_async_cmd_event_file,
1809 uobj);
1810
1811 if (atomic_add_return(cmd_out_len, &ev_file->ev_queue.bytes_in_use) >
1812 MAX_ASYNC_BYTES_IN_USE) {
1813 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use);
1814 return -EAGAIN;
1815 }
1816
1817 async_data = kvzalloc(struct_size(async_data, hdr.out_data,
1818 cmd_out_len), GFP_KERNEL);
1819 if (!async_data) {
1820 err = -ENOMEM;
1821 goto sub_bytes;
1822 }
1823
1824 err = uverbs_copy_from(&async_data->hdr.wr_id, attrs,
1825 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID);
1826 if (err)
1827 goto free_async;
1828
1829 async_data->cmd_out_len = cmd_out_len;
1830 async_data->mdev = mdev;
1831 async_data->ev_file = ev_file;
1832
1833 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1834 err = mlx5_cmd_exec_cb(&ev_file->async_ctx, cmd_in,
1835 uverbs_attr_get_len(attrs,
1836 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN),
1837 async_data->hdr.out_data,
1838 async_data->cmd_out_len,
1839 devx_query_callback, &async_data->cb_work);
1840
1841 if (err)
1842 goto free_async;
1843
1844 return 0;
1845
1846free_async:
1847 kvfree(async_data);
1848sub_bytes:
1849 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use);
1850 return err;
1851}
1852
1853static void
1854subscribe_event_xa_dealloc(struct mlx5_devx_event_table *devx_event_table,
1855 u32 key_level1,
1856 bool is_level2,
1857 u32 key_level2)
1858{
1859 struct devx_event *event;
1860 struct devx_obj_event *xa_val_level2;
1861
1862 /* Level 1 is valid for future use, no need to free */
1863 if (!is_level2)
1864 return;
1865
1866 event = xa_load(&devx_event_table->event_xa, key_level1);
1867 WARN_ON(!event);
1868
1869 xa_val_level2 = xa_load(&event->object_ids,
1870 key_level2);
1871 if (list_empty(&xa_val_level2->obj_sub_list)) {
1872 xa_erase(&event->object_ids,
1873 key_level2);
1874 kfree_rcu(xa_val_level2, rcu);
1875 }
1876}
1877
1878static int
1879subscribe_event_xa_alloc(struct mlx5_devx_event_table *devx_event_table,
1880 u32 key_level1,
1881 bool is_level2,
1882 u32 key_level2)
1883{
1884 struct devx_obj_event *obj_event;
1885 struct devx_event *event;
1886 int err;
1887
1888 event = xa_load(&devx_event_table->event_xa, key_level1);
1889 if (!event) {
1890 event = kzalloc(sizeof(*event), GFP_KERNEL);
1891 if (!event)
1892 return -ENOMEM;
1893
1894 INIT_LIST_HEAD(&event->unaffiliated_list);
1895 xa_init(&event->object_ids);
1896
1897 err = xa_insert(&devx_event_table->event_xa,
1898 key_level1,
1899 event,
1900 GFP_KERNEL);
1901 if (err) {
1902 kfree(event);
1903 return err;
1904 }
1905 }
1906
1907 if (!is_level2)
1908 return 0;
1909
1910 obj_event = xa_load(&event->object_ids, key_level2);
1911 if (!obj_event) {
1912 obj_event = kzalloc(sizeof(*obj_event), GFP_KERNEL);
1913 if (!obj_event)
1914 /* Level1 is valid for future use, no need to free */
1915 return -ENOMEM;
1916
1917 err = xa_insert(&event->object_ids,
1918 key_level2,
1919 obj_event,
1920 GFP_KERNEL);
1921 if (err) {
1922 kfree(obj_event);
1923 return err;
1924 }
1925 INIT_LIST_HEAD(&obj_event->obj_sub_list);
1926 }
1927
1928 return 0;
1929}
1930
1931static bool is_valid_events_legacy(int num_events, u16 *event_type_num_list,
1932 struct devx_obj *obj)
1933{
1934 int i;
1935
1936 for (i = 0; i < num_events; i++) {
1937 if (obj) {
1938 if (!is_legacy_obj_event_num(event_type_num_list[i]))
1939 return false;
1940 } else if (!is_legacy_unaffiliated_event_num(
1941 event_type_num_list[i])) {
1942 return false;
1943 }
1944 }
1945
1946 return true;
1947}
1948
1949#define MAX_SUPP_EVENT_NUM 255
1950static bool is_valid_events(struct mlx5_core_dev *dev,
1951 int num_events, u16 *event_type_num_list,
1952 struct devx_obj *obj)
1953{
1954 __be64 *aff_events;
1955 __be64 *unaff_events;
1956 int mask_entry;
1957 int mask_bit;
1958 int i;
1959
1960 if (MLX5_CAP_GEN(dev, event_cap)) {
1961 aff_events = MLX5_CAP_DEV_EVENT(dev,
1962 user_affiliated_events);
1963 unaff_events = MLX5_CAP_DEV_EVENT(dev,
1964 user_unaffiliated_events);
1965 } else {
1966 return is_valid_events_legacy(num_events, event_type_num_list,
1967 obj);
1968 }
1969
1970 for (i = 0; i < num_events; i++) {
1971 if (event_type_num_list[i] > MAX_SUPP_EVENT_NUM)
1972 return false;
1973
1974 mask_entry = event_type_num_list[i] / 64;
1975 mask_bit = event_type_num_list[i] % 64;
1976
1977 if (obj) {
1978 /* CQ completion */
1979 if (event_type_num_list[i] == 0)
1980 continue;
1981
1982 if (!(be64_to_cpu(aff_events[mask_entry]) &
1983 (1ull << mask_bit)))
1984 return false;
1985
1986 continue;
1987 }
1988
1989 if (!(be64_to_cpu(unaff_events[mask_entry]) &
1990 (1ull << mask_bit)))
1991 return false;
1992 }
1993
1994 return true;
1995}
1996
1997#define MAX_NUM_EVENTS 16
1998static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)(
1999 struct uverbs_attr_bundle *attrs)
2000{
2001 struct ib_uobject *devx_uobj = uverbs_attr_get_uobject(
2002 attrs,
2003 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE);
2004 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
2005 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2006 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
2007 struct ib_uobject *fd_uobj;
2008 struct devx_obj *obj = NULL;
2009 struct devx_async_event_file *ev_file;
2010 struct mlx5_devx_event_table *devx_event_table = &dev->devx_event_table;
2011 u16 *event_type_num_list;
2012 struct devx_event_subscription *event_sub, *tmp_sub;
2013 struct list_head sub_list;
2014 int redirect_fd;
2015 bool use_eventfd = false;
2016 int num_events;
2017 u16 obj_type = 0;
2018 u64 cookie = 0;
2019 u32 obj_id = 0;
2020 int err;
2021 int i;
2022
2023 if (!c->devx_uid)
2024 return -EINVAL;
2025
2026 if (!IS_ERR(devx_uobj)) {
2027 obj = (struct devx_obj *)devx_uobj->object;
2028 if (obj)
2029 obj_id = get_dec_obj_id(obj->obj_id);
2030 }
2031
2032 fd_uobj = uverbs_attr_get_uobject(attrs,
2033 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE);
2034 if (IS_ERR(fd_uobj))
2035 return PTR_ERR(fd_uobj);
2036
2037 ev_file = container_of(fd_uobj, struct devx_async_event_file,
2038 uobj);
2039
2040 if (uverbs_attr_is_valid(attrs,
2041 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM)) {
2042 err = uverbs_copy_from(&redirect_fd, attrs,
2043 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM);
2044 if (err)
2045 return err;
2046
2047 use_eventfd = true;
2048 }
2049
2050 if (uverbs_attr_is_valid(attrs,
2051 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE)) {
2052 if (use_eventfd)
2053 return -EINVAL;
2054
2055 err = uverbs_copy_from(&cookie, attrs,
2056 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE);
2057 if (err)
2058 return err;
2059 }
2060
2061 num_events = uverbs_attr_ptr_get_array_size(
2062 attrs, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST,
2063 sizeof(u16));
2064
2065 if (num_events < 0)
2066 return num_events;
2067
2068 if (num_events > MAX_NUM_EVENTS)
2069 return -EINVAL;
2070
2071 event_type_num_list = uverbs_attr_get_alloced_ptr(attrs,
2072 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST);
2073
2074 if (!is_valid_events(dev->mdev, num_events, event_type_num_list, obj))
2075 return -EINVAL;
2076
2077 INIT_LIST_HEAD(&sub_list);
2078
2079 /* Protect from concurrent subscriptions to same XA entries to allow
2080 * both to succeed
2081 */
2082 mutex_lock(&devx_event_table->event_xa_lock);
2083 for (i = 0; i < num_events; i++) {
2084 u32 key_level1;
2085
2086 if (obj)
2087 obj_type = get_dec_obj_type(obj,
2088 event_type_num_list[i]);
2089 key_level1 = event_type_num_list[i] | obj_type << 16;
2090
2091 err = subscribe_event_xa_alloc(devx_event_table,
2092 key_level1,
2093 obj,
2094 obj_id);
2095 if (err)
2096 goto err;
2097
2098 event_sub = kzalloc(sizeof(*event_sub), GFP_KERNEL);
2099 if (!event_sub) {
2100 err = -ENOMEM;
2101 goto err;
2102 }
2103
2104 list_add_tail(&event_sub->event_list, &sub_list);
2105 uverbs_uobject_get(&ev_file->uobj);
2106 if (use_eventfd) {
2107 event_sub->eventfd =
2108 eventfd_ctx_fdget(redirect_fd);
2109
2110 if (IS_ERR(event_sub->eventfd)) {
2111 err = PTR_ERR(event_sub->eventfd);
2112 event_sub->eventfd = NULL;
2113 goto err;
2114 }
2115 }
2116
2117 event_sub->cookie = cookie;
2118 event_sub->ev_file = ev_file;
2119 /* May be needed upon cleanup the devx object/subscription */
2120 event_sub->xa_key_level1 = key_level1;
2121 event_sub->xa_key_level2 = obj_id;
2122 INIT_LIST_HEAD(&event_sub->obj_list);
2123 }
2124
2125 /* Once all the allocations and the XA data insertions were done we
2126 * can go ahead and add all the subscriptions to the relevant lists
2127 * without concern of a failure.
2128 */
2129 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) {
2130 struct devx_event *event;
2131 struct devx_obj_event *obj_event;
2132
2133 list_del_init(&event_sub->event_list);
2134
2135 spin_lock_irq(&ev_file->lock);
2136 list_add_tail_rcu(&event_sub->file_list,
2137 &ev_file->subscribed_events_list);
2138 spin_unlock_irq(&ev_file->lock);
2139
2140 event = xa_load(&devx_event_table->event_xa,
2141 event_sub->xa_key_level1);
2142 WARN_ON(!event);
2143
2144 if (!obj) {
2145 list_add_tail_rcu(&event_sub->xa_list,
2146 &event->unaffiliated_list);
2147 continue;
2148 }
2149
2150 obj_event = xa_load(&event->object_ids, obj_id);
2151 WARN_ON(!obj_event);
2152 list_add_tail_rcu(&event_sub->xa_list,
2153 &obj_event->obj_sub_list);
2154 list_add_tail_rcu(&event_sub->obj_list,
2155 &obj->event_sub);
2156 }
2157
2158 mutex_unlock(&devx_event_table->event_xa_lock);
2159 return 0;
2160
2161err:
2162 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) {
2163 list_del(&event_sub->event_list);
2164
2165 subscribe_event_xa_dealloc(devx_event_table,
2166 event_sub->xa_key_level1,
2167 obj,
2168 obj_id);
2169
2170 if (event_sub->eventfd)
2171 eventfd_ctx_put(event_sub->eventfd);
2172 uverbs_uobject_put(&event_sub->ev_file->uobj);
2173 kfree(event_sub);
2174 }
2175
2176 mutex_unlock(&devx_event_table->event_xa_lock);
2177 return err;
2178}
2179
2180static int devx_umem_get(struct mlx5_ib_dev *dev, struct ib_ucontext *ucontext,
2181 struct uverbs_attr_bundle *attrs,
2182 struct devx_umem *obj, u32 access_flags)
2183{
2184 u64 addr;
2185 size_t size;
2186 int err;
2187
2188 if (uverbs_copy_from(&addr, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR) ||
2189 uverbs_copy_from(&size, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_LEN))
2190 return -EFAULT;
2191
2192 err = ib_check_mr_access(&dev->ib_dev, access_flags);
2193 if (err)
2194 return err;
2195
2196 if (uverbs_attr_is_valid(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD)) {
2197 struct ib_umem_dmabuf *umem_dmabuf;
2198 int dmabuf_fd;
2199
2200 err = uverbs_get_raw_fd(&dmabuf_fd, attrs,
2201 MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD);
2202 if (err)
2203 return -EFAULT;
2204
2205 umem_dmabuf = ib_umem_dmabuf_get_pinned(
2206 &dev->ib_dev, addr, size, dmabuf_fd, access_flags);
2207 if (IS_ERR(umem_dmabuf))
2208 return PTR_ERR(umem_dmabuf);
2209 obj->umem = &umem_dmabuf->umem;
2210 } else {
2211 obj->umem = ib_umem_get(&dev->ib_dev, addr, size, access_flags);
2212 if (IS_ERR(obj->umem))
2213 return PTR_ERR(obj->umem);
2214 }
2215 return 0;
2216}
2217
2218static unsigned int devx_umem_find_best_pgsize(struct ib_umem *umem,
2219 unsigned long pgsz_bitmap)
2220{
2221 unsigned long page_size;
2222
2223 /* Don't bother checking larger page sizes as offset must be zero and
2224 * total DEVX umem length must be equal to total umem length.
2225 */
2226 pgsz_bitmap &= GENMASK_ULL(max_t(u64, order_base_2(umem->length),
2227 PAGE_SHIFT),
2228 MLX5_ADAPTER_PAGE_SHIFT);
2229 if (!pgsz_bitmap)
2230 return 0;
2231
2232 page_size = ib_umem_find_best_pgoff(umem, pgsz_bitmap, U64_MAX);
2233 if (!page_size)
2234 return 0;
2235
2236 /* If the page_size is less than the CPU page size then we can use the
2237 * offset and create a umem which is a subset of the page list.
2238 * For larger page sizes we can't be sure the DMA list reflects the
2239 * VA so we must ensure that the umem extent is exactly equal to the
2240 * page list. Reduce the page size until one of these cases is true.
2241 */
2242 while ((ib_umem_dma_offset(umem, page_size) != 0 ||
2243 (umem->length % page_size) != 0) &&
2244 page_size > PAGE_SIZE)
2245 page_size /= 2;
2246
2247 return page_size;
2248}
2249
2250static int devx_umem_reg_cmd_alloc(struct mlx5_ib_dev *dev,
2251 struct uverbs_attr_bundle *attrs,
2252 struct devx_umem *obj,
2253 struct devx_umem_reg_cmd *cmd,
2254 int access)
2255{
2256 unsigned long pgsz_bitmap;
2257 unsigned int page_size;
2258 __be64 *mtt;
2259 void *umem;
2260 int ret;
2261
2262 /*
2263 * If the user does not pass in pgsz_bitmap then the user promises not
2264 * to use umem_offset!=0 in any commands that allocate on top of the
2265 * umem.
2266 *
2267 * If the user wants to use a umem_offset then it must pass in
2268 * pgsz_bitmap which guides the maximum page size and thus maximum
2269 * object alignment inside the umem. See the PRM.
2270 *
2271 * Users are not allowed to use IOVA here, mkeys are not supported on
2272 * umem.
2273 */
2274 ret = uverbs_get_const_default(&pgsz_bitmap, attrs,
2275 MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP,
2276 GENMASK_ULL(63,
2277 min(PAGE_SHIFT, MLX5_ADAPTER_PAGE_SHIFT)));
2278 if (ret)
2279 return ret;
2280
2281 page_size = devx_umem_find_best_pgsize(obj->umem, pgsz_bitmap);
2282 if (!page_size)
2283 return -EINVAL;
2284
2285 cmd->inlen = MLX5_ST_SZ_BYTES(create_umem_in) +
2286 (MLX5_ST_SZ_BYTES(mtt) *
2287 ib_umem_num_dma_blocks(obj->umem, page_size));
2288 cmd->in = uverbs_zalloc(attrs, cmd->inlen);
2289 if (IS_ERR(cmd->in))
2290 return PTR_ERR(cmd->in);
2291
2292 umem = MLX5_ADDR_OF(create_umem_in, cmd->in, umem);
2293 mtt = (__be64 *)MLX5_ADDR_OF(umem, umem, mtt);
2294
2295 MLX5_SET(create_umem_in, cmd->in, opcode, MLX5_CMD_OP_CREATE_UMEM);
2296 MLX5_SET64(umem, umem, num_of_mtt,
2297 ib_umem_num_dma_blocks(obj->umem, page_size));
2298 MLX5_SET(umem, umem, log_page_size,
2299 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT);
2300 MLX5_SET(umem, umem, page_offset,
2301 ib_umem_dma_offset(obj->umem, page_size));
2302
2303 if (mlx5_umem_needs_ats(dev, obj->umem, access))
2304 MLX5_SET(umem, umem, ats, 1);
2305
2306 mlx5_ib_populate_pas(obj->umem, page_size, mtt,
2307 (obj->umem->writable ? MLX5_IB_MTT_WRITE : 0) |
2308 MLX5_IB_MTT_READ);
2309 return 0;
2310}
2311
2312static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_UMEM_REG)(
2313 struct uverbs_attr_bundle *attrs)
2314{
2315 struct devx_umem_reg_cmd cmd;
2316 struct devx_umem *obj;
2317 struct ib_uobject *uobj = uverbs_attr_get_uobject(
2318 attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE);
2319 u32 obj_id;
2320 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
2321 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2322 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
2323 int access_flags;
2324 int err;
2325
2326 if (!c->devx_uid)
2327 return -EINVAL;
2328
2329 err = uverbs_get_flags32(&access_flags, attrs,
2330 MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS,
2331 IB_ACCESS_LOCAL_WRITE |
2332 IB_ACCESS_REMOTE_WRITE |
2333 IB_ACCESS_REMOTE_READ |
2334 IB_ACCESS_RELAXED_ORDERING);
2335 if (err)
2336 return err;
2337
2338 obj = kzalloc(sizeof(struct devx_umem), GFP_KERNEL);
2339 if (!obj)
2340 return -ENOMEM;
2341
2342 err = devx_umem_get(dev, &c->ibucontext, attrs, obj, access_flags);
2343 if (err)
2344 goto err_obj_free;
2345
2346 err = devx_umem_reg_cmd_alloc(dev, attrs, obj, &cmd, access_flags);
2347 if (err)
2348 goto err_umem_release;
2349
2350 MLX5_SET(create_umem_in, cmd.in, uid, c->devx_uid);
2351 err = mlx5_cmd_exec(dev->mdev, cmd.in, cmd.inlen, cmd.out,
2352 sizeof(cmd.out));
2353 if (err)
2354 goto err_umem_release;
2355
2356 obj->mdev = dev->mdev;
2357 uobj->object = obj;
2358 devx_obj_build_destroy_cmd(cmd.in, cmd.out, obj->dinbox, &obj->dinlen, &obj_id);
2359 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE);
2360
2361 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, &obj_id,
2362 sizeof(obj_id));
2363 return err;
2364
2365err_umem_release:
2366 ib_umem_release(obj->umem);
2367err_obj_free:
2368 kfree(obj);
2369 return err;
2370}
2371
2372static int devx_umem_cleanup(struct ib_uobject *uobject,
2373 enum rdma_remove_reason why,
2374 struct uverbs_attr_bundle *attrs)
2375{
2376 struct devx_umem *obj = uobject->object;
2377 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2378 int err;
2379
2380 err = mlx5_cmd_exec(obj->mdev, obj->dinbox, obj->dinlen, out, sizeof(out));
2381 if (err)
2382 return err;
2383
2384 ib_umem_release(obj->umem);
2385 kfree(obj);
2386 return 0;
2387}
2388
2389static bool is_unaffiliated_event(struct mlx5_core_dev *dev,
2390 unsigned long event_type)
2391{
2392 __be64 *unaff_events;
2393 int mask_entry;
2394 int mask_bit;
2395
2396 if (!MLX5_CAP_GEN(dev, event_cap))
2397 return is_legacy_unaffiliated_event_num(event_type);
2398
2399 unaff_events = MLX5_CAP_DEV_EVENT(dev,
2400 user_unaffiliated_events);
2401 WARN_ON(event_type > MAX_SUPP_EVENT_NUM);
2402
2403 mask_entry = event_type / 64;
2404 mask_bit = event_type % 64;
2405
2406 if (!(be64_to_cpu(unaff_events[mask_entry]) & (1ull << mask_bit)))
2407 return false;
2408
2409 return true;
2410}
2411
2412static u32 devx_get_obj_id_from_event(unsigned long event_type, void *data)
2413{
2414 struct mlx5_eqe *eqe = data;
2415 u32 obj_id = 0;
2416
2417 switch (event_type) {
2418 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
2419 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
2420 case MLX5_EVENT_TYPE_PATH_MIG:
2421 case MLX5_EVENT_TYPE_COMM_EST:
2422 case MLX5_EVENT_TYPE_SQ_DRAINED:
2423 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
2424 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
2425 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
2426 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
2427 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
2428 obj_id = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
2429 break;
2430 case MLX5_EVENT_TYPE_XRQ_ERROR:
2431 obj_id = be32_to_cpu(eqe->data.xrq_err.type_xrqn) & 0xffffff;
2432 break;
2433 case MLX5_EVENT_TYPE_DCT_DRAINED:
2434 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION:
2435 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
2436 break;
2437 case MLX5_EVENT_TYPE_CQ_ERROR:
2438 obj_id = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
2439 break;
2440 default:
2441 obj_id = MLX5_GET(affiliated_event_header, &eqe->data, obj_id);
2442 break;
2443 }
2444
2445 return obj_id;
2446}
2447
2448static int deliver_event(struct devx_event_subscription *event_sub,
2449 const void *data)
2450{
2451 struct devx_async_event_file *ev_file;
2452 struct devx_async_event_data *event_data;
2453 unsigned long flags;
2454
2455 ev_file = event_sub->ev_file;
2456
2457 if (ev_file->omit_data) {
2458 spin_lock_irqsave(&ev_file->lock, flags);
2459 if (!list_empty(&event_sub->event_list) ||
2460 ev_file->is_destroyed) {
2461 spin_unlock_irqrestore(&ev_file->lock, flags);
2462 return 0;
2463 }
2464
2465 list_add_tail(&event_sub->event_list, &ev_file->event_list);
2466 spin_unlock_irqrestore(&ev_file->lock, flags);
2467 wake_up_interruptible(&ev_file->poll_wait);
2468 return 0;
2469 }
2470
2471 event_data = kzalloc(sizeof(*event_data) + sizeof(struct mlx5_eqe),
2472 GFP_ATOMIC);
2473 if (!event_data) {
2474 spin_lock_irqsave(&ev_file->lock, flags);
2475 ev_file->is_overflow_err = 1;
2476 spin_unlock_irqrestore(&ev_file->lock, flags);
2477 return -ENOMEM;
2478 }
2479
2480 event_data->hdr.cookie = event_sub->cookie;
2481 memcpy(event_data->hdr.out_data, data, sizeof(struct mlx5_eqe));
2482
2483 spin_lock_irqsave(&ev_file->lock, flags);
2484 if (!ev_file->is_destroyed)
2485 list_add_tail(&event_data->list, &ev_file->event_list);
2486 else
2487 kfree(event_data);
2488 spin_unlock_irqrestore(&ev_file->lock, flags);
2489 wake_up_interruptible(&ev_file->poll_wait);
2490
2491 return 0;
2492}
2493
2494static void dispatch_event_fd(struct list_head *fd_list,
2495 const void *data)
2496{
2497 struct devx_event_subscription *item;
2498
2499 list_for_each_entry_rcu(item, fd_list, xa_list) {
2500 if (item->eventfd)
2501 eventfd_signal(item->eventfd);
2502 else
2503 deliver_event(item, data);
2504 }
2505}
2506
2507static int devx_event_notifier(struct notifier_block *nb,
2508 unsigned long event_type, void *data)
2509{
2510 struct mlx5_devx_event_table *table;
2511 struct mlx5_ib_dev *dev;
2512 struct devx_event *event;
2513 struct devx_obj_event *obj_event;
2514 u16 obj_type = 0;
2515 bool is_unaffiliated;
2516 u32 obj_id;
2517
2518 /* Explicit filtering to kernel events which may occur frequently */
2519 if (event_type == MLX5_EVENT_TYPE_CMD ||
2520 event_type == MLX5_EVENT_TYPE_PAGE_REQUEST)
2521 return NOTIFY_OK;
2522
2523 table = container_of(nb, struct mlx5_devx_event_table, devx_nb.nb);
2524 dev = container_of(table, struct mlx5_ib_dev, devx_event_table);
2525 is_unaffiliated = is_unaffiliated_event(dev->mdev, event_type);
2526
2527 if (!is_unaffiliated)
2528 obj_type = get_event_obj_type(event_type, data);
2529
2530 rcu_read_lock();
2531 event = xa_load(&table->event_xa, event_type | (obj_type << 16));
2532 if (!event) {
2533 rcu_read_unlock();
2534 return NOTIFY_DONE;
2535 }
2536
2537 if (is_unaffiliated) {
2538 dispatch_event_fd(&event->unaffiliated_list, data);
2539 rcu_read_unlock();
2540 return NOTIFY_OK;
2541 }
2542
2543 obj_id = devx_get_obj_id_from_event(event_type, data);
2544 obj_event = xa_load(&event->object_ids, obj_id);
2545 if (!obj_event) {
2546 rcu_read_unlock();
2547 return NOTIFY_DONE;
2548 }
2549
2550 dispatch_event_fd(&obj_event->obj_sub_list, data);
2551
2552 rcu_read_unlock();
2553 return NOTIFY_OK;
2554}
2555
2556int mlx5_ib_devx_init(struct mlx5_ib_dev *dev)
2557{
2558 struct mlx5_devx_event_table *table = &dev->devx_event_table;
2559 int uid;
2560
2561 uid = mlx5_ib_devx_create(dev, false);
2562 if (uid > 0) {
2563 dev->devx_whitelist_uid = uid;
2564 xa_init(&table->event_xa);
2565 mutex_init(&table->event_xa_lock);
2566 MLX5_NB_INIT(&table->devx_nb, devx_event_notifier, NOTIFY_ANY);
2567 mlx5_eq_notifier_register(dev->mdev, &table->devx_nb);
2568 }
2569
2570 return 0;
2571}
2572
2573void mlx5_ib_devx_cleanup(struct mlx5_ib_dev *dev)
2574{
2575 struct mlx5_devx_event_table *table = &dev->devx_event_table;
2576 struct devx_event_subscription *sub, *tmp;
2577 struct devx_event *event;
2578 void *entry;
2579 unsigned long id;
2580
2581 if (dev->devx_whitelist_uid) {
2582 mlx5_eq_notifier_unregister(dev->mdev, &table->devx_nb);
2583 mutex_lock(&dev->devx_event_table.event_xa_lock);
2584 xa_for_each(&table->event_xa, id, entry) {
2585 event = entry;
2586 list_for_each_entry_safe(
2587 sub, tmp, &event->unaffiliated_list, xa_list)
2588 devx_cleanup_subscription(dev, sub);
2589 kfree(entry);
2590 }
2591 mutex_unlock(&dev->devx_event_table.event_xa_lock);
2592 xa_destroy(&table->event_xa);
2593
2594 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
2595 }
2596}
2597
2598static ssize_t devx_async_cmd_event_read(struct file *filp, char __user *buf,
2599 size_t count, loff_t *pos)
2600{
2601 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data;
2602 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue;
2603 struct devx_async_data *event;
2604 int ret = 0;
2605 size_t eventsz;
2606
2607 spin_lock_irq(&ev_queue->lock);
2608
2609 while (list_empty(&ev_queue->event_list)) {
2610 spin_unlock_irq(&ev_queue->lock);
2611
2612 if (filp->f_flags & O_NONBLOCK)
2613 return -EAGAIN;
2614
2615 if (wait_event_interruptible(
2616 ev_queue->poll_wait,
2617 (!list_empty(&ev_queue->event_list) ||
2618 ev_queue->is_destroyed))) {
2619 return -ERESTARTSYS;
2620 }
2621
2622 spin_lock_irq(&ev_queue->lock);
2623 if (ev_queue->is_destroyed) {
2624 spin_unlock_irq(&ev_queue->lock);
2625 return -EIO;
2626 }
2627 }
2628
2629 event = list_entry(ev_queue->event_list.next,
2630 struct devx_async_data, list);
2631 eventsz = event->cmd_out_len +
2632 sizeof(struct mlx5_ib_uapi_devx_async_cmd_hdr);
2633
2634 if (eventsz > count) {
2635 spin_unlock_irq(&ev_queue->lock);
2636 return -ENOSPC;
2637 }
2638
2639 list_del(ev_queue->event_list.next);
2640 spin_unlock_irq(&ev_queue->lock);
2641
2642 if (copy_to_user(buf, &event->hdr, eventsz))
2643 ret = -EFAULT;
2644 else
2645 ret = eventsz;
2646
2647 atomic_sub(event->cmd_out_len, &ev_queue->bytes_in_use);
2648 kvfree(event);
2649 return ret;
2650}
2651
2652static __poll_t devx_async_cmd_event_poll(struct file *filp,
2653 struct poll_table_struct *wait)
2654{
2655 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data;
2656 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue;
2657 __poll_t pollflags = 0;
2658
2659 poll_wait(filp, &ev_queue->poll_wait, wait);
2660
2661 spin_lock_irq(&ev_queue->lock);
2662 if (ev_queue->is_destroyed)
2663 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP;
2664 else if (!list_empty(&ev_queue->event_list))
2665 pollflags = EPOLLIN | EPOLLRDNORM;
2666 spin_unlock_irq(&ev_queue->lock);
2667
2668 return pollflags;
2669}
2670
2671static const struct file_operations devx_async_cmd_event_fops = {
2672 .owner = THIS_MODULE,
2673 .read = devx_async_cmd_event_read,
2674 .poll = devx_async_cmd_event_poll,
2675 .release = uverbs_uobject_fd_release,
2676 .llseek = no_llseek,
2677};
2678
2679static ssize_t devx_async_event_read(struct file *filp, char __user *buf,
2680 size_t count, loff_t *pos)
2681{
2682 struct devx_async_event_file *ev_file = filp->private_data;
2683 struct devx_event_subscription *event_sub;
2684 struct devx_async_event_data *event;
2685 int ret = 0;
2686 size_t eventsz;
2687 bool omit_data;
2688 void *event_data;
2689
2690 omit_data = ev_file->omit_data;
2691
2692 spin_lock_irq(&ev_file->lock);
2693
2694 if (ev_file->is_overflow_err) {
2695 ev_file->is_overflow_err = 0;
2696 spin_unlock_irq(&ev_file->lock);
2697 return -EOVERFLOW;
2698 }
2699
2700
2701 while (list_empty(&ev_file->event_list)) {
2702 spin_unlock_irq(&ev_file->lock);
2703
2704 if (filp->f_flags & O_NONBLOCK)
2705 return -EAGAIN;
2706
2707 if (wait_event_interruptible(ev_file->poll_wait,
2708 (!list_empty(&ev_file->event_list) ||
2709 ev_file->is_destroyed))) {
2710 return -ERESTARTSYS;
2711 }
2712
2713 spin_lock_irq(&ev_file->lock);
2714 if (ev_file->is_destroyed) {
2715 spin_unlock_irq(&ev_file->lock);
2716 return -EIO;
2717 }
2718 }
2719
2720 if (omit_data) {
2721 event_sub = list_first_entry(&ev_file->event_list,
2722 struct devx_event_subscription,
2723 event_list);
2724 eventsz = sizeof(event_sub->cookie);
2725 event_data = &event_sub->cookie;
2726 } else {
2727 event = list_first_entry(&ev_file->event_list,
2728 struct devx_async_event_data, list);
2729 eventsz = sizeof(struct mlx5_eqe) +
2730 sizeof(struct mlx5_ib_uapi_devx_async_event_hdr);
2731 event_data = &event->hdr;
2732 }
2733
2734 if (eventsz > count) {
2735 spin_unlock_irq(&ev_file->lock);
2736 return -EINVAL;
2737 }
2738
2739 if (omit_data)
2740 list_del_init(&event_sub->event_list);
2741 else
2742 list_del(&event->list);
2743
2744 spin_unlock_irq(&ev_file->lock);
2745
2746 if (copy_to_user(buf, event_data, eventsz))
2747 /* This points to an application issue, not a kernel concern */
2748 ret = -EFAULT;
2749 else
2750 ret = eventsz;
2751
2752 if (!omit_data)
2753 kfree(event);
2754 return ret;
2755}
2756
2757static __poll_t devx_async_event_poll(struct file *filp,
2758 struct poll_table_struct *wait)
2759{
2760 struct devx_async_event_file *ev_file = filp->private_data;
2761 __poll_t pollflags = 0;
2762
2763 poll_wait(filp, &ev_file->poll_wait, wait);
2764
2765 spin_lock_irq(&ev_file->lock);
2766 if (ev_file->is_destroyed)
2767 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP;
2768 else if (!list_empty(&ev_file->event_list))
2769 pollflags = EPOLLIN | EPOLLRDNORM;
2770 spin_unlock_irq(&ev_file->lock);
2771
2772 return pollflags;
2773}
2774
2775static void devx_free_subscription(struct rcu_head *rcu)
2776{
2777 struct devx_event_subscription *event_sub =
2778 container_of(rcu, struct devx_event_subscription, rcu);
2779
2780 if (event_sub->eventfd)
2781 eventfd_ctx_put(event_sub->eventfd);
2782 uverbs_uobject_put(&event_sub->ev_file->uobj);
2783 kfree(event_sub);
2784}
2785
2786static const struct file_operations devx_async_event_fops = {
2787 .owner = THIS_MODULE,
2788 .read = devx_async_event_read,
2789 .poll = devx_async_event_poll,
2790 .release = uverbs_uobject_fd_release,
2791 .llseek = no_llseek,
2792};
2793
2794static void devx_async_cmd_event_destroy_uobj(struct ib_uobject *uobj,
2795 enum rdma_remove_reason why)
2796{
2797 struct devx_async_cmd_event_file *comp_ev_file =
2798 container_of(uobj, struct devx_async_cmd_event_file,
2799 uobj);
2800 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue;
2801 struct devx_async_data *entry, *tmp;
2802
2803 spin_lock_irq(&ev_queue->lock);
2804 ev_queue->is_destroyed = 1;
2805 spin_unlock_irq(&ev_queue->lock);
2806 wake_up_interruptible(&ev_queue->poll_wait);
2807
2808 mlx5_cmd_cleanup_async_ctx(&comp_ev_file->async_ctx);
2809
2810 spin_lock_irq(&comp_ev_file->ev_queue.lock);
2811 list_for_each_entry_safe(entry, tmp,
2812 &comp_ev_file->ev_queue.event_list, list) {
2813 list_del(&entry->list);
2814 kvfree(entry);
2815 }
2816 spin_unlock_irq(&comp_ev_file->ev_queue.lock);
2817};
2818
2819static void devx_async_event_destroy_uobj(struct ib_uobject *uobj,
2820 enum rdma_remove_reason why)
2821{
2822 struct devx_async_event_file *ev_file =
2823 container_of(uobj, struct devx_async_event_file,
2824 uobj);
2825 struct devx_event_subscription *event_sub, *event_sub_tmp;
2826 struct mlx5_ib_dev *dev = ev_file->dev;
2827
2828 spin_lock_irq(&ev_file->lock);
2829 ev_file->is_destroyed = 1;
2830
2831 /* free the pending events allocation */
2832 if (ev_file->omit_data) {
2833 struct devx_event_subscription *event_sub, *tmp;
2834
2835 list_for_each_entry_safe(event_sub, tmp, &ev_file->event_list,
2836 event_list)
2837 list_del_init(&event_sub->event_list);
2838
2839 } else {
2840 struct devx_async_event_data *entry, *tmp;
2841
2842 list_for_each_entry_safe(entry, tmp, &ev_file->event_list,
2843 list) {
2844 list_del(&entry->list);
2845 kfree(entry);
2846 }
2847 }
2848
2849 spin_unlock_irq(&ev_file->lock);
2850 wake_up_interruptible(&ev_file->poll_wait);
2851
2852 mutex_lock(&dev->devx_event_table.event_xa_lock);
2853 /* delete the subscriptions which are related to this FD */
2854 list_for_each_entry_safe(event_sub, event_sub_tmp,
2855 &ev_file->subscribed_events_list, file_list) {
2856 devx_cleanup_subscription(dev, event_sub);
2857 list_del_rcu(&event_sub->file_list);
2858 /* subscription may not be used by the read API any more */
2859 call_rcu(&event_sub->rcu, devx_free_subscription);
2860 }
2861 mutex_unlock(&dev->devx_event_table.event_xa_lock);
2862
2863 put_device(&dev->ib_dev.dev);
2864};
2865
2866DECLARE_UVERBS_NAMED_METHOD(
2867 MLX5_IB_METHOD_DEVX_UMEM_REG,
2868 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE,
2869 MLX5_IB_OBJECT_DEVX_UMEM,
2870 UVERBS_ACCESS_NEW,
2871 UA_MANDATORY),
2872 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR,
2873 UVERBS_ATTR_TYPE(u64),
2874 UA_MANDATORY),
2875 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_LEN,
2876 UVERBS_ATTR_TYPE(u64),
2877 UA_MANDATORY),
2878 UVERBS_ATTR_RAW_FD(MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD,
2879 UA_OPTIONAL),
2880 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS,
2881 enum ib_access_flags),
2882 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP,
2883 u64),
2884 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID,
2885 UVERBS_ATTR_TYPE(u32),
2886 UA_MANDATORY));
2887
2888DECLARE_UVERBS_NAMED_METHOD_DESTROY(
2889 MLX5_IB_METHOD_DEVX_UMEM_DEREG,
2890 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE,
2891 MLX5_IB_OBJECT_DEVX_UMEM,
2892 UVERBS_ACCESS_DESTROY,
2893 UA_MANDATORY));
2894
2895DECLARE_UVERBS_NAMED_METHOD(
2896 MLX5_IB_METHOD_DEVX_QUERY_EQN,
2897 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC,
2898 UVERBS_ATTR_TYPE(u32),
2899 UA_MANDATORY),
2900 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN,
2901 UVERBS_ATTR_TYPE(u32),
2902 UA_MANDATORY));
2903
2904DECLARE_UVERBS_NAMED_METHOD(
2905 MLX5_IB_METHOD_DEVX_QUERY_UAR,
2906 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX,
2907 UVERBS_ATTR_TYPE(u32),
2908 UA_MANDATORY),
2909 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX,
2910 UVERBS_ATTR_TYPE(u32),
2911 UA_MANDATORY));
2912
2913DECLARE_UVERBS_NAMED_METHOD(
2914 MLX5_IB_METHOD_DEVX_OTHER,
2915 UVERBS_ATTR_PTR_IN(
2916 MLX5_IB_ATTR_DEVX_OTHER_CMD_IN,
2917 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
2918 UA_MANDATORY,
2919 UA_ALLOC_AND_COPY),
2920 UVERBS_ATTR_PTR_OUT(
2921 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT,
2922 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
2923 UA_MANDATORY));
2924
2925DECLARE_UVERBS_NAMED_METHOD(
2926 MLX5_IB_METHOD_DEVX_OBJ_CREATE,
2927 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE,
2928 MLX5_IB_OBJECT_DEVX_OBJ,
2929 UVERBS_ACCESS_NEW,
2930 UA_MANDATORY),
2931 UVERBS_ATTR_PTR_IN(
2932 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN,
2933 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
2934 UA_MANDATORY,
2935 UA_ALLOC_AND_COPY),
2936 UVERBS_ATTR_PTR_OUT(
2937 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT,
2938 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
2939 UA_MANDATORY));
2940
2941DECLARE_UVERBS_NAMED_METHOD_DESTROY(
2942 MLX5_IB_METHOD_DEVX_OBJ_DESTROY,
2943 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE,
2944 MLX5_IB_OBJECT_DEVX_OBJ,
2945 UVERBS_ACCESS_DESTROY,
2946 UA_MANDATORY));
2947
2948DECLARE_UVERBS_NAMED_METHOD(
2949 MLX5_IB_METHOD_DEVX_OBJ_MODIFY,
2950 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE,
2951 UVERBS_IDR_ANY_OBJECT,
2952 UVERBS_ACCESS_READ,
2953 UA_MANDATORY),
2954 UVERBS_ATTR_PTR_IN(
2955 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN,
2956 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
2957 UA_MANDATORY,
2958 UA_ALLOC_AND_COPY),
2959 UVERBS_ATTR_PTR_OUT(
2960 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT,
2961 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
2962 UA_MANDATORY));
2963
2964DECLARE_UVERBS_NAMED_METHOD(
2965 MLX5_IB_METHOD_DEVX_OBJ_QUERY,
2966 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE,
2967 UVERBS_IDR_ANY_OBJECT,
2968 UVERBS_ACCESS_READ,
2969 UA_MANDATORY),
2970 UVERBS_ATTR_PTR_IN(
2971 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN,
2972 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
2973 UA_MANDATORY,
2974 UA_ALLOC_AND_COPY),
2975 UVERBS_ATTR_PTR_OUT(
2976 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT,
2977 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
2978 UA_MANDATORY));
2979
2980DECLARE_UVERBS_NAMED_METHOD(
2981 MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY,
2982 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE,
2983 UVERBS_IDR_ANY_OBJECT,
2984 UVERBS_ACCESS_READ,
2985 UA_MANDATORY),
2986 UVERBS_ATTR_PTR_IN(
2987 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN,
2988 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
2989 UA_MANDATORY,
2990 UA_ALLOC_AND_COPY),
2991 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN,
2992 u16, UA_MANDATORY),
2993 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD,
2994 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
2995 UVERBS_ACCESS_READ,
2996 UA_MANDATORY),
2997 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID,
2998 UVERBS_ATTR_TYPE(u64),
2999 UA_MANDATORY));
3000
3001DECLARE_UVERBS_NAMED_METHOD(
3002 MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT,
3003 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE,
3004 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3005 UVERBS_ACCESS_READ,
3006 UA_MANDATORY),
3007 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE,
3008 MLX5_IB_OBJECT_DEVX_OBJ,
3009 UVERBS_ACCESS_READ,
3010 UA_OPTIONAL),
3011 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST,
3012 UVERBS_ATTR_MIN_SIZE(sizeof(u16)),
3013 UA_MANDATORY,
3014 UA_ALLOC_AND_COPY),
3015 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE,
3016 UVERBS_ATTR_TYPE(u64),
3017 UA_OPTIONAL),
3018 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM,
3019 UVERBS_ATTR_TYPE(u32),
3020 UA_OPTIONAL));
3021
3022DECLARE_UVERBS_GLOBAL_METHODS(MLX5_IB_OBJECT_DEVX,
3023 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OTHER),
3024 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_UAR),
3025 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_EQN),
3026 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT));
3027
3028DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_OBJ,
3029 UVERBS_TYPE_ALLOC_IDR(devx_obj_cleanup),
3030 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_CREATE),
3031 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_DESTROY),
3032 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_MODIFY),
3033 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_QUERY),
3034 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY));
3035
3036DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_UMEM,
3037 UVERBS_TYPE_ALLOC_IDR(devx_umem_cleanup),
3038 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_REG),
3039 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_DEREG));
3040
3041
3042DECLARE_UVERBS_NAMED_METHOD(
3043 MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC,
3044 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE,
3045 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3046 UVERBS_ACCESS_NEW,
3047 UA_MANDATORY));
3048
3049DECLARE_UVERBS_NAMED_OBJECT(
3050 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3051 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_cmd_event_file),
3052 devx_async_cmd_event_destroy_uobj,
3053 &devx_async_cmd_event_fops, "[devx_async_cmd]",
3054 O_RDONLY),
3055 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC));
3056
3057DECLARE_UVERBS_NAMED_METHOD(
3058 MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC,
3059 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE,
3060 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3061 UVERBS_ACCESS_NEW,
3062 UA_MANDATORY),
3063 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS,
3064 enum mlx5_ib_uapi_devx_create_event_channel_flags,
3065 UA_MANDATORY));
3066
3067DECLARE_UVERBS_NAMED_OBJECT(
3068 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3069 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_event_file),
3070 devx_async_event_destroy_uobj,
3071 &devx_async_event_fops, "[devx_async_event]",
3072 O_RDONLY),
3073 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC));
3074
3075static bool devx_is_supported(struct ib_device *device)
3076{
3077 struct mlx5_ib_dev *dev = to_mdev(device);
3078
3079 return MLX5_CAP_GEN(dev->mdev, log_max_uctx);
3080}
3081
3082const struct uapi_definition mlx5_ib_devx_defs[] = {
3083 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3084 MLX5_IB_OBJECT_DEVX,
3085 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3086 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3087 MLX5_IB_OBJECT_DEVX_OBJ,
3088 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3089 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3090 MLX5_IB_OBJECT_DEVX_UMEM,
3091 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3092 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3093 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3094 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3095 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3096 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3097 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3098 {},
3099};
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/*
3 * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved.
4 */
5
6#include <rdma/ib_user_verbs.h>
7#include <rdma/ib_verbs.h>
8#include <rdma/uverbs_types.h>
9#include <rdma/uverbs_ioctl.h>
10#include <rdma/mlx5_user_ioctl_cmds.h>
11#include <rdma/mlx5_user_ioctl_verbs.h>
12#include <rdma/ib_umem.h>
13#include <rdma/uverbs_std_types.h>
14#include <linux/mlx5/driver.h>
15#include <linux/mlx5/fs.h>
16#include "mlx5_ib.h"
17#include "devx.h"
18#include "qp.h"
19#include <linux/xarray.h>
20
21#define UVERBS_MODULE_NAME mlx5_ib
22#include <rdma/uverbs_named_ioctl.h>
23
24static void dispatch_event_fd(struct list_head *fd_list, const void *data);
25
26enum devx_obj_flags {
27 DEVX_OBJ_FLAGS_INDIRECT_MKEY = 1 << 0,
28 DEVX_OBJ_FLAGS_DCT = 1 << 1,
29 DEVX_OBJ_FLAGS_CQ = 1 << 2,
30 DEVX_OBJ_FLAGS_HW_FREED = 1 << 3,
31};
32
33#define MAX_ASYNC_CMDS 8
34
35struct mlx5_async_cmd {
36 struct ib_uobject *uobject;
37 void *in;
38 int in_size;
39 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
40 int err;
41 struct mlx5_async_work cb_work;
42 struct completion comp;
43};
44
45struct devx_async_data {
46 struct mlx5_ib_dev *mdev;
47 struct list_head list;
48 struct devx_async_cmd_event_file *ev_file;
49 struct mlx5_async_work cb_work;
50 u16 cmd_out_len;
51 /* must be last field in this structure */
52 struct mlx5_ib_uapi_devx_async_cmd_hdr hdr;
53};
54
55struct devx_async_event_data {
56 struct list_head list; /* headed in ev_file->event_list */
57 struct mlx5_ib_uapi_devx_async_event_hdr hdr;
58};
59
60/* first level XA value data structure */
61struct devx_event {
62 struct xarray object_ids; /* second XA level, Key = object id */
63 struct list_head unaffiliated_list;
64};
65
66/* second level XA value data structure */
67struct devx_obj_event {
68 struct rcu_head rcu;
69 struct list_head obj_sub_list;
70};
71
72struct devx_event_subscription {
73 struct list_head file_list; /* headed in ev_file->
74 * subscribed_events_list
75 */
76 struct list_head xa_list; /* headed in devx_event->unaffiliated_list or
77 * devx_obj_event->obj_sub_list
78 */
79 struct list_head obj_list; /* headed in devx_object */
80 struct list_head event_list; /* headed in ev_file->event_list or in
81 * temp list via subscription
82 */
83
84 u8 is_cleaned:1;
85 u32 xa_key_level1;
86 u32 xa_key_level2;
87 struct rcu_head rcu;
88 u64 cookie;
89 struct devx_async_event_file *ev_file;
90 struct eventfd_ctx *eventfd;
91};
92
93struct devx_async_event_file {
94 struct ib_uobject uobj;
95 /* Head of events that are subscribed to this FD */
96 struct list_head subscribed_events_list;
97 spinlock_t lock;
98 wait_queue_head_t poll_wait;
99 struct list_head event_list;
100 struct mlx5_ib_dev *dev;
101 u8 omit_data:1;
102 u8 is_overflow_err:1;
103 u8 is_destroyed:1;
104};
105
106struct devx_umem {
107 struct mlx5_core_dev *mdev;
108 struct ib_umem *umem;
109 u32 dinlen;
110 u32 dinbox[MLX5_ST_SZ_DW(destroy_umem_in)];
111};
112
113struct devx_umem_reg_cmd {
114 void *in;
115 u32 inlen;
116 u32 out[MLX5_ST_SZ_DW(create_umem_out)];
117};
118
119static struct mlx5_ib_ucontext *
120devx_ufile2uctx(const struct uverbs_attr_bundle *attrs)
121{
122 return to_mucontext(ib_uverbs_get_ucontext(attrs));
123}
124
125int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user)
126{
127 u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {};
128 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {};
129 void *uctx;
130 int err;
131 u16 uid;
132 u32 cap = 0;
133
134 /* 0 means not supported */
135 if (!MLX5_CAP_GEN(dev->mdev, log_max_uctx))
136 return -EINVAL;
137
138 uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx);
139 if (is_user && capable(CAP_NET_RAW) &&
140 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RAW_TX))
141 cap |= MLX5_UCTX_CAP_RAW_TX;
142 if (is_user && capable(CAP_SYS_RAWIO) &&
143 (MLX5_CAP_GEN(dev->mdev, uctx_cap) &
144 MLX5_UCTX_CAP_INTERNAL_DEV_RES))
145 cap |= MLX5_UCTX_CAP_INTERNAL_DEV_RES;
146
147 MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX);
148 MLX5_SET(uctx, uctx, cap, cap);
149
150 err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
151 if (err)
152 return err;
153
154 uid = MLX5_GET(create_uctx_out, out, uid);
155 return uid;
156}
157
158void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid)
159{
160 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {};
161 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {};
162
163 MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX);
164 MLX5_SET(destroy_uctx_in, in, uid, uid);
165
166 mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
167}
168
169static bool is_legacy_unaffiliated_event_num(u16 event_num)
170{
171 switch (event_num) {
172 case MLX5_EVENT_TYPE_PORT_CHANGE:
173 return true;
174 default:
175 return false;
176 }
177}
178
179static bool is_legacy_obj_event_num(u16 event_num)
180{
181 switch (event_num) {
182 case MLX5_EVENT_TYPE_PATH_MIG:
183 case MLX5_EVENT_TYPE_COMM_EST:
184 case MLX5_EVENT_TYPE_SQ_DRAINED:
185 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
186 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
187 case MLX5_EVENT_TYPE_CQ_ERROR:
188 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
189 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
190 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
191 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
192 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
193 case MLX5_EVENT_TYPE_DCT_DRAINED:
194 case MLX5_EVENT_TYPE_COMP:
195 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION:
196 case MLX5_EVENT_TYPE_XRQ_ERROR:
197 return true;
198 default:
199 return false;
200 }
201}
202
203static u16 get_legacy_obj_type(u16 opcode)
204{
205 switch (opcode) {
206 case MLX5_CMD_OP_CREATE_RQ:
207 return MLX5_EVENT_QUEUE_TYPE_RQ;
208 case MLX5_CMD_OP_CREATE_QP:
209 return MLX5_EVENT_QUEUE_TYPE_QP;
210 case MLX5_CMD_OP_CREATE_SQ:
211 return MLX5_EVENT_QUEUE_TYPE_SQ;
212 case MLX5_CMD_OP_CREATE_DCT:
213 return MLX5_EVENT_QUEUE_TYPE_DCT;
214 default:
215 return 0;
216 }
217}
218
219static u16 get_dec_obj_type(struct devx_obj *obj, u16 event_num)
220{
221 u16 opcode;
222
223 opcode = (obj->obj_id >> 32) & 0xffff;
224
225 if (is_legacy_obj_event_num(event_num))
226 return get_legacy_obj_type(opcode);
227
228 switch (opcode) {
229 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
230 return (obj->obj_id >> 48);
231 case MLX5_CMD_OP_CREATE_RQ:
232 return MLX5_OBJ_TYPE_RQ;
233 case MLX5_CMD_OP_CREATE_QP:
234 return MLX5_OBJ_TYPE_QP;
235 case MLX5_CMD_OP_CREATE_SQ:
236 return MLX5_OBJ_TYPE_SQ;
237 case MLX5_CMD_OP_CREATE_DCT:
238 return MLX5_OBJ_TYPE_DCT;
239 case MLX5_CMD_OP_CREATE_TIR:
240 return MLX5_OBJ_TYPE_TIR;
241 case MLX5_CMD_OP_CREATE_TIS:
242 return MLX5_OBJ_TYPE_TIS;
243 case MLX5_CMD_OP_CREATE_PSV:
244 return MLX5_OBJ_TYPE_PSV;
245 case MLX5_OBJ_TYPE_MKEY:
246 return MLX5_OBJ_TYPE_MKEY;
247 case MLX5_CMD_OP_CREATE_RMP:
248 return MLX5_OBJ_TYPE_RMP;
249 case MLX5_CMD_OP_CREATE_XRC_SRQ:
250 return MLX5_OBJ_TYPE_XRC_SRQ;
251 case MLX5_CMD_OP_CREATE_XRQ:
252 return MLX5_OBJ_TYPE_XRQ;
253 case MLX5_CMD_OP_CREATE_RQT:
254 return MLX5_OBJ_TYPE_RQT;
255 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
256 return MLX5_OBJ_TYPE_FLOW_COUNTER;
257 case MLX5_CMD_OP_CREATE_CQ:
258 return MLX5_OBJ_TYPE_CQ;
259 default:
260 return 0;
261 }
262}
263
264static u16 get_event_obj_type(unsigned long event_type, struct mlx5_eqe *eqe)
265{
266 switch (event_type) {
267 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
268 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
269 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
270 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
271 case MLX5_EVENT_TYPE_PATH_MIG:
272 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
273 case MLX5_EVENT_TYPE_COMM_EST:
274 case MLX5_EVENT_TYPE_SQ_DRAINED:
275 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
276 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
277 return eqe->data.qp_srq.type;
278 case MLX5_EVENT_TYPE_CQ_ERROR:
279 case MLX5_EVENT_TYPE_XRQ_ERROR:
280 return 0;
281 case MLX5_EVENT_TYPE_DCT_DRAINED:
282 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION:
283 return MLX5_EVENT_QUEUE_TYPE_DCT;
284 default:
285 return MLX5_GET(affiliated_event_header, &eqe->data, obj_type);
286 }
287}
288
289static u32 get_dec_obj_id(u64 obj_id)
290{
291 return (obj_id & 0xffffffff);
292}
293
294/*
295 * As the obj_id in the firmware is not globally unique the object type
296 * must be considered upon checking for a valid object id.
297 * For that the opcode of the creator command is encoded as part of the obj_id.
298 */
299static u64 get_enc_obj_id(u32 opcode, u32 obj_id)
300{
301 return ((u64)opcode << 32) | obj_id;
302}
303
304static u32 devx_get_created_obj_id(const void *in, const void *out, u16 opcode)
305{
306 switch (opcode) {
307 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
308 return MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
309 case MLX5_CMD_OP_CREATE_UMEM:
310 return MLX5_GET(create_umem_out, out, umem_id);
311 case MLX5_CMD_OP_CREATE_MKEY:
312 return MLX5_GET(create_mkey_out, out, mkey_index);
313 case MLX5_CMD_OP_CREATE_CQ:
314 return MLX5_GET(create_cq_out, out, cqn);
315 case MLX5_CMD_OP_ALLOC_PD:
316 return MLX5_GET(alloc_pd_out, out, pd);
317 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
318 return MLX5_GET(alloc_transport_domain_out, out,
319 transport_domain);
320 case MLX5_CMD_OP_CREATE_RMP:
321 return MLX5_GET(create_rmp_out, out, rmpn);
322 case MLX5_CMD_OP_CREATE_SQ:
323 return MLX5_GET(create_sq_out, out, sqn);
324 case MLX5_CMD_OP_CREATE_RQ:
325 return MLX5_GET(create_rq_out, out, rqn);
326 case MLX5_CMD_OP_CREATE_RQT:
327 return MLX5_GET(create_rqt_out, out, rqtn);
328 case MLX5_CMD_OP_CREATE_TIR:
329 return MLX5_GET(create_tir_out, out, tirn);
330 case MLX5_CMD_OP_CREATE_TIS:
331 return MLX5_GET(create_tis_out, out, tisn);
332 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
333 return MLX5_GET(alloc_q_counter_out, out, counter_set_id);
334 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
335 return MLX5_GET(create_flow_table_out, out, table_id);
336 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
337 return MLX5_GET(create_flow_group_out, out, group_id);
338 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
339 return MLX5_GET(set_fte_in, in, flow_index);
340 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
341 return MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
342 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
343 return MLX5_GET(alloc_packet_reformat_context_out, out,
344 packet_reformat_id);
345 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
346 return MLX5_GET(alloc_modify_header_context_out, out,
347 modify_header_id);
348 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
349 return MLX5_GET(create_scheduling_element_out, out,
350 scheduling_element_id);
351 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
352 return MLX5_GET(add_vxlan_udp_dport_in, in, vxlan_udp_port);
353 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
354 return MLX5_GET(set_l2_table_entry_in, in, table_index);
355 case MLX5_CMD_OP_CREATE_QP:
356 return MLX5_GET(create_qp_out, out, qpn);
357 case MLX5_CMD_OP_CREATE_SRQ:
358 return MLX5_GET(create_srq_out, out, srqn);
359 case MLX5_CMD_OP_CREATE_XRC_SRQ:
360 return MLX5_GET(create_xrc_srq_out, out, xrc_srqn);
361 case MLX5_CMD_OP_CREATE_DCT:
362 return MLX5_GET(create_dct_out, out, dctn);
363 case MLX5_CMD_OP_CREATE_XRQ:
364 return MLX5_GET(create_xrq_out, out, xrqn);
365 case MLX5_CMD_OP_ATTACH_TO_MCG:
366 return MLX5_GET(attach_to_mcg_in, in, qpn);
367 case MLX5_CMD_OP_ALLOC_XRCD:
368 return MLX5_GET(alloc_xrcd_out, out, xrcd);
369 case MLX5_CMD_OP_CREATE_PSV:
370 return MLX5_GET(create_psv_out, out, psv0_index);
371 default:
372 /* The entry must match to one of the devx_is_obj_create_cmd */
373 WARN_ON(true);
374 return 0;
375 }
376}
377
378static u64 devx_get_obj_id(const void *in)
379{
380 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
381 u64 obj_id;
382
383 switch (opcode) {
384 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
385 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
386 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_GENERAL_OBJECT |
387 MLX5_GET(general_obj_in_cmd_hdr, in,
388 obj_type) << 16,
389 MLX5_GET(general_obj_in_cmd_hdr, in,
390 obj_id));
391 break;
392 case MLX5_CMD_OP_QUERY_MKEY:
393 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_MKEY,
394 MLX5_GET(query_mkey_in, in,
395 mkey_index));
396 break;
397 case MLX5_CMD_OP_QUERY_CQ:
398 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ,
399 MLX5_GET(query_cq_in, in, cqn));
400 break;
401 case MLX5_CMD_OP_MODIFY_CQ:
402 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ,
403 MLX5_GET(modify_cq_in, in, cqn));
404 break;
405 case MLX5_CMD_OP_QUERY_SQ:
406 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ,
407 MLX5_GET(query_sq_in, in, sqn));
408 break;
409 case MLX5_CMD_OP_MODIFY_SQ:
410 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ,
411 MLX5_GET(modify_sq_in, in, sqn));
412 break;
413 case MLX5_CMD_OP_QUERY_RQ:
414 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
415 MLX5_GET(query_rq_in, in, rqn));
416 break;
417 case MLX5_CMD_OP_MODIFY_RQ:
418 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
419 MLX5_GET(modify_rq_in, in, rqn));
420 break;
421 case MLX5_CMD_OP_QUERY_RMP:
422 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP,
423 MLX5_GET(query_rmp_in, in, rmpn));
424 break;
425 case MLX5_CMD_OP_MODIFY_RMP:
426 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP,
427 MLX5_GET(modify_rmp_in, in, rmpn));
428 break;
429 case MLX5_CMD_OP_QUERY_RQT:
430 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT,
431 MLX5_GET(query_rqt_in, in, rqtn));
432 break;
433 case MLX5_CMD_OP_MODIFY_RQT:
434 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT,
435 MLX5_GET(modify_rqt_in, in, rqtn));
436 break;
437 case MLX5_CMD_OP_QUERY_TIR:
438 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR,
439 MLX5_GET(query_tir_in, in, tirn));
440 break;
441 case MLX5_CMD_OP_MODIFY_TIR:
442 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR,
443 MLX5_GET(modify_tir_in, in, tirn));
444 break;
445 case MLX5_CMD_OP_QUERY_TIS:
446 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS,
447 MLX5_GET(query_tis_in, in, tisn));
448 break;
449 case MLX5_CMD_OP_MODIFY_TIS:
450 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS,
451 MLX5_GET(modify_tis_in, in, tisn));
452 break;
453 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
454 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE,
455 MLX5_GET(query_flow_table_in, in,
456 table_id));
457 break;
458 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
459 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE,
460 MLX5_GET(modify_flow_table_in, in,
461 table_id));
462 break;
463 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
464 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_GROUP,
465 MLX5_GET(query_flow_group_in, in,
466 group_id));
467 break;
468 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
469 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY,
470 MLX5_GET(query_fte_in, in,
471 flow_index));
472 break;
473 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
474 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY,
475 MLX5_GET(set_fte_in, in, flow_index));
476 break;
477 case MLX5_CMD_OP_QUERY_Q_COUNTER:
478 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_Q_COUNTER,
479 MLX5_GET(query_q_counter_in, in,
480 counter_set_id));
481 break;
482 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
483 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_FLOW_COUNTER,
484 MLX5_GET(query_flow_counter_in, in,
485 flow_counter_id));
486 break;
487 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT:
488 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT,
489 MLX5_GET(query_modify_header_context_in,
490 in, modify_header_id));
491 break;
492 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
493 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT,
494 MLX5_GET(query_scheduling_element_in,
495 in, scheduling_element_id));
496 break;
497 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
498 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT,
499 MLX5_GET(modify_scheduling_element_in,
500 in, scheduling_element_id));
501 break;
502 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
503 obj_id = get_enc_obj_id(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT,
504 MLX5_GET(add_vxlan_udp_dport_in, in,
505 vxlan_udp_port));
506 break;
507 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
508 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY,
509 MLX5_GET(query_l2_table_entry_in, in,
510 table_index));
511 break;
512 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
513 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY,
514 MLX5_GET(set_l2_table_entry_in, in,
515 table_index));
516 break;
517 case MLX5_CMD_OP_QUERY_QP:
518 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
519 MLX5_GET(query_qp_in, in, qpn));
520 break;
521 case MLX5_CMD_OP_RST2INIT_QP:
522 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
523 MLX5_GET(rst2init_qp_in, in, qpn));
524 break;
525 case MLX5_CMD_OP_INIT2INIT_QP:
526 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
527 MLX5_GET(init2init_qp_in, in, qpn));
528 break;
529 case MLX5_CMD_OP_INIT2RTR_QP:
530 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
531 MLX5_GET(init2rtr_qp_in, in, qpn));
532 break;
533 case MLX5_CMD_OP_RTR2RTS_QP:
534 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
535 MLX5_GET(rtr2rts_qp_in, in, qpn));
536 break;
537 case MLX5_CMD_OP_RTS2RTS_QP:
538 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
539 MLX5_GET(rts2rts_qp_in, in, qpn));
540 break;
541 case MLX5_CMD_OP_SQERR2RTS_QP:
542 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
543 MLX5_GET(sqerr2rts_qp_in, in, qpn));
544 break;
545 case MLX5_CMD_OP_2ERR_QP:
546 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
547 MLX5_GET(qp_2err_in, in, qpn));
548 break;
549 case MLX5_CMD_OP_2RST_QP:
550 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
551 MLX5_GET(qp_2rst_in, in, qpn));
552 break;
553 case MLX5_CMD_OP_QUERY_DCT:
554 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
555 MLX5_GET(query_dct_in, in, dctn));
556 break;
557 case MLX5_CMD_OP_QUERY_XRQ:
558 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY:
559 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS:
560 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ,
561 MLX5_GET(query_xrq_in, in, xrqn));
562 break;
563 case MLX5_CMD_OP_QUERY_XRC_SRQ:
564 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ,
565 MLX5_GET(query_xrc_srq_in, in,
566 xrc_srqn));
567 break;
568 case MLX5_CMD_OP_ARM_XRC_SRQ:
569 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ,
570 MLX5_GET(arm_xrc_srq_in, in, xrc_srqn));
571 break;
572 case MLX5_CMD_OP_QUERY_SRQ:
573 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SRQ,
574 MLX5_GET(query_srq_in, in, srqn));
575 break;
576 case MLX5_CMD_OP_ARM_RQ:
577 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
578 MLX5_GET(arm_rq_in, in, srq_number));
579 break;
580 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
581 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
582 MLX5_GET(drain_dct_in, in, dctn));
583 break;
584 case MLX5_CMD_OP_ARM_XRQ:
585 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY:
586 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
587 case MLX5_CMD_OP_MODIFY_XRQ:
588 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ,
589 MLX5_GET(arm_xrq_in, in, xrqn));
590 break;
591 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT:
592 obj_id = get_enc_obj_id
593 (MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT,
594 MLX5_GET(query_packet_reformat_context_in,
595 in, packet_reformat_id));
596 break;
597 default:
598 obj_id = 0;
599 }
600
601 return obj_id;
602}
603
604static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs,
605 struct ib_uobject *uobj, const void *in)
606{
607 struct mlx5_ib_dev *dev = mlx5_udata_to_mdev(&attrs->driver_udata);
608 u64 obj_id = devx_get_obj_id(in);
609
610 if (!obj_id)
611 return false;
612
613 switch (uobj_get_object_id(uobj)) {
614 case UVERBS_OBJECT_CQ:
615 return get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ,
616 to_mcq(uobj->object)->mcq.cqn) ==
617 obj_id;
618
619 case UVERBS_OBJECT_SRQ:
620 {
621 struct mlx5_core_srq *srq = &(to_msrq(uobj->object)->msrq);
622 u16 opcode;
623
624 switch (srq->common.res) {
625 case MLX5_RES_XSRQ:
626 opcode = MLX5_CMD_OP_CREATE_XRC_SRQ;
627 break;
628 case MLX5_RES_XRQ:
629 opcode = MLX5_CMD_OP_CREATE_XRQ;
630 break;
631 default:
632 if (!dev->mdev->issi)
633 opcode = MLX5_CMD_OP_CREATE_SRQ;
634 else
635 opcode = MLX5_CMD_OP_CREATE_RMP;
636 }
637
638 return get_enc_obj_id(opcode,
639 to_msrq(uobj->object)->msrq.srqn) ==
640 obj_id;
641 }
642
643 case UVERBS_OBJECT_QP:
644 {
645 struct mlx5_ib_qp *qp = to_mqp(uobj->object);
646
647 if (qp->type == IB_QPT_RAW_PACKET ||
648 (qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
649 struct mlx5_ib_raw_packet_qp *raw_packet_qp =
650 &qp->raw_packet_qp;
651 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
652 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
653
654 return (get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
655 rq->base.mqp.qpn) == obj_id ||
656 get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ,
657 sq->base.mqp.qpn) == obj_id ||
658 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR,
659 rq->tirn) == obj_id ||
660 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS,
661 sq->tisn) == obj_id);
662 }
663
664 if (qp->type == MLX5_IB_QPT_DCT)
665 return get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT,
666 qp->dct.mdct.mqp.qpn) == obj_id;
667 return get_enc_obj_id(MLX5_CMD_OP_CREATE_QP,
668 qp->ibqp.qp_num) == obj_id;
669 }
670
671 case UVERBS_OBJECT_WQ:
672 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ,
673 to_mrwq(uobj->object)->core_qp.qpn) ==
674 obj_id;
675
676 case UVERBS_OBJECT_RWQ_IND_TBL:
677 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT,
678 to_mrwq_ind_table(uobj->object)->rqtn) ==
679 obj_id;
680
681 case MLX5_IB_OBJECT_DEVX_OBJ:
682 {
683 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
684 struct devx_obj *devx_uobj = uobj->object;
685
686 if (opcode == MLX5_CMD_OP_QUERY_FLOW_COUNTER &&
687 devx_uobj->flow_counter_bulk_size) {
688 u64 end;
689
690 end = devx_uobj->obj_id +
691 devx_uobj->flow_counter_bulk_size;
692 return devx_uobj->obj_id <= obj_id && end > obj_id;
693 }
694
695 return devx_uobj->obj_id == obj_id;
696 }
697
698 default:
699 return false;
700 }
701}
702
703static void devx_set_umem_valid(const void *in)
704{
705 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
706
707 switch (opcode) {
708 case MLX5_CMD_OP_CREATE_MKEY:
709 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1);
710 break;
711 case MLX5_CMD_OP_CREATE_CQ:
712 {
713 void *cqc;
714
715 MLX5_SET(create_cq_in, in, cq_umem_valid, 1);
716 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
717 MLX5_SET(cqc, cqc, dbr_umem_valid, 1);
718 break;
719 }
720 case MLX5_CMD_OP_CREATE_QP:
721 {
722 void *qpc;
723
724 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
725 MLX5_SET(qpc, qpc, dbr_umem_valid, 1);
726 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
727 break;
728 }
729
730 case MLX5_CMD_OP_CREATE_RQ:
731 {
732 void *rqc, *wq;
733
734 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
735 wq = MLX5_ADDR_OF(rqc, rqc, wq);
736 MLX5_SET(wq, wq, dbr_umem_valid, 1);
737 MLX5_SET(wq, wq, wq_umem_valid, 1);
738 break;
739 }
740
741 case MLX5_CMD_OP_CREATE_SQ:
742 {
743 void *sqc, *wq;
744
745 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
746 wq = MLX5_ADDR_OF(sqc, sqc, wq);
747 MLX5_SET(wq, wq, dbr_umem_valid, 1);
748 MLX5_SET(wq, wq, wq_umem_valid, 1);
749 break;
750 }
751
752 case MLX5_CMD_OP_MODIFY_CQ:
753 MLX5_SET(modify_cq_in, in, cq_umem_valid, 1);
754 break;
755
756 case MLX5_CMD_OP_CREATE_RMP:
757 {
758 void *rmpc, *wq;
759
760 rmpc = MLX5_ADDR_OF(create_rmp_in, in, ctx);
761 wq = MLX5_ADDR_OF(rmpc, rmpc, wq);
762 MLX5_SET(wq, wq, dbr_umem_valid, 1);
763 MLX5_SET(wq, wq, wq_umem_valid, 1);
764 break;
765 }
766
767 case MLX5_CMD_OP_CREATE_XRQ:
768 {
769 void *xrqc, *wq;
770
771 xrqc = MLX5_ADDR_OF(create_xrq_in, in, xrq_context);
772 wq = MLX5_ADDR_OF(xrqc, xrqc, wq);
773 MLX5_SET(wq, wq, dbr_umem_valid, 1);
774 MLX5_SET(wq, wq, wq_umem_valid, 1);
775 break;
776 }
777
778 case MLX5_CMD_OP_CREATE_XRC_SRQ:
779 {
780 void *xrc_srqc;
781
782 MLX5_SET(create_xrc_srq_in, in, xrc_srq_umem_valid, 1);
783 xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, in,
784 xrc_srq_context_entry);
785 MLX5_SET(xrc_srqc, xrc_srqc, dbr_umem_valid, 1);
786 break;
787 }
788
789 default:
790 return;
791 }
792}
793
794static bool devx_is_obj_create_cmd(const void *in, u16 *opcode)
795{
796 *opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
797
798 switch (*opcode) {
799 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
800 case MLX5_CMD_OP_CREATE_MKEY:
801 case MLX5_CMD_OP_CREATE_CQ:
802 case MLX5_CMD_OP_ALLOC_PD:
803 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
804 case MLX5_CMD_OP_CREATE_RMP:
805 case MLX5_CMD_OP_CREATE_SQ:
806 case MLX5_CMD_OP_CREATE_RQ:
807 case MLX5_CMD_OP_CREATE_RQT:
808 case MLX5_CMD_OP_CREATE_TIR:
809 case MLX5_CMD_OP_CREATE_TIS:
810 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
811 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
812 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
813 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
814 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
815 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
816 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
817 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
818 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
819 case MLX5_CMD_OP_CREATE_QP:
820 case MLX5_CMD_OP_CREATE_SRQ:
821 case MLX5_CMD_OP_CREATE_XRC_SRQ:
822 case MLX5_CMD_OP_CREATE_DCT:
823 case MLX5_CMD_OP_CREATE_XRQ:
824 case MLX5_CMD_OP_ATTACH_TO_MCG:
825 case MLX5_CMD_OP_ALLOC_XRCD:
826 return true;
827 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
828 {
829 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod);
830 if (op_mod == 0)
831 return true;
832 return false;
833 }
834 case MLX5_CMD_OP_CREATE_PSV:
835 {
836 u8 num_psv = MLX5_GET(create_psv_in, in, num_psv);
837
838 if (num_psv == 1)
839 return true;
840 return false;
841 }
842 default:
843 return false;
844 }
845}
846
847static bool devx_is_obj_modify_cmd(const void *in)
848{
849 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
850
851 switch (opcode) {
852 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
853 case MLX5_CMD_OP_MODIFY_CQ:
854 case MLX5_CMD_OP_MODIFY_RMP:
855 case MLX5_CMD_OP_MODIFY_SQ:
856 case MLX5_CMD_OP_MODIFY_RQ:
857 case MLX5_CMD_OP_MODIFY_RQT:
858 case MLX5_CMD_OP_MODIFY_TIR:
859 case MLX5_CMD_OP_MODIFY_TIS:
860 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
861 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
862 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
863 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
864 case MLX5_CMD_OP_RST2INIT_QP:
865 case MLX5_CMD_OP_INIT2RTR_QP:
866 case MLX5_CMD_OP_INIT2INIT_QP:
867 case MLX5_CMD_OP_RTR2RTS_QP:
868 case MLX5_CMD_OP_RTS2RTS_QP:
869 case MLX5_CMD_OP_SQERR2RTS_QP:
870 case MLX5_CMD_OP_2ERR_QP:
871 case MLX5_CMD_OP_2RST_QP:
872 case MLX5_CMD_OP_ARM_XRC_SRQ:
873 case MLX5_CMD_OP_ARM_RQ:
874 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
875 case MLX5_CMD_OP_ARM_XRQ:
876 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY:
877 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
878 case MLX5_CMD_OP_MODIFY_XRQ:
879 return true;
880 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
881 {
882 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod);
883
884 if (op_mod == 1)
885 return true;
886 return false;
887 }
888 default:
889 return false;
890 }
891}
892
893static bool devx_is_obj_query_cmd(const void *in)
894{
895 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
896
897 switch (opcode) {
898 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
899 case MLX5_CMD_OP_QUERY_MKEY:
900 case MLX5_CMD_OP_QUERY_CQ:
901 case MLX5_CMD_OP_QUERY_RMP:
902 case MLX5_CMD_OP_QUERY_SQ:
903 case MLX5_CMD_OP_QUERY_RQ:
904 case MLX5_CMD_OP_QUERY_RQT:
905 case MLX5_CMD_OP_QUERY_TIR:
906 case MLX5_CMD_OP_QUERY_TIS:
907 case MLX5_CMD_OP_QUERY_Q_COUNTER:
908 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
909 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
910 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
911 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
912 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT:
913 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
914 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
915 case MLX5_CMD_OP_QUERY_QP:
916 case MLX5_CMD_OP_QUERY_SRQ:
917 case MLX5_CMD_OP_QUERY_XRC_SRQ:
918 case MLX5_CMD_OP_QUERY_DCT:
919 case MLX5_CMD_OP_QUERY_XRQ:
920 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY:
921 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS:
922 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT:
923 return true;
924 default:
925 return false;
926 }
927}
928
929static bool devx_is_whitelist_cmd(void *in)
930{
931 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
932
933 switch (opcode) {
934 case MLX5_CMD_OP_QUERY_HCA_CAP:
935 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
936 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
937 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
938 return true;
939 default:
940 return false;
941 }
942}
943
944static int devx_get_uid(struct mlx5_ib_ucontext *c, void *cmd_in)
945{
946 if (devx_is_whitelist_cmd(cmd_in)) {
947 struct mlx5_ib_dev *dev;
948
949 if (c->devx_uid)
950 return c->devx_uid;
951
952 dev = to_mdev(c->ibucontext.device);
953 if (dev->devx_whitelist_uid)
954 return dev->devx_whitelist_uid;
955
956 return -EOPNOTSUPP;
957 }
958
959 if (!c->devx_uid)
960 return -EINVAL;
961
962 return c->devx_uid;
963}
964
965static bool devx_is_general_cmd(void *in, struct mlx5_ib_dev *dev)
966{
967 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
968
969 /* Pass all cmds for vhca_tunnel as general, tracking is done in FW */
970 if ((MLX5_CAP_GEN_64(dev->mdev, vhca_tunnel_commands) &&
971 MLX5_GET(general_obj_in_cmd_hdr, in, vhca_tunnel_id)) ||
972 (opcode >= MLX5_CMD_OP_GENERAL_START &&
973 opcode < MLX5_CMD_OP_GENERAL_END))
974 return true;
975
976 switch (opcode) {
977 case MLX5_CMD_OP_QUERY_HCA_CAP:
978 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
979 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
980 case MLX5_CMD_OP_QUERY_VPORT_STATE:
981 case MLX5_CMD_OP_QUERY_ADAPTER:
982 case MLX5_CMD_OP_QUERY_ISSI:
983 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
984 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
985 case MLX5_CMD_OP_QUERY_VNIC_ENV:
986 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
987 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
988 case MLX5_CMD_OP_NOP:
989 case MLX5_CMD_OP_QUERY_CONG_STATUS:
990 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
991 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
992 case MLX5_CMD_OP_QUERY_LAG:
993 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
994 return true;
995 default:
996 return false;
997 }
998}
999
1000static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)(
1001 struct uverbs_attr_bundle *attrs)
1002{
1003 struct mlx5_ib_ucontext *c;
1004 struct mlx5_ib_dev *dev;
1005 int user_vector;
1006 int dev_eqn;
1007 int err;
1008
1009 if (uverbs_copy_from(&user_vector, attrs,
1010 MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC))
1011 return -EFAULT;
1012
1013 c = devx_ufile2uctx(attrs);
1014 if (IS_ERR(c))
1015 return PTR_ERR(c);
1016 dev = to_mdev(c->ibucontext.device);
1017
1018 err = mlx5_comp_eqn_get(dev->mdev, user_vector, &dev_eqn);
1019 if (err < 0)
1020 return err;
1021
1022 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN,
1023 &dev_eqn, sizeof(dev_eqn)))
1024 return -EFAULT;
1025
1026 return 0;
1027}
1028
1029/*
1030 *Security note:
1031 * The hardware protection mechanism works like this: Each device object that
1032 * is subject to UAR doorbells (QP/SQ/CQ) gets a UAR ID (called uar_page in
1033 * the device specification manual) upon its creation. Then upon doorbell,
1034 * hardware fetches the object context for which the doorbell was rang, and
1035 * validates that the UAR through which the DB was rang matches the UAR ID
1036 * of the object.
1037 * If no match the doorbell is silently ignored by the hardware. Of course,
1038 * the user cannot ring a doorbell on a UAR that was not mapped to it.
1039 * Now in devx, as the devx kernel does not manipulate the QP/SQ/CQ command
1040 * mailboxes (except tagging them with UID), we expose to the user its UAR
1041 * ID, so it can embed it in these objects in the expected specification
1042 * format. So the only thing the user can do is hurt itself by creating a
1043 * QP/SQ/CQ with a UAR ID other than his, and then in this case other users
1044 * may ring a doorbell on its objects.
1045 * The consequence of that will be that another user can schedule a QP/SQ
1046 * of the buggy user for execution (just insert it to the hardware schedule
1047 * queue or arm its CQ for event generation), no further harm is expected.
1048 */
1049static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_UAR)(
1050 struct uverbs_attr_bundle *attrs)
1051{
1052 struct mlx5_ib_ucontext *c;
1053 struct mlx5_ib_dev *dev;
1054 u32 user_idx;
1055 s32 dev_idx;
1056
1057 c = devx_ufile2uctx(attrs);
1058 if (IS_ERR(c))
1059 return PTR_ERR(c);
1060 dev = to_mdev(c->ibucontext.device);
1061
1062 if (uverbs_copy_from(&user_idx, attrs,
1063 MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX))
1064 return -EFAULT;
1065
1066 dev_idx = bfregn_to_uar_index(dev, &c->bfregi, user_idx, true);
1067 if (dev_idx < 0)
1068 return dev_idx;
1069
1070 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX,
1071 &dev_idx, sizeof(dev_idx)))
1072 return -EFAULT;
1073
1074 return 0;
1075}
1076
1077static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OTHER)(
1078 struct uverbs_attr_bundle *attrs)
1079{
1080 struct mlx5_ib_ucontext *c;
1081 struct mlx5_ib_dev *dev;
1082 void *cmd_in = uverbs_attr_get_alloced_ptr(
1083 attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN);
1084 int cmd_out_len = uverbs_attr_get_len(attrs,
1085 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT);
1086 void *cmd_out;
1087 int err, err2;
1088 int uid;
1089
1090 c = devx_ufile2uctx(attrs);
1091 if (IS_ERR(c))
1092 return PTR_ERR(c);
1093 dev = to_mdev(c->ibucontext.device);
1094
1095 uid = devx_get_uid(c, cmd_in);
1096 if (uid < 0)
1097 return uid;
1098
1099 /* Only white list of some general HCA commands are allowed for this method. */
1100 if (!devx_is_general_cmd(cmd_in, dev))
1101 return -EINVAL;
1102
1103 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1104 if (IS_ERR(cmd_out))
1105 return PTR_ERR(cmd_out);
1106
1107 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1108 err = mlx5_cmd_do(dev->mdev, cmd_in,
1109 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN),
1110 cmd_out, cmd_out_len);
1111 if (err && err != -EREMOTEIO)
1112 return err;
1113
1114 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, cmd_out,
1115 cmd_out_len);
1116
1117 return err2 ?: err;
1118}
1119
1120static void devx_obj_build_destroy_cmd(void *in, void *out, void *din,
1121 u32 *dinlen,
1122 u32 *obj_id)
1123{
1124 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
1125 u16 uid = MLX5_GET(general_obj_in_cmd_hdr, in, uid);
1126
1127 *obj_id = devx_get_created_obj_id(in, out, opcode);
1128 *dinlen = MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr);
1129 MLX5_SET(general_obj_in_cmd_hdr, din, uid, uid);
1130
1131 switch (opcode) {
1132 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
1133 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT);
1134 MLX5_SET(general_obj_in_cmd_hdr, din, obj_id, *obj_id);
1135 MLX5_SET(general_obj_in_cmd_hdr, din, obj_type,
1136 MLX5_GET(general_obj_in_cmd_hdr, in, obj_type));
1137 break;
1138
1139 case MLX5_CMD_OP_CREATE_UMEM:
1140 MLX5_SET(destroy_umem_in, din, opcode,
1141 MLX5_CMD_OP_DESTROY_UMEM);
1142 MLX5_SET(destroy_umem_in, din, umem_id, *obj_id);
1143 break;
1144 case MLX5_CMD_OP_CREATE_MKEY:
1145 MLX5_SET(destroy_mkey_in, din, opcode,
1146 MLX5_CMD_OP_DESTROY_MKEY);
1147 MLX5_SET(destroy_mkey_in, din, mkey_index, *obj_id);
1148 break;
1149 case MLX5_CMD_OP_CREATE_CQ:
1150 MLX5_SET(destroy_cq_in, din, opcode, MLX5_CMD_OP_DESTROY_CQ);
1151 MLX5_SET(destroy_cq_in, din, cqn, *obj_id);
1152 break;
1153 case MLX5_CMD_OP_ALLOC_PD:
1154 MLX5_SET(dealloc_pd_in, din, opcode, MLX5_CMD_OP_DEALLOC_PD);
1155 MLX5_SET(dealloc_pd_in, din, pd, *obj_id);
1156 break;
1157 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
1158 MLX5_SET(dealloc_transport_domain_in, din, opcode,
1159 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN);
1160 MLX5_SET(dealloc_transport_domain_in, din, transport_domain,
1161 *obj_id);
1162 break;
1163 case MLX5_CMD_OP_CREATE_RMP:
1164 MLX5_SET(destroy_rmp_in, din, opcode, MLX5_CMD_OP_DESTROY_RMP);
1165 MLX5_SET(destroy_rmp_in, din, rmpn, *obj_id);
1166 break;
1167 case MLX5_CMD_OP_CREATE_SQ:
1168 MLX5_SET(destroy_sq_in, din, opcode, MLX5_CMD_OP_DESTROY_SQ);
1169 MLX5_SET(destroy_sq_in, din, sqn, *obj_id);
1170 break;
1171 case MLX5_CMD_OP_CREATE_RQ:
1172 MLX5_SET(destroy_rq_in, din, opcode, MLX5_CMD_OP_DESTROY_RQ);
1173 MLX5_SET(destroy_rq_in, din, rqn, *obj_id);
1174 break;
1175 case MLX5_CMD_OP_CREATE_RQT:
1176 MLX5_SET(destroy_rqt_in, din, opcode, MLX5_CMD_OP_DESTROY_RQT);
1177 MLX5_SET(destroy_rqt_in, din, rqtn, *obj_id);
1178 break;
1179 case MLX5_CMD_OP_CREATE_TIR:
1180 MLX5_SET(destroy_tir_in, din, opcode, MLX5_CMD_OP_DESTROY_TIR);
1181 MLX5_SET(destroy_tir_in, din, tirn, *obj_id);
1182 break;
1183 case MLX5_CMD_OP_CREATE_TIS:
1184 MLX5_SET(destroy_tis_in, din, opcode, MLX5_CMD_OP_DESTROY_TIS);
1185 MLX5_SET(destroy_tis_in, din, tisn, *obj_id);
1186 break;
1187 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
1188 MLX5_SET(dealloc_q_counter_in, din, opcode,
1189 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
1190 MLX5_SET(dealloc_q_counter_in, din, counter_set_id, *obj_id);
1191 break;
1192 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
1193 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_table_in);
1194 MLX5_SET(destroy_flow_table_in, din, other_vport,
1195 MLX5_GET(create_flow_table_in, in, other_vport));
1196 MLX5_SET(destroy_flow_table_in, din, vport_number,
1197 MLX5_GET(create_flow_table_in, in, vport_number));
1198 MLX5_SET(destroy_flow_table_in, din, table_type,
1199 MLX5_GET(create_flow_table_in, in, table_type));
1200 MLX5_SET(destroy_flow_table_in, din, table_id, *obj_id);
1201 MLX5_SET(destroy_flow_table_in, din, opcode,
1202 MLX5_CMD_OP_DESTROY_FLOW_TABLE);
1203 break;
1204 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
1205 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_group_in);
1206 MLX5_SET(destroy_flow_group_in, din, other_vport,
1207 MLX5_GET(create_flow_group_in, in, other_vport));
1208 MLX5_SET(destroy_flow_group_in, din, vport_number,
1209 MLX5_GET(create_flow_group_in, in, vport_number));
1210 MLX5_SET(destroy_flow_group_in, din, table_type,
1211 MLX5_GET(create_flow_group_in, in, table_type));
1212 MLX5_SET(destroy_flow_group_in, din, table_id,
1213 MLX5_GET(create_flow_group_in, in, table_id));
1214 MLX5_SET(destroy_flow_group_in, din, group_id, *obj_id);
1215 MLX5_SET(destroy_flow_group_in, din, opcode,
1216 MLX5_CMD_OP_DESTROY_FLOW_GROUP);
1217 break;
1218 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
1219 *dinlen = MLX5_ST_SZ_BYTES(delete_fte_in);
1220 MLX5_SET(delete_fte_in, din, other_vport,
1221 MLX5_GET(set_fte_in, in, other_vport));
1222 MLX5_SET(delete_fte_in, din, vport_number,
1223 MLX5_GET(set_fte_in, in, vport_number));
1224 MLX5_SET(delete_fte_in, din, table_type,
1225 MLX5_GET(set_fte_in, in, table_type));
1226 MLX5_SET(delete_fte_in, din, table_id,
1227 MLX5_GET(set_fte_in, in, table_id));
1228 MLX5_SET(delete_fte_in, din, flow_index, *obj_id);
1229 MLX5_SET(delete_fte_in, din, opcode,
1230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY);
1231 break;
1232 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
1233 MLX5_SET(dealloc_flow_counter_in, din, opcode,
1234 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER);
1235 MLX5_SET(dealloc_flow_counter_in, din, flow_counter_id,
1236 *obj_id);
1237 break;
1238 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
1239 MLX5_SET(dealloc_packet_reformat_context_in, din, opcode,
1240 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT);
1241 MLX5_SET(dealloc_packet_reformat_context_in, din,
1242 packet_reformat_id, *obj_id);
1243 break;
1244 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
1245 MLX5_SET(dealloc_modify_header_context_in, din, opcode,
1246 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT);
1247 MLX5_SET(dealloc_modify_header_context_in, din,
1248 modify_header_id, *obj_id);
1249 break;
1250 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
1251 *dinlen = MLX5_ST_SZ_BYTES(destroy_scheduling_element_in);
1252 MLX5_SET(destroy_scheduling_element_in, din,
1253 scheduling_hierarchy,
1254 MLX5_GET(create_scheduling_element_in, in,
1255 scheduling_hierarchy));
1256 MLX5_SET(destroy_scheduling_element_in, din,
1257 scheduling_element_id, *obj_id);
1258 MLX5_SET(destroy_scheduling_element_in, din, opcode,
1259 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
1260 break;
1261 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
1262 *dinlen = MLX5_ST_SZ_BYTES(delete_vxlan_udp_dport_in);
1263 MLX5_SET(delete_vxlan_udp_dport_in, din, vxlan_udp_port, *obj_id);
1264 MLX5_SET(delete_vxlan_udp_dport_in, din, opcode,
1265 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT);
1266 break;
1267 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
1268 *dinlen = MLX5_ST_SZ_BYTES(delete_l2_table_entry_in);
1269 MLX5_SET(delete_l2_table_entry_in, din, table_index, *obj_id);
1270 MLX5_SET(delete_l2_table_entry_in, din, opcode,
1271 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
1272 break;
1273 case MLX5_CMD_OP_CREATE_QP:
1274 MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP);
1275 MLX5_SET(destroy_qp_in, din, qpn, *obj_id);
1276 break;
1277 case MLX5_CMD_OP_CREATE_SRQ:
1278 MLX5_SET(destroy_srq_in, din, opcode, MLX5_CMD_OP_DESTROY_SRQ);
1279 MLX5_SET(destroy_srq_in, din, srqn, *obj_id);
1280 break;
1281 case MLX5_CMD_OP_CREATE_XRC_SRQ:
1282 MLX5_SET(destroy_xrc_srq_in, din, opcode,
1283 MLX5_CMD_OP_DESTROY_XRC_SRQ);
1284 MLX5_SET(destroy_xrc_srq_in, din, xrc_srqn, *obj_id);
1285 break;
1286 case MLX5_CMD_OP_CREATE_DCT:
1287 MLX5_SET(destroy_dct_in, din, opcode, MLX5_CMD_OP_DESTROY_DCT);
1288 MLX5_SET(destroy_dct_in, din, dctn, *obj_id);
1289 break;
1290 case MLX5_CMD_OP_CREATE_XRQ:
1291 MLX5_SET(destroy_xrq_in, din, opcode, MLX5_CMD_OP_DESTROY_XRQ);
1292 MLX5_SET(destroy_xrq_in, din, xrqn, *obj_id);
1293 break;
1294 case MLX5_CMD_OP_ATTACH_TO_MCG:
1295 *dinlen = MLX5_ST_SZ_BYTES(detach_from_mcg_in);
1296 MLX5_SET(detach_from_mcg_in, din, qpn,
1297 MLX5_GET(attach_to_mcg_in, in, qpn));
1298 memcpy(MLX5_ADDR_OF(detach_from_mcg_in, din, multicast_gid),
1299 MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid),
1300 MLX5_FLD_SZ_BYTES(attach_to_mcg_in, multicast_gid));
1301 MLX5_SET(detach_from_mcg_in, din, opcode,
1302 MLX5_CMD_OP_DETACH_FROM_MCG);
1303 MLX5_SET(detach_from_mcg_in, din, qpn, *obj_id);
1304 break;
1305 case MLX5_CMD_OP_ALLOC_XRCD:
1306 MLX5_SET(dealloc_xrcd_in, din, opcode,
1307 MLX5_CMD_OP_DEALLOC_XRCD);
1308 MLX5_SET(dealloc_xrcd_in, din, xrcd, *obj_id);
1309 break;
1310 case MLX5_CMD_OP_CREATE_PSV:
1311 MLX5_SET(destroy_psv_in, din, opcode,
1312 MLX5_CMD_OP_DESTROY_PSV);
1313 MLX5_SET(destroy_psv_in, din, psvn, *obj_id);
1314 break;
1315 default:
1316 /* The entry must match to one of the devx_is_obj_create_cmd */
1317 WARN_ON(true);
1318 break;
1319 }
1320}
1321
1322static int devx_handle_mkey_indirect(struct devx_obj *obj,
1323 struct mlx5_ib_dev *dev,
1324 void *in, void *out)
1325{
1326 struct mlx5_ib_mkey *mkey = &obj->mkey;
1327 void *mkc;
1328 u8 key;
1329
1330 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1331 key = MLX5_GET(mkc, mkc, mkey_7_0);
1332 mkey->key = mlx5_idx_to_mkey(
1333 MLX5_GET(create_mkey_out, out, mkey_index)) | key;
1334 mkey->type = MLX5_MKEY_INDIRECT_DEVX;
1335 mkey->ndescs = MLX5_GET(mkc, mkc, translations_octword_size);
1336 init_waitqueue_head(&mkey->wait);
1337
1338 return mlx5r_store_odp_mkey(dev, mkey);
1339}
1340
1341static int devx_handle_mkey_create(struct mlx5_ib_dev *dev,
1342 struct devx_obj *obj,
1343 void *in, int in_len)
1344{
1345 int min_len = MLX5_BYTE_OFF(create_mkey_in, memory_key_mkey_entry) +
1346 MLX5_FLD_SZ_BYTES(create_mkey_in,
1347 memory_key_mkey_entry);
1348 void *mkc;
1349 u8 access_mode;
1350
1351 if (in_len < min_len)
1352 return -EINVAL;
1353
1354 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1355
1356 access_mode = MLX5_GET(mkc, mkc, access_mode_1_0);
1357 access_mode |= MLX5_GET(mkc, mkc, access_mode_4_2) << 2;
1358
1359 if (access_mode == MLX5_MKC_ACCESS_MODE_KLMS ||
1360 access_mode == MLX5_MKC_ACCESS_MODE_KSM) {
1361 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
1362 obj->flags |= DEVX_OBJ_FLAGS_INDIRECT_MKEY;
1363 return 0;
1364 }
1365
1366 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1);
1367 return 0;
1368}
1369
1370static void devx_cleanup_subscription(struct mlx5_ib_dev *dev,
1371 struct devx_event_subscription *sub)
1372{
1373 struct devx_event *event;
1374 struct devx_obj_event *xa_val_level2;
1375
1376 if (sub->is_cleaned)
1377 return;
1378
1379 sub->is_cleaned = 1;
1380 list_del_rcu(&sub->xa_list);
1381
1382 if (list_empty(&sub->obj_list))
1383 return;
1384
1385 list_del_rcu(&sub->obj_list);
1386 /* check whether key level 1 for this obj_sub_list is empty */
1387 event = xa_load(&dev->devx_event_table.event_xa,
1388 sub->xa_key_level1);
1389 WARN_ON(!event);
1390
1391 xa_val_level2 = xa_load(&event->object_ids, sub->xa_key_level2);
1392 if (list_empty(&xa_val_level2->obj_sub_list)) {
1393 xa_erase(&event->object_ids,
1394 sub->xa_key_level2);
1395 kfree_rcu(xa_val_level2, rcu);
1396 }
1397}
1398
1399static int devx_obj_cleanup(struct ib_uobject *uobject,
1400 enum rdma_remove_reason why,
1401 struct uverbs_attr_bundle *attrs)
1402{
1403 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
1404 struct mlx5_devx_event_table *devx_event_table;
1405 struct devx_obj *obj = uobject->object;
1406 struct devx_event_subscription *sub_entry, *tmp;
1407 struct mlx5_ib_dev *dev;
1408 int ret;
1409
1410 dev = mlx5_udata_to_mdev(&attrs->driver_udata);
1411 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY &&
1412 xa_erase(&obj->ib_dev->odp_mkeys,
1413 mlx5_base_mkey(obj->mkey.key)))
1414 /*
1415 * The pagefault_single_data_segment() does commands against
1416 * the mmkey, we must wait for that to stop before freeing the
1417 * mkey, as another allocation could get the same mkey #.
1418 */
1419 mlx5r_deref_wait_odp_mkey(&obj->mkey);
1420
1421 if (obj->flags & DEVX_OBJ_FLAGS_HW_FREED)
1422 ret = 0;
1423 else if (obj->flags & DEVX_OBJ_FLAGS_DCT)
1424 ret = mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct);
1425 else if (obj->flags & DEVX_OBJ_FLAGS_CQ)
1426 ret = mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq);
1427 else
1428 ret = mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox,
1429 obj->dinlen, out, sizeof(out));
1430 if (ret)
1431 return ret;
1432
1433 devx_event_table = &dev->devx_event_table;
1434
1435 mutex_lock(&devx_event_table->event_xa_lock);
1436 list_for_each_entry_safe(sub_entry, tmp, &obj->event_sub, obj_list)
1437 devx_cleanup_subscription(dev, sub_entry);
1438 mutex_unlock(&devx_event_table->event_xa_lock);
1439
1440 kfree(obj);
1441 return ret;
1442}
1443
1444static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe)
1445{
1446 struct devx_obj *obj = container_of(mcq, struct devx_obj, core_cq);
1447 struct mlx5_devx_event_table *table;
1448 struct devx_event *event;
1449 struct devx_obj_event *obj_event;
1450 u32 obj_id = mcq->cqn;
1451
1452 table = &obj->ib_dev->devx_event_table;
1453 rcu_read_lock();
1454 event = xa_load(&table->event_xa, MLX5_EVENT_TYPE_COMP);
1455 if (!event)
1456 goto out;
1457
1458 obj_event = xa_load(&event->object_ids, obj_id);
1459 if (!obj_event)
1460 goto out;
1461
1462 dispatch_event_fd(&obj_event->obj_sub_list, eqe);
1463out:
1464 rcu_read_unlock();
1465}
1466
1467static bool is_apu_cq(struct mlx5_ib_dev *dev, const void *in)
1468{
1469 if (!MLX5_CAP_GEN(dev->mdev, apu) ||
1470 !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), apu_cq))
1471 return false;
1472
1473 return true;
1474}
1475
1476static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)(
1477 struct uverbs_attr_bundle *attrs)
1478{
1479 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN);
1480 int cmd_out_len = uverbs_attr_get_len(attrs,
1481 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT);
1482 int cmd_in_len = uverbs_attr_get_len(attrs,
1483 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN);
1484 void *cmd_out;
1485 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1486 attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE);
1487 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1488 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1489 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
1490 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
1491 struct devx_obj *obj;
1492 u16 obj_type = 0;
1493 int err, err2 = 0;
1494 int uid;
1495 u32 obj_id;
1496 u16 opcode;
1497
1498 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1499 return -EINVAL;
1500
1501 uid = devx_get_uid(c, cmd_in);
1502 if (uid < 0)
1503 return uid;
1504
1505 if (!devx_is_obj_create_cmd(cmd_in, &opcode))
1506 return -EINVAL;
1507
1508 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1509 if (IS_ERR(cmd_out))
1510 return PTR_ERR(cmd_out);
1511
1512 obj = kzalloc(sizeof(struct devx_obj), GFP_KERNEL);
1513 if (!obj)
1514 return -ENOMEM;
1515
1516 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1517 if (opcode == MLX5_CMD_OP_CREATE_MKEY) {
1518 err = devx_handle_mkey_create(dev, obj, cmd_in, cmd_in_len);
1519 if (err)
1520 goto obj_free;
1521 } else {
1522 devx_set_umem_valid(cmd_in);
1523 }
1524
1525 if (opcode == MLX5_CMD_OP_CREATE_DCT) {
1526 obj->flags |= DEVX_OBJ_FLAGS_DCT;
1527 err = mlx5_core_create_dct(dev, &obj->core_dct, cmd_in,
1528 cmd_in_len, cmd_out, cmd_out_len);
1529 } else if (opcode == MLX5_CMD_OP_CREATE_CQ &&
1530 !is_apu_cq(dev, cmd_in)) {
1531 obj->flags |= DEVX_OBJ_FLAGS_CQ;
1532 obj->core_cq.comp = devx_cq_comp;
1533 err = mlx5_create_cq(dev->mdev, &obj->core_cq,
1534 cmd_in, cmd_in_len, cmd_out,
1535 cmd_out_len);
1536 } else {
1537 err = mlx5_cmd_do(dev->mdev, cmd_in, cmd_in_len,
1538 cmd_out, cmd_out_len);
1539 }
1540
1541 if (err == -EREMOTEIO)
1542 err2 = uverbs_copy_to(attrs,
1543 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT,
1544 cmd_out, cmd_out_len);
1545 if (err)
1546 goto obj_free;
1547
1548 if (opcode == MLX5_CMD_OP_ALLOC_FLOW_COUNTER) {
1549 u32 bulk = MLX5_GET(alloc_flow_counter_in,
1550 cmd_in,
1551 flow_counter_bulk_log_size);
1552
1553 if (bulk)
1554 bulk = 1 << bulk;
1555 else
1556 bulk = 128UL * MLX5_GET(alloc_flow_counter_in,
1557 cmd_in,
1558 flow_counter_bulk);
1559 obj->flow_counter_bulk_size = bulk;
1560 }
1561
1562 uobj->object = obj;
1563 INIT_LIST_HEAD(&obj->event_sub);
1564 obj->ib_dev = dev;
1565 devx_obj_build_destroy_cmd(cmd_in, cmd_out, obj->dinbox, &obj->dinlen,
1566 &obj_id);
1567 WARN_ON(obj->dinlen > MLX5_MAX_DESTROY_INBOX_SIZE_DW * sizeof(u32));
1568
1569 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, cmd_out, cmd_out_len);
1570 if (err)
1571 goto obj_destroy;
1572
1573 if (opcode == MLX5_CMD_OP_CREATE_GENERAL_OBJECT)
1574 obj_type = MLX5_GET(general_obj_in_cmd_hdr, cmd_in, obj_type);
1575 obj->obj_id = get_enc_obj_id(opcode | obj_type << 16, obj_id);
1576
1577 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY) {
1578 err = devx_handle_mkey_indirect(obj, dev, cmd_in, cmd_out);
1579 if (err)
1580 goto obj_destroy;
1581 }
1582 return 0;
1583
1584obj_destroy:
1585 if (obj->flags & DEVX_OBJ_FLAGS_DCT)
1586 mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct);
1587 else if (obj->flags & DEVX_OBJ_FLAGS_CQ)
1588 mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq);
1589 else
1590 mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, obj->dinlen, out,
1591 sizeof(out));
1592obj_free:
1593 kfree(obj);
1594 return err2 ?: err;
1595}
1596
1597static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_MODIFY)(
1598 struct uverbs_attr_bundle *attrs)
1599{
1600 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN);
1601 int cmd_out_len = uverbs_attr_get_len(attrs,
1602 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT);
1603 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs,
1604 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE);
1605 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1606 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1607 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device);
1608 void *cmd_out;
1609 int err, err2;
1610 int uid;
1611
1612 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1613 return -EINVAL;
1614
1615 uid = devx_get_uid(c, cmd_in);
1616 if (uid < 0)
1617 return uid;
1618
1619 if (!devx_is_obj_modify_cmd(cmd_in))
1620 return -EINVAL;
1621
1622 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in))
1623 return -EINVAL;
1624
1625 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1626 if (IS_ERR(cmd_out))
1627 return PTR_ERR(cmd_out);
1628
1629 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1630 devx_set_umem_valid(cmd_in);
1631
1632 err = mlx5_cmd_do(mdev->mdev, cmd_in,
1633 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN),
1634 cmd_out, cmd_out_len);
1635 if (err && err != -EREMOTEIO)
1636 return err;
1637
1638 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT,
1639 cmd_out, cmd_out_len);
1640
1641 return err2 ?: err;
1642}
1643
1644static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_QUERY)(
1645 struct uverbs_attr_bundle *attrs)
1646{
1647 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN);
1648 int cmd_out_len = uverbs_attr_get_len(attrs,
1649 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT);
1650 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs,
1651 MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE);
1652 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1653 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1654 void *cmd_out;
1655 int err, err2;
1656 int uid;
1657 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device);
1658
1659 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1660 return -EINVAL;
1661
1662 uid = devx_get_uid(c, cmd_in);
1663 if (uid < 0)
1664 return uid;
1665
1666 if (!devx_is_obj_query_cmd(cmd_in))
1667 return -EINVAL;
1668
1669 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in))
1670 return -EINVAL;
1671
1672 cmd_out = uverbs_zalloc(attrs, cmd_out_len);
1673 if (IS_ERR(cmd_out))
1674 return PTR_ERR(cmd_out);
1675
1676 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1677 err = mlx5_cmd_do(mdev->mdev, cmd_in,
1678 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN),
1679 cmd_out, cmd_out_len);
1680 if (err && err != -EREMOTEIO)
1681 return err;
1682
1683 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT,
1684 cmd_out, cmd_out_len);
1685
1686 return err2 ?: err;
1687}
1688
1689struct devx_async_event_queue {
1690 spinlock_t lock;
1691 wait_queue_head_t poll_wait;
1692 struct list_head event_list;
1693 atomic_t bytes_in_use;
1694 u8 is_destroyed:1;
1695};
1696
1697struct devx_async_cmd_event_file {
1698 struct ib_uobject uobj;
1699 struct devx_async_event_queue ev_queue;
1700 struct mlx5_async_ctx async_ctx;
1701};
1702
1703static void devx_init_event_queue(struct devx_async_event_queue *ev_queue)
1704{
1705 spin_lock_init(&ev_queue->lock);
1706 INIT_LIST_HEAD(&ev_queue->event_list);
1707 init_waitqueue_head(&ev_queue->poll_wait);
1708 atomic_set(&ev_queue->bytes_in_use, 0);
1709 ev_queue->is_destroyed = 0;
1710}
1711
1712static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)(
1713 struct uverbs_attr_bundle *attrs)
1714{
1715 struct devx_async_cmd_event_file *ev_file;
1716
1717 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1718 attrs, MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE);
1719 struct mlx5_ib_dev *mdev = mlx5_udata_to_mdev(&attrs->driver_udata);
1720
1721 ev_file = container_of(uobj, struct devx_async_cmd_event_file,
1722 uobj);
1723 devx_init_event_queue(&ev_file->ev_queue);
1724 mlx5_cmd_init_async_ctx(mdev->mdev, &ev_file->async_ctx);
1725 return 0;
1726}
1727
1728static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)(
1729 struct uverbs_attr_bundle *attrs)
1730{
1731 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1732 attrs, MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE);
1733 struct devx_async_event_file *ev_file;
1734 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1735 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1736 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
1737 u32 flags;
1738 int err;
1739
1740 err = uverbs_get_flags32(&flags, attrs,
1741 MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS,
1742 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA);
1743
1744 if (err)
1745 return err;
1746
1747 ev_file = container_of(uobj, struct devx_async_event_file,
1748 uobj);
1749 spin_lock_init(&ev_file->lock);
1750 INIT_LIST_HEAD(&ev_file->event_list);
1751 init_waitqueue_head(&ev_file->poll_wait);
1752 if (flags & MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA)
1753 ev_file->omit_data = 1;
1754 INIT_LIST_HEAD(&ev_file->subscribed_events_list);
1755 ev_file->dev = dev;
1756 get_device(&dev->ib_dev.dev);
1757 return 0;
1758}
1759
1760static void devx_query_callback(int status, struct mlx5_async_work *context)
1761{
1762 struct devx_async_data *async_data =
1763 container_of(context, struct devx_async_data, cb_work);
1764 struct devx_async_cmd_event_file *ev_file = async_data->ev_file;
1765 struct devx_async_event_queue *ev_queue = &ev_file->ev_queue;
1766 unsigned long flags;
1767
1768 /*
1769 * Note that if the struct devx_async_cmd_event_file uobj begins to be
1770 * destroyed it will block at mlx5_cmd_cleanup_async_ctx() until this
1771 * routine returns, ensuring that it always remains valid here.
1772 */
1773 spin_lock_irqsave(&ev_queue->lock, flags);
1774 list_add_tail(&async_data->list, &ev_queue->event_list);
1775 spin_unlock_irqrestore(&ev_queue->lock, flags);
1776
1777 wake_up_interruptible(&ev_queue->poll_wait);
1778}
1779
1780#define MAX_ASYNC_BYTES_IN_USE (1024 * 1024) /* 1MB */
1781
1782static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)(
1783 struct uverbs_attr_bundle *attrs)
1784{
1785 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs,
1786 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN);
1787 struct ib_uobject *uobj = uverbs_attr_get_uobject(
1788 attrs,
1789 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE);
1790 u16 cmd_out_len;
1791 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
1792 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
1793 struct ib_uobject *fd_uobj;
1794 int err;
1795 int uid;
1796 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device);
1797 struct devx_async_cmd_event_file *ev_file;
1798 struct devx_async_data *async_data;
1799
1800 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id))
1801 return -EINVAL;
1802
1803 uid = devx_get_uid(c, cmd_in);
1804 if (uid < 0)
1805 return uid;
1806
1807 if (!devx_is_obj_query_cmd(cmd_in))
1808 return -EINVAL;
1809
1810 err = uverbs_get_const(&cmd_out_len, attrs,
1811 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN);
1812 if (err)
1813 return err;
1814
1815 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in))
1816 return -EINVAL;
1817
1818 fd_uobj = uverbs_attr_get_uobject(attrs,
1819 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD);
1820 if (IS_ERR(fd_uobj))
1821 return PTR_ERR(fd_uobj);
1822
1823 ev_file = container_of(fd_uobj, struct devx_async_cmd_event_file,
1824 uobj);
1825
1826 if (atomic_add_return(cmd_out_len, &ev_file->ev_queue.bytes_in_use) >
1827 MAX_ASYNC_BYTES_IN_USE) {
1828 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use);
1829 return -EAGAIN;
1830 }
1831
1832 async_data = kvzalloc(struct_size(async_data, hdr.out_data,
1833 cmd_out_len), GFP_KERNEL);
1834 if (!async_data) {
1835 err = -ENOMEM;
1836 goto sub_bytes;
1837 }
1838
1839 err = uverbs_copy_from(&async_data->hdr.wr_id, attrs,
1840 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID);
1841 if (err)
1842 goto free_async;
1843
1844 async_data->cmd_out_len = cmd_out_len;
1845 async_data->mdev = mdev;
1846 async_data->ev_file = ev_file;
1847
1848 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid);
1849 err = mlx5_cmd_exec_cb(&ev_file->async_ctx, cmd_in,
1850 uverbs_attr_get_len(attrs,
1851 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN),
1852 async_data->hdr.out_data,
1853 async_data->cmd_out_len,
1854 devx_query_callback, &async_data->cb_work);
1855
1856 if (err)
1857 goto free_async;
1858
1859 return 0;
1860
1861free_async:
1862 kvfree(async_data);
1863sub_bytes:
1864 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use);
1865 return err;
1866}
1867
1868static void
1869subscribe_event_xa_dealloc(struct mlx5_devx_event_table *devx_event_table,
1870 u32 key_level1,
1871 bool is_level2,
1872 u32 key_level2)
1873{
1874 struct devx_event *event;
1875 struct devx_obj_event *xa_val_level2;
1876
1877 /* Level 1 is valid for future use, no need to free */
1878 if (!is_level2)
1879 return;
1880
1881 event = xa_load(&devx_event_table->event_xa, key_level1);
1882 WARN_ON(!event);
1883
1884 xa_val_level2 = xa_load(&event->object_ids,
1885 key_level2);
1886 if (list_empty(&xa_val_level2->obj_sub_list)) {
1887 xa_erase(&event->object_ids,
1888 key_level2);
1889 kfree_rcu(xa_val_level2, rcu);
1890 }
1891}
1892
1893static int
1894subscribe_event_xa_alloc(struct mlx5_devx_event_table *devx_event_table,
1895 u32 key_level1,
1896 bool is_level2,
1897 u32 key_level2)
1898{
1899 struct devx_obj_event *obj_event;
1900 struct devx_event *event;
1901 int err;
1902
1903 event = xa_load(&devx_event_table->event_xa, key_level1);
1904 if (!event) {
1905 event = kzalloc(sizeof(*event), GFP_KERNEL);
1906 if (!event)
1907 return -ENOMEM;
1908
1909 INIT_LIST_HEAD(&event->unaffiliated_list);
1910 xa_init(&event->object_ids);
1911
1912 err = xa_insert(&devx_event_table->event_xa,
1913 key_level1,
1914 event,
1915 GFP_KERNEL);
1916 if (err) {
1917 kfree(event);
1918 return err;
1919 }
1920 }
1921
1922 if (!is_level2)
1923 return 0;
1924
1925 obj_event = xa_load(&event->object_ids, key_level2);
1926 if (!obj_event) {
1927 obj_event = kzalloc(sizeof(*obj_event), GFP_KERNEL);
1928 if (!obj_event)
1929 /* Level1 is valid for future use, no need to free */
1930 return -ENOMEM;
1931
1932 err = xa_insert(&event->object_ids,
1933 key_level2,
1934 obj_event,
1935 GFP_KERNEL);
1936 if (err) {
1937 kfree(obj_event);
1938 return err;
1939 }
1940 INIT_LIST_HEAD(&obj_event->obj_sub_list);
1941 }
1942
1943 return 0;
1944}
1945
1946static bool is_valid_events_legacy(int num_events, u16 *event_type_num_list,
1947 struct devx_obj *obj)
1948{
1949 int i;
1950
1951 for (i = 0; i < num_events; i++) {
1952 if (obj) {
1953 if (!is_legacy_obj_event_num(event_type_num_list[i]))
1954 return false;
1955 } else if (!is_legacy_unaffiliated_event_num(
1956 event_type_num_list[i])) {
1957 return false;
1958 }
1959 }
1960
1961 return true;
1962}
1963
1964#define MAX_SUPP_EVENT_NUM 255
1965static bool is_valid_events(struct mlx5_core_dev *dev,
1966 int num_events, u16 *event_type_num_list,
1967 struct devx_obj *obj)
1968{
1969 __be64 *aff_events;
1970 __be64 *unaff_events;
1971 int mask_entry;
1972 int mask_bit;
1973 int i;
1974
1975 if (MLX5_CAP_GEN(dev, event_cap)) {
1976 aff_events = MLX5_CAP_DEV_EVENT(dev,
1977 user_affiliated_events);
1978 unaff_events = MLX5_CAP_DEV_EVENT(dev,
1979 user_unaffiliated_events);
1980 } else {
1981 return is_valid_events_legacy(num_events, event_type_num_list,
1982 obj);
1983 }
1984
1985 for (i = 0; i < num_events; i++) {
1986 if (event_type_num_list[i] > MAX_SUPP_EVENT_NUM)
1987 return false;
1988
1989 mask_entry = event_type_num_list[i] / 64;
1990 mask_bit = event_type_num_list[i] % 64;
1991
1992 if (obj) {
1993 /* CQ completion */
1994 if (event_type_num_list[i] == 0)
1995 continue;
1996
1997 if (!(be64_to_cpu(aff_events[mask_entry]) &
1998 (1ull << mask_bit)))
1999 return false;
2000
2001 continue;
2002 }
2003
2004 if (!(be64_to_cpu(unaff_events[mask_entry]) &
2005 (1ull << mask_bit)))
2006 return false;
2007 }
2008
2009 return true;
2010}
2011
2012#define MAX_NUM_EVENTS 16
2013static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)(
2014 struct uverbs_attr_bundle *attrs)
2015{
2016 struct ib_uobject *devx_uobj = uverbs_attr_get_uobject(
2017 attrs,
2018 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE);
2019 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
2020 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2021 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
2022 struct ib_uobject *fd_uobj;
2023 struct devx_obj *obj = NULL;
2024 struct devx_async_event_file *ev_file;
2025 struct mlx5_devx_event_table *devx_event_table = &dev->devx_event_table;
2026 u16 *event_type_num_list;
2027 struct devx_event_subscription *event_sub, *tmp_sub;
2028 struct list_head sub_list;
2029 int redirect_fd;
2030 bool use_eventfd = false;
2031 int num_events;
2032 u16 obj_type = 0;
2033 u64 cookie = 0;
2034 u32 obj_id = 0;
2035 int err;
2036 int i;
2037
2038 if (!c->devx_uid)
2039 return -EINVAL;
2040
2041 if (!IS_ERR(devx_uobj)) {
2042 obj = (struct devx_obj *)devx_uobj->object;
2043 if (obj)
2044 obj_id = get_dec_obj_id(obj->obj_id);
2045 }
2046
2047 fd_uobj = uverbs_attr_get_uobject(attrs,
2048 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE);
2049 if (IS_ERR(fd_uobj))
2050 return PTR_ERR(fd_uobj);
2051
2052 ev_file = container_of(fd_uobj, struct devx_async_event_file,
2053 uobj);
2054
2055 if (uverbs_attr_is_valid(attrs,
2056 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM)) {
2057 err = uverbs_copy_from(&redirect_fd, attrs,
2058 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM);
2059 if (err)
2060 return err;
2061
2062 use_eventfd = true;
2063 }
2064
2065 if (uverbs_attr_is_valid(attrs,
2066 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE)) {
2067 if (use_eventfd)
2068 return -EINVAL;
2069
2070 err = uverbs_copy_from(&cookie, attrs,
2071 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE);
2072 if (err)
2073 return err;
2074 }
2075
2076 num_events = uverbs_attr_ptr_get_array_size(
2077 attrs, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST,
2078 sizeof(u16));
2079
2080 if (num_events < 0)
2081 return num_events;
2082
2083 if (num_events > MAX_NUM_EVENTS)
2084 return -EINVAL;
2085
2086 event_type_num_list = uverbs_attr_get_alloced_ptr(attrs,
2087 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST);
2088
2089 if (!is_valid_events(dev->mdev, num_events, event_type_num_list, obj))
2090 return -EINVAL;
2091
2092 INIT_LIST_HEAD(&sub_list);
2093
2094 /* Protect from concurrent subscriptions to same XA entries to allow
2095 * both to succeed
2096 */
2097 mutex_lock(&devx_event_table->event_xa_lock);
2098 for (i = 0; i < num_events; i++) {
2099 u32 key_level1;
2100
2101 if (obj)
2102 obj_type = get_dec_obj_type(obj,
2103 event_type_num_list[i]);
2104 key_level1 = event_type_num_list[i] | obj_type << 16;
2105
2106 err = subscribe_event_xa_alloc(devx_event_table,
2107 key_level1,
2108 obj,
2109 obj_id);
2110 if (err)
2111 goto err;
2112
2113 event_sub = kzalloc(sizeof(*event_sub), GFP_KERNEL);
2114 if (!event_sub) {
2115 err = -ENOMEM;
2116 goto err;
2117 }
2118
2119 list_add_tail(&event_sub->event_list, &sub_list);
2120 uverbs_uobject_get(&ev_file->uobj);
2121 if (use_eventfd) {
2122 event_sub->eventfd =
2123 eventfd_ctx_fdget(redirect_fd);
2124
2125 if (IS_ERR(event_sub->eventfd)) {
2126 err = PTR_ERR(event_sub->eventfd);
2127 event_sub->eventfd = NULL;
2128 goto err;
2129 }
2130 }
2131
2132 event_sub->cookie = cookie;
2133 event_sub->ev_file = ev_file;
2134 /* May be needed upon cleanup the devx object/subscription */
2135 event_sub->xa_key_level1 = key_level1;
2136 event_sub->xa_key_level2 = obj_id;
2137 INIT_LIST_HEAD(&event_sub->obj_list);
2138 }
2139
2140 /* Once all the allocations and the XA data insertions were done we
2141 * can go ahead and add all the subscriptions to the relevant lists
2142 * without concern of a failure.
2143 */
2144 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) {
2145 struct devx_event *event;
2146 struct devx_obj_event *obj_event;
2147
2148 list_del_init(&event_sub->event_list);
2149
2150 spin_lock_irq(&ev_file->lock);
2151 list_add_tail_rcu(&event_sub->file_list,
2152 &ev_file->subscribed_events_list);
2153 spin_unlock_irq(&ev_file->lock);
2154
2155 event = xa_load(&devx_event_table->event_xa,
2156 event_sub->xa_key_level1);
2157 WARN_ON(!event);
2158
2159 if (!obj) {
2160 list_add_tail_rcu(&event_sub->xa_list,
2161 &event->unaffiliated_list);
2162 continue;
2163 }
2164
2165 obj_event = xa_load(&event->object_ids, obj_id);
2166 WARN_ON(!obj_event);
2167 list_add_tail_rcu(&event_sub->xa_list,
2168 &obj_event->obj_sub_list);
2169 list_add_tail_rcu(&event_sub->obj_list,
2170 &obj->event_sub);
2171 }
2172
2173 mutex_unlock(&devx_event_table->event_xa_lock);
2174 return 0;
2175
2176err:
2177 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) {
2178 list_del(&event_sub->event_list);
2179
2180 subscribe_event_xa_dealloc(devx_event_table,
2181 event_sub->xa_key_level1,
2182 obj,
2183 obj_id);
2184
2185 if (event_sub->eventfd)
2186 eventfd_ctx_put(event_sub->eventfd);
2187 uverbs_uobject_put(&event_sub->ev_file->uobj);
2188 kfree(event_sub);
2189 }
2190
2191 mutex_unlock(&devx_event_table->event_xa_lock);
2192 return err;
2193}
2194
2195static int devx_umem_get(struct mlx5_ib_dev *dev, struct ib_ucontext *ucontext,
2196 struct uverbs_attr_bundle *attrs,
2197 struct devx_umem *obj, u32 access_flags)
2198{
2199 u64 addr;
2200 size_t size;
2201 int err;
2202
2203 if (uverbs_copy_from(&addr, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR) ||
2204 uverbs_copy_from(&size, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_LEN))
2205 return -EFAULT;
2206
2207 err = ib_check_mr_access(&dev->ib_dev, access_flags);
2208 if (err)
2209 return err;
2210
2211 if (uverbs_attr_is_valid(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD)) {
2212 struct ib_umem_dmabuf *umem_dmabuf;
2213 int dmabuf_fd;
2214
2215 err = uverbs_get_raw_fd(&dmabuf_fd, attrs,
2216 MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD);
2217 if (err)
2218 return -EFAULT;
2219
2220 umem_dmabuf = ib_umem_dmabuf_get_pinned(
2221 &dev->ib_dev, addr, size, dmabuf_fd, access_flags);
2222 if (IS_ERR(umem_dmabuf))
2223 return PTR_ERR(umem_dmabuf);
2224 obj->umem = &umem_dmabuf->umem;
2225 } else {
2226 obj->umem = ib_umem_get(&dev->ib_dev, addr, size, access_flags);
2227 if (IS_ERR(obj->umem))
2228 return PTR_ERR(obj->umem);
2229 }
2230 return 0;
2231}
2232
2233static unsigned int devx_umem_find_best_pgsize(struct ib_umem *umem,
2234 unsigned long pgsz_bitmap)
2235{
2236 unsigned long page_size;
2237
2238 /* Don't bother checking larger page sizes as offset must be zero and
2239 * total DEVX umem length must be equal to total umem length.
2240 */
2241 pgsz_bitmap &= GENMASK_ULL(max_t(u64, order_base_2(umem->length),
2242 PAGE_SHIFT),
2243 MLX5_ADAPTER_PAGE_SHIFT);
2244 if (!pgsz_bitmap)
2245 return 0;
2246
2247 page_size = ib_umem_find_best_pgoff(umem, pgsz_bitmap, U64_MAX);
2248 if (!page_size)
2249 return 0;
2250
2251 /* If the page_size is less than the CPU page size then we can use the
2252 * offset and create a umem which is a subset of the page list.
2253 * For larger page sizes we can't be sure the DMA list reflects the
2254 * VA so we must ensure that the umem extent is exactly equal to the
2255 * page list. Reduce the page size until one of these cases is true.
2256 */
2257 while ((ib_umem_dma_offset(umem, page_size) != 0 ||
2258 (umem->length % page_size) != 0) &&
2259 page_size > PAGE_SIZE)
2260 page_size /= 2;
2261
2262 return page_size;
2263}
2264
2265static int devx_umem_reg_cmd_alloc(struct mlx5_ib_dev *dev,
2266 struct uverbs_attr_bundle *attrs,
2267 struct devx_umem *obj,
2268 struct devx_umem_reg_cmd *cmd,
2269 int access)
2270{
2271 unsigned long pgsz_bitmap;
2272 unsigned int page_size;
2273 __be64 *mtt;
2274 void *umem;
2275 int ret;
2276
2277 /*
2278 * If the user does not pass in pgsz_bitmap then the user promises not
2279 * to use umem_offset!=0 in any commands that allocate on top of the
2280 * umem.
2281 *
2282 * If the user wants to use a umem_offset then it must pass in
2283 * pgsz_bitmap which guides the maximum page size and thus maximum
2284 * object alignment inside the umem. See the PRM.
2285 *
2286 * Users are not allowed to use IOVA here, mkeys are not supported on
2287 * umem.
2288 */
2289 ret = uverbs_get_const_default(&pgsz_bitmap, attrs,
2290 MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP,
2291 GENMASK_ULL(63,
2292 min(PAGE_SHIFT, MLX5_ADAPTER_PAGE_SHIFT)));
2293 if (ret)
2294 return ret;
2295
2296 page_size = devx_umem_find_best_pgsize(obj->umem, pgsz_bitmap);
2297 if (!page_size)
2298 return -EINVAL;
2299
2300 cmd->inlen = MLX5_ST_SZ_BYTES(create_umem_in) +
2301 (MLX5_ST_SZ_BYTES(mtt) *
2302 ib_umem_num_dma_blocks(obj->umem, page_size));
2303 cmd->in = uverbs_zalloc(attrs, cmd->inlen);
2304 if (IS_ERR(cmd->in))
2305 return PTR_ERR(cmd->in);
2306
2307 umem = MLX5_ADDR_OF(create_umem_in, cmd->in, umem);
2308 mtt = (__be64 *)MLX5_ADDR_OF(umem, umem, mtt);
2309
2310 MLX5_SET(create_umem_in, cmd->in, opcode, MLX5_CMD_OP_CREATE_UMEM);
2311 MLX5_SET64(umem, umem, num_of_mtt,
2312 ib_umem_num_dma_blocks(obj->umem, page_size));
2313 MLX5_SET(umem, umem, log_page_size,
2314 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT);
2315 MLX5_SET(umem, umem, page_offset,
2316 ib_umem_dma_offset(obj->umem, page_size));
2317
2318 if (mlx5_umem_needs_ats(dev, obj->umem, access))
2319 MLX5_SET(umem, umem, ats, 1);
2320
2321 mlx5_ib_populate_pas(obj->umem, page_size, mtt,
2322 (obj->umem->writable ? MLX5_IB_MTT_WRITE : 0) |
2323 MLX5_IB_MTT_READ);
2324 return 0;
2325}
2326
2327static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_UMEM_REG)(
2328 struct uverbs_attr_bundle *attrs)
2329{
2330 struct devx_umem_reg_cmd cmd;
2331 struct devx_umem *obj;
2332 struct ib_uobject *uobj = uverbs_attr_get_uobject(
2333 attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE);
2334 u32 obj_id;
2335 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context(
2336 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2337 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device);
2338 int access_flags;
2339 int err;
2340
2341 if (!c->devx_uid)
2342 return -EINVAL;
2343
2344 err = uverbs_get_flags32(&access_flags, attrs,
2345 MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS,
2346 IB_ACCESS_LOCAL_WRITE |
2347 IB_ACCESS_REMOTE_WRITE |
2348 IB_ACCESS_REMOTE_READ |
2349 IB_ACCESS_RELAXED_ORDERING);
2350 if (err)
2351 return err;
2352
2353 obj = kzalloc(sizeof(struct devx_umem), GFP_KERNEL);
2354 if (!obj)
2355 return -ENOMEM;
2356
2357 err = devx_umem_get(dev, &c->ibucontext, attrs, obj, access_flags);
2358 if (err)
2359 goto err_obj_free;
2360
2361 err = devx_umem_reg_cmd_alloc(dev, attrs, obj, &cmd, access_flags);
2362 if (err)
2363 goto err_umem_release;
2364
2365 MLX5_SET(create_umem_in, cmd.in, uid, c->devx_uid);
2366 err = mlx5_cmd_exec(dev->mdev, cmd.in, cmd.inlen, cmd.out,
2367 sizeof(cmd.out));
2368 if (err)
2369 goto err_umem_release;
2370
2371 obj->mdev = dev->mdev;
2372 uobj->object = obj;
2373 devx_obj_build_destroy_cmd(cmd.in, cmd.out, obj->dinbox, &obj->dinlen, &obj_id);
2374 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE);
2375
2376 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, &obj_id,
2377 sizeof(obj_id));
2378 return err;
2379
2380err_umem_release:
2381 ib_umem_release(obj->umem);
2382err_obj_free:
2383 kfree(obj);
2384 return err;
2385}
2386
2387static int devx_umem_cleanup(struct ib_uobject *uobject,
2388 enum rdma_remove_reason why,
2389 struct uverbs_attr_bundle *attrs)
2390{
2391 struct devx_umem *obj = uobject->object;
2392 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2393 int err;
2394
2395 err = mlx5_cmd_exec(obj->mdev, obj->dinbox, obj->dinlen, out, sizeof(out));
2396 if (err)
2397 return err;
2398
2399 ib_umem_release(obj->umem);
2400 kfree(obj);
2401 return 0;
2402}
2403
2404static bool is_unaffiliated_event(struct mlx5_core_dev *dev,
2405 unsigned long event_type)
2406{
2407 __be64 *unaff_events;
2408 int mask_entry;
2409 int mask_bit;
2410
2411 if (!MLX5_CAP_GEN(dev, event_cap))
2412 return is_legacy_unaffiliated_event_num(event_type);
2413
2414 unaff_events = MLX5_CAP_DEV_EVENT(dev,
2415 user_unaffiliated_events);
2416 WARN_ON(event_type > MAX_SUPP_EVENT_NUM);
2417
2418 mask_entry = event_type / 64;
2419 mask_bit = event_type % 64;
2420
2421 if (!(be64_to_cpu(unaff_events[mask_entry]) & (1ull << mask_bit)))
2422 return false;
2423
2424 return true;
2425}
2426
2427static u32 devx_get_obj_id_from_event(unsigned long event_type, void *data)
2428{
2429 struct mlx5_eqe *eqe = data;
2430 u32 obj_id = 0;
2431
2432 switch (event_type) {
2433 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
2434 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
2435 case MLX5_EVENT_TYPE_PATH_MIG:
2436 case MLX5_EVENT_TYPE_COMM_EST:
2437 case MLX5_EVENT_TYPE_SQ_DRAINED:
2438 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
2439 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
2440 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
2441 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
2442 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
2443 obj_id = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
2444 break;
2445 case MLX5_EVENT_TYPE_XRQ_ERROR:
2446 obj_id = be32_to_cpu(eqe->data.xrq_err.type_xrqn) & 0xffffff;
2447 break;
2448 case MLX5_EVENT_TYPE_DCT_DRAINED:
2449 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION:
2450 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
2451 break;
2452 case MLX5_EVENT_TYPE_CQ_ERROR:
2453 obj_id = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
2454 break;
2455 default:
2456 obj_id = MLX5_GET(affiliated_event_header, &eqe->data, obj_id);
2457 break;
2458 }
2459
2460 return obj_id;
2461}
2462
2463static int deliver_event(struct devx_event_subscription *event_sub,
2464 const void *data)
2465{
2466 struct devx_async_event_file *ev_file;
2467 struct devx_async_event_data *event_data;
2468 unsigned long flags;
2469
2470 ev_file = event_sub->ev_file;
2471
2472 if (ev_file->omit_data) {
2473 spin_lock_irqsave(&ev_file->lock, flags);
2474 if (!list_empty(&event_sub->event_list) ||
2475 ev_file->is_destroyed) {
2476 spin_unlock_irqrestore(&ev_file->lock, flags);
2477 return 0;
2478 }
2479
2480 list_add_tail(&event_sub->event_list, &ev_file->event_list);
2481 spin_unlock_irqrestore(&ev_file->lock, flags);
2482 wake_up_interruptible(&ev_file->poll_wait);
2483 return 0;
2484 }
2485
2486 event_data = kzalloc(sizeof(*event_data) + sizeof(struct mlx5_eqe),
2487 GFP_ATOMIC);
2488 if (!event_data) {
2489 spin_lock_irqsave(&ev_file->lock, flags);
2490 ev_file->is_overflow_err = 1;
2491 spin_unlock_irqrestore(&ev_file->lock, flags);
2492 return -ENOMEM;
2493 }
2494
2495 event_data->hdr.cookie = event_sub->cookie;
2496 memcpy(event_data->hdr.out_data, data, sizeof(struct mlx5_eqe));
2497
2498 spin_lock_irqsave(&ev_file->lock, flags);
2499 if (!ev_file->is_destroyed)
2500 list_add_tail(&event_data->list, &ev_file->event_list);
2501 else
2502 kfree(event_data);
2503 spin_unlock_irqrestore(&ev_file->lock, flags);
2504 wake_up_interruptible(&ev_file->poll_wait);
2505
2506 return 0;
2507}
2508
2509static void dispatch_event_fd(struct list_head *fd_list,
2510 const void *data)
2511{
2512 struct devx_event_subscription *item;
2513
2514 list_for_each_entry_rcu(item, fd_list, xa_list) {
2515 if (item->eventfd)
2516 eventfd_signal(item->eventfd);
2517 else
2518 deliver_event(item, data);
2519 }
2520}
2521
2522static int devx_event_notifier(struct notifier_block *nb,
2523 unsigned long event_type, void *data)
2524{
2525 struct mlx5_devx_event_table *table;
2526 struct mlx5_ib_dev *dev;
2527 struct devx_event *event;
2528 struct devx_obj_event *obj_event;
2529 u16 obj_type = 0;
2530 bool is_unaffiliated;
2531 u32 obj_id;
2532
2533 /* Explicit filtering to kernel events which may occur frequently */
2534 if (event_type == MLX5_EVENT_TYPE_CMD ||
2535 event_type == MLX5_EVENT_TYPE_PAGE_REQUEST)
2536 return NOTIFY_OK;
2537
2538 table = container_of(nb, struct mlx5_devx_event_table, devx_nb.nb);
2539 dev = container_of(table, struct mlx5_ib_dev, devx_event_table);
2540 is_unaffiliated = is_unaffiliated_event(dev->mdev, event_type);
2541
2542 if (!is_unaffiliated)
2543 obj_type = get_event_obj_type(event_type, data);
2544
2545 rcu_read_lock();
2546 event = xa_load(&table->event_xa, event_type | (obj_type << 16));
2547 if (!event) {
2548 rcu_read_unlock();
2549 return NOTIFY_DONE;
2550 }
2551
2552 if (is_unaffiliated) {
2553 dispatch_event_fd(&event->unaffiliated_list, data);
2554 rcu_read_unlock();
2555 return NOTIFY_OK;
2556 }
2557
2558 obj_id = devx_get_obj_id_from_event(event_type, data);
2559 obj_event = xa_load(&event->object_ids, obj_id);
2560 if (!obj_event) {
2561 rcu_read_unlock();
2562 return NOTIFY_DONE;
2563 }
2564
2565 dispatch_event_fd(&obj_event->obj_sub_list, data);
2566
2567 rcu_read_unlock();
2568 return NOTIFY_OK;
2569}
2570
2571int mlx5_ib_devx_init(struct mlx5_ib_dev *dev)
2572{
2573 struct mlx5_devx_event_table *table = &dev->devx_event_table;
2574 int uid;
2575
2576 uid = mlx5_ib_devx_create(dev, false);
2577 if (uid > 0) {
2578 dev->devx_whitelist_uid = uid;
2579 xa_init(&table->event_xa);
2580 mutex_init(&table->event_xa_lock);
2581 MLX5_NB_INIT(&table->devx_nb, devx_event_notifier, NOTIFY_ANY);
2582 mlx5_eq_notifier_register(dev->mdev, &table->devx_nb);
2583 }
2584
2585 return 0;
2586}
2587
2588void mlx5_ib_devx_cleanup(struct mlx5_ib_dev *dev)
2589{
2590 struct mlx5_devx_event_table *table = &dev->devx_event_table;
2591 struct devx_event_subscription *sub, *tmp;
2592 struct devx_event *event;
2593 void *entry;
2594 unsigned long id;
2595
2596 if (dev->devx_whitelist_uid) {
2597 mlx5_eq_notifier_unregister(dev->mdev, &table->devx_nb);
2598 mutex_lock(&dev->devx_event_table.event_xa_lock);
2599 xa_for_each(&table->event_xa, id, entry) {
2600 event = entry;
2601 list_for_each_entry_safe(
2602 sub, tmp, &event->unaffiliated_list, xa_list)
2603 devx_cleanup_subscription(dev, sub);
2604 kfree(entry);
2605 }
2606 mutex_unlock(&dev->devx_event_table.event_xa_lock);
2607 xa_destroy(&table->event_xa);
2608
2609 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
2610 }
2611}
2612
2613static void devx_async_destroy_cb(int status, struct mlx5_async_work *context)
2614{
2615 struct mlx5_async_cmd *devx_out = container_of(context,
2616 struct mlx5_async_cmd, cb_work);
2617 struct devx_obj *obj = devx_out->uobject->object;
2618
2619 if (!status)
2620 obj->flags |= DEVX_OBJ_FLAGS_HW_FREED;
2621
2622 complete(&devx_out->comp);
2623}
2624
2625static void devx_async_destroy(struct mlx5_ib_dev *dev,
2626 struct mlx5_async_cmd *cmd)
2627{
2628 init_completion(&cmd->comp);
2629 cmd->err = mlx5_cmd_exec_cb(&dev->async_ctx, cmd->in, cmd->in_size,
2630 &cmd->out, sizeof(cmd->out),
2631 devx_async_destroy_cb, &cmd->cb_work);
2632}
2633
2634static void devx_wait_async_destroy(struct mlx5_async_cmd *cmd)
2635{
2636 if (!cmd->err)
2637 wait_for_completion(&cmd->comp);
2638 atomic_set(&cmd->uobject->usecnt, 0);
2639}
2640
2641void mlx5_ib_ufile_hw_cleanup(struct ib_uverbs_file *ufile)
2642{
2643 struct mlx5_async_cmd async_cmd[MAX_ASYNC_CMDS];
2644 struct ib_ucontext *ucontext = ufile->ucontext;
2645 struct ib_device *device = ucontext->device;
2646 struct mlx5_ib_dev *dev = to_mdev(device);
2647 struct ib_uobject *uobject;
2648 struct devx_obj *obj;
2649 int head = 0;
2650 int tail = 0;
2651
2652 list_for_each_entry(uobject, &ufile->uobjects, list) {
2653 WARN_ON(uverbs_try_lock_object(uobject, UVERBS_LOOKUP_WRITE));
2654
2655 /*
2656 * Currently we only support QP destruction, if other objects
2657 * are to be destroyed need to add type synchronization to the
2658 * cleanup algorithm and handle pre/post FW cleanup for the
2659 * new types if needed.
2660 */
2661 if (uobj_get_object_id(uobject) != MLX5_IB_OBJECT_DEVX_OBJ ||
2662 (get_dec_obj_type(uobject->object, MLX5_EVENT_TYPE_MAX) !=
2663 MLX5_OBJ_TYPE_QP)) {
2664 atomic_set(&uobject->usecnt, 0);
2665 continue;
2666 }
2667
2668 obj = uobject->object;
2669
2670 async_cmd[tail % MAX_ASYNC_CMDS].in = obj->dinbox;
2671 async_cmd[tail % MAX_ASYNC_CMDS].in_size = obj->dinlen;
2672 async_cmd[tail % MAX_ASYNC_CMDS].uobject = uobject;
2673
2674 devx_async_destroy(dev, &async_cmd[tail % MAX_ASYNC_CMDS]);
2675 tail++;
2676
2677 if (tail - head == MAX_ASYNC_CMDS) {
2678 devx_wait_async_destroy(&async_cmd[head % MAX_ASYNC_CMDS]);
2679 head++;
2680 }
2681 }
2682
2683 while (head != tail) {
2684 devx_wait_async_destroy(&async_cmd[head % MAX_ASYNC_CMDS]);
2685 head++;
2686 }
2687}
2688
2689static ssize_t devx_async_cmd_event_read(struct file *filp, char __user *buf,
2690 size_t count, loff_t *pos)
2691{
2692 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data;
2693 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue;
2694 struct devx_async_data *event;
2695 int ret = 0;
2696 size_t eventsz;
2697
2698 spin_lock_irq(&ev_queue->lock);
2699
2700 while (list_empty(&ev_queue->event_list)) {
2701 spin_unlock_irq(&ev_queue->lock);
2702
2703 if (filp->f_flags & O_NONBLOCK)
2704 return -EAGAIN;
2705
2706 if (wait_event_interruptible(
2707 ev_queue->poll_wait,
2708 (!list_empty(&ev_queue->event_list) ||
2709 ev_queue->is_destroyed))) {
2710 return -ERESTARTSYS;
2711 }
2712
2713 spin_lock_irq(&ev_queue->lock);
2714 if (ev_queue->is_destroyed) {
2715 spin_unlock_irq(&ev_queue->lock);
2716 return -EIO;
2717 }
2718 }
2719
2720 event = list_entry(ev_queue->event_list.next,
2721 struct devx_async_data, list);
2722 eventsz = event->cmd_out_len +
2723 sizeof(struct mlx5_ib_uapi_devx_async_cmd_hdr);
2724
2725 if (eventsz > count) {
2726 spin_unlock_irq(&ev_queue->lock);
2727 return -ENOSPC;
2728 }
2729
2730 list_del(ev_queue->event_list.next);
2731 spin_unlock_irq(&ev_queue->lock);
2732
2733 if (copy_to_user(buf, &event->hdr, eventsz))
2734 ret = -EFAULT;
2735 else
2736 ret = eventsz;
2737
2738 atomic_sub(event->cmd_out_len, &ev_queue->bytes_in_use);
2739 kvfree(event);
2740 return ret;
2741}
2742
2743static __poll_t devx_async_cmd_event_poll(struct file *filp,
2744 struct poll_table_struct *wait)
2745{
2746 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data;
2747 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue;
2748 __poll_t pollflags = 0;
2749
2750 poll_wait(filp, &ev_queue->poll_wait, wait);
2751
2752 spin_lock_irq(&ev_queue->lock);
2753 if (ev_queue->is_destroyed)
2754 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP;
2755 else if (!list_empty(&ev_queue->event_list))
2756 pollflags = EPOLLIN | EPOLLRDNORM;
2757 spin_unlock_irq(&ev_queue->lock);
2758
2759 return pollflags;
2760}
2761
2762static const struct file_operations devx_async_cmd_event_fops = {
2763 .owner = THIS_MODULE,
2764 .read = devx_async_cmd_event_read,
2765 .poll = devx_async_cmd_event_poll,
2766 .release = uverbs_uobject_fd_release,
2767};
2768
2769static ssize_t devx_async_event_read(struct file *filp, char __user *buf,
2770 size_t count, loff_t *pos)
2771{
2772 struct devx_async_event_file *ev_file = filp->private_data;
2773 struct devx_event_subscription *event_sub;
2774 struct devx_async_event_data *event;
2775 int ret = 0;
2776 size_t eventsz;
2777 bool omit_data;
2778 void *event_data;
2779
2780 omit_data = ev_file->omit_data;
2781
2782 spin_lock_irq(&ev_file->lock);
2783
2784 if (ev_file->is_overflow_err) {
2785 ev_file->is_overflow_err = 0;
2786 spin_unlock_irq(&ev_file->lock);
2787 return -EOVERFLOW;
2788 }
2789
2790
2791 while (list_empty(&ev_file->event_list)) {
2792 spin_unlock_irq(&ev_file->lock);
2793
2794 if (filp->f_flags & O_NONBLOCK)
2795 return -EAGAIN;
2796
2797 if (wait_event_interruptible(ev_file->poll_wait,
2798 (!list_empty(&ev_file->event_list) ||
2799 ev_file->is_destroyed))) {
2800 return -ERESTARTSYS;
2801 }
2802
2803 spin_lock_irq(&ev_file->lock);
2804 if (ev_file->is_destroyed) {
2805 spin_unlock_irq(&ev_file->lock);
2806 return -EIO;
2807 }
2808 }
2809
2810 if (omit_data) {
2811 event_sub = list_first_entry(&ev_file->event_list,
2812 struct devx_event_subscription,
2813 event_list);
2814 eventsz = sizeof(event_sub->cookie);
2815 event_data = &event_sub->cookie;
2816 } else {
2817 event = list_first_entry(&ev_file->event_list,
2818 struct devx_async_event_data, list);
2819 eventsz = sizeof(struct mlx5_eqe) +
2820 sizeof(struct mlx5_ib_uapi_devx_async_event_hdr);
2821 event_data = &event->hdr;
2822 }
2823
2824 if (eventsz > count) {
2825 spin_unlock_irq(&ev_file->lock);
2826 return -EINVAL;
2827 }
2828
2829 if (omit_data)
2830 list_del_init(&event_sub->event_list);
2831 else
2832 list_del(&event->list);
2833
2834 spin_unlock_irq(&ev_file->lock);
2835
2836 if (copy_to_user(buf, event_data, eventsz))
2837 /* This points to an application issue, not a kernel concern */
2838 ret = -EFAULT;
2839 else
2840 ret = eventsz;
2841
2842 if (!omit_data)
2843 kfree(event);
2844 return ret;
2845}
2846
2847static __poll_t devx_async_event_poll(struct file *filp,
2848 struct poll_table_struct *wait)
2849{
2850 struct devx_async_event_file *ev_file = filp->private_data;
2851 __poll_t pollflags = 0;
2852
2853 poll_wait(filp, &ev_file->poll_wait, wait);
2854
2855 spin_lock_irq(&ev_file->lock);
2856 if (ev_file->is_destroyed)
2857 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP;
2858 else if (!list_empty(&ev_file->event_list))
2859 pollflags = EPOLLIN | EPOLLRDNORM;
2860 spin_unlock_irq(&ev_file->lock);
2861
2862 return pollflags;
2863}
2864
2865static void devx_free_subscription(struct rcu_head *rcu)
2866{
2867 struct devx_event_subscription *event_sub =
2868 container_of(rcu, struct devx_event_subscription, rcu);
2869
2870 if (event_sub->eventfd)
2871 eventfd_ctx_put(event_sub->eventfd);
2872 uverbs_uobject_put(&event_sub->ev_file->uobj);
2873 kfree(event_sub);
2874}
2875
2876static const struct file_operations devx_async_event_fops = {
2877 .owner = THIS_MODULE,
2878 .read = devx_async_event_read,
2879 .poll = devx_async_event_poll,
2880 .release = uverbs_uobject_fd_release,
2881};
2882
2883static void devx_async_cmd_event_destroy_uobj(struct ib_uobject *uobj,
2884 enum rdma_remove_reason why)
2885{
2886 struct devx_async_cmd_event_file *comp_ev_file =
2887 container_of(uobj, struct devx_async_cmd_event_file,
2888 uobj);
2889 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue;
2890 struct devx_async_data *entry, *tmp;
2891
2892 spin_lock_irq(&ev_queue->lock);
2893 ev_queue->is_destroyed = 1;
2894 spin_unlock_irq(&ev_queue->lock);
2895 wake_up_interruptible(&ev_queue->poll_wait);
2896
2897 mlx5_cmd_cleanup_async_ctx(&comp_ev_file->async_ctx);
2898
2899 spin_lock_irq(&comp_ev_file->ev_queue.lock);
2900 list_for_each_entry_safe(entry, tmp,
2901 &comp_ev_file->ev_queue.event_list, list) {
2902 list_del(&entry->list);
2903 kvfree(entry);
2904 }
2905 spin_unlock_irq(&comp_ev_file->ev_queue.lock);
2906};
2907
2908static void devx_async_event_destroy_uobj(struct ib_uobject *uobj,
2909 enum rdma_remove_reason why)
2910{
2911 struct devx_async_event_file *ev_file =
2912 container_of(uobj, struct devx_async_event_file,
2913 uobj);
2914 struct devx_event_subscription *event_sub, *event_sub_tmp;
2915 struct mlx5_ib_dev *dev = ev_file->dev;
2916
2917 spin_lock_irq(&ev_file->lock);
2918 ev_file->is_destroyed = 1;
2919
2920 /* free the pending events allocation */
2921 if (ev_file->omit_data) {
2922 struct devx_event_subscription *event_sub, *tmp;
2923
2924 list_for_each_entry_safe(event_sub, tmp, &ev_file->event_list,
2925 event_list)
2926 list_del_init(&event_sub->event_list);
2927
2928 } else {
2929 struct devx_async_event_data *entry, *tmp;
2930
2931 list_for_each_entry_safe(entry, tmp, &ev_file->event_list,
2932 list) {
2933 list_del(&entry->list);
2934 kfree(entry);
2935 }
2936 }
2937
2938 spin_unlock_irq(&ev_file->lock);
2939 wake_up_interruptible(&ev_file->poll_wait);
2940
2941 mutex_lock(&dev->devx_event_table.event_xa_lock);
2942 /* delete the subscriptions which are related to this FD */
2943 list_for_each_entry_safe(event_sub, event_sub_tmp,
2944 &ev_file->subscribed_events_list, file_list) {
2945 devx_cleanup_subscription(dev, event_sub);
2946 list_del_rcu(&event_sub->file_list);
2947 /* subscription may not be used by the read API any more */
2948 call_rcu(&event_sub->rcu, devx_free_subscription);
2949 }
2950 mutex_unlock(&dev->devx_event_table.event_xa_lock);
2951
2952 put_device(&dev->ib_dev.dev);
2953};
2954
2955DECLARE_UVERBS_NAMED_METHOD(
2956 MLX5_IB_METHOD_DEVX_UMEM_REG,
2957 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE,
2958 MLX5_IB_OBJECT_DEVX_UMEM,
2959 UVERBS_ACCESS_NEW,
2960 UA_MANDATORY),
2961 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR,
2962 UVERBS_ATTR_TYPE(u64),
2963 UA_MANDATORY),
2964 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_LEN,
2965 UVERBS_ATTR_TYPE(u64),
2966 UA_MANDATORY),
2967 UVERBS_ATTR_RAW_FD(MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD,
2968 UA_OPTIONAL),
2969 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS,
2970 enum ib_access_flags),
2971 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP,
2972 u64),
2973 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID,
2974 UVERBS_ATTR_TYPE(u32),
2975 UA_MANDATORY));
2976
2977DECLARE_UVERBS_NAMED_METHOD_DESTROY(
2978 MLX5_IB_METHOD_DEVX_UMEM_DEREG,
2979 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE,
2980 MLX5_IB_OBJECT_DEVX_UMEM,
2981 UVERBS_ACCESS_DESTROY,
2982 UA_MANDATORY));
2983
2984DECLARE_UVERBS_NAMED_METHOD(
2985 MLX5_IB_METHOD_DEVX_QUERY_EQN,
2986 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC,
2987 UVERBS_ATTR_TYPE(u32),
2988 UA_MANDATORY),
2989 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN,
2990 UVERBS_ATTR_TYPE(u32),
2991 UA_MANDATORY));
2992
2993DECLARE_UVERBS_NAMED_METHOD(
2994 MLX5_IB_METHOD_DEVX_QUERY_UAR,
2995 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX,
2996 UVERBS_ATTR_TYPE(u32),
2997 UA_MANDATORY),
2998 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX,
2999 UVERBS_ATTR_TYPE(u32),
3000 UA_MANDATORY));
3001
3002DECLARE_UVERBS_NAMED_METHOD(
3003 MLX5_IB_METHOD_DEVX_OTHER,
3004 UVERBS_ATTR_PTR_IN(
3005 MLX5_IB_ATTR_DEVX_OTHER_CMD_IN,
3006 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
3007 UA_MANDATORY,
3008 UA_ALLOC_AND_COPY),
3009 UVERBS_ATTR_PTR_OUT(
3010 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT,
3011 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
3012 UA_MANDATORY));
3013
3014DECLARE_UVERBS_NAMED_METHOD(
3015 MLX5_IB_METHOD_DEVX_OBJ_CREATE,
3016 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE,
3017 MLX5_IB_OBJECT_DEVX_OBJ,
3018 UVERBS_ACCESS_NEW,
3019 UA_MANDATORY),
3020 UVERBS_ATTR_PTR_IN(
3021 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN,
3022 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
3023 UA_MANDATORY,
3024 UA_ALLOC_AND_COPY),
3025 UVERBS_ATTR_PTR_OUT(
3026 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT,
3027 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
3028 UA_MANDATORY));
3029
3030DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3031 MLX5_IB_METHOD_DEVX_OBJ_DESTROY,
3032 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE,
3033 MLX5_IB_OBJECT_DEVX_OBJ,
3034 UVERBS_ACCESS_DESTROY,
3035 UA_MANDATORY));
3036
3037DECLARE_UVERBS_NAMED_METHOD(
3038 MLX5_IB_METHOD_DEVX_OBJ_MODIFY,
3039 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE,
3040 UVERBS_IDR_ANY_OBJECT,
3041 UVERBS_ACCESS_READ,
3042 UA_MANDATORY),
3043 UVERBS_ATTR_PTR_IN(
3044 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN,
3045 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
3046 UA_MANDATORY,
3047 UA_ALLOC_AND_COPY),
3048 UVERBS_ATTR_PTR_OUT(
3049 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT,
3050 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
3051 UA_MANDATORY));
3052
3053DECLARE_UVERBS_NAMED_METHOD(
3054 MLX5_IB_METHOD_DEVX_OBJ_QUERY,
3055 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE,
3056 UVERBS_IDR_ANY_OBJECT,
3057 UVERBS_ACCESS_READ,
3058 UA_MANDATORY),
3059 UVERBS_ATTR_PTR_IN(
3060 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN,
3061 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
3062 UA_MANDATORY,
3063 UA_ALLOC_AND_COPY),
3064 UVERBS_ATTR_PTR_OUT(
3065 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT,
3066 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)),
3067 UA_MANDATORY));
3068
3069DECLARE_UVERBS_NAMED_METHOD(
3070 MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY,
3071 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE,
3072 UVERBS_IDR_ANY_OBJECT,
3073 UVERBS_ACCESS_READ,
3074 UA_MANDATORY),
3075 UVERBS_ATTR_PTR_IN(
3076 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN,
3077 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)),
3078 UA_MANDATORY,
3079 UA_ALLOC_AND_COPY),
3080 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN,
3081 u16, UA_MANDATORY),
3082 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD,
3083 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3084 UVERBS_ACCESS_READ,
3085 UA_MANDATORY),
3086 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID,
3087 UVERBS_ATTR_TYPE(u64),
3088 UA_MANDATORY));
3089
3090DECLARE_UVERBS_NAMED_METHOD(
3091 MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT,
3092 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE,
3093 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3094 UVERBS_ACCESS_READ,
3095 UA_MANDATORY),
3096 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE,
3097 MLX5_IB_OBJECT_DEVX_OBJ,
3098 UVERBS_ACCESS_READ,
3099 UA_OPTIONAL),
3100 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST,
3101 UVERBS_ATTR_MIN_SIZE(sizeof(u16)),
3102 UA_MANDATORY,
3103 UA_ALLOC_AND_COPY),
3104 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE,
3105 UVERBS_ATTR_TYPE(u64),
3106 UA_OPTIONAL),
3107 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM,
3108 UVERBS_ATTR_TYPE(u32),
3109 UA_OPTIONAL));
3110
3111DECLARE_UVERBS_GLOBAL_METHODS(MLX5_IB_OBJECT_DEVX,
3112 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OTHER),
3113 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_UAR),
3114 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_EQN),
3115 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT));
3116
3117DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_OBJ,
3118 UVERBS_TYPE_ALLOC_IDR(devx_obj_cleanup),
3119 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_CREATE),
3120 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_DESTROY),
3121 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_MODIFY),
3122 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_QUERY),
3123 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY));
3124
3125DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_UMEM,
3126 UVERBS_TYPE_ALLOC_IDR(devx_umem_cleanup),
3127 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_REG),
3128 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_DEREG));
3129
3130
3131DECLARE_UVERBS_NAMED_METHOD(
3132 MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC,
3133 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE,
3134 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3135 UVERBS_ACCESS_NEW,
3136 UA_MANDATORY));
3137
3138DECLARE_UVERBS_NAMED_OBJECT(
3139 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3140 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_cmd_event_file),
3141 devx_async_cmd_event_destroy_uobj,
3142 &devx_async_cmd_event_fops, "[devx_async_cmd]",
3143 O_RDONLY),
3144 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC));
3145
3146DECLARE_UVERBS_NAMED_METHOD(
3147 MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC,
3148 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE,
3149 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3150 UVERBS_ACCESS_NEW,
3151 UA_MANDATORY),
3152 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS,
3153 enum mlx5_ib_uapi_devx_create_event_channel_flags,
3154 UA_MANDATORY));
3155
3156DECLARE_UVERBS_NAMED_OBJECT(
3157 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3158 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_event_file),
3159 devx_async_event_destroy_uobj,
3160 &devx_async_event_fops, "[devx_async_event]",
3161 O_RDONLY),
3162 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC));
3163
3164static bool devx_is_supported(struct ib_device *device)
3165{
3166 struct mlx5_ib_dev *dev = to_mdev(device);
3167
3168 return MLX5_CAP_GEN(dev->mdev, log_max_uctx);
3169}
3170
3171const struct uapi_definition mlx5_ib_devx_defs[] = {
3172 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3173 MLX5_IB_OBJECT_DEVX,
3174 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3175 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3176 MLX5_IB_OBJECT_DEVX_OBJ,
3177 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3178 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3179 MLX5_IB_OBJECT_DEVX_UMEM,
3180 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3181 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3182 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
3183 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3184 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
3185 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
3186 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)),
3187 {},
3188};