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1/*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/ethtool.h>
42#include <linux/mutex.h>
43#include <linux/list.h>
44#include <linux/rculist.h>
45#include <linux/spinlock.h>
46#include <linux/pci.h>
47#include <net/dcbnl.h>
48#include <net/ipv6.h>
49#include <net/addrconf.h>
50#include <linux/if_ether.h>
51#include <linux/auxiliary_bus.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/ib_user_verbs.h>
55#include <rdma/ib_umem.h>
56#include <rdma/ib_addr.h>
57#include <linux/hashtable.h>
58
59#include "bnxt_ulp.h"
60#include "roce_hsi.h"
61#include "qplib_res.h"
62#include "qplib_sp.h"
63#include "qplib_fp.h"
64#include "qplib_rcfw.h"
65#include "bnxt_re.h"
66#include "ib_verbs.h"
67#include <rdma/bnxt_re-abi.h>
68#include "bnxt.h"
69#include "hw_counters.h"
70
71static char version[] =
72 BNXT_RE_DESC "\n";
73
74MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
75MODULE_DESCRIPTION(BNXT_RE_DESC);
76MODULE_LICENSE("Dual BSD/GPL");
77
78/* globals */
79static DEFINE_MUTEX(bnxt_re_mutex);
80
81static void bnxt_re_stop_irq(void *handle);
82static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev);
83static int bnxt_re_netdev_event(struct notifier_block *notifier,
84 unsigned long event, void *ptr);
85static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev);
86static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev);
87static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
88
89static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
90 u32 *offset);
91static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
92{
93 struct bnxt_qplib_chip_ctx *cctx;
94 struct bnxt_en_dev *en_dev;
95 struct bnxt_qplib_res *res;
96 u32 l2db_len = 0;
97 u32 offset = 0;
98 u32 barlen;
99 int rc;
100
101 res = &rdev->qplib_res;
102 en_dev = rdev->en_dev;
103 cctx = rdev->chip_ctx;
104
105 /* Issue qcfg */
106 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
107 if (rc)
108 dev_info(rdev_to_dev(rdev),
109 "Couldn't get DB bar size, Low latency framework is disabled\n");
110 /* set register offsets for both UC and WC */
111 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
112 res->dpi_tbl.ucreg.offset = offset;
113 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
114 } else {
115 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
116 BNXT_QPLIB_DBR_PF_DB_OFFSET;
117 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
118 }
119
120 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
121 * is equal to the DB-Bar actual size. This indicates that L2
122 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
123 * in such cases and DB-push will be disabled.
124 */
125 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
126 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
127 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
128 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
129 }
130}
131
132static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode)
133{
134 struct bnxt_qplib_chip_ctx *cctx;
135
136 cctx = rdev->chip_ctx;
137 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
138 mode : BNXT_QPLIB_WQE_MODE_STATIC;
139 if (bnxt_re_hwrm_qcaps(rdev))
140 dev_err(rdev_to_dev(rdev),
141 "Failed to query hwrm qcaps\n");
142 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx))
143 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;
144}
145
146static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
147{
148 struct bnxt_qplib_chip_ctx *chip_ctx;
149
150 if (!rdev->chip_ctx)
151 return;
152 chip_ctx = rdev->chip_ctx;
153 rdev->chip_ctx = NULL;
154 rdev->rcfw.res = NULL;
155 rdev->qplib_res.cctx = NULL;
156 rdev->qplib_res.pdev = NULL;
157 rdev->qplib_res.netdev = NULL;
158 kfree(chip_ctx);
159}
160
161static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode)
162{
163 struct bnxt_qplib_chip_ctx *chip_ctx;
164 struct bnxt_en_dev *en_dev;
165 int rc;
166
167 en_dev = rdev->en_dev;
168
169 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
170 if (!chip_ctx)
171 return -ENOMEM;
172 chip_ctx->chip_num = en_dev->chip_num;
173 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
174
175 rdev->chip_ctx = chip_ctx;
176 /* rest members to follow eventually */
177
178 rdev->qplib_res.cctx = rdev->chip_ctx;
179 rdev->rcfw.res = &rdev->qplib_res;
180 rdev->qplib_res.dattr = &rdev->dev_attr;
181 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
182
183 bnxt_re_set_drv_mode(rdev, wqe_mode);
184
185 bnxt_re_set_db_offset(rdev);
186 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
187 if (rc)
188 return rc;
189
190 if (bnxt_qplib_determine_atomics(en_dev->pdev))
191 ibdev_info(&rdev->ibdev,
192 "platform doesn't support global atomics.");
193 return 0;
194}
195
196/* SR-IOV helper functions */
197
198static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
199{
200 if (BNXT_EN_VF(rdev->en_dev))
201 rdev->is_virtfn = 1;
202}
203
204/* Set the maximum number of each resource that the driver actually wants
205 * to allocate. This may be up to the maximum number the firmware has
206 * reserved for the function. The driver may choose to allocate fewer
207 * resources than the firmware maximum.
208 */
209static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
210{
211 struct bnxt_qplib_dev_attr *attr;
212 struct bnxt_qplib_ctx *ctx;
213 int i;
214
215 attr = &rdev->dev_attr;
216 ctx = &rdev->qplib_ctx;
217
218 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
219 attr->max_qp);
220 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
221 /* Use max_mr from fw since max_mrw does not get set */
222 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
223 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
224 attr->max_srq);
225 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
226 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
227 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
228 rdev->qplib_ctx.tqm_ctx.qcount[i] =
229 rdev->dev_attr.tqm_alloc_reqs[i];
230}
231
232static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
233{
234 struct bnxt_qplib_vf_res *vf_res;
235 u32 mrws = 0;
236 u32 vf_pct;
237 u32 nvfs;
238
239 vf_res = &qplib_ctx->vf_res;
240 /*
241 * Reserve a set of resources for the PF. Divide the remaining
242 * resources among the VFs
243 */
244 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
245 nvfs = num_vf;
246 num_vf = 100 * num_vf;
247 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
248 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
249 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
250 /*
251 * The driver allows many more MRs than other resources. If the
252 * firmware does also, then reserve a fixed amount for the PF and
253 * divide the rest among VFs. VFs may use many MRs for NFS
254 * mounts, ISER, NVME applications, etc. If the firmware severely
255 * restricts the number of MRs, then let PF have half and divide
256 * the rest among VFs, as for the other resource types.
257 */
258 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
259 mrws = qplib_ctx->mrw_count * vf_pct;
260 nvfs = num_vf;
261 } else {
262 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
263 }
264 vf_res->max_mrw_per_vf = (mrws / nvfs);
265 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
266}
267
268static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
269{
270 u32 num_vfs;
271
272 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
273 bnxt_re_limit_pf_res(rdev);
274
275 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
276 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
277 if (num_vfs)
278 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
279}
280
281static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
282{
283 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
284 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
285 bnxt_re_set_resource_limits(rdev);
286 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
287 &rdev->qplib_ctx);
288 }
289}
290
291static void bnxt_re_shutdown(struct auxiliary_device *adev)
292{
293 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
294
295 if (!rdev)
296 return;
297 ib_unregister_device(&rdev->ibdev);
298 bnxt_re_dev_uninit(rdev);
299}
300
301static void bnxt_re_stop_irq(void *handle)
302{
303 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
304 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
305 struct bnxt_qplib_nq *nq;
306 int indx;
307
308 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) {
309 nq = &rdev->nq[indx - 1];
310 bnxt_qplib_nq_stop_irq(nq, false);
311 }
312
313 bnxt_qplib_rcfw_stop_irq(rcfw, false);
314}
315
316static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
317{
318 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
319 struct bnxt_msix_entry *msix_ent = rdev->en_dev->msix_entries;
320 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
321 struct bnxt_qplib_nq *nq;
322 int indx, rc;
323
324 if (!ent) {
325 /* Not setting the f/w timeout bit in rcfw.
326 * During the driver unload the first command
327 * to f/w will timeout and that will set the
328 * timeout bit.
329 */
330 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
331 return;
332 }
333
334 /* Vectors may change after restart, so update with new vectors
335 * in device sctructure.
336 */
337 for (indx = 0; indx < rdev->num_msix; indx++)
338 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector;
339
340 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
341 false);
342 if (rc) {
343 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
344 return;
345 }
346 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) {
347 nq = &rdev->nq[indx - 1];
348 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
349 msix_ent[indx].vector, false);
350 if (rc) {
351 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
352 indx - 1);
353 return;
354 }
355 }
356}
357
358static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
359 .ulp_irq_stop = bnxt_re_stop_irq,
360 .ulp_irq_restart = bnxt_re_start_irq
361};
362
363/* RoCE -> Net driver */
364
365static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
366{
367 struct bnxt_en_dev *en_dev;
368 int rc;
369
370 en_dev = rdev->en_dev;
371
372 rc = bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev);
373 if (!rc)
374 rdev->qplib_res.pdev = rdev->en_dev->pdev;
375 return rc;
376}
377
378static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
379{
380 hdr->req_type = cpu_to_le16(opcd);
381 hdr->cmpl_ring = cpu_to_le16(-1);
382 hdr->target_id = cpu_to_le16(-1);
383}
384
385static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
386 int msg_len, void *resp, int resp_max_len,
387 int timeout)
388{
389 fw_msg->msg = msg;
390 fw_msg->msg_len = msg_len;
391 fw_msg->resp = resp;
392 fw_msg->resp_max_len = resp_max_len;
393 fw_msg->timeout = timeout;
394}
395
396/* Query device config using common hwrm */
397static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
398 u32 *offset)
399{
400 struct bnxt_en_dev *en_dev = rdev->en_dev;
401 struct hwrm_func_qcfg_output resp = {0};
402 struct hwrm_func_qcfg_input req = {0};
403 struct bnxt_fw_msg fw_msg = {};
404 int rc;
405
406 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
407 req.fid = cpu_to_le16(0xffff);
408 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
409 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
410 rc = bnxt_send_msg(en_dev, &fw_msg);
411 if (!rc) {
412 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
413 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
414 }
415 return rc;
416}
417
418/* Query function capabilities using common hwrm */
419int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
420{
421 struct bnxt_en_dev *en_dev = rdev->en_dev;
422 struct hwrm_func_qcaps_output resp = {};
423 struct hwrm_func_qcaps_input req = {};
424 struct bnxt_qplib_chip_ctx *cctx;
425 struct bnxt_fw_msg fw_msg = {};
426 int rc;
427
428 cctx = rdev->chip_ctx;
429 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
430 req.fid = cpu_to_le16(0xffff);
431 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
432 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
433
434 rc = bnxt_send_msg(en_dev, &fw_msg);
435 if (rc)
436 return rc;
437 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
438
439 cctx->modes.dbr_pacing =
440 le32_to_cpu(resp.flags_ext2) &
441 FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED;
442 return 0;
443}
444
445static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
446{
447 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
448 struct hwrm_func_dbr_pacing_qcfg_input req = {};
449 struct bnxt_en_dev *en_dev = rdev->en_dev;
450 struct bnxt_qplib_chip_ctx *cctx;
451 struct bnxt_fw_msg fw_msg = {};
452 int rc;
453
454 cctx = rdev->chip_ctx;
455 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
456 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
457 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
458 rc = bnxt_send_msg(en_dev, &fw_msg);
459 if (rc)
460 return rc;
461
462 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
463 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
464 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
465 cctx->dbr_stat_db_fifo =
466 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
467 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
468 return 0;
469}
470
471/* Update the pacing tunable parameters to the default values */
472static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
473{
474 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
475
476 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
477 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
478 pacing_data->alarm_th =
479 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
480}
481
482static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
483{
484 u32 read_val, fifo_occup;
485
486 /* loop shouldn't run infintely as the occupancy usually goes
487 * below pacing algo threshold as soon as pacing kicks in.
488 */
489 while (1) {
490 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
491 fifo_occup = BNXT_RE_MAX_FIFO_DEPTH -
492 ((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >>
493 BNXT_RE_DB_FIFO_ROOM_SHIFT);
494 /* Fifo occupancy cannot be greater the MAX FIFO depth */
495 if (fifo_occup > BNXT_RE_MAX_FIFO_DEPTH)
496 break;
497
498 if (fifo_occup < rdev->qplib_res.pacing_data->pacing_th)
499 break;
500 }
501}
502
503static void bnxt_re_db_fifo_check(struct work_struct *work)
504{
505 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
506 dbq_fifo_check_work);
507 struct bnxt_qplib_db_pacing_data *pacing_data;
508 u32 pacing_save;
509
510 if (!mutex_trylock(&rdev->pacing.dbq_lock))
511 return;
512 pacing_data = rdev->qplib_res.pacing_data;
513 pacing_save = rdev->pacing.do_pacing_save;
514 __wait_for_fifo_occupancy_below_th(rdev);
515 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
516 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
517 /* Double the do_pacing value during the congestion */
518 pacing_save = pacing_save << 1;
519 } else {
520 /*
521 * when a new congestion is detected increase the do_pacing
522 * by 8 times. And also increase the pacing_th by 4 times. The
523 * reason to increase pacing_th is to give more space for the
524 * queue to oscillate down without getting empty, but also more
525 * room for the queue to increase without causing another alarm.
526 */
527 pacing_save = pacing_save << 3;
528 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
529 }
530
531 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
532 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
533
534 pacing_data->do_pacing = pacing_save;
535 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
536 pacing_data->alarm_th =
537 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
538 schedule_delayed_work(&rdev->dbq_pacing_work,
539 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
540 rdev->stats.pacing.alerts++;
541 mutex_unlock(&rdev->pacing.dbq_lock);
542}
543
544static void bnxt_re_pacing_timer_exp(struct work_struct *work)
545{
546 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
547 dbq_pacing_work.work);
548 struct bnxt_qplib_db_pacing_data *pacing_data;
549 u32 read_val, fifo_occup;
550
551 if (!mutex_trylock(&rdev->pacing.dbq_lock))
552 return;
553
554 pacing_data = rdev->qplib_res.pacing_data;
555 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
556 fifo_occup = BNXT_RE_MAX_FIFO_DEPTH -
557 ((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >>
558 BNXT_RE_DB_FIFO_ROOM_SHIFT);
559
560 if (fifo_occup > pacing_data->pacing_th)
561 goto restart_timer;
562
563 /*
564 * Instead of immediately going back to the default do_pacing
565 * reduce it by 1/8 times and restart the timer.
566 */
567 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
568 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
569 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
570 bnxt_re_set_default_pacing_data(rdev);
571 rdev->stats.pacing.complete++;
572 goto dbq_unlock;
573 }
574
575restart_timer:
576 schedule_delayed_work(&rdev->dbq_pacing_work,
577 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
578 rdev->stats.pacing.resched++;
579dbq_unlock:
580 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
581 mutex_unlock(&rdev->pacing.dbq_lock);
582}
583
584void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
585{
586 struct bnxt_qplib_db_pacing_data *pacing_data;
587
588 if (!rdev->pacing.dbr_pacing)
589 return;
590 mutex_lock(&rdev->pacing.dbq_lock);
591 pacing_data = rdev->qplib_res.pacing_data;
592
593 /*
594 * Increase the alarm_th to max so that other user lib instances do not
595 * keep alerting the driver.
596 */
597 pacing_data->alarm_th = BNXT_RE_MAX_FIFO_DEPTH;
598 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
599 cancel_work_sync(&rdev->dbq_fifo_check_work);
600 schedule_work(&rdev->dbq_fifo_check_work);
601 mutex_unlock(&rdev->pacing.dbq_lock);
602}
603
604static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
605{
606 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev))
607 return -EIO;
608
609 /* Allocate a page for app use */
610 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
611 if (!rdev->pacing.dbr_page)
612 return -ENOMEM;
613
614 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
615 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
616
617 /* MAP HW window 2 for reading db fifo depth */
618 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
619 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
620 rdev->pacing.dbr_db_fifo_reg_off =
621 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
622 BNXT_RE_GRC_FIFO_REG_BASE;
623 rdev->pacing.dbr_bar_addr =
624 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
625
626 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
627 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
628 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
629 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
630 rdev->qplib_res.pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH;
631 rdev->qplib_res.pacing_data->fifo_room_mask = BNXT_RE_DB_FIFO_ROOM_MASK;
632 rdev->qplib_res.pacing_data->fifo_room_shift = BNXT_RE_DB_FIFO_ROOM_SHIFT;
633 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
634 bnxt_re_set_default_pacing_data(rdev);
635 /* Initialize worker for DBR Pacing */
636 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
637 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
638 return 0;
639}
640
641static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
642{
643 cancel_work_sync(&rdev->dbq_fifo_check_work);
644 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
645 if (rdev->pacing.dbr_page)
646 free_page((u64)rdev->pacing.dbr_page);
647
648 rdev->pacing.dbr_page = NULL;
649 rdev->pacing.dbr_pacing = false;
650}
651
652static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
653 u16 fw_ring_id, int type)
654{
655 struct bnxt_en_dev *en_dev;
656 struct hwrm_ring_free_input req = {};
657 struct hwrm_ring_free_output resp;
658 struct bnxt_fw_msg fw_msg = {};
659 int rc = -EINVAL;
660
661 if (!rdev)
662 return rc;
663
664 en_dev = rdev->en_dev;
665
666 if (!en_dev)
667 return rc;
668
669 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
670 return 0;
671
672 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
673 req.ring_type = type;
674 req.ring_id = cpu_to_le16(fw_ring_id);
675 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
676 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
677 rc = bnxt_send_msg(en_dev, &fw_msg);
678 if (rc)
679 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
680 req.ring_id, rc);
681 return rc;
682}
683
684static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
685 struct bnxt_re_ring_attr *ring_attr,
686 u16 *fw_ring_id)
687{
688 struct bnxt_en_dev *en_dev = rdev->en_dev;
689 struct hwrm_ring_alloc_input req = {};
690 struct hwrm_ring_alloc_output resp;
691 struct bnxt_fw_msg fw_msg = {};
692 int rc = -EINVAL;
693
694 if (!en_dev)
695 return rc;
696
697 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
698 req.enables = 0;
699 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
700 if (ring_attr->pages > 1) {
701 /* Page size is in log2 units */
702 req.page_size = BNXT_PAGE_SHIFT;
703 req.page_tbl_depth = 1;
704 }
705 req.fbo = 0;
706 /* Association of ring index with doorbell index and MSIX number */
707 req.logical_id = cpu_to_le16(ring_attr->lrid);
708 req.length = cpu_to_le32(ring_attr->depth + 1);
709 req.ring_type = ring_attr->type;
710 req.int_mode = ring_attr->mode;
711 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
712 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
713 rc = bnxt_send_msg(en_dev, &fw_msg);
714 if (!rc)
715 *fw_ring_id = le16_to_cpu(resp.ring_id);
716
717 return rc;
718}
719
720static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
721 u32 fw_stats_ctx_id)
722{
723 struct bnxt_en_dev *en_dev = rdev->en_dev;
724 struct hwrm_stat_ctx_free_input req = {};
725 struct hwrm_stat_ctx_free_output resp = {};
726 struct bnxt_fw_msg fw_msg = {};
727 int rc = -EINVAL;
728
729 if (!en_dev)
730 return rc;
731
732 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
733 return 0;
734
735 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
736 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
737 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
738 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
739 rc = bnxt_send_msg(en_dev, &fw_msg);
740 if (rc)
741 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
742 rc);
743
744 return rc;
745}
746
747static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
748 dma_addr_t dma_map,
749 u32 *fw_stats_ctx_id)
750{
751 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
752 struct hwrm_stat_ctx_alloc_output resp = {};
753 struct hwrm_stat_ctx_alloc_input req = {};
754 struct bnxt_en_dev *en_dev = rdev->en_dev;
755 struct bnxt_fw_msg fw_msg = {};
756 int rc = -EINVAL;
757
758 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
759
760 if (!en_dev)
761 return rc;
762
763 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
764 req.update_period_ms = cpu_to_le32(1000);
765 req.stats_dma_addr = cpu_to_le64(dma_map);
766 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
767 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
768 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
769 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
770 rc = bnxt_send_msg(en_dev, &fw_msg);
771 if (!rc)
772 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
773
774 return rc;
775}
776
777static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
778{
779}
780
781/* Device */
782
783static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
784{
785 struct ib_device *ibdev =
786 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE);
787 if (!ibdev)
788 return NULL;
789
790 return container_of(ibdev, struct bnxt_re_dev, ibdev);
791}
792
793static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
794 char *buf)
795{
796 struct bnxt_re_dev *rdev =
797 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
798
799 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
800}
801static DEVICE_ATTR_RO(hw_rev);
802
803static ssize_t hca_type_show(struct device *device,
804 struct device_attribute *attr, char *buf)
805{
806 struct bnxt_re_dev *rdev =
807 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
808
809 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
810}
811static DEVICE_ATTR_RO(hca_type);
812
813static struct attribute *bnxt_re_attributes[] = {
814 &dev_attr_hw_rev.attr,
815 &dev_attr_hca_type.attr,
816 NULL
817};
818
819static const struct attribute_group bnxt_re_dev_attr_group = {
820 .attrs = bnxt_re_attributes,
821};
822
823static const struct ib_device_ops bnxt_re_dev_ops = {
824 .owner = THIS_MODULE,
825 .driver_id = RDMA_DRIVER_BNXT_RE,
826 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
827
828 .add_gid = bnxt_re_add_gid,
829 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
830 .alloc_mr = bnxt_re_alloc_mr,
831 .alloc_pd = bnxt_re_alloc_pd,
832 .alloc_ucontext = bnxt_re_alloc_ucontext,
833 .create_ah = bnxt_re_create_ah,
834 .create_cq = bnxt_re_create_cq,
835 .create_qp = bnxt_re_create_qp,
836 .create_srq = bnxt_re_create_srq,
837 .create_user_ah = bnxt_re_create_ah,
838 .dealloc_pd = bnxt_re_dealloc_pd,
839 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
840 .del_gid = bnxt_re_del_gid,
841 .dereg_mr = bnxt_re_dereg_mr,
842 .destroy_ah = bnxt_re_destroy_ah,
843 .destroy_cq = bnxt_re_destroy_cq,
844 .destroy_qp = bnxt_re_destroy_qp,
845 .destroy_srq = bnxt_re_destroy_srq,
846 .device_group = &bnxt_re_dev_attr_group,
847 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
848 .get_dev_fw_str = bnxt_re_query_fw_str,
849 .get_dma_mr = bnxt_re_get_dma_mr,
850 .get_hw_stats = bnxt_re_ib_get_hw_stats,
851 .get_link_layer = bnxt_re_get_link_layer,
852 .get_port_immutable = bnxt_re_get_port_immutable,
853 .map_mr_sg = bnxt_re_map_mr_sg,
854 .mmap = bnxt_re_mmap,
855 .mmap_free = bnxt_re_mmap_free,
856 .modify_qp = bnxt_re_modify_qp,
857 .modify_srq = bnxt_re_modify_srq,
858 .poll_cq = bnxt_re_poll_cq,
859 .post_recv = bnxt_re_post_recv,
860 .post_send = bnxt_re_post_send,
861 .post_srq_recv = bnxt_re_post_srq_recv,
862 .query_ah = bnxt_re_query_ah,
863 .query_device = bnxt_re_query_device,
864 .query_pkey = bnxt_re_query_pkey,
865 .query_port = bnxt_re_query_port,
866 .query_qp = bnxt_re_query_qp,
867 .query_srq = bnxt_re_query_srq,
868 .reg_user_mr = bnxt_re_reg_user_mr,
869 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
870 .req_notify_cq = bnxt_re_req_notify_cq,
871 .resize_cq = bnxt_re_resize_cq,
872 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
873 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
874 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
875 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
876 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
877 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
878};
879
880static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
881{
882 struct ib_device *ibdev = &rdev->ibdev;
883 int ret;
884
885 /* ib device init */
886 ibdev->node_type = RDMA_NODE_IB_CA;
887 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
888 strlen(BNXT_RE_DESC) + 5);
889 ibdev->phys_port_cnt = 1;
890
891 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
892
893 ibdev->num_comp_vectors = rdev->num_msix - 1;
894 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
895 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
896
897 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
898 ibdev->driver_def = bnxt_re_uapi_defs;
899
900 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
901 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
902 if (ret)
903 return ret;
904
905 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
906 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
907 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
908}
909
910static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv,
911 struct bnxt_en_dev *en_dev)
912{
913 struct bnxt_re_dev *rdev;
914
915 /* Allocate bnxt_re_dev instance here */
916 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
917 if (!rdev) {
918 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
919 ROCE_DRV_MODULE_NAME);
920 return NULL;
921 }
922 /* Default values */
923 rdev->nb.notifier_call = NULL;
924 rdev->netdev = en_dev->net;
925 rdev->en_dev = en_dev;
926 rdev->id = rdev->en_dev->pdev->devfn;
927 INIT_LIST_HEAD(&rdev->qp_list);
928 mutex_init(&rdev->qp_lock);
929 mutex_init(&rdev->pacing.dbq_lock);
930 atomic_set(&rdev->stats.res.qp_count, 0);
931 atomic_set(&rdev->stats.res.cq_count, 0);
932 atomic_set(&rdev->stats.res.srq_count, 0);
933 atomic_set(&rdev->stats.res.mr_count, 0);
934 atomic_set(&rdev->stats.res.mw_count, 0);
935 atomic_set(&rdev->stats.res.ah_count, 0);
936 atomic_set(&rdev->stats.res.pd_count, 0);
937 rdev->cosq[0] = 0xFFFF;
938 rdev->cosq[1] = 0xFFFF;
939
940 return rdev;
941}
942
943static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
944 *unaffi_async)
945{
946 switch (unaffi_async->event) {
947 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
948 break;
949 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
950 break;
951 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
952 break;
953 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
954 break;
955 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
956 break;
957 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
958 break;
959 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
960 break;
961 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
962 break;
963 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
964 break;
965 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
966 break;
967 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
968 break;
969 default:
970 return -EINVAL;
971 }
972 return 0;
973}
974
975static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
976 struct bnxt_re_qp *qp)
977{
978 struct bnxt_re_srq *srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq,
979 qplib_srq);
980 struct creq_qp_error_notification *err_event;
981 struct ib_event event = {};
982 unsigned int flags;
983
984 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
985 rdma_is_kernel_res(&qp->ib_qp.res)) {
986 flags = bnxt_re_lock_cqs(qp);
987 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
988 bnxt_re_unlock_cqs(qp, flags);
989 }
990
991 event.device = &qp->rdev->ibdev;
992 event.element.qp = &qp->ib_qp;
993 event.event = IB_EVENT_QP_FATAL;
994
995 err_event = (struct creq_qp_error_notification *)qp_event;
996
997 switch (err_event->req_err_state_reason) {
998 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR:
999 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT:
1000 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT:
1001 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2:
1002 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3:
1003 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP:
1004 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND:
1005 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG:
1006 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE:
1007 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR:
1008 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR:
1009 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR:
1010 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR:
1011 event.event = IB_EVENT_QP_ACCESS_ERR;
1012 break;
1013 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1:
1014 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4:
1015 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH:
1016 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR:
1017 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR:
1018 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR:
1019 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR:
1020 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR:
1021 event.event = IB_EVENT_QP_REQ_ERR;
1022 break;
1023 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR:
1024 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR:
1025 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR:
1026 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR:
1027 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR:
1028 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR:
1029 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR:
1030 event.event = IB_EVENT_QP_FATAL;
1031 break;
1032
1033 default:
1034 break;
1035 }
1036
1037 switch (err_event->res_err_state_reason) {
1038 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX:
1039 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH:
1040 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT:
1041 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY:
1042 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR:
1043 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION:
1044 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR:
1045 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY:
1046 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR:
1047 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION:
1048 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR:
1049 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC:
1050 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND:
1051 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY:
1052 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR:
1053 event.event = IB_EVENT_QP_ACCESS_ERR;
1054 break;
1055 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE:
1056 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR:
1057 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE:
1058 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE:
1059 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR:
1060 event.event = IB_EVENT_QP_REQ_ERR;
1061 break;
1062 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW:
1063 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR:
1064 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR:
1065 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR:
1066 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR:
1067 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR:
1068 event.event = IB_EVENT_QP_FATAL;
1069 break;
1070 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR:
1071 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR:
1072 if (srq)
1073 event.event = IB_EVENT_SRQ_ERR;
1074 break;
1075 default:
1076 break;
1077 }
1078
1079 if (err_event->res_err_state_reason || err_event->req_err_state_reason) {
1080 ibdev_dbg(&qp->rdev->ibdev,
1081 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n",
1082 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user",
1083 qp->qplib_qp.id,
1084 err_event->sq_cons_idx,
1085 err_event->rq_cons_idx,
1086 err_event->req_slow_path_state,
1087 err_event->req_err_state_reason,
1088 err_event->res_slow_path_state,
1089 err_event->res_err_state_reason);
1090 } else {
1091 if (srq)
1092 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
1093 }
1094
1095 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) {
1096 (*srq->ib_srq.event_handler)(&event,
1097 srq->ib_srq.srq_context);
1098 } else if (event.device && qp->ib_qp.event_handler) {
1099 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
1100 }
1101
1102 return 0;
1103}
1104
1105static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq)
1106{
1107 struct creq_cq_error_notification *cqerr;
1108 struct ib_event ibevent = {};
1109
1110 cqerr = event;
1111 switch (cqerr->cq_err_reason) {
1112 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR:
1113 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR:
1114 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR:
1115 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR:
1116 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR:
1117 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR:
1118 ibevent.event = IB_EVENT_CQ_ERR;
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) {
1125 ibevent.element.cq = &cq->ib_cq;
1126 ibevent.device = &cq->rdev->ibdev;
1127
1128 ibdev_dbg(&cq->rdev->ibdev,
1129 "%s err reason %d\n", __func__, cqerr->cq_err_reason);
1130 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context);
1131 }
1132
1133 return 0;
1134}
1135
1136static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1137 void *obj)
1138{
1139 struct bnxt_qplib_qp *lib_qp;
1140 struct bnxt_qplib_cq *lib_cq;
1141 struct bnxt_re_qp *qp;
1142 struct bnxt_re_cq *cq;
1143 int rc = 0;
1144 u8 event;
1145
1146 if (!obj)
1147 return rc; /* QP was already dead, still return success */
1148
1149 event = affi_async->event;
1150 switch (event) {
1151 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
1152 lib_qp = obj;
1153 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp);
1154 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1155 break;
1156 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION:
1157 lib_cq = obj;
1158 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq);
1159 rc = bnxt_re_handle_cq_async_error(affi_async, cq);
1160 break;
1161 default:
1162 rc = -EINVAL;
1163 }
1164 return rc;
1165}
1166
1167static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1168 void *aeqe, void *obj)
1169{
1170 struct creq_qp_event *affi_async;
1171 struct creq_func_event *unaffi_async;
1172 u8 type;
1173 int rc;
1174
1175 type = ((struct creq_base *)aeqe)->type;
1176 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1177 unaffi_async = aeqe;
1178 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1179 } else {
1180 affi_async = aeqe;
1181 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1182 }
1183
1184 return rc;
1185}
1186
1187static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1188 struct bnxt_qplib_srq *handle, u8 event)
1189{
1190 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1191 qplib_srq);
1192 struct ib_event ib_event;
1193
1194 ib_event.device = &srq->rdev->ibdev;
1195 ib_event.element.srq = &srq->ib_srq;
1196
1197 if (srq->ib_srq.event_handler) {
1198 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1199 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1200 (*srq->ib_srq.event_handler)(&ib_event,
1201 srq->ib_srq.srq_context);
1202 }
1203 return 0;
1204}
1205
1206static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1207 struct bnxt_qplib_cq *handle)
1208{
1209 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1210 qplib_cq);
1211 u32 *cq_ptr;
1212
1213 if (cq->ib_cq.comp_handler) {
1214 if (cq->uctx_cq_page) {
1215 cq_ptr = (u32 *)cq->uctx_cq_page;
1216 *cq_ptr = cq->qplib_cq.toggle;
1217 }
1218 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1219 }
1220
1221 return 0;
1222}
1223
1224static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1225{
1226 int i;
1227
1228 for (i = 1; i < rdev->num_msix; i++)
1229 bnxt_qplib_disable_nq(&rdev->nq[i - 1]);
1230
1231 if (rdev->qplib_res.rcfw)
1232 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1233}
1234
1235static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1236{
1237 int num_vec_enabled = 0;
1238 int rc = 0, i;
1239 u32 db_offt;
1240
1241 bnxt_qplib_init_res(&rdev->qplib_res);
1242
1243 for (i = 1; i < rdev->num_msix ; i++) {
1244 db_offt = rdev->en_dev->msix_entries[i].db_offset;
1245 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
1246 i - 1, rdev->en_dev->msix_entries[i].vector,
1247 db_offt, &bnxt_re_cqn_handler,
1248 &bnxt_re_srqn_handler);
1249 if (rc) {
1250 ibdev_err(&rdev->ibdev,
1251 "Failed to enable NQ with rc = 0x%x", rc);
1252 goto fail;
1253 }
1254 num_vec_enabled++;
1255 }
1256 return 0;
1257fail:
1258 for (i = num_vec_enabled; i >= 0; i--)
1259 bnxt_qplib_disable_nq(&rdev->nq[i]);
1260 return rc;
1261}
1262
1263static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1264{
1265 u8 type;
1266 int i;
1267
1268 for (i = 0; i < rdev->num_msix - 1; i++) {
1269 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1270 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1271 bnxt_qplib_free_nq(&rdev->nq[i]);
1272 rdev->nq[i].res = NULL;
1273 }
1274}
1275
1276static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1277{
1278 bnxt_re_free_nq_res(rdev);
1279
1280 if (rdev->qplib_res.dpi_tbl.max) {
1281 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1282 &rdev->dpi_privileged);
1283 }
1284 if (rdev->qplib_res.rcfw) {
1285 bnxt_qplib_free_res(&rdev->qplib_res);
1286 rdev->qplib_res.rcfw = NULL;
1287 }
1288}
1289
1290static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1291{
1292 struct bnxt_re_ring_attr rattr = {};
1293 int num_vec_created = 0;
1294 int rc, i;
1295 u8 type;
1296
1297 /* Configure and allocate resources for qplib */
1298 rdev->qplib_res.rcfw = &rdev->rcfw;
1299 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr);
1300 if (rc)
1301 goto fail;
1302
1303 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev,
1304 rdev->netdev, &rdev->dev_attr);
1305 if (rc)
1306 goto fail;
1307
1308 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1309 &rdev->dpi_privileged,
1310 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1311 if (rc)
1312 goto dealloc_res;
1313
1314 for (i = 0; i < rdev->num_msix - 1; i++) {
1315 struct bnxt_qplib_nq *nq;
1316
1317 nq = &rdev->nq[i];
1318 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1319 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]);
1320 if (rc) {
1321 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1322 i, rc);
1323 goto free_nq;
1324 }
1325 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1326 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1327 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count;
1328 rattr.type = type;
1329 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1330 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1331 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx;
1332 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1333 if (rc) {
1334 ibdev_err(&rdev->ibdev,
1335 "Failed to allocate NQ fw id with rc = 0x%x",
1336 rc);
1337 bnxt_qplib_free_nq(&rdev->nq[i]);
1338 goto free_nq;
1339 }
1340 num_vec_created++;
1341 }
1342 return 0;
1343free_nq:
1344 for (i = num_vec_created - 1; i >= 0; i--) {
1345 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1346 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1347 bnxt_qplib_free_nq(&rdev->nq[i]);
1348 }
1349 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1350 &rdev->dpi_privileged);
1351dealloc_res:
1352 bnxt_qplib_free_res(&rdev->qplib_res);
1353
1354fail:
1355 rdev->qplib_res.rcfw = NULL;
1356 return rc;
1357}
1358
1359static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1360 u8 port_num, enum ib_event_type event)
1361{
1362 struct ib_event ib_event;
1363
1364 ib_event.device = ibdev;
1365 if (qp) {
1366 ib_event.element.qp = qp;
1367 ib_event.event = event;
1368 if (qp->event_handler)
1369 qp->event_handler(&ib_event, qp->qp_context);
1370
1371 } else {
1372 ib_event.element.port_num = port_num;
1373 ib_event.event = event;
1374 ib_dispatch_event(&ib_event);
1375 }
1376}
1377
1378static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1379 struct bnxt_re_qp *qp)
1380{
1381 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1382 (qp == rdev->gsi_ctx.gsi_sqp);
1383}
1384
1385static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1386{
1387 int mask = IB_QP_STATE;
1388 struct ib_qp_attr qp_attr;
1389 struct bnxt_re_qp *qp;
1390
1391 qp_attr.qp_state = IB_QPS_ERR;
1392 mutex_lock(&rdev->qp_lock);
1393 list_for_each_entry(qp, &rdev->qp_list, list) {
1394 /* Modify the state of all QPs except QP1/Shadow QP */
1395 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1396 if (qp->qplib_qp.state !=
1397 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1398 qp->qplib_qp.state !=
1399 CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1400 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1401 1, IB_EVENT_QP_FATAL);
1402 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask,
1403 NULL);
1404 }
1405 }
1406 }
1407 mutex_unlock(&rdev->qp_lock);
1408}
1409
1410static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1411{
1412 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1413 struct bnxt_qplib_gid gid;
1414 u16 gid_idx, index;
1415 int rc = 0;
1416
1417 if (!ib_device_try_get(&rdev->ibdev))
1418 return 0;
1419
1420 for (index = 0; index < sgid_tbl->active; index++) {
1421 gid_idx = sgid_tbl->hw_id[index];
1422
1423 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1424 sizeof(bnxt_qplib_gid_zero)))
1425 continue;
1426 /* need to modify the VLAN enable setting of non VLAN GID only
1427 * as setting is done for VLAN GID while adding GID
1428 */
1429 if (sgid_tbl->vlan[index])
1430 continue;
1431
1432 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1433
1434 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1435 rdev->qplib_res.netdev->dev_addr);
1436 }
1437
1438 ib_device_put(&rdev->ibdev);
1439 return rc;
1440}
1441
1442static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1443{
1444 u32 prio_map = 0, tmp_map = 0;
1445 struct net_device *netdev;
1446 struct dcb_app app = {};
1447
1448 netdev = rdev->netdev;
1449
1450 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1451 app.protocol = ETH_P_IBOE;
1452 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1453 prio_map = tmp_map;
1454
1455 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1456 app.protocol = ROCE_V2_UDP_DPORT;
1457 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1458 prio_map |= tmp_map;
1459
1460 return prio_map;
1461}
1462
1463static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1464{
1465 u8 prio_map = 0;
1466
1467 /* Get priority for roce */
1468 prio_map = bnxt_re_get_priority_mask(rdev);
1469
1470 if (prio_map == rdev->cur_prio_map)
1471 return 0;
1472 rdev->cur_prio_map = prio_map;
1473 /* Actual priorities are not programmed as they are already
1474 * done by L2 driver; just enable or disable priority vlan tagging
1475 */
1476 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1477 (prio_map != 0 && !rdev->qplib_res.prio)) {
1478 rdev->qplib_res.prio = prio_map;
1479 bnxt_re_update_gid(rdev);
1480 }
1481
1482 return 0;
1483}
1484
1485static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1486{
1487 struct bnxt_en_dev *en_dev = rdev->en_dev;
1488 struct hwrm_ver_get_output resp = {};
1489 struct hwrm_ver_get_input req = {};
1490 struct bnxt_qplib_chip_ctx *cctx;
1491 struct bnxt_fw_msg fw_msg = {};
1492 int rc;
1493
1494 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1495 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1496 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1497 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1498 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1499 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1500 rc = bnxt_send_msg(en_dev, &fw_msg);
1501 if (rc) {
1502 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1503 rc);
1504 return;
1505 }
1506
1507 cctx = rdev->chip_ctx;
1508 cctx->hwrm_intf_ver =
1509 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1510 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1511 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1512 le16_to_cpu(resp.hwrm_intf_patch);
1513
1514 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
1515
1516 if (!cctx->hwrm_cmd_max_timeout)
1517 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
1518}
1519
1520static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1521{
1522 int rc;
1523 u32 event;
1524
1525 /* Register ib dev */
1526 rc = bnxt_re_register_ib(rdev);
1527 if (rc) {
1528 pr_err("Failed to register with IB: %#x\n", rc);
1529 return rc;
1530 }
1531 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1532 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1533
1534 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1535 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1536
1537 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
1538
1539 return rc;
1540}
1541
1542static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev)
1543{
1544 u8 type;
1545 int rc;
1546
1547 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1548 cancel_delayed_work_sync(&rdev->worker);
1549
1550 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1551 &rdev->flags))
1552 bnxt_re_cleanup_res(rdev);
1553 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1554 bnxt_re_free_res(rdev);
1555
1556 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1557 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1558 if (rc)
1559 ibdev_warn(&rdev->ibdev,
1560 "Failed to deinitialize RCFW: %#x", rc);
1561 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1562 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1563 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1564 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1565 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1566 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1567 }
1568
1569 rdev->num_msix = 0;
1570
1571 if (rdev->pacing.dbr_pacing)
1572 bnxt_re_deinitialize_dbr_pacing(rdev);
1573
1574 bnxt_re_destroy_chip_ctx(rdev);
1575 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
1576 bnxt_unregister_dev(rdev->en_dev);
1577}
1578
1579/* worker thread for polling periodic events. Now used for QoS programming*/
1580static void bnxt_re_worker(struct work_struct *work)
1581{
1582 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1583 worker.work);
1584
1585 bnxt_re_setup_qos(rdev);
1586 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1587}
1588
1589static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)
1590{
1591 struct bnxt_re_ring_attr rattr = {};
1592 struct bnxt_qplib_creq_ctx *creq;
1593 u32 db_offt;
1594 int vid;
1595 u8 type;
1596 int rc;
1597
1598 /* Registered a new RoCE device instance to netdev */
1599 rc = bnxt_re_register_netdev(rdev);
1600 if (rc) {
1601 ibdev_err(&rdev->ibdev,
1602 "Failed to register with netedev: %#x\n", rc);
1603 return -EINVAL;
1604 }
1605 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1606
1607 rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode);
1608 if (rc) {
1609 bnxt_unregister_dev(rdev->en_dev);
1610 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1611 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
1612 return -EINVAL;
1613 }
1614
1615 /* Check whether VF or PF */
1616 bnxt_re_get_sriov_func_type(rdev);
1617
1618 if (!rdev->en_dev->ulp_tbl->msix_requested) {
1619 ibdev_err(&rdev->ibdev,
1620 "Failed to get MSI-X vectors: %#x\n", rc);
1621 rc = -EINVAL;
1622 goto fail;
1623 }
1624 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
1625 rdev->en_dev->ulp_tbl->msix_requested);
1626 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
1627
1628 bnxt_re_query_hwrm_intf_version(rdev);
1629
1630 /* Establish RCFW Communication Channel to initialize the context
1631 * memory for the function and all child VFs
1632 */
1633 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
1634 &rdev->qplib_ctx,
1635 BNXT_RE_MAX_QPC_COUNT);
1636 if (rc) {
1637 ibdev_err(&rdev->ibdev,
1638 "Failed to allocate RCFW Channel: %#x\n", rc);
1639 goto fail;
1640 }
1641
1642 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1643 creq = &rdev->rcfw.creq;
1644 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1645 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
1646 rattr.type = type;
1647 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1648 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
1649 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
1650 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
1651 if (rc) {
1652 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
1653 goto free_rcfw;
1654 }
1655 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
1656 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;
1657 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
1658 vid, db_offt,
1659 &bnxt_re_aeq_handler);
1660 if (rc) {
1661 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
1662 rc);
1663 goto free_ring;
1664 }
1665
1666 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
1667 rc = bnxt_re_initialize_dbr_pacing(rdev);
1668 if (!rc) {
1669 rdev->pacing.dbr_pacing = true;
1670 } else {
1671 ibdev_err(&rdev->ibdev,
1672 "DBR pacing disabled with error : %d\n", rc);
1673 rdev->pacing.dbr_pacing = false;
1674 }
1675 }
1676 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr);
1677 if (rc)
1678 goto disable_rcfw;
1679
1680 bnxt_re_set_resource_limits(rdev);
1681
1682 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
1683 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));
1684 if (rc) {
1685 ibdev_err(&rdev->ibdev,
1686 "Failed to allocate QPLIB context: %#x\n", rc);
1687 goto disable_rcfw;
1688 }
1689 rc = bnxt_re_net_stats_ctx_alloc(rdev,
1690 rdev->qplib_ctx.stats.dma_map,
1691 &rdev->qplib_ctx.stats.fw_id);
1692 if (rc) {
1693 ibdev_err(&rdev->ibdev,
1694 "Failed to allocate stats context: %#x\n", rc);
1695 goto free_ctx;
1696 }
1697
1698 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
1699 rdev->is_virtfn);
1700 if (rc) {
1701 ibdev_err(&rdev->ibdev,
1702 "Failed to initialize RCFW: %#x\n", rc);
1703 goto free_sctx;
1704 }
1705 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
1706
1707 /* Resources based on the 'new' device caps */
1708 rc = bnxt_re_alloc_res(rdev);
1709 if (rc) {
1710 ibdev_err(&rdev->ibdev,
1711 "Failed to allocate resources: %#x\n", rc);
1712 goto fail;
1713 }
1714 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
1715 rc = bnxt_re_init_res(rdev);
1716 if (rc) {
1717 ibdev_err(&rdev->ibdev,
1718 "Failed to initialize resources: %#x\n", rc);
1719 goto fail;
1720 }
1721
1722 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
1723
1724 if (!rdev->is_virtfn) {
1725 rc = bnxt_re_setup_qos(rdev);
1726 if (rc)
1727 ibdev_info(&rdev->ibdev,
1728 "RoCE priority not yet configured\n");
1729
1730 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
1731 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
1732 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1733 /*
1734 * Use the total VF count since the actual VF count may not be
1735 * available at this point.
1736 */
1737 bnxt_re_vf_res_config(rdev);
1738 }
1739 hash_init(rdev->cq_hash);
1740
1741 return 0;
1742free_sctx:
1743 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1744free_ctx:
1745 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1746disable_rcfw:
1747 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1748free_ring:
1749 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1750 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1751free_rcfw:
1752 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1753fail:
1754 bnxt_re_dev_uninit(rdev);
1755
1756 return rc;
1757}
1758
1759static int bnxt_re_add_device(struct auxiliary_device *adev, u8 wqe_mode)
1760{
1761 struct bnxt_aux_priv *aux_priv =
1762 container_of(adev, struct bnxt_aux_priv, aux_dev);
1763 struct bnxt_en_dev *en_dev;
1764 struct bnxt_re_dev *rdev;
1765 int rc;
1766
1767 /* en_dev should never be NULL as long as adev and aux_dev are valid. */
1768 en_dev = aux_priv->edev;
1769
1770 rdev = bnxt_re_dev_add(aux_priv, en_dev);
1771 if (!rdev || !rdev_to_dev(rdev)) {
1772 rc = -ENOMEM;
1773 goto exit;
1774 }
1775
1776 rc = bnxt_re_dev_init(rdev, wqe_mode);
1777 if (rc)
1778 goto re_dev_dealloc;
1779
1780 rc = bnxt_re_ib_init(rdev);
1781 if (rc) {
1782 pr_err("Failed to register with IB: %s",
1783 aux_priv->aux_dev.name);
1784 goto re_dev_uninit;
1785 }
1786 auxiliary_set_drvdata(adev, rdev);
1787
1788 return 0;
1789
1790re_dev_uninit:
1791 bnxt_re_dev_uninit(rdev);
1792re_dev_dealloc:
1793 ib_dealloc_device(&rdev->ibdev);
1794exit:
1795 return rc;
1796}
1797
1798static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
1799{
1800 struct bnxt_qplib_cc_param cc_param = {};
1801
1802 /* Do not enable congestion control on VFs */
1803 if (rdev->is_virtfn)
1804 return;
1805
1806 /* Currently enabling only for GenP5 adapters */
1807 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
1808 return;
1809
1810 if (enable) {
1811 cc_param.enable = 1;
1812 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE;
1813 }
1814
1815 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE |
1816 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
1817 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
1818
1819 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
1820 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
1821}
1822
1823/*
1824 * "Notifier chain callback can be invoked for the same chain from
1825 * different CPUs at the same time".
1826 *
1827 * For cases when the netdev is already present, our call to the
1828 * register_netdevice_notifier() will actually get the rtnl_lock()
1829 * before sending NETDEV_REGISTER and (if up) NETDEV_UP
1830 * events.
1831 *
1832 * But for cases when the netdev is not already present, the notifier
1833 * chain is subjected to be invoked from different CPUs simultaneously.
1834 *
1835 * This is protected by the netdev_mutex.
1836 */
1837static int bnxt_re_netdev_event(struct notifier_block *notifier,
1838 unsigned long event, void *ptr)
1839{
1840 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
1841 struct bnxt_re_dev *rdev;
1842
1843 real_dev = rdma_vlan_dev_real_dev(netdev);
1844 if (!real_dev)
1845 real_dev = netdev;
1846
1847 if (real_dev != netdev)
1848 goto exit;
1849
1850 rdev = bnxt_re_from_netdev(real_dev);
1851 if (!rdev)
1852 return NOTIFY_DONE;
1853
1854
1855 switch (event) {
1856 case NETDEV_UP:
1857 case NETDEV_DOWN:
1858 case NETDEV_CHANGE:
1859 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
1860 netif_carrier_ok(real_dev) ?
1861 IB_EVENT_PORT_ACTIVE :
1862 IB_EVENT_PORT_ERR);
1863 break;
1864 default:
1865 break;
1866 }
1867 ib_device_put(&rdev->ibdev);
1868exit:
1869 return NOTIFY_DONE;
1870}
1871
1872#define BNXT_ADEV_NAME "bnxt_en"
1873
1874static void bnxt_re_remove(struct auxiliary_device *adev)
1875{
1876 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1877
1878 if (!rdev)
1879 return;
1880
1881 mutex_lock(&bnxt_re_mutex);
1882 if (rdev->nb.notifier_call) {
1883 unregister_netdevice_notifier(&rdev->nb);
1884 rdev->nb.notifier_call = NULL;
1885 } else {
1886 /* If notifier is null, we should have already done a
1887 * clean up before coming here.
1888 */
1889 goto skip_remove;
1890 }
1891 bnxt_re_setup_cc(rdev, false);
1892 ib_unregister_device(&rdev->ibdev);
1893 bnxt_re_dev_uninit(rdev);
1894 ib_dealloc_device(&rdev->ibdev);
1895skip_remove:
1896 mutex_unlock(&bnxt_re_mutex);
1897}
1898
1899static int bnxt_re_probe(struct auxiliary_device *adev,
1900 const struct auxiliary_device_id *id)
1901{
1902 struct bnxt_re_dev *rdev;
1903 int rc;
1904
1905 mutex_lock(&bnxt_re_mutex);
1906 rc = bnxt_re_add_device(adev, BNXT_QPLIB_WQE_MODE_STATIC);
1907 if (rc) {
1908 mutex_unlock(&bnxt_re_mutex);
1909 return rc;
1910 }
1911
1912 rdev = auxiliary_get_drvdata(adev);
1913
1914 rdev->nb.notifier_call = bnxt_re_netdev_event;
1915 rc = register_netdevice_notifier(&rdev->nb);
1916 if (rc) {
1917 rdev->nb.notifier_call = NULL;
1918 pr_err("%s: Cannot register to netdevice_notifier",
1919 ROCE_DRV_MODULE_NAME);
1920 goto err;
1921 }
1922
1923 bnxt_re_setup_cc(rdev, true);
1924 mutex_unlock(&bnxt_re_mutex);
1925 return 0;
1926
1927err:
1928 mutex_unlock(&bnxt_re_mutex);
1929 bnxt_re_remove(adev);
1930
1931 return rc;
1932}
1933
1934static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
1935{
1936 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1937
1938 if (!rdev)
1939 return 0;
1940
1941 mutex_lock(&bnxt_re_mutex);
1942 /* L2 driver may invoke this callback during device error/crash or device
1943 * reset. Current RoCE driver doesn't recover the device in case of
1944 * error. Handle the error by dispatching fatal events to all qps
1945 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
1946 * L2 driver want to modify the MSIx table.
1947 */
1948
1949 ibdev_info(&rdev->ibdev, "Handle device suspend call");
1950 /* Check the current device state from bnxt_en_dev and move the
1951 * device to detached state if FW_FATAL_COND is set.
1952 * This prevents more commands to HW during clean-up,
1953 * in case the device is already in error.
1954 */
1955 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state))
1956 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
1957
1958 bnxt_re_dev_stop(rdev);
1959 bnxt_re_stop_irq(rdev);
1960 /* Move the device states to detached and avoid sending any more
1961 * commands to HW
1962 */
1963 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
1964 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
1965 wake_up_all(&rdev->rcfw.cmdq.waitq);
1966 mutex_unlock(&bnxt_re_mutex);
1967
1968 return 0;
1969}
1970
1971static int bnxt_re_resume(struct auxiliary_device *adev)
1972{
1973 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1974
1975 if (!rdev)
1976 return 0;
1977
1978 mutex_lock(&bnxt_re_mutex);
1979 /* L2 driver may invoke this callback during device recovery, resume.
1980 * reset. Current RoCE driver doesn't recover the device in case of
1981 * error. Handle the error by dispatching fatal events to all qps
1982 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
1983 * L2 driver want to modify the MSIx table.
1984 */
1985
1986 ibdev_info(&rdev->ibdev, "Handle device resume call");
1987 mutex_unlock(&bnxt_re_mutex);
1988
1989 return 0;
1990}
1991
1992static const struct auxiliary_device_id bnxt_re_id_table[] = {
1993 { .name = BNXT_ADEV_NAME ".rdma", },
1994 {},
1995};
1996
1997MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
1998
1999static struct auxiliary_driver bnxt_re_driver = {
2000 .name = "rdma",
2001 .probe = bnxt_re_probe,
2002 .remove = bnxt_re_remove,
2003 .shutdown = bnxt_re_shutdown,
2004 .suspend = bnxt_re_suspend,
2005 .resume = bnxt_re_resume,
2006 .id_table = bnxt_re_id_table,
2007};
2008
2009static int __init bnxt_re_mod_init(void)
2010{
2011 int rc;
2012
2013 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
2014 rc = auxiliary_driver_register(&bnxt_re_driver);
2015 if (rc) {
2016 pr_err("%s: Failed to register auxiliary driver\n",
2017 ROCE_DRV_MODULE_NAME);
2018 return rc;
2019 }
2020 return 0;
2021}
2022
2023static void __exit bnxt_re_mod_exit(void)
2024{
2025 auxiliary_driver_unregister(&bnxt_re_driver);
2026}
2027
2028module_init(bnxt_re_mod_init);
2029module_exit(bnxt_re_mod_exit);
1/*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/ethtool.h>
42#include <linux/mutex.h>
43#include <linux/list.h>
44#include <linux/rculist.h>
45#include <linux/spinlock.h>
46#include <linux/pci.h>
47#include <net/dcbnl.h>
48#include <net/ipv6.h>
49#include <net/addrconf.h>
50#include <linux/if_ether.h>
51#include <linux/auxiliary_bus.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/ib_user_verbs.h>
55#include <rdma/ib_umem.h>
56#include <rdma/ib_addr.h>
57#include <linux/hashtable.h>
58
59#include "bnxt_ulp.h"
60#include "roce_hsi.h"
61#include "qplib_res.h"
62#include "qplib_sp.h"
63#include "qplib_fp.h"
64#include "qplib_rcfw.h"
65#include "bnxt_re.h"
66#include "ib_verbs.h"
67#include <rdma/bnxt_re-abi.h>
68#include "bnxt.h"
69#include "hw_counters.h"
70#include "debugfs.h"
71
72static char version[] =
73 BNXT_RE_DESC "\n";
74
75MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
76MODULE_DESCRIPTION(BNXT_RE_DESC);
77MODULE_LICENSE("Dual BSD/GPL");
78
79/* globals */
80static DEFINE_MUTEX(bnxt_re_mutex);
81
82static void bnxt_re_stop_irq(void *handle);
83static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev);
84static int bnxt_re_netdev_event(struct notifier_block *notifier,
85 unsigned long event, void *ptr);
86static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev);
87static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type);
88static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
89
90static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
91 u32 *offset);
92static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable);
93static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
94{
95 struct bnxt_qplib_chip_ctx *cctx;
96 struct bnxt_en_dev *en_dev;
97 struct bnxt_qplib_res *res;
98 u32 l2db_len = 0;
99 u32 offset = 0;
100 u32 barlen;
101 int rc;
102
103 res = &rdev->qplib_res;
104 en_dev = rdev->en_dev;
105 cctx = rdev->chip_ctx;
106
107 /* Issue qcfg */
108 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
109 if (rc)
110 dev_info(rdev_to_dev(rdev),
111 "Couldn't get DB bar size, Low latency framework is disabled\n");
112 /* set register offsets for both UC and WC */
113 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
114 res->dpi_tbl.ucreg.offset = offset;
115 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
116 } else {
117 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
118 BNXT_QPLIB_DBR_PF_DB_OFFSET;
119 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
120 }
121
122 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
123 * is equal to the DB-Bar actual size. This indicates that L2
124 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
125 * in such cases and DB-push will be disabled.
126 */
127 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
128 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
129 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
130 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
131 }
132}
133
134static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev)
135{
136 struct bnxt_qplib_chip_ctx *cctx;
137
138 cctx = rdev->chip_ctx;
139 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ?
140 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC;
141 if (bnxt_re_hwrm_qcaps(rdev))
142 dev_err(rdev_to_dev(rdev),
143 "Failed to query hwrm qcaps\n");
144 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) {
145 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;
146 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT;
147 }
148}
149
150static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
151{
152 struct bnxt_qplib_chip_ctx *chip_ctx;
153
154 if (!rdev->chip_ctx)
155 return;
156
157 kfree(rdev->dev_attr);
158 rdev->dev_attr = NULL;
159
160 chip_ctx = rdev->chip_ctx;
161 rdev->chip_ctx = NULL;
162 rdev->rcfw.res = NULL;
163 rdev->qplib_res.cctx = NULL;
164 rdev->qplib_res.pdev = NULL;
165 rdev->qplib_res.netdev = NULL;
166 kfree(chip_ctx);
167}
168
169static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
170{
171 struct bnxt_qplib_chip_ctx *chip_ctx;
172 struct bnxt_en_dev *en_dev;
173 int rc = -ENOMEM;
174
175 en_dev = rdev->en_dev;
176
177 rdev->qplib_res.pdev = en_dev->pdev;
178 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
179 if (!chip_ctx)
180 return -ENOMEM;
181 chip_ctx->chip_num = en_dev->chip_num;
182 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
183
184 rdev->chip_ctx = chip_ctx;
185 /* rest members to follow eventually */
186
187 rdev->qplib_res.cctx = rdev->chip_ctx;
188 rdev->rcfw.res = &rdev->qplib_res;
189 rdev->dev_attr = kzalloc(sizeof(*rdev->dev_attr), GFP_KERNEL);
190 if (!rdev->dev_attr)
191 goto free_chip_ctx;
192 rdev->qplib_res.dattr = rdev->dev_attr;
193 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
194 rdev->qplib_res.en_dev = en_dev;
195
196 bnxt_re_set_drv_mode(rdev);
197
198 bnxt_re_set_db_offset(rdev);
199 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
200 if (rc)
201 goto free_dev_attr;
202
203 if (bnxt_qplib_determine_atomics(en_dev->pdev))
204 ibdev_info(&rdev->ibdev,
205 "platform doesn't support global atomics.");
206 return 0;
207free_dev_attr:
208 kfree(rdev->dev_attr);
209 rdev->dev_attr = NULL;
210free_chip_ctx:
211 kfree(rdev->chip_ctx);
212 rdev->chip_ctx = NULL;
213 return rc;
214}
215
216/* SR-IOV helper functions */
217
218static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
219{
220 if (BNXT_EN_VF(rdev->en_dev))
221 rdev->is_virtfn = 1;
222}
223
224/* Set the maximum number of each resource that the driver actually wants
225 * to allocate. This may be up to the maximum number the firmware has
226 * reserved for the function. The driver may choose to allocate fewer
227 * resources than the firmware maximum.
228 */
229static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
230{
231 struct bnxt_qplib_dev_attr *attr;
232 struct bnxt_qplib_ctx *ctx;
233 int i;
234
235 attr = rdev->dev_attr;
236 ctx = &rdev->qplib_ctx;
237
238 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
239 attr->max_qp);
240 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
241 /* Use max_mr from fw since max_mrw does not get set */
242 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
243 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
244 attr->max_srq);
245 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
246 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
247 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
248 rdev->qplib_ctx.tqm_ctx.qcount[i] =
249 rdev->dev_attr->tqm_alloc_reqs[i];
250}
251
252static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
253{
254 struct bnxt_qplib_vf_res *vf_res;
255 u32 mrws = 0;
256 u32 vf_pct;
257 u32 nvfs;
258
259 vf_res = &qplib_ctx->vf_res;
260 /*
261 * Reserve a set of resources for the PF. Divide the remaining
262 * resources among the VFs
263 */
264 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
265 nvfs = num_vf;
266 num_vf = 100 * num_vf;
267 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
268 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
269 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
270 /*
271 * The driver allows many more MRs than other resources. If the
272 * firmware does also, then reserve a fixed amount for the PF and
273 * divide the rest among VFs. VFs may use many MRs for NFS
274 * mounts, ISER, NVME applications, etc. If the firmware severely
275 * restricts the number of MRs, then let PF have half and divide
276 * the rest among VFs, as for the other resource types.
277 */
278 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
279 mrws = qplib_ctx->mrw_count * vf_pct;
280 nvfs = num_vf;
281 } else {
282 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
283 }
284 vf_res->max_mrw_per_vf = (mrws / nvfs);
285 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
286}
287
288static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
289{
290 u32 num_vfs;
291
292 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
293 bnxt_re_limit_pf_res(rdev);
294
295 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
296 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
297 if (num_vfs)
298 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
299}
300
301static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
302{
303 /*
304 * Use the total VF count since the actual VF count may not be
305 * available at this point.
306 */
307 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
308 if (!rdev->num_vfs)
309 return;
310
311 bnxt_re_set_resource_limits(rdev);
312 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
313 &rdev->qplib_ctx);
314}
315
316static void bnxt_re_shutdown(struct auxiliary_device *adev)
317{
318 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
319 struct bnxt_re_dev *rdev;
320
321 rdev = en_info->rdev;
322 ib_unregister_device(&rdev->ibdev);
323 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
324}
325
326static void bnxt_re_stop_irq(void *handle)
327{
328 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
329 struct bnxt_qplib_rcfw *rcfw;
330 struct bnxt_re_dev *rdev;
331 struct bnxt_qplib_nq *nq;
332 int indx;
333
334 rdev = en_info->rdev;
335 if (!rdev)
336 return;
337 rcfw = &rdev->rcfw;
338
339 for (indx = BNXT_RE_NQ_IDX; indx < rdev->nqr->num_msix; indx++) {
340 nq = &rdev->nqr->nq[indx - 1];
341 bnxt_qplib_nq_stop_irq(nq, false);
342 }
343
344 bnxt_qplib_rcfw_stop_irq(rcfw, false);
345}
346
347static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
348{
349 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
350 struct bnxt_msix_entry *msix_ent;
351 struct bnxt_qplib_rcfw *rcfw;
352 struct bnxt_re_dev *rdev;
353 struct bnxt_qplib_nq *nq;
354 int indx, rc;
355
356 rdev = en_info->rdev;
357 if (!rdev)
358 return;
359 msix_ent = rdev->nqr->msix_entries;
360 rcfw = &rdev->rcfw;
361 if (!ent) {
362 /* Not setting the f/w timeout bit in rcfw.
363 * During the driver unload the first command
364 * to f/w will timeout and that will set the
365 * timeout bit.
366 */
367 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
368 return;
369 }
370
371 /* Vectors may change after restart, so update with new vectors
372 * in device sctructure.
373 */
374 for (indx = 0; indx < rdev->nqr->num_msix; indx++)
375 rdev->nqr->msix_entries[indx].vector = ent[indx].vector;
376
377 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
378 false);
379 if (rc) {
380 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
381 return;
382 }
383 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->nqr->num_msix; indx++) {
384 nq = &rdev->nqr->nq[indx - 1];
385 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
386 msix_ent[indx].vector, false);
387 if (rc) {
388 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
389 indx - 1);
390 return;
391 }
392 }
393}
394
395static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
396 .ulp_irq_stop = bnxt_re_stop_irq,
397 .ulp_irq_restart = bnxt_re_start_irq
398};
399
400/* RoCE -> Net driver */
401
402static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
403{
404 struct bnxt_en_dev *en_dev;
405
406 en_dev = rdev->en_dev;
407 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev);
408}
409
410static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
411{
412 hdr->req_type = cpu_to_le16(opcd);
413 hdr->cmpl_ring = cpu_to_le16(-1);
414 hdr->target_id = cpu_to_le16(-1);
415}
416
417static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
418 int msg_len, void *resp, int resp_max_len,
419 int timeout)
420{
421 fw_msg->msg = msg;
422 fw_msg->msg_len = msg_len;
423 fw_msg->resp = resp;
424 fw_msg->resp_max_len = resp_max_len;
425 fw_msg->timeout = timeout;
426}
427
428/* Query device config using common hwrm */
429static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
430 u32 *offset)
431{
432 struct bnxt_en_dev *en_dev = rdev->en_dev;
433 struct hwrm_func_qcfg_output resp = {0};
434 struct hwrm_func_qcfg_input req = {0};
435 struct bnxt_fw_msg fw_msg = {};
436 int rc;
437
438 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
439 req.fid = cpu_to_le16(0xffff);
440 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
441 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
442 rc = bnxt_send_msg(en_dev, &fw_msg);
443 if (!rc) {
444 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
445 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
446 }
447 return rc;
448}
449
450/* Query function capabilities using common hwrm */
451int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
452{
453 struct bnxt_en_dev *en_dev = rdev->en_dev;
454 struct hwrm_func_qcaps_output resp = {};
455 struct hwrm_func_qcaps_input req = {};
456 struct bnxt_qplib_chip_ctx *cctx;
457 struct bnxt_fw_msg fw_msg = {};
458 u32 flags_ext2;
459 int rc;
460
461 cctx = rdev->chip_ctx;
462 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
463 req.fid = cpu_to_le16(0xffff);
464 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
465 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
466
467 rc = bnxt_send_msg(en_dev, &fw_msg);
468 if (rc)
469 return rc;
470 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
471
472 flags_ext2 = le32_to_cpu(resp.flags_ext2);
473 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED ||
474 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED;
475 return 0;
476}
477
478static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
479{
480 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
481 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
482 struct hwrm_func_dbr_pacing_qcfg_input req = {};
483 struct bnxt_en_dev *en_dev = rdev->en_dev;
484 struct bnxt_qplib_chip_ctx *cctx;
485 struct bnxt_fw_msg fw_msg = {};
486 int rc;
487
488 cctx = rdev->chip_ctx;
489 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
490 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
491 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
492 rc = bnxt_send_msg(en_dev, &fw_msg);
493 if (rc)
494 return rc;
495
496 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
497 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
498 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
499 cctx->dbr_stat_db_fifo =
500 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
501 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
502
503 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth);
504 if (!pacing_data->fifo_max_depth)
505 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx);
506 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask);
507 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift;
508
509 return 0;
510}
511
512/* Update the pacing tunable parameters to the default values */
513static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
514{
515 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
516
517 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
518 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
519 pacing_data->alarm_th =
520 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
521}
522
523static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev)
524{
525 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
526 u32 read_val, fifo_occup;
527
528 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
529 fifo_occup = pacing_data->fifo_max_depth -
530 ((read_val & pacing_data->fifo_room_mask) >>
531 pacing_data->fifo_room_shift);
532 return fifo_occup;
533}
534
535static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev)
536{
537 u32 max_occup, fifo_occup;
538
539 fifo_occup = __get_fifo_occupancy(rdev);
540 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1;
541 if (fifo_occup == max_occup)
542 return true;
543
544 return false;
545}
546
547static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
548{
549 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
550 u32 retry_fifo_check = 1000;
551 u32 fifo_occup;
552
553 /* loop shouldn't run infintely as the occupancy usually goes
554 * below pacing algo threshold as soon as pacing kicks in.
555 */
556 while (1) {
557 fifo_occup = __get_fifo_occupancy(rdev);
558 /* Fifo occupancy cannot be greater the MAX FIFO depth */
559 if (fifo_occup > pacing_data->fifo_max_depth)
560 break;
561
562 if (fifo_occup < pacing_data->pacing_th)
563 break;
564 if (!retry_fifo_check--) {
565 dev_info_once(rdev_to_dev(rdev),
566 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n",
567 __func__, fifo_occup, pacing_data->fifo_max_depth,
568 pacing_data->pacing_th);
569 break;
570 }
571
572 }
573}
574
575static void bnxt_re_db_fifo_check(struct work_struct *work)
576{
577 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
578 dbq_fifo_check_work);
579 struct bnxt_qplib_db_pacing_data *pacing_data;
580 u32 pacing_save;
581
582 if (!mutex_trylock(&rdev->pacing.dbq_lock))
583 return;
584 pacing_data = rdev->qplib_res.pacing_data;
585 pacing_save = rdev->pacing.do_pacing_save;
586 __wait_for_fifo_occupancy_below_th(rdev);
587 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
588 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
589 /* Double the do_pacing value during the congestion */
590 pacing_save = pacing_save << 1;
591 } else {
592 /*
593 * when a new congestion is detected increase the do_pacing
594 * by 8 times. And also increase the pacing_th by 4 times. The
595 * reason to increase pacing_th is to give more space for the
596 * queue to oscillate down without getting empty, but also more
597 * room for the queue to increase without causing another alarm.
598 */
599 pacing_save = pacing_save << 3;
600 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
601 }
602
603 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
604 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
605
606 pacing_data->do_pacing = pacing_save;
607 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
608 pacing_data->alarm_th =
609 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
610 schedule_delayed_work(&rdev->dbq_pacing_work,
611 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
612 rdev->stats.pacing.alerts++;
613 mutex_unlock(&rdev->pacing.dbq_lock);
614}
615
616static void bnxt_re_pacing_timer_exp(struct work_struct *work)
617{
618 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
619 dbq_pacing_work.work);
620 struct bnxt_qplib_db_pacing_data *pacing_data;
621 u32 fifo_occup;
622
623 if (!mutex_trylock(&rdev->pacing.dbq_lock))
624 return;
625
626 pacing_data = rdev->qplib_res.pacing_data;
627 fifo_occup = __get_fifo_occupancy(rdev);
628
629 if (fifo_occup > pacing_data->pacing_th)
630 goto restart_timer;
631
632 /*
633 * Instead of immediately going back to the default do_pacing
634 * reduce it by 1/8 times and restart the timer.
635 */
636 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
637 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
638 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
639 bnxt_re_set_default_pacing_data(rdev);
640 rdev->stats.pacing.complete++;
641 goto dbq_unlock;
642 }
643
644restart_timer:
645 schedule_delayed_work(&rdev->dbq_pacing_work,
646 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
647 rdev->stats.pacing.resched++;
648dbq_unlock:
649 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
650 mutex_unlock(&rdev->pacing.dbq_lock);
651}
652
653void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
654{
655 struct bnxt_qplib_db_pacing_data *pacing_data;
656
657 if (!rdev->pacing.dbr_pacing)
658 return;
659 mutex_lock(&rdev->pacing.dbq_lock);
660 pacing_data = rdev->qplib_res.pacing_data;
661
662 /*
663 * Increase the alarm_th to max so that other user lib instances do not
664 * keep alerting the driver.
665 */
666 pacing_data->alarm_th = pacing_data->fifo_max_depth;
667 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
668 cancel_work_sync(&rdev->dbq_fifo_check_work);
669 schedule_work(&rdev->dbq_fifo_check_work);
670 mutex_unlock(&rdev->pacing.dbq_lock);
671}
672
673static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
674{
675 /* Allocate a page for app use */
676 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
677 if (!rdev->pacing.dbr_page)
678 return -ENOMEM;
679
680 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
681 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
682
683 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) {
684 free_page((u64)rdev->pacing.dbr_page);
685 rdev->pacing.dbr_page = NULL;
686 return -EIO;
687 }
688
689 /* MAP HW window 2 for reading db fifo depth */
690 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
691 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
692 rdev->pacing.dbr_db_fifo_reg_off =
693 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
694 BNXT_RE_GRC_FIFO_REG_BASE;
695 rdev->pacing.dbr_bar_addr =
696 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
697
698 if (is_dbr_fifo_full(rdev)) {
699 free_page((u64)rdev->pacing.dbr_page);
700 rdev->pacing.dbr_page = NULL;
701 return -EIO;
702 }
703
704 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
705 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
706 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
707 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
708 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
709 bnxt_re_set_default_pacing_data(rdev);
710 /* Initialize worker for DBR Pacing */
711 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
712 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
713 return 0;
714}
715
716static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
717{
718 cancel_work_sync(&rdev->dbq_fifo_check_work);
719 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
720 if (rdev->pacing.dbr_page)
721 free_page((u64)rdev->pacing.dbr_page);
722
723 rdev->pacing.dbr_page = NULL;
724 rdev->pacing.dbr_pacing = false;
725}
726
727static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
728 u16 fw_ring_id, int type)
729{
730 struct bnxt_en_dev *en_dev;
731 struct hwrm_ring_free_input req = {};
732 struct hwrm_ring_free_output resp;
733 struct bnxt_fw_msg fw_msg = {};
734 int rc = -EINVAL;
735
736 if (!rdev)
737 return rc;
738
739 en_dev = rdev->en_dev;
740
741 if (!en_dev)
742 return rc;
743
744 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
745 return 0;
746
747 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
748 req.ring_type = type;
749 req.ring_id = cpu_to_le16(fw_ring_id);
750 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
751 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
752 rc = bnxt_send_msg(en_dev, &fw_msg);
753 if (rc)
754 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
755 req.ring_id, rc);
756 return rc;
757}
758
759static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
760 struct bnxt_re_ring_attr *ring_attr,
761 u16 *fw_ring_id)
762{
763 struct bnxt_en_dev *en_dev = rdev->en_dev;
764 struct hwrm_ring_alloc_input req = {};
765 struct hwrm_ring_alloc_output resp;
766 struct bnxt_fw_msg fw_msg = {};
767 int rc = -EINVAL;
768
769 if (!en_dev)
770 return rc;
771
772 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
773 req.enables = 0;
774 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
775 if (ring_attr->pages > 1) {
776 /* Page size is in log2 units */
777 req.page_size = BNXT_PAGE_SHIFT;
778 req.page_tbl_depth = 1;
779 }
780 req.fbo = 0;
781 /* Association of ring index with doorbell index and MSIX number */
782 req.logical_id = cpu_to_le16(ring_attr->lrid);
783 req.length = cpu_to_le32(ring_attr->depth + 1);
784 req.ring_type = ring_attr->type;
785 req.int_mode = ring_attr->mode;
786 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
787 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
788 rc = bnxt_send_msg(en_dev, &fw_msg);
789 if (!rc)
790 *fw_ring_id = le16_to_cpu(resp.ring_id);
791
792 return rc;
793}
794
795static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
796 u32 fw_stats_ctx_id)
797{
798 struct bnxt_en_dev *en_dev = rdev->en_dev;
799 struct hwrm_stat_ctx_free_input req = {};
800 struct hwrm_stat_ctx_free_output resp = {};
801 struct bnxt_fw_msg fw_msg = {};
802 int rc = -EINVAL;
803
804 if (!en_dev)
805 return rc;
806
807 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
808 return 0;
809
810 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
811 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
812 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
813 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
814 rc = bnxt_send_msg(en_dev, &fw_msg);
815 if (rc)
816 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
817 rc);
818
819 return rc;
820}
821
822static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
823 dma_addr_t dma_map,
824 u32 *fw_stats_ctx_id)
825{
826 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
827 struct hwrm_stat_ctx_alloc_output resp = {};
828 struct hwrm_stat_ctx_alloc_input req = {};
829 struct bnxt_en_dev *en_dev = rdev->en_dev;
830 struct bnxt_fw_msg fw_msg = {};
831 int rc = -EINVAL;
832
833 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
834
835 if (!en_dev)
836 return rc;
837
838 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
839 req.update_period_ms = cpu_to_le32(1000);
840 req.stats_dma_addr = cpu_to_le64(dma_map);
841 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
842 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
843 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
844 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
845 rc = bnxt_send_msg(en_dev, &fw_msg);
846 if (!rc)
847 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
848
849 return rc;
850}
851
852static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
853{
854}
855
856/* Device */
857
858static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
859{
860 struct ib_device *ibdev =
861 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE);
862 if (!ibdev)
863 return NULL;
864
865 return container_of(ibdev, struct bnxt_re_dev, ibdev);
866}
867
868static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
869 char *buf)
870{
871 struct bnxt_re_dev *rdev =
872 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
873
874 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
875}
876static DEVICE_ATTR_RO(hw_rev);
877
878static ssize_t hca_type_show(struct device *device,
879 struct device_attribute *attr, char *buf)
880{
881 struct bnxt_re_dev *rdev =
882 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
883
884 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
885}
886static DEVICE_ATTR_RO(hca_type);
887
888static struct attribute *bnxt_re_attributes[] = {
889 &dev_attr_hw_rev.attr,
890 &dev_attr_hca_type.attr,
891 NULL
892};
893
894static const struct attribute_group bnxt_re_dev_attr_group = {
895 .attrs = bnxt_re_attributes,
896};
897
898static int bnxt_re_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr)
899{
900 struct bnxt_qplib_hwq *mr_hwq;
901 struct nlattr *table_attr;
902 struct bnxt_re_mr *mr;
903
904 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
905 if (!table_attr)
906 return -EMSGSIZE;
907
908 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
909 mr_hwq = &mr->qplib_mr.hwq;
910
911 if (rdma_nl_put_driver_u32(msg, "page_size",
912 mr_hwq->qe_ppg * mr_hwq->element_size))
913 goto err;
914 if (rdma_nl_put_driver_u32(msg, "max_elements", mr_hwq->max_elements))
915 goto err;
916 if (rdma_nl_put_driver_u32(msg, "element_size", mr_hwq->element_size))
917 goto err;
918 if (rdma_nl_put_driver_u64_hex(msg, "hwq", (unsigned long)mr_hwq))
919 goto err;
920 if (rdma_nl_put_driver_u64_hex(msg, "va", mr->qplib_mr.va))
921 goto err;
922
923 nla_nest_end(msg, table_attr);
924 return 0;
925
926err:
927 nla_nest_cancel(msg, table_attr);
928 return -EMSGSIZE;
929}
930
931static int bnxt_re_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr)
932{
933 struct bnxt_re_dev *rdev;
934 struct bnxt_re_mr *mr;
935 int err, len;
936 void *data;
937
938 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
939 rdev = mr->rdev;
940
941 err = bnxt_re_read_context_allowed(rdev);
942 if (err)
943 return err;
944
945 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P7 :
946 BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P5;
947 data = kzalloc(len, GFP_KERNEL);
948 if (!data)
949 return -ENOMEM;
950
951 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_MRW,
952 mr->qplib_mr.lkey, len, data);
953 if (!err)
954 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
955
956 kfree(data);
957 return err;
958}
959
960static int bnxt_re_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq)
961{
962 struct bnxt_qplib_hwq *cq_hwq;
963 struct nlattr *table_attr;
964 struct bnxt_re_cq *cq;
965
966 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
967 cq_hwq = &cq->qplib_cq.hwq;
968
969 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
970 if (!table_attr)
971 return -EMSGSIZE;
972
973 if (rdma_nl_put_driver_u32(msg, "cq_depth", cq_hwq->depth))
974 goto err;
975 if (rdma_nl_put_driver_u32(msg, "max_elements", cq_hwq->max_elements))
976 goto err;
977 if (rdma_nl_put_driver_u32(msg, "element_size", cq_hwq->element_size))
978 goto err;
979 if (rdma_nl_put_driver_u32(msg, "max_wqe", cq->qplib_cq.max_wqe))
980 goto err;
981
982 nla_nest_end(msg, table_attr);
983 return 0;
984
985err:
986 nla_nest_cancel(msg, table_attr);
987 return -EMSGSIZE;
988}
989
990static int bnxt_re_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq)
991{
992 struct bnxt_re_dev *rdev;
993 struct bnxt_re_cq *cq;
994 int err, len;
995 void *data;
996
997 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
998 rdev = cq->rdev;
999
1000 err = bnxt_re_read_context_allowed(rdev);
1001 if (err)
1002 return err;
1003
1004 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P7 :
1005 BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P5;
1006 data = kzalloc(len, GFP_KERNEL);
1007 if (!data)
1008 return -ENOMEM;
1009
1010 err = bnxt_qplib_read_context(&rdev->rcfw,
1011 CMDQ_READ_CONTEXT_TYPE_CQ,
1012 cq->qplib_cq.id, len, data);
1013 if (!err)
1014 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1015
1016 kfree(data);
1017 return err;
1018}
1019
1020static int bnxt_re_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp)
1021{
1022 struct bnxt_qplib_qp *qplib_qp;
1023 struct nlattr *table_attr;
1024 struct bnxt_re_qp *qp;
1025
1026 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1027 if (!table_attr)
1028 return -EMSGSIZE;
1029
1030 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1031 qplib_qp = &qp->qplib_qp;
1032
1033 if (rdma_nl_put_driver_u32(msg, "sq_max_wqe", qplib_qp->sq.max_wqe))
1034 goto err;
1035 if (rdma_nl_put_driver_u32(msg, "sq_max_sge", qplib_qp->sq.max_sge))
1036 goto err;
1037 if (rdma_nl_put_driver_u32(msg, "sq_wqe_size", qplib_qp->sq.wqe_size))
1038 goto err;
1039 if (rdma_nl_put_driver_u32(msg, "sq_swq_start", qplib_qp->sq.swq_start))
1040 goto err;
1041 if (rdma_nl_put_driver_u32(msg, "sq_swq_last", qplib_qp->sq.swq_last))
1042 goto err;
1043 if (rdma_nl_put_driver_u32(msg, "rq_max_wqe", qplib_qp->rq.max_wqe))
1044 goto err;
1045 if (rdma_nl_put_driver_u32(msg, "rq_max_sge", qplib_qp->rq.max_sge))
1046 goto err;
1047 if (rdma_nl_put_driver_u32(msg, "rq_wqe_size", qplib_qp->rq.wqe_size))
1048 goto err;
1049 if (rdma_nl_put_driver_u32(msg, "rq_swq_start", qplib_qp->rq.swq_start))
1050 goto err;
1051 if (rdma_nl_put_driver_u32(msg, "rq_swq_last", qplib_qp->rq.swq_last))
1052 goto err;
1053 if (rdma_nl_put_driver_u32(msg, "timeout", qplib_qp->timeout))
1054 goto err;
1055
1056 nla_nest_end(msg, table_attr);
1057 return 0;
1058
1059err:
1060 nla_nest_cancel(msg, table_attr);
1061 return -EMSGSIZE;
1062}
1063
1064static int bnxt_re_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ibqp)
1065{
1066 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibqp->device, ibdev);
1067 int err, len;
1068 void *data;
1069
1070 err = bnxt_re_read_context_allowed(rdev);
1071 if (err)
1072 return err;
1073
1074 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P7 :
1075 BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P5;
1076 data = kzalloc(len, GFP_KERNEL);
1077 if (!data)
1078 return -ENOMEM;
1079
1080 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_QPC,
1081 ibqp->qp_num, len, data);
1082 if (!err)
1083 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1084
1085 kfree(data);
1086 return err;
1087}
1088
1089static int bnxt_re_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq)
1090{
1091 struct nlattr *table_attr;
1092 struct bnxt_re_srq *srq;
1093
1094 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1095 if (!table_attr)
1096 return -EMSGSIZE;
1097
1098 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1099
1100 if (rdma_nl_put_driver_u32_hex(msg, "wqe_size", srq->qplib_srq.wqe_size))
1101 goto err;
1102 if (rdma_nl_put_driver_u32_hex(msg, "max_wqe", srq->qplib_srq.max_wqe))
1103 goto err;
1104 if (rdma_nl_put_driver_u32_hex(msg, "max_sge", srq->qplib_srq.max_sge))
1105 goto err;
1106
1107 nla_nest_end(msg, table_attr);
1108 return 0;
1109
1110err:
1111 nla_nest_cancel(msg, table_attr);
1112 return -EMSGSIZE;
1113}
1114
1115static int bnxt_re_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq)
1116{
1117 struct bnxt_re_dev *rdev;
1118 struct bnxt_re_srq *srq;
1119 int err, len;
1120 void *data;
1121
1122 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1123 rdev = srq->rdev;
1124
1125 err = bnxt_re_read_context_allowed(rdev);
1126 if (err)
1127 return err;
1128
1129 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P7 :
1130 BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P5;
1131
1132 data = kzalloc(len, GFP_KERNEL);
1133 if (!data)
1134 return -ENOMEM;
1135
1136 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_SRQ,
1137 srq->qplib_srq.id, len, data);
1138 if (!err)
1139 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1140
1141 kfree(data);
1142 return err;
1143}
1144
1145static const struct ib_device_ops bnxt_re_dev_ops = {
1146 .owner = THIS_MODULE,
1147 .driver_id = RDMA_DRIVER_BNXT_RE,
1148 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
1149
1150 .add_gid = bnxt_re_add_gid,
1151 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
1152 .alloc_mr = bnxt_re_alloc_mr,
1153 .alloc_pd = bnxt_re_alloc_pd,
1154 .alloc_ucontext = bnxt_re_alloc_ucontext,
1155 .create_ah = bnxt_re_create_ah,
1156 .create_cq = bnxt_re_create_cq,
1157 .create_qp = bnxt_re_create_qp,
1158 .create_srq = bnxt_re_create_srq,
1159 .create_user_ah = bnxt_re_create_ah,
1160 .dealloc_pd = bnxt_re_dealloc_pd,
1161 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
1162 .del_gid = bnxt_re_del_gid,
1163 .dereg_mr = bnxt_re_dereg_mr,
1164 .destroy_ah = bnxt_re_destroy_ah,
1165 .destroy_cq = bnxt_re_destroy_cq,
1166 .destroy_qp = bnxt_re_destroy_qp,
1167 .destroy_srq = bnxt_re_destroy_srq,
1168 .device_group = &bnxt_re_dev_attr_group,
1169 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
1170 .get_dev_fw_str = bnxt_re_query_fw_str,
1171 .get_dma_mr = bnxt_re_get_dma_mr,
1172 .get_hw_stats = bnxt_re_ib_get_hw_stats,
1173 .get_link_layer = bnxt_re_get_link_layer,
1174 .get_port_immutable = bnxt_re_get_port_immutable,
1175 .map_mr_sg = bnxt_re_map_mr_sg,
1176 .mmap = bnxt_re_mmap,
1177 .mmap_free = bnxt_re_mmap_free,
1178 .modify_qp = bnxt_re_modify_qp,
1179 .modify_srq = bnxt_re_modify_srq,
1180 .poll_cq = bnxt_re_poll_cq,
1181 .post_recv = bnxt_re_post_recv,
1182 .post_send = bnxt_re_post_send,
1183 .post_srq_recv = bnxt_re_post_srq_recv,
1184 .query_ah = bnxt_re_query_ah,
1185 .query_device = bnxt_re_query_device,
1186 .modify_device = bnxt_re_modify_device,
1187 .query_pkey = bnxt_re_query_pkey,
1188 .query_port = bnxt_re_query_port,
1189 .query_qp = bnxt_re_query_qp,
1190 .query_srq = bnxt_re_query_srq,
1191 .reg_user_mr = bnxt_re_reg_user_mr,
1192 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
1193 .req_notify_cq = bnxt_re_req_notify_cq,
1194 .resize_cq = bnxt_re_resize_cq,
1195 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
1196 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
1197 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
1198 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
1199 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
1200 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
1201};
1202
1203static const struct ib_device_ops restrack_ops = {
1204 .fill_res_cq_entry = bnxt_re_fill_res_cq_entry,
1205 .fill_res_cq_entry_raw = bnxt_re_fill_res_cq_entry_raw,
1206 .fill_res_qp_entry = bnxt_re_fill_res_qp_entry,
1207 .fill_res_qp_entry_raw = bnxt_re_fill_res_qp_entry_raw,
1208 .fill_res_mr_entry = bnxt_re_fill_res_mr_entry,
1209 .fill_res_mr_entry_raw = bnxt_re_fill_res_mr_entry_raw,
1210 .fill_res_srq_entry = bnxt_re_fill_res_srq_entry,
1211 .fill_res_srq_entry_raw = bnxt_re_fill_res_srq_entry_raw,
1212};
1213
1214static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
1215{
1216 struct ib_device *ibdev = &rdev->ibdev;
1217 int ret;
1218
1219 /* ib device init */
1220 ibdev->node_type = RDMA_NODE_IB_CA;
1221 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
1222 strlen(BNXT_RE_DESC) + 5);
1223 ibdev->phys_port_cnt = 1;
1224
1225 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
1226
1227 ibdev->num_comp_vectors = rdev->nqr->num_msix - 1;
1228 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
1229 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
1230
1231 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
1232 ibdev->driver_def = bnxt_re_uapi_defs;
1233
1234 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
1235 ib_set_device_ops(ibdev, &restrack_ops);
1236 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
1237 if (ret)
1238 return ret;
1239
1240 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
1241 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
1242 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
1243}
1244
1245static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev,
1246 struct bnxt_en_dev *en_dev)
1247{
1248 struct bnxt_re_dev *rdev;
1249
1250 /* Allocate bnxt_re_dev instance here */
1251 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
1252 if (!rdev) {
1253 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
1254 ROCE_DRV_MODULE_NAME);
1255 return NULL;
1256 }
1257 /* Default values */
1258 rdev->nb.notifier_call = NULL;
1259 rdev->netdev = en_dev->net;
1260 rdev->en_dev = en_dev;
1261 rdev->adev = adev;
1262 rdev->id = rdev->en_dev->pdev->devfn;
1263 INIT_LIST_HEAD(&rdev->qp_list);
1264 mutex_init(&rdev->qp_lock);
1265 mutex_init(&rdev->pacing.dbq_lock);
1266 atomic_set(&rdev->stats.res.qp_count, 0);
1267 atomic_set(&rdev->stats.res.cq_count, 0);
1268 atomic_set(&rdev->stats.res.srq_count, 0);
1269 atomic_set(&rdev->stats.res.mr_count, 0);
1270 atomic_set(&rdev->stats.res.mw_count, 0);
1271 atomic_set(&rdev->stats.res.ah_count, 0);
1272 atomic_set(&rdev->stats.res.pd_count, 0);
1273 rdev->cosq[0] = 0xFFFF;
1274 rdev->cosq[1] = 0xFFFF;
1275 rdev->cq_coalescing.buf_maxtime = BNXT_QPLIB_CQ_COAL_DEF_BUF_MAXTIME;
1276 if (bnxt_re_chip_gen_p7(en_dev->chip_num)) {
1277 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P7;
1278 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P7;
1279 } else {
1280 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P5;
1281 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P5;
1282 }
1283 rdev->cq_coalescing.en_ring_idle_mode = BNXT_QPLIB_CQ_COAL_DEF_EN_RING_IDLE_MODE;
1284
1285 return rdev;
1286}
1287
1288static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
1289 *unaffi_async)
1290{
1291 switch (unaffi_async->event) {
1292 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
1293 break;
1294 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
1295 break;
1296 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
1297 break;
1298 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
1299 break;
1300 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
1301 break;
1302 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
1303 break;
1304 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
1305 break;
1306 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
1307 break;
1308 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
1309 break;
1310 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
1311 break;
1312 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
1313 break;
1314 default:
1315 return -EINVAL;
1316 }
1317 return 0;
1318}
1319
1320static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
1321 struct bnxt_re_qp *qp)
1322{
1323 struct creq_qp_error_notification *err_event;
1324 struct bnxt_re_srq *srq = NULL;
1325 struct ib_event event = {};
1326 unsigned int flags;
1327
1328 if (qp->qplib_qp.srq)
1329 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq,
1330 qplib_srq);
1331
1332 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
1333 rdma_is_kernel_res(&qp->ib_qp.res)) {
1334 flags = bnxt_re_lock_cqs(qp);
1335 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1336 bnxt_re_unlock_cqs(qp, flags);
1337 }
1338
1339 event.device = &qp->rdev->ibdev;
1340 event.element.qp = &qp->ib_qp;
1341 event.event = IB_EVENT_QP_FATAL;
1342
1343 err_event = (struct creq_qp_error_notification *)qp_event;
1344
1345 switch (err_event->req_err_state_reason) {
1346 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR:
1347 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT:
1348 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT:
1349 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2:
1350 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3:
1351 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP:
1352 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND:
1353 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG:
1354 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE:
1355 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR:
1356 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR:
1357 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR:
1358 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR:
1359 event.event = IB_EVENT_QP_ACCESS_ERR;
1360 break;
1361 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1:
1362 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4:
1363 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH:
1364 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR:
1365 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR:
1366 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR:
1367 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR:
1368 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR:
1369 event.event = IB_EVENT_QP_REQ_ERR;
1370 break;
1371 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR:
1372 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR:
1373 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR:
1374 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR:
1375 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR:
1376 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR:
1377 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR:
1378 event.event = IB_EVENT_QP_FATAL;
1379 break;
1380
1381 default:
1382 break;
1383 }
1384
1385 switch (err_event->res_err_state_reason) {
1386 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX:
1387 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH:
1388 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT:
1389 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY:
1390 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR:
1391 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION:
1392 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR:
1393 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY:
1394 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR:
1395 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION:
1396 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR:
1397 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC:
1398 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND:
1399 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY:
1400 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR:
1401 event.event = IB_EVENT_QP_ACCESS_ERR;
1402 break;
1403 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE:
1404 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR:
1405 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE:
1406 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE:
1407 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR:
1408 event.event = IB_EVENT_QP_REQ_ERR;
1409 break;
1410 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW:
1411 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR:
1412 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR:
1413 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR:
1414 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR:
1415 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR:
1416 event.event = IB_EVENT_QP_FATAL;
1417 break;
1418 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR:
1419 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR:
1420 if (srq)
1421 event.event = IB_EVENT_SRQ_ERR;
1422 break;
1423 default:
1424 break;
1425 }
1426
1427 if (err_event->res_err_state_reason || err_event->req_err_state_reason) {
1428 ibdev_dbg(&qp->rdev->ibdev,
1429 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n",
1430 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user",
1431 qp->qplib_qp.id,
1432 err_event->sq_cons_idx,
1433 err_event->rq_cons_idx,
1434 err_event->req_slow_path_state,
1435 err_event->req_err_state_reason,
1436 err_event->res_slow_path_state,
1437 err_event->res_err_state_reason);
1438 } else {
1439 if (srq)
1440 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
1441 }
1442
1443 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) {
1444 (*srq->ib_srq.event_handler)(&event,
1445 srq->ib_srq.srq_context);
1446 } else if (event.device && qp->ib_qp.event_handler) {
1447 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
1448 }
1449
1450 return 0;
1451}
1452
1453static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq)
1454{
1455 struct creq_cq_error_notification *cqerr;
1456 struct ib_event ibevent = {};
1457
1458 cqerr = event;
1459 switch (cqerr->cq_err_reason) {
1460 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR:
1461 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR:
1462 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR:
1463 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR:
1464 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR:
1465 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR:
1466 ibevent.event = IB_EVENT_CQ_ERR;
1467 break;
1468 default:
1469 break;
1470 }
1471
1472 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) {
1473 ibevent.element.cq = &cq->ib_cq;
1474 ibevent.device = &cq->rdev->ibdev;
1475
1476 ibdev_dbg(&cq->rdev->ibdev,
1477 "%s err reason %d\n", __func__, cqerr->cq_err_reason);
1478 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context);
1479 }
1480
1481 return 0;
1482}
1483
1484static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1485 void *obj)
1486{
1487 struct bnxt_qplib_qp *lib_qp;
1488 struct bnxt_qplib_cq *lib_cq;
1489 struct bnxt_re_qp *qp;
1490 struct bnxt_re_cq *cq;
1491 int rc = 0;
1492 u8 event;
1493
1494 if (!obj)
1495 return rc; /* QP was already dead, still return success */
1496
1497 event = affi_async->event;
1498 switch (event) {
1499 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
1500 lib_qp = obj;
1501 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp);
1502 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1503 break;
1504 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION:
1505 lib_cq = obj;
1506 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq);
1507 rc = bnxt_re_handle_cq_async_error(affi_async, cq);
1508 break;
1509 default:
1510 rc = -EINVAL;
1511 }
1512 return rc;
1513}
1514
1515static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1516 void *aeqe, void *obj)
1517{
1518 struct creq_qp_event *affi_async;
1519 struct creq_func_event *unaffi_async;
1520 u8 type;
1521 int rc;
1522
1523 type = ((struct creq_base *)aeqe)->type;
1524 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1525 unaffi_async = aeqe;
1526 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1527 } else {
1528 affi_async = aeqe;
1529 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1530 }
1531
1532 return rc;
1533}
1534
1535static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1536 struct bnxt_qplib_srq *handle, u8 event)
1537{
1538 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1539 qplib_srq);
1540 struct ib_event ib_event;
1541
1542 ib_event.device = &srq->rdev->ibdev;
1543 ib_event.element.srq = &srq->ib_srq;
1544
1545 if (srq->ib_srq.event_handler) {
1546 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1547 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1548 (*srq->ib_srq.event_handler)(&ib_event,
1549 srq->ib_srq.srq_context);
1550 }
1551 return 0;
1552}
1553
1554static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1555 struct bnxt_qplib_cq *handle)
1556{
1557 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1558 qplib_cq);
1559
1560 if (cq->ib_cq.comp_handler)
1561 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1562
1563 return 0;
1564}
1565
1566static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1567{
1568 int i;
1569
1570 for (i = 1; i < rdev->nqr->num_msix; i++)
1571 bnxt_qplib_disable_nq(&rdev->nqr->nq[i - 1]);
1572
1573 if (rdev->qplib_res.rcfw)
1574 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1575}
1576
1577static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1578{
1579 int num_vec_enabled = 0;
1580 int rc = 0, i;
1581 u32 db_offt;
1582
1583 bnxt_qplib_init_res(&rdev->qplib_res);
1584
1585 mutex_init(&rdev->nqr->load_lock);
1586
1587 for (i = 1; i < rdev->nqr->num_msix ; i++) {
1588 db_offt = rdev->nqr->msix_entries[i].db_offset;
1589 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nqr->nq[i - 1],
1590 i - 1, rdev->nqr->msix_entries[i].vector,
1591 db_offt, &bnxt_re_cqn_handler,
1592 &bnxt_re_srqn_handler);
1593 if (rc) {
1594 ibdev_err(&rdev->ibdev,
1595 "Failed to enable NQ with rc = 0x%x", rc);
1596 goto fail;
1597 }
1598 num_vec_enabled++;
1599 }
1600 return 0;
1601fail:
1602 for (i = num_vec_enabled; i >= 0; i--)
1603 bnxt_qplib_disable_nq(&rdev->nqr->nq[i]);
1604 return rc;
1605}
1606
1607static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1608{
1609 struct bnxt_qplib_nq *nq;
1610 u8 type;
1611 int i;
1612
1613 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1614 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1615 nq = &rdev->nqr->nq[i];
1616 bnxt_re_net_ring_free(rdev, nq->ring_id, type);
1617 bnxt_qplib_free_nq(nq);
1618 nq->res = NULL;
1619 }
1620}
1621
1622static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1623{
1624 bnxt_re_free_nq_res(rdev);
1625
1626 if (rdev->qplib_res.dpi_tbl.max) {
1627 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1628 &rdev->dpi_privileged);
1629 }
1630 if (rdev->qplib_res.rcfw) {
1631 bnxt_qplib_free_res(&rdev->qplib_res);
1632 rdev->qplib_res.rcfw = NULL;
1633 }
1634}
1635
1636static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1637{
1638 struct bnxt_re_ring_attr rattr = {};
1639 int num_vec_created = 0;
1640 int rc, i;
1641 u8 type;
1642
1643 /* Configure and allocate resources for qplib */
1644 rdev->qplib_res.rcfw = &rdev->rcfw;
1645 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
1646 if (rc)
1647 goto fail;
1648
1649 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->netdev);
1650 if (rc)
1651 goto fail;
1652
1653 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1654 &rdev->dpi_privileged,
1655 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1656 if (rc)
1657 goto dealloc_res;
1658
1659 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1660 struct bnxt_qplib_nq *nq;
1661
1662 nq = &rdev->nqr->nq[i];
1663 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1664 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, nq);
1665 if (rc) {
1666 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1667 i, rc);
1668 goto free_nq;
1669 }
1670 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1671 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1672 rattr.pages = nq->hwq.pbl[rdev->nqr->nq[i].hwq.level].pg_count;
1673 rattr.type = type;
1674 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1675 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1676 rattr.lrid = rdev->nqr->msix_entries[i + 1].ring_idx;
1677 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1678 if (rc) {
1679 ibdev_err(&rdev->ibdev,
1680 "Failed to allocate NQ fw id with rc = 0x%x",
1681 rc);
1682 bnxt_qplib_free_nq(nq);
1683 goto free_nq;
1684 }
1685 num_vec_created++;
1686 }
1687 return 0;
1688free_nq:
1689 for (i = num_vec_created - 1; i >= 0; i--) {
1690 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1691 bnxt_re_net_ring_free(rdev, rdev->nqr->nq[i].ring_id, type);
1692 bnxt_qplib_free_nq(&rdev->nqr->nq[i]);
1693 }
1694 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1695 &rdev->dpi_privileged);
1696dealloc_res:
1697 bnxt_qplib_free_res(&rdev->qplib_res);
1698
1699fail:
1700 rdev->qplib_res.rcfw = NULL;
1701 return rc;
1702}
1703
1704static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1705 u8 port_num, enum ib_event_type event)
1706{
1707 struct ib_event ib_event;
1708
1709 ib_event.device = ibdev;
1710 if (qp) {
1711 ib_event.element.qp = qp;
1712 ib_event.event = event;
1713 if (qp->event_handler)
1714 qp->event_handler(&ib_event, qp->qp_context);
1715
1716 } else {
1717 ib_event.element.port_num = port_num;
1718 ib_event.event = event;
1719 ib_dispatch_event(&ib_event);
1720 }
1721}
1722
1723static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1724 struct bnxt_re_qp *qp)
1725{
1726 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1727 (qp == rdev->gsi_ctx.gsi_sqp);
1728}
1729
1730static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1731{
1732 struct bnxt_re_qp *qp;
1733
1734 mutex_lock(&rdev->qp_lock);
1735 list_for_each_entry(qp, &rdev->qp_list, list) {
1736 /* Modify the state of all QPs except QP1/Shadow QP */
1737 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1738 if (qp->qplib_qp.state !=
1739 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1740 qp->qplib_qp.state !=
1741 CMDQ_MODIFY_QP_NEW_STATE_ERR)
1742 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1743 1, IB_EVENT_QP_FATAL);
1744 }
1745 }
1746 mutex_unlock(&rdev->qp_lock);
1747}
1748
1749static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1750{
1751 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1752 struct bnxt_qplib_gid gid;
1753 u16 gid_idx, index;
1754 int rc = 0;
1755
1756 if (!ib_device_try_get(&rdev->ibdev))
1757 return 0;
1758
1759 for (index = 0; index < sgid_tbl->active; index++) {
1760 gid_idx = sgid_tbl->hw_id[index];
1761
1762 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1763 sizeof(bnxt_qplib_gid_zero)))
1764 continue;
1765 /* need to modify the VLAN enable setting of non VLAN GID only
1766 * as setting is done for VLAN GID while adding GID
1767 */
1768 if (sgid_tbl->vlan[index])
1769 continue;
1770
1771 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1772
1773 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1774 rdev->qplib_res.netdev->dev_addr);
1775 }
1776
1777 ib_device_put(&rdev->ibdev);
1778 return rc;
1779}
1780
1781static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1782{
1783 u32 prio_map = 0, tmp_map = 0;
1784 struct net_device *netdev;
1785 struct dcb_app app = {};
1786
1787 netdev = rdev->netdev;
1788
1789 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1790 app.protocol = ETH_P_IBOE;
1791 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1792 prio_map = tmp_map;
1793
1794 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1795 app.protocol = ROCE_V2_UDP_DPORT;
1796 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1797 prio_map |= tmp_map;
1798
1799 return prio_map;
1800}
1801
1802static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1803{
1804 u8 prio_map = 0;
1805
1806 /* Get priority for roce */
1807 prio_map = bnxt_re_get_priority_mask(rdev);
1808
1809 if (prio_map == rdev->cur_prio_map)
1810 return 0;
1811 rdev->cur_prio_map = prio_map;
1812 /* Actual priorities are not programmed as they are already
1813 * done by L2 driver; just enable or disable priority vlan tagging
1814 */
1815 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1816 (prio_map != 0 && !rdev->qplib_res.prio)) {
1817 rdev->qplib_res.prio = prio_map;
1818 bnxt_re_update_gid(rdev);
1819 }
1820
1821 return 0;
1822}
1823
1824static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1825{
1826 struct bnxt_en_dev *en_dev = rdev->en_dev;
1827 struct hwrm_ver_get_output resp = {};
1828 struct hwrm_ver_get_input req = {};
1829 struct bnxt_qplib_chip_ctx *cctx;
1830 struct bnxt_fw_msg fw_msg = {};
1831 int rc;
1832
1833 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1834 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1835 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1836 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1837 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1838 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1839 rc = bnxt_send_msg(en_dev, &fw_msg);
1840 if (rc) {
1841 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1842 rc);
1843 return;
1844 }
1845
1846 cctx = rdev->chip_ctx;
1847 cctx->hwrm_intf_ver =
1848 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1849 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1850 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1851 le16_to_cpu(resp.hwrm_intf_patch);
1852
1853 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
1854
1855 if (!cctx->hwrm_cmd_max_timeout)
1856 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
1857}
1858
1859static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1860{
1861 int rc;
1862 u32 event;
1863
1864 /* Register ib dev */
1865 rc = bnxt_re_register_ib(rdev);
1866 if (rc) {
1867 pr_err("Failed to register with IB: %#x\n", rc);
1868 return rc;
1869 }
1870 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1871 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1872
1873 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1874 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1875
1876 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
1877
1878 return rc;
1879}
1880
1881static int bnxt_re_alloc_nqr_mem(struct bnxt_re_dev *rdev)
1882{
1883 rdev->nqr = kzalloc(sizeof(*rdev->nqr), GFP_KERNEL);
1884 if (!rdev->nqr)
1885 return -ENOMEM;
1886
1887 return 0;
1888}
1889
1890static void bnxt_re_free_nqr_mem(struct bnxt_re_dev *rdev)
1891{
1892 kfree(rdev->nqr);
1893 rdev->nqr = NULL;
1894}
1895
1896static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type)
1897{
1898 u8 type;
1899 int rc;
1900
1901 bnxt_re_debugfs_rem_pdev(rdev);
1902
1903 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1904 cancel_delayed_work_sync(&rdev->worker);
1905
1906 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1907 &rdev->flags))
1908 bnxt_re_cleanup_res(rdev);
1909 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1910 bnxt_re_free_res(rdev);
1911
1912 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1913 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1914 if (rc)
1915 ibdev_warn(&rdev->ibdev,
1916 "Failed to deinitialize RCFW: %#x", rc);
1917 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1918 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1919 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1920 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1921 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1922 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1923 }
1924
1925 rdev->nqr->num_msix = 0;
1926
1927 if (rdev->pacing.dbr_pacing)
1928 bnxt_re_deinitialize_dbr_pacing(rdev);
1929
1930 bnxt_re_free_nqr_mem(rdev);
1931 bnxt_re_destroy_chip_ctx(rdev);
1932 if (op_type == BNXT_RE_COMPLETE_REMOVE) {
1933 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
1934 bnxt_unregister_dev(rdev->en_dev);
1935 }
1936}
1937
1938/* worker thread for polling periodic events. Now used for QoS programming*/
1939static void bnxt_re_worker(struct work_struct *work)
1940{
1941 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1942 worker.work);
1943
1944 bnxt_re_setup_qos(rdev);
1945 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1946}
1947
1948static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type)
1949{
1950 struct bnxt_re_ring_attr rattr = {};
1951 struct bnxt_qplib_creq_ctx *creq;
1952 u32 db_offt;
1953 int vid;
1954 u8 type;
1955 int rc;
1956
1957 if (op_type == BNXT_RE_COMPLETE_INIT) {
1958 /* Registered a new RoCE device instance to netdev */
1959 rc = bnxt_re_register_netdev(rdev);
1960 if (rc) {
1961 ibdev_err(&rdev->ibdev,
1962 "Failed to register with netedev: %#x\n", rc);
1963 return -EINVAL;
1964 }
1965 }
1966 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1967
1968 if (rdev->en_dev->ulp_tbl->msix_requested < BNXT_RE_MIN_MSIX) {
1969 ibdev_err(&rdev->ibdev,
1970 "RoCE requires minimum 2 MSI-X vectors, but only %d reserved\n",
1971 rdev->en_dev->ulp_tbl->msix_requested);
1972 bnxt_unregister_dev(rdev->en_dev);
1973 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1974 return -EINVAL;
1975 }
1976 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
1977 rdev->en_dev->ulp_tbl->msix_requested);
1978
1979 rc = bnxt_re_setup_chip_ctx(rdev);
1980 if (rc) {
1981 bnxt_unregister_dev(rdev->en_dev);
1982 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1983 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
1984 return -EINVAL;
1985 }
1986
1987 rc = bnxt_re_alloc_nqr_mem(rdev);
1988 if (rc) {
1989 bnxt_re_destroy_chip_ctx(rdev);
1990 bnxt_unregister_dev(rdev->en_dev);
1991 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1992 return rc;
1993 }
1994 rdev->nqr->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
1995 memcpy(rdev->nqr->msix_entries, rdev->en_dev->msix_entries,
1996 sizeof(struct bnxt_msix_entry) * rdev->nqr->num_msix);
1997
1998 /* Check whether VF or PF */
1999 bnxt_re_get_sriov_func_type(rdev);
2000
2001 bnxt_re_query_hwrm_intf_version(rdev);
2002
2003 /* Establish RCFW Communication Channel to initialize the context
2004 * memory for the function and all child VFs
2005 */
2006 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
2007 &rdev->qplib_ctx,
2008 BNXT_RE_MAX_QPC_COUNT);
2009 if (rc) {
2010 ibdev_err(&rdev->ibdev,
2011 "Failed to allocate RCFW Channel: %#x\n", rc);
2012 goto fail;
2013 }
2014
2015 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2016 creq = &rdev->rcfw.creq;
2017 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
2018 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
2019 rattr.type = type;
2020 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
2021 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
2022 rattr.lrid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
2023 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
2024 if (rc) {
2025 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
2026 goto free_rcfw;
2027 }
2028 db_offt = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
2029 vid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].vector;
2030 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
2031 vid, db_offt,
2032 &bnxt_re_aeq_handler);
2033 if (rc) {
2034 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
2035 rc);
2036 goto free_ring;
2037 }
2038
2039 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
2040 rc = bnxt_re_initialize_dbr_pacing(rdev);
2041 if (!rc) {
2042 rdev->pacing.dbr_pacing = true;
2043 } else {
2044 ibdev_err(&rdev->ibdev,
2045 "DBR pacing disabled with error : %d\n", rc);
2046 rdev->pacing.dbr_pacing = false;
2047 }
2048 }
2049 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
2050 if (rc)
2051 goto disable_rcfw;
2052
2053 bnxt_re_set_resource_limits(rdev);
2054
2055 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
2056 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));
2057 if (rc) {
2058 ibdev_err(&rdev->ibdev,
2059 "Failed to allocate QPLIB context: %#x\n", rc);
2060 goto disable_rcfw;
2061 }
2062 rc = bnxt_re_net_stats_ctx_alloc(rdev,
2063 rdev->qplib_ctx.stats.dma_map,
2064 &rdev->qplib_ctx.stats.fw_id);
2065 if (rc) {
2066 ibdev_err(&rdev->ibdev,
2067 "Failed to allocate stats context: %#x\n", rc);
2068 goto free_ctx;
2069 }
2070
2071 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
2072 rdev->is_virtfn);
2073 if (rc) {
2074 ibdev_err(&rdev->ibdev,
2075 "Failed to initialize RCFW: %#x\n", rc);
2076 goto free_sctx;
2077 }
2078 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
2079
2080 /* Resources based on the 'new' device caps */
2081 rc = bnxt_re_alloc_res(rdev);
2082 if (rc) {
2083 ibdev_err(&rdev->ibdev,
2084 "Failed to allocate resources: %#x\n", rc);
2085 goto fail;
2086 }
2087 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
2088 rc = bnxt_re_init_res(rdev);
2089 if (rc) {
2090 ibdev_err(&rdev->ibdev,
2091 "Failed to initialize resources: %#x\n", rc);
2092 goto fail;
2093 }
2094
2095 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
2096
2097 if (!rdev->is_virtfn) {
2098 rc = bnxt_re_setup_qos(rdev);
2099 if (rc)
2100 ibdev_info(&rdev->ibdev,
2101 "RoCE priority not yet configured\n");
2102
2103 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
2104 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
2105 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
2106
2107 if (!(rdev->qplib_res.en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT))
2108 bnxt_re_vf_res_config(rdev);
2109 }
2110 hash_init(rdev->cq_hash);
2111 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT)
2112 hash_init(rdev->srq_hash);
2113
2114 bnxt_re_debugfs_add_pdev(rdev);
2115
2116 return 0;
2117free_sctx:
2118 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
2119free_ctx:
2120 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
2121disable_rcfw:
2122 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
2123free_ring:
2124 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2125 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
2126free_rcfw:
2127 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
2128fail:
2129 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2130
2131 return rc;
2132}
2133
2134static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev,
2135 struct bnxt_re_en_dev_info *en_info,
2136 struct auxiliary_device *adev)
2137{
2138 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure,
2139 * take the rtnl lock to avoid accessing invalid rdev pointer from
2140 * L2 ULP callbacks. This is applicable in all the places where rdev
2141 * pointer is updated in bnxt_re_en_dev_info.
2142 */
2143 rtnl_lock();
2144 en_info->rdev = rdev;
2145 rtnl_unlock();
2146}
2147
2148static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type)
2149{
2150 struct bnxt_aux_priv *aux_priv =
2151 container_of(adev, struct bnxt_aux_priv, aux_dev);
2152 struct bnxt_re_en_dev_info *en_info;
2153 struct bnxt_en_dev *en_dev;
2154 struct bnxt_re_dev *rdev;
2155 int rc;
2156
2157 en_info = auxiliary_get_drvdata(adev);
2158 en_dev = en_info->en_dev;
2159
2160
2161 rdev = bnxt_re_dev_add(adev, en_dev);
2162 if (!rdev || !rdev_to_dev(rdev)) {
2163 rc = -ENOMEM;
2164 goto exit;
2165 }
2166
2167 bnxt_re_update_en_info_rdev(rdev, en_info, adev);
2168
2169 rc = bnxt_re_dev_init(rdev, op_type);
2170 if (rc)
2171 goto re_dev_dealloc;
2172
2173 rc = bnxt_re_ib_init(rdev);
2174 if (rc) {
2175 pr_err("Failed to register with IB: %s",
2176 aux_priv->aux_dev.name);
2177 goto re_dev_uninit;
2178 }
2179
2180 rdev->nb.notifier_call = bnxt_re_netdev_event;
2181 rc = register_netdevice_notifier(&rdev->nb);
2182 if (rc) {
2183 rdev->nb.notifier_call = NULL;
2184 pr_err("%s: Cannot register to netdevice_notifier",
2185 ROCE_DRV_MODULE_NAME);
2186 goto re_dev_unreg;
2187 }
2188 bnxt_re_setup_cc(rdev, true);
2189
2190 return 0;
2191
2192re_dev_unreg:
2193 ib_unregister_device(&rdev->ibdev);
2194re_dev_uninit:
2195 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2196 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2197re_dev_dealloc:
2198 ib_dealloc_device(&rdev->ibdev);
2199exit:
2200 return rc;
2201}
2202
2203static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
2204{
2205 struct bnxt_qplib_cc_param cc_param = {};
2206
2207 /* Do not enable congestion control on VFs */
2208 if (rdev->is_virtfn)
2209 return;
2210
2211 /* Currently enabling only for GenP5 adapters */
2212 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
2213 return;
2214
2215 if (enable) {
2216 cc_param.enable = 1;
2217 cc_param.tos_ecn = 1;
2218 }
2219
2220 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
2221 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
2222
2223 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
2224 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
2225}
2226
2227/*
2228 * "Notifier chain callback can be invoked for the same chain from
2229 * different CPUs at the same time".
2230 *
2231 * For cases when the netdev is already present, our call to the
2232 * register_netdevice_notifier() will actually get the rtnl_lock()
2233 * before sending NETDEV_REGISTER and (if up) NETDEV_UP
2234 * events.
2235 *
2236 * But for cases when the netdev is not already present, the notifier
2237 * chain is subjected to be invoked from different CPUs simultaneously.
2238 *
2239 * This is protected by the netdev_mutex.
2240 */
2241static int bnxt_re_netdev_event(struct notifier_block *notifier,
2242 unsigned long event, void *ptr)
2243{
2244 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
2245 struct bnxt_re_dev *rdev;
2246
2247 real_dev = rdma_vlan_dev_real_dev(netdev);
2248 if (!real_dev)
2249 real_dev = netdev;
2250
2251 if (real_dev != netdev)
2252 goto exit;
2253
2254 rdev = bnxt_re_from_netdev(real_dev);
2255 if (!rdev)
2256 return NOTIFY_DONE;
2257
2258
2259 switch (event) {
2260 case NETDEV_UP:
2261 case NETDEV_DOWN:
2262 case NETDEV_CHANGE:
2263 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
2264 netif_carrier_ok(real_dev) ?
2265 IB_EVENT_PORT_ACTIVE :
2266 IB_EVENT_PORT_ERR);
2267 break;
2268 default:
2269 break;
2270 }
2271 ib_device_put(&rdev->ibdev);
2272exit:
2273 return NOTIFY_DONE;
2274}
2275
2276#define BNXT_ADEV_NAME "bnxt_en"
2277
2278static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type,
2279 struct auxiliary_device *aux_dev)
2280{
2281 if (rdev->nb.notifier_call) {
2282 unregister_netdevice_notifier(&rdev->nb);
2283 rdev->nb.notifier_call = NULL;
2284 } else {
2285 /* If notifier is null, we should have already done a
2286 * clean up before coming here.
2287 */
2288 return;
2289 }
2290 bnxt_re_setup_cc(rdev, false);
2291 ib_unregister_device(&rdev->ibdev);
2292 bnxt_re_dev_uninit(rdev, op_type);
2293 ib_dealloc_device(&rdev->ibdev);
2294}
2295
2296static void bnxt_re_remove(struct auxiliary_device *adev)
2297{
2298 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2299 struct bnxt_re_dev *rdev;
2300
2301 mutex_lock(&bnxt_re_mutex);
2302 rdev = en_info->rdev;
2303
2304 if (rdev)
2305 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev);
2306 kfree(en_info);
2307 mutex_unlock(&bnxt_re_mutex);
2308}
2309
2310static int bnxt_re_probe(struct auxiliary_device *adev,
2311 const struct auxiliary_device_id *id)
2312{
2313 struct bnxt_aux_priv *aux_priv =
2314 container_of(adev, struct bnxt_aux_priv, aux_dev);
2315 struct bnxt_re_en_dev_info *en_info;
2316 struct bnxt_en_dev *en_dev;
2317 int rc;
2318
2319 en_dev = aux_priv->edev;
2320
2321 mutex_lock(&bnxt_re_mutex);
2322 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL);
2323 if (!en_info) {
2324 mutex_unlock(&bnxt_re_mutex);
2325 return -ENOMEM;
2326 }
2327 en_info->en_dev = en_dev;
2328
2329 auxiliary_set_drvdata(adev, en_info);
2330
2331 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT);
2332 if (rc)
2333 goto err;
2334 mutex_unlock(&bnxt_re_mutex);
2335 return 0;
2336
2337err:
2338 mutex_unlock(&bnxt_re_mutex);
2339 kfree(en_info);
2340
2341 return rc;
2342}
2343
2344static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
2345{
2346 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2347 struct bnxt_en_dev *en_dev;
2348 struct bnxt_re_dev *rdev;
2349
2350 rdev = en_info->rdev;
2351 en_dev = en_info->en_dev;
2352 mutex_lock(&bnxt_re_mutex);
2353
2354 ibdev_info(&rdev->ibdev, "Handle device suspend call");
2355 /* Check the current device state from bnxt_en_dev and move the
2356 * device to detached state if FW_FATAL_COND is set.
2357 * This prevents more commands to HW during clean-up,
2358 * in case the device is already in error.
2359 */
2360 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) {
2361 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
2362 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
2363 wake_up_all(&rdev->rcfw.cmdq.waitq);
2364 bnxt_re_dev_stop(rdev);
2365 }
2366
2367 if (rdev->pacing.dbr_pacing)
2368 bnxt_re_set_pacing_dev_state(rdev);
2369
2370 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx",
2371 __func__, en_dev->en_state);
2372 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev);
2373 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2374 mutex_unlock(&bnxt_re_mutex);
2375
2376 return 0;
2377}
2378
2379static int bnxt_re_resume(struct auxiliary_device *adev)
2380{
2381 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2382 struct bnxt_re_dev *rdev;
2383
2384 mutex_lock(&bnxt_re_mutex);
2385 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT);
2386 rdev = en_info->rdev;
2387 ibdev_info(&rdev->ibdev, "Device resume completed");
2388 mutex_unlock(&bnxt_re_mutex);
2389
2390 return 0;
2391}
2392
2393static const struct auxiliary_device_id bnxt_re_id_table[] = {
2394 { .name = BNXT_ADEV_NAME ".rdma", },
2395 {},
2396};
2397
2398MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
2399
2400static struct auxiliary_driver bnxt_re_driver = {
2401 .name = "rdma",
2402 .probe = bnxt_re_probe,
2403 .remove = bnxt_re_remove,
2404 .shutdown = bnxt_re_shutdown,
2405 .suspend = bnxt_re_suspend,
2406 .resume = bnxt_re_resume,
2407 .id_table = bnxt_re_id_table,
2408};
2409
2410static int __init bnxt_re_mod_init(void)
2411{
2412 int rc;
2413
2414 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
2415 bnxt_re_register_debugfs();
2416
2417 rc = auxiliary_driver_register(&bnxt_re_driver);
2418 if (rc) {
2419 pr_err("%s: Failed to register auxiliary driver\n",
2420 ROCE_DRV_MODULE_NAME);
2421 goto err_debug;
2422 }
2423 return 0;
2424err_debug:
2425 bnxt_re_unregister_debugfs();
2426 return rc;
2427}
2428
2429static void __exit bnxt_re_mod_exit(void)
2430{
2431 auxiliary_driver_unregister(&bnxt_re_driver);
2432 bnxt_re_unregister_debugfs();
2433}
2434
2435module_init(bnxt_re_mod_init);
2436module_exit(bnxt_re_mod_exit);