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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * OMAP hardware spinlock driver
4 *
5 * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Contact: Simon Que <sque@ti.com>
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
10 * Suman Anna <s-anna@ti.com>
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/device.h>
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/bitops.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/hwspinlock.h>
23#include <linux/of.h>
24#include <linux/platform_device.h>
25
26#include "hwspinlock_internal.h"
27
28/* Spinlock register offsets */
29#define SYSSTATUS_OFFSET 0x0014
30#define LOCK_BASE_OFFSET 0x0800
31
32#define SPINLOCK_NUMLOCKS_BIT_OFFSET (24)
33
34/* Possible values of SPINLOCK_LOCK_REG */
35#define SPINLOCK_NOTTAKEN (0) /* free */
36#define SPINLOCK_TAKEN (1) /* locked */
37
38static int omap_hwspinlock_trylock(struct hwspinlock *lock)
39{
40 void __iomem *lock_addr = lock->priv;
41
42 /* attempt to acquire the lock by reading its value */
43 return (SPINLOCK_NOTTAKEN == readl(lock_addr));
44}
45
46static void omap_hwspinlock_unlock(struct hwspinlock *lock)
47{
48 void __iomem *lock_addr = lock->priv;
49
50 /* release the lock by writing 0 to it */
51 writel(SPINLOCK_NOTTAKEN, lock_addr);
52}
53
54/*
55 * relax the OMAP interconnect while spinning on it.
56 *
57 * The specs recommended that the retry delay time will be
58 * just over half of the time that a requester would be
59 * expected to hold the lock.
60 *
61 * The number below is taken from an hardware specs example,
62 * obviously it is somewhat arbitrary.
63 */
64static void omap_hwspinlock_relax(struct hwspinlock *lock)
65{
66 ndelay(50);
67}
68
69static const struct hwspinlock_ops omap_hwspinlock_ops = {
70 .trylock = omap_hwspinlock_trylock,
71 .unlock = omap_hwspinlock_unlock,
72 .relax = omap_hwspinlock_relax,
73};
74
75static int omap_hwspinlock_probe(struct platform_device *pdev)
76{
77 struct device_node *node = pdev->dev.of_node;
78 struct hwspinlock_device *bank;
79 struct hwspinlock *hwlock;
80 void __iomem *io_base;
81 int num_locks, i, ret;
82 /* Only a single hwspinlock block device is supported */
83 int base_id = 0;
84
85 if (!node)
86 return -ENODEV;
87
88 io_base = devm_platform_ioremap_resource(pdev, 0);
89 if (IS_ERR(io_base))
90 return PTR_ERR(io_base);
91
92 /*
93 * make sure the module is enabled and clocked before reading
94 * the module SYSSTATUS register
95 */
96 pm_runtime_enable(&pdev->dev);
97 ret = pm_runtime_resume_and_get(&pdev->dev);
98 if (ret < 0)
99 goto runtime_err;
100
101 /* Determine number of locks */
102 i = readl(io_base + SYSSTATUS_OFFSET);
103 i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET;
104
105 /*
106 * runtime PM will make sure the clock of this module is
107 * enabled again iff at least one lock is requested
108 */
109 ret = pm_runtime_put(&pdev->dev);
110 if (ret < 0)
111 goto runtime_err;
112
113 /* one of the four lsb's must be set, and nothing else */
114 if (hweight_long(i & 0xf) != 1 || i > 8) {
115 ret = -EINVAL;
116 goto runtime_err;
117 }
118
119 num_locks = i * 32; /* actual number of locks in this device */
120
121 bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
122 GFP_KERNEL);
123 if (!bank) {
124 ret = -ENOMEM;
125 goto runtime_err;
126 }
127
128 platform_set_drvdata(pdev, bank);
129
130 for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
131 hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
132
133 ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops,
134 base_id, num_locks);
135 if (ret)
136 goto runtime_err;
137
138 dev_dbg(&pdev->dev, "Registered %d locks with HwSpinlock core\n",
139 num_locks);
140
141 return 0;
142
143runtime_err:
144 pm_runtime_disable(&pdev->dev);
145 return ret;
146}
147
148static void omap_hwspinlock_remove(struct platform_device *pdev)
149{
150 struct hwspinlock_device *bank = platform_get_drvdata(pdev);
151 int ret;
152
153 ret = hwspin_lock_unregister(bank);
154 if (ret) {
155 dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
156 return;
157 }
158
159 pm_runtime_disable(&pdev->dev);
160}
161
162static const struct of_device_id omap_hwspinlock_of_match[] = {
163 { .compatible = "ti,omap4-hwspinlock", },
164 { .compatible = "ti,am64-hwspinlock", },
165 { .compatible = "ti,am654-hwspinlock", },
166 { /* end */ },
167};
168MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match);
169
170static struct platform_driver omap_hwspinlock_driver = {
171 .probe = omap_hwspinlock_probe,
172 .remove_new = omap_hwspinlock_remove,
173 .driver = {
174 .name = "omap_hwspinlock",
175 .of_match_table = omap_hwspinlock_of_match,
176 },
177};
178
179static int __init omap_hwspinlock_init(void)
180{
181 return platform_driver_register(&omap_hwspinlock_driver);
182}
183/* board init code might need to reserve hwspinlocks for predefined purposes */
184postcore_initcall(omap_hwspinlock_init);
185
186static void __exit omap_hwspinlock_exit(void)
187{
188 platform_driver_unregister(&omap_hwspinlock_driver);
189}
190module_exit(omap_hwspinlock_exit);
191
192MODULE_LICENSE("GPL v2");
193MODULE_DESCRIPTION("Hardware spinlock driver for OMAP");
194MODULE_AUTHOR("Simon Que <sque@ti.com>");
195MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
196MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * OMAP hardware spinlock driver
4 *
5 * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Contact: Simon Que <sque@ti.com>
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
10 * Suman Anna <s-anna@ti.com>
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/device.h>
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/bitops.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/hwspinlock.h>
23#include <linux/of.h>
24#include <linux/platform_device.h>
25
26#include "hwspinlock_internal.h"
27
28/* Spinlock register offsets */
29#define SYSSTATUS_OFFSET 0x0014
30#define LOCK_BASE_OFFSET 0x0800
31
32#define SPINLOCK_NUMLOCKS_BIT_OFFSET (24)
33
34/* Possible values of SPINLOCK_LOCK_REG */
35#define SPINLOCK_NOTTAKEN (0) /* free */
36#define SPINLOCK_TAKEN (1) /* locked */
37
38static int omap_hwspinlock_trylock(struct hwspinlock *lock)
39{
40 void __iomem *lock_addr = lock->priv;
41
42 /* attempt to acquire the lock by reading its value */
43 return (SPINLOCK_NOTTAKEN == readl(lock_addr));
44}
45
46static void omap_hwspinlock_unlock(struct hwspinlock *lock)
47{
48 void __iomem *lock_addr = lock->priv;
49
50 /* release the lock by writing 0 to it */
51 writel(SPINLOCK_NOTTAKEN, lock_addr);
52}
53
54/*
55 * relax the OMAP interconnect while spinning on it.
56 *
57 * The specs recommended that the retry delay time will be
58 * just over half of the time that a requester would be
59 * expected to hold the lock.
60 *
61 * The number below is taken from an hardware specs example,
62 * obviously it is somewhat arbitrary.
63 */
64static void omap_hwspinlock_relax(struct hwspinlock *lock)
65{
66 ndelay(50);
67}
68
69static const struct hwspinlock_ops omap_hwspinlock_ops = {
70 .trylock = omap_hwspinlock_trylock,
71 .unlock = omap_hwspinlock_unlock,
72 .relax = omap_hwspinlock_relax,
73};
74
75static int omap_hwspinlock_probe(struct platform_device *pdev)
76{
77 struct hwspinlock_device *bank;
78 void __iomem *io_base;
79 int num_locks, i, ret;
80 /* Only a single hwspinlock block device is supported */
81 int base_id = 0;
82
83 io_base = devm_platform_ioremap_resource(pdev, 0);
84 if (IS_ERR(io_base))
85 return PTR_ERR(io_base);
86
87 /*
88 * make sure the module is enabled and clocked before reading
89 * the module SYSSTATUS register
90 */
91 devm_pm_runtime_enable(&pdev->dev);
92 ret = pm_runtime_resume_and_get(&pdev->dev);
93 if (ret < 0)
94 return ret;
95
96 /* Determine number of locks */
97 i = readl(io_base + SYSSTATUS_OFFSET);
98 i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET;
99
100 /*
101 * runtime PM will make sure the clock of this module is
102 * enabled again iff at least one lock is requested
103 */
104 ret = pm_runtime_put(&pdev->dev);
105 if (ret < 0)
106 return ret;
107
108 /* one of the four lsb's must be set, and nothing else */
109 if (hweight_long(i & 0xf) != 1 || i > 8)
110 return -EINVAL;
111
112 num_locks = i * 32; /* actual number of locks in this device */
113
114 bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
115 GFP_KERNEL);
116 if (!bank)
117 return -ENOMEM;
118
119 for (i = 0; i < num_locks; i++)
120 bank->lock[i].priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
121
122 return devm_hwspin_lock_register(&pdev->dev, bank, &omap_hwspinlock_ops,
123 base_id, num_locks);
124}
125
126static const struct of_device_id omap_hwspinlock_of_match[] = {
127 { .compatible = "ti,omap4-hwspinlock", },
128 { .compatible = "ti,am64-hwspinlock", },
129 { .compatible = "ti,am654-hwspinlock", },
130 { /* end */ },
131};
132MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match);
133
134static struct platform_driver omap_hwspinlock_driver = {
135 .probe = omap_hwspinlock_probe,
136 .driver = {
137 .name = "omap_hwspinlock",
138 .of_match_table = omap_hwspinlock_of_match,
139 },
140};
141
142static int __init omap_hwspinlock_init(void)
143{
144 return platform_driver_register(&omap_hwspinlock_driver);
145}
146/* board init code might need to reserve hwspinlocks for predefined purposes */
147postcore_initcall(omap_hwspinlock_init);
148
149static void __exit omap_hwspinlock_exit(void)
150{
151 platform_driver_unregister(&omap_hwspinlock_driver);
152}
153module_exit(omap_hwspinlock_exit);
154
155MODULE_LICENSE("GPL v2");
156MODULE_DESCRIPTION("Hardware spinlock driver for OMAP");
157MODULE_AUTHOR("Simon Que <sque@ti.com>");
158MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
159MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");