Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/power_supply.h>
29#include <linux/kthread.h>
30#include <linux/module.h>
31#include <linux/console.h>
32#include <linux/slab.h>
33#include <linux/iommu.h>
34#include <linux/pci.h>
35#include <linux/pci-p2pdma.h>
36#include <linux/apple-gmux.h>
37
38#include <drm/drm_aperture.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_fb_helper.h>
42#include <drm/drm_probe_helper.h>
43#include <drm/amdgpu_drm.h>
44#include <linux/device.h>
45#include <linux/vgaarb.h>
46#include <linux/vga_switcheroo.h>
47#include <linux/efi.h>
48#include "amdgpu.h"
49#include "amdgpu_trace.h"
50#include "amdgpu_i2c.h"
51#include "atom.h"
52#include "amdgpu_atombios.h"
53#include "amdgpu_atomfirmware.h"
54#include "amd_pcie.h"
55#ifdef CONFIG_DRM_AMDGPU_SI
56#include "si.h"
57#endif
58#ifdef CONFIG_DRM_AMDGPU_CIK
59#include "cik.h"
60#endif
61#include "vi.h"
62#include "soc15.h"
63#include "nv.h"
64#include "bif/bif_4_1_d.h"
65#include <linux/firmware.h>
66#include "amdgpu_vf_error.h"
67
68#include "amdgpu_amdkfd.h"
69#include "amdgpu_pm.h"
70
71#include "amdgpu_xgmi.h"
72#include "amdgpu_ras.h"
73#include "amdgpu_pmu.h"
74#include "amdgpu_fru_eeprom.h"
75#include "amdgpu_reset.h"
76#include "amdgpu_virt.h"
77
78#include <linux/suspend.h>
79#include <drm/task_barrier.h>
80#include <linux/pm_runtime.h>
81
82#include <drm/drm_drv.h>
83
84#if IS_ENABLED(CONFIG_X86)
85#include <asm/intel-family.h>
86#endif
87
88MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
95
96#define AMDGPU_RESUME_MS 2000
97#define AMDGPU_MAX_RETRY_LIMIT 2
98#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
99
100static const struct drm_driver amdgpu_kms_driver;
101
102const char *amdgpu_asic_name[] = {
103 "TAHITI",
104 "PITCAIRN",
105 "VERDE",
106 "OLAND",
107 "HAINAN",
108 "BONAIRE",
109 "KAVERI",
110 "KABINI",
111 "HAWAII",
112 "MULLINS",
113 "TOPAZ",
114 "TONGA",
115 "FIJI",
116 "CARRIZO",
117 "STONEY",
118 "POLARIS10",
119 "POLARIS11",
120 "POLARIS12",
121 "VEGAM",
122 "VEGA10",
123 "VEGA12",
124 "VEGA20",
125 "RAVEN",
126 "ARCTURUS",
127 "RENOIR",
128 "ALDEBARAN",
129 "NAVI10",
130 "CYAN_SKILLFISH",
131 "NAVI14",
132 "NAVI12",
133 "SIENNA_CICHLID",
134 "NAVY_FLOUNDER",
135 "VANGOGH",
136 "DIMGREY_CAVEFISH",
137 "BEIGE_GOBY",
138 "YELLOW_CARP",
139 "IP DISCOVERY",
140 "LAST",
141};
142
143/**
144 * DOC: pcie_replay_count
145 *
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
150 */
151
152static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
154{
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
158
159 return sysfs_emit(buf, "%llu\n", cnt);
160}
161
162static DEVICE_ATTR(pcie_replay_count, 0444,
163 amdgpu_device_get_pcie_replay_count, NULL);
164
165static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,
166 struct bin_attribute *attr, char *buf,
167 loff_t ppos, size_t count)
168{
169 struct device *dev = kobj_to_dev(kobj);
170 struct drm_device *ddev = dev_get_drvdata(dev);
171 struct amdgpu_device *adev = drm_to_adev(ddev);
172 ssize_t bytes_read;
173
174 switch (ppos) {
175 case AMDGPU_SYS_REG_STATE_XGMI:
176 bytes_read = amdgpu_asic_get_reg_state(
177 adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);
178 break;
179 case AMDGPU_SYS_REG_STATE_WAFL:
180 bytes_read = amdgpu_asic_get_reg_state(
181 adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);
182 break;
183 case AMDGPU_SYS_REG_STATE_PCIE:
184 bytes_read = amdgpu_asic_get_reg_state(
185 adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);
186 break;
187 case AMDGPU_SYS_REG_STATE_USR:
188 bytes_read = amdgpu_asic_get_reg_state(
189 adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);
190 break;
191 case AMDGPU_SYS_REG_STATE_USR_1:
192 bytes_read = amdgpu_asic_get_reg_state(
193 adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);
194 break;
195 default:
196 return -EINVAL;
197 }
198
199 return bytes_read;
200}
201
202BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,
203 AMDGPU_SYS_REG_STATE_END);
204
205int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)
206{
207 int ret;
208
209 if (!amdgpu_asic_get_reg_state_supported(adev))
210 return 0;
211
212 ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
213
214 return ret;
215}
216
217void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)
218{
219 if (!amdgpu_asic_get_reg_state_supported(adev))
220 return;
221 sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
222}
223
224/**
225 * DOC: board_info
226 *
227 * The amdgpu driver provides a sysfs API for giving board related information.
228 * It provides the form factor information in the format
229 *
230 * type : form factor
231 *
232 * Possible form factor values
233 *
234 * - "cem" - PCIE CEM card
235 * - "oam" - Open Compute Accelerator Module
236 * - "unknown" - Not known
237 *
238 */
239
240static ssize_t amdgpu_device_get_board_info(struct device *dev,
241 struct device_attribute *attr,
242 char *buf)
243{
244 struct drm_device *ddev = dev_get_drvdata(dev);
245 struct amdgpu_device *adev = drm_to_adev(ddev);
246 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
247 const char *pkg;
248
249 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
250 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
251
252 switch (pkg_type) {
253 case AMDGPU_PKG_TYPE_CEM:
254 pkg = "cem";
255 break;
256 case AMDGPU_PKG_TYPE_OAM:
257 pkg = "oam";
258 break;
259 default:
260 pkg = "unknown";
261 break;
262 }
263
264 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
265}
266
267static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
268
269static struct attribute *amdgpu_board_attrs[] = {
270 &dev_attr_board_info.attr,
271 NULL,
272};
273
274static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
275 struct attribute *attr, int n)
276{
277 struct device *dev = kobj_to_dev(kobj);
278 struct drm_device *ddev = dev_get_drvdata(dev);
279 struct amdgpu_device *adev = drm_to_adev(ddev);
280
281 if (adev->flags & AMD_IS_APU)
282 return 0;
283
284 return attr->mode;
285}
286
287static const struct attribute_group amdgpu_board_attrs_group = {
288 .attrs = amdgpu_board_attrs,
289 .is_visible = amdgpu_board_attrs_is_visible
290};
291
292static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
293
294
295/**
296 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
297 *
298 * @dev: drm_device pointer
299 *
300 * Returns true if the device is a dGPU with ATPX power control,
301 * otherwise return false.
302 */
303bool amdgpu_device_supports_px(struct drm_device *dev)
304{
305 struct amdgpu_device *adev = drm_to_adev(dev);
306
307 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
308 return true;
309 return false;
310}
311
312/**
313 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
314 *
315 * @dev: drm_device pointer
316 *
317 * Returns true if the device is a dGPU with ACPI power control,
318 * otherwise return false.
319 */
320bool amdgpu_device_supports_boco(struct drm_device *dev)
321{
322 struct amdgpu_device *adev = drm_to_adev(dev);
323
324 if (adev->has_pr3 ||
325 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
326 return true;
327 return false;
328}
329
330/**
331 * amdgpu_device_supports_baco - Does the device support BACO
332 *
333 * @dev: drm_device pointer
334 *
335 * Returns true if the device supporte BACO,
336 * otherwise return false.
337 */
338bool amdgpu_device_supports_baco(struct drm_device *dev)
339{
340 struct amdgpu_device *adev = drm_to_adev(dev);
341
342 return amdgpu_asic_supports_baco(adev);
343}
344
345/**
346 * amdgpu_device_supports_smart_shift - Is the device dGPU with
347 * smart shift support
348 *
349 * @dev: drm_device pointer
350 *
351 * Returns true if the device is a dGPU with Smart Shift support,
352 * otherwise returns false.
353 */
354bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
355{
356 return (amdgpu_device_supports_boco(dev) &&
357 amdgpu_acpi_is_power_shift_control_supported());
358}
359
360/*
361 * VRAM access helper functions
362 */
363
364/**
365 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
366 *
367 * @adev: amdgpu_device pointer
368 * @pos: offset of the buffer in vram
369 * @buf: virtual address of the buffer in system memory
370 * @size: read/write size, sizeof(@buf) must > @size
371 * @write: true - write to vram, otherwise - read from vram
372 */
373void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
374 void *buf, size_t size, bool write)
375{
376 unsigned long flags;
377 uint32_t hi = ~0, tmp = 0;
378 uint32_t *data = buf;
379 uint64_t last;
380 int idx;
381
382 if (!drm_dev_enter(adev_to_drm(adev), &idx))
383 return;
384
385 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
386
387 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
388 for (last = pos + size; pos < last; pos += 4) {
389 tmp = pos >> 31;
390
391 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
392 if (tmp != hi) {
393 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
394 hi = tmp;
395 }
396 if (write)
397 WREG32_NO_KIQ(mmMM_DATA, *data++);
398 else
399 *data++ = RREG32_NO_KIQ(mmMM_DATA);
400 }
401
402 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
403 drm_dev_exit(idx);
404}
405
406/**
407 * amdgpu_device_aper_access - access vram by vram aperature
408 *
409 * @adev: amdgpu_device pointer
410 * @pos: offset of the buffer in vram
411 * @buf: virtual address of the buffer in system memory
412 * @size: read/write size, sizeof(@buf) must > @size
413 * @write: true - write to vram, otherwise - read from vram
414 *
415 * The return value means how many bytes have been transferred.
416 */
417size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
418 void *buf, size_t size, bool write)
419{
420#ifdef CONFIG_64BIT
421 void __iomem *addr;
422 size_t count = 0;
423 uint64_t last;
424
425 if (!adev->mman.aper_base_kaddr)
426 return 0;
427
428 last = min(pos + size, adev->gmc.visible_vram_size);
429 if (last > pos) {
430 addr = adev->mman.aper_base_kaddr + pos;
431 count = last - pos;
432
433 if (write) {
434 memcpy_toio(addr, buf, count);
435 /* Make sure HDP write cache flush happens without any reordering
436 * after the system memory contents are sent over PCIe device
437 */
438 mb();
439 amdgpu_device_flush_hdp(adev, NULL);
440 } else {
441 amdgpu_device_invalidate_hdp(adev, NULL);
442 /* Make sure HDP read cache is invalidated before issuing a read
443 * to the PCIe device
444 */
445 mb();
446 memcpy_fromio(buf, addr, count);
447 }
448
449 }
450
451 return count;
452#else
453 return 0;
454#endif
455}
456
457/**
458 * amdgpu_device_vram_access - read/write a buffer in vram
459 *
460 * @adev: amdgpu_device pointer
461 * @pos: offset of the buffer in vram
462 * @buf: virtual address of the buffer in system memory
463 * @size: read/write size, sizeof(@buf) must > @size
464 * @write: true - write to vram, otherwise - read from vram
465 */
466void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
467 void *buf, size_t size, bool write)
468{
469 size_t count;
470
471 /* try to using vram apreature to access vram first */
472 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
473 size -= count;
474 if (size) {
475 /* using MM to access rest vram */
476 pos += count;
477 buf += count;
478 amdgpu_device_mm_access(adev, pos, buf, size, write);
479 }
480}
481
482/*
483 * register access helper functions.
484 */
485
486/* Check if hw access should be skipped because of hotplug or device error */
487bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
488{
489 if (adev->no_hw_access)
490 return true;
491
492#ifdef CONFIG_LOCKDEP
493 /*
494 * This is a bit complicated to understand, so worth a comment. What we assert
495 * here is that the GPU reset is not running on another thread in parallel.
496 *
497 * For this we trylock the read side of the reset semaphore, if that succeeds
498 * we know that the reset is not running in paralell.
499 *
500 * If the trylock fails we assert that we are either already holding the read
501 * side of the lock or are the reset thread itself and hold the write side of
502 * the lock.
503 */
504 if (in_task()) {
505 if (down_read_trylock(&adev->reset_domain->sem))
506 up_read(&adev->reset_domain->sem);
507 else
508 lockdep_assert_held(&adev->reset_domain->sem);
509 }
510#endif
511 return false;
512}
513
514/**
515 * amdgpu_device_rreg - read a memory mapped IO or indirect register
516 *
517 * @adev: amdgpu_device pointer
518 * @reg: dword aligned register offset
519 * @acc_flags: access flags which require special behavior
520 *
521 * Returns the 32 bit value from the offset specified.
522 */
523uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
524 uint32_t reg, uint32_t acc_flags)
525{
526 uint32_t ret;
527
528 if (amdgpu_device_skip_hw_access(adev))
529 return 0;
530
531 if ((reg * 4) < adev->rmmio_size) {
532 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
533 amdgpu_sriov_runtime(adev) &&
534 down_read_trylock(&adev->reset_domain->sem)) {
535 ret = amdgpu_kiq_rreg(adev, reg, 0);
536 up_read(&adev->reset_domain->sem);
537 } else {
538 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
539 }
540 } else {
541 ret = adev->pcie_rreg(adev, reg * 4);
542 }
543
544 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
545
546 return ret;
547}
548
549/*
550 * MMIO register read with bytes helper functions
551 * @offset:bytes offset from MMIO start
552 */
553
554/**
555 * amdgpu_mm_rreg8 - read a memory mapped IO register
556 *
557 * @adev: amdgpu_device pointer
558 * @offset: byte aligned register offset
559 *
560 * Returns the 8 bit value from the offset specified.
561 */
562uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
563{
564 if (amdgpu_device_skip_hw_access(adev))
565 return 0;
566
567 if (offset < adev->rmmio_size)
568 return (readb(adev->rmmio + offset));
569 BUG();
570}
571
572
573/**
574 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
575 *
576 * @adev: amdgpu_device pointer
577 * @reg: dword aligned register offset
578 * @acc_flags: access flags which require special behavior
579 * @xcc_id: xcc accelerated compute core id
580 *
581 * Returns the 32 bit value from the offset specified.
582 */
583uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
584 uint32_t reg, uint32_t acc_flags,
585 uint32_t xcc_id)
586{
587 uint32_t ret, rlcg_flag;
588
589 if (amdgpu_device_skip_hw_access(adev))
590 return 0;
591
592 if ((reg * 4) < adev->rmmio_size) {
593 if (amdgpu_sriov_vf(adev) &&
594 !amdgpu_sriov_runtime(adev) &&
595 adev->gfx.rlc.rlcg_reg_access_supported &&
596 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
597 GC_HWIP, false,
598 &rlcg_flag)) {
599 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
600 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
601 amdgpu_sriov_runtime(adev) &&
602 down_read_trylock(&adev->reset_domain->sem)) {
603 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
604 up_read(&adev->reset_domain->sem);
605 } else {
606 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
607 }
608 } else {
609 ret = adev->pcie_rreg(adev, reg * 4);
610 }
611
612 return ret;
613}
614
615/*
616 * MMIO register write with bytes helper functions
617 * @offset:bytes offset from MMIO start
618 * @value: the value want to be written to the register
619 */
620
621/**
622 * amdgpu_mm_wreg8 - read a memory mapped IO register
623 *
624 * @adev: amdgpu_device pointer
625 * @offset: byte aligned register offset
626 * @value: 8 bit value to write
627 *
628 * Writes the value specified to the offset specified.
629 */
630void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
631{
632 if (amdgpu_device_skip_hw_access(adev))
633 return;
634
635 if (offset < adev->rmmio_size)
636 writeb(value, adev->rmmio + offset);
637 else
638 BUG();
639}
640
641/**
642 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
643 *
644 * @adev: amdgpu_device pointer
645 * @reg: dword aligned register offset
646 * @v: 32 bit value to write to the register
647 * @acc_flags: access flags which require special behavior
648 *
649 * Writes the value specified to the offset specified.
650 */
651void amdgpu_device_wreg(struct amdgpu_device *adev,
652 uint32_t reg, uint32_t v,
653 uint32_t acc_flags)
654{
655 if (amdgpu_device_skip_hw_access(adev))
656 return;
657
658 if ((reg * 4) < adev->rmmio_size) {
659 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
660 amdgpu_sriov_runtime(adev) &&
661 down_read_trylock(&adev->reset_domain->sem)) {
662 amdgpu_kiq_wreg(adev, reg, v, 0);
663 up_read(&adev->reset_domain->sem);
664 } else {
665 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
666 }
667 } else {
668 adev->pcie_wreg(adev, reg * 4, v);
669 }
670
671 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
672}
673
674/**
675 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
676 *
677 * @adev: amdgpu_device pointer
678 * @reg: mmio/rlc register
679 * @v: value to write
680 * @xcc_id: xcc accelerated compute core id
681 *
682 * this function is invoked only for the debugfs register access
683 */
684void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
685 uint32_t reg, uint32_t v,
686 uint32_t xcc_id)
687{
688 if (amdgpu_device_skip_hw_access(adev))
689 return;
690
691 if (amdgpu_sriov_fullaccess(adev) &&
692 adev->gfx.rlc.funcs &&
693 adev->gfx.rlc.funcs->is_rlcg_access_range) {
694 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
695 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
696 } else if ((reg * 4) >= adev->rmmio_size) {
697 adev->pcie_wreg(adev, reg * 4, v);
698 } else {
699 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
700 }
701}
702
703/**
704 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
705 *
706 * @adev: amdgpu_device pointer
707 * @reg: dword aligned register offset
708 * @v: 32 bit value to write to the register
709 * @acc_flags: access flags which require special behavior
710 * @xcc_id: xcc accelerated compute core id
711 *
712 * Writes the value specified to the offset specified.
713 */
714void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
715 uint32_t reg, uint32_t v,
716 uint32_t acc_flags, uint32_t xcc_id)
717{
718 uint32_t rlcg_flag;
719
720 if (amdgpu_device_skip_hw_access(adev))
721 return;
722
723 if ((reg * 4) < adev->rmmio_size) {
724 if (amdgpu_sriov_vf(adev) &&
725 !amdgpu_sriov_runtime(adev) &&
726 adev->gfx.rlc.rlcg_reg_access_supported &&
727 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
728 GC_HWIP, true,
729 &rlcg_flag)) {
730 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
731 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
732 amdgpu_sriov_runtime(adev) &&
733 down_read_trylock(&adev->reset_domain->sem)) {
734 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
735 up_read(&adev->reset_domain->sem);
736 } else {
737 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
738 }
739 } else {
740 adev->pcie_wreg(adev, reg * 4, v);
741 }
742}
743
744/**
745 * amdgpu_device_indirect_rreg - read an indirect register
746 *
747 * @adev: amdgpu_device pointer
748 * @reg_addr: indirect register address to read from
749 *
750 * Returns the value of indirect register @reg_addr
751 */
752u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
753 u32 reg_addr)
754{
755 unsigned long flags, pcie_index, pcie_data;
756 void __iomem *pcie_index_offset;
757 void __iomem *pcie_data_offset;
758 u32 r;
759
760 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
761 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
762
763 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
764 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
765 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
766
767 writel(reg_addr, pcie_index_offset);
768 readl(pcie_index_offset);
769 r = readl(pcie_data_offset);
770 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
771
772 return r;
773}
774
775u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
776 u64 reg_addr)
777{
778 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
779 u32 r;
780 void __iomem *pcie_index_offset;
781 void __iomem *pcie_index_hi_offset;
782 void __iomem *pcie_data_offset;
783
784 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
785 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
786 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
787 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
788 else
789 pcie_index_hi = 0;
790
791 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
792 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
793 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
794 if (pcie_index_hi != 0)
795 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
796 pcie_index_hi * 4;
797
798 writel(reg_addr, pcie_index_offset);
799 readl(pcie_index_offset);
800 if (pcie_index_hi != 0) {
801 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
802 readl(pcie_index_hi_offset);
803 }
804 r = readl(pcie_data_offset);
805
806 /* clear the high bits */
807 if (pcie_index_hi != 0) {
808 writel(0, pcie_index_hi_offset);
809 readl(pcie_index_hi_offset);
810 }
811
812 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
813
814 return r;
815}
816
817/**
818 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
819 *
820 * @adev: amdgpu_device pointer
821 * @reg_addr: indirect register address to read from
822 *
823 * Returns the value of indirect register @reg_addr
824 */
825u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
826 u32 reg_addr)
827{
828 unsigned long flags, pcie_index, pcie_data;
829 void __iomem *pcie_index_offset;
830 void __iomem *pcie_data_offset;
831 u64 r;
832
833 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
834 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
835
836 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
837 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
838 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
839
840 /* read low 32 bits */
841 writel(reg_addr, pcie_index_offset);
842 readl(pcie_index_offset);
843 r = readl(pcie_data_offset);
844 /* read high 32 bits */
845 writel(reg_addr + 4, pcie_index_offset);
846 readl(pcie_index_offset);
847 r |= ((u64)readl(pcie_data_offset) << 32);
848 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
849
850 return r;
851}
852
853u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
854 u64 reg_addr)
855{
856 unsigned long flags, pcie_index, pcie_data;
857 unsigned long pcie_index_hi = 0;
858 void __iomem *pcie_index_offset;
859 void __iomem *pcie_index_hi_offset;
860 void __iomem *pcie_data_offset;
861 u64 r;
862
863 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
864 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
865 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
866 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
867
868 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
869 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
870 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
871 if (pcie_index_hi != 0)
872 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
873 pcie_index_hi * 4;
874
875 /* read low 32 bits */
876 writel(reg_addr, pcie_index_offset);
877 readl(pcie_index_offset);
878 if (pcie_index_hi != 0) {
879 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
880 readl(pcie_index_hi_offset);
881 }
882 r = readl(pcie_data_offset);
883 /* read high 32 bits */
884 writel(reg_addr + 4, pcie_index_offset);
885 readl(pcie_index_offset);
886 if (pcie_index_hi != 0) {
887 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
888 readl(pcie_index_hi_offset);
889 }
890 r |= ((u64)readl(pcie_data_offset) << 32);
891
892 /* clear the high bits */
893 if (pcie_index_hi != 0) {
894 writel(0, pcie_index_hi_offset);
895 readl(pcie_index_hi_offset);
896 }
897
898 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
899
900 return r;
901}
902
903/**
904 * amdgpu_device_indirect_wreg - write an indirect register address
905 *
906 * @adev: amdgpu_device pointer
907 * @reg_addr: indirect register offset
908 * @reg_data: indirect register data
909 *
910 */
911void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
912 u32 reg_addr, u32 reg_data)
913{
914 unsigned long flags, pcie_index, pcie_data;
915 void __iomem *pcie_index_offset;
916 void __iomem *pcie_data_offset;
917
918 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
919 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
920
921 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
922 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
923 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
924
925 writel(reg_addr, pcie_index_offset);
926 readl(pcie_index_offset);
927 writel(reg_data, pcie_data_offset);
928 readl(pcie_data_offset);
929 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
930}
931
932void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
933 u64 reg_addr, u32 reg_data)
934{
935 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
936 void __iomem *pcie_index_offset;
937 void __iomem *pcie_index_hi_offset;
938 void __iomem *pcie_data_offset;
939
940 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
941 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
942 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
943 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
944 else
945 pcie_index_hi = 0;
946
947 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
948 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
949 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
950 if (pcie_index_hi != 0)
951 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
952 pcie_index_hi * 4;
953
954 writel(reg_addr, pcie_index_offset);
955 readl(pcie_index_offset);
956 if (pcie_index_hi != 0) {
957 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
958 readl(pcie_index_hi_offset);
959 }
960 writel(reg_data, pcie_data_offset);
961 readl(pcie_data_offset);
962
963 /* clear the high bits */
964 if (pcie_index_hi != 0) {
965 writel(0, pcie_index_hi_offset);
966 readl(pcie_index_hi_offset);
967 }
968
969 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
970}
971
972/**
973 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
974 *
975 * @adev: amdgpu_device pointer
976 * @reg_addr: indirect register offset
977 * @reg_data: indirect register data
978 *
979 */
980void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
981 u32 reg_addr, u64 reg_data)
982{
983 unsigned long flags, pcie_index, pcie_data;
984 void __iomem *pcie_index_offset;
985 void __iomem *pcie_data_offset;
986
987 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
988 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
989
990 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
991 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
992 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
993
994 /* write low 32 bits */
995 writel(reg_addr, pcie_index_offset);
996 readl(pcie_index_offset);
997 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
998 readl(pcie_data_offset);
999 /* write high 32 bits */
1000 writel(reg_addr + 4, pcie_index_offset);
1001 readl(pcie_index_offset);
1002 writel((u32)(reg_data >> 32), pcie_data_offset);
1003 readl(pcie_data_offset);
1004 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1005}
1006
1007void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1008 u64 reg_addr, u64 reg_data)
1009{
1010 unsigned long flags, pcie_index, pcie_data;
1011 unsigned long pcie_index_hi = 0;
1012 void __iomem *pcie_index_offset;
1013 void __iomem *pcie_index_hi_offset;
1014 void __iomem *pcie_data_offset;
1015
1016 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1017 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1018 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1019 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1020
1021 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1022 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1023 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1024 if (pcie_index_hi != 0)
1025 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1026 pcie_index_hi * 4;
1027
1028 /* write low 32 bits */
1029 writel(reg_addr, pcie_index_offset);
1030 readl(pcie_index_offset);
1031 if (pcie_index_hi != 0) {
1032 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1033 readl(pcie_index_hi_offset);
1034 }
1035 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1036 readl(pcie_data_offset);
1037 /* write high 32 bits */
1038 writel(reg_addr + 4, pcie_index_offset);
1039 readl(pcie_index_offset);
1040 if (pcie_index_hi != 0) {
1041 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1042 readl(pcie_index_hi_offset);
1043 }
1044 writel((u32)(reg_data >> 32), pcie_data_offset);
1045 readl(pcie_data_offset);
1046
1047 /* clear the high bits */
1048 if (pcie_index_hi != 0) {
1049 writel(0, pcie_index_hi_offset);
1050 readl(pcie_index_hi_offset);
1051 }
1052
1053 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1054}
1055
1056/**
1057 * amdgpu_device_get_rev_id - query device rev_id
1058 *
1059 * @adev: amdgpu_device pointer
1060 *
1061 * Return device rev_id
1062 */
1063u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1064{
1065 return adev->nbio.funcs->get_rev_id(adev);
1066}
1067
1068/**
1069 * amdgpu_invalid_rreg - dummy reg read function
1070 *
1071 * @adev: amdgpu_device pointer
1072 * @reg: offset of register
1073 *
1074 * Dummy register read function. Used for register blocks
1075 * that certain asics don't have (all asics).
1076 * Returns the value in the register.
1077 */
1078static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1079{
1080 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1081 BUG();
1082 return 0;
1083}
1084
1085static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1086{
1087 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1088 BUG();
1089 return 0;
1090}
1091
1092/**
1093 * amdgpu_invalid_wreg - dummy reg write function
1094 *
1095 * @adev: amdgpu_device pointer
1096 * @reg: offset of register
1097 * @v: value to write to the register
1098 *
1099 * Dummy register read function. Used for register blocks
1100 * that certain asics don't have (all asics).
1101 */
1102static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1103{
1104 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1105 reg, v);
1106 BUG();
1107}
1108
1109static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1110{
1111 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1112 reg, v);
1113 BUG();
1114}
1115
1116/**
1117 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1118 *
1119 * @adev: amdgpu_device pointer
1120 * @reg: offset of register
1121 *
1122 * Dummy register read function. Used for register blocks
1123 * that certain asics don't have (all asics).
1124 * Returns the value in the register.
1125 */
1126static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1127{
1128 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1129 BUG();
1130 return 0;
1131}
1132
1133static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1134{
1135 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1136 BUG();
1137 return 0;
1138}
1139
1140/**
1141 * amdgpu_invalid_wreg64 - dummy reg write function
1142 *
1143 * @adev: amdgpu_device pointer
1144 * @reg: offset of register
1145 * @v: value to write to the register
1146 *
1147 * Dummy register read function. Used for register blocks
1148 * that certain asics don't have (all asics).
1149 */
1150static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1151{
1152 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1153 reg, v);
1154 BUG();
1155}
1156
1157static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1158{
1159 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1160 reg, v);
1161 BUG();
1162}
1163
1164/**
1165 * amdgpu_block_invalid_rreg - dummy reg read function
1166 *
1167 * @adev: amdgpu_device pointer
1168 * @block: offset of instance
1169 * @reg: offset of register
1170 *
1171 * Dummy register read function. Used for register blocks
1172 * that certain asics don't have (all asics).
1173 * Returns the value in the register.
1174 */
1175static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1176 uint32_t block, uint32_t reg)
1177{
1178 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1179 reg, block);
1180 BUG();
1181 return 0;
1182}
1183
1184/**
1185 * amdgpu_block_invalid_wreg - dummy reg write function
1186 *
1187 * @adev: amdgpu_device pointer
1188 * @block: offset of instance
1189 * @reg: offset of register
1190 * @v: value to write to the register
1191 *
1192 * Dummy register read function. Used for register blocks
1193 * that certain asics don't have (all asics).
1194 */
1195static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1196 uint32_t block,
1197 uint32_t reg, uint32_t v)
1198{
1199 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1200 reg, block, v);
1201 BUG();
1202}
1203
1204/**
1205 * amdgpu_device_asic_init - Wrapper for atom asic_init
1206 *
1207 * @adev: amdgpu_device pointer
1208 *
1209 * Does any asic specific work and then calls atom asic init.
1210 */
1211static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1212{
1213 int ret;
1214
1215 amdgpu_asic_pre_asic_init(adev);
1216
1217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1218 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1219 amdgpu_psp_wait_for_bootloader(adev);
1220 ret = amdgpu_atomfirmware_asic_init(adev, true);
1221 /* TODO: check the return val and stop device initialization if boot fails */
1222 amdgpu_psp_query_boot_status(adev);
1223 return ret;
1224 } else {
1225 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1226 }
1227
1228 return 0;
1229}
1230
1231/**
1232 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1233 *
1234 * @adev: amdgpu_device pointer
1235 *
1236 * Allocates a scratch page of VRAM for use by various things in the
1237 * driver.
1238 */
1239static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1240{
1241 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1242 AMDGPU_GEM_DOMAIN_VRAM |
1243 AMDGPU_GEM_DOMAIN_GTT,
1244 &adev->mem_scratch.robj,
1245 &adev->mem_scratch.gpu_addr,
1246 (void **)&adev->mem_scratch.ptr);
1247}
1248
1249/**
1250 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1251 *
1252 * @adev: amdgpu_device pointer
1253 *
1254 * Frees the VRAM scratch page.
1255 */
1256static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1257{
1258 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1259}
1260
1261/**
1262 * amdgpu_device_program_register_sequence - program an array of registers.
1263 *
1264 * @adev: amdgpu_device pointer
1265 * @registers: pointer to the register array
1266 * @array_size: size of the register array
1267 *
1268 * Programs an array or registers with and or masks.
1269 * This is a helper for setting golden registers.
1270 */
1271void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1272 const u32 *registers,
1273 const u32 array_size)
1274{
1275 u32 tmp, reg, and_mask, or_mask;
1276 int i;
1277
1278 if (array_size % 3)
1279 return;
1280
1281 for (i = 0; i < array_size; i += 3) {
1282 reg = registers[i + 0];
1283 and_mask = registers[i + 1];
1284 or_mask = registers[i + 2];
1285
1286 if (and_mask == 0xffffffff) {
1287 tmp = or_mask;
1288 } else {
1289 tmp = RREG32(reg);
1290 tmp &= ~and_mask;
1291 if (adev->family >= AMDGPU_FAMILY_AI)
1292 tmp |= (or_mask & and_mask);
1293 else
1294 tmp |= or_mask;
1295 }
1296 WREG32(reg, tmp);
1297 }
1298}
1299
1300/**
1301 * amdgpu_device_pci_config_reset - reset the GPU
1302 *
1303 * @adev: amdgpu_device pointer
1304 *
1305 * Resets the GPU using the pci config reset sequence.
1306 * Only applicable to asics prior to vega10.
1307 */
1308void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1309{
1310 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1311}
1312
1313/**
1314 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1315 *
1316 * @adev: amdgpu_device pointer
1317 *
1318 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1319 */
1320int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1321{
1322 return pci_reset_function(adev->pdev);
1323}
1324
1325/*
1326 * amdgpu_device_wb_*()
1327 * Writeback is the method by which the GPU updates special pages in memory
1328 * with the status of certain GPU events (fences, ring pointers,etc.).
1329 */
1330
1331/**
1332 * amdgpu_device_wb_fini - Disable Writeback and free memory
1333 *
1334 * @adev: amdgpu_device pointer
1335 *
1336 * Disables Writeback and frees the Writeback memory (all asics).
1337 * Used at driver shutdown.
1338 */
1339static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1340{
1341 if (adev->wb.wb_obj) {
1342 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1343 &adev->wb.gpu_addr,
1344 (void **)&adev->wb.wb);
1345 adev->wb.wb_obj = NULL;
1346 }
1347}
1348
1349/**
1350 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1351 *
1352 * @adev: amdgpu_device pointer
1353 *
1354 * Initializes writeback and allocates writeback memory (all asics).
1355 * Used at driver startup.
1356 * Returns 0 on success or an -error on failure.
1357 */
1358static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1359{
1360 int r;
1361
1362 if (adev->wb.wb_obj == NULL) {
1363 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1364 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1365 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1366 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1367 (void **)&adev->wb.wb);
1368 if (r) {
1369 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1370 return r;
1371 }
1372
1373 adev->wb.num_wb = AMDGPU_MAX_WB;
1374 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1375
1376 /* clear wb memory */
1377 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1378 }
1379
1380 return 0;
1381}
1382
1383/**
1384 * amdgpu_device_wb_get - Allocate a wb entry
1385 *
1386 * @adev: amdgpu_device pointer
1387 * @wb: wb index
1388 *
1389 * Allocate a wb slot for use by the driver (all asics).
1390 * Returns 0 on success or -EINVAL on failure.
1391 */
1392int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1393{
1394 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1395
1396 if (offset < adev->wb.num_wb) {
1397 __set_bit(offset, adev->wb.used);
1398 *wb = offset << 3; /* convert to dw offset */
1399 return 0;
1400 } else {
1401 return -EINVAL;
1402 }
1403}
1404
1405/**
1406 * amdgpu_device_wb_free - Free a wb entry
1407 *
1408 * @adev: amdgpu_device pointer
1409 * @wb: wb index
1410 *
1411 * Free a wb slot allocated for use by the driver (all asics)
1412 */
1413void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1414{
1415 wb >>= 3;
1416 if (wb < adev->wb.num_wb)
1417 __clear_bit(wb, adev->wb.used);
1418}
1419
1420/**
1421 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1422 *
1423 * @adev: amdgpu_device pointer
1424 *
1425 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1426 * to fail, but if any of the BARs is not accessible after the size we abort
1427 * driver loading by returning -ENODEV.
1428 */
1429int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1430{
1431 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1432 struct pci_bus *root;
1433 struct resource *res;
1434 unsigned int i;
1435 u16 cmd;
1436 int r;
1437
1438 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1439 return 0;
1440
1441 /* Bypass for VF */
1442 if (amdgpu_sriov_vf(adev))
1443 return 0;
1444
1445 /* skip if the bios has already enabled large BAR */
1446 if (adev->gmc.real_vram_size &&
1447 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1448 return 0;
1449
1450 /* Check if the root BUS has 64bit memory resources */
1451 root = adev->pdev->bus;
1452 while (root->parent)
1453 root = root->parent;
1454
1455 pci_bus_for_each_resource(root, res, i) {
1456 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1457 res->start > 0x100000000ull)
1458 break;
1459 }
1460
1461 /* Trying to resize is pointless without a root hub window above 4GB */
1462 if (!res)
1463 return 0;
1464
1465 /* Limit the BAR size to what is available */
1466 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1467 rbar_size);
1468
1469 /* Disable memory decoding while we change the BAR addresses and size */
1470 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1471 pci_write_config_word(adev->pdev, PCI_COMMAND,
1472 cmd & ~PCI_COMMAND_MEMORY);
1473
1474 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1475 amdgpu_doorbell_fini(adev);
1476 if (adev->asic_type >= CHIP_BONAIRE)
1477 pci_release_resource(adev->pdev, 2);
1478
1479 pci_release_resource(adev->pdev, 0);
1480
1481 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1482 if (r == -ENOSPC)
1483 DRM_INFO("Not enough PCI address space for a large BAR.");
1484 else if (r && r != -ENOTSUPP)
1485 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1486
1487 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1488
1489 /* When the doorbell or fb BAR isn't available we have no chance of
1490 * using the device.
1491 */
1492 r = amdgpu_doorbell_init(adev);
1493 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1494 return -ENODEV;
1495
1496 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1497
1498 return 0;
1499}
1500
1501static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1502{
1503 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1504 return false;
1505
1506 return true;
1507}
1508
1509/*
1510 * GPU helpers function.
1511 */
1512/**
1513 * amdgpu_device_need_post - check if the hw need post or not
1514 *
1515 * @adev: amdgpu_device pointer
1516 *
1517 * Check if the asic has been initialized (all asics) at driver startup
1518 * or post is needed if hw reset is performed.
1519 * Returns true if need or false if not.
1520 */
1521bool amdgpu_device_need_post(struct amdgpu_device *adev)
1522{
1523 uint32_t reg;
1524
1525 if (amdgpu_sriov_vf(adev))
1526 return false;
1527
1528 if (!amdgpu_device_read_bios(adev))
1529 return false;
1530
1531 if (amdgpu_passthrough(adev)) {
1532 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1533 * some old smc fw still need driver do vPost otherwise gpu hang, while
1534 * those smc fw version above 22.15 doesn't have this flaw, so we force
1535 * vpost executed for smc version below 22.15
1536 */
1537 if (adev->asic_type == CHIP_FIJI) {
1538 int err;
1539 uint32_t fw_ver;
1540
1541 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1542 /* force vPost if error occured */
1543 if (err)
1544 return true;
1545
1546 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1547 release_firmware(adev->pm.fw);
1548 if (fw_ver < 0x00160e00)
1549 return true;
1550 }
1551 }
1552
1553 /* Don't post if we need to reset whole hive on init */
1554 if (adev->gmc.xgmi.pending_reset)
1555 return false;
1556
1557 if (adev->has_hw_reset) {
1558 adev->has_hw_reset = false;
1559 return true;
1560 }
1561
1562 /* bios scratch used on CIK+ */
1563 if (adev->asic_type >= CHIP_BONAIRE)
1564 return amdgpu_atombios_scratch_need_asic_init(adev);
1565
1566 /* check MEM_SIZE for older asics */
1567 reg = amdgpu_asic_get_config_memsize(adev);
1568
1569 if ((reg != 0) && (reg != 0xffffffff))
1570 return false;
1571
1572 return true;
1573}
1574
1575/*
1576 * Check whether seamless boot is supported.
1577 *
1578 * So far we only support seamless boot on DCE 3.0 or later.
1579 * If users report that it works on older ASICS as well, we may
1580 * loosen this.
1581 */
1582bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1583{
1584 switch (amdgpu_seamless) {
1585 case -1:
1586 break;
1587 case 1:
1588 return true;
1589 case 0:
1590 return false;
1591 default:
1592 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1593 amdgpu_seamless);
1594 return false;
1595 }
1596
1597 if (!(adev->flags & AMD_IS_APU))
1598 return false;
1599
1600 if (adev->mman.keep_stolen_vga_memory)
1601 return false;
1602
1603 return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0);
1604}
1605
1606/*
1607 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1608 * don't support dynamic speed switching. Until we have confirmation from Intel
1609 * that a specific host supports it, it's safer that we keep it disabled for all.
1610 *
1611 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1612 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1613 */
1614static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)
1615{
1616#if IS_ENABLED(CONFIG_X86)
1617 struct cpuinfo_x86 *c = &cpu_data(0);
1618
1619 /* eGPU change speeds based on USB4 fabric conditions */
1620 if (dev_is_removable(adev->dev))
1621 return true;
1622
1623 if (c->x86_vendor == X86_VENDOR_INTEL)
1624 return false;
1625#endif
1626 return true;
1627}
1628
1629/**
1630 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1631 *
1632 * @adev: amdgpu_device pointer
1633 *
1634 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1635 * be set for this device.
1636 *
1637 * Returns true if it should be used or false if not.
1638 */
1639bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1640{
1641 switch (amdgpu_aspm) {
1642 case -1:
1643 break;
1644 case 0:
1645 return false;
1646 case 1:
1647 return true;
1648 default:
1649 return false;
1650 }
1651 if (adev->flags & AMD_IS_APU)
1652 return false;
1653 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1654 return false;
1655 return pcie_aspm_enabled(adev->pdev);
1656}
1657
1658/* if we get transitioned to only one device, take VGA back */
1659/**
1660 * amdgpu_device_vga_set_decode - enable/disable vga decode
1661 *
1662 * @pdev: PCI device pointer
1663 * @state: enable/disable vga decode
1664 *
1665 * Enable/disable vga decode (all asics).
1666 * Returns VGA resource flags.
1667 */
1668static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1669 bool state)
1670{
1671 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1672
1673 amdgpu_asic_set_vga_state(adev, state);
1674 if (state)
1675 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1676 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1677 else
1678 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1679}
1680
1681/**
1682 * amdgpu_device_check_block_size - validate the vm block size
1683 *
1684 * @adev: amdgpu_device pointer
1685 *
1686 * Validates the vm block size specified via module parameter.
1687 * The vm block size defines number of bits in page table versus page directory,
1688 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1689 * page table and the remaining bits are in the page directory.
1690 */
1691static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1692{
1693 /* defines number of bits in page table versus page directory,
1694 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1695 * page table and the remaining bits are in the page directory
1696 */
1697 if (amdgpu_vm_block_size == -1)
1698 return;
1699
1700 if (amdgpu_vm_block_size < 9) {
1701 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1702 amdgpu_vm_block_size);
1703 amdgpu_vm_block_size = -1;
1704 }
1705}
1706
1707/**
1708 * amdgpu_device_check_vm_size - validate the vm size
1709 *
1710 * @adev: amdgpu_device pointer
1711 *
1712 * Validates the vm size in GB specified via module parameter.
1713 * The VM size is the size of the GPU virtual memory space in GB.
1714 */
1715static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1716{
1717 /* no need to check the default value */
1718 if (amdgpu_vm_size == -1)
1719 return;
1720
1721 if (amdgpu_vm_size < 1) {
1722 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1723 amdgpu_vm_size);
1724 amdgpu_vm_size = -1;
1725 }
1726}
1727
1728static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1729{
1730 struct sysinfo si;
1731 bool is_os_64 = (sizeof(void *) == 8);
1732 uint64_t total_memory;
1733 uint64_t dram_size_seven_GB = 0x1B8000000;
1734 uint64_t dram_size_three_GB = 0xB8000000;
1735
1736 if (amdgpu_smu_memory_pool_size == 0)
1737 return;
1738
1739 if (!is_os_64) {
1740 DRM_WARN("Not 64-bit OS, feature not supported\n");
1741 goto def_value;
1742 }
1743 si_meminfo(&si);
1744 total_memory = (uint64_t)si.totalram * si.mem_unit;
1745
1746 if ((amdgpu_smu_memory_pool_size == 1) ||
1747 (amdgpu_smu_memory_pool_size == 2)) {
1748 if (total_memory < dram_size_three_GB)
1749 goto def_value1;
1750 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1751 (amdgpu_smu_memory_pool_size == 8)) {
1752 if (total_memory < dram_size_seven_GB)
1753 goto def_value1;
1754 } else {
1755 DRM_WARN("Smu memory pool size not supported\n");
1756 goto def_value;
1757 }
1758 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1759
1760 return;
1761
1762def_value1:
1763 DRM_WARN("No enough system memory\n");
1764def_value:
1765 adev->pm.smu_prv_buffer_size = 0;
1766}
1767
1768static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1769{
1770 if (!(adev->flags & AMD_IS_APU) ||
1771 adev->asic_type < CHIP_RAVEN)
1772 return 0;
1773
1774 switch (adev->asic_type) {
1775 case CHIP_RAVEN:
1776 if (adev->pdev->device == 0x15dd)
1777 adev->apu_flags |= AMD_APU_IS_RAVEN;
1778 if (adev->pdev->device == 0x15d8)
1779 adev->apu_flags |= AMD_APU_IS_PICASSO;
1780 break;
1781 case CHIP_RENOIR:
1782 if ((adev->pdev->device == 0x1636) ||
1783 (adev->pdev->device == 0x164c))
1784 adev->apu_flags |= AMD_APU_IS_RENOIR;
1785 else
1786 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1787 break;
1788 case CHIP_VANGOGH:
1789 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1790 break;
1791 case CHIP_YELLOW_CARP:
1792 break;
1793 case CHIP_CYAN_SKILLFISH:
1794 if ((adev->pdev->device == 0x13FE) ||
1795 (adev->pdev->device == 0x143F))
1796 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1797 break;
1798 default:
1799 break;
1800 }
1801
1802 return 0;
1803}
1804
1805/**
1806 * amdgpu_device_check_arguments - validate module params
1807 *
1808 * @adev: amdgpu_device pointer
1809 *
1810 * Validates certain module parameters and updates
1811 * the associated values used by the driver (all asics).
1812 */
1813static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1814{
1815 if (amdgpu_sched_jobs < 4) {
1816 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1817 amdgpu_sched_jobs);
1818 amdgpu_sched_jobs = 4;
1819 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1820 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1821 amdgpu_sched_jobs);
1822 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1823 }
1824
1825 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1826 /* gart size must be greater or equal to 32M */
1827 dev_warn(adev->dev, "gart size (%d) too small\n",
1828 amdgpu_gart_size);
1829 amdgpu_gart_size = -1;
1830 }
1831
1832 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1833 /* gtt size must be greater or equal to 32M */
1834 dev_warn(adev->dev, "gtt size (%d) too small\n",
1835 amdgpu_gtt_size);
1836 amdgpu_gtt_size = -1;
1837 }
1838
1839 /* valid range is between 4 and 9 inclusive */
1840 if (amdgpu_vm_fragment_size != -1 &&
1841 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1842 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1843 amdgpu_vm_fragment_size = -1;
1844 }
1845
1846 if (amdgpu_sched_hw_submission < 2) {
1847 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1848 amdgpu_sched_hw_submission);
1849 amdgpu_sched_hw_submission = 2;
1850 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1851 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1852 amdgpu_sched_hw_submission);
1853 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1854 }
1855
1856 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1857 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1858 amdgpu_reset_method = -1;
1859 }
1860
1861 amdgpu_device_check_smu_prv_buffer_size(adev);
1862
1863 amdgpu_device_check_vm_size(adev);
1864
1865 amdgpu_device_check_block_size(adev);
1866
1867 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1868
1869 return 0;
1870}
1871
1872/**
1873 * amdgpu_switcheroo_set_state - set switcheroo state
1874 *
1875 * @pdev: pci dev pointer
1876 * @state: vga_switcheroo state
1877 *
1878 * Callback for the switcheroo driver. Suspends or resumes
1879 * the asics before or after it is powered up using ACPI methods.
1880 */
1881static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1882 enum vga_switcheroo_state state)
1883{
1884 struct drm_device *dev = pci_get_drvdata(pdev);
1885 int r;
1886
1887 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1888 return;
1889
1890 if (state == VGA_SWITCHEROO_ON) {
1891 pr_info("switched on\n");
1892 /* don't suspend or resume card normally */
1893 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1894
1895 pci_set_power_state(pdev, PCI_D0);
1896 amdgpu_device_load_pci_state(pdev);
1897 r = pci_enable_device(pdev);
1898 if (r)
1899 DRM_WARN("pci_enable_device failed (%d)\n", r);
1900 amdgpu_device_resume(dev, true);
1901
1902 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1903 } else {
1904 pr_info("switched off\n");
1905 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1906 amdgpu_device_prepare(dev);
1907 amdgpu_device_suspend(dev, true);
1908 amdgpu_device_cache_pci_state(pdev);
1909 /* Shut down the device */
1910 pci_disable_device(pdev);
1911 pci_set_power_state(pdev, PCI_D3cold);
1912 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1913 }
1914}
1915
1916/**
1917 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1918 *
1919 * @pdev: pci dev pointer
1920 *
1921 * Callback for the switcheroo driver. Check of the switcheroo
1922 * state can be changed.
1923 * Returns true if the state can be changed, false if not.
1924 */
1925static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1926{
1927 struct drm_device *dev = pci_get_drvdata(pdev);
1928
1929 /*
1930 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1931 * locking inversion with the driver load path. And the access here is
1932 * completely racy anyway. So don't bother with locking for now.
1933 */
1934 return atomic_read(&dev->open_count) == 0;
1935}
1936
1937static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1938 .set_gpu_state = amdgpu_switcheroo_set_state,
1939 .reprobe = NULL,
1940 .can_switch = amdgpu_switcheroo_can_switch,
1941};
1942
1943/**
1944 * amdgpu_device_ip_set_clockgating_state - set the CG state
1945 *
1946 * @dev: amdgpu_device pointer
1947 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1948 * @state: clockgating state (gate or ungate)
1949 *
1950 * Sets the requested clockgating state for all instances of
1951 * the hardware IP specified.
1952 * Returns the error code from the last instance.
1953 */
1954int amdgpu_device_ip_set_clockgating_state(void *dev,
1955 enum amd_ip_block_type block_type,
1956 enum amd_clockgating_state state)
1957{
1958 struct amdgpu_device *adev = dev;
1959 int i, r = 0;
1960
1961 for (i = 0; i < adev->num_ip_blocks; i++) {
1962 if (!adev->ip_blocks[i].status.valid)
1963 continue;
1964 if (adev->ip_blocks[i].version->type != block_type)
1965 continue;
1966 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1967 continue;
1968 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1969 (void *)adev, state);
1970 if (r)
1971 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1972 adev->ip_blocks[i].version->funcs->name, r);
1973 }
1974 return r;
1975}
1976
1977/**
1978 * amdgpu_device_ip_set_powergating_state - set the PG state
1979 *
1980 * @dev: amdgpu_device pointer
1981 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1982 * @state: powergating state (gate or ungate)
1983 *
1984 * Sets the requested powergating state for all instances of
1985 * the hardware IP specified.
1986 * Returns the error code from the last instance.
1987 */
1988int amdgpu_device_ip_set_powergating_state(void *dev,
1989 enum amd_ip_block_type block_type,
1990 enum amd_powergating_state state)
1991{
1992 struct amdgpu_device *adev = dev;
1993 int i, r = 0;
1994
1995 for (i = 0; i < adev->num_ip_blocks; i++) {
1996 if (!adev->ip_blocks[i].status.valid)
1997 continue;
1998 if (adev->ip_blocks[i].version->type != block_type)
1999 continue;
2000 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
2001 continue;
2002 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
2003 (void *)adev, state);
2004 if (r)
2005 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
2006 adev->ip_blocks[i].version->funcs->name, r);
2007 }
2008 return r;
2009}
2010
2011/**
2012 * amdgpu_device_ip_get_clockgating_state - get the CG state
2013 *
2014 * @adev: amdgpu_device pointer
2015 * @flags: clockgating feature flags
2016 *
2017 * Walks the list of IPs on the device and updates the clockgating
2018 * flags for each IP.
2019 * Updates @flags with the feature flags for each hardware IP where
2020 * clockgating is enabled.
2021 */
2022void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
2023 u64 *flags)
2024{
2025 int i;
2026
2027 for (i = 0; i < adev->num_ip_blocks; i++) {
2028 if (!adev->ip_blocks[i].status.valid)
2029 continue;
2030 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
2031 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
2032 }
2033}
2034
2035/**
2036 * amdgpu_device_ip_wait_for_idle - wait for idle
2037 *
2038 * @adev: amdgpu_device pointer
2039 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2040 *
2041 * Waits for the request hardware IP to be idle.
2042 * Returns 0 for success or a negative error code on failure.
2043 */
2044int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
2045 enum amd_ip_block_type block_type)
2046{
2047 int i, r;
2048
2049 for (i = 0; i < adev->num_ip_blocks; i++) {
2050 if (!adev->ip_blocks[i].status.valid)
2051 continue;
2052 if (adev->ip_blocks[i].version->type == block_type) {
2053 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
2054 if (r)
2055 return r;
2056 break;
2057 }
2058 }
2059 return 0;
2060
2061}
2062
2063/**
2064 * amdgpu_device_ip_is_idle - is the hardware IP idle
2065 *
2066 * @adev: amdgpu_device pointer
2067 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2068 *
2069 * Check if the hardware IP is idle or not.
2070 * Returns true if it the IP is idle, false if not.
2071 */
2072bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
2073 enum amd_ip_block_type block_type)
2074{
2075 int i;
2076
2077 for (i = 0; i < adev->num_ip_blocks; i++) {
2078 if (!adev->ip_blocks[i].status.valid)
2079 continue;
2080 if (adev->ip_blocks[i].version->type == block_type)
2081 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
2082 }
2083 return true;
2084
2085}
2086
2087/**
2088 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2089 *
2090 * @adev: amdgpu_device pointer
2091 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2092 *
2093 * Returns a pointer to the hardware IP block structure
2094 * if it exists for the asic, otherwise NULL.
2095 */
2096struct amdgpu_ip_block *
2097amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2098 enum amd_ip_block_type type)
2099{
2100 int i;
2101
2102 for (i = 0; i < adev->num_ip_blocks; i++)
2103 if (adev->ip_blocks[i].version->type == type)
2104 return &adev->ip_blocks[i];
2105
2106 return NULL;
2107}
2108
2109/**
2110 * amdgpu_device_ip_block_version_cmp
2111 *
2112 * @adev: amdgpu_device pointer
2113 * @type: enum amd_ip_block_type
2114 * @major: major version
2115 * @minor: minor version
2116 *
2117 * return 0 if equal or greater
2118 * return 1 if smaller or the ip_block doesn't exist
2119 */
2120int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2121 enum amd_ip_block_type type,
2122 u32 major, u32 minor)
2123{
2124 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2125
2126 if (ip_block && ((ip_block->version->major > major) ||
2127 ((ip_block->version->major == major) &&
2128 (ip_block->version->minor >= minor))))
2129 return 0;
2130
2131 return 1;
2132}
2133
2134/**
2135 * amdgpu_device_ip_block_add
2136 *
2137 * @adev: amdgpu_device pointer
2138 * @ip_block_version: pointer to the IP to add
2139 *
2140 * Adds the IP block driver information to the collection of IPs
2141 * on the asic.
2142 */
2143int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2144 const struct amdgpu_ip_block_version *ip_block_version)
2145{
2146 if (!ip_block_version)
2147 return -EINVAL;
2148
2149 switch (ip_block_version->type) {
2150 case AMD_IP_BLOCK_TYPE_VCN:
2151 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2152 return 0;
2153 break;
2154 case AMD_IP_BLOCK_TYPE_JPEG:
2155 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2156 return 0;
2157 break;
2158 default:
2159 break;
2160 }
2161
2162 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2163 ip_block_version->funcs->name);
2164
2165 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2166
2167 return 0;
2168}
2169
2170/**
2171 * amdgpu_device_enable_virtual_display - enable virtual display feature
2172 *
2173 * @adev: amdgpu_device pointer
2174 *
2175 * Enabled the virtual display feature if the user has enabled it via
2176 * the module parameter virtual_display. This feature provides a virtual
2177 * display hardware on headless boards or in virtualized environments.
2178 * This function parses and validates the configuration string specified by
2179 * the user and configues the virtual display configuration (number of
2180 * virtual connectors, crtcs, etc.) specified.
2181 */
2182static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2183{
2184 adev->enable_virtual_display = false;
2185
2186 if (amdgpu_virtual_display) {
2187 const char *pci_address_name = pci_name(adev->pdev);
2188 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2189
2190 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2191 pciaddstr_tmp = pciaddstr;
2192 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2193 pciaddname = strsep(&pciaddname_tmp, ",");
2194 if (!strcmp("all", pciaddname)
2195 || !strcmp(pci_address_name, pciaddname)) {
2196 long num_crtc;
2197 int res = -1;
2198
2199 adev->enable_virtual_display = true;
2200
2201 if (pciaddname_tmp)
2202 res = kstrtol(pciaddname_tmp, 10,
2203 &num_crtc);
2204
2205 if (!res) {
2206 if (num_crtc < 1)
2207 num_crtc = 1;
2208 if (num_crtc > 6)
2209 num_crtc = 6;
2210 adev->mode_info.num_crtc = num_crtc;
2211 } else {
2212 adev->mode_info.num_crtc = 1;
2213 }
2214 break;
2215 }
2216 }
2217
2218 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2219 amdgpu_virtual_display, pci_address_name,
2220 adev->enable_virtual_display, adev->mode_info.num_crtc);
2221
2222 kfree(pciaddstr);
2223 }
2224}
2225
2226void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2227{
2228 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2229 adev->mode_info.num_crtc = 1;
2230 adev->enable_virtual_display = true;
2231 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2232 adev->enable_virtual_display, adev->mode_info.num_crtc);
2233 }
2234}
2235
2236/**
2237 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2238 *
2239 * @adev: amdgpu_device pointer
2240 *
2241 * Parses the asic configuration parameters specified in the gpu info
2242 * firmware and makes them availale to the driver for use in configuring
2243 * the asic.
2244 * Returns 0 on success, -EINVAL on failure.
2245 */
2246static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2247{
2248 const char *chip_name;
2249 char fw_name[40];
2250 int err;
2251 const struct gpu_info_firmware_header_v1_0 *hdr;
2252
2253 adev->firmware.gpu_info_fw = NULL;
2254
2255 if (adev->mman.discovery_bin)
2256 return 0;
2257
2258 switch (adev->asic_type) {
2259 default:
2260 return 0;
2261 case CHIP_VEGA10:
2262 chip_name = "vega10";
2263 break;
2264 case CHIP_VEGA12:
2265 chip_name = "vega12";
2266 break;
2267 case CHIP_RAVEN:
2268 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2269 chip_name = "raven2";
2270 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2271 chip_name = "picasso";
2272 else
2273 chip_name = "raven";
2274 break;
2275 case CHIP_ARCTURUS:
2276 chip_name = "arcturus";
2277 break;
2278 case CHIP_NAVI12:
2279 chip_name = "navi12";
2280 break;
2281 }
2282
2283 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2284 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2285 if (err) {
2286 dev_err(adev->dev,
2287 "Failed to get gpu_info firmware \"%s\"\n",
2288 fw_name);
2289 goto out;
2290 }
2291
2292 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2293 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2294
2295 switch (hdr->version_major) {
2296 case 1:
2297 {
2298 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2299 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2300 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2301
2302 /*
2303 * Should be droped when DAL no longer needs it.
2304 */
2305 if (adev->asic_type == CHIP_NAVI12)
2306 goto parse_soc_bounding_box;
2307
2308 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2309 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2310 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2311 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2312 adev->gfx.config.max_texture_channel_caches =
2313 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2314 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2315 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2316 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2317 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2318 adev->gfx.config.double_offchip_lds_buf =
2319 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2320 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2321 adev->gfx.cu_info.max_waves_per_simd =
2322 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2323 adev->gfx.cu_info.max_scratch_slots_per_cu =
2324 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2325 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2326 if (hdr->version_minor >= 1) {
2327 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2328 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2329 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2330 adev->gfx.config.num_sc_per_sh =
2331 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2332 adev->gfx.config.num_packer_per_sc =
2333 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2334 }
2335
2336parse_soc_bounding_box:
2337 /*
2338 * soc bounding box info is not integrated in disocovery table,
2339 * we always need to parse it from gpu info firmware if needed.
2340 */
2341 if (hdr->version_minor == 2) {
2342 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2343 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2344 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2345 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2346 }
2347 break;
2348 }
2349 default:
2350 dev_err(adev->dev,
2351 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2352 err = -EINVAL;
2353 goto out;
2354 }
2355out:
2356 return err;
2357}
2358
2359/**
2360 * amdgpu_device_ip_early_init - run early init for hardware IPs
2361 *
2362 * @adev: amdgpu_device pointer
2363 *
2364 * Early initialization pass for hardware IPs. The hardware IPs that make
2365 * up each asic are discovered each IP's early_init callback is run. This
2366 * is the first stage in initializing the asic.
2367 * Returns 0 on success, negative error code on failure.
2368 */
2369static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2370{
2371 struct pci_dev *parent;
2372 int i, r;
2373 bool total;
2374
2375 amdgpu_device_enable_virtual_display(adev);
2376
2377 if (amdgpu_sriov_vf(adev)) {
2378 r = amdgpu_virt_request_full_gpu(adev, true);
2379 if (r)
2380 return r;
2381 }
2382
2383 switch (adev->asic_type) {
2384#ifdef CONFIG_DRM_AMDGPU_SI
2385 case CHIP_VERDE:
2386 case CHIP_TAHITI:
2387 case CHIP_PITCAIRN:
2388 case CHIP_OLAND:
2389 case CHIP_HAINAN:
2390 adev->family = AMDGPU_FAMILY_SI;
2391 r = si_set_ip_blocks(adev);
2392 if (r)
2393 return r;
2394 break;
2395#endif
2396#ifdef CONFIG_DRM_AMDGPU_CIK
2397 case CHIP_BONAIRE:
2398 case CHIP_HAWAII:
2399 case CHIP_KAVERI:
2400 case CHIP_KABINI:
2401 case CHIP_MULLINS:
2402 if (adev->flags & AMD_IS_APU)
2403 adev->family = AMDGPU_FAMILY_KV;
2404 else
2405 adev->family = AMDGPU_FAMILY_CI;
2406
2407 r = cik_set_ip_blocks(adev);
2408 if (r)
2409 return r;
2410 break;
2411#endif
2412 case CHIP_TOPAZ:
2413 case CHIP_TONGA:
2414 case CHIP_FIJI:
2415 case CHIP_POLARIS10:
2416 case CHIP_POLARIS11:
2417 case CHIP_POLARIS12:
2418 case CHIP_VEGAM:
2419 case CHIP_CARRIZO:
2420 case CHIP_STONEY:
2421 if (adev->flags & AMD_IS_APU)
2422 adev->family = AMDGPU_FAMILY_CZ;
2423 else
2424 adev->family = AMDGPU_FAMILY_VI;
2425
2426 r = vi_set_ip_blocks(adev);
2427 if (r)
2428 return r;
2429 break;
2430 default:
2431 r = amdgpu_discovery_set_ip_blocks(adev);
2432 if (r)
2433 return r;
2434 break;
2435 }
2436
2437 if (amdgpu_has_atpx() &&
2438 (amdgpu_is_atpx_hybrid() ||
2439 amdgpu_has_atpx_dgpu_power_cntl()) &&
2440 ((adev->flags & AMD_IS_APU) == 0) &&
2441 !dev_is_removable(&adev->pdev->dev))
2442 adev->flags |= AMD_IS_PX;
2443
2444 if (!(adev->flags & AMD_IS_APU)) {
2445 parent = pcie_find_root_port(adev->pdev);
2446 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2447 }
2448
2449
2450 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2451 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2452 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2453 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2454 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2455 if (!amdgpu_device_pcie_dynamic_switching_supported(adev))
2456 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2457
2458 total = true;
2459 for (i = 0; i < adev->num_ip_blocks; i++) {
2460 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2461 DRM_WARN("disabled ip block: %d <%s>\n",
2462 i, adev->ip_blocks[i].version->funcs->name);
2463 adev->ip_blocks[i].status.valid = false;
2464 } else {
2465 if (adev->ip_blocks[i].version->funcs->early_init) {
2466 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2467 if (r == -ENOENT) {
2468 adev->ip_blocks[i].status.valid = false;
2469 } else if (r) {
2470 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2471 adev->ip_blocks[i].version->funcs->name, r);
2472 total = false;
2473 } else {
2474 adev->ip_blocks[i].status.valid = true;
2475 }
2476 } else {
2477 adev->ip_blocks[i].status.valid = true;
2478 }
2479 }
2480 /* get the vbios after the asic_funcs are set up */
2481 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2482 r = amdgpu_device_parse_gpu_info_fw(adev);
2483 if (r)
2484 return r;
2485
2486 /* Read BIOS */
2487 if (amdgpu_device_read_bios(adev)) {
2488 if (!amdgpu_get_bios(adev))
2489 return -EINVAL;
2490
2491 r = amdgpu_atombios_init(adev);
2492 if (r) {
2493 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2494 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2495 return r;
2496 }
2497 }
2498
2499 /*get pf2vf msg info at it's earliest time*/
2500 if (amdgpu_sriov_vf(adev))
2501 amdgpu_virt_init_data_exchange(adev);
2502
2503 }
2504 }
2505 if (!total)
2506 return -ENODEV;
2507
2508 amdgpu_amdkfd_device_probe(adev);
2509 adev->cg_flags &= amdgpu_cg_mask;
2510 adev->pg_flags &= amdgpu_pg_mask;
2511
2512 return 0;
2513}
2514
2515static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2516{
2517 int i, r;
2518
2519 for (i = 0; i < adev->num_ip_blocks; i++) {
2520 if (!adev->ip_blocks[i].status.sw)
2521 continue;
2522 if (adev->ip_blocks[i].status.hw)
2523 continue;
2524 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2525 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2526 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2527 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2528 if (r) {
2529 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2530 adev->ip_blocks[i].version->funcs->name, r);
2531 return r;
2532 }
2533 adev->ip_blocks[i].status.hw = true;
2534 }
2535 }
2536
2537 return 0;
2538}
2539
2540static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2541{
2542 int i, r;
2543
2544 for (i = 0; i < adev->num_ip_blocks; i++) {
2545 if (!adev->ip_blocks[i].status.sw)
2546 continue;
2547 if (adev->ip_blocks[i].status.hw)
2548 continue;
2549 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2550 if (r) {
2551 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2552 adev->ip_blocks[i].version->funcs->name, r);
2553 return r;
2554 }
2555 adev->ip_blocks[i].status.hw = true;
2556 }
2557
2558 return 0;
2559}
2560
2561static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2562{
2563 int r = 0;
2564 int i;
2565 uint32_t smu_version;
2566
2567 if (adev->asic_type >= CHIP_VEGA10) {
2568 for (i = 0; i < adev->num_ip_blocks; i++) {
2569 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2570 continue;
2571
2572 if (!adev->ip_blocks[i].status.sw)
2573 continue;
2574
2575 /* no need to do the fw loading again if already done*/
2576 if (adev->ip_blocks[i].status.hw == true)
2577 break;
2578
2579 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2580 r = adev->ip_blocks[i].version->funcs->resume(adev);
2581 if (r) {
2582 DRM_ERROR("resume of IP block <%s> failed %d\n",
2583 adev->ip_blocks[i].version->funcs->name, r);
2584 return r;
2585 }
2586 } else {
2587 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2588 if (r) {
2589 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2590 adev->ip_blocks[i].version->funcs->name, r);
2591 return r;
2592 }
2593 }
2594
2595 adev->ip_blocks[i].status.hw = true;
2596 break;
2597 }
2598 }
2599
2600 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2601 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2602
2603 return r;
2604}
2605
2606static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2607{
2608 long timeout;
2609 int r, i;
2610
2611 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2612 struct amdgpu_ring *ring = adev->rings[i];
2613
2614 /* No need to setup the GPU scheduler for rings that don't need it */
2615 if (!ring || ring->no_scheduler)
2616 continue;
2617
2618 switch (ring->funcs->type) {
2619 case AMDGPU_RING_TYPE_GFX:
2620 timeout = adev->gfx_timeout;
2621 break;
2622 case AMDGPU_RING_TYPE_COMPUTE:
2623 timeout = adev->compute_timeout;
2624 break;
2625 case AMDGPU_RING_TYPE_SDMA:
2626 timeout = adev->sdma_timeout;
2627 break;
2628 default:
2629 timeout = adev->video_timeout;
2630 break;
2631 }
2632
2633 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL,
2634 DRM_SCHED_PRIORITY_COUNT,
2635 ring->num_hw_submission, 0,
2636 timeout, adev->reset_domain->wq,
2637 ring->sched_score, ring->name,
2638 adev->dev);
2639 if (r) {
2640 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2641 ring->name);
2642 return r;
2643 }
2644 r = amdgpu_uvd_entity_init(adev, ring);
2645 if (r) {
2646 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2647 ring->name);
2648 return r;
2649 }
2650 r = amdgpu_vce_entity_init(adev, ring);
2651 if (r) {
2652 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2653 ring->name);
2654 return r;
2655 }
2656 }
2657
2658 amdgpu_xcp_update_partition_sched_list(adev);
2659
2660 return 0;
2661}
2662
2663
2664/**
2665 * amdgpu_device_ip_init - run init for hardware IPs
2666 *
2667 * @adev: amdgpu_device pointer
2668 *
2669 * Main initialization pass for hardware IPs. The list of all the hardware
2670 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2671 * are run. sw_init initializes the software state associated with each IP
2672 * and hw_init initializes the hardware associated with each IP.
2673 * Returns 0 on success, negative error code on failure.
2674 */
2675static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2676{
2677 int i, r;
2678
2679 r = amdgpu_ras_init(adev);
2680 if (r)
2681 return r;
2682
2683 for (i = 0; i < adev->num_ip_blocks; i++) {
2684 if (!adev->ip_blocks[i].status.valid)
2685 continue;
2686 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2687 if (r) {
2688 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2689 adev->ip_blocks[i].version->funcs->name, r);
2690 goto init_failed;
2691 }
2692 adev->ip_blocks[i].status.sw = true;
2693
2694 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2695 /* need to do common hw init early so everything is set up for gmc */
2696 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2697 if (r) {
2698 DRM_ERROR("hw_init %d failed %d\n", i, r);
2699 goto init_failed;
2700 }
2701 adev->ip_blocks[i].status.hw = true;
2702 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2703 /* need to do gmc hw init early so we can allocate gpu mem */
2704 /* Try to reserve bad pages early */
2705 if (amdgpu_sriov_vf(adev))
2706 amdgpu_virt_exchange_data(adev);
2707
2708 r = amdgpu_device_mem_scratch_init(adev);
2709 if (r) {
2710 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2711 goto init_failed;
2712 }
2713 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2714 if (r) {
2715 DRM_ERROR("hw_init %d failed %d\n", i, r);
2716 goto init_failed;
2717 }
2718 r = amdgpu_device_wb_init(adev);
2719 if (r) {
2720 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2721 goto init_failed;
2722 }
2723 adev->ip_blocks[i].status.hw = true;
2724
2725 /* right after GMC hw init, we create CSA */
2726 if (adev->gfx.mcbp) {
2727 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2728 AMDGPU_GEM_DOMAIN_VRAM |
2729 AMDGPU_GEM_DOMAIN_GTT,
2730 AMDGPU_CSA_SIZE);
2731 if (r) {
2732 DRM_ERROR("allocate CSA failed %d\n", r);
2733 goto init_failed;
2734 }
2735 }
2736
2737 r = amdgpu_seq64_init(adev);
2738 if (r) {
2739 DRM_ERROR("allocate seq64 failed %d\n", r);
2740 goto init_failed;
2741 }
2742 }
2743 }
2744
2745 if (amdgpu_sriov_vf(adev))
2746 amdgpu_virt_init_data_exchange(adev);
2747
2748 r = amdgpu_ib_pool_init(adev);
2749 if (r) {
2750 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2751 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2752 goto init_failed;
2753 }
2754
2755 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2756 if (r)
2757 goto init_failed;
2758
2759 r = amdgpu_device_ip_hw_init_phase1(adev);
2760 if (r)
2761 goto init_failed;
2762
2763 r = amdgpu_device_fw_loading(adev);
2764 if (r)
2765 goto init_failed;
2766
2767 r = amdgpu_device_ip_hw_init_phase2(adev);
2768 if (r)
2769 goto init_failed;
2770
2771 /*
2772 * retired pages will be loaded from eeprom and reserved here,
2773 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2774 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2775 * for I2C communication which only true at this point.
2776 *
2777 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2778 * failure from bad gpu situation and stop amdgpu init process
2779 * accordingly. For other failed cases, it will still release all
2780 * the resource and print error message, rather than returning one
2781 * negative value to upper level.
2782 *
2783 * Note: theoretically, this should be called before all vram allocations
2784 * to protect retired page from abusing
2785 */
2786 r = amdgpu_ras_recovery_init(adev);
2787 if (r)
2788 goto init_failed;
2789
2790 /**
2791 * In case of XGMI grab extra reference for reset domain for this device
2792 */
2793 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2794 if (amdgpu_xgmi_add_device(adev) == 0) {
2795 if (!amdgpu_sriov_vf(adev)) {
2796 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2797
2798 if (WARN_ON(!hive)) {
2799 r = -ENOENT;
2800 goto init_failed;
2801 }
2802
2803 if (!hive->reset_domain ||
2804 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2805 r = -ENOENT;
2806 amdgpu_put_xgmi_hive(hive);
2807 goto init_failed;
2808 }
2809
2810 /* Drop the early temporary reset domain we created for device */
2811 amdgpu_reset_put_reset_domain(adev->reset_domain);
2812 adev->reset_domain = hive->reset_domain;
2813 amdgpu_put_xgmi_hive(hive);
2814 }
2815 }
2816 }
2817
2818 r = amdgpu_device_init_schedulers(adev);
2819 if (r)
2820 goto init_failed;
2821
2822 if (adev->mman.buffer_funcs_ring->sched.ready)
2823 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2824
2825 /* Don't init kfd if whole hive need to be reset during init */
2826 if (!adev->gmc.xgmi.pending_reset) {
2827 kgd2kfd_init_zone_device(adev);
2828 amdgpu_amdkfd_device_init(adev);
2829 }
2830
2831 amdgpu_fru_get_product_info(adev);
2832
2833init_failed:
2834
2835 return r;
2836}
2837
2838/**
2839 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2840 *
2841 * @adev: amdgpu_device pointer
2842 *
2843 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2844 * this function before a GPU reset. If the value is retained after a
2845 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2846 */
2847static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2848{
2849 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2850}
2851
2852/**
2853 * amdgpu_device_check_vram_lost - check if vram is valid
2854 *
2855 * @adev: amdgpu_device pointer
2856 *
2857 * Checks the reset magic value written to the gart pointer in VRAM.
2858 * The driver calls this after a GPU reset to see if the contents of
2859 * VRAM is lost or now.
2860 * returns true if vram is lost, false if not.
2861 */
2862static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2863{
2864 if (memcmp(adev->gart.ptr, adev->reset_magic,
2865 AMDGPU_RESET_MAGIC_NUM))
2866 return true;
2867
2868 if (!amdgpu_in_reset(adev))
2869 return false;
2870
2871 /*
2872 * For all ASICs with baco/mode1 reset, the VRAM is
2873 * always assumed to be lost.
2874 */
2875 switch (amdgpu_asic_reset_method(adev)) {
2876 case AMD_RESET_METHOD_BACO:
2877 case AMD_RESET_METHOD_MODE1:
2878 return true;
2879 default:
2880 return false;
2881 }
2882}
2883
2884/**
2885 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2886 *
2887 * @adev: amdgpu_device pointer
2888 * @state: clockgating state (gate or ungate)
2889 *
2890 * The list of all the hardware IPs that make up the asic is walked and the
2891 * set_clockgating_state callbacks are run.
2892 * Late initialization pass enabling clockgating for hardware IPs.
2893 * Fini or suspend, pass disabling clockgating for hardware IPs.
2894 * Returns 0 on success, negative error code on failure.
2895 */
2896
2897int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2898 enum amd_clockgating_state state)
2899{
2900 int i, j, r;
2901
2902 if (amdgpu_emu_mode == 1)
2903 return 0;
2904
2905 for (j = 0; j < adev->num_ip_blocks; j++) {
2906 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2907 if (!adev->ip_blocks[i].status.late_initialized)
2908 continue;
2909 /* skip CG for GFX, SDMA on S0ix */
2910 if (adev->in_s0ix &&
2911 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2912 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2913 continue;
2914 /* skip CG for VCE/UVD, it's handled specially */
2915 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2916 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2917 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2918 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2919 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2920 /* enable clockgating to save power */
2921 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2922 state);
2923 if (r) {
2924 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2925 adev->ip_blocks[i].version->funcs->name, r);
2926 return r;
2927 }
2928 }
2929 }
2930
2931 return 0;
2932}
2933
2934int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2935 enum amd_powergating_state state)
2936{
2937 int i, j, r;
2938
2939 if (amdgpu_emu_mode == 1)
2940 return 0;
2941
2942 for (j = 0; j < adev->num_ip_blocks; j++) {
2943 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2944 if (!adev->ip_blocks[i].status.late_initialized)
2945 continue;
2946 /* skip PG for GFX, SDMA on S0ix */
2947 if (adev->in_s0ix &&
2948 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2949 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2950 continue;
2951 /* skip CG for VCE/UVD, it's handled specially */
2952 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2953 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2954 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2955 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2956 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2957 /* enable powergating to save power */
2958 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2959 state);
2960 if (r) {
2961 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2962 adev->ip_blocks[i].version->funcs->name, r);
2963 return r;
2964 }
2965 }
2966 }
2967 return 0;
2968}
2969
2970static int amdgpu_device_enable_mgpu_fan_boost(void)
2971{
2972 struct amdgpu_gpu_instance *gpu_ins;
2973 struct amdgpu_device *adev;
2974 int i, ret = 0;
2975
2976 mutex_lock(&mgpu_info.mutex);
2977
2978 /*
2979 * MGPU fan boost feature should be enabled
2980 * only when there are two or more dGPUs in
2981 * the system
2982 */
2983 if (mgpu_info.num_dgpu < 2)
2984 goto out;
2985
2986 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2987 gpu_ins = &(mgpu_info.gpu_ins[i]);
2988 adev = gpu_ins->adev;
2989 if (!(adev->flags & AMD_IS_APU) &&
2990 !gpu_ins->mgpu_fan_enabled) {
2991 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2992 if (ret)
2993 break;
2994
2995 gpu_ins->mgpu_fan_enabled = 1;
2996 }
2997 }
2998
2999out:
3000 mutex_unlock(&mgpu_info.mutex);
3001
3002 return ret;
3003}
3004
3005/**
3006 * amdgpu_device_ip_late_init - run late init for hardware IPs
3007 *
3008 * @adev: amdgpu_device pointer
3009 *
3010 * Late initialization pass for hardware IPs. The list of all the hardware
3011 * IPs that make up the asic is walked and the late_init callbacks are run.
3012 * late_init covers any special initialization that an IP requires
3013 * after all of the have been initialized or something that needs to happen
3014 * late in the init process.
3015 * Returns 0 on success, negative error code on failure.
3016 */
3017static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
3018{
3019 struct amdgpu_gpu_instance *gpu_instance;
3020 int i = 0, r;
3021
3022 for (i = 0; i < adev->num_ip_blocks; i++) {
3023 if (!adev->ip_blocks[i].status.hw)
3024 continue;
3025 if (adev->ip_blocks[i].version->funcs->late_init) {
3026 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
3027 if (r) {
3028 DRM_ERROR("late_init of IP block <%s> failed %d\n",
3029 adev->ip_blocks[i].version->funcs->name, r);
3030 return r;
3031 }
3032 }
3033 adev->ip_blocks[i].status.late_initialized = true;
3034 }
3035
3036 r = amdgpu_ras_late_init(adev);
3037 if (r) {
3038 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
3039 return r;
3040 }
3041
3042 amdgpu_ras_set_error_query_ready(adev, true);
3043
3044 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
3045 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
3046
3047 amdgpu_device_fill_reset_magic(adev);
3048
3049 r = amdgpu_device_enable_mgpu_fan_boost();
3050 if (r)
3051 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
3052
3053 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
3054 if (amdgpu_passthrough(adev) &&
3055 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
3056 adev->asic_type == CHIP_ALDEBARAN))
3057 amdgpu_dpm_handle_passthrough_sbr(adev, true);
3058
3059 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3060 mutex_lock(&mgpu_info.mutex);
3061
3062 /*
3063 * Reset device p-state to low as this was booted with high.
3064 *
3065 * This should be performed only after all devices from the same
3066 * hive get initialized.
3067 *
3068 * However, it's unknown how many device in the hive in advance.
3069 * As this is counted one by one during devices initializations.
3070 *
3071 * So, we wait for all XGMI interlinked devices initialized.
3072 * This may bring some delays as those devices may come from
3073 * different hives. But that should be OK.
3074 */
3075 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3076 for (i = 0; i < mgpu_info.num_gpu; i++) {
3077 gpu_instance = &(mgpu_info.gpu_ins[i]);
3078 if (gpu_instance->adev->flags & AMD_IS_APU)
3079 continue;
3080
3081 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3082 AMDGPU_XGMI_PSTATE_MIN);
3083 if (r) {
3084 DRM_ERROR("pstate setting failed (%d).\n", r);
3085 break;
3086 }
3087 }
3088 }
3089
3090 mutex_unlock(&mgpu_info.mutex);
3091 }
3092
3093 return 0;
3094}
3095
3096/**
3097 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3098 *
3099 * @adev: amdgpu_device pointer
3100 *
3101 * For ASICs need to disable SMC first
3102 */
3103static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3104{
3105 int i, r;
3106
3107 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3108 return;
3109
3110 for (i = 0; i < adev->num_ip_blocks; i++) {
3111 if (!adev->ip_blocks[i].status.hw)
3112 continue;
3113 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3114 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3115 /* XXX handle errors */
3116 if (r) {
3117 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3118 adev->ip_blocks[i].version->funcs->name, r);
3119 }
3120 adev->ip_blocks[i].status.hw = false;
3121 break;
3122 }
3123 }
3124}
3125
3126static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3127{
3128 int i, r;
3129
3130 for (i = 0; i < adev->num_ip_blocks; i++) {
3131 if (!adev->ip_blocks[i].version->funcs->early_fini)
3132 continue;
3133
3134 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
3135 if (r) {
3136 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3137 adev->ip_blocks[i].version->funcs->name, r);
3138 }
3139 }
3140
3141 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3142 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3143
3144 amdgpu_amdkfd_suspend(adev, false);
3145
3146 /* Workaroud for ASICs need to disable SMC first */
3147 amdgpu_device_smu_fini_early(adev);
3148
3149 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3150 if (!adev->ip_blocks[i].status.hw)
3151 continue;
3152
3153 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3154 /* XXX handle errors */
3155 if (r) {
3156 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3157 adev->ip_blocks[i].version->funcs->name, r);
3158 }
3159
3160 adev->ip_blocks[i].status.hw = false;
3161 }
3162
3163 if (amdgpu_sriov_vf(adev)) {
3164 if (amdgpu_virt_release_full_gpu(adev, false))
3165 DRM_ERROR("failed to release exclusive mode on fini\n");
3166 }
3167
3168 return 0;
3169}
3170
3171/**
3172 * amdgpu_device_ip_fini - run fini for hardware IPs
3173 *
3174 * @adev: amdgpu_device pointer
3175 *
3176 * Main teardown pass for hardware IPs. The list of all the hardware
3177 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3178 * are run. hw_fini tears down the hardware associated with each IP
3179 * and sw_fini tears down any software state associated with each IP.
3180 * Returns 0 on success, negative error code on failure.
3181 */
3182static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3183{
3184 int i, r;
3185
3186 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3187 amdgpu_virt_release_ras_err_handler_data(adev);
3188
3189 if (adev->gmc.xgmi.num_physical_nodes > 1)
3190 amdgpu_xgmi_remove_device(adev);
3191
3192 amdgpu_amdkfd_device_fini_sw(adev);
3193
3194 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3195 if (!adev->ip_blocks[i].status.sw)
3196 continue;
3197
3198 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3199 amdgpu_ucode_free_bo(adev);
3200 amdgpu_free_static_csa(&adev->virt.csa_obj);
3201 amdgpu_device_wb_fini(adev);
3202 amdgpu_device_mem_scratch_fini(adev);
3203 amdgpu_ib_pool_fini(adev);
3204 amdgpu_seq64_fini(adev);
3205 }
3206
3207 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
3208 /* XXX handle errors */
3209 if (r) {
3210 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3211 adev->ip_blocks[i].version->funcs->name, r);
3212 }
3213 adev->ip_blocks[i].status.sw = false;
3214 adev->ip_blocks[i].status.valid = false;
3215 }
3216
3217 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3218 if (!adev->ip_blocks[i].status.late_initialized)
3219 continue;
3220 if (adev->ip_blocks[i].version->funcs->late_fini)
3221 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
3222 adev->ip_blocks[i].status.late_initialized = false;
3223 }
3224
3225 amdgpu_ras_fini(adev);
3226
3227 return 0;
3228}
3229
3230/**
3231 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3232 *
3233 * @work: work_struct.
3234 */
3235static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3236{
3237 struct amdgpu_device *adev =
3238 container_of(work, struct amdgpu_device, delayed_init_work.work);
3239 int r;
3240
3241 r = amdgpu_ib_ring_tests(adev);
3242 if (r)
3243 DRM_ERROR("ib ring test failed (%d).\n", r);
3244}
3245
3246static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3247{
3248 struct amdgpu_device *adev =
3249 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3250
3251 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3252 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3253
3254 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3255 adev->gfx.gfx_off_state = true;
3256}
3257
3258/**
3259 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3260 *
3261 * @adev: amdgpu_device pointer
3262 *
3263 * Main suspend function for hardware IPs. The list of all the hardware
3264 * IPs that make up the asic is walked, clockgating is disabled and the
3265 * suspend callbacks are run. suspend puts the hardware and software state
3266 * in each IP into a state suitable for suspend.
3267 * Returns 0 on success, negative error code on failure.
3268 */
3269static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3270{
3271 int i, r;
3272
3273 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3274 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3275
3276 /*
3277 * Per PMFW team's suggestion, driver needs to handle gfxoff
3278 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3279 * scenario. Add the missing df cstate disablement here.
3280 */
3281 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3282 dev_warn(adev->dev, "Failed to disallow df cstate");
3283
3284 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3285 if (!adev->ip_blocks[i].status.valid)
3286 continue;
3287
3288 /* displays are handled separately */
3289 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3290 continue;
3291
3292 /* XXX handle errors */
3293 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3294 /* XXX handle errors */
3295 if (r) {
3296 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3297 adev->ip_blocks[i].version->funcs->name, r);
3298 return r;
3299 }
3300
3301 adev->ip_blocks[i].status.hw = false;
3302 }
3303
3304 return 0;
3305}
3306
3307/**
3308 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3309 *
3310 * @adev: amdgpu_device pointer
3311 *
3312 * Main suspend function for hardware IPs. The list of all the hardware
3313 * IPs that make up the asic is walked, clockgating is disabled and the
3314 * suspend callbacks are run. suspend puts the hardware and software state
3315 * in each IP into a state suitable for suspend.
3316 * Returns 0 on success, negative error code on failure.
3317 */
3318static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3319{
3320 int i, r;
3321
3322 if (adev->in_s0ix)
3323 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3324
3325 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3326 if (!adev->ip_blocks[i].status.valid)
3327 continue;
3328 /* displays are handled in phase1 */
3329 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3330 continue;
3331 /* PSP lost connection when err_event_athub occurs */
3332 if (amdgpu_ras_intr_triggered() &&
3333 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3334 adev->ip_blocks[i].status.hw = false;
3335 continue;
3336 }
3337
3338 /* skip unnecessary suspend if we do not initialize them yet */
3339 if (adev->gmc.xgmi.pending_reset &&
3340 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3341 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3342 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3343 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3344 adev->ip_blocks[i].status.hw = false;
3345 continue;
3346 }
3347
3348 /* skip suspend of gfx/mes and psp for S0ix
3349 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3350 * like at runtime. PSP is also part of the always on hardware
3351 * so no need to suspend it.
3352 */
3353 if (adev->in_s0ix &&
3354 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3355 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3356 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3357 continue;
3358
3359 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3360 if (adev->in_s0ix &&
3361 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3362 IP_VERSION(5, 0, 0)) &&
3363 (adev->ip_blocks[i].version->type ==
3364 AMD_IP_BLOCK_TYPE_SDMA))
3365 continue;
3366
3367 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3368 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3369 * from this location and RLC Autoload automatically also gets loaded
3370 * from here based on PMFW -> PSP message during re-init sequence.
3371 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3372 * the TMR and reload FWs again for IMU enabled APU ASICs.
3373 */
3374 if (amdgpu_in_reset(adev) &&
3375 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3376 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3377 continue;
3378
3379 /* XXX handle errors */
3380 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3381 /* XXX handle errors */
3382 if (r) {
3383 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3384 adev->ip_blocks[i].version->funcs->name, r);
3385 }
3386 adev->ip_blocks[i].status.hw = false;
3387 /* handle putting the SMC in the appropriate state */
3388 if (!amdgpu_sriov_vf(adev)) {
3389 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3390 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3391 if (r) {
3392 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3393 adev->mp1_state, r);
3394 return r;
3395 }
3396 }
3397 }
3398 }
3399
3400 return 0;
3401}
3402
3403/**
3404 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3405 *
3406 * @adev: amdgpu_device pointer
3407 *
3408 * Main suspend function for hardware IPs. The list of all the hardware
3409 * IPs that make up the asic is walked, clockgating is disabled and the
3410 * suspend callbacks are run. suspend puts the hardware and software state
3411 * in each IP into a state suitable for suspend.
3412 * Returns 0 on success, negative error code on failure.
3413 */
3414int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3415{
3416 int r;
3417
3418 if (amdgpu_sriov_vf(adev)) {
3419 amdgpu_virt_fini_data_exchange(adev);
3420 amdgpu_virt_request_full_gpu(adev, false);
3421 }
3422
3423 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3424
3425 r = amdgpu_device_ip_suspend_phase1(adev);
3426 if (r)
3427 return r;
3428 r = amdgpu_device_ip_suspend_phase2(adev);
3429
3430 if (amdgpu_sriov_vf(adev))
3431 amdgpu_virt_release_full_gpu(adev, false);
3432
3433 return r;
3434}
3435
3436static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3437{
3438 int i, r;
3439
3440 static enum amd_ip_block_type ip_order[] = {
3441 AMD_IP_BLOCK_TYPE_COMMON,
3442 AMD_IP_BLOCK_TYPE_GMC,
3443 AMD_IP_BLOCK_TYPE_PSP,
3444 AMD_IP_BLOCK_TYPE_IH,
3445 };
3446
3447 for (i = 0; i < adev->num_ip_blocks; i++) {
3448 int j;
3449 struct amdgpu_ip_block *block;
3450
3451 block = &adev->ip_blocks[i];
3452 block->status.hw = false;
3453
3454 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3455
3456 if (block->version->type != ip_order[j] ||
3457 !block->status.valid)
3458 continue;
3459
3460 r = block->version->funcs->hw_init(adev);
3461 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3462 if (r)
3463 return r;
3464 block->status.hw = true;
3465 }
3466 }
3467
3468 return 0;
3469}
3470
3471static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3472{
3473 int i, r;
3474
3475 static enum amd_ip_block_type ip_order[] = {
3476 AMD_IP_BLOCK_TYPE_SMC,
3477 AMD_IP_BLOCK_TYPE_DCE,
3478 AMD_IP_BLOCK_TYPE_GFX,
3479 AMD_IP_BLOCK_TYPE_SDMA,
3480 AMD_IP_BLOCK_TYPE_MES,
3481 AMD_IP_BLOCK_TYPE_UVD,
3482 AMD_IP_BLOCK_TYPE_VCE,
3483 AMD_IP_BLOCK_TYPE_VCN,
3484 AMD_IP_BLOCK_TYPE_JPEG
3485 };
3486
3487 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3488 int j;
3489 struct amdgpu_ip_block *block;
3490
3491 for (j = 0; j < adev->num_ip_blocks; j++) {
3492 block = &adev->ip_blocks[j];
3493
3494 if (block->version->type != ip_order[i] ||
3495 !block->status.valid ||
3496 block->status.hw)
3497 continue;
3498
3499 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3500 r = block->version->funcs->resume(adev);
3501 else
3502 r = block->version->funcs->hw_init(adev);
3503
3504 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3505 if (r)
3506 return r;
3507 block->status.hw = true;
3508 }
3509 }
3510
3511 return 0;
3512}
3513
3514/**
3515 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3516 *
3517 * @adev: amdgpu_device pointer
3518 *
3519 * First resume function for hardware IPs. The list of all the hardware
3520 * IPs that make up the asic is walked and the resume callbacks are run for
3521 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3522 * after a suspend and updates the software state as necessary. This
3523 * function is also used for restoring the GPU after a GPU reset.
3524 * Returns 0 on success, negative error code on failure.
3525 */
3526static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3527{
3528 int i, r;
3529
3530 for (i = 0; i < adev->num_ip_blocks; i++) {
3531 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3532 continue;
3533 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3534 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3535 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3536 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3537
3538 r = adev->ip_blocks[i].version->funcs->resume(adev);
3539 if (r) {
3540 DRM_ERROR("resume of IP block <%s> failed %d\n",
3541 adev->ip_blocks[i].version->funcs->name, r);
3542 return r;
3543 }
3544 adev->ip_blocks[i].status.hw = true;
3545 }
3546 }
3547
3548 return 0;
3549}
3550
3551/**
3552 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3553 *
3554 * @adev: amdgpu_device pointer
3555 *
3556 * First resume function for hardware IPs. The list of all the hardware
3557 * IPs that make up the asic is walked and the resume callbacks are run for
3558 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3559 * functional state after a suspend and updates the software state as
3560 * necessary. This function is also used for restoring the GPU after a GPU
3561 * reset.
3562 * Returns 0 on success, negative error code on failure.
3563 */
3564static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3565{
3566 int i, r;
3567
3568 for (i = 0; i < adev->num_ip_blocks; i++) {
3569 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3570 continue;
3571 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3572 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3573 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3574 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3575 continue;
3576 r = adev->ip_blocks[i].version->funcs->resume(adev);
3577 if (r) {
3578 DRM_ERROR("resume of IP block <%s> failed %d\n",
3579 adev->ip_blocks[i].version->funcs->name, r);
3580 return r;
3581 }
3582 adev->ip_blocks[i].status.hw = true;
3583 }
3584
3585 return 0;
3586}
3587
3588/**
3589 * amdgpu_device_ip_resume - run resume for hardware IPs
3590 *
3591 * @adev: amdgpu_device pointer
3592 *
3593 * Main resume function for hardware IPs. The hardware IPs
3594 * are split into two resume functions because they are
3595 * also used in recovering from a GPU reset and some additional
3596 * steps need to be take between them. In this case (S3/S4) they are
3597 * run sequentially.
3598 * Returns 0 on success, negative error code on failure.
3599 */
3600static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3601{
3602 int r;
3603
3604 r = amdgpu_device_ip_resume_phase1(adev);
3605 if (r)
3606 return r;
3607
3608 r = amdgpu_device_fw_loading(adev);
3609 if (r)
3610 return r;
3611
3612 r = amdgpu_device_ip_resume_phase2(adev);
3613
3614 if (adev->mman.buffer_funcs_ring->sched.ready)
3615 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3616
3617 return r;
3618}
3619
3620/**
3621 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3622 *
3623 * @adev: amdgpu_device pointer
3624 *
3625 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3626 */
3627static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3628{
3629 if (amdgpu_sriov_vf(adev)) {
3630 if (adev->is_atom_fw) {
3631 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3632 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3633 } else {
3634 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3635 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3636 }
3637
3638 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3639 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3640 }
3641}
3642
3643/**
3644 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3645 *
3646 * @asic_type: AMD asic type
3647 *
3648 * Check if there is DC (new modesetting infrastructre) support for an asic.
3649 * returns true if DC has support, false if not.
3650 */
3651bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3652{
3653 switch (asic_type) {
3654#ifdef CONFIG_DRM_AMDGPU_SI
3655 case CHIP_HAINAN:
3656#endif
3657 case CHIP_TOPAZ:
3658 /* chips with no display hardware */
3659 return false;
3660#if defined(CONFIG_DRM_AMD_DC)
3661 case CHIP_TAHITI:
3662 case CHIP_PITCAIRN:
3663 case CHIP_VERDE:
3664 case CHIP_OLAND:
3665 /*
3666 * We have systems in the wild with these ASICs that require
3667 * LVDS and VGA support which is not supported with DC.
3668 *
3669 * Fallback to the non-DC driver here by default so as not to
3670 * cause regressions.
3671 */
3672#if defined(CONFIG_DRM_AMD_DC_SI)
3673 return amdgpu_dc > 0;
3674#else
3675 return false;
3676#endif
3677 case CHIP_BONAIRE:
3678 case CHIP_KAVERI:
3679 case CHIP_KABINI:
3680 case CHIP_MULLINS:
3681 /*
3682 * We have systems in the wild with these ASICs that require
3683 * VGA support which is not supported with DC.
3684 *
3685 * Fallback to the non-DC driver here by default so as not to
3686 * cause regressions.
3687 */
3688 return amdgpu_dc > 0;
3689 default:
3690 return amdgpu_dc != 0;
3691#else
3692 default:
3693 if (amdgpu_dc > 0)
3694 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3695 return false;
3696#endif
3697 }
3698}
3699
3700/**
3701 * amdgpu_device_has_dc_support - check if dc is supported
3702 *
3703 * @adev: amdgpu_device pointer
3704 *
3705 * Returns true for supported, false for not supported
3706 */
3707bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3708{
3709 if (adev->enable_virtual_display ||
3710 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3711 return false;
3712
3713 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3714}
3715
3716static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3717{
3718 struct amdgpu_device *adev =
3719 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3720 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3721
3722 /* It's a bug to not have a hive within this function */
3723 if (WARN_ON(!hive))
3724 return;
3725
3726 /*
3727 * Use task barrier to synchronize all xgmi reset works across the
3728 * hive. task_barrier_enter and task_barrier_exit will block
3729 * until all the threads running the xgmi reset works reach
3730 * those points. task_barrier_full will do both blocks.
3731 */
3732 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3733
3734 task_barrier_enter(&hive->tb);
3735 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3736
3737 if (adev->asic_reset_res)
3738 goto fail;
3739
3740 task_barrier_exit(&hive->tb);
3741 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3742
3743 if (adev->asic_reset_res)
3744 goto fail;
3745
3746 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
3747 } else {
3748
3749 task_barrier_full(&hive->tb);
3750 adev->asic_reset_res = amdgpu_asic_reset(adev);
3751 }
3752
3753fail:
3754 if (adev->asic_reset_res)
3755 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3756 adev->asic_reset_res, adev_to_drm(adev)->unique);
3757 amdgpu_put_xgmi_hive(hive);
3758}
3759
3760static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3761{
3762 char *input = amdgpu_lockup_timeout;
3763 char *timeout_setting = NULL;
3764 int index = 0;
3765 long timeout;
3766 int ret = 0;
3767
3768 /*
3769 * By default timeout for non compute jobs is 10000
3770 * and 60000 for compute jobs.
3771 * In SR-IOV or passthrough mode, timeout for compute
3772 * jobs are 60000 by default.
3773 */
3774 adev->gfx_timeout = msecs_to_jiffies(10000);
3775 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3776 if (amdgpu_sriov_vf(adev))
3777 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3778 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3779 else
3780 adev->compute_timeout = msecs_to_jiffies(60000);
3781
3782 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3783 while ((timeout_setting = strsep(&input, ",")) &&
3784 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3785 ret = kstrtol(timeout_setting, 0, &timeout);
3786 if (ret)
3787 return ret;
3788
3789 if (timeout == 0) {
3790 index++;
3791 continue;
3792 } else if (timeout < 0) {
3793 timeout = MAX_SCHEDULE_TIMEOUT;
3794 dev_warn(adev->dev, "lockup timeout disabled");
3795 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3796 } else {
3797 timeout = msecs_to_jiffies(timeout);
3798 }
3799
3800 switch (index++) {
3801 case 0:
3802 adev->gfx_timeout = timeout;
3803 break;
3804 case 1:
3805 adev->compute_timeout = timeout;
3806 break;
3807 case 2:
3808 adev->sdma_timeout = timeout;
3809 break;
3810 case 3:
3811 adev->video_timeout = timeout;
3812 break;
3813 default:
3814 break;
3815 }
3816 }
3817 /*
3818 * There is only one value specified and
3819 * it should apply to all non-compute jobs.
3820 */
3821 if (index == 1) {
3822 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3823 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3824 adev->compute_timeout = adev->gfx_timeout;
3825 }
3826 }
3827
3828 return ret;
3829}
3830
3831/**
3832 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3833 *
3834 * @adev: amdgpu_device pointer
3835 *
3836 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3837 */
3838static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3839{
3840 struct iommu_domain *domain;
3841
3842 domain = iommu_get_domain_for_dev(adev->dev);
3843 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3844 adev->ram_is_direct_mapped = true;
3845}
3846
3847static const struct attribute *amdgpu_dev_attributes[] = {
3848 &dev_attr_pcie_replay_count.attr,
3849 NULL
3850};
3851
3852static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3853{
3854 if (amdgpu_mcbp == 1)
3855 adev->gfx.mcbp = true;
3856 else if (amdgpu_mcbp == 0)
3857 adev->gfx.mcbp = false;
3858
3859 if (amdgpu_sriov_vf(adev))
3860 adev->gfx.mcbp = true;
3861
3862 if (adev->gfx.mcbp)
3863 DRM_INFO("MCBP is enabled\n");
3864}
3865
3866/**
3867 * amdgpu_device_init - initialize the driver
3868 *
3869 * @adev: amdgpu_device pointer
3870 * @flags: driver flags
3871 *
3872 * Initializes the driver info and hw (all asics).
3873 * Returns 0 for success or an error on failure.
3874 * Called at driver startup.
3875 */
3876int amdgpu_device_init(struct amdgpu_device *adev,
3877 uint32_t flags)
3878{
3879 struct drm_device *ddev = adev_to_drm(adev);
3880 struct pci_dev *pdev = adev->pdev;
3881 int r, i;
3882 bool px = false;
3883 u32 max_MBps;
3884 int tmp;
3885
3886 adev->shutdown = false;
3887 adev->flags = flags;
3888
3889 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3890 adev->asic_type = amdgpu_force_asic_type;
3891 else
3892 adev->asic_type = flags & AMD_ASIC_MASK;
3893
3894 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3895 if (amdgpu_emu_mode == 1)
3896 adev->usec_timeout *= 10;
3897 adev->gmc.gart_size = 512 * 1024 * 1024;
3898 adev->accel_working = false;
3899 adev->num_rings = 0;
3900 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3901 adev->mman.buffer_funcs = NULL;
3902 adev->mman.buffer_funcs_ring = NULL;
3903 adev->vm_manager.vm_pte_funcs = NULL;
3904 adev->vm_manager.vm_pte_num_scheds = 0;
3905 adev->gmc.gmc_funcs = NULL;
3906 adev->harvest_ip_mask = 0x0;
3907 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3908 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3909
3910 adev->smc_rreg = &amdgpu_invalid_rreg;
3911 adev->smc_wreg = &amdgpu_invalid_wreg;
3912 adev->pcie_rreg = &amdgpu_invalid_rreg;
3913 adev->pcie_wreg = &amdgpu_invalid_wreg;
3914 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3915 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3916 adev->pciep_rreg = &amdgpu_invalid_rreg;
3917 adev->pciep_wreg = &amdgpu_invalid_wreg;
3918 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3919 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3920 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
3921 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
3922 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3923 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3924 adev->didt_rreg = &amdgpu_invalid_rreg;
3925 adev->didt_wreg = &amdgpu_invalid_wreg;
3926 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3927 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3928 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3929 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3930
3931 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3932 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3933 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3934
3935 /* mutex initialization are all done here so we
3936 * can recall function without having locking issues
3937 */
3938 mutex_init(&adev->firmware.mutex);
3939 mutex_init(&adev->pm.mutex);
3940 mutex_init(&adev->gfx.gpu_clock_mutex);
3941 mutex_init(&adev->srbm_mutex);
3942 mutex_init(&adev->gfx.pipe_reserve_mutex);
3943 mutex_init(&adev->gfx.gfx_off_mutex);
3944 mutex_init(&adev->gfx.partition_mutex);
3945 mutex_init(&adev->grbm_idx_mutex);
3946 mutex_init(&adev->mn_lock);
3947 mutex_init(&adev->virt.vf_errors.lock);
3948 hash_init(adev->mn_hash);
3949 mutex_init(&adev->psp.mutex);
3950 mutex_init(&adev->notifier_lock);
3951 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3952 mutex_init(&adev->benchmark_mutex);
3953
3954 amdgpu_device_init_apu_flags(adev);
3955
3956 r = amdgpu_device_check_arguments(adev);
3957 if (r)
3958 return r;
3959
3960 spin_lock_init(&adev->mmio_idx_lock);
3961 spin_lock_init(&adev->smc_idx_lock);
3962 spin_lock_init(&adev->pcie_idx_lock);
3963 spin_lock_init(&adev->uvd_ctx_idx_lock);
3964 spin_lock_init(&adev->didt_idx_lock);
3965 spin_lock_init(&adev->gc_cac_idx_lock);
3966 spin_lock_init(&adev->se_cac_idx_lock);
3967 spin_lock_init(&adev->audio_endpt_idx_lock);
3968 spin_lock_init(&adev->mm_stats.lock);
3969
3970 INIT_LIST_HEAD(&adev->shadow_list);
3971 mutex_init(&adev->shadow_list_lock);
3972
3973 INIT_LIST_HEAD(&adev->reset_list);
3974
3975 INIT_LIST_HEAD(&adev->ras_list);
3976
3977 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
3978
3979 INIT_DELAYED_WORK(&adev->delayed_init_work,
3980 amdgpu_device_delayed_init_work_handler);
3981 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3982 amdgpu_device_delay_enable_gfx_off);
3983
3984 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3985
3986 adev->gfx.gfx_off_req_count = 1;
3987 adev->gfx.gfx_off_residency = 0;
3988 adev->gfx.gfx_off_entrycount = 0;
3989 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3990
3991 atomic_set(&adev->throttling_logging_enabled, 1);
3992 /*
3993 * If throttling continues, logging will be performed every minute
3994 * to avoid log flooding. "-1" is subtracted since the thermal
3995 * throttling interrupt comes every second. Thus, the total logging
3996 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3997 * for throttling interrupt) = 60 seconds.
3998 */
3999 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
4000 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
4001
4002 /* Registers mapping */
4003 /* TODO: block userspace mapping of io register */
4004 if (adev->asic_type >= CHIP_BONAIRE) {
4005 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
4006 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
4007 } else {
4008 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
4009 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
4010 }
4011
4012 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
4013 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
4014
4015 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
4016 if (!adev->rmmio)
4017 return -ENOMEM;
4018
4019 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
4020 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
4021
4022 /*
4023 * Reset domain needs to be present early, before XGMI hive discovered
4024 * (if any) and intitialized to use reset sem and in_gpu reset flag
4025 * early on during init and before calling to RREG32.
4026 */
4027 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
4028 if (!adev->reset_domain)
4029 return -ENOMEM;
4030
4031 /* detect hw virtualization here */
4032 amdgpu_detect_virtualization(adev);
4033
4034 amdgpu_device_get_pcie_info(adev);
4035
4036 r = amdgpu_device_get_job_timeout_settings(adev);
4037 if (r) {
4038 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
4039 return r;
4040 }
4041
4042 /* early init functions */
4043 r = amdgpu_device_ip_early_init(adev);
4044 if (r)
4045 return r;
4046
4047 amdgpu_device_set_mcbp(adev);
4048
4049 /* Get rid of things like offb */
4050 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
4051 if (r)
4052 return r;
4053
4054 /* Enable TMZ based on IP_VERSION */
4055 amdgpu_gmc_tmz_set(adev);
4056
4057 amdgpu_gmc_noretry_set(adev);
4058 /* Need to get xgmi info early to decide the reset behavior*/
4059 if (adev->gmc.xgmi.supported) {
4060 r = adev->gfxhub.funcs->get_xgmi_info(adev);
4061 if (r)
4062 return r;
4063 }
4064
4065 /* enable PCIE atomic ops */
4066 if (amdgpu_sriov_vf(adev)) {
4067 if (adev->virt.fw_reserve.p_pf2vf)
4068 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
4069 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
4070 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4071 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4072 * internal path natively support atomics, set have_atomics_support to true.
4073 */
4074 } else if ((adev->flags & AMD_IS_APU) &&
4075 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4076 IP_VERSION(9, 0, 0))) {
4077 adev->have_atomics_support = true;
4078 } else {
4079 adev->have_atomics_support =
4080 !pci_enable_atomic_ops_to_root(adev->pdev,
4081 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4082 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4083 }
4084
4085 if (!adev->have_atomics_support)
4086 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4087
4088 /* doorbell bar mapping and doorbell index init*/
4089 amdgpu_doorbell_init(adev);
4090
4091 if (amdgpu_emu_mode == 1) {
4092 /* post the asic on emulation mode */
4093 emu_soc_asic_init(adev);
4094 goto fence_driver_init;
4095 }
4096
4097 amdgpu_reset_init(adev);
4098
4099 /* detect if we are with an SRIOV vbios */
4100 if (adev->bios)
4101 amdgpu_device_detect_sriov_bios(adev);
4102
4103 /* check if we need to reset the asic
4104 * E.g., driver was not cleanly unloaded previously, etc.
4105 */
4106 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4107 if (adev->gmc.xgmi.num_physical_nodes) {
4108 dev_info(adev->dev, "Pending hive reset.\n");
4109 adev->gmc.xgmi.pending_reset = true;
4110 /* Only need to init necessary block for SMU to handle the reset */
4111 for (i = 0; i < adev->num_ip_blocks; i++) {
4112 if (!adev->ip_blocks[i].status.valid)
4113 continue;
4114 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
4115 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
4116 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
4117 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
4118 DRM_DEBUG("IP %s disabled for hw_init.\n",
4119 adev->ip_blocks[i].version->funcs->name);
4120 adev->ip_blocks[i].status.hw = true;
4121 }
4122 }
4123 } else {
4124 tmp = amdgpu_reset_method;
4125 /* It should do a default reset when loading or reloading the driver,
4126 * regardless of the module parameter reset_method.
4127 */
4128 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4129 r = amdgpu_asic_reset(adev);
4130 amdgpu_reset_method = tmp;
4131 if (r) {
4132 dev_err(adev->dev, "asic reset on init failed\n");
4133 goto failed;
4134 }
4135 }
4136 }
4137
4138 /* Post card if necessary */
4139 if (amdgpu_device_need_post(adev)) {
4140 if (!adev->bios) {
4141 dev_err(adev->dev, "no vBIOS found\n");
4142 r = -EINVAL;
4143 goto failed;
4144 }
4145 DRM_INFO("GPU posting now...\n");
4146 r = amdgpu_device_asic_init(adev);
4147 if (r) {
4148 dev_err(adev->dev, "gpu post error!\n");
4149 goto failed;
4150 }
4151 }
4152
4153 if (adev->bios) {
4154 if (adev->is_atom_fw) {
4155 /* Initialize clocks */
4156 r = amdgpu_atomfirmware_get_clock_info(adev);
4157 if (r) {
4158 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4159 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4160 goto failed;
4161 }
4162 } else {
4163 /* Initialize clocks */
4164 r = amdgpu_atombios_get_clock_info(adev);
4165 if (r) {
4166 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4167 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4168 goto failed;
4169 }
4170 /* init i2c buses */
4171 if (!amdgpu_device_has_dc_support(adev))
4172 amdgpu_atombios_i2c_init(adev);
4173 }
4174 }
4175
4176fence_driver_init:
4177 /* Fence driver */
4178 r = amdgpu_fence_driver_sw_init(adev);
4179 if (r) {
4180 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4181 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4182 goto failed;
4183 }
4184
4185 /* init the mode config */
4186 drm_mode_config_init(adev_to_drm(adev));
4187
4188 r = amdgpu_device_ip_init(adev);
4189 if (r) {
4190 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4191 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4192 goto release_ras_con;
4193 }
4194
4195 amdgpu_fence_driver_hw_init(adev);
4196
4197 dev_info(adev->dev,
4198 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4199 adev->gfx.config.max_shader_engines,
4200 adev->gfx.config.max_sh_per_se,
4201 adev->gfx.config.max_cu_per_sh,
4202 adev->gfx.cu_info.number);
4203
4204 adev->accel_working = true;
4205
4206 amdgpu_vm_check_compute_bug(adev);
4207
4208 /* Initialize the buffer migration limit. */
4209 if (amdgpu_moverate >= 0)
4210 max_MBps = amdgpu_moverate;
4211 else
4212 max_MBps = 8; /* Allow 8 MB/s. */
4213 /* Get a log2 for easy divisions. */
4214 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4215
4216 /*
4217 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4218 * Otherwise the mgpu fan boost feature will be skipped due to the
4219 * gpu instance is counted less.
4220 */
4221 amdgpu_register_gpu_instance(adev);
4222
4223 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4224 * explicit gating rather than handling it automatically.
4225 */
4226 if (!adev->gmc.xgmi.pending_reset) {
4227 r = amdgpu_device_ip_late_init(adev);
4228 if (r) {
4229 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4230 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4231 goto release_ras_con;
4232 }
4233 /* must succeed. */
4234 amdgpu_ras_resume(adev);
4235 queue_delayed_work(system_wq, &adev->delayed_init_work,
4236 msecs_to_jiffies(AMDGPU_RESUME_MS));
4237 }
4238
4239 if (amdgpu_sriov_vf(adev)) {
4240 amdgpu_virt_release_full_gpu(adev, true);
4241 flush_delayed_work(&adev->delayed_init_work);
4242 }
4243
4244 /*
4245 * Place those sysfs registering after `late_init`. As some of those
4246 * operations performed in `late_init` might affect the sysfs
4247 * interfaces creating.
4248 */
4249 r = amdgpu_atombios_sysfs_init(adev);
4250 if (r)
4251 drm_err(&adev->ddev,
4252 "registering atombios sysfs failed (%d).\n", r);
4253
4254 r = amdgpu_pm_sysfs_init(adev);
4255 if (r)
4256 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4257
4258 r = amdgpu_ucode_sysfs_init(adev);
4259 if (r) {
4260 adev->ucode_sysfs_en = false;
4261 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4262 } else
4263 adev->ucode_sysfs_en = true;
4264
4265 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4266 if (r)
4267 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4268
4269 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4270 if (r)
4271 dev_err(adev->dev,
4272 "Could not create amdgpu board attributes\n");
4273
4274 amdgpu_fru_sysfs_init(adev);
4275 amdgpu_reg_state_sysfs_init(adev);
4276
4277 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4278 r = amdgpu_pmu_init(adev);
4279 if (r)
4280 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4281
4282 /* Have stored pci confspace at hand for restore in sudden PCI error */
4283 if (amdgpu_device_cache_pci_state(adev->pdev))
4284 pci_restore_state(pdev);
4285
4286 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4287 /* this will fail for cards that aren't VGA class devices, just
4288 * ignore it
4289 */
4290 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4291 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4292
4293 px = amdgpu_device_supports_px(ddev);
4294
4295 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4296 apple_gmux_detect(NULL, NULL)))
4297 vga_switcheroo_register_client(adev->pdev,
4298 &amdgpu_switcheroo_ops, px);
4299
4300 if (px)
4301 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4302
4303 if (adev->gmc.xgmi.pending_reset)
4304 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
4305 msecs_to_jiffies(AMDGPU_RESUME_MS));
4306
4307 amdgpu_device_check_iommu_direct_map(adev);
4308
4309 return 0;
4310
4311release_ras_con:
4312 if (amdgpu_sriov_vf(adev))
4313 amdgpu_virt_release_full_gpu(adev, true);
4314
4315 /* failed in exclusive mode due to timeout */
4316 if (amdgpu_sriov_vf(adev) &&
4317 !amdgpu_sriov_runtime(adev) &&
4318 amdgpu_virt_mmio_blocked(adev) &&
4319 !amdgpu_virt_wait_reset(adev)) {
4320 dev_err(adev->dev, "VF exclusive mode timeout\n");
4321 /* Don't send request since VF is inactive. */
4322 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4323 adev->virt.ops = NULL;
4324 r = -EAGAIN;
4325 }
4326 amdgpu_release_ras_context(adev);
4327
4328failed:
4329 amdgpu_vf_error_trans_all(adev);
4330
4331 return r;
4332}
4333
4334static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4335{
4336
4337 /* Clear all CPU mappings pointing to this device */
4338 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4339
4340 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4341 amdgpu_doorbell_fini(adev);
4342
4343 iounmap(adev->rmmio);
4344 adev->rmmio = NULL;
4345 if (adev->mman.aper_base_kaddr)
4346 iounmap(adev->mman.aper_base_kaddr);
4347 adev->mman.aper_base_kaddr = NULL;
4348
4349 /* Memory manager related */
4350 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4351 arch_phys_wc_del(adev->gmc.vram_mtrr);
4352 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4353 }
4354}
4355
4356/**
4357 * amdgpu_device_fini_hw - tear down the driver
4358 *
4359 * @adev: amdgpu_device pointer
4360 *
4361 * Tear down the driver info (all asics).
4362 * Called at driver shutdown.
4363 */
4364void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4365{
4366 dev_info(adev->dev, "amdgpu: finishing device.\n");
4367 flush_delayed_work(&adev->delayed_init_work);
4368 adev->shutdown = true;
4369
4370 /* make sure IB test finished before entering exclusive mode
4371 * to avoid preemption on IB test
4372 */
4373 if (amdgpu_sriov_vf(adev)) {
4374 amdgpu_virt_request_full_gpu(adev, false);
4375 amdgpu_virt_fini_data_exchange(adev);
4376 }
4377
4378 /* disable all interrupts */
4379 amdgpu_irq_disable_all(adev);
4380 if (adev->mode_info.mode_config_initialized) {
4381 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4382 drm_helper_force_disable_all(adev_to_drm(adev));
4383 else
4384 drm_atomic_helper_shutdown(adev_to_drm(adev));
4385 }
4386 amdgpu_fence_driver_hw_fini(adev);
4387
4388 if (adev->mman.initialized)
4389 drain_workqueue(adev->mman.bdev.wq);
4390
4391 if (adev->pm.sysfs_initialized)
4392 amdgpu_pm_sysfs_fini(adev);
4393 if (adev->ucode_sysfs_en)
4394 amdgpu_ucode_sysfs_fini(adev);
4395 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4396 amdgpu_fru_sysfs_fini(adev);
4397
4398 amdgpu_reg_state_sysfs_fini(adev);
4399
4400 /* disable ras feature must before hw fini */
4401 amdgpu_ras_pre_fini(adev);
4402
4403 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4404
4405 amdgpu_device_ip_fini_early(adev);
4406
4407 amdgpu_irq_fini_hw(adev);
4408
4409 if (adev->mman.initialized)
4410 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4411
4412 amdgpu_gart_dummy_page_fini(adev);
4413
4414 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4415 amdgpu_device_unmap_mmio(adev);
4416
4417}
4418
4419void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4420{
4421 int idx;
4422 bool px;
4423
4424 amdgpu_fence_driver_sw_fini(adev);
4425 amdgpu_device_ip_fini(adev);
4426 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4427 adev->accel_working = false;
4428 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4429
4430 amdgpu_reset_fini(adev);
4431
4432 /* free i2c buses */
4433 if (!amdgpu_device_has_dc_support(adev))
4434 amdgpu_i2c_fini(adev);
4435
4436 if (amdgpu_emu_mode != 1)
4437 amdgpu_atombios_fini(adev);
4438
4439 kfree(adev->bios);
4440 adev->bios = NULL;
4441
4442 kfree(adev->fru_info);
4443 adev->fru_info = NULL;
4444
4445 px = amdgpu_device_supports_px(adev_to_drm(adev));
4446
4447 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4448 apple_gmux_detect(NULL, NULL)))
4449 vga_switcheroo_unregister_client(adev->pdev);
4450
4451 if (px)
4452 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4453
4454 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4455 vga_client_unregister(adev->pdev);
4456
4457 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4458
4459 iounmap(adev->rmmio);
4460 adev->rmmio = NULL;
4461 amdgpu_doorbell_fini(adev);
4462 drm_dev_exit(idx);
4463 }
4464
4465 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4466 amdgpu_pmu_fini(adev);
4467 if (adev->mman.discovery_bin)
4468 amdgpu_discovery_fini(adev);
4469
4470 amdgpu_reset_put_reset_domain(adev->reset_domain);
4471 adev->reset_domain = NULL;
4472
4473 kfree(adev->pci_state);
4474
4475}
4476
4477/**
4478 * amdgpu_device_evict_resources - evict device resources
4479 * @adev: amdgpu device object
4480 *
4481 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4482 * of the vram memory type. Mainly used for evicting device resources
4483 * at suspend time.
4484 *
4485 */
4486static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4487{
4488 int ret;
4489
4490 /* No need to evict vram on APUs for suspend to ram or s2idle */
4491 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4492 return 0;
4493
4494 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4495 if (ret)
4496 DRM_WARN("evicting device resources failed\n");
4497 return ret;
4498}
4499
4500/*
4501 * Suspend & resume.
4502 */
4503/**
4504 * amdgpu_device_prepare - prepare for device suspend
4505 *
4506 * @dev: drm dev pointer
4507 *
4508 * Prepare to put the hw in the suspend state (all asics).
4509 * Returns 0 for success or an error on failure.
4510 * Called at driver suspend.
4511 */
4512int amdgpu_device_prepare(struct drm_device *dev)
4513{
4514 struct amdgpu_device *adev = drm_to_adev(dev);
4515 int i, r;
4516
4517 amdgpu_choose_low_power_state(adev);
4518
4519 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4520 return 0;
4521
4522 /* Evict the majority of BOs before starting suspend sequence */
4523 r = amdgpu_device_evict_resources(adev);
4524 if (r)
4525 goto unprepare;
4526
4527 for (i = 0; i < adev->num_ip_blocks; i++) {
4528 if (!adev->ip_blocks[i].status.valid)
4529 continue;
4530 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4531 continue;
4532 r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev);
4533 if (r)
4534 goto unprepare;
4535 }
4536
4537 return 0;
4538
4539unprepare:
4540 adev->in_s0ix = adev->in_s3 = false;
4541
4542 return r;
4543}
4544
4545/**
4546 * amdgpu_device_suspend - initiate device suspend
4547 *
4548 * @dev: drm dev pointer
4549 * @fbcon : notify the fbdev of suspend
4550 *
4551 * Puts the hw in the suspend state (all asics).
4552 * Returns 0 for success or an error on failure.
4553 * Called at driver suspend.
4554 */
4555int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4556{
4557 struct amdgpu_device *adev = drm_to_adev(dev);
4558 int r = 0;
4559
4560 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4561 return 0;
4562
4563 adev->in_suspend = true;
4564
4565 if (amdgpu_sriov_vf(adev)) {
4566 amdgpu_virt_fini_data_exchange(adev);
4567 r = amdgpu_virt_request_full_gpu(adev, false);
4568 if (r)
4569 return r;
4570 }
4571
4572 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4573 DRM_WARN("smart shift update failed\n");
4574
4575 if (fbcon)
4576 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4577
4578 cancel_delayed_work_sync(&adev->delayed_init_work);
4579
4580 amdgpu_ras_suspend(adev);
4581
4582 amdgpu_device_ip_suspend_phase1(adev);
4583
4584 if (!adev->in_s0ix)
4585 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4586
4587 r = amdgpu_device_evict_resources(adev);
4588 if (r)
4589 return r;
4590
4591 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4592
4593 amdgpu_fence_driver_hw_fini(adev);
4594
4595 amdgpu_device_ip_suspend_phase2(adev);
4596
4597 if (amdgpu_sriov_vf(adev))
4598 amdgpu_virt_release_full_gpu(adev, false);
4599
4600 r = amdgpu_dpm_notify_rlc_state(adev, false);
4601 if (r)
4602 return r;
4603
4604 return 0;
4605}
4606
4607/**
4608 * amdgpu_device_resume - initiate device resume
4609 *
4610 * @dev: drm dev pointer
4611 * @fbcon : notify the fbdev of resume
4612 *
4613 * Bring the hw back to operating state (all asics).
4614 * Returns 0 for success or an error on failure.
4615 * Called at driver resume.
4616 */
4617int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4618{
4619 struct amdgpu_device *adev = drm_to_adev(dev);
4620 int r = 0;
4621
4622 if (amdgpu_sriov_vf(adev)) {
4623 r = amdgpu_virt_request_full_gpu(adev, true);
4624 if (r)
4625 return r;
4626 }
4627
4628 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4629 return 0;
4630
4631 if (adev->in_s0ix)
4632 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4633
4634 /* post card */
4635 if (amdgpu_device_need_post(adev)) {
4636 r = amdgpu_device_asic_init(adev);
4637 if (r)
4638 dev_err(adev->dev, "amdgpu asic init failed\n");
4639 }
4640
4641 r = amdgpu_device_ip_resume(adev);
4642
4643 if (r) {
4644 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4645 goto exit;
4646 }
4647 amdgpu_fence_driver_hw_init(adev);
4648
4649 if (!adev->in_s0ix) {
4650 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4651 if (r)
4652 goto exit;
4653 }
4654
4655 r = amdgpu_device_ip_late_init(adev);
4656 if (r)
4657 goto exit;
4658
4659 queue_delayed_work(system_wq, &adev->delayed_init_work,
4660 msecs_to_jiffies(AMDGPU_RESUME_MS));
4661exit:
4662 if (amdgpu_sriov_vf(adev)) {
4663 amdgpu_virt_init_data_exchange(adev);
4664 amdgpu_virt_release_full_gpu(adev, true);
4665 }
4666
4667 if (r)
4668 return r;
4669
4670 /* Make sure IB tests flushed */
4671 flush_delayed_work(&adev->delayed_init_work);
4672
4673 if (fbcon)
4674 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4675
4676 amdgpu_ras_resume(adev);
4677
4678 if (adev->mode_info.num_crtc) {
4679 /*
4680 * Most of the connector probing functions try to acquire runtime pm
4681 * refs to ensure that the GPU is powered on when connector polling is
4682 * performed. Since we're calling this from a runtime PM callback,
4683 * trying to acquire rpm refs will cause us to deadlock.
4684 *
4685 * Since we're guaranteed to be holding the rpm lock, it's safe to
4686 * temporarily disable the rpm helpers so this doesn't deadlock us.
4687 */
4688#ifdef CONFIG_PM
4689 dev->dev->power.disable_depth++;
4690#endif
4691 if (!adev->dc_enabled)
4692 drm_helper_hpd_irq_event(dev);
4693 else
4694 drm_kms_helper_hotplug_event(dev);
4695#ifdef CONFIG_PM
4696 dev->dev->power.disable_depth--;
4697#endif
4698 }
4699 adev->in_suspend = false;
4700
4701 if (adev->enable_mes)
4702 amdgpu_mes_self_test(adev);
4703
4704 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4705 DRM_WARN("smart shift update failed\n");
4706
4707 return 0;
4708}
4709
4710/**
4711 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4712 *
4713 * @adev: amdgpu_device pointer
4714 *
4715 * The list of all the hardware IPs that make up the asic is walked and
4716 * the check_soft_reset callbacks are run. check_soft_reset determines
4717 * if the asic is still hung or not.
4718 * Returns true if any of the IPs are still in a hung state, false if not.
4719 */
4720static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4721{
4722 int i;
4723 bool asic_hang = false;
4724
4725 if (amdgpu_sriov_vf(adev))
4726 return true;
4727
4728 if (amdgpu_asic_need_full_reset(adev))
4729 return true;
4730
4731 for (i = 0; i < adev->num_ip_blocks; i++) {
4732 if (!adev->ip_blocks[i].status.valid)
4733 continue;
4734 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4735 adev->ip_blocks[i].status.hang =
4736 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4737 if (adev->ip_blocks[i].status.hang) {
4738 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4739 asic_hang = true;
4740 }
4741 }
4742 return asic_hang;
4743}
4744
4745/**
4746 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4747 *
4748 * @adev: amdgpu_device pointer
4749 *
4750 * The list of all the hardware IPs that make up the asic is walked and the
4751 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4752 * handles any IP specific hardware or software state changes that are
4753 * necessary for a soft reset to succeed.
4754 * Returns 0 on success, negative error code on failure.
4755 */
4756static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4757{
4758 int i, r = 0;
4759
4760 for (i = 0; i < adev->num_ip_blocks; i++) {
4761 if (!adev->ip_blocks[i].status.valid)
4762 continue;
4763 if (adev->ip_blocks[i].status.hang &&
4764 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4765 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4766 if (r)
4767 return r;
4768 }
4769 }
4770
4771 return 0;
4772}
4773
4774/**
4775 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4776 *
4777 * @adev: amdgpu_device pointer
4778 *
4779 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4780 * reset is necessary to recover.
4781 * Returns true if a full asic reset is required, false if not.
4782 */
4783static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4784{
4785 int i;
4786
4787 if (amdgpu_asic_need_full_reset(adev))
4788 return true;
4789
4790 for (i = 0; i < adev->num_ip_blocks; i++) {
4791 if (!adev->ip_blocks[i].status.valid)
4792 continue;
4793 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4794 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4795 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4796 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4797 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4798 if (adev->ip_blocks[i].status.hang) {
4799 dev_info(adev->dev, "Some block need full reset!\n");
4800 return true;
4801 }
4802 }
4803 }
4804 return false;
4805}
4806
4807/**
4808 * amdgpu_device_ip_soft_reset - do a soft reset
4809 *
4810 * @adev: amdgpu_device pointer
4811 *
4812 * The list of all the hardware IPs that make up the asic is walked and the
4813 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4814 * IP specific hardware or software state changes that are necessary to soft
4815 * reset the IP.
4816 * Returns 0 on success, negative error code on failure.
4817 */
4818static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4819{
4820 int i, r = 0;
4821
4822 for (i = 0; i < adev->num_ip_blocks; i++) {
4823 if (!adev->ip_blocks[i].status.valid)
4824 continue;
4825 if (adev->ip_blocks[i].status.hang &&
4826 adev->ip_blocks[i].version->funcs->soft_reset) {
4827 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4828 if (r)
4829 return r;
4830 }
4831 }
4832
4833 return 0;
4834}
4835
4836/**
4837 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4838 *
4839 * @adev: amdgpu_device pointer
4840 *
4841 * The list of all the hardware IPs that make up the asic is walked and the
4842 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4843 * handles any IP specific hardware or software state changes that are
4844 * necessary after the IP has been soft reset.
4845 * Returns 0 on success, negative error code on failure.
4846 */
4847static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4848{
4849 int i, r = 0;
4850
4851 for (i = 0; i < adev->num_ip_blocks; i++) {
4852 if (!adev->ip_blocks[i].status.valid)
4853 continue;
4854 if (adev->ip_blocks[i].status.hang &&
4855 adev->ip_blocks[i].version->funcs->post_soft_reset)
4856 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4857 if (r)
4858 return r;
4859 }
4860
4861 return 0;
4862}
4863
4864/**
4865 * amdgpu_device_recover_vram - Recover some VRAM contents
4866 *
4867 * @adev: amdgpu_device pointer
4868 *
4869 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4870 * restore things like GPUVM page tables after a GPU reset where
4871 * the contents of VRAM might be lost.
4872 *
4873 * Returns:
4874 * 0 on success, negative error code on failure.
4875 */
4876static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4877{
4878 struct dma_fence *fence = NULL, *next = NULL;
4879 struct amdgpu_bo *shadow;
4880 struct amdgpu_bo_vm *vmbo;
4881 long r = 1, tmo;
4882
4883 if (amdgpu_sriov_runtime(adev))
4884 tmo = msecs_to_jiffies(8000);
4885 else
4886 tmo = msecs_to_jiffies(100);
4887
4888 dev_info(adev->dev, "recover vram bo from shadow start\n");
4889 mutex_lock(&adev->shadow_list_lock);
4890 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4891 /* If vm is compute context or adev is APU, shadow will be NULL */
4892 if (!vmbo->shadow)
4893 continue;
4894 shadow = vmbo->shadow;
4895
4896 /* No need to recover an evicted BO */
4897 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4898 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4899 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4900 continue;
4901
4902 r = amdgpu_bo_restore_shadow(shadow, &next);
4903 if (r)
4904 break;
4905
4906 if (fence) {
4907 tmo = dma_fence_wait_timeout(fence, false, tmo);
4908 dma_fence_put(fence);
4909 fence = next;
4910 if (tmo == 0) {
4911 r = -ETIMEDOUT;
4912 break;
4913 } else if (tmo < 0) {
4914 r = tmo;
4915 break;
4916 }
4917 } else {
4918 fence = next;
4919 }
4920 }
4921 mutex_unlock(&adev->shadow_list_lock);
4922
4923 if (fence)
4924 tmo = dma_fence_wait_timeout(fence, false, tmo);
4925 dma_fence_put(fence);
4926
4927 if (r < 0 || tmo <= 0) {
4928 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4929 return -EIO;
4930 }
4931
4932 dev_info(adev->dev, "recover vram bo from shadow done\n");
4933 return 0;
4934}
4935
4936
4937/**
4938 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4939 *
4940 * @adev: amdgpu_device pointer
4941 * @from_hypervisor: request from hypervisor
4942 *
4943 * do VF FLR and reinitialize Asic
4944 * return 0 means succeeded otherwise failed
4945 */
4946static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4947 bool from_hypervisor)
4948{
4949 int r;
4950 struct amdgpu_hive_info *hive = NULL;
4951 int retry_limit = 0;
4952
4953retry:
4954 amdgpu_amdkfd_pre_reset(adev);
4955
4956 if (from_hypervisor)
4957 r = amdgpu_virt_request_full_gpu(adev, true);
4958 else
4959 r = amdgpu_virt_reset_gpu(adev);
4960 if (r)
4961 return r;
4962 amdgpu_irq_gpu_reset_resume_helper(adev);
4963
4964 /* some sw clean up VF needs to do before recover */
4965 amdgpu_virt_post_reset(adev);
4966
4967 /* Resume IP prior to SMC */
4968 r = amdgpu_device_ip_reinit_early_sriov(adev);
4969 if (r)
4970 goto error;
4971
4972 amdgpu_virt_init_data_exchange(adev);
4973
4974 r = amdgpu_device_fw_loading(adev);
4975 if (r)
4976 return r;
4977
4978 /* now we are okay to resume SMC/CP/SDMA */
4979 r = amdgpu_device_ip_reinit_late_sriov(adev);
4980 if (r)
4981 goto error;
4982
4983 hive = amdgpu_get_xgmi_hive(adev);
4984 /* Update PSP FW topology after reset */
4985 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4986 r = amdgpu_xgmi_update_topology(hive, adev);
4987
4988 if (hive)
4989 amdgpu_put_xgmi_hive(hive);
4990
4991 if (!r) {
4992 r = amdgpu_ib_ring_tests(adev);
4993
4994 amdgpu_amdkfd_post_reset(adev);
4995 }
4996
4997error:
4998 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4999 amdgpu_inc_vram_lost(adev);
5000 r = amdgpu_device_recover_vram(adev);
5001 }
5002 amdgpu_virt_release_full_gpu(adev, true);
5003
5004 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
5005 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
5006 retry_limit++;
5007 goto retry;
5008 } else
5009 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
5010 }
5011
5012 return r;
5013}
5014
5015/**
5016 * amdgpu_device_has_job_running - check if there is any job in mirror list
5017 *
5018 * @adev: amdgpu_device pointer
5019 *
5020 * check if there is any job in mirror list
5021 */
5022bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
5023{
5024 int i;
5025 struct drm_sched_job *job;
5026
5027 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5028 struct amdgpu_ring *ring = adev->rings[i];
5029
5030 if (!amdgpu_ring_sched_ready(ring))
5031 continue;
5032
5033 spin_lock(&ring->sched.job_list_lock);
5034 job = list_first_entry_or_null(&ring->sched.pending_list,
5035 struct drm_sched_job, list);
5036 spin_unlock(&ring->sched.job_list_lock);
5037 if (job)
5038 return true;
5039 }
5040 return false;
5041}
5042
5043/**
5044 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
5045 *
5046 * @adev: amdgpu_device pointer
5047 *
5048 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
5049 * a hung GPU.
5050 */
5051bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
5052{
5053
5054 if (amdgpu_gpu_recovery == 0)
5055 goto disabled;
5056
5057 /* Skip soft reset check in fatal error mode */
5058 if (!amdgpu_ras_is_poison_mode_supported(adev))
5059 return true;
5060
5061 if (amdgpu_sriov_vf(adev))
5062 return true;
5063
5064 if (amdgpu_gpu_recovery == -1) {
5065 switch (adev->asic_type) {
5066#ifdef CONFIG_DRM_AMDGPU_SI
5067 case CHIP_VERDE:
5068 case CHIP_TAHITI:
5069 case CHIP_PITCAIRN:
5070 case CHIP_OLAND:
5071 case CHIP_HAINAN:
5072#endif
5073#ifdef CONFIG_DRM_AMDGPU_CIK
5074 case CHIP_KAVERI:
5075 case CHIP_KABINI:
5076 case CHIP_MULLINS:
5077#endif
5078 case CHIP_CARRIZO:
5079 case CHIP_STONEY:
5080 case CHIP_CYAN_SKILLFISH:
5081 goto disabled;
5082 default:
5083 break;
5084 }
5085 }
5086
5087 return true;
5088
5089disabled:
5090 dev_info(adev->dev, "GPU recovery disabled.\n");
5091 return false;
5092}
5093
5094int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5095{
5096 u32 i;
5097 int ret = 0;
5098
5099 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5100
5101 dev_info(adev->dev, "GPU mode1 reset\n");
5102
5103 /* disable BM */
5104 pci_clear_master(adev->pdev);
5105
5106 amdgpu_device_cache_pci_state(adev->pdev);
5107
5108 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5109 dev_info(adev->dev, "GPU smu mode1 reset\n");
5110 ret = amdgpu_dpm_mode1_reset(adev);
5111 } else {
5112 dev_info(adev->dev, "GPU psp mode1 reset\n");
5113 ret = psp_gpu_reset(adev);
5114 }
5115
5116 if (ret)
5117 goto mode1_reset_failed;
5118
5119 amdgpu_device_load_pci_state(adev->pdev);
5120 ret = amdgpu_psp_wait_for_bootloader(adev);
5121 if (ret)
5122 goto mode1_reset_failed;
5123
5124 /* wait for asic to come out of reset */
5125 for (i = 0; i < adev->usec_timeout; i++) {
5126 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5127
5128 if (memsize != 0xffffffff)
5129 break;
5130 udelay(1);
5131 }
5132
5133 if (i >= adev->usec_timeout) {
5134 ret = -ETIMEDOUT;
5135 goto mode1_reset_failed;
5136 }
5137
5138 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5139
5140 return 0;
5141
5142mode1_reset_failed:
5143 dev_err(adev->dev, "GPU mode1 reset failed\n");
5144 return ret;
5145}
5146
5147int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5148 struct amdgpu_reset_context *reset_context)
5149{
5150 int i, r = 0;
5151 struct amdgpu_job *job = NULL;
5152 bool need_full_reset =
5153 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5154
5155 if (reset_context->reset_req_dev == adev)
5156 job = reset_context->job;
5157
5158 if (amdgpu_sriov_vf(adev)) {
5159 /* stop the data exchange thread */
5160 amdgpu_virt_fini_data_exchange(adev);
5161 }
5162
5163 amdgpu_fence_driver_isr_toggle(adev, true);
5164
5165 /* block all schedulers and reset given job's ring */
5166 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5167 struct amdgpu_ring *ring = adev->rings[i];
5168
5169 if (!amdgpu_ring_sched_ready(ring))
5170 continue;
5171
5172 /* Clear job fence from fence drv to avoid force_completion
5173 * leave NULL and vm flush fence in fence drv
5174 */
5175 amdgpu_fence_driver_clear_job_fences(ring);
5176
5177 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5178 amdgpu_fence_driver_force_completion(ring);
5179 }
5180
5181 amdgpu_fence_driver_isr_toggle(adev, false);
5182
5183 if (job && job->vm)
5184 drm_sched_increase_karma(&job->base);
5185
5186 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5187 /* If reset handler not implemented, continue; otherwise return */
5188 if (r == -EOPNOTSUPP)
5189 r = 0;
5190 else
5191 return r;
5192
5193 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5194 if (!amdgpu_sriov_vf(adev)) {
5195
5196 if (!need_full_reset)
5197 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5198
5199 if (!need_full_reset && amdgpu_gpu_recovery &&
5200 amdgpu_device_ip_check_soft_reset(adev)) {
5201 amdgpu_device_ip_pre_soft_reset(adev);
5202 r = amdgpu_device_ip_soft_reset(adev);
5203 amdgpu_device_ip_post_soft_reset(adev);
5204 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5205 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5206 need_full_reset = true;
5207 }
5208 }
5209
5210 if (need_full_reset)
5211 r = amdgpu_device_ip_suspend(adev);
5212 if (need_full_reset)
5213 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5214 else
5215 clear_bit(AMDGPU_NEED_FULL_RESET,
5216 &reset_context->flags);
5217 }
5218
5219 return r;
5220}
5221
5222static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
5223{
5224 int i;
5225
5226 lockdep_assert_held(&adev->reset_domain->sem);
5227
5228 for (i = 0; i < adev->reset_info.num_regs; i++) {
5229 adev->reset_info.reset_dump_reg_value[i] =
5230 RREG32(adev->reset_info.reset_dump_reg_list[i]);
5231
5232 trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i],
5233 adev->reset_info.reset_dump_reg_value[i]);
5234 }
5235
5236 return 0;
5237}
5238
5239int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5240 struct amdgpu_reset_context *reset_context)
5241{
5242 struct amdgpu_device *tmp_adev = NULL;
5243 bool need_full_reset, skip_hw_reset, vram_lost = false;
5244 int r = 0;
5245
5246 /* Try reset handler method first */
5247 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5248 reset_list);
5249 amdgpu_reset_reg_dumps(tmp_adev);
5250
5251 reset_context->reset_device_list = device_list_handle;
5252 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5253 /* If reset handler not implemented, continue; otherwise return */
5254 if (r == -EOPNOTSUPP)
5255 r = 0;
5256 else
5257 return r;
5258
5259 /* Reset handler not implemented, use the default method */
5260 need_full_reset =
5261 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5262 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5263
5264 /*
5265 * ASIC reset has to be done on all XGMI hive nodes ASAP
5266 * to allow proper links negotiation in FW (within 1 sec)
5267 */
5268 if (!skip_hw_reset && need_full_reset) {
5269 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5270 /* For XGMI run all resets in parallel to speed up the process */
5271 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5272 tmp_adev->gmc.xgmi.pending_reset = false;
5273 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
5274 r = -EALREADY;
5275 } else
5276 r = amdgpu_asic_reset(tmp_adev);
5277
5278 if (r) {
5279 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
5280 r, adev_to_drm(tmp_adev)->unique);
5281 goto out;
5282 }
5283 }
5284
5285 /* For XGMI wait for all resets to complete before proceed */
5286 if (!r) {
5287 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5288 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5289 flush_work(&tmp_adev->xgmi_reset_work);
5290 r = tmp_adev->asic_reset_res;
5291 if (r)
5292 break;
5293 }
5294 }
5295 }
5296 }
5297
5298 if (!r && amdgpu_ras_intr_triggered()) {
5299 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5300 amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);
5301 }
5302
5303 amdgpu_ras_intr_cleared();
5304 }
5305
5306 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5307 if (need_full_reset) {
5308 /* post card */
5309 r = amdgpu_device_asic_init(tmp_adev);
5310 if (r) {
5311 dev_warn(tmp_adev->dev, "asic atom init failed!");
5312 } else {
5313 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5314
5315 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5316 if (r)
5317 goto out;
5318
5319 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5320
5321 amdgpu_coredump(tmp_adev, vram_lost, reset_context);
5322
5323 if (vram_lost) {
5324 DRM_INFO("VRAM is lost due to GPU reset!\n");
5325 amdgpu_inc_vram_lost(tmp_adev);
5326 }
5327
5328 r = amdgpu_device_fw_loading(tmp_adev);
5329 if (r)
5330 return r;
5331
5332 r = amdgpu_xcp_restore_partition_mode(
5333 tmp_adev->xcp_mgr);
5334 if (r)
5335 goto out;
5336
5337 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5338 if (r)
5339 goto out;
5340
5341 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5342 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5343
5344 if (vram_lost)
5345 amdgpu_device_fill_reset_magic(tmp_adev);
5346
5347 /*
5348 * Add this ASIC as tracked as reset was already
5349 * complete successfully.
5350 */
5351 amdgpu_register_gpu_instance(tmp_adev);
5352
5353 if (!reset_context->hive &&
5354 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5355 amdgpu_xgmi_add_device(tmp_adev);
5356
5357 r = amdgpu_device_ip_late_init(tmp_adev);
5358 if (r)
5359 goto out;
5360
5361 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5362
5363 /*
5364 * The GPU enters bad state once faulty pages
5365 * by ECC has reached the threshold, and ras
5366 * recovery is scheduled next. So add one check
5367 * here to break recovery if it indeed exceeds
5368 * bad page threshold, and remind user to
5369 * retire this GPU or setting one bigger
5370 * bad_page_threshold value to fix this once
5371 * probing driver again.
5372 */
5373 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5374 /* must succeed. */
5375 amdgpu_ras_resume(tmp_adev);
5376 } else {
5377 r = -EINVAL;
5378 goto out;
5379 }
5380
5381 /* Update PSP FW topology after reset */
5382 if (reset_context->hive &&
5383 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5384 r = amdgpu_xgmi_update_topology(
5385 reset_context->hive, tmp_adev);
5386 }
5387 }
5388
5389out:
5390 if (!r) {
5391 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5392 r = amdgpu_ib_ring_tests(tmp_adev);
5393 if (r) {
5394 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5395 need_full_reset = true;
5396 r = -EAGAIN;
5397 goto end;
5398 }
5399 }
5400
5401 if (!r)
5402 r = amdgpu_device_recover_vram(tmp_adev);
5403 else
5404 tmp_adev->asic_reset_res = r;
5405 }
5406
5407end:
5408 if (need_full_reset)
5409 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5410 else
5411 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5412 return r;
5413}
5414
5415static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5416{
5417
5418 switch (amdgpu_asic_reset_method(adev)) {
5419 case AMD_RESET_METHOD_MODE1:
5420 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5421 break;
5422 case AMD_RESET_METHOD_MODE2:
5423 adev->mp1_state = PP_MP1_STATE_RESET;
5424 break;
5425 default:
5426 adev->mp1_state = PP_MP1_STATE_NONE;
5427 break;
5428 }
5429}
5430
5431static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5432{
5433 amdgpu_vf_error_trans_all(adev);
5434 adev->mp1_state = PP_MP1_STATE_NONE;
5435}
5436
5437static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5438{
5439 struct pci_dev *p = NULL;
5440
5441 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5442 adev->pdev->bus->number, 1);
5443 if (p) {
5444 pm_runtime_enable(&(p->dev));
5445 pm_runtime_resume(&(p->dev));
5446 }
5447
5448 pci_dev_put(p);
5449}
5450
5451static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5452{
5453 enum amd_reset_method reset_method;
5454 struct pci_dev *p = NULL;
5455 u64 expires;
5456
5457 /*
5458 * For now, only BACO and mode1 reset are confirmed
5459 * to suffer the audio issue without proper suspended.
5460 */
5461 reset_method = amdgpu_asic_reset_method(adev);
5462 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5463 (reset_method != AMD_RESET_METHOD_MODE1))
5464 return -EINVAL;
5465
5466 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5467 adev->pdev->bus->number, 1);
5468 if (!p)
5469 return -ENODEV;
5470
5471 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5472 if (!expires)
5473 /*
5474 * If we cannot get the audio device autosuspend delay,
5475 * a fixed 4S interval will be used. Considering 3S is
5476 * the audio controller default autosuspend delay setting.
5477 * 4S used here is guaranteed to cover that.
5478 */
5479 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5480
5481 while (!pm_runtime_status_suspended(&(p->dev))) {
5482 if (!pm_runtime_suspend(&(p->dev)))
5483 break;
5484
5485 if (expires < ktime_get_mono_fast_ns()) {
5486 dev_warn(adev->dev, "failed to suspend display audio\n");
5487 pci_dev_put(p);
5488 /* TODO: abort the succeeding gpu reset? */
5489 return -ETIMEDOUT;
5490 }
5491 }
5492
5493 pm_runtime_disable(&(p->dev));
5494
5495 pci_dev_put(p);
5496 return 0;
5497}
5498
5499static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5500{
5501 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5502
5503#if defined(CONFIG_DEBUG_FS)
5504 if (!amdgpu_sriov_vf(adev))
5505 cancel_work(&adev->reset_work);
5506#endif
5507
5508 if (adev->kfd.dev)
5509 cancel_work(&adev->kfd.reset_work);
5510
5511 if (amdgpu_sriov_vf(adev))
5512 cancel_work(&adev->virt.flr_work);
5513
5514 if (con && adev->ras_enabled)
5515 cancel_work(&con->recovery_work);
5516
5517}
5518
5519/**
5520 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5521 *
5522 * @adev: amdgpu_device pointer
5523 * @job: which job trigger hang
5524 * @reset_context: amdgpu reset context pointer
5525 *
5526 * Attempt to reset the GPU if it has hung (all asics).
5527 * Attempt to do soft-reset or full-reset and reinitialize Asic
5528 * Returns 0 for success or an error on failure.
5529 */
5530
5531int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5532 struct amdgpu_job *job,
5533 struct amdgpu_reset_context *reset_context)
5534{
5535 struct list_head device_list, *device_list_handle = NULL;
5536 bool job_signaled = false;
5537 struct amdgpu_hive_info *hive = NULL;
5538 struct amdgpu_device *tmp_adev = NULL;
5539 int i, r = 0;
5540 bool need_emergency_restart = false;
5541 bool audio_suspended = false;
5542
5543 /*
5544 * Special case: RAS triggered and full reset isn't supported
5545 */
5546 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5547
5548 /*
5549 * Flush RAM to disk so that after reboot
5550 * the user can read log and see why the system rebooted.
5551 */
5552 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5553 amdgpu_ras_get_context(adev)->reboot) {
5554 DRM_WARN("Emergency reboot.");
5555
5556 ksys_sync_helper();
5557 emergency_restart();
5558 }
5559
5560 dev_info(adev->dev, "GPU %s begin!\n",
5561 need_emergency_restart ? "jobs stop":"reset");
5562
5563 if (!amdgpu_sriov_vf(adev))
5564 hive = amdgpu_get_xgmi_hive(adev);
5565 if (hive)
5566 mutex_lock(&hive->hive_lock);
5567
5568 reset_context->job = job;
5569 reset_context->hive = hive;
5570 /*
5571 * Build list of devices to reset.
5572 * In case we are in XGMI hive mode, resort the device list
5573 * to put adev in the 1st position.
5574 */
5575 INIT_LIST_HEAD(&device_list);
5576 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5577 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5578 list_add_tail(&tmp_adev->reset_list, &device_list);
5579 if (adev->shutdown)
5580 tmp_adev->shutdown = true;
5581 }
5582 if (!list_is_first(&adev->reset_list, &device_list))
5583 list_rotate_to_front(&adev->reset_list, &device_list);
5584 device_list_handle = &device_list;
5585 } else {
5586 list_add_tail(&adev->reset_list, &device_list);
5587 device_list_handle = &device_list;
5588 }
5589
5590 /* We need to lock reset domain only once both for XGMI and single device */
5591 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5592 reset_list);
5593 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5594
5595 /* block all schedulers and reset given job's ring */
5596 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5597
5598 amdgpu_device_set_mp1_state(tmp_adev);
5599
5600 /*
5601 * Try to put the audio codec into suspend state
5602 * before gpu reset started.
5603 *
5604 * Due to the power domain of the graphics device
5605 * is shared with AZ power domain. Without this,
5606 * we may change the audio hardware from behind
5607 * the audio driver's back. That will trigger
5608 * some audio codec errors.
5609 */
5610 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5611 audio_suspended = true;
5612
5613 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5614
5615 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5616
5617 if (!amdgpu_sriov_vf(tmp_adev))
5618 amdgpu_amdkfd_pre_reset(tmp_adev);
5619
5620 /*
5621 * Mark these ASICs to be reseted as untracked first
5622 * And add them back after reset completed
5623 */
5624 amdgpu_unregister_gpu_instance(tmp_adev);
5625
5626 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5627
5628 /* disable ras on ALL IPs */
5629 if (!need_emergency_restart &&
5630 amdgpu_device_ip_need_full_reset(tmp_adev))
5631 amdgpu_ras_suspend(tmp_adev);
5632
5633 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5634 struct amdgpu_ring *ring = tmp_adev->rings[i];
5635
5636 if (!amdgpu_ring_sched_ready(ring))
5637 continue;
5638
5639 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5640
5641 if (need_emergency_restart)
5642 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5643 }
5644 atomic_inc(&tmp_adev->gpu_reset_counter);
5645 }
5646
5647 if (need_emergency_restart)
5648 goto skip_sched_resume;
5649
5650 /*
5651 * Must check guilty signal here since after this point all old
5652 * HW fences are force signaled.
5653 *
5654 * job->base holds a reference to parent fence
5655 */
5656 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5657 job_signaled = true;
5658 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5659 goto skip_hw_reset;
5660 }
5661
5662retry: /* Rest of adevs pre asic reset from XGMI hive. */
5663 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5664 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5665 /*TODO Should we stop ?*/
5666 if (r) {
5667 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5668 r, adev_to_drm(tmp_adev)->unique);
5669 tmp_adev->asic_reset_res = r;
5670 }
5671
5672 /*
5673 * Drop all pending non scheduler resets. Scheduler resets
5674 * were already dropped during drm_sched_stop
5675 */
5676 amdgpu_device_stop_pending_resets(tmp_adev);
5677 }
5678
5679 /* Actual ASIC resets if needed.*/
5680 /* Host driver will handle XGMI hive reset for SRIOV */
5681 if (amdgpu_sriov_vf(adev)) {
5682 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5683 if (r)
5684 adev->asic_reset_res = r;
5685
5686 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5687 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5688 IP_VERSION(9, 4, 2) ||
5689 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5690 amdgpu_ras_resume(adev);
5691 } else {
5692 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5693 if (r && r == -EAGAIN)
5694 goto retry;
5695 }
5696
5697skip_hw_reset:
5698
5699 /* Post ASIC reset for all devs .*/
5700 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5701
5702 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5703 struct amdgpu_ring *ring = tmp_adev->rings[i];
5704
5705 if (!amdgpu_ring_sched_ready(ring))
5706 continue;
5707
5708 drm_sched_start(&ring->sched, true);
5709 }
5710
5711 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5712 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5713
5714 if (tmp_adev->asic_reset_res)
5715 r = tmp_adev->asic_reset_res;
5716
5717 tmp_adev->asic_reset_res = 0;
5718
5719 if (r) {
5720 /* bad news, how to tell it to userspace ? */
5721 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5722 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5723 } else {
5724 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5725 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5726 DRM_WARN("smart shift update failed\n");
5727 }
5728 }
5729
5730skip_sched_resume:
5731 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5732 /* unlock kfd: SRIOV would do it separately */
5733 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5734 amdgpu_amdkfd_post_reset(tmp_adev);
5735
5736 /* kfd_post_reset will do nothing if kfd device is not initialized,
5737 * need to bring up kfd here if it's not be initialized before
5738 */
5739 if (!adev->kfd.init_complete)
5740 amdgpu_amdkfd_device_init(adev);
5741
5742 if (audio_suspended)
5743 amdgpu_device_resume_display_audio(tmp_adev);
5744
5745 amdgpu_device_unset_mp1_state(tmp_adev);
5746
5747 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5748 }
5749
5750 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5751 reset_list);
5752 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5753
5754 if (hive) {
5755 mutex_unlock(&hive->hive_lock);
5756 amdgpu_put_xgmi_hive(hive);
5757 }
5758
5759 if (r)
5760 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5761
5762 atomic_set(&adev->reset_domain->reset_res, r);
5763 return r;
5764}
5765
5766/**
5767 * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner
5768 *
5769 * @adev: amdgpu_device pointer
5770 * @speed: pointer to the speed of the link
5771 * @width: pointer to the width of the link
5772 *
5773 * Evaluate the hierarchy to find the speed and bandwidth capabilities of the
5774 * first physical partner to an AMD dGPU.
5775 * This will exclude any virtual switches and links.
5776 */
5777static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
5778 enum pci_bus_speed *speed,
5779 enum pcie_link_width *width)
5780{
5781 struct pci_dev *parent = adev->pdev;
5782
5783 if (!speed || !width)
5784 return;
5785
5786 *speed = PCI_SPEED_UNKNOWN;
5787 *width = PCIE_LNK_WIDTH_UNKNOWN;
5788
5789 while ((parent = pci_upstream_bridge(parent))) {
5790 /* skip upstream/downstream switches internal to dGPU*/
5791 if (parent->vendor == PCI_VENDOR_ID_ATI)
5792 continue;
5793 *speed = pcie_get_speed_cap(parent);
5794 *width = pcie_get_width_cap(parent);
5795 break;
5796 }
5797}
5798
5799/**
5800 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5801 *
5802 * @adev: amdgpu_device pointer
5803 *
5804 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5805 * and lanes) of the slot the device is in. Handles APUs and
5806 * virtualized environments where PCIE config space may not be available.
5807 */
5808static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5809{
5810 struct pci_dev *pdev;
5811 enum pci_bus_speed speed_cap, platform_speed_cap;
5812 enum pcie_link_width platform_link_width;
5813
5814 if (amdgpu_pcie_gen_cap)
5815 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5816
5817 if (amdgpu_pcie_lane_cap)
5818 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5819
5820 /* covers APUs as well */
5821 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5822 if (adev->pm.pcie_gen_mask == 0)
5823 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5824 if (adev->pm.pcie_mlw_mask == 0)
5825 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5826 return;
5827 }
5828
5829 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5830 return;
5831
5832 amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
5833 &platform_link_width);
5834
5835 if (adev->pm.pcie_gen_mask == 0) {
5836 /* asic caps */
5837 pdev = adev->pdev;
5838 speed_cap = pcie_get_speed_cap(pdev);
5839 if (speed_cap == PCI_SPEED_UNKNOWN) {
5840 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5841 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5842 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5843 } else {
5844 if (speed_cap == PCIE_SPEED_32_0GT)
5845 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5846 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5847 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5848 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5849 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5850 else if (speed_cap == PCIE_SPEED_16_0GT)
5851 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5852 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5853 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5854 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5855 else if (speed_cap == PCIE_SPEED_8_0GT)
5856 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5857 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5858 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5859 else if (speed_cap == PCIE_SPEED_5_0GT)
5860 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5861 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5862 else
5863 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5864 }
5865 /* platform caps */
5866 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5867 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5868 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5869 } else {
5870 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5871 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5872 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5873 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5874 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5875 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5876 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5877 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5878 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5879 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5880 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5881 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5882 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5883 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5884 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5885 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5886 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5887 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5888 else
5889 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5890
5891 }
5892 }
5893 if (adev->pm.pcie_mlw_mask == 0) {
5894 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5895 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5896 } else {
5897 switch (platform_link_width) {
5898 case PCIE_LNK_X32:
5899 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5900 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5901 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5902 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5903 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5904 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5905 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5906 break;
5907 case PCIE_LNK_X16:
5908 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5909 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5910 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5911 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5912 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5913 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5914 break;
5915 case PCIE_LNK_X12:
5916 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5917 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5918 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5919 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5920 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5921 break;
5922 case PCIE_LNK_X8:
5923 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5924 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5925 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5926 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5927 break;
5928 case PCIE_LNK_X4:
5929 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5930 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5931 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5932 break;
5933 case PCIE_LNK_X2:
5934 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5935 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5936 break;
5937 case PCIE_LNK_X1:
5938 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5939 break;
5940 default:
5941 break;
5942 }
5943 }
5944 }
5945}
5946
5947/**
5948 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5949 *
5950 * @adev: amdgpu_device pointer
5951 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5952 *
5953 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5954 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5955 * @peer_adev.
5956 */
5957bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5958 struct amdgpu_device *peer_adev)
5959{
5960#ifdef CONFIG_HSA_AMD_P2P
5961 uint64_t address_mask = peer_adev->dev->dma_mask ?
5962 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5963 resource_size_t aper_limit =
5964 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5965 bool p2p_access =
5966 !adev->gmc.xgmi.connected_to_cpu &&
5967 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5968
5969 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5970 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5971 !(adev->gmc.aper_base & address_mask ||
5972 aper_limit & address_mask));
5973#else
5974 return false;
5975#endif
5976}
5977
5978int amdgpu_device_baco_enter(struct drm_device *dev)
5979{
5980 struct amdgpu_device *adev = drm_to_adev(dev);
5981 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5982
5983 if (!amdgpu_device_supports_baco(dev))
5984 return -ENOTSUPP;
5985
5986 if (ras && adev->ras_enabled &&
5987 adev->nbio.funcs->enable_doorbell_interrupt)
5988 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5989
5990 return amdgpu_dpm_baco_enter(adev);
5991}
5992
5993int amdgpu_device_baco_exit(struct drm_device *dev)
5994{
5995 struct amdgpu_device *adev = drm_to_adev(dev);
5996 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5997 int ret = 0;
5998
5999 if (!amdgpu_device_supports_baco(dev))
6000 return -ENOTSUPP;
6001
6002 ret = amdgpu_dpm_baco_exit(adev);
6003 if (ret)
6004 return ret;
6005
6006 if (ras && adev->ras_enabled &&
6007 adev->nbio.funcs->enable_doorbell_interrupt)
6008 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
6009
6010 if (amdgpu_passthrough(adev) &&
6011 adev->nbio.funcs->clear_doorbell_interrupt)
6012 adev->nbio.funcs->clear_doorbell_interrupt(adev);
6013
6014 return 0;
6015}
6016
6017/**
6018 * amdgpu_pci_error_detected - Called when a PCI error is detected.
6019 * @pdev: PCI device struct
6020 * @state: PCI channel state
6021 *
6022 * Description: Called when a PCI error is detected.
6023 *
6024 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
6025 */
6026pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6027{
6028 struct drm_device *dev = pci_get_drvdata(pdev);
6029 struct amdgpu_device *adev = drm_to_adev(dev);
6030 int i;
6031
6032 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
6033
6034 if (adev->gmc.xgmi.num_physical_nodes > 1) {
6035 DRM_WARN("No support for XGMI hive yet...");
6036 return PCI_ERS_RESULT_DISCONNECT;
6037 }
6038
6039 adev->pci_channel_state = state;
6040
6041 switch (state) {
6042 case pci_channel_io_normal:
6043 return PCI_ERS_RESULT_CAN_RECOVER;
6044 /* Fatal error, prepare for slot reset */
6045 case pci_channel_io_frozen:
6046 /*
6047 * Locking adev->reset_domain->sem will prevent any external access
6048 * to GPU during PCI error recovery
6049 */
6050 amdgpu_device_lock_reset_domain(adev->reset_domain);
6051 amdgpu_device_set_mp1_state(adev);
6052
6053 /*
6054 * Block any work scheduling as we do for regular GPU reset
6055 * for the duration of the recovery
6056 */
6057 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6058 struct amdgpu_ring *ring = adev->rings[i];
6059
6060 if (!amdgpu_ring_sched_ready(ring))
6061 continue;
6062
6063 drm_sched_stop(&ring->sched, NULL);
6064 }
6065 atomic_inc(&adev->gpu_reset_counter);
6066 return PCI_ERS_RESULT_NEED_RESET;
6067 case pci_channel_io_perm_failure:
6068 /* Permanent error, prepare for device removal */
6069 return PCI_ERS_RESULT_DISCONNECT;
6070 }
6071
6072 return PCI_ERS_RESULT_NEED_RESET;
6073}
6074
6075/**
6076 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6077 * @pdev: pointer to PCI device
6078 */
6079pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6080{
6081
6082 DRM_INFO("PCI error: mmio enabled callback!!\n");
6083
6084 /* TODO - dump whatever for debugging purposes */
6085
6086 /* This called only if amdgpu_pci_error_detected returns
6087 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6088 * works, no need to reset slot.
6089 */
6090
6091 return PCI_ERS_RESULT_RECOVERED;
6092}
6093
6094/**
6095 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6096 * @pdev: PCI device struct
6097 *
6098 * Description: This routine is called by the pci error recovery
6099 * code after the PCI slot has been reset, just before we
6100 * should resume normal operations.
6101 */
6102pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6103{
6104 struct drm_device *dev = pci_get_drvdata(pdev);
6105 struct amdgpu_device *adev = drm_to_adev(dev);
6106 int r, i;
6107 struct amdgpu_reset_context reset_context;
6108 u32 memsize;
6109 struct list_head device_list;
6110
6111 DRM_INFO("PCI error: slot reset callback!!\n");
6112
6113 memset(&reset_context, 0, sizeof(reset_context));
6114
6115 INIT_LIST_HEAD(&device_list);
6116 list_add_tail(&adev->reset_list, &device_list);
6117
6118 /* wait for asic to come out of reset */
6119 msleep(500);
6120
6121 /* Restore PCI confspace */
6122 amdgpu_device_load_pci_state(pdev);
6123
6124 /* confirm ASIC came out of reset */
6125 for (i = 0; i < adev->usec_timeout; i++) {
6126 memsize = amdgpu_asic_get_config_memsize(adev);
6127
6128 if (memsize != 0xffffffff)
6129 break;
6130 udelay(1);
6131 }
6132 if (memsize == 0xffffffff) {
6133 r = -ETIME;
6134 goto out;
6135 }
6136
6137 reset_context.method = AMD_RESET_METHOD_NONE;
6138 reset_context.reset_req_dev = adev;
6139 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6140 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6141
6142 adev->no_hw_access = true;
6143 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6144 adev->no_hw_access = false;
6145 if (r)
6146 goto out;
6147
6148 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6149
6150out:
6151 if (!r) {
6152 if (amdgpu_device_cache_pci_state(adev->pdev))
6153 pci_restore_state(adev->pdev);
6154
6155 DRM_INFO("PCIe error recovery succeeded\n");
6156 } else {
6157 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6158 amdgpu_device_unset_mp1_state(adev);
6159 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6160 }
6161
6162 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6163}
6164
6165/**
6166 * amdgpu_pci_resume() - resume normal ops after PCI reset
6167 * @pdev: pointer to PCI device
6168 *
6169 * Called when the error recovery driver tells us that its
6170 * OK to resume normal operation.
6171 */
6172void amdgpu_pci_resume(struct pci_dev *pdev)
6173{
6174 struct drm_device *dev = pci_get_drvdata(pdev);
6175 struct amdgpu_device *adev = drm_to_adev(dev);
6176 int i;
6177
6178
6179 DRM_INFO("PCI error: resume callback!!\n");
6180
6181 /* Only continue execution for the case of pci_channel_io_frozen */
6182 if (adev->pci_channel_state != pci_channel_io_frozen)
6183 return;
6184
6185 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6186 struct amdgpu_ring *ring = adev->rings[i];
6187
6188 if (!amdgpu_ring_sched_ready(ring))
6189 continue;
6190
6191 drm_sched_start(&ring->sched, true);
6192 }
6193
6194 amdgpu_device_unset_mp1_state(adev);
6195 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6196}
6197
6198bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6199{
6200 struct drm_device *dev = pci_get_drvdata(pdev);
6201 struct amdgpu_device *adev = drm_to_adev(dev);
6202 int r;
6203
6204 r = pci_save_state(pdev);
6205 if (!r) {
6206 kfree(adev->pci_state);
6207
6208 adev->pci_state = pci_store_saved_state(pdev);
6209
6210 if (!adev->pci_state) {
6211 DRM_ERROR("Failed to store PCI saved state");
6212 return false;
6213 }
6214 } else {
6215 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6216 return false;
6217 }
6218
6219 return true;
6220}
6221
6222bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6223{
6224 struct drm_device *dev = pci_get_drvdata(pdev);
6225 struct amdgpu_device *adev = drm_to_adev(dev);
6226 int r;
6227
6228 if (!adev->pci_state)
6229 return false;
6230
6231 r = pci_load_saved_state(pdev, adev->pci_state);
6232
6233 if (!r) {
6234 pci_restore_state(pdev);
6235 } else {
6236 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6237 return false;
6238 }
6239
6240 return true;
6241}
6242
6243void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6244 struct amdgpu_ring *ring)
6245{
6246#ifdef CONFIG_X86_64
6247 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6248 return;
6249#endif
6250 if (adev->gmc.xgmi.connected_to_cpu)
6251 return;
6252
6253 if (ring && ring->funcs->emit_hdp_flush)
6254 amdgpu_ring_emit_hdp_flush(ring);
6255 else
6256 amdgpu_asic_flush_hdp(adev, ring);
6257}
6258
6259void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6260 struct amdgpu_ring *ring)
6261{
6262#ifdef CONFIG_X86_64
6263 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6264 return;
6265#endif
6266 if (adev->gmc.xgmi.connected_to_cpu)
6267 return;
6268
6269 amdgpu_asic_invalidate_hdp(adev, ring);
6270}
6271
6272int amdgpu_in_reset(struct amdgpu_device *adev)
6273{
6274 return atomic_read(&adev->reset_domain->in_gpu_reset);
6275}
6276
6277/**
6278 * amdgpu_device_halt() - bring hardware to some kind of halt state
6279 *
6280 * @adev: amdgpu_device pointer
6281 *
6282 * Bring hardware to some kind of halt state so that no one can touch it
6283 * any more. It will help to maintain error context when error occurred.
6284 * Compare to a simple hang, the system will keep stable at least for SSH
6285 * access. Then it should be trivial to inspect the hardware state and
6286 * see what's going on. Implemented as following:
6287 *
6288 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6289 * clears all CPU mappings to device, disallows remappings through page faults
6290 * 2. amdgpu_irq_disable_all() disables all interrupts
6291 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6292 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6293 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6294 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6295 * flush any in flight DMA operations
6296 */
6297void amdgpu_device_halt(struct amdgpu_device *adev)
6298{
6299 struct pci_dev *pdev = adev->pdev;
6300 struct drm_device *ddev = adev_to_drm(adev);
6301
6302 amdgpu_xcp_dev_unplug(adev);
6303 drm_dev_unplug(ddev);
6304
6305 amdgpu_irq_disable_all(adev);
6306
6307 amdgpu_fence_driver_hw_fini(adev);
6308
6309 adev->no_hw_access = true;
6310
6311 amdgpu_device_unmap_mmio(adev);
6312
6313 pci_disable_device(pdev);
6314 pci_wait_for_pending_transaction(pdev);
6315}
6316
6317u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6318 u32 reg)
6319{
6320 unsigned long flags, address, data;
6321 u32 r;
6322
6323 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6324 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6325
6326 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6327 WREG32(address, reg * 4);
6328 (void)RREG32(address);
6329 r = RREG32(data);
6330 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6331 return r;
6332}
6333
6334void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6335 u32 reg, u32 v)
6336{
6337 unsigned long flags, address, data;
6338
6339 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6340 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6341
6342 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6343 WREG32(address, reg * 4);
6344 (void)RREG32(address);
6345 WREG32(data, v);
6346 (void)RREG32(data);
6347 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6348}
6349
6350/**
6351 * amdgpu_device_switch_gang - switch to a new gang
6352 * @adev: amdgpu_device pointer
6353 * @gang: the gang to switch to
6354 *
6355 * Try to switch to a new gang.
6356 * Returns: NULL if we switched to the new gang or a reference to the current
6357 * gang leader.
6358 */
6359struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6360 struct dma_fence *gang)
6361{
6362 struct dma_fence *old = NULL;
6363
6364 do {
6365 dma_fence_put(old);
6366 rcu_read_lock();
6367 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6368 rcu_read_unlock();
6369
6370 if (old == gang)
6371 break;
6372
6373 if (!dma_fence_is_signaled(old))
6374 return old;
6375
6376 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6377 old, gang) != old);
6378
6379 dma_fence_put(old);
6380 return NULL;
6381}
6382
6383bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6384{
6385 switch (adev->asic_type) {
6386#ifdef CONFIG_DRM_AMDGPU_SI
6387 case CHIP_HAINAN:
6388#endif
6389 case CHIP_TOPAZ:
6390 /* chips with no display hardware */
6391 return false;
6392#ifdef CONFIG_DRM_AMDGPU_SI
6393 case CHIP_TAHITI:
6394 case CHIP_PITCAIRN:
6395 case CHIP_VERDE:
6396 case CHIP_OLAND:
6397#endif
6398#ifdef CONFIG_DRM_AMDGPU_CIK
6399 case CHIP_BONAIRE:
6400 case CHIP_HAWAII:
6401 case CHIP_KAVERI:
6402 case CHIP_KABINI:
6403 case CHIP_MULLINS:
6404#endif
6405 case CHIP_TONGA:
6406 case CHIP_FIJI:
6407 case CHIP_POLARIS10:
6408 case CHIP_POLARIS11:
6409 case CHIP_POLARIS12:
6410 case CHIP_VEGAM:
6411 case CHIP_CARRIZO:
6412 case CHIP_STONEY:
6413 /* chips with display hardware */
6414 return true;
6415 default:
6416 /* IP discovery */
6417 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6418 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6419 return false;
6420 return true;
6421 }
6422}
6423
6424uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6425 uint32_t inst, uint32_t reg_addr, char reg_name[],
6426 uint32_t expected_value, uint32_t mask)
6427{
6428 uint32_t ret = 0;
6429 uint32_t old_ = 0;
6430 uint32_t tmp_ = RREG32(reg_addr);
6431 uint32_t loop = adev->usec_timeout;
6432
6433 while ((tmp_ & (mask)) != (expected_value)) {
6434 if (old_ != tmp_) {
6435 loop = adev->usec_timeout;
6436 old_ = tmp_;
6437 } else
6438 udelay(1);
6439 tmp_ = RREG32(reg_addr);
6440 loop--;
6441 if (!loop) {
6442 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6443 inst, reg_name, (uint32_t)expected_value,
6444 (uint32_t)(tmp_ & (mask)));
6445 ret = -ETIMEDOUT;
6446 break;
6447 }
6448 }
6449 return ret;
6450}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/aperture.h>
30#include <linux/power_supply.h>
31#include <linux/kthread.h>
32#include <linux/module.h>
33#include <linux/console.h>
34#include <linux/slab.h>
35#include <linux/iommu.h>
36#include <linux/pci.h>
37#include <linux/pci-p2pdma.h>
38#include <linux/apple-gmux.h>
39
40#include <drm/drm_atomic_helper.h>
41#include <drm/drm_client_event.h>
42#include <drm/drm_crtc_helper.h>
43#include <drm/drm_probe_helper.h>
44#include <drm/amdgpu_drm.h>
45#include <linux/device.h>
46#include <linux/vgaarb.h>
47#include <linux/vga_switcheroo.h>
48#include <linux/efi.h>
49#include "amdgpu.h"
50#include "amdgpu_trace.h"
51#include "amdgpu_i2c.h"
52#include "atom.h"
53#include "amdgpu_atombios.h"
54#include "amdgpu_atomfirmware.h"
55#include "amd_pcie.h"
56#ifdef CONFIG_DRM_AMDGPU_SI
57#include "si.h"
58#endif
59#ifdef CONFIG_DRM_AMDGPU_CIK
60#include "cik.h"
61#endif
62#include "vi.h"
63#include "soc15.h"
64#include "nv.h"
65#include "bif/bif_4_1_d.h"
66#include <linux/firmware.h>
67#include "amdgpu_vf_error.h"
68
69#include "amdgpu_amdkfd.h"
70#include "amdgpu_pm.h"
71
72#include "amdgpu_xgmi.h"
73#include "amdgpu_ras.h"
74#include "amdgpu_pmu.h"
75#include "amdgpu_fru_eeprom.h"
76#include "amdgpu_reset.h"
77#include "amdgpu_virt.h"
78#include "amdgpu_dev_coredump.h"
79
80#include <linux/suspend.h>
81#include <drm/task_barrier.h>
82#include <linux/pm_runtime.h>
83
84#include <drm/drm_drv.h>
85
86#if IS_ENABLED(CONFIG_X86)
87#include <asm/intel-family.h>
88#endif
89
90MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
91MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
92MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
93MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
94MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
95MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
96MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
97
98#define AMDGPU_RESUME_MS 2000
99#define AMDGPU_MAX_RETRY_LIMIT 2
100#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
101#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2)
102#define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2)
103#define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2)
104
105static const struct drm_driver amdgpu_kms_driver;
106
107const char *amdgpu_asic_name[] = {
108 "TAHITI",
109 "PITCAIRN",
110 "VERDE",
111 "OLAND",
112 "HAINAN",
113 "BONAIRE",
114 "KAVERI",
115 "KABINI",
116 "HAWAII",
117 "MULLINS",
118 "TOPAZ",
119 "TONGA",
120 "FIJI",
121 "CARRIZO",
122 "STONEY",
123 "POLARIS10",
124 "POLARIS11",
125 "POLARIS12",
126 "VEGAM",
127 "VEGA10",
128 "VEGA12",
129 "VEGA20",
130 "RAVEN",
131 "ARCTURUS",
132 "RENOIR",
133 "ALDEBARAN",
134 "NAVI10",
135 "CYAN_SKILLFISH",
136 "NAVI14",
137 "NAVI12",
138 "SIENNA_CICHLID",
139 "NAVY_FLOUNDER",
140 "VANGOGH",
141 "DIMGREY_CAVEFISH",
142 "BEIGE_GOBY",
143 "YELLOW_CARP",
144 "IP DISCOVERY",
145 "LAST",
146};
147
148#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)
149/*
150 * Default init level where all blocks are expected to be initialized. This is
151 * the level of initialization expected by default and also after a full reset
152 * of the device.
153 */
154struct amdgpu_init_level amdgpu_init_default = {
155 .level = AMDGPU_INIT_LEVEL_DEFAULT,
156 .hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL,
157};
158
159struct amdgpu_init_level amdgpu_init_recovery = {
160 .level = AMDGPU_INIT_LEVEL_RESET_RECOVERY,
161 .hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL,
162};
163
164/*
165 * Minimal blocks needed to be initialized before a XGMI hive can be reset. This
166 * is used for cases like reset on initialization where the entire hive needs to
167 * be reset before first use.
168 */
169struct amdgpu_init_level amdgpu_init_minimal_xgmi = {
170 .level = AMDGPU_INIT_LEVEL_MINIMAL_XGMI,
171 .hwini_ip_block_mask =
172 BIT(AMD_IP_BLOCK_TYPE_GMC) | BIT(AMD_IP_BLOCK_TYPE_SMC) |
173 BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) |
174 BIT(AMD_IP_BLOCK_TYPE_PSP)
175};
176
177static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev,
178 enum amd_ip_block_type block)
179{
180 return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0;
181}
182
183void amdgpu_set_init_level(struct amdgpu_device *adev,
184 enum amdgpu_init_lvl_id lvl)
185{
186 switch (lvl) {
187 case AMDGPU_INIT_LEVEL_MINIMAL_XGMI:
188 adev->init_lvl = &amdgpu_init_minimal_xgmi;
189 break;
190 case AMDGPU_INIT_LEVEL_RESET_RECOVERY:
191 adev->init_lvl = &amdgpu_init_recovery;
192 break;
193 case AMDGPU_INIT_LEVEL_DEFAULT:
194 fallthrough;
195 default:
196 adev->init_lvl = &amdgpu_init_default;
197 break;
198 }
199}
200
201static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev);
202
203/**
204 * DOC: pcie_replay_count
205 *
206 * The amdgpu driver provides a sysfs API for reporting the total number
207 * of PCIe replays (NAKs)
208 * The file pcie_replay_count is used for this and returns the total
209 * number of replays as a sum of the NAKs generated and NAKs received
210 */
211
212static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
213 struct device_attribute *attr, char *buf)
214{
215 struct drm_device *ddev = dev_get_drvdata(dev);
216 struct amdgpu_device *adev = drm_to_adev(ddev);
217 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
218
219 return sysfs_emit(buf, "%llu\n", cnt);
220}
221
222static DEVICE_ATTR(pcie_replay_count, 0444,
223 amdgpu_device_get_pcie_replay_count, NULL);
224
225static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,
226 struct bin_attribute *attr, char *buf,
227 loff_t ppos, size_t count)
228{
229 struct device *dev = kobj_to_dev(kobj);
230 struct drm_device *ddev = dev_get_drvdata(dev);
231 struct amdgpu_device *adev = drm_to_adev(ddev);
232 ssize_t bytes_read;
233
234 switch (ppos) {
235 case AMDGPU_SYS_REG_STATE_XGMI:
236 bytes_read = amdgpu_asic_get_reg_state(
237 adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);
238 break;
239 case AMDGPU_SYS_REG_STATE_WAFL:
240 bytes_read = amdgpu_asic_get_reg_state(
241 adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);
242 break;
243 case AMDGPU_SYS_REG_STATE_PCIE:
244 bytes_read = amdgpu_asic_get_reg_state(
245 adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);
246 break;
247 case AMDGPU_SYS_REG_STATE_USR:
248 bytes_read = amdgpu_asic_get_reg_state(
249 adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);
250 break;
251 case AMDGPU_SYS_REG_STATE_USR_1:
252 bytes_read = amdgpu_asic_get_reg_state(
253 adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 return bytes_read;
260}
261
262BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,
263 AMDGPU_SYS_REG_STATE_END);
264
265int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)
266{
267 int ret;
268
269 if (!amdgpu_asic_get_reg_state_supported(adev))
270 return 0;
271
272 ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
273
274 return ret;
275}
276
277void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)
278{
279 if (!amdgpu_asic_get_reg_state_supported(adev))
280 return;
281 sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
282}
283
284int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block)
285{
286 int r;
287
288 if (ip_block->version->funcs->suspend) {
289 r = ip_block->version->funcs->suspend(ip_block);
290 if (r) {
291 dev_err(ip_block->adev->dev,
292 "suspend of IP block <%s> failed %d\n",
293 ip_block->version->funcs->name, r);
294 return r;
295 }
296 }
297
298 ip_block->status.hw = false;
299 return 0;
300}
301
302int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block)
303{
304 int r;
305
306 if (ip_block->version->funcs->resume) {
307 r = ip_block->version->funcs->resume(ip_block);
308 if (r) {
309 dev_err(ip_block->adev->dev,
310 "resume of IP block <%s> failed %d\n",
311 ip_block->version->funcs->name, r);
312 return r;
313 }
314 }
315
316 ip_block->status.hw = true;
317 return 0;
318}
319
320/**
321 * DOC: board_info
322 *
323 * The amdgpu driver provides a sysfs API for giving board related information.
324 * It provides the form factor information in the format
325 *
326 * type : form factor
327 *
328 * Possible form factor values
329 *
330 * - "cem" - PCIE CEM card
331 * - "oam" - Open Compute Accelerator Module
332 * - "unknown" - Not known
333 *
334 */
335
336static ssize_t amdgpu_device_get_board_info(struct device *dev,
337 struct device_attribute *attr,
338 char *buf)
339{
340 struct drm_device *ddev = dev_get_drvdata(dev);
341 struct amdgpu_device *adev = drm_to_adev(ddev);
342 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
343 const char *pkg;
344
345 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
346 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
347
348 switch (pkg_type) {
349 case AMDGPU_PKG_TYPE_CEM:
350 pkg = "cem";
351 break;
352 case AMDGPU_PKG_TYPE_OAM:
353 pkg = "oam";
354 break;
355 default:
356 pkg = "unknown";
357 break;
358 }
359
360 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
361}
362
363static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
364
365static struct attribute *amdgpu_board_attrs[] = {
366 &dev_attr_board_info.attr,
367 NULL,
368};
369
370static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
371 struct attribute *attr, int n)
372{
373 struct device *dev = kobj_to_dev(kobj);
374 struct drm_device *ddev = dev_get_drvdata(dev);
375 struct amdgpu_device *adev = drm_to_adev(ddev);
376
377 if (adev->flags & AMD_IS_APU)
378 return 0;
379
380 return attr->mode;
381}
382
383static const struct attribute_group amdgpu_board_attrs_group = {
384 .attrs = amdgpu_board_attrs,
385 .is_visible = amdgpu_board_attrs_is_visible
386};
387
388static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
389
390
391/**
392 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
393 *
394 * @dev: drm_device pointer
395 *
396 * Returns true if the device is a dGPU with ATPX power control,
397 * otherwise return false.
398 */
399bool amdgpu_device_supports_px(struct drm_device *dev)
400{
401 struct amdgpu_device *adev = drm_to_adev(dev);
402
403 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
404 return true;
405 return false;
406}
407
408/**
409 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
410 *
411 * @dev: drm_device pointer
412 *
413 * Returns true if the device is a dGPU with ACPI power control,
414 * otherwise return false.
415 */
416bool amdgpu_device_supports_boco(struct drm_device *dev)
417{
418 struct amdgpu_device *adev = drm_to_adev(dev);
419
420 if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
421 return false;
422
423 if (adev->has_pr3 ||
424 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
425 return true;
426 return false;
427}
428
429/**
430 * amdgpu_device_supports_baco - Does the device support BACO
431 *
432 * @dev: drm_device pointer
433 *
434 * Return:
435 * 1 if the device supporte BACO;
436 * 3 if the device support MACO (only works if BACO is supported)
437 * otherwise return 0.
438 */
439int amdgpu_device_supports_baco(struct drm_device *dev)
440{
441 struct amdgpu_device *adev = drm_to_adev(dev);
442
443 return amdgpu_asic_supports_baco(adev);
444}
445
446void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev)
447{
448 struct drm_device *dev;
449 int bamaco_support;
450
451 dev = adev_to_drm(adev);
452
453 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
454 bamaco_support = amdgpu_device_supports_baco(dev);
455
456 switch (amdgpu_runtime_pm) {
457 case 2:
458 if (bamaco_support & MACO_SUPPORT) {
459 adev->pm.rpm_mode = AMDGPU_RUNPM_BAMACO;
460 dev_info(adev->dev, "Forcing BAMACO for runtime pm\n");
461 } else if (bamaco_support == BACO_SUPPORT) {
462 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
463 dev_info(adev->dev, "Requested mode BAMACO not available,fallback to use BACO\n");
464 }
465 break;
466 case 1:
467 if (bamaco_support & BACO_SUPPORT) {
468 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
469 dev_info(adev->dev, "Forcing BACO for runtime pm\n");
470 }
471 break;
472 case -1:
473 case -2:
474 if (amdgpu_device_supports_px(dev)) { /* enable PX as runtime mode */
475 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
476 dev_info(adev->dev, "Using ATPX for runtime pm\n");
477 } else if (amdgpu_device_supports_boco(dev)) { /* enable boco as runtime mode */
478 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
479 dev_info(adev->dev, "Using BOCO for runtime pm\n");
480 } else {
481 if (!bamaco_support)
482 goto no_runtime_pm;
483
484 switch (adev->asic_type) {
485 case CHIP_VEGA20:
486 case CHIP_ARCTURUS:
487 /* BACO are not supported on vega20 and arctrus */
488 break;
489 case CHIP_VEGA10:
490 /* enable BACO as runpm mode if noretry=0 */
491 if (!adev->gmc.noretry)
492 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
493 break;
494 default:
495 /* enable BACO as runpm mode on CI+ */
496 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
497 break;
498 }
499
500 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
501 if (bamaco_support & MACO_SUPPORT) {
502 adev->pm.rpm_mode = AMDGPU_RUNPM_BAMACO;
503 dev_info(adev->dev, "Using BAMACO for runtime pm\n");
504 } else {
505 dev_info(adev->dev, "Using BACO for runtime pm\n");
506 }
507 }
508 }
509 break;
510 case 0:
511 dev_info(adev->dev, "runtime pm is manually disabled\n");
512 break;
513 default:
514 break;
515 }
516
517no_runtime_pm:
518 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
519 dev_info(adev->dev, "Runtime PM not available\n");
520}
521/**
522 * amdgpu_device_supports_smart_shift - Is the device dGPU with
523 * smart shift support
524 *
525 * @dev: drm_device pointer
526 *
527 * Returns true if the device is a dGPU with Smart Shift support,
528 * otherwise returns false.
529 */
530bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
531{
532 return (amdgpu_device_supports_boco(dev) &&
533 amdgpu_acpi_is_power_shift_control_supported());
534}
535
536/*
537 * VRAM access helper functions
538 */
539
540/**
541 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
542 *
543 * @adev: amdgpu_device pointer
544 * @pos: offset of the buffer in vram
545 * @buf: virtual address of the buffer in system memory
546 * @size: read/write size, sizeof(@buf) must > @size
547 * @write: true - write to vram, otherwise - read from vram
548 */
549void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
550 void *buf, size_t size, bool write)
551{
552 unsigned long flags;
553 uint32_t hi = ~0, tmp = 0;
554 uint32_t *data = buf;
555 uint64_t last;
556 int idx;
557
558 if (!drm_dev_enter(adev_to_drm(adev), &idx))
559 return;
560
561 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
562
563 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
564 for (last = pos + size; pos < last; pos += 4) {
565 tmp = pos >> 31;
566
567 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
568 if (tmp != hi) {
569 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
570 hi = tmp;
571 }
572 if (write)
573 WREG32_NO_KIQ(mmMM_DATA, *data++);
574 else
575 *data++ = RREG32_NO_KIQ(mmMM_DATA);
576 }
577
578 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
579 drm_dev_exit(idx);
580}
581
582/**
583 * amdgpu_device_aper_access - access vram by vram aperature
584 *
585 * @adev: amdgpu_device pointer
586 * @pos: offset of the buffer in vram
587 * @buf: virtual address of the buffer in system memory
588 * @size: read/write size, sizeof(@buf) must > @size
589 * @write: true - write to vram, otherwise - read from vram
590 *
591 * The return value means how many bytes have been transferred.
592 */
593size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
594 void *buf, size_t size, bool write)
595{
596#ifdef CONFIG_64BIT
597 void __iomem *addr;
598 size_t count = 0;
599 uint64_t last;
600
601 if (!adev->mman.aper_base_kaddr)
602 return 0;
603
604 last = min(pos + size, adev->gmc.visible_vram_size);
605 if (last > pos) {
606 addr = adev->mman.aper_base_kaddr + pos;
607 count = last - pos;
608
609 if (write) {
610 memcpy_toio(addr, buf, count);
611 /* Make sure HDP write cache flush happens without any reordering
612 * after the system memory contents are sent over PCIe device
613 */
614 mb();
615 amdgpu_device_flush_hdp(adev, NULL);
616 } else {
617 amdgpu_device_invalidate_hdp(adev, NULL);
618 /* Make sure HDP read cache is invalidated before issuing a read
619 * to the PCIe device
620 */
621 mb();
622 memcpy_fromio(buf, addr, count);
623 }
624
625 }
626
627 return count;
628#else
629 return 0;
630#endif
631}
632
633/**
634 * amdgpu_device_vram_access - read/write a buffer in vram
635 *
636 * @adev: amdgpu_device pointer
637 * @pos: offset of the buffer in vram
638 * @buf: virtual address of the buffer in system memory
639 * @size: read/write size, sizeof(@buf) must > @size
640 * @write: true - write to vram, otherwise - read from vram
641 */
642void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
643 void *buf, size_t size, bool write)
644{
645 size_t count;
646
647 /* try to using vram apreature to access vram first */
648 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
649 size -= count;
650 if (size) {
651 /* using MM to access rest vram */
652 pos += count;
653 buf += count;
654 amdgpu_device_mm_access(adev, pos, buf, size, write);
655 }
656}
657
658/*
659 * register access helper functions.
660 */
661
662/* Check if hw access should be skipped because of hotplug or device error */
663bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
664{
665 if (adev->no_hw_access)
666 return true;
667
668#ifdef CONFIG_LOCKDEP
669 /*
670 * This is a bit complicated to understand, so worth a comment. What we assert
671 * here is that the GPU reset is not running on another thread in parallel.
672 *
673 * For this we trylock the read side of the reset semaphore, if that succeeds
674 * we know that the reset is not running in paralell.
675 *
676 * If the trylock fails we assert that we are either already holding the read
677 * side of the lock or are the reset thread itself and hold the write side of
678 * the lock.
679 */
680 if (in_task()) {
681 if (down_read_trylock(&adev->reset_domain->sem))
682 up_read(&adev->reset_domain->sem);
683 else
684 lockdep_assert_held(&adev->reset_domain->sem);
685 }
686#endif
687 return false;
688}
689
690/**
691 * amdgpu_device_rreg - read a memory mapped IO or indirect register
692 *
693 * @adev: amdgpu_device pointer
694 * @reg: dword aligned register offset
695 * @acc_flags: access flags which require special behavior
696 *
697 * Returns the 32 bit value from the offset specified.
698 */
699uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
700 uint32_t reg, uint32_t acc_flags)
701{
702 uint32_t ret;
703
704 if (amdgpu_device_skip_hw_access(adev))
705 return 0;
706
707 if ((reg * 4) < adev->rmmio_size) {
708 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
709 amdgpu_sriov_runtime(adev) &&
710 down_read_trylock(&adev->reset_domain->sem)) {
711 ret = amdgpu_kiq_rreg(adev, reg, 0);
712 up_read(&adev->reset_domain->sem);
713 } else {
714 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
715 }
716 } else {
717 ret = adev->pcie_rreg(adev, reg * 4);
718 }
719
720 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
721
722 return ret;
723}
724
725/*
726 * MMIO register read with bytes helper functions
727 * @offset:bytes offset from MMIO start
728 */
729
730/**
731 * amdgpu_mm_rreg8 - read a memory mapped IO register
732 *
733 * @adev: amdgpu_device pointer
734 * @offset: byte aligned register offset
735 *
736 * Returns the 8 bit value from the offset specified.
737 */
738uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
739{
740 if (amdgpu_device_skip_hw_access(adev))
741 return 0;
742
743 if (offset < adev->rmmio_size)
744 return (readb(adev->rmmio + offset));
745 BUG();
746}
747
748
749/**
750 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
751 *
752 * @adev: amdgpu_device pointer
753 * @reg: dword aligned register offset
754 * @acc_flags: access flags which require special behavior
755 * @xcc_id: xcc accelerated compute core id
756 *
757 * Returns the 32 bit value from the offset specified.
758 */
759uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
760 uint32_t reg, uint32_t acc_flags,
761 uint32_t xcc_id)
762{
763 uint32_t ret, rlcg_flag;
764
765 if (amdgpu_device_skip_hw_access(adev))
766 return 0;
767
768 if ((reg * 4) < adev->rmmio_size) {
769 if (amdgpu_sriov_vf(adev) &&
770 !amdgpu_sriov_runtime(adev) &&
771 adev->gfx.rlc.rlcg_reg_access_supported &&
772 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
773 GC_HWIP, false,
774 &rlcg_flag)) {
775 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id));
776 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
777 amdgpu_sriov_runtime(adev) &&
778 down_read_trylock(&adev->reset_domain->sem)) {
779 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
780 up_read(&adev->reset_domain->sem);
781 } else {
782 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
783 }
784 } else {
785 ret = adev->pcie_rreg(adev, reg * 4);
786 }
787
788 return ret;
789}
790
791/*
792 * MMIO register write with bytes helper functions
793 * @offset:bytes offset from MMIO start
794 * @value: the value want to be written to the register
795 */
796
797/**
798 * amdgpu_mm_wreg8 - read a memory mapped IO register
799 *
800 * @adev: amdgpu_device pointer
801 * @offset: byte aligned register offset
802 * @value: 8 bit value to write
803 *
804 * Writes the value specified to the offset specified.
805 */
806void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
807{
808 if (amdgpu_device_skip_hw_access(adev))
809 return;
810
811 if (offset < adev->rmmio_size)
812 writeb(value, adev->rmmio + offset);
813 else
814 BUG();
815}
816
817/**
818 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
819 *
820 * @adev: amdgpu_device pointer
821 * @reg: dword aligned register offset
822 * @v: 32 bit value to write to the register
823 * @acc_flags: access flags which require special behavior
824 *
825 * Writes the value specified to the offset specified.
826 */
827void amdgpu_device_wreg(struct amdgpu_device *adev,
828 uint32_t reg, uint32_t v,
829 uint32_t acc_flags)
830{
831 if (amdgpu_device_skip_hw_access(adev))
832 return;
833
834 if ((reg * 4) < adev->rmmio_size) {
835 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
836 amdgpu_sriov_runtime(adev) &&
837 down_read_trylock(&adev->reset_domain->sem)) {
838 amdgpu_kiq_wreg(adev, reg, v, 0);
839 up_read(&adev->reset_domain->sem);
840 } else {
841 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
842 }
843 } else {
844 adev->pcie_wreg(adev, reg * 4, v);
845 }
846
847 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
848}
849
850/**
851 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
852 *
853 * @adev: amdgpu_device pointer
854 * @reg: mmio/rlc register
855 * @v: value to write
856 * @xcc_id: xcc accelerated compute core id
857 *
858 * this function is invoked only for the debugfs register access
859 */
860void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
861 uint32_t reg, uint32_t v,
862 uint32_t xcc_id)
863{
864 if (amdgpu_device_skip_hw_access(adev))
865 return;
866
867 if (amdgpu_sriov_fullaccess(adev) &&
868 adev->gfx.rlc.funcs &&
869 adev->gfx.rlc.funcs->is_rlcg_access_range) {
870 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
871 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
872 } else if ((reg * 4) >= adev->rmmio_size) {
873 adev->pcie_wreg(adev, reg * 4, v);
874 } else {
875 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
876 }
877}
878
879/**
880 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
881 *
882 * @adev: amdgpu_device pointer
883 * @reg: dword aligned register offset
884 * @v: 32 bit value to write to the register
885 * @acc_flags: access flags which require special behavior
886 * @xcc_id: xcc accelerated compute core id
887 *
888 * Writes the value specified to the offset specified.
889 */
890void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
891 uint32_t reg, uint32_t v,
892 uint32_t acc_flags, uint32_t xcc_id)
893{
894 uint32_t rlcg_flag;
895
896 if (amdgpu_device_skip_hw_access(adev))
897 return;
898
899 if ((reg * 4) < adev->rmmio_size) {
900 if (amdgpu_sriov_vf(adev) &&
901 !amdgpu_sriov_runtime(adev) &&
902 adev->gfx.rlc.rlcg_reg_access_supported &&
903 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
904 GC_HWIP, true,
905 &rlcg_flag)) {
906 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));
907 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
908 amdgpu_sriov_runtime(adev) &&
909 down_read_trylock(&adev->reset_domain->sem)) {
910 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
911 up_read(&adev->reset_domain->sem);
912 } else {
913 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
914 }
915 } else {
916 adev->pcie_wreg(adev, reg * 4, v);
917 }
918}
919
920/**
921 * amdgpu_device_indirect_rreg - read an indirect register
922 *
923 * @adev: amdgpu_device pointer
924 * @reg_addr: indirect register address to read from
925 *
926 * Returns the value of indirect register @reg_addr
927 */
928u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
929 u32 reg_addr)
930{
931 unsigned long flags, pcie_index, pcie_data;
932 void __iomem *pcie_index_offset;
933 void __iomem *pcie_data_offset;
934 u32 r;
935
936 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
937 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
938
939 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
940 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
941 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
942
943 writel(reg_addr, pcie_index_offset);
944 readl(pcie_index_offset);
945 r = readl(pcie_data_offset);
946 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
947
948 return r;
949}
950
951u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
952 u64 reg_addr)
953{
954 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
955 u32 r;
956 void __iomem *pcie_index_offset;
957 void __iomem *pcie_index_hi_offset;
958 void __iomem *pcie_data_offset;
959
960 if (unlikely(!adev->nbio.funcs)) {
961 pcie_index = AMDGPU_PCIE_INDEX_FALLBACK;
962 pcie_data = AMDGPU_PCIE_DATA_FALLBACK;
963 } else {
964 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
965 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
966 }
967
968 if (reg_addr >> 32) {
969 if (unlikely(!adev->nbio.funcs))
970 pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK;
971 else
972 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
973 } else {
974 pcie_index_hi = 0;
975 }
976
977 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
978 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
979 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
980 if (pcie_index_hi != 0)
981 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
982 pcie_index_hi * 4;
983
984 writel(reg_addr, pcie_index_offset);
985 readl(pcie_index_offset);
986 if (pcie_index_hi != 0) {
987 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
988 readl(pcie_index_hi_offset);
989 }
990 r = readl(pcie_data_offset);
991
992 /* clear the high bits */
993 if (pcie_index_hi != 0) {
994 writel(0, pcie_index_hi_offset);
995 readl(pcie_index_hi_offset);
996 }
997
998 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
999
1000 return r;
1001}
1002
1003/**
1004 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
1005 *
1006 * @adev: amdgpu_device pointer
1007 * @reg_addr: indirect register address to read from
1008 *
1009 * Returns the value of indirect register @reg_addr
1010 */
1011u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1012 u32 reg_addr)
1013{
1014 unsigned long flags, pcie_index, pcie_data;
1015 void __iomem *pcie_index_offset;
1016 void __iomem *pcie_data_offset;
1017 u64 r;
1018
1019 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1020 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1021
1022 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1023 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1024 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1025
1026 /* read low 32 bits */
1027 writel(reg_addr, pcie_index_offset);
1028 readl(pcie_index_offset);
1029 r = readl(pcie_data_offset);
1030 /* read high 32 bits */
1031 writel(reg_addr + 4, pcie_index_offset);
1032 readl(pcie_index_offset);
1033 r |= ((u64)readl(pcie_data_offset) << 32);
1034 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1035
1036 return r;
1037}
1038
1039u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1040 u64 reg_addr)
1041{
1042 unsigned long flags, pcie_index, pcie_data;
1043 unsigned long pcie_index_hi = 0;
1044 void __iomem *pcie_index_offset;
1045 void __iomem *pcie_index_hi_offset;
1046 void __iomem *pcie_data_offset;
1047 u64 r;
1048
1049 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1050 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1051 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1052 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1053
1054 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1055 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1056 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1057 if (pcie_index_hi != 0)
1058 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1059 pcie_index_hi * 4;
1060
1061 /* read low 32 bits */
1062 writel(reg_addr, pcie_index_offset);
1063 readl(pcie_index_offset);
1064 if (pcie_index_hi != 0) {
1065 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1066 readl(pcie_index_hi_offset);
1067 }
1068 r = readl(pcie_data_offset);
1069 /* read high 32 bits */
1070 writel(reg_addr + 4, pcie_index_offset);
1071 readl(pcie_index_offset);
1072 if (pcie_index_hi != 0) {
1073 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1074 readl(pcie_index_hi_offset);
1075 }
1076 r |= ((u64)readl(pcie_data_offset) << 32);
1077
1078 /* clear the high bits */
1079 if (pcie_index_hi != 0) {
1080 writel(0, pcie_index_hi_offset);
1081 readl(pcie_index_hi_offset);
1082 }
1083
1084 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1085
1086 return r;
1087}
1088
1089/**
1090 * amdgpu_device_indirect_wreg - write an indirect register address
1091 *
1092 * @adev: amdgpu_device pointer
1093 * @reg_addr: indirect register offset
1094 * @reg_data: indirect register data
1095 *
1096 */
1097void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1098 u32 reg_addr, u32 reg_data)
1099{
1100 unsigned long flags, pcie_index, pcie_data;
1101 void __iomem *pcie_index_offset;
1102 void __iomem *pcie_data_offset;
1103
1104 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1105 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1106
1107 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1108 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1109 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1110
1111 writel(reg_addr, pcie_index_offset);
1112 readl(pcie_index_offset);
1113 writel(reg_data, pcie_data_offset);
1114 readl(pcie_data_offset);
1115 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1116}
1117
1118void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1119 u64 reg_addr, u32 reg_data)
1120{
1121 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
1122 void __iomem *pcie_index_offset;
1123 void __iomem *pcie_index_hi_offset;
1124 void __iomem *pcie_data_offset;
1125
1126 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1127 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1128 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1129 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1130 else
1131 pcie_index_hi = 0;
1132
1133 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1134 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1135 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1136 if (pcie_index_hi != 0)
1137 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1138 pcie_index_hi * 4;
1139
1140 writel(reg_addr, pcie_index_offset);
1141 readl(pcie_index_offset);
1142 if (pcie_index_hi != 0) {
1143 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1144 readl(pcie_index_hi_offset);
1145 }
1146 writel(reg_data, pcie_data_offset);
1147 readl(pcie_data_offset);
1148
1149 /* clear the high bits */
1150 if (pcie_index_hi != 0) {
1151 writel(0, pcie_index_hi_offset);
1152 readl(pcie_index_hi_offset);
1153 }
1154
1155 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1156}
1157
1158/**
1159 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
1160 *
1161 * @adev: amdgpu_device pointer
1162 * @reg_addr: indirect register offset
1163 * @reg_data: indirect register data
1164 *
1165 */
1166void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1167 u32 reg_addr, u64 reg_data)
1168{
1169 unsigned long flags, pcie_index, pcie_data;
1170 void __iomem *pcie_index_offset;
1171 void __iomem *pcie_data_offset;
1172
1173 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1174 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1175
1176 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1177 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1178 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1179
1180 /* write low 32 bits */
1181 writel(reg_addr, pcie_index_offset);
1182 readl(pcie_index_offset);
1183 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1184 readl(pcie_data_offset);
1185 /* write high 32 bits */
1186 writel(reg_addr + 4, pcie_index_offset);
1187 readl(pcie_index_offset);
1188 writel((u32)(reg_data >> 32), pcie_data_offset);
1189 readl(pcie_data_offset);
1190 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1191}
1192
1193void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1194 u64 reg_addr, u64 reg_data)
1195{
1196 unsigned long flags, pcie_index, pcie_data;
1197 unsigned long pcie_index_hi = 0;
1198 void __iomem *pcie_index_offset;
1199 void __iomem *pcie_index_hi_offset;
1200 void __iomem *pcie_data_offset;
1201
1202 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1203 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1204 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1205 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1206
1207 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1208 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1209 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1210 if (pcie_index_hi != 0)
1211 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1212 pcie_index_hi * 4;
1213
1214 /* write low 32 bits */
1215 writel(reg_addr, pcie_index_offset);
1216 readl(pcie_index_offset);
1217 if (pcie_index_hi != 0) {
1218 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1219 readl(pcie_index_hi_offset);
1220 }
1221 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1222 readl(pcie_data_offset);
1223 /* write high 32 bits */
1224 writel(reg_addr + 4, pcie_index_offset);
1225 readl(pcie_index_offset);
1226 if (pcie_index_hi != 0) {
1227 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1228 readl(pcie_index_hi_offset);
1229 }
1230 writel((u32)(reg_data >> 32), pcie_data_offset);
1231 readl(pcie_data_offset);
1232
1233 /* clear the high bits */
1234 if (pcie_index_hi != 0) {
1235 writel(0, pcie_index_hi_offset);
1236 readl(pcie_index_hi_offset);
1237 }
1238
1239 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1240}
1241
1242/**
1243 * amdgpu_device_get_rev_id - query device rev_id
1244 *
1245 * @adev: amdgpu_device pointer
1246 *
1247 * Return device rev_id
1248 */
1249u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1250{
1251 return adev->nbio.funcs->get_rev_id(adev);
1252}
1253
1254/**
1255 * amdgpu_invalid_rreg - dummy reg read function
1256 *
1257 * @adev: amdgpu_device pointer
1258 * @reg: offset of register
1259 *
1260 * Dummy register read function. Used for register blocks
1261 * that certain asics don't have (all asics).
1262 * Returns the value in the register.
1263 */
1264static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1265{
1266 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1267 BUG();
1268 return 0;
1269}
1270
1271static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1272{
1273 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1274 BUG();
1275 return 0;
1276}
1277
1278/**
1279 * amdgpu_invalid_wreg - dummy reg write function
1280 *
1281 * @adev: amdgpu_device pointer
1282 * @reg: offset of register
1283 * @v: value to write to the register
1284 *
1285 * Dummy register read function. Used for register blocks
1286 * that certain asics don't have (all asics).
1287 */
1288static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1289{
1290 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1291 reg, v);
1292 BUG();
1293}
1294
1295static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1296{
1297 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1298 reg, v);
1299 BUG();
1300}
1301
1302/**
1303 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1304 *
1305 * @adev: amdgpu_device pointer
1306 * @reg: offset of register
1307 *
1308 * Dummy register read function. Used for register blocks
1309 * that certain asics don't have (all asics).
1310 * Returns the value in the register.
1311 */
1312static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1313{
1314 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1315 BUG();
1316 return 0;
1317}
1318
1319static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1320{
1321 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1322 BUG();
1323 return 0;
1324}
1325
1326/**
1327 * amdgpu_invalid_wreg64 - dummy reg write function
1328 *
1329 * @adev: amdgpu_device pointer
1330 * @reg: offset of register
1331 * @v: value to write to the register
1332 *
1333 * Dummy register read function. Used for register blocks
1334 * that certain asics don't have (all asics).
1335 */
1336static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1337{
1338 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1339 reg, v);
1340 BUG();
1341}
1342
1343static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1344{
1345 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1346 reg, v);
1347 BUG();
1348}
1349
1350/**
1351 * amdgpu_block_invalid_rreg - dummy reg read function
1352 *
1353 * @adev: amdgpu_device pointer
1354 * @block: offset of instance
1355 * @reg: offset of register
1356 *
1357 * Dummy register read function. Used for register blocks
1358 * that certain asics don't have (all asics).
1359 * Returns the value in the register.
1360 */
1361static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1362 uint32_t block, uint32_t reg)
1363{
1364 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1365 reg, block);
1366 BUG();
1367 return 0;
1368}
1369
1370/**
1371 * amdgpu_block_invalid_wreg - dummy reg write function
1372 *
1373 * @adev: amdgpu_device pointer
1374 * @block: offset of instance
1375 * @reg: offset of register
1376 * @v: value to write to the register
1377 *
1378 * Dummy register read function. Used for register blocks
1379 * that certain asics don't have (all asics).
1380 */
1381static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1382 uint32_t block,
1383 uint32_t reg, uint32_t v)
1384{
1385 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1386 reg, block, v);
1387 BUG();
1388}
1389
1390/**
1391 * amdgpu_device_asic_init - Wrapper for atom asic_init
1392 *
1393 * @adev: amdgpu_device pointer
1394 *
1395 * Does any asic specific work and then calls atom asic init.
1396 */
1397static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1398{
1399 int ret;
1400
1401 amdgpu_asic_pre_asic_init(adev);
1402
1403 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1404 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
1405 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1406 amdgpu_psp_wait_for_bootloader(adev);
1407 ret = amdgpu_atomfirmware_asic_init(adev, true);
1408 return ret;
1409 } else {
1410 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1411 }
1412
1413 return 0;
1414}
1415
1416/**
1417 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1418 *
1419 * @adev: amdgpu_device pointer
1420 *
1421 * Allocates a scratch page of VRAM for use by various things in the
1422 * driver.
1423 */
1424static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1425{
1426 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1427 AMDGPU_GEM_DOMAIN_VRAM |
1428 AMDGPU_GEM_DOMAIN_GTT,
1429 &adev->mem_scratch.robj,
1430 &adev->mem_scratch.gpu_addr,
1431 (void **)&adev->mem_scratch.ptr);
1432}
1433
1434/**
1435 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1436 *
1437 * @adev: amdgpu_device pointer
1438 *
1439 * Frees the VRAM scratch page.
1440 */
1441static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1442{
1443 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1444}
1445
1446/**
1447 * amdgpu_device_program_register_sequence - program an array of registers.
1448 *
1449 * @adev: amdgpu_device pointer
1450 * @registers: pointer to the register array
1451 * @array_size: size of the register array
1452 *
1453 * Programs an array or registers with and or masks.
1454 * This is a helper for setting golden registers.
1455 */
1456void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1457 const u32 *registers,
1458 const u32 array_size)
1459{
1460 u32 tmp, reg, and_mask, or_mask;
1461 int i;
1462
1463 if (array_size % 3)
1464 return;
1465
1466 for (i = 0; i < array_size; i += 3) {
1467 reg = registers[i + 0];
1468 and_mask = registers[i + 1];
1469 or_mask = registers[i + 2];
1470
1471 if (and_mask == 0xffffffff) {
1472 tmp = or_mask;
1473 } else {
1474 tmp = RREG32(reg);
1475 tmp &= ~and_mask;
1476 if (adev->family >= AMDGPU_FAMILY_AI)
1477 tmp |= (or_mask & and_mask);
1478 else
1479 tmp |= or_mask;
1480 }
1481 WREG32(reg, tmp);
1482 }
1483}
1484
1485/**
1486 * amdgpu_device_pci_config_reset - reset the GPU
1487 *
1488 * @adev: amdgpu_device pointer
1489 *
1490 * Resets the GPU using the pci config reset sequence.
1491 * Only applicable to asics prior to vega10.
1492 */
1493void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1494{
1495 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1496}
1497
1498/**
1499 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1500 *
1501 * @adev: amdgpu_device pointer
1502 *
1503 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1504 */
1505int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1506{
1507 return pci_reset_function(adev->pdev);
1508}
1509
1510/*
1511 * amdgpu_device_wb_*()
1512 * Writeback is the method by which the GPU updates special pages in memory
1513 * with the status of certain GPU events (fences, ring pointers,etc.).
1514 */
1515
1516/**
1517 * amdgpu_device_wb_fini - Disable Writeback and free memory
1518 *
1519 * @adev: amdgpu_device pointer
1520 *
1521 * Disables Writeback and frees the Writeback memory (all asics).
1522 * Used at driver shutdown.
1523 */
1524static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1525{
1526 if (adev->wb.wb_obj) {
1527 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1528 &adev->wb.gpu_addr,
1529 (void **)&adev->wb.wb);
1530 adev->wb.wb_obj = NULL;
1531 }
1532}
1533
1534/**
1535 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1536 *
1537 * @adev: amdgpu_device pointer
1538 *
1539 * Initializes writeback and allocates writeback memory (all asics).
1540 * Used at driver startup.
1541 * Returns 0 on success or an -error on failure.
1542 */
1543static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1544{
1545 int r;
1546
1547 if (adev->wb.wb_obj == NULL) {
1548 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1549 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1551 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1552 (void **)&adev->wb.wb);
1553 if (r) {
1554 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1555 return r;
1556 }
1557
1558 adev->wb.num_wb = AMDGPU_MAX_WB;
1559 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1560
1561 /* clear wb memory */
1562 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1563 }
1564
1565 return 0;
1566}
1567
1568/**
1569 * amdgpu_device_wb_get - Allocate a wb entry
1570 *
1571 * @adev: amdgpu_device pointer
1572 * @wb: wb index
1573 *
1574 * Allocate a wb slot for use by the driver (all asics).
1575 * Returns 0 on success or -EINVAL on failure.
1576 */
1577int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1578{
1579 unsigned long flags, offset;
1580
1581 spin_lock_irqsave(&adev->wb.lock, flags);
1582 offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1583 if (offset < adev->wb.num_wb) {
1584 __set_bit(offset, adev->wb.used);
1585 spin_unlock_irqrestore(&adev->wb.lock, flags);
1586 *wb = offset << 3; /* convert to dw offset */
1587 return 0;
1588 } else {
1589 spin_unlock_irqrestore(&adev->wb.lock, flags);
1590 return -EINVAL;
1591 }
1592}
1593
1594/**
1595 * amdgpu_device_wb_free - Free a wb entry
1596 *
1597 * @adev: amdgpu_device pointer
1598 * @wb: wb index
1599 *
1600 * Free a wb slot allocated for use by the driver (all asics)
1601 */
1602void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1603{
1604 unsigned long flags;
1605
1606 wb >>= 3;
1607 spin_lock_irqsave(&adev->wb.lock, flags);
1608 if (wb < adev->wb.num_wb)
1609 __clear_bit(wb, adev->wb.used);
1610 spin_unlock_irqrestore(&adev->wb.lock, flags);
1611}
1612
1613/**
1614 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1615 *
1616 * @adev: amdgpu_device pointer
1617 *
1618 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1619 * to fail, but if any of the BARs is not accessible after the size we abort
1620 * driver loading by returning -ENODEV.
1621 */
1622int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1623{
1624 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1625 struct pci_bus *root;
1626 struct resource *res;
1627 unsigned int i;
1628 u16 cmd;
1629 int r;
1630
1631 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1632 return 0;
1633
1634 /* Bypass for VF */
1635 if (amdgpu_sriov_vf(adev))
1636 return 0;
1637
1638 /* resizing on Dell G5 SE platforms causes problems with runtime pm */
1639 if ((amdgpu_runtime_pm != 0) &&
1640 adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
1641 adev->pdev->device == 0x731f &&
1642 adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
1643 return 0;
1644
1645 /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
1646 if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
1647 DRM_WARN("System can't access extended configuration space, please check!!\n");
1648
1649 /* skip if the bios has already enabled large BAR */
1650 if (adev->gmc.real_vram_size &&
1651 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1652 return 0;
1653
1654 /* Check if the root BUS has 64bit memory resources */
1655 root = adev->pdev->bus;
1656 while (root->parent)
1657 root = root->parent;
1658
1659 pci_bus_for_each_resource(root, res, i) {
1660 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1661 res->start > 0x100000000ull)
1662 break;
1663 }
1664
1665 /* Trying to resize is pointless without a root hub window above 4GB */
1666 if (!res)
1667 return 0;
1668
1669 /* Limit the BAR size to what is available */
1670 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1671 rbar_size);
1672
1673 /* Disable memory decoding while we change the BAR addresses and size */
1674 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1675 pci_write_config_word(adev->pdev, PCI_COMMAND,
1676 cmd & ~PCI_COMMAND_MEMORY);
1677
1678 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1679 amdgpu_doorbell_fini(adev);
1680 if (adev->asic_type >= CHIP_BONAIRE)
1681 pci_release_resource(adev->pdev, 2);
1682
1683 pci_release_resource(adev->pdev, 0);
1684
1685 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1686 if (r == -ENOSPC)
1687 DRM_INFO("Not enough PCI address space for a large BAR.");
1688 else if (r && r != -ENOTSUPP)
1689 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1690
1691 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1692
1693 /* When the doorbell or fb BAR isn't available we have no chance of
1694 * using the device.
1695 */
1696 r = amdgpu_doorbell_init(adev);
1697 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1698 return -ENODEV;
1699
1700 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1701
1702 return 0;
1703}
1704
1705static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1706{
1707 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1708 return false;
1709
1710 return true;
1711}
1712
1713/*
1714 * GPU helpers function.
1715 */
1716/**
1717 * amdgpu_device_need_post - check if the hw need post or not
1718 *
1719 * @adev: amdgpu_device pointer
1720 *
1721 * Check if the asic has been initialized (all asics) at driver startup
1722 * or post is needed if hw reset is performed.
1723 * Returns true if need or false if not.
1724 */
1725bool amdgpu_device_need_post(struct amdgpu_device *adev)
1726{
1727 uint32_t reg;
1728
1729 if (amdgpu_sriov_vf(adev))
1730 return false;
1731
1732 if (!amdgpu_device_read_bios(adev))
1733 return false;
1734
1735 if (amdgpu_passthrough(adev)) {
1736 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1737 * some old smc fw still need driver do vPost otherwise gpu hang, while
1738 * those smc fw version above 22.15 doesn't have this flaw, so we force
1739 * vpost executed for smc version below 22.15
1740 */
1741 if (adev->asic_type == CHIP_FIJI) {
1742 int err;
1743 uint32_t fw_ver;
1744
1745 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1746 /* force vPost if error occured */
1747 if (err)
1748 return true;
1749
1750 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1751 release_firmware(adev->pm.fw);
1752 if (fw_ver < 0x00160e00)
1753 return true;
1754 }
1755 }
1756
1757 /* Don't post if we need to reset whole hive on init */
1758 if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI)
1759 return false;
1760
1761 if (adev->has_hw_reset) {
1762 adev->has_hw_reset = false;
1763 return true;
1764 }
1765
1766 /* bios scratch used on CIK+ */
1767 if (adev->asic_type >= CHIP_BONAIRE)
1768 return amdgpu_atombios_scratch_need_asic_init(adev);
1769
1770 /* check MEM_SIZE for older asics */
1771 reg = amdgpu_asic_get_config_memsize(adev);
1772
1773 if ((reg != 0) && (reg != 0xffffffff))
1774 return false;
1775
1776 return true;
1777}
1778
1779/*
1780 * Check whether seamless boot is supported.
1781 *
1782 * So far we only support seamless boot on DCE 3.0 or later.
1783 * If users report that it works on older ASICS as well, we may
1784 * loosen this.
1785 */
1786bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1787{
1788 switch (amdgpu_seamless) {
1789 case -1:
1790 break;
1791 case 1:
1792 return true;
1793 case 0:
1794 return false;
1795 default:
1796 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1797 amdgpu_seamless);
1798 return false;
1799 }
1800
1801 if (!(adev->flags & AMD_IS_APU))
1802 return false;
1803
1804 if (adev->mman.keep_stolen_vga_memory)
1805 return false;
1806
1807 return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0);
1808}
1809
1810/*
1811 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1812 * don't support dynamic speed switching. Until we have confirmation from Intel
1813 * that a specific host supports it, it's safer that we keep it disabled for all.
1814 *
1815 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1816 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1817 */
1818static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)
1819{
1820#if IS_ENABLED(CONFIG_X86)
1821 struct cpuinfo_x86 *c = &cpu_data(0);
1822
1823 /* eGPU change speeds based on USB4 fabric conditions */
1824 if (dev_is_removable(adev->dev))
1825 return true;
1826
1827 if (c->x86_vendor == X86_VENDOR_INTEL)
1828 return false;
1829#endif
1830 return true;
1831}
1832
1833/**
1834 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1835 *
1836 * @adev: amdgpu_device pointer
1837 *
1838 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1839 * be set for this device.
1840 *
1841 * Returns true if it should be used or false if not.
1842 */
1843bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1844{
1845 switch (amdgpu_aspm) {
1846 case -1:
1847 break;
1848 case 0:
1849 return false;
1850 case 1:
1851 return true;
1852 default:
1853 return false;
1854 }
1855 if (adev->flags & AMD_IS_APU)
1856 return false;
1857 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1858 return false;
1859 return pcie_aspm_enabled(adev->pdev);
1860}
1861
1862/* if we get transitioned to only one device, take VGA back */
1863/**
1864 * amdgpu_device_vga_set_decode - enable/disable vga decode
1865 *
1866 * @pdev: PCI device pointer
1867 * @state: enable/disable vga decode
1868 *
1869 * Enable/disable vga decode (all asics).
1870 * Returns VGA resource flags.
1871 */
1872static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1873 bool state)
1874{
1875 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1876
1877 amdgpu_asic_set_vga_state(adev, state);
1878 if (state)
1879 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1880 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1881 else
1882 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1883}
1884
1885/**
1886 * amdgpu_device_check_block_size - validate the vm block size
1887 *
1888 * @adev: amdgpu_device pointer
1889 *
1890 * Validates the vm block size specified via module parameter.
1891 * The vm block size defines number of bits in page table versus page directory,
1892 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1893 * page table and the remaining bits are in the page directory.
1894 */
1895static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1896{
1897 /* defines number of bits in page table versus page directory,
1898 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1899 * page table and the remaining bits are in the page directory
1900 */
1901 if (amdgpu_vm_block_size == -1)
1902 return;
1903
1904 if (amdgpu_vm_block_size < 9) {
1905 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1906 amdgpu_vm_block_size);
1907 amdgpu_vm_block_size = -1;
1908 }
1909}
1910
1911/**
1912 * amdgpu_device_check_vm_size - validate the vm size
1913 *
1914 * @adev: amdgpu_device pointer
1915 *
1916 * Validates the vm size in GB specified via module parameter.
1917 * The VM size is the size of the GPU virtual memory space in GB.
1918 */
1919static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1920{
1921 /* no need to check the default value */
1922 if (amdgpu_vm_size == -1)
1923 return;
1924
1925 if (amdgpu_vm_size < 1) {
1926 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1927 amdgpu_vm_size);
1928 amdgpu_vm_size = -1;
1929 }
1930}
1931
1932static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1933{
1934 struct sysinfo si;
1935 bool is_os_64 = (sizeof(void *) == 8);
1936 uint64_t total_memory;
1937 uint64_t dram_size_seven_GB = 0x1B8000000;
1938 uint64_t dram_size_three_GB = 0xB8000000;
1939
1940 if (amdgpu_smu_memory_pool_size == 0)
1941 return;
1942
1943 if (!is_os_64) {
1944 DRM_WARN("Not 64-bit OS, feature not supported\n");
1945 goto def_value;
1946 }
1947 si_meminfo(&si);
1948 total_memory = (uint64_t)si.totalram * si.mem_unit;
1949
1950 if ((amdgpu_smu_memory_pool_size == 1) ||
1951 (amdgpu_smu_memory_pool_size == 2)) {
1952 if (total_memory < dram_size_three_GB)
1953 goto def_value1;
1954 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1955 (amdgpu_smu_memory_pool_size == 8)) {
1956 if (total_memory < dram_size_seven_GB)
1957 goto def_value1;
1958 } else {
1959 DRM_WARN("Smu memory pool size not supported\n");
1960 goto def_value;
1961 }
1962 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1963
1964 return;
1965
1966def_value1:
1967 DRM_WARN("No enough system memory\n");
1968def_value:
1969 adev->pm.smu_prv_buffer_size = 0;
1970}
1971
1972static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1973{
1974 if (!(adev->flags & AMD_IS_APU) ||
1975 adev->asic_type < CHIP_RAVEN)
1976 return 0;
1977
1978 switch (adev->asic_type) {
1979 case CHIP_RAVEN:
1980 if (adev->pdev->device == 0x15dd)
1981 adev->apu_flags |= AMD_APU_IS_RAVEN;
1982 if (adev->pdev->device == 0x15d8)
1983 adev->apu_flags |= AMD_APU_IS_PICASSO;
1984 break;
1985 case CHIP_RENOIR:
1986 if ((adev->pdev->device == 0x1636) ||
1987 (adev->pdev->device == 0x164c))
1988 adev->apu_flags |= AMD_APU_IS_RENOIR;
1989 else
1990 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1991 break;
1992 case CHIP_VANGOGH:
1993 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1994 break;
1995 case CHIP_YELLOW_CARP:
1996 break;
1997 case CHIP_CYAN_SKILLFISH:
1998 if ((adev->pdev->device == 0x13FE) ||
1999 (adev->pdev->device == 0x143F))
2000 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
2001 break;
2002 default:
2003 break;
2004 }
2005
2006 return 0;
2007}
2008
2009/**
2010 * amdgpu_device_check_arguments - validate module params
2011 *
2012 * @adev: amdgpu_device pointer
2013 *
2014 * Validates certain module parameters and updates
2015 * the associated values used by the driver (all asics).
2016 */
2017static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
2018{
2019 int i;
2020
2021 if (amdgpu_sched_jobs < 4) {
2022 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
2023 amdgpu_sched_jobs);
2024 amdgpu_sched_jobs = 4;
2025 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
2026 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
2027 amdgpu_sched_jobs);
2028 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
2029 }
2030
2031 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
2032 /* gart size must be greater or equal to 32M */
2033 dev_warn(adev->dev, "gart size (%d) too small\n",
2034 amdgpu_gart_size);
2035 amdgpu_gart_size = -1;
2036 }
2037
2038 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
2039 /* gtt size must be greater or equal to 32M */
2040 dev_warn(adev->dev, "gtt size (%d) too small\n",
2041 amdgpu_gtt_size);
2042 amdgpu_gtt_size = -1;
2043 }
2044
2045 /* valid range is between 4 and 9 inclusive */
2046 if (amdgpu_vm_fragment_size != -1 &&
2047 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
2048 dev_warn(adev->dev, "valid range is between 4 and 9\n");
2049 amdgpu_vm_fragment_size = -1;
2050 }
2051
2052 if (amdgpu_sched_hw_submission < 2) {
2053 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
2054 amdgpu_sched_hw_submission);
2055 amdgpu_sched_hw_submission = 2;
2056 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
2057 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
2058 amdgpu_sched_hw_submission);
2059 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
2060 }
2061
2062 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
2063 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
2064 amdgpu_reset_method = -1;
2065 }
2066
2067 amdgpu_device_check_smu_prv_buffer_size(adev);
2068
2069 amdgpu_device_check_vm_size(adev);
2070
2071 amdgpu_device_check_block_size(adev);
2072
2073 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
2074
2075 for (i = 0; i < MAX_XCP; i++)
2076 adev->enforce_isolation[i] = !!enforce_isolation;
2077
2078 return 0;
2079}
2080
2081/**
2082 * amdgpu_switcheroo_set_state - set switcheroo state
2083 *
2084 * @pdev: pci dev pointer
2085 * @state: vga_switcheroo state
2086 *
2087 * Callback for the switcheroo driver. Suspends or resumes
2088 * the asics before or after it is powered up using ACPI methods.
2089 */
2090static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
2091 enum vga_switcheroo_state state)
2092{
2093 struct drm_device *dev = pci_get_drvdata(pdev);
2094 int r;
2095
2096 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
2097 return;
2098
2099 if (state == VGA_SWITCHEROO_ON) {
2100 pr_info("switched on\n");
2101 /* don't suspend or resume card normally */
2102 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2103
2104 pci_set_power_state(pdev, PCI_D0);
2105 amdgpu_device_load_pci_state(pdev);
2106 r = pci_enable_device(pdev);
2107 if (r)
2108 DRM_WARN("pci_enable_device failed (%d)\n", r);
2109 amdgpu_device_resume(dev, true);
2110
2111 dev->switch_power_state = DRM_SWITCH_POWER_ON;
2112 } else {
2113 pr_info("switched off\n");
2114 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2115 amdgpu_device_prepare(dev);
2116 amdgpu_device_suspend(dev, true);
2117 amdgpu_device_cache_pci_state(pdev);
2118 /* Shut down the device */
2119 pci_disable_device(pdev);
2120 pci_set_power_state(pdev, PCI_D3cold);
2121 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
2122 }
2123}
2124
2125/**
2126 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
2127 *
2128 * @pdev: pci dev pointer
2129 *
2130 * Callback for the switcheroo driver. Check of the switcheroo
2131 * state can be changed.
2132 * Returns true if the state can be changed, false if not.
2133 */
2134static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
2135{
2136 struct drm_device *dev = pci_get_drvdata(pdev);
2137
2138 /*
2139 * FIXME: open_count is protected by drm_global_mutex but that would lead to
2140 * locking inversion with the driver load path. And the access here is
2141 * completely racy anyway. So don't bother with locking for now.
2142 */
2143 return atomic_read(&dev->open_count) == 0;
2144}
2145
2146static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
2147 .set_gpu_state = amdgpu_switcheroo_set_state,
2148 .reprobe = NULL,
2149 .can_switch = amdgpu_switcheroo_can_switch,
2150};
2151
2152/**
2153 * amdgpu_device_ip_set_clockgating_state - set the CG state
2154 *
2155 * @dev: amdgpu_device pointer
2156 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2157 * @state: clockgating state (gate or ungate)
2158 *
2159 * Sets the requested clockgating state for all instances of
2160 * the hardware IP specified.
2161 * Returns the error code from the last instance.
2162 */
2163int amdgpu_device_ip_set_clockgating_state(void *dev,
2164 enum amd_ip_block_type block_type,
2165 enum amd_clockgating_state state)
2166{
2167 struct amdgpu_device *adev = dev;
2168 int i, r = 0;
2169
2170 for (i = 0; i < adev->num_ip_blocks; i++) {
2171 if (!adev->ip_blocks[i].status.valid)
2172 continue;
2173 if (adev->ip_blocks[i].version->type != block_type)
2174 continue;
2175 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
2176 continue;
2177 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
2178 (void *)adev, state);
2179 if (r)
2180 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
2181 adev->ip_blocks[i].version->funcs->name, r);
2182 }
2183 return r;
2184}
2185
2186/**
2187 * amdgpu_device_ip_set_powergating_state - set the PG state
2188 *
2189 * @dev: amdgpu_device pointer
2190 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2191 * @state: powergating state (gate or ungate)
2192 *
2193 * Sets the requested powergating state for all instances of
2194 * the hardware IP specified.
2195 * Returns the error code from the last instance.
2196 */
2197int amdgpu_device_ip_set_powergating_state(void *dev,
2198 enum amd_ip_block_type block_type,
2199 enum amd_powergating_state state)
2200{
2201 struct amdgpu_device *adev = dev;
2202 int i, r = 0;
2203
2204 for (i = 0; i < adev->num_ip_blocks; i++) {
2205 if (!adev->ip_blocks[i].status.valid)
2206 continue;
2207 if (adev->ip_blocks[i].version->type != block_type)
2208 continue;
2209 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
2210 continue;
2211 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
2212 (void *)adev, state);
2213 if (r)
2214 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
2215 adev->ip_blocks[i].version->funcs->name, r);
2216 }
2217 return r;
2218}
2219
2220/**
2221 * amdgpu_device_ip_get_clockgating_state - get the CG state
2222 *
2223 * @adev: amdgpu_device pointer
2224 * @flags: clockgating feature flags
2225 *
2226 * Walks the list of IPs on the device and updates the clockgating
2227 * flags for each IP.
2228 * Updates @flags with the feature flags for each hardware IP where
2229 * clockgating is enabled.
2230 */
2231void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
2232 u64 *flags)
2233{
2234 int i;
2235
2236 for (i = 0; i < adev->num_ip_blocks; i++) {
2237 if (!adev->ip_blocks[i].status.valid)
2238 continue;
2239 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
2240 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
2241 }
2242}
2243
2244/**
2245 * amdgpu_device_ip_wait_for_idle - wait for idle
2246 *
2247 * @adev: amdgpu_device pointer
2248 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2249 *
2250 * Waits for the request hardware IP to be idle.
2251 * Returns 0 for success or a negative error code on failure.
2252 */
2253int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
2254 enum amd_ip_block_type block_type)
2255{
2256 int i, r;
2257
2258 for (i = 0; i < adev->num_ip_blocks; i++) {
2259 if (!adev->ip_blocks[i].status.valid)
2260 continue;
2261 if (adev->ip_blocks[i].version->type == block_type) {
2262 if (adev->ip_blocks[i].version->funcs->wait_for_idle) {
2263 r = adev->ip_blocks[i].version->funcs->wait_for_idle(
2264 &adev->ip_blocks[i]);
2265 if (r)
2266 return r;
2267 }
2268 break;
2269 }
2270 }
2271 return 0;
2272
2273}
2274
2275/**
2276 * amdgpu_device_ip_is_valid - is the hardware IP enabled
2277 *
2278 * @adev: amdgpu_device pointer
2279 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2280 *
2281 * Check if the hardware IP is enable or not.
2282 * Returns true if it the IP is enable, false if not.
2283 */
2284bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
2285 enum amd_ip_block_type block_type)
2286{
2287 int i;
2288
2289 for (i = 0; i < adev->num_ip_blocks; i++) {
2290 if (adev->ip_blocks[i].version->type == block_type)
2291 return adev->ip_blocks[i].status.valid;
2292 }
2293 return false;
2294
2295}
2296
2297/**
2298 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2299 *
2300 * @adev: amdgpu_device pointer
2301 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2302 *
2303 * Returns a pointer to the hardware IP block structure
2304 * if it exists for the asic, otherwise NULL.
2305 */
2306struct amdgpu_ip_block *
2307amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2308 enum amd_ip_block_type type)
2309{
2310 int i;
2311
2312 for (i = 0; i < adev->num_ip_blocks; i++)
2313 if (adev->ip_blocks[i].version->type == type)
2314 return &adev->ip_blocks[i];
2315
2316 return NULL;
2317}
2318
2319/**
2320 * amdgpu_device_ip_block_version_cmp
2321 *
2322 * @adev: amdgpu_device pointer
2323 * @type: enum amd_ip_block_type
2324 * @major: major version
2325 * @minor: minor version
2326 *
2327 * return 0 if equal or greater
2328 * return 1 if smaller or the ip_block doesn't exist
2329 */
2330int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2331 enum amd_ip_block_type type,
2332 u32 major, u32 minor)
2333{
2334 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2335
2336 if (ip_block && ((ip_block->version->major > major) ||
2337 ((ip_block->version->major == major) &&
2338 (ip_block->version->minor >= minor))))
2339 return 0;
2340
2341 return 1;
2342}
2343
2344/**
2345 * amdgpu_device_ip_block_add
2346 *
2347 * @adev: amdgpu_device pointer
2348 * @ip_block_version: pointer to the IP to add
2349 *
2350 * Adds the IP block driver information to the collection of IPs
2351 * on the asic.
2352 */
2353int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2354 const struct amdgpu_ip_block_version *ip_block_version)
2355{
2356 if (!ip_block_version)
2357 return -EINVAL;
2358
2359 switch (ip_block_version->type) {
2360 case AMD_IP_BLOCK_TYPE_VCN:
2361 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2362 return 0;
2363 break;
2364 case AMD_IP_BLOCK_TYPE_JPEG:
2365 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2366 return 0;
2367 break;
2368 default:
2369 break;
2370 }
2371
2372 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2373 ip_block_version->funcs->name);
2374
2375 adev->ip_blocks[adev->num_ip_blocks].adev = adev;
2376
2377 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2378
2379 return 0;
2380}
2381
2382/**
2383 * amdgpu_device_enable_virtual_display - enable virtual display feature
2384 *
2385 * @adev: amdgpu_device pointer
2386 *
2387 * Enabled the virtual display feature if the user has enabled it via
2388 * the module parameter virtual_display. This feature provides a virtual
2389 * display hardware on headless boards or in virtualized environments.
2390 * This function parses and validates the configuration string specified by
2391 * the user and configues the virtual display configuration (number of
2392 * virtual connectors, crtcs, etc.) specified.
2393 */
2394static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2395{
2396 adev->enable_virtual_display = false;
2397
2398 if (amdgpu_virtual_display) {
2399 const char *pci_address_name = pci_name(adev->pdev);
2400 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2401
2402 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2403 pciaddstr_tmp = pciaddstr;
2404 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2405 pciaddname = strsep(&pciaddname_tmp, ",");
2406 if (!strcmp("all", pciaddname)
2407 || !strcmp(pci_address_name, pciaddname)) {
2408 long num_crtc;
2409 int res = -1;
2410
2411 adev->enable_virtual_display = true;
2412
2413 if (pciaddname_tmp)
2414 res = kstrtol(pciaddname_tmp, 10,
2415 &num_crtc);
2416
2417 if (!res) {
2418 if (num_crtc < 1)
2419 num_crtc = 1;
2420 if (num_crtc > 6)
2421 num_crtc = 6;
2422 adev->mode_info.num_crtc = num_crtc;
2423 } else {
2424 adev->mode_info.num_crtc = 1;
2425 }
2426 break;
2427 }
2428 }
2429
2430 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2431 amdgpu_virtual_display, pci_address_name,
2432 adev->enable_virtual_display, adev->mode_info.num_crtc);
2433
2434 kfree(pciaddstr);
2435 }
2436}
2437
2438void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2439{
2440 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2441 adev->mode_info.num_crtc = 1;
2442 adev->enable_virtual_display = true;
2443 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2444 adev->enable_virtual_display, adev->mode_info.num_crtc);
2445 }
2446}
2447
2448/**
2449 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2450 *
2451 * @adev: amdgpu_device pointer
2452 *
2453 * Parses the asic configuration parameters specified in the gpu info
2454 * firmware and makes them availale to the driver for use in configuring
2455 * the asic.
2456 * Returns 0 on success, -EINVAL on failure.
2457 */
2458static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2459{
2460 const char *chip_name;
2461 int err;
2462 const struct gpu_info_firmware_header_v1_0 *hdr;
2463
2464 adev->firmware.gpu_info_fw = NULL;
2465
2466 if (adev->mman.discovery_bin)
2467 return 0;
2468
2469 switch (adev->asic_type) {
2470 default:
2471 return 0;
2472 case CHIP_VEGA10:
2473 chip_name = "vega10";
2474 break;
2475 case CHIP_VEGA12:
2476 chip_name = "vega12";
2477 break;
2478 case CHIP_RAVEN:
2479 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2480 chip_name = "raven2";
2481 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2482 chip_name = "picasso";
2483 else
2484 chip_name = "raven";
2485 break;
2486 case CHIP_ARCTURUS:
2487 chip_name = "arcturus";
2488 break;
2489 case CHIP_NAVI12:
2490 chip_name = "navi12";
2491 break;
2492 }
2493
2494 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw,
2495 "amdgpu/%s_gpu_info.bin", chip_name);
2496 if (err) {
2497 dev_err(adev->dev,
2498 "Failed to get gpu_info firmware \"%s_gpu_info.bin\"\n",
2499 chip_name);
2500 goto out;
2501 }
2502
2503 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2504 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2505
2506 switch (hdr->version_major) {
2507 case 1:
2508 {
2509 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2510 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2511 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2512
2513 /*
2514 * Should be droped when DAL no longer needs it.
2515 */
2516 if (adev->asic_type == CHIP_NAVI12)
2517 goto parse_soc_bounding_box;
2518
2519 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2520 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2521 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2522 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2523 adev->gfx.config.max_texture_channel_caches =
2524 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2525 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2526 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2527 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2528 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2529 adev->gfx.config.double_offchip_lds_buf =
2530 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2531 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2532 adev->gfx.cu_info.max_waves_per_simd =
2533 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2534 adev->gfx.cu_info.max_scratch_slots_per_cu =
2535 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2536 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2537 if (hdr->version_minor >= 1) {
2538 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2539 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2540 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2541 adev->gfx.config.num_sc_per_sh =
2542 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2543 adev->gfx.config.num_packer_per_sc =
2544 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2545 }
2546
2547parse_soc_bounding_box:
2548 /*
2549 * soc bounding box info is not integrated in disocovery table,
2550 * we always need to parse it from gpu info firmware if needed.
2551 */
2552 if (hdr->version_minor == 2) {
2553 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2554 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2555 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2556 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2557 }
2558 break;
2559 }
2560 default:
2561 dev_err(adev->dev,
2562 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2563 err = -EINVAL;
2564 goto out;
2565 }
2566out:
2567 return err;
2568}
2569
2570/**
2571 * amdgpu_device_ip_early_init - run early init for hardware IPs
2572 *
2573 * @adev: amdgpu_device pointer
2574 *
2575 * Early initialization pass for hardware IPs. The hardware IPs that make
2576 * up each asic are discovered each IP's early_init callback is run. This
2577 * is the first stage in initializing the asic.
2578 * Returns 0 on success, negative error code on failure.
2579 */
2580static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2581{
2582 struct amdgpu_ip_block *ip_block;
2583 struct pci_dev *parent;
2584 int i, r;
2585 bool total;
2586
2587 amdgpu_device_enable_virtual_display(adev);
2588
2589 if (amdgpu_sriov_vf(adev)) {
2590 r = amdgpu_virt_request_full_gpu(adev, true);
2591 if (r)
2592 return r;
2593 }
2594
2595 switch (adev->asic_type) {
2596#ifdef CONFIG_DRM_AMDGPU_SI
2597 case CHIP_VERDE:
2598 case CHIP_TAHITI:
2599 case CHIP_PITCAIRN:
2600 case CHIP_OLAND:
2601 case CHIP_HAINAN:
2602 adev->family = AMDGPU_FAMILY_SI;
2603 r = si_set_ip_blocks(adev);
2604 if (r)
2605 return r;
2606 break;
2607#endif
2608#ifdef CONFIG_DRM_AMDGPU_CIK
2609 case CHIP_BONAIRE:
2610 case CHIP_HAWAII:
2611 case CHIP_KAVERI:
2612 case CHIP_KABINI:
2613 case CHIP_MULLINS:
2614 if (adev->flags & AMD_IS_APU)
2615 adev->family = AMDGPU_FAMILY_KV;
2616 else
2617 adev->family = AMDGPU_FAMILY_CI;
2618
2619 r = cik_set_ip_blocks(adev);
2620 if (r)
2621 return r;
2622 break;
2623#endif
2624 case CHIP_TOPAZ:
2625 case CHIP_TONGA:
2626 case CHIP_FIJI:
2627 case CHIP_POLARIS10:
2628 case CHIP_POLARIS11:
2629 case CHIP_POLARIS12:
2630 case CHIP_VEGAM:
2631 case CHIP_CARRIZO:
2632 case CHIP_STONEY:
2633 if (adev->flags & AMD_IS_APU)
2634 adev->family = AMDGPU_FAMILY_CZ;
2635 else
2636 adev->family = AMDGPU_FAMILY_VI;
2637
2638 r = vi_set_ip_blocks(adev);
2639 if (r)
2640 return r;
2641 break;
2642 default:
2643 r = amdgpu_discovery_set_ip_blocks(adev);
2644 if (r)
2645 return r;
2646 break;
2647 }
2648
2649 if (amdgpu_has_atpx() &&
2650 (amdgpu_is_atpx_hybrid() ||
2651 amdgpu_has_atpx_dgpu_power_cntl()) &&
2652 ((adev->flags & AMD_IS_APU) == 0) &&
2653 !dev_is_removable(&adev->pdev->dev))
2654 adev->flags |= AMD_IS_PX;
2655
2656 if (!(adev->flags & AMD_IS_APU)) {
2657 parent = pcie_find_root_port(adev->pdev);
2658 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2659 }
2660
2661
2662 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2663 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2664 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2665 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2666 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2667 if (!amdgpu_device_pcie_dynamic_switching_supported(adev))
2668 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2669
2670 total = true;
2671 for (i = 0; i < adev->num_ip_blocks; i++) {
2672 ip_block = &adev->ip_blocks[i];
2673
2674 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2675 DRM_WARN("disabled ip block: %d <%s>\n",
2676 i, adev->ip_blocks[i].version->funcs->name);
2677 adev->ip_blocks[i].status.valid = false;
2678 } else if (ip_block->version->funcs->early_init) {
2679 r = ip_block->version->funcs->early_init(ip_block);
2680 if (r == -ENOENT) {
2681 adev->ip_blocks[i].status.valid = false;
2682 } else if (r) {
2683 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2684 adev->ip_blocks[i].version->funcs->name, r);
2685 total = false;
2686 } else {
2687 adev->ip_blocks[i].status.valid = true;
2688 }
2689 } else {
2690 adev->ip_blocks[i].status.valid = true;
2691 }
2692 /* get the vbios after the asic_funcs are set up */
2693 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2694 r = amdgpu_device_parse_gpu_info_fw(adev);
2695 if (r)
2696 return r;
2697
2698 /* Read BIOS */
2699 if (amdgpu_device_read_bios(adev)) {
2700 if (!amdgpu_get_bios(adev))
2701 return -EINVAL;
2702
2703 r = amdgpu_atombios_init(adev);
2704 if (r) {
2705 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2706 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2707 return r;
2708 }
2709 }
2710
2711 /*get pf2vf msg info at it's earliest time*/
2712 if (amdgpu_sriov_vf(adev))
2713 amdgpu_virt_init_data_exchange(adev);
2714
2715 }
2716 }
2717 if (!total)
2718 return -ENODEV;
2719
2720 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
2721 if (ip_block->status.valid != false)
2722 amdgpu_amdkfd_device_probe(adev);
2723
2724 adev->cg_flags &= amdgpu_cg_mask;
2725 adev->pg_flags &= amdgpu_pg_mask;
2726
2727 return 0;
2728}
2729
2730static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2731{
2732 int i, r;
2733
2734 for (i = 0; i < adev->num_ip_blocks; i++) {
2735 if (!adev->ip_blocks[i].status.sw)
2736 continue;
2737 if (adev->ip_blocks[i].status.hw)
2738 continue;
2739 if (!amdgpu_ip_member_of_hwini(
2740 adev, adev->ip_blocks[i].version->type))
2741 continue;
2742 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2743 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2744 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2745 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2746 if (r) {
2747 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2748 adev->ip_blocks[i].version->funcs->name, r);
2749 return r;
2750 }
2751 adev->ip_blocks[i].status.hw = true;
2752 }
2753 }
2754
2755 return 0;
2756}
2757
2758static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2759{
2760 int i, r;
2761
2762 for (i = 0; i < adev->num_ip_blocks; i++) {
2763 if (!adev->ip_blocks[i].status.sw)
2764 continue;
2765 if (adev->ip_blocks[i].status.hw)
2766 continue;
2767 if (!amdgpu_ip_member_of_hwini(
2768 adev, adev->ip_blocks[i].version->type))
2769 continue;
2770 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2771 if (r) {
2772 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2773 adev->ip_blocks[i].version->funcs->name, r);
2774 return r;
2775 }
2776 adev->ip_blocks[i].status.hw = true;
2777 }
2778
2779 return 0;
2780}
2781
2782static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2783{
2784 int r = 0;
2785 int i;
2786 uint32_t smu_version;
2787
2788 if (adev->asic_type >= CHIP_VEGA10) {
2789 for (i = 0; i < adev->num_ip_blocks; i++) {
2790 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2791 continue;
2792
2793 if (!amdgpu_ip_member_of_hwini(adev,
2794 AMD_IP_BLOCK_TYPE_PSP))
2795 break;
2796
2797 if (!adev->ip_blocks[i].status.sw)
2798 continue;
2799
2800 /* no need to do the fw loading again if already done*/
2801 if (adev->ip_blocks[i].status.hw == true)
2802 break;
2803
2804 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2805 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
2806 if (r)
2807 return r;
2808 } else {
2809 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2810 if (r) {
2811 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2812 adev->ip_blocks[i].version->funcs->name, r);
2813 return r;
2814 }
2815 adev->ip_blocks[i].status.hw = true;
2816 }
2817 break;
2818 }
2819 }
2820
2821 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2822 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2823
2824 return r;
2825}
2826
2827static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2828{
2829 long timeout;
2830 int r, i;
2831
2832 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2833 struct amdgpu_ring *ring = adev->rings[i];
2834
2835 /* No need to setup the GPU scheduler for rings that don't need it */
2836 if (!ring || ring->no_scheduler)
2837 continue;
2838
2839 switch (ring->funcs->type) {
2840 case AMDGPU_RING_TYPE_GFX:
2841 timeout = adev->gfx_timeout;
2842 break;
2843 case AMDGPU_RING_TYPE_COMPUTE:
2844 timeout = adev->compute_timeout;
2845 break;
2846 case AMDGPU_RING_TYPE_SDMA:
2847 timeout = adev->sdma_timeout;
2848 break;
2849 default:
2850 timeout = adev->video_timeout;
2851 break;
2852 }
2853
2854 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL,
2855 DRM_SCHED_PRIORITY_COUNT,
2856 ring->num_hw_submission, 0,
2857 timeout, adev->reset_domain->wq,
2858 ring->sched_score, ring->name,
2859 adev->dev);
2860 if (r) {
2861 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2862 ring->name);
2863 return r;
2864 }
2865 r = amdgpu_uvd_entity_init(adev, ring);
2866 if (r) {
2867 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2868 ring->name);
2869 return r;
2870 }
2871 r = amdgpu_vce_entity_init(adev, ring);
2872 if (r) {
2873 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2874 ring->name);
2875 return r;
2876 }
2877 }
2878
2879 amdgpu_xcp_update_partition_sched_list(adev);
2880
2881 return 0;
2882}
2883
2884
2885/**
2886 * amdgpu_device_ip_init - run init for hardware IPs
2887 *
2888 * @adev: amdgpu_device pointer
2889 *
2890 * Main initialization pass for hardware IPs. The list of all the hardware
2891 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2892 * are run. sw_init initializes the software state associated with each IP
2893 * and hw_init initializes the hardware associated with each IP.
2894 * Returns 0 on success, negative error code on failure.
2895 */
2896static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2897{
2898 bool init_badpage;
2899 int i, r;
2900
2901 r = amdgpu_ras_init(adev);
2902 if (r)
2903 return r;
2904
2905 for (i = 0; i < adev->num_ip_blocks; i++) {
2906 if (!adev->ip_blocks[i].status.valid)
2907 continue;
2908 if (adev->ip_blocks[i].version->funcs->sw_init) {
2909 r = adev->ip_blocks[i].version->funcs->sw_init(&adev->ip_blocks[i]);
2910 if (r) {
2911 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2912 adev->ip_blocks[i].version->funcs->name, r);
2913 goto init_failed;
2914 }
2915 }
2916 adev->ip_blocks[i].status.sw = true;
2917
2918 if (!amdgpu_ip_member_of_hwini(
2919 adev, adev->ip_blocks[i].version->type))
2920 continue;
2921
2922 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2923 /* need to do common hw init early so everything is set up for gmc */
2924 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2925 if (r) {
2926 DRM_ERROR("hw_init %d failed %d\n", i, r);
2927 goto init_failed;
2928 }
2929 adev->ip_blocks[i].status.hw = true;
2930 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2931 /* need to do gmc hw init early so we can allocate gpu mem */
2932 /* Try to reserve bad pages early */
2933 if (amdgpu_sriov_vf(adev))
2934 amdgpu_virt_exchange_data(adev);
2935
2936 r = amdgpu_device_mem_scratch_init(adev);
2937 if (r) {
2938 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2939 goto init_failed;
2940 }
2941 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2942 if (r) {
2943 DRM_ERROR("hw_init %d failed %d\n", i, r);
2944 goto init_failed;
2945 }
2946 r = amdgpu_device_wb_init(adev);
2947 if (r) {
2948 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2949 goto init_failed;
2950 }
2951 adev->ip_blocks[i].status.hw = true;
2952
2953 /* right after GMC hw init, we create CSA */
2954 if (adev->gfx.mcbp) {
2955 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2956 AMDGPU_GEM_DOMAIN_VRAM |
2957 AMDGPU_GEM_DOMAIN_GTT,
2958 AMDGPU_CSA_SIZE);
2959 if (r) {
2960 DRM_ERROR("allocate CSA failed %d\n", r);
2961 goto init_failed;
2962 }
2963 }
2964
2965 r = amdgpu_seq64_init(adev);
2966 if (r) {
2967 DRM_ERROR("allocate seq64 failed %d\n", r);
2968 goto init_failed;
2969 }
2970 }
2971 }
2972
2973 if (amdgpu_sriov_vf(adev))
2974 amdgpu_virt_init_data_exchange(adev);
2975
2976 r = amdgpu_ib_pool_init(adev);
2977 if (r) {
2978 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2979 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2980 goto init_failed;
2981 }
2982
2983 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2984 if (r)
2985 goto init_failed;
2986
2987 r = amdgpu_device_ip_hw_init_phase1(adev);
2988 if (r)
2989 goto init_failed;
2990
2991 r = amdgpu_device_fw_loading(adev);
2992 if (r)
2993 goto init_failed;
2994
2995 r = amdgpu_device_ip_hw_init_phase2(adev);
2996 if (r)
2997 goto init_failed;
2998
2999 /*
3000 * retired pages will be loaded from eeprom and reserved here,
3001 * it should be called after amdgpu_device_ip_hw_init_phase2 since
3002 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
3003 * for I2C communication which only true at this point.
3004 *
3005 * amdgpu_ras_recovery_init may fail, but the upper only cares the
3006 * failure from bad gpu situation and stop amdgpu init process
3007 * accordingly. For other failed cases, it will still release all
3008 * the resource and print error message, rather than returning one
3009 * negative value to upper level.
3010 *
3011 * Note: theoretically, this should be called before all vram allocations
3012 * to protect retired page from abusing
3013 */
3014 init_badpage = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI);
3015 r = amdgpu_ras_recovery_init(adev, init_badpage);
3016 if (r)
3017 goto init_failed;
3018
3019 /**
3020 * In case of XGMI grab extra reference for reset domain for this device
3021 */
3022 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3023 if (amdgpu_xgmi_add_device(adev) == 0) {
3024 if (!amdgpu_sriov_vf(adev)) {
3025 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3026
3027 if (WARN_ON(!hive)) {
3028 r = -ENOENT;
3029 goto init_failed;
3030 }
3031
3032 if (!hive->reset_domain ||
3033 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
3034 r = -ENOENT;
3035 amdgpu_put_xgmi_hive(hive);
3036 goto init_failed;
3037 }
3038
3039 /* Drop the early temporary reset domain we created for device */
3040 amdgpu_reset_put_reset_domain(adev->reset_domain);
3041 adev->reset_domain = hive->reset_domain;
3042 amdgpu_put_xgmi_hive(hive);
3043 }
3044 }
3045 }
3046
3047 r = amdgpu_device_init_schedulers(adev);
3048 if (r)
3049 goto init_failed;
3050
3051 if (adev->mman.buffer_funcs_ring->sched.ready)
3052 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3053
3054 /* Don't init kfd if whole hive need to be reset during init */
3055 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
3056 kgd2kfd_init_zone_device(adev);
3057 amdgpu_amdkfd_device_init(adev);
3058 }
3059
3060 amdgpu_fru_get_product_info(adev);
3061
3062init_failed:
3063
3064 return r;
3065}
3066
3067/**
3068 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
3069 *
3070 * @adev: amdgpu_device pointer
3071 *
3072 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
3073 * this function before a GPU reset. If the value is retained after a
3074 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
3075 */
3076static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
3077{
3078 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
3079}
3080
3081/**
3082 * amdgpu_device_check_vram_lost - check if vram is valid
3083 *
3084 * @adev: amdgpu_device pointer
3085 *
3086 * Checks the reset magic value written to the gart pointer in VRAM.
3087 * The driver calls this after a GPU reset to see if the contents of
3088 * VRAM is lost or now.
3089 * returns true if vram is lost, false if not.
3090 */
3091static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
3092{
3093 if (memcmp(adev->gart.ptr, adev->reset_magic,
3094 AMDGPU_RESET_MAGIC_NUM))
3095 return true;
3096
3097 if (!amdgpu_in_reset(adev))
3098 return false;
3099
3100 /*
3101 * For all ASICs with baco/mode1 reset, the VRAM is
3102 * always assumed to be lost.
3103 */
3104 switch (amdgpu_asic_reset_method(adev)) {
3105 case AMD_RESET_METHOD_BACO:
3106 case AMD_RESET_METHOD_MODE1:
3107 return true;
3108 default:
3109 return false;
3110 }
3111}
3112
3113/**
3114 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
3115 *
3116 * @adev: amdgpu_device pointer
3117 * @state: clockgating state (gate or ungate)
3118 *
3119 * The list of all the hardware IPs that make up the asic is walked and the
3120 * set_clockgating_state callbacks are run.
3121 * Late initialization pass enabling clockgating for hardware IPs.
3122 * Fini or suspend, pass disabling clockgating for hardware IPs.
3123 * Returns 0 on success, negative error code on failure.
3124 */
3125
3126int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
3127 enum amd_clockgating_state state)
3128{
3129 int i, j, r;
3130
3131 if (amdgpu_emu_mode == 1)
3132 return 0;
3133
3134 for (j = 0; j < adev->num_ip_blocks; j++) {
3135 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
3136 if (!adev->ip_blocks[i].status.late_initialized)
3137 continue;
3138 /* skip CG for GFX, SDMA on S0ix */
3139 if (adev->in_s0ix &&
3140 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3141 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3142 continue;
3143 /* skip CG for VCE/UVD, it's handled specially */
3144 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
3145 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
3146 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
3147 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
3148 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
3149 /* enable clockgating to save power */
3150 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
3151 state);
3152 if (r) {
3153 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
3154 adev->ip_blocks[i].version->funcs->name, r);
3155 return r;
3156 }
3157 }
3158 }
3159
3160 return 0;
3161}
3162
3163int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
3164 enum amd_powergating_state state)
3165{
3166 int i, j, r;
3167
3168 if (amdgpu_emu_mode == 1)
3169 return 0;
3170
3171 for (j = 0; j < adev->num_ip_blocks; j++) {
3172 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
3173 if (!adev->ip_blocks[i].status.late_initialized)
3174 continue;
3175 /* skip PG for GFX, SDMA on S0ix */
3176 if (adev->in_s0ix &&
3177 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3178 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3179 continue;
3180 /* skip CG for VCE/UVD, it's handled specially */
3181 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
3182 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
3183 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
3184 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
3185 adev->ip_blocks[i].version->funcs->set_powergating_state) {
3186 /* enable powergating to save power */
3187 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
3188 state);
3189 if (r) {
3190 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
3191 adev->ip_blocks[i].version->funcs->name, r);
3192 return r;
3193 }
3194 }
3195 }
3196 return 0;
3197}
3198
3199static int amdgpu_device_enable_mgpu_fan_boost(void)
3200{
3201 struct amdgpu_gpu_instance *gpu_ins;
3202 struct amdgpu_device *adev;
3203 int i, ret = 0;
3204
3205 mutex_lock(&mgpu_info.mutex);
3206
3207 /*
3208 * MGPU fan boost feature should be enabled
3209 * only when there are two or more dGPUs in
3210 * the system
3211 */
3212 if (mgpu_info.num_dgpu < 2)
3213 goto out;
3214
3215 for (i = 0; i < mgpu_info.num_dgpu; i++) {
3216 gpu_ins = &(mgpu_info.gpu_ins[i]);
3217 adev = gpu_ins->adev;
3218 if (!(adev->flags & AMD_IS_APU) &&
3219 !gpu_ins->mgpu_fan_enabled) {
3220 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
3221 if (ret)
3222 break;
3223
3224 gpu_ins->mgpu_fan_enabled = 1;
3225 }
3226 }
3227
3228out:
3229 mutex_unlock(&mgpu_info.mutex);
3230
3231 return ret;
3232}
3233
3234/**
3235 * amdgpu_device_ip_late_init - run late init for hardware IPs
3236 *
3237 * @adev: amdgpu_device pointer
3238 *
3239 * Late initialization pass for hardware IPs. The list of all the hardware
3240 * IPs that make up the asic is walked and the late_init callbacks are run.
3241 * late_init covers any special initialization that an IP requires
3242 * after all of the have been initialized or something that needs to happen
3243 * late in the init process.
3244 * Returns 0 on success, negative error code on failure.
3245 */
3246static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
3247{
3248 struct amdgpu_gpu_instance *gpu_instance;
3249 int i = 0, r;
3250
3251 for (i = 0; i < adev->num_ip_blocks; i++) {
3252 if (!adev->ip_blocks[i].status.hw)
3253 continue;
3254 if (adev->ip_blocks[i].version->funcs->late_init) {
3255 r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]);
3256 if (r) {
3257 DRM_ERROR("late_init of IP block <%s> failed %d\n",
3258 adev->ip_blocks[i].version->funcs->name, r);
3259 return r;
3260 }
3261 }
3262 adev->ip_blocks[i].status.late_initialized = true;
3263 }
3264
3265 r = amdgpu_ras_late_init(adev);
3266 if (r) {
3267 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
3268 return r;
3269 }
3270
3271 if (!amdgpu_reset_in_recovery(adev))
3272 amdgpu_ras_set_error_query_ready(adev, true);
3273
3274 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
3275 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
3276
3277 amdgpu_device_fill_reset_magic(adev);
3278
3279 r = amdgpu_device_enable_mgpu_fan_boost();
3280 if (r)
3281 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
3282
3283 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
3284 if (amdgpu_passthrough(adev) &&
3285 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
3286 adev->asic_type == CHIP_ALDEBARAN))
3287 amdgpu_dpm_handle_passthrough_sbr(adev, true);
3288
3289 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3290 mutex_lock(&mgpu_info.mutex);
3291
3292 /*
3293 * Reset device p-state to low as this was booted with high.
3294 *
3295 * This should be performed only after all devices from the same
3296 * hive get initialized.
3297 *
3298 * However, it's unknown how many device in the hive in advance.
3299 * As this is counted one by one during devices initializations.
3300 *
3301 * So, we wait for all XGMI interlinked devices initialized.
3302 * This may bring some delays as those devices may come from
3303 * different hives. But that should be OK.
3304 */
3305 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3306 for (i = 0; i < mgpu_info.num_gpu; i++) {
3307 gpu_instance = &(mgpu_info.gpu_ins[i]);
3308 if (gpu_instance->adev->flags & AMD_IS_APU)
3309 continue;
3310
3311 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3312 AMDGPU_XGMI_PSTATE_MIN);
3313 if (r) {
3314 DRM_ERROR("pstate setting failed (%d).\n", r);
3315 break;
3316 }
3317 }
3318 }
3319
3320 mutex_unlock(&mgpu_info.mutex);
3321 }
3322
3323 return 0;
3324}
3325
3326static void amdgpu_ip_block_hw_fini(struct amdgpu_ip_block *ip_block)
3327{
3328 int r;
3329
3330 if (!ip_block->version->funcs->hw_fini) {
3331 DRM_ERROR("hw_fini of IP block <%s> not defined\n",
3332 ip_block->version->funcs->name);
3333 } else {
3334 r = ip_block->version->funcs->hw_fini(ip_block);
3335 /* XXX handle errors */
3336 if (r) {
3337 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3338 ip_block->version->funcs->name, r);
3339 }
3340 }
3341
3342 ip_block->status.hw = false;
3343}
3344
3345/**
3346 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3347 *
3348 * @adev: amdgpu_device pointer
3349 *
3350 * For ASICs need to disable SMC first
3351 */
3352static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3353{
3354 int i;
3355
3356 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3357 return;
3358
3359 for (i = 0; i < adev->num_ip_blocks; i++) {
3360 if (!adev->ip_blocks[i].status.hw)
3361 continue;
3362 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3363 amdgpu_ip_block_hw_fini(&adev->ip_blocks[i]);
3364 break;
3365 }
3366 }
3367}
3368
3369static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3370{
3371 int i, r;
3372
3373 for (i = 0; i < adev->num_ip_blocks; i++) {
3374 if (!adev->ip_blocks[i].version->funcs->early_fini)
3375 continue;
3376
3377 r = adev->ip_blocks[i].version->funcs->early_fini(&adev->ip_blocks[i]);
3378 if (r) {
3379 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3380 adev->ip_blocks[i].version->funcs->name, r);
3381 }
3382 }
3383
3384 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3385 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3386
3387 amdgpu_amdkfd_suspend(adev, false);
3388
3389 /* Workaroud for ASICs need to disable SMC first */
3390 amdgpu_device_smu_fini_early(adev);
3391
3392 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3393 if (!adev->ip_blocks[i].status.hw)
3394 continue;
3395
3396 amdgpu_ip_block_hw_fini(&adev->ip_blocks[i]);
3397 }
3398
3399 if (amdgpu_sriov_vf(adev)) {
3400 if (amdgpu_virt_release_full_gpu(adev, false))
3401 DRM_ERROR("failed to release exclusive mode on fini\n");
3402 }
3403
3404 return 0;
3405}
3406
3407/**
3408 * amdgpu_device_ip_fini - run fini for hardware IPs
3409 *
3410 * @adev: amdgpu_device pointer
3411 *
3412 * Main teardown pass for hardware IPs. The list of all the hardware
3413 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3414 * are run. hw_fini tears down the hardware associated with each IP
3415 * and sw_fini tears down any software state associated with each IP.
3416 * Returns 0 on success, negative error code on failure.
3417 */
3418static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3419{
3420 int i, r;
3421
3422 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3423 amdgpu_virt_release_ras_err_handler_data(adev);
3424
3425 if (adev->gmc.xgmi.num_physical_nodes > 1)
3426 amdgpu_xgmi_remove_device(adev);
3427
3428 amdgpu_amdkfd_device_fini_sw(adev);
3429
3430 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3431 if (!adev->ip_blocks[i].status.sw)
3432 continue;
3433
3434 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3435 amdgpu_ucode_free_bo(adev);
3436 amdgpu_free_static_csa(&adev->virt.csa_obj);
3437 amdgpu_device_wb_fini(adev);
3438 amdgpu_device_mem_scratch_fini(adev);
3439 amdgpu_ib_pool_fini(adev);
3440 amdgpu_seq64_fini(adev);
3441 }
3442 if (adev->ip_blocks[i].version->funcs->sw_fini) {
3443 r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]);
3444 /* XXX handle errors */
3445 if (r) {
3446 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3447 adev->ip_blocks[i].version->funcs->name, r);
3448 }
3449 }
3450 adev->ip_blocks[i].status.sw = false;
3451 adev->ip_blocks[i].status.valid = false;
3452 }
3453
3454 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3455 if (!adev->ip_blocks[i].status.late_initialized)
3456 continue;
3457 if (adev->ip_blocks[i].version->funcs->late_fini)
3458 adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]);
3459 adev->ip_blocks[i].status.late_initialized = false;
3460 }
3461
3462 amdgpu_ras_fini(adev);
3463
3464 return 0;
3465}
3466
3467/**
3468 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3469 *
3470 * @work: work_struct.
3471 */
3472static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3473{
3474 struct amdgpu_device *adev =
3475 container_of(work, struct amdgpu_device, delayed_init_work.work);
3476 int r;
3477
3478 r = amdgpu_ib_ring_tests(adev);
3479 if (r)
3480 DRM_ERROR("ib ring test failed (%d).\n", r);
3481}
3482
3483static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3484{
3485 struct amdgpu_device *adev =
3486 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3487
3488 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3489 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3490
3491 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3492 adev->gfx.gfx_off_state = true;
3493}
3494
3495/**
3496 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3497 *
3498 * @adev: amdgpu_device pointer
3499 *
3500 * Main suspend function for hardware IPs. The list of all the hardware
3501 * IPs that make up the asic is walked, clockgating is disabled and the
3502 * suspend callbacks are run. suspend puts the hardware and software state
3503 * in each IP into a state suitable for suspend.
3504 * Returns 0 on success, negative error code on failure.
3505 */
3506static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3507{
3508 int i, r;
3509
3510 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3511 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3512
3513 /*
3514 * Per PMFW team's suggestion, driver needs to handle gfxoff
3515 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3516 * scenario. Add the missing df cstate disablement here.
3517 */
3518 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3519 dev_warn(adev->dev, "Failed to disallow df cstate");
3520
3521 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3522 if (!adev->ip_blocks[i].status.valid)
3523 continue;
3524
3525 /* displays are handled separately */
3526 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3527 continue;
3528
3529 /* XXX handle errors */
3530 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
3531 if (r)
3532 return r;
3533 }
3534
3535 return 0;
3536}
3537
3538/**
3539 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3540 *
3541 * @adev: amdgpu_device pointer
3542 *
3543 * Main suspend function for hardware IPs. The list of all the hardware
3544 * IPs that make up the asic is walked, clockgating is disabled and the
3545 * suspend callbacks are run. suspend puts the hardware and software state
3546 * in each IP into a state suitable for suspend.
3547 * Returns 0 on success, negative error code on failure.
3548 */
3549static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3550{
3551 int i, r;
3552
3553 if (adev->in_s0ix)
3554 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3555
3556 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3557 if (!adev->ip_blocks[i].status.valid)
3558 continue;
3559 /* displays are handled in phase1 */
3560 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3561 continue;
3562 /* PSP lost connection when err_event_athub occurs */
3563 if (amdgpu_ras_intr_triggered() &&
3564 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3565 adev->ip_blocks[i].status.hw = false;
3566 continue;
3567 }
3568
3569 /* skip unnecessary suspend if we do not initialize them yet */
3570 if (!amdgpu_ip_member_of_hwini(
3571 adev, adev->ip_blocks[i].version->type))
3572 continue;
3573
3574 /* skip suspend of gfx/mes and psp for S0ix
3575 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3576 * like at runtime. PSP is also part of the always on hardware
3577 * so no need to suspend it.
3578 */
3579 if (adev->in_s0ix &&
3580 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3581 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3582 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3583 continue;
3584
3585 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3586 if (adev->in_s0ix &&
3587 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3588 IP_VERSION(5, 0, 0)) &&
3589 (adev->ip_blocks[i].version->type ==
3590 AMD_IP_BLOCK_TYPE_SDMA))
3591 continue;
3592
3593 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3594 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3595 * from this location and RLC Autoload automatically also gets loaded
3596 * from here based on PMFW -> PSP message during re-init sequence.
3597 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3598 * the TMR and reload FWs again for IMU enabled APU ASICs.
3599 */
3600 if (amdgpu_in_reset(adev) &&
3601 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3602 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3603 continue;
3604
3605 /* XXX handle errors */
3606 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
3607 adev->ip_blocks[i].status.hw = false;
3608
3609 /* handle putting the SMC in the appropriate state */
3610 if (!amdgpu_sriov_vf(adev)) {
3611 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3612 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3613 if (r) {
3614 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3615 adev->mp1_state, r);
3616 return r;
3617 }
3618 }
3619 }
3620 }
3621
3622 return 0;
3623}
3624
3625/**
3626 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3627 *
3628 * @adev: amdgpu_device pointer
3629 *
3630 * Main suspend function for hardware IPs. The list of all the hardware
3631 * IPs that make up the asic is walked, clockgating is disabled and the
3632 * suspend callbacks are run. suspend puts the hardware and software state
3633 * in each IP into a state suitable for suspend.
3634 * Returns 0 on success, negative error code on failure.
3635 */
3636int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3637{
3638 int r;
3639
3640 if (amdgpu_sriov_vf(adev)) {
3641 amdgpu_virt_fini_data_exchange(adev);
3642 amdgpu_virt_request_full_gpu(adev, false);
3643 }
3644
3645 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3646
3647 r = amdgpu_device_ip_suspend_phase1(adev);
3648 if (r)
3649 return r;
3650 r = amdgpu_device_ip_suspend_phase2(adev);
3651
3652 if (amdgpu_sriov_vf(adev))
3653 amdgpu_virt_release_full_gpu(adev, false);
3654
3655 return r;
3656}
3657
3658static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3659{
3660 int i, r;
3661
3662 static enum amd_ip_block_type ip_order[] = {
3663 AMD_IP_BLOCK_TYPE_COMMON,
3664 AMD_IP_BLOCK_TYPE_GMC,
3665 AMD_IP_BLOCK_TYPE_PSP,
3666 AMD_IP_BLOCK_TYPE_IH,
3667 };
3668
3669 for (i = 0; i < adev->num_ip_blocks; i++) {
3670 int j;
3671 struct amdgpu_ip_block *block;
3672
3673 block = &adev->ip_blocks[i];
3674 block->status.hw = false;
3675
3676 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3677
3678 if (block->version->type != ip_order[j] ||
3679 !block->status.valid)
3680 continue;
3681
3682 r = block->version->funcs->hw_init(&adev->ip_blocks[i]);
3683 if (r) {
3684 dev_err(adev->dev, "RE-INIT-early: %s failed\n",
3685 block->version->funcs->name);
3686 return r;
3687 }
3688 block->status.hw = true;
3689 }
3690 }
3691
3692 return 0;
3693}
3694
3695static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3696{
3697 struct amdgpu_ip_block *block;
3698 int i, r = 0;
3699
3700 static enum amd_ip_block_type ip_order[] = {
3701 AMD_IP_BLOCK_TYPE_SMC,
3702 AMD_IP_BLOCK_TYPE_DCE,
3703 AMD_IP_BLOCK_TYPE_GFX,
3704 AMD_IP_BLOCK_TYPE_SDMA,
3705 AMD_IP_BLOCK_TYPE_MES,
3706 AMD_IP_BLOCK_TYPE_UVD,
3707 AMD_IP_BLOCK_TYPE_VCE,
3708 AMD_IP_BLOCK_TYPE_VCN,
3709 AMD_IP_BLOCK_TYPE_JPEG
3710 };
3711
3712 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3713 block = amdgpu_device_ip_get_ip_block(adev, ip_order[i]);
3714
3715 if (!block)
3716 continue;
3717
3718 if (block->status.valid && !block->status.hw) {
3719 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) {
3720 r = amdgpu_ip_block_resume(block);
3721 } else {
3722 r = block->version->funcs->hw_init(block);
3723 }
3724
3725 if (r) {
3726 dev_err(adev->dev, "RE-INIT-late: %s failed\n",
3727 block->version->funcs->name);
3728 break;
3729 }
3730 block->status.hw = true;
3731 }
3732 }
3733
3734 return r;
3735}
3736
3737/**
3738 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3739 *
3740 * @adev: amdgpu_device pointer
3741 *
3742 * First resume function for hardware IPs. The list of all the hardware
3743 * IPs that make up the asic is walked and the resume callbacks are run for
3744 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3745 * after a suspend and updates the software state as necessary. This
3746 * function is also used for restoring the GPU after a GPU reset.
3747 * Returns 0 on success, negative error code on failure.
3748 */
3749static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3750{
3751 int i, r;
3752
3753 for (i = 0; i < adev->num_ip_blocks; i++) {
3754 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3755 continue;
3756 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3757 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3758 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3759 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3760
3761 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3762 if (r)
3763 return r;
3764 }
3765 }
3766
3767 return 0;
3768}
3769
3770/**
3771 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3772 *
3773 * @adev: amdgpu_device pointer
3774 *
3775 * Second resume function for hardware IPs. The list of all the hardware
3776 * IPs that make up the asic is walked and the resume callbacks are run for
3777 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3778 * functional state after a suspend and updates the software state as
3779 * necessary. This function is also used for restoring the GPU after a GPU
3780 * reset.
3781 * Returns 0 on success, negative error code on failure.
3782 */
3783static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3784{
3785 int i, r;
3786
3787 for (i = 0; i < adev->num_ip_blocks; i++) {
3788 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3789 continue;
3790 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3791 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3792 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3793 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE ||
3794 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3795 continue;
3796 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3797 if (r)
3798 return r;
3799 }
3800
3801 return 0;
3802}
3803
3804/**
3805 * amdgpu_device_ip_resume_phase3 - run resume for hardware IPs
3806 *
3807 * @adev: amdgpu_device pointer
3808 *
3809 * Third resume function for hardware IPs. The list of all the hardware
3810 * IPs that make up the asic is walked and the resume callbacks are run for
3811 * all DCE. resume puts the hardware into a functional state after a suspend
3812 * and updates the software state as necessary. This function is also used
3813 * for restoring the GPU after a GPU reset.
3814 *
3815 * Returns 0 on success, negative error code on failure.
3816 */
3817static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
3818{
3819 int i, r;
3820
3821 for (i = 0; i < adev->num_ip_blocks; i++) {
3822 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3823 continue;
3824 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
3825 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3826 if (r)
3827 return r;
3828 }
3829 }
3830
3831 return 0;
3832}
3833
3834/**
3835 * amdgpu_device_ip_resume - run resume for hardware IPs
3836 *
3837 * @adev: amdgpu_device pointer
3838 *
3839 * Main resume function for hardware IPs. The hardware IPs
3840 * are split into two resume functions because they are
3841 * also used in recovering from a GPU reset and some additional
3842 * steps need to be take between them. In this case (S3/S4) they are
3843 * run sequentially.
3844 * Returns 0 on success, negative error code on failure.
3845 */
3846static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3847{
3848 int r;
3849
3850 r = amdgpu_device_ip_resume_phase1(adev);
3851 if (r)
3852 return r;
3853
3854 r = amdgpu_device_fw_loading(adev);
3855 if (r)
3856 return r;
3857
3858 r = amdgpu_device_ip_resume_phase2(adev);
3859
3860 if (adev->mman.buffer_funcs_ring->sched.ready)
3861 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3862
3863 if (r)
3864 return r;
3865
3866 amdgpu_fence_driver_hw_init(adev);
3867
3868 r = amdgpu_device_ip_resume_phase3(adev);
3869
3870 return r;
3871}
3872
3873/**
3874 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3875 *
3876 * @adev: amdgpu_device pointer
3877 *
3878 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3879 */
3880static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3881{
3882 if (amdgpu_sriov_vf(adev)) {
3883 if (adev->is_atom_fw) {
3884 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3885 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3886 } else {
3887 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3888 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3889 }
3890
3891 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3892 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3893 }
3894}
3895
3896/**
3897 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3898 *
3899 * @asic_type: AMD asic type
3900 *
3901 * Check if there is DC (new modesetting infrastructre) support for an asic.
3902 * returns true if DC has support, false if not.
3903 */
3904bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3905{
3906 switch (asic_type) {
3907#ifdef CONFIG_DRM_AMDGPU_SI
3908 case CHIP_HAINAN:
3909#endif
3910 case CHIP_TOPAZ:
3911 /* chips with no display hardware */
3912 return false;
3913#if defined(CONFIG_DRM_AMD_DC)
3914 case CHIP_TAHITI:
3915 case CHIP_PITCAIRN:
3916 case CHIP_VERDE:
3917 case CHIP_OLAND:
3918 /*
3919 * We have systems in the wild with these ASICs that require
3920 * LVDS and VGA support which is not supported with DC.
3921 *
3922 * Fallback to the non-DC driver here by default so as not to
3923 * cause regressions.
3924 */
3925#if defined(CONFIG_DRM_AMD_DC_SI)
3926 return amdgpu_dc > 0;
3927#else
3928 return false;
3929#endif
3930 case CHIP_BONAIRE:
3931 case CHIP_KAVERI:
3932 case CHIP_KABINI:
3933 case CHIP_MULLINS:
3934 /*
3935 * We have systems in the wild with these ASICs that require
3936 * VGA support which is not supported with DC.
3937 *
3938 * Fallback to the non-DC driver here by default so as not to
3939 * cause regressions.
3940 */
3941 return amdgpu_dc > 0;
3942 default:
3943 return amdgpu_dc != 0;
3944#else
3945 default:
3946 if (amdgpu_dc > 0)
3947 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3948 return false;
3949#endif
3950 }
3951}
3952
3953/**
3954 * amdgpu_device_has_dc_support - check if dc is supported
3955 *
3956 * @adev: amdgpu_device pointer
3957 *
3958 * Returns true for supported, false for not supported
3959 */
3960bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3961{
3962 if (adev->enable_virtual_display ||
3963 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3964 return false;
3965
3966 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3967}
3968
3969static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3970{
3971 struct amdgpu_device *adev =
3972 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3973 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3974
3975 /* It's a bug to not have a hive within this function */
3976 if (WARN_ON(!hive))
3977 return;
3978
3979 /*
3980 * Use task barrier to synchronize all xgmi reset works across the
3981 * hive. task_barrier_enter and task_barrier_exit will block
3982 * until all the threads running the xgmi reset works reach
3983 * those points. task_barrier_full will do both blocks.
3984 */
3985 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3986
3987 task_barrier_enter(&hive->tb);
3988 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3989
3990 if (adev->asic_reset_res)
3991 goto fail;
3992
3993 task_barrier_exit(&hive->tb);
3994 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3995
3996 if (adev->asic_reset_res)
3997 goto fail;
3998
3999 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
4000 } else {
4001
4002 task_barrier_full(&hive->tb);
4003 adev->asic_reset_res = amdgpu_asic_reset(adev);
4004 }
4005
4006fail:
4007 if (adev->asic_reset_res)
4008 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
4009 adev->asic_reset_res, adev_to_drm(adev)->unique);
4010 amdgpu_put_xgmi_hive(hive);
4011}
4012
4013static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
4014{
4015 char *input = amdgpu_lockup_timeout;
4016 char *timeout_setting = NULL;
4017 int index = 0;
4018 long timeout;
4019 int ret = 0;
4020
4021 /*
4022 * By default timeout for non compute jobs is 10000
4023 * and 60000 for compute jobs.
4024 * In SR-IOV or passthrough mode, timeout for compute
4025 * jobs are 60000 by default.
4026 */
4027 adev->gfx_timeout = msecs_to_jiffies(10000);
4028 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
4029 if (amdgpu_sriov_vf(adev))
4030 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
4031 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
4032 else
4033 adev->compute_timeout = msecs_to_jiffies(60000);
4034
4035 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
4036 while ((timeout_setting = strsep(&input, ",")) &&
4037 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
4038 ret = kstrtol(timeout_setting, 0, &timeout);
4039 if (ret)
4040 return ret;
4041
4042 if (timeout == 0) {
4043 index++;
4044 continue;
4045 } else if (timeout < 0) {
4046 timeout = MAX_SCHEDULE_TIMEOUT;
4047 dev_warn(adev->dev, "lockup timeout disabled");
4048 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
4049 } else {
4050 timeout = msecs_to_jiffies(timeout);
4051 }
4052
4053 switch (index++) {
4054 case 0:
4055 adev->gfx_timeout = timeout;
4056 break;
4057 case 1:
4058 adev->compute_timeout = timeout;
4059 break;
4060 case 2:
4061 adev->sdma_timeout = timeout;
4062 break;
4063 case 3:
4064 adev->video_timeout = timeout;
4065 break;
4066 default:
4067 break;
4068 }
4069 }
4070 /*
4071 * There is only one value specified and
4072 * it should apply to all non-compute jobs.
4073 */
4074 if (index == 1) {
4075 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
4076 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
4077 adev->compute_timeout = adev->gfx_timeout;
4078 }
4079 }
4080
4081 return ret;
4082}
4083
4084/**
4085 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
4086 *
4087 * @adev: amdgpu_device pointer
4088 *
4089 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
4090 */
4091static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
4092{
4093 struct iommu_domain *domain;
4094
4095 domain = iommu_get_domain_for_dev(adev->dev);
4096 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
4097 adev->ram_is_direct_mapped = true;
4098}
4099
4100#if defined(CONFIG_HSA_AMD_P2P)
4101/**
4102 * amdgpu_device_check_iommu_remap - Check if DMA remapping is enabled.
4103 *
4104 * @adev: amdgpu_device pointer
4105 *
4106 * return if IOMMU remapping bar address
4107 */
4108static bool amdgpu_device_check_iommu_remap(struct amdgpu_device *adev)
4109{
4110 struct iommu_domain *domain;
4111
4112 domain = iommu_get_domain_for_dev(adev->dev);
4113 if (domain && (domain->type == IOMMU_DOMAIN_DMA ||
4114 domain->type == IOMMU_DOMAIN_DMA_FQ))
4115 return true;
4116
4117 return false;
4118}
4119#endif
4120
4121static const struct attribute *amdgpu_dev_attributes[] = {
4122 &dev_attr_pcie_replay_count.attr,
4123 NULL
4124};
4125
4126static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
4127{
4128 if (amdgpu_mcbp == 1)
4129 adev->gfx.mcbp = true;
4130 else if (amdgpu_mcbp == 0)
4131 adev->gfx.mcbp = false;
4132
4133 if (amdgpu_sriov_vf(adev))
4134 adev->gfx.mcbp = true;
4135
4136 if (adev->gfx.mcbp)
4137 DRM_INFO("MCBP is enabled\n");
4138}
4139
4140/**
4141 * amdgpu_device_init - initialize the driver
4142 *
4143 * @adev: amdgpu_device pointer
4144 * @flags: driver flags
4145 *
4146 * Initializes the driver info and hw (all asics).
4147 * Returns 0 for success or an error on failure.
4148 * Called at driver startup.
4149 */
4150int amdgpu_device_init(struct amdgpu_device *adev,
4151 uint32_t flags)
4152{
4153 struct drm_device *ddev = adev_to_drm(adev);
4154 struct pci_dev *pdev = adev->pdev;
4155 int r, i;
4156 bool px = false;
4157 u32 max_MBps;
4158 int tmp;
4159
4160 adev->shutdown = false;
4161 adev->flags = flags;
4162
4163 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
4164 adev->asic_type = amdgpu_force_asic_type;
4165 else
4166 adev->asic_type = flags & AMD_ASIC_MASK;
4167
4168 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
4169 if (amdgpu_emu_mode == 1)
4170 adev->usec_timeout *= 10;
4171 adev->gmc.gart_size = 512 * 1024 * 1024;
4172 adev->accel_working = false;
4173 adev->num_rings = 0;
4174 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
4175 adev->mman.buffer_funcs = NULL;
4176 adev->mman.buffer_funcs_ring = NULL;
4177 adev->vm_manager.vm_pte_funcs = NULL;
4178 adev->vm_manager.vm_pte_num_scheds = 0;
4179 adev->gmc.gmc_funcs = NULL;
4180 adev->harvest_ip_mask = 0x0;
4181 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
4182 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4183
4184 adev->smc_rreg = &amdgpu_invalid_rreg;
4185 adev->smc_wreg = &amdgpu_invalid_wreg;
4186 adev->pcie_rreg = &amdgpu_invalid_rreg;
4187 adev->pcie_wreg = &amdgpu_invalid_wreg;
4188 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
4189 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
4190 adev->pciep_rreg = &amdgpu_invalid_rreg;
4191 adev->pciep_wreg = &amdgpu_invalid_wreg;
4192 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
4193 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
4194 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
4195 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
4196 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
4197 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
4198 adev->didt_rreg = &amdgpu_invalid_rreg;
4199 adev->didt_wreg = &amdgpu_invalid_wreg;
4200 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
4201 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
4202 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
4203 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
4204
4205 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
4206 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
4207 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
4208
4209 /* mutex initialization are all done here so we
4210 * can recall function without having locking issues
4211 */
4212 mutex_init(&adev->firmware.mutex);
4213 mutex_init(&adev->pm.mutex);
4214 mutex_init(&adev->gfx.gpu_clock_mutex);
4215 mutex_init(&adev->srbm_mutex);
4216 mutex_init(&adev->gfx.pipe_reserve_mutex);
4217 mutex_init(&adev->gfx.gfx_off_mutex);
4218 mutex_init(&adev->gfx.partition_mutex);
4219 mutex_init(&adev->grbm_idx_mutex);
4220 mutex_init(&adev->mn_lock);
4221 mutex_init(&adev->virt.vf_errors.lock);
4222 mutex_init(&adev->virt.rlcg_reg_lock);
4223 hash_init(adev->mn_hash);
4224 mutex_init(&adev->psp.mutex);
4225 mutex_init(&adev->notifier_lock);
4226 mutex_init(&adev->pm.stable_pstate_ctx_lock);
4227 mutex_init(&adev->benchmark_mutex);
4228 mutex_init(&adev->gfx.reset_sem_mutex);
4229 /* Initialize the mutex for cleaner shader isolation between GFX and compute processes */
4230 mutex_init(&adev->enforce_isolation_mutex);
4231 mutex_init(&adev->gfx.kfd_sch_mutex);
4232
4233 amdgpu_device_init_apu_flags(adev);
4234
4235 r = amdgpu_device_check_arguments(adev);
4236 if (r)
4237 return r;
4238
4239 spin_lock_init(&adev->mmio_idx_lock);
4240 spin_lock_init(&adev->smc_idx_lock);
4241 spin_lock_init(&adev->pcie_idx_lock);
4242 spin_lock_init(&adev->uvd_ctx_idx_lock);
4243 spin_lock_init(&adev->didt_idx_lock);
4244 spin_lock_init(&adev->gc_cac_idx_lock);
4245 spin_lock_init(&adev->se_cac_idx_lock);
4246 spin_lock_init(&adev->audio_endpt_idx_lock);
4247 spin_lock_init(&adev->mm_stats.lock);
4248 spin_lock_init(&adev->wb.lock);
4249
4250 INIT_LIST_HEAD(&adev->reset_list);
4251
4252 INIT_LIST_HEAD(&adev->ras_list);
4253
4254 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
4255
4256 INIT_DELAYED_WORK(&adev->delayed_init_work,
4257 amdgpu_device_delayed_init_work_handler);
4258 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
4259 amdgpu_device_delay_enable_gfx_off);
4260 /*
4261 * Initialize the enforce_isolation work structures for each XCP
4262 * partition. This work handler is responsible for enforcing shader
4263 * isolation on AMD GPUs. It counts the number of emitted fences for
4264 * each GFX and compute ring. If there are any fences, it schedules
4265 * the `enforce_isolation_work` to be run after a delay. If there are
4266 * no fences, it signals the Kernel Fusion Driver (KFD) to resume the
4267 * runqueue.
4268 */
4269 for (i = 0; i < MAX_XCP; i++) {
4270 INIT_DELAYED_WORK(&adev->gfx.enforce_isolation[i].work,
4271 amdgpu_gfx_enforce_isolation_handler);
4272 adev->gfx.enforce_isolation[i].adev = adev;
4273 adev->gfx.enforce_isolation[i].xcp_id = i;
4274 }
4275
4276 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
4277
4278 adev->gfx.gfx_off_req_count = 1;
4279 adev->gfx.gfx_off_residency = 0;
4280 adev->gfx.gfx_off_entrycount = 0;
4281 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
4282
4283 atomic_set(&adev->throttling_logging_enabled, 1);
4284 /*
4285 * If throttling continues, logging will be performed every minute
4286 * to avoid log flooding. "-1" is subtracted since the thermal
4287 * throttling interrupt comes every second. Thus, the total logging
4288 * interval is 59 seconds(retelimited printk interval) + 1(waiting
4289 * for throttling interrupt) = 60 seconds.
4290 */
4291 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
4292 ratelimit_state_init(&adev->virt.ras_telemetry_rs, 5 * HZ, 1);
4293
4294 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
4295 ratelimit_set_flags(&adev->virt.ras_telemetry_rs, RATELIMIT_MSG_ON_RELEASE);
4296
4297 /* Registers mapping */
4298 /* TODO: block userspace mapping of io register */
4299 if (adev->asic_type >= CHIP_BONAIRE) {
4300 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
4301 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
4302 } else {
4303 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
4304 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
4305 }
4306
4307 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
4308 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
4309
4310 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
4311 if (!adev->rmmio)
4312 return -ENOMEM;
4313
4314 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
4315 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
4316
4317 /*
4318 * Reset domain needs to be present early, before XGMI hive discovered
4319 * (if any) and intitialized to use reset sem and in_gpu reset flag
4320 * early on during init and before calling to RREG32.
4321 */
4322 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
4323 if (!adev->reset_domain)
4324 return -ENOMEM;
4325
4326 /* detect hw virtualization here */
4327 amdgpu_detect_virtualization(adev);
4328
4329 amdgpu_device_get_pcie_info(adev);
4330
4331 r = amdgpu_device_get_job_timeout_settings(adev);
4332 if (r) {
4333 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
4334 return r;
4335 }
4336
4337 amdgpu_device_set_mcbp(adev);
4338
4339 /*
4340 * By default, use default mode where all blocks are expected to be
4341 * initialized. At present a 'swinit' of blocks is required to be
4342 * completed before the need for a different level is detected.
4343 */
4344 amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_DEFAULT);
4345 /* early init functions */
4346 r = amdgpu_device_ip_early_init(adev);
4347 if (r)
4348 return r;
4349
4350 /* Get rid of things like offb */
4351 r = aperture_remove_conflicting_pci_devices(adev->pdev, amdgpu_kms_driver.name);
4352 if (r)
4353 return r;
4354
4355 /* Enable TMZ based on IP_VERSION */
4356 amdgpu_gmc_tmz_set(adev);
4357
4358 if (amdgpu_sriov_vf(adev) &&
4359 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4360 /* VF MMIO access (except mailbox range) from CPU
4361 * will be blocked during sriov runtime
4362 */
4363 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
4364
4365 amdgpu_gmc_noretry_set(adev);
4366 /* Need to get xgmi info early to decide the reset behavior*/
4367 if (adev->gmc.xgmi.supported) {
4368 r = adev->gfxhub.funcs->get_xgmi_info(adev);
4369 if (r)
4370 return r;
4371 }
4372
4373 /* enable PCIE atomic ops */
4374 if (amdgpu_sriov_vf(adev)) {
4375 if (adev->virt.fw_reserve.p_pf2vf)
4376 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
4377 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
4378 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4379 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4380 * internal path natively support atomics, set have_atomics_support to true.
4381 */
4382 } else if ((adev->flags & AMD_IS_APU) &&
4383 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4384 IP_VERSION(9, 0, 0))) {
4385 adev->have_atomics_support = true;
4386 } else {
4387 adev->have_atomics_support =
4388 !pci_enable_atomic_ops_to_root(adev->pdev,
4389 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4390 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4391 }
4392
4393 if (!adev->have_atomics_support)
4394 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4395
4396 /* doorbell bar mapping and doorbell index init*/
4397 amdgpu_doorbell_init(adev);
4398
4399 if (amdgpu_emu_mode == 1) {
4400 /* post the asic on emulation mode */
4401 emu_soc_asic_init(adev);
4402 goto fence_driver_init;
4403 }
4404
4405 amdgpu_reset_init(adev);
4406
4407 /* detect if we are with an SRIOV vbios */
4408 if (adev->bios)
4409 amdgpu_device_detect_sriov_bios(adev);
4410
4411 /* check if we need to reset the asic
4412 * E.g., driver was not cleanly unloaded previously, etc.
4413 */
4414 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4415 if (adev->gmc.xgmi.num_physical_nodes) {
4416 dev_info(adev->dev, "Pending hive reset.\n");
4417 amdgpu_set_init_level(adev,
4418 AMDGPU_INIT_LEVEL_MINIMAL_XGMI);
4419 } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
4420 !amdgpu_device_has_display_hardware(adev)) {
4421 r = psp_gpu_reset(adev);
4422 } else {
4423 tmp = amdgpu_reset_method;
4424 /* It should do a default reset when loading or reloading the driver,
4425 * regardless of the module parameter reset_method.
4426 */
4427 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4428 r = amdgpu_asic_reset(adev);
4429 amdgpu_reset_method = tmp;
4430 }
4431
4432 if (r) {
4433 dev_err(adev->dev, "asic reset on init failed\n");
4434 goto failed;
4435 }
4436 }
4437
4438 /* Post card if necessary */
4439 if (amdgpu_device_need_post(adev)) {
4440 if (!adev->bios) {
4441 dev_err(adev->dev, "no vBIOS found\n");
4442 r = -EINVAL;
4443 goto failed;
4444 }
4445 DRM_INFO("GPU posting now...\n");
4446 r = amdgpu_device_asic_init(adev);
4447 if (r) {
4448 dev_err(adev->dev, "gpu post error!\n");
4449 goto failed;
4450 }
4451 }
4452
4453 if (adev->bios) {
4454 if (adev->is_atom_fw) {
4455 /* Initialize clocks */
4456 r = amdgpu_atomfirmware_get_clock_info(adev);
4457 if (r) {
4458 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4459 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4460 goto failed;
4461 }
4462 } else {
4463 /* Initialize clocks */
4464 r = amdgpu_atombios_get_clock_info(adev);
4465 if (r) {
4466 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4467 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4468 goto failed;
4469 }
4470 /* init i2c buses */
4471 if (!amdgpu_device_has_dc_support(adev))
4472 amdgpu_atombios_i2c_init(adev);
4473 }
4474 }
4475
4476fence_driver_init:
4477 /* Fence driver */
4478 r = amdgpu_fence_driver_sw_init(adev);
4479 if (r) {
4480 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4481 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4482 goto failed;
4483 }
4484
4485 /* init the mode config */
4486 drm_mode_config_init(adev_to_drm(adev));
4487
4488 r = amdgpu_device_ip_init(adev);
4489 if (r) {
4490 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4491 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4492 goto release_ras_con;
4493 }
4494
4495 amdgpu_fence_driver_hw_init(adev);
4496
4497 dev_info(adev->dev,
4498 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4499 adev->gfx.config.max_shader_engines,
4500 adev->gfx.config.max_sh_per_se,
4501 adev->gfx.config.max_cu_per_sh,
4502 adev->gfx.cu_info.number);
4503
4504 adev->accel_working = true;
4505
4506 amdgpu_vm_check_compute_bug(adev);
4507
4508 /* Initialize the buffer migration limit. */
4509 if (amdgpu_moverate >= 0)
4510 max_MBps = amdgpu_moverate;
4511 else
4512 max_MBps = 8; /* Allow 8 MB/s. */
4513 /* Get a log2 for easy divisions. */
4514 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4515
4516 /*
4517 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4518 * Otherwise the mgpu fan boost feature will be skipped due to the
4519 * gpu instance is counted less.
4520 */
4521 amdgpu_register_gpu_instance(adev);
4522
4523 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4524 * explicit gating rather than handling it automatically.
4525 */
4526 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
4527 r = amdgpu_device_ip_late_init(adev);
4528 if (r) {
4529 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4530 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4531 goto release_ras_con;
4532 }
4533 /* must succeed. */
4534 amdgpu_ras_resume(adev);
4535 queue_delayed_work(system_wq, &adev->delayed_init_work,
4536 msecs_to_jiffies(AMDGPU_RESUME_MS));
4537 }
4538
4539 if (amdgpu_sriov_vf(adev)) {
4540 amdgpu_virt_release_full_gpu(adev, true);
4541 flush_delayed_work(&adev->delayed_init_work);
4542 }
4543
4544 /*
4545 * Place those sysfs registering after `late_init`. As some of those
4546 * operations performed in `late_init` might affect the sysfs
4547 * interfaces creating.
4548 */
4549 r = amdgpu_atombios_sysfs_init(adev);
4550 if (r)
4551 drm_err(&adev->ddev,
4552 "registering atombios sysfs failed (%d).\n", r);
4553
4554 r = amdgpu_pm_sysfs_init(adev);
4555 if (r)
4556 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4557
4558 r = amdgpu_ucode_sysfs_init(adev);
4559 if (r) {
4560 adev->ucode_sysfs_en = false;
4561 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4562 } else
4563 adev->ucode_sysfs_en = true;
4564
4565 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4566 if (r)
4567 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4568
4569 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4570 if (r)
4571 dev_err(adev->dev,
4572 "Could not create amdgpu board attributes\n");
4573
4574 amdgpu_fru_sysfs_init(adev);
4575 amdgpu_reg_state_sysfs_init(adev);
4576 amdgpu_xcp_cfg_sysfs_init(adev);
4577
4578 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4579 r = amdgpu_pmu_init(adev);
4580 if (r)
4581 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4582
4583 /* Have stored pci confspace at hand for restore in sudden PCI error */
4584 if (amdgpu_device_cache_pci_state(adev->pdev))
4585 pci_restore_state(pdev);
4586
4587 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4588 /* this will fail for cards that aren't VGA class devices, just
4589 * ignore it
4590 */
4591 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4592 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4593
4594 px = amdgpu_device_supports_px(ddev);
4595
4596 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4597 apple_gmux_detect(NULL, NULL)))
4598 vga_switcheroo_register_client(adev->pdev,
4599 &amdgpu_switcheroo_ops, px);
4600
4601 if (px)
4602 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4603
4604 if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI)
4605 amdgpu_xgmi_reset_on_init(adev);
4606
4607 amdgpu_device_check_iommu_direct_map(adev);
4608
4609 return 0;
4610
4611release_ras_con:
4612 if (amdgpu_sriov_vf(adev))
4613 amdgpu_virt_release_full_gpu(adev, true);
4614
4615 /* failed in exclusive mode due to timeout */
4616 if (amdgpu_sriov_vf(adev) &&
4617 !amdgpu_sriov_runtime(adev) &&
4618 amdgpu_virt_mmio_blocked(adev) &&
4619 !amdgpu_virt_wait_reset(adev)) {
4620 dev_err(adev->dev, "VF exclusive mode timeout\n");
4621 /* Don't send request since VF is inactive. */
4622 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4623 adev->virt.ops = NULL;
4624 r = -EAGAIN;
4625 }
4626 amdgpu_release_ras_context(adev);
4627
4628failed:
4629 amdgpu_vf_error_trans_all(adev);
4630
4631 return r;
4632}
4633
4634static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4635{
4636
4637 /* Clear all CPU mappings pointing to this device */
4638 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4639
4640 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4641 amdgpu_doorbell_fini(adev);
4642
4643 iounmap(adev->rmmio);
4644 adev->rmmio = NULL;
4645 if (adev->mman.aper_base_kaddr)
4646 iounmap(adev->mman.aper_base_kaddr);
4647 adev->mman.aper_base_kaddr = NULL;
4648
4649 /* Memory manager related */
4650 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4651 arch_phys_wc_del(adev->gmc.vram_mtrr);
4652 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4653 }
4654}
4655
4656/**
4657 * amdgpu_device_fini_hw - tear down the driver
4658 *
4659 * @adev: amdgpu_device pointer
4660 *
4661 * Tear down the driver info (all asics).
4662 * Called at driver shutdown.
4663 */
4664void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4665{
4666 dev_info(adev->dev, "amdgpu: finishing device.\n");
4667 flush_delayed_work(&adev->delayed_init_work);
4668
4669 if (adev->mman.initialized)
4670 drain_workqueue(adev->mman.bdev.wq);
4671 adev->shutdown = true;
4672
4673 /* make sure IB test finished before entering exclusive mode
4674 * to avoid preemption on IB test
4675 */
4676 if (amdgpu_sriov_vf(adev)) {
4677 amdgpu_virt_request_full_gpu(adev, false);
4678 amdgpu_virt_fini_data_exchange(adev);
4679 }
4680
4681 /* disable all interrupts */
4682 amdgpu_irq_disable_all(adev);
4683 if (adev->mode_info.mode_config_initialized) {
4684 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4685 drm_helper_force_disable_all(adev_to_drm(adev));
4686 else
4687 drm_atomic_helper_shutdown(adev_to_drm(adev));
4688 }
4689 amdgpu_fence_driver_hw_fini(adev);
4690
4691 if (adev->pm.sysfs_initialized)
4692 amdgpu_pm_sysfs_fini(adev);
4693 if (adev->ucode_sysfs_en)
4694 amdgpu_ucode_sysfs_fini(adev);
4695 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4696 amdgpu_fru_sysfs_fini(adev);
4697
4698 amdgpu_reg_state_sysfs_fini(adev);
4699 amdgpu_xcp_cfg_sysfs_fini(adev);
4700
4701 /* disable ras feature must before hw fini */
4702 amdgpu_ras_pre_fini(adev);
4703
4704 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4705
4706 amdgpu_device_ip_fini_early(adev);
4707
4708 amdgpu_irq_fini_hw(adev);
4709
4710 if (adev->mman.initialized)
4711 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4712
4713 amdgpu_gart_dummy_page_fini(adev);
4714
4715 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4716 amdgpu_device_unmap_mmio(adev);
4717
4718}
4719
4720void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4721{
4722 int idx;
4723 bool px;
4724
4725 amdgpu_device_ip_fini(adev);
4726 amdgpu_fence_driver_sw_fini(adev);
4727 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4728 adev->accel_working = false;
4729 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4730
4731 amdgpu_reset_fini(adev);
4732
4733 /* free i2c buses */
4734 if (!amdgpu_device_has_dc_support(adev))
4735 amdgpu_i2c_fini(adev);
4736
4737 if (amdgpu_emu_mode != 1)
4738 amdgpu_atombios_fini(adev);
4739
4740 kfree(adev->bios);
4741 adev->bios = NULL;
4742
4743 kfree(adev->fru_info);
4744 adev->fru_info = NULL;
4745
4746 px = amdgpu_device_supports_px(adev_to_drm(adev));
4747
4748 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4749 apple_gmux_detect(NULL, NULL)))
4750 vga_switcheroo_unregister_client(adev->pdev);
4751
4752 if (px)
4753 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4754
4755 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4756 vga_client_unregister(adev->pdev);
4757
4758 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4759
4760 iounmap(adev->rmmio);
4761 adev->rmmio = NULL;
4762 amdgpu_doorbell_fini(adev);
4763 drm_dev_exit(idx);
4764 }
4765
4766 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4767 amdgpu_pmu_fini(adev);
4768 if (adev->mman.discovery_bin)
4769 amdgpu_discovery_fini(adev);
4770
4771 amdgpu_reset_put_reset_domain(adev->reset_domain);
4772 adev->reset_domain = NULL;
4773
4774 kfree(adev->pci_state);
4775
4776}
4777
4778/**
4779 * amdgpu_device_evict_resources - evict device resources
4780 * @adev: amdgpu device object
4781 *
4782 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4783 * of the vram memory type. Mainly used for evicting device resources
4784 * at suspend time.
4785 *
4786 */
4787static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4788{
4789 int ret;
4790
4791 /* No need to evict vram on APUs for suspend to ram or s2idle */
4792 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4793 return 0;
4794
4795 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4796 if (ret)
4797 DRM_WARN("evicting device resources failed\n");
4798 return ret;
4799}
4800
4801/*
4802 * Suspend & resume.
4803 */
4804/**
4805 * amdgpu_device_prepare - prepare for device suspend
4806 *
4807 * @dev: drm dev pointer
4808 *
4809 * Prepare to put the hw in the suspend state (all asics).
4810 * Returns 0 for success or an error on failure.
4811 * Called at driver suspend.
4812 */
4813int amdgpu_device_prepare(struct drm_device *dev)
4814{
4815 struct amdgpu_device *adev = drm_to_adev(dev);
4816 int i, r;
4817
4818 amdgpu_choose_low_power_state(adev);
4819
4820 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4821 return 0;
4822
4823 /* Evict the majority of BOs before starting suspend sequence */
4824 r = amdgpu_device_evict_resources(adev);
4825 if (r)
4826 goto unprepare;
4827
4828 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4829
4830 for (i = 0; i < adev->num_ip_blocks; i++) {
4831 if (!adev->ip_blocks[i].status.valid)
4832 continue;
4833 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4834 continue;
4835 r = adev->ip_blocks[i].version->funcs->prepare_suspend(&adev->ip_blocks[i]);
4836 if (r)
4837 goto unprepare;
4838 }
4839
4840 return 0;
4841
4842unprepare:
4843 adev->in_s0ix = adev->in_s3 = false;
4844
4845 return r;
4846}
4847
4848/**
4849 * amdgpu_device_suspend - initiate device suspend
4850 *
4851 * @dev: drm dev pointer
4852 * @notify_clients: notify in-kernel DRM clients
4853 *
4854 * Puts the hw in the suspend state (all asics).
4855 * Returns 0 for success or an error on failure.
4856 * Called at driver suspend.
4857 */
4858int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
4859{
4860 struct amdgpu_device *adev = drm_to_adev(dev);
4861 int r = 0;
4862
4863 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4864 return 0;
4865
4866 adev->in_suspend = true;
4867
4868 if (amdgpu_sriov_vf(adev)) {
4869 amdgpu_virt_fini_data_exchange(adev);
4870 r = amdgpu_virt_request_full_gpu(adev, false);
4871 if (r)
4872 return r;
4873 }
4874
4875 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4876 DRM_WARN("smart shift update failed\n");
4877
4878 if (notify_clients)
4879 drm_client_dev_suspend(adev_to_drm(adev), false);
4880
4881 cancel_delayed_work_sync(&adev->delayed_init_work);
4882
4883 amdgpu_ras_suspend(adev);
4884
4885 amdgpu_device_ip_suspend_phase1(adev);
4886
4887 if (!adev->in_s0ix)
4888 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4889
4890 r = amdgpu_device_evict_resources(adev);
4891 if (r)
4892 return r;
4893
4894 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4895
4896 amdgpu_fence_driver_hw_fini(adev);
4897
4898 amdgpu_device_ip_suspend_phase2(adev);
4899
4900 if (amdgpu_sriov_vf(adev))
4901 amdgpu_virt_release_full_gpu(adev, false);
4902
4903 r = amdgpu_dpm_notify_rlc_state(adev, false);
4904 if (r)
4905 return r;
4906
4907 return 0;
4908}
4909
4910/**
4911 * amdgpu_device_resume - initiate device resume
4912 *
4913 * @dev: drm dev pointer
4914 * @notify_clients: notify in-kernel DRM clients
4915 *
4916 * Bring the hw back to operating state (all asics).
4917 * Returns 0 for success or an error on failure.
4918 * Called at driver resume.
4919 */
4920int amdgpu_device_resume(struct drm_device *dev, bool notify_clients)
4921{
4922 struct amdgpu_device *adev = drm_to_adev(dev);
4923 int r = 0;
4924
4925 if (amdgpu_sriov_vf(adev)) {
4926 r = amdgpu_virt_request_full_gpu(adev, true);
4927 if (r)
4928 return r;
4929 }
4930
4931 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4932 return 0;
4933
4934 if (adev->in_s0ix)
4935 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4936
4937 /* post card */
4938 if (amdgpu_device_need_post(adev)) {
4939 r = amdgpu_device_asic_init(adev);
4940 if (r)
4941 dev_err(adev->dev, "amdgpu asic init failed\n");
4942 }
4943
4944 r = amdgpu_device_ip_resume(adev);
4945
4946 if (r) {
4947 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4948 goto exit;
4949 }
4950
4951 if (!adev->in_s0ix) {
4952 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4953 if (r)
4954 goto exit;
4955 }
4956
4957 r = amdgpu_device_ip_late_init(adev);
4958 if (r)
4959 goto exit;
4960
4961 queue_delayed_work(system_wq, &adev->delayed_init_work,
4962 msecs_to_jiffies(AMDGPU_RESUME_MS));
4963exit:
4964 if (amdgpu_sriov_vf(adev)) {
4965 amdgpu_virt_init_data_exchange(adev);
4966 amdgpu_virt_release_full_gpu(adev, true);
4967 }
4968
4969 if (r)
4970 return r;
4971
4972 /* Make sure IB tests flushed */
4973 flush_delayed_work(&adev->delayed_init_work);
4974
4975 if (notify_clients)
4976 drm_client_dev_resume(adev_to_drm(adev), false);
4977
4978 amdgpu_ras_resume(adev);
4979
4980 if (adev->mode_info.num_crtc) {
4981 /*
4982 * Most of the connector probing functions try to acquire runtime pm
4983 * refs to ensure that the GPU is powered on when connector polling is
4984 * performed. Since we're calling this from a runtime PM callback,
4985 * trying to acquire rpm refs will cause us to deadlock.
4986 *
4987 * Since we're guaranteed to be holding the rpm lock, it's safe to
4988 * temporarily disable the rpm helpers so this doesn't deadlock us.
4989 */
4990#ifdef CONFIG_PM
4991 dev->dev->power.disable_depth++;
4992#endif
4993 if (!adev->dc_enabled)
4994 drm_helper_hpd_irq_event(dev);
4995 else
4996 drm_kms_helper_hotplug_event(dev);
4997#ifdef CONFIG_PM
4998 dev->dev->power.disable_depth--;
4999#endif
5000 }
5001 adev->in_suspend = false;
5002
5003 if (adev->enable_mes)
5004 amdgpu_mes_self_test(adev);
5005
5006 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
5007 DRM_WARN("smart shift update failed\n");
5008
5009 return 0;
5010}
5011
5012/**
5013 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
5014 *
5015 * @adev: amdgpu_device pointer
5016 *
5017 * The list of all the hardware IPs that make up the asic is walked and
5018 * the check_soft_reset callbacks are run. check_soft_reset determines
5019 * if the asic is still hung or not.
5020 * Returns true if any of the IPs are still in a hung state, false if not.
5021 */
5022static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
5023{
5024 int i;
5025 bool asic_hang = false;
5026
5027 if (amdgpu_sriov_vf(adev))
5028 return true;
5029
5030 if (amdgpu_asic_need_full_reset(adev))
5031 return true;
5032
5033 for (i = 0; i < adev->num_ip_blocks; i++) {
5034 if (!adev->ip_blocks[i].status.valid)
5035 continue;
5036 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
5037 adev->ip_blocks[i].status.hang =
5038 adev->ip_blocks[i].version->funcs->check_soft_reset(
5039 &adev->ip_blocks[i]);
5040 if (adev->ip_blocks[i].status.hang) {
5041 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
5042 asic_hang = true;
5043 }
5044 }
5045 return asic_hang;
5046}
5047
5048/**
5049 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
5050 *
5051 * @adev: amdgpu_device pointer
5052 *
5053 * The list of all the hardware IPs that make up the asic is walked and the
5054 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
5055 * handles any IP specific hardware or software state changes that are
5056 * necessary for a soft reset to succeed.
5057 * Returns 0 on success, negative error code on failure.
5058 */
5059static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
5060{
5061 int i, r = 0;
5062
5063 for (i = 0; i < adev->num_ip_blocks; i++) {
5064 if (!adev->ip_blocks[i].status.valid)
5065 continue;
5066 if (adev->ip_blocks[i].status.hang &&
5067 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
5068 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(&adev->ip_blocks[i]);
5069 if (r)
5070 return r;
5071 }
5072 }
5073
5074 return 0;
5075}
5076
5077/**
5078 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
5079 *
5080 * @adev: amdgpu_device pointer
5081 *
5082 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
5083 * reset is necessary to recover.
5084 * Returns true if a full asic reset is required, false if not.
5085 */
5086static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
5087{
5088 int i;
5089
5090 if (amdgpu_asic_need_full_reset(adev))
5091 return true;
5092
5093 for (i = 0; i < adev->num_ip_blocks; i++) {
5094 if (!adev->ip_blocks[i].status.valid)
5095 continue;
5096 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
5097 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
5098 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
5099 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
5100 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
5101 if (adev->ip_blocks[i].status.hang) {
5102 dev_info(adev->dev, "Some block need full reset!\n");
5103 return true;
5104 }
5105 }
5106 }
5107 return false;
5108}
5109
5110/**
5111 * amdgpu_device_ip_soft_reset - do a soft reset
5112 *
5113 * @adev: amdgpu_device pointer
5114 *
5115 * The list of all the hardware IPs that make up the asic is walked and the
5116 * soft_reset callbacks are run if the block is hung. soft_reset handles any
5117 * IP specific hardware or software state changes that are necessary to soft
5118 * reset the IP.
5119 * Returns 0 on success, negative error code on failure.
5120 */
5121static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
5122{
5123 int i, r = 0;
5124
5125 for (i = 0; i < adev->num_ip_blocks; i++) {
5126 if (!adev->ip_blocks[i].status.valid)
5127 continue;
5128 if (adev->ip_blocks[i].status.hang &&
5129 adev->ip_blocks[i].version->funcs->soft_reset) {
5130 r = adev->ip_blocks[i].version->funcs->soft_reset(&adev->ip_blocks[i]);
5131 if (r)
5132 return r;
5133 }
5134 }
5135
5136 return 0;
5137}
5138
5139/**
5140 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
5141 *
5142 * @adev: amdgpu_device pointer
5143 *
5144 * The list of all the hardware IPs that make up the asic is walked and the
5145 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
5146 * handles any IP specific hardware or software state changes that are
5147 * necessary after the IP has been soft reset.
5148 * Returns 0 on success, negative error code on failure.
5149 */
5150static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
5151{
5152 int i, r = 0;
5153
5154 for (i = 0; i < adev->num_ip_blocks; i++) {
5155 if (!adev->ip_blocks[i].status.valid)
5156 continue;
5157 if (adev->ip_blocks[i].status.hang &&
5158 adev->ip_blocks[i].version->funcs->post_soft_reset)
5159 r = adev->ip_blocks[i].version->funcs->post_soft_reset(&adev->ip_blocks[i]);
5160 if (r)
5161 return r;
5162 }
5163
5164 return 0;
5165}
5166
5167/**
5168 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
5169 *
5170 * @adev: amdgpu_device pointer
5171 * @reset_context: amdgpu reset context pointer
5172 *
5173 * do VF FLR and reinitialize Asic
5174 * return 0 means succeeded otherwise failed
5175 */
5176static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
5177 struct amdgpu_reset_context *reset_context)
5178{
5179 int r;
5180 struct amdgpu_hive_info *hive = NULL;
5181
5182 if (test_bit(AMDGPU_HOST_FLR, &reset_context->flags)) {
5183 if (!amdgpu_ras_get_fed_status(adev))
5184 amdgpu_virt_ready_to_reset(adev);
5185 amdgpu_virt_wait_reset(adev);
5186 clear_bit(AMDGPU_HOST_FLR, &reset_context->flags);
5187 r = amdgpu_virt_request_full_gpu(adev, true);
5188 } else {
5189 r = amdgpu_virt_reset_gpu(adev);
5190 }
5191 if (r)
5192 return r;
5193
5194 amdgpu_ras_set_fed(adev, false);
5195 amdgpu_irq_gpu_reset_resume_helper(adev);
5196
5197 /* some sw clean up VF needs to do before recover */
5198 amdgpu_virt_post_reset(adev);
5199
5200 /* Resume IP prior to SMC */
5201 r = amdgpu_device_ip_reinit_early_sriov(adev);
5202 if (r)
5203 return r;
5204
5205 amdgpu_virt_init_data_exchange(adev);
5206
5207 r = amdgpu_device_fw_loading(adev);
5208 if (r)
5209 return r;
5210
5211 /* now we are okay to resume SMC/CP/SDMA */
5212 r = amdgpu_device_ip_reinit_late_sriov(adev);
5213 if (r)
5214 return r;
5215
5216 hive = amdgpu_get_xgmi_hive(adev);
5217 /* Update PSP FW topology after reset */
5218 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
5219 r = amdgpu_xgmi_update_topology(hive, adev);
5220 if (hive)
5221 amdgpu_put_xgmi_hive(hive);
5222 if (r)
5223 return r;
5224
5225 r = amdgpu_ib_ring_tests(adev);
5226 if (r)
5227 return r;
5228
5229 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST)
5230 amdgpu_inc_vram_lost(adev);
5231
5232 /* need to be called during full access so we can't do it later like
5233 * bare-metal does.
5234 */
5235 amdgpu_amdkfd_post_reset(adev);
5236 amdgpu_virt_release_full_gpu(adev, true);
5237
5238 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5239 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
5240 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
5241 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
5242 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5243 amdgpu_ras_resume(adev);
5244
5245 amdgpu_virt_ras_telemetry_post_reset(adev);
5246
5247 return 0;
5248}
5249
5250/**
5251 * amdgpu_device_has_job_running - check if there is any job in mirror list
5252 *
5253 * @adev: amdgpu_device pointer
5254 *
5255 * check if there is any job in mirror list
5256 */
5257bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
5258{
5259 int i;
5260 struct drm_sched_job *job;
5261
5262 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5263 struct amdgpu_ring *ring = adev->rings[i];
5264
5265 if (!amdgpu_ring_sched_ready(ring))
5266 continue;
5267
5268 spin_lock(&ring->sched.job_list_lock);
5269 job = list_first_entry_or_null(&ring->sched.pending_list,
5270 struct drm_sched_job, list);
5271 spin_unlock(&ring->sched.job_list_lock);
5272 if (job)
5273 return true;
5274 }
5275 return false;
5276}
5277
5278/**
5279 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
5280 *
5281 * @adev: amdgpu_device pointer
5282 *
5283 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
5284 * a hung GPU.
5285 */
5286bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
5287{
5288
5289 if (amdgpu_gpu_recovery == 0)
5290 goto disabled;
5291
5292 /* Skip soft reset check in fatal error mode */
5293 if (!amdgpu_ras_is_poison_mode_supported(adev))
5294 return true;
5295
5296 if (amdgpu_sriov_vf(adev))
5297 return true;
5298
5299 if (amdgpu_gpu_recovery == -1) {
5300 switch (adev->asic_type) {
5301#ifdef CONFIG_DRM_AMDGPU_SI
5302 case CHIP_VERDE:
5303 case CHIP_TAHITI:
5304 case CHIP_PITCAIRN:
5305 case CHIP_OLAND:
5306 case CHIP_HAINAN:
5307#endif
5308#ifdef CONFIG_DRM_AMDGPU_CIK
5309 case CHIP_KAVERI:
5310 case CHIP_KABINI:
5311 case CHIP_MULLINS:
5312#endif
5313 case CHIP_CARRIZO:
5314 case CHIP_STONEY:
5315 case CHIP_CYAN_SKILLFISH:
5316 goto disabled;
5317 default:
5318 break;
5319 }
5320 }
5321
5322 return true;
5323
5324disabled:
5325 dev_info(adev->dev, "GPU recovery disabled.\n");
5326 return false;
5327}
5328
5329int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5330{
5331 u32 i;
5332 int ret = 0;
5333
5334 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5335
5336 dev_info(adev->dev, "GPU mode1 reset\n");
5337
5338 /* Cache the state before bus master disable. The saved config space
5339 * values are used in other cases like restore after mode-2 reset.
5340 */
5341 amdgpu_device_cache_pci_state(adev->pdev);
5342
5343 /* disable BM */
5344 pci_clear_master(adev->pdev);
5345
5346 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5347 dev_info(adev->dev, "GPU smu mode1 reset\n");
5348 ret = amdgpu_dpm_mode1_reset(adev);
5349 } else {
5350 dev_info(adev->dev, "GPU psp mode1 reset\n");
5351 ret = psp_gpu_reset(adev);
5352 }
5353
5354 if (ret)
5355 goto mode1_reset_failed;
5356
5357 amdgpu_device_load_pci_state(adev->pdev);
5358 ret = amdgpu_psp_wait_for_bootloader(adev);
5359 if (ret)
5360 goto mode1_reset_failed;
5361
5362 /* wait for asic to come out of reset */
5363 for (i = 0; i < adev->usec_timeout; i++) {
5364 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5365
5366 if (memsize != 0xffffffff)
5367 break;
5368 udelay(1);
5369 }
5370
5371 if (i >= adev->usec_timeout) {
5372 ret = -ETIMEDOUT;
5373 goto mode1_reset_failed;
5374 }
5375
5376 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5377
5378 return 0;
5379
5380mode1_reset_failed:
5381 dev_err(adev->dev, "GPU mode1 reset failed\n");
5382 return ret;
5383}
5384
5385int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5386 struct amdgpu_reset_context *reset_context)
5387{
5388 int i, r = 0;
5389 struct amdgpu_job *job = NULL;
5390 struct amdgpu_device *tmp_adev = reset_context->reset_req_dev;
5391 bool need_full_reset =
5392 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5393
5394 if (reset_context->reset_req_dev == adev)
5395 job = reset_context->job;
5396
5397 if (amdgpu_sriov_vf(adev))
5398 amdgpu_virt_pre_reset(adev);
5399
5400 amdgpu_fence_driver_isr_toggle(adev, true);
5401
5402 /* block all schedulers and reset given job's ring */
5403 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5404 struct amdgpu_ring *ring = adev->rings[i];
5405
5406 if (!amdgpu_ring_sched_ready(ring))
5407 continue;
5408
5409 /* Clear job fence from fence drv to avoid force_completion
5410 * leave NULL and vm flush fence in fence drv
5411 */
5412 amdgpu_fence_driver_clear_job_fences(ring);
5413
5414 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5415 amdgpu_fence_driver_force_completion(ring);
5416 }
5417
5418 amdgpu_fence_driver_isr_toggle(adev, false);
5419
5420 if (job && job->vm)
5421 drm_sched_increase_karma(&job->base);
5422
5423 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5424 /* If reset handler not implemented, continue; otherwise return */
5425 if (r == -EOPNOTSUPP)
5426 r = 0;
5427 else
5428 return r;
5429
5430 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5431 if (!amdgpu_sriov_vf(adev)) {
5432
5433 if (!need_full_reset)
5434 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5435
5436 if (!need_full_reset && amdgpu_gpu_recovery &&
5437 amdgpu_device_ip_check_soft_reset(adev)) {
5438 amdgpu_device_ip_pre_soft_reset(adev);
5439 r = amdgpu_device_ip_soft_reset(adev);
5440 amdgpu_device_ip_post_soft_reset(adev);
5441 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5442 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5443 need_full_reset = true;
5444 }
5445 }
5446
5447 if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags)) {
5448 dev_info(tmp_adev->dev, "Dumping IP State\n");
5449 /* Trigger ip dump before we reset the asic */
5450 for (i = 0; i < tmp_adev->num_ip_blocks; i++)
5451 if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
5452 tmp_adev->ip_blocks[i].version->funcs
5453 ->dump_ip_state((void *)&tmp_adev->ip_blocks[i]);
5454 dev_info(tmp_adev->dev, "Dumping IP State Completed\n");
5455 }
5456
5457 if (need_full_reset)
5458 r = amdgpu_device_ip_suspend(adev);
5459 if (need_full_reset)
5460 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5461 else
5462 clear_bit(AMDGPU_NEED_FULL_RESET,
5463 &reset_context->flags);
5464 }
5465
5466 return r;
5467}
5468
5469int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context)
5470{
5471 struct list_head *device_list_handle;
5472 bool full_reset, vram_lost = false;
5473 struct amdgpu_device *tmp_adev;
5474 int r, init_level;
5475
5476 device_list_handle = reset_context->reset_device_list;
5477
5478 if (!device_list_handle)
5479 return -EINVAL;
5480
5481 full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5482
5483 /**
5484 * If it's reset on init, it's default init level, otherwise keep level
5485 * as recovery level.
5486 */
5487 if (reset_context->method == AMD_RESET_METHOD_ON_INIT)
5488 init_level = AMDGPU_INIT_LEVEL_DEFAULT;
5489 else
5490 init_level = AMDGPU_INIT_LEVEL_RESET_RECOVERY;
5491
5492 r = 0;
5493 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5494 amdgpu_set_init_level(tmp_adev, init_level);
5495 if (full_reset) {
5496 /* post card */
5497 amdgpu_ras_set_fed(tmp_adev, false);
5498 r = amdgpu_device_asic_init(tmp_adev);
5499 if (r) {
5500 dev_warn(tmp_adev->dev, "asic atom init failed!");
5501 } else {
5502 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5503
5504 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5505 if (r)
5506 goto out;
5507
5508 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5509
5510 if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags))
5511 amdgpu_coredump(tmp_adev, false, vram_lost, reset_context->job);
5512
5513 if (vram_lost) {
5514 DRM_INFO("VRAM is lost due to GPU reset!\n");
5515 amdgpu_inc_vram_lost(tmp_adev);
5516 }
5517
5518 r = amdgpu_device_fw_loading(tmp_adev);
5519 if (r)
5520 return r;
5521
5522 r = amdgpu_xcp_restore_partition_mode(
5523 tmp_adev->xcp_mgr);
5524 if (r)
5525 goto out;
5526
5527 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5528 if (r)
5529 goto out;
5530
5531 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5532 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5533
5534 r = amdgpu_device_ip_resume_phase3(tmp_adev);
5535 if (r)
5536 goto out;
5537
5538 if (vram_lost)
5539 amdgpu_device_fill_reset_magic(tmp_adev);
5540
5541 /*
5542 * Add this ASIC as tracked as reset was already
5543 * complete successfully.
5544 */
5545 amdgpu_register_gpu_instance(tmp_adev);
5546
5547 if (!reset_context->hive &&
5548 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5549 amdgpu_xgmi_add_device(tmp_adev);
5550
5551 r = amdgpu_device_ip_late_init(tmp_adev);
5552 if (r)
5553 goto out;
5554
5555 drm_client_dev_resume(adev_to_drm(tmp_adev), false);
5556
5557 /*
5558 * The GPU enters bad state once faulty pages
5559 * by ECC has reached the threshold, and ras
5560 * recovery is scheduled next. So add one check
5561 * here to break recovery if it indeed exceeds
5562 * bad page threshold, and remind user to
5563 * retire this GPU or setting one bigger
5564 * bad_page_threshold value to fix this once
5565 * probing driver again.
5566 */
5567 if (!amdgpu_ras_is_rma(tmp_adev)) {
5568 /* must succeed. */
5569 amdgpu_ras_resume(tmp_adev);
5570 } else {
5571 r = -EINVAL;
5572 goto out;
5573 }
5574
5575 /* Update PSP FW topology after reset */
5576 if (reset_context->hive &&
5577 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5578 r = amdgpu_xgmi_update_topology(
5579 reset_context->hive, tmp_adev);
5580 }
5581 }
5582
5583out:
5584 if (!r) {
5585 /* IP init is complete now, set level as default */
5586 amdgpu_set_init_level(tmp_adev,
5587 AMDGPU_INIT_LEVEL_DEFAULT);
5588 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5589 r = amdgpu_ib_ring_tests(tmp_adev);
5590 if (r) {
5591 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5592 r = -EAGAIN;
5593 goto end;
5594 }
5595 }
5596
5597 if (r)
5598 tmp_adev->asic_reset_res = r;
5599 }
5600
5601end:
5602 return r;
5603}
5604
5605int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5606 struct amdgpu_reset_context *reset_context)
5607{
5608 struct amdgpu_device *tmp_adev = NULL;
5609 bool need_full_reset, skip_hw_reset;
5610 int r = 0;
5611
5612 /* Try reset handler method first */
5613 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5614 reset_list);
5615
5616 reset_context->reset_device_list = device_list_handle;
5617 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5618 /* If reset handler not implemented, continue; otherwise return */
5619 if (r == -EOPNOTSUPP)
5620 r = 0;
5621 else
5622 return r;
5623
5624 /* Reset handler not implemented, use the default method */
5625 need_full_reset =
5626 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5627 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5628
5629 /*
5630 * ASIC reset has to be done on all XGMI hive nodes ASAP
5631 * to allow proper links negotiation in FW (within 1 sec)
5632 */
5633 if (!skip_hw_reset && need_full_reset) {
5634 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5635 /* For XGMI run all resets in parallel to speed up the process */
5636 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5637 if (!queue_work(system_unbound_wq,
5638 &tmp_adev->xgmi_reset_work))
5639 r = -EALREADY;
5640 } else
5641 r = amdgpu_asic_reset(tmp_adev);
5642
5643 if (r) {
5644 dev_err(tmp_adev->dev,
5645 "ASIC reset failed with error, %d for drm dev, %s",
5646 r, adev_to_drm(tmp_adev)->unique);
5647 goto out;
5648 }
5649 }
5650
5651 /* For XGMI wait for all resets to complete before proceed */
5652 if (!r) {
5653 list_for_each_entry(tmp_adev, device_list_handle,
5654 reset_list) {
5655 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5656 flush_work(&tmp_adev->xgmi_reset_work);
5657 r = tmp_adev->asic_reset_res;
5658 if (r)
5659 break;
5660 }
5661 }
5662 }
5663 }
5664
5665 if (!r && amdgpu_ras_intr_triggered()) {
5666 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5667 amdgpu_ras_reset_error_count(tmp_adev,
5668 AMDGPU_RAS_BLOCK__MMHUB);
5669 }
5670
5671 amdgpu_ras_intr_cleared();
5672 }
5673
5674 r = amdgpu_device_reinit_after_reset(reset_context);
5675 if (r == -EAGAIN)
5676 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5677 else
5678 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5679
5680out:
5681 return r;
5682}
5683
5684static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5685{
5686
5687 switch (amdgpu_asic_reset_method(adev)) {
5688 case AMD_RESET_METHOD_MODE1:
5689 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5690 break;
5691 case AMD_RESET_METHOD_MODE2:
5692 adev->mp1_state = PP_MP1_STATE_RESET;
5693 break;
5694 default:
5695 adev->mp1_state = PP_MP1_STATE_NONE;
5696 break;
5697 }
5698}
5699
5700static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5701{
5702 amdgpu_vf_error_trans_all(adev);
5703 adev->mp1_state = PP_MP1_STATE_NONE;
5704}
5705
5706static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5707{
5708 struct pci_dev *p = NULL;
5709
5710 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5711 adev->pdev->bus->number, 1);
5712 if (p) {
5713 pm_runtime_enable(&(p->dev));
5714 pm_runtime_resume(&(p->dev));
5715 }
5716
5717 pci_dev_put(p);
5718}
5719
5720static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5721{
5722 enum amd_reset_method reset_method;
5723 struct pci_dev *p = NULL;
5724 u64 expires;
5725
5726 /*
5727 * For now, only BACO and mode1 reset are confirmed
5728 * to suffer the audio issue without proper suspended.
5729 */
5730 reset_method = amdgpu_asic_reset_method(adev);
5731 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5732 (reset_method != AMD_RESET_METHOD_MODE1))
5733 return -EINVAL;
5734
5735 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5736 adev->pdev->bus->number, 1);
5737 if (!p)
5738 return -ENODEV;
5739
5740 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5741 if (!expires)
5742 /*
5743 * If we cannot get the audio device autosuspend delay,
5744 * a fixed 4S interval will be used. Considering 3S is
5745 * the audio controller default autosuspend delay setting.
5746 * 4S used here is guaranteed to cover that.
5747 */
5748 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5749
5750 while (!pm_runtime_status_suspended(&(p->dev))) {
5751 if (!pm_runtime_suspend(&(p->dev)))
5752 break;
5753
5754 if (expires < ktime_get_mono_fast_ns()) {
5755 dev_warn(adev->dev, "failed to suspend display audio\n");
5756 pci_dev_put(p);
5757 /* TODO: abort the succeeding gpu reset? */
5758 return -ETIMEDOUT;
5759 }
5760 }
5761
5762 pm_runtime_disable(&(p->dev));
5763
5764 pci_dev_put(p);
5765 return 0;
5766}
5767
5768static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5769{
5770 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5771
5772#if defined(CONFIG_DEBUG_FS)
5773 if (!amdgpu_sriov_vf(adev))
5774 cancel_work(&adev->reset_work);
5775#endif
5776
5777 if (adev->kfd.dev)
5778 cancel_work(&adev->kfd.reset_work);
5779
5780 if (amdgpu_sriov_vf(adev))
5781 cancel_work(&adev->virt.flr_work);
5782
5783 if (con && adev->ras_enabled)
5784 cancel_work(&con->recovery_work);
5785
5786}
5787
5788static int amdgpu_device_health_check(struct list_head *device_list_handle)
5789{
5790 struct amdgpu_device *tmp_adev;
5791 int ret = 0;
5792 u32 status;
5793
5794 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5795 pci_read_config_dword(tmp_adev->pdev, PCI_COMMAND, &status);
5796 if (PCI_POSSIBLE_ERROR(status)) {
5797 dev_err(tmp_adev->dev, "device lost from bus!");
5798 ret = -ENODEV;
5799 }
5800 }
5801
5802 return ret;
5803}
5804
5805/**
5806 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5807 *
5808 * @adev: amdgpu_device pointer
5809 * @job: which job trigger hang
5810 * @reset_context: amdgpu reset context pointer
5811 *
5812 * Attempt to reset the GPU if it has hung (all asics).
5813 * Attempt to do soft-reset or full-reset and reinitialize Asic
5814 * Returns 0 for success or an error on failure.
5815 */
5816
5817int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5818 struct amdgpu_job *job,
5819 struct amdgpu_reset_context *reset_context)
5820{
5821 struct list_head device_list, *device_list_handle = NULL;
5822 bool job_signaled = false;
5823 struct amdgpu_hive_info *hive = NULL;
5824 struct amdgpu_device *tmp_adev = NULL;
5825 int i, r = 0;
5826 bool need_emergency_restart = false;
5827 bool audio_suspended = false;
5828 int retry_limit = AMDGPU_MAX_RETRY_LIMIT;
5829
5830 /*
5831 * Special case: RAS triggered and full reset isn't supported
5832 */
5833 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5834
5835 /*
5836 * Flush RAM to disk so that after reboot
5837 * the user can read log and see why the system rebooted.
5838 */
5839 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5840 amdgpu_ras_get_context(adev)->reboot) {
5841 DRM_WARN("Emergency reboot.");
5842
5843 ksys_sync_helper();
5844 emergency_restart();
5845 }
5846
5847 dev_info(adev->dev, "GPU %s begin!\n",
5848 need_emergency_restart ? "jobs stop":"reset");
5849
5850 if (!amdgpu_sriov_vf(adev))
5851 hive = amdgpu_get_xgmi_hive(adev);
5852 if (hive)
5853 mutex_lock(&hive->hive_lock);
5854
5855 reset_context->job = job;
5856 reset_context->hive = hive;
5857 /*
5858 * Build list of devices to reset.
5859 * In case we are in XGMI hive mode, resort the device list
5860 * to put adev in the 1st position.
5861 */
5862 INIT_LIST_HEAD(&device_list);
5863 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) {
5864 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5865 list_add_tail(&tmp_adev->reset_list, &device_list);
5866 if (adev->shutdown)
5867 tmp_adev->shutdown = true;
5868 }
5869 if (!list_is_first(&adev->reset_list, &device_list))
5870 list_rotate_to_front(&adev->reset_list, &device_list);
5871 device_list_handle = &device_list;
5872 } else {
5873 list_add_tail(&adev->reset_list, &device_list);
5874 device_list_handle = &device_list;
5875 }
5876
5877 if (!amdgpu_sriov_vf(adev)) {
5878 r = amdgpu_device_health_check(device_list_handle);
5879 if (r)
5880 goto end_reset;
5881 }
5882
5883 /* We need to lock reset domain only once both for XGMI and single device */
5884 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5885 reset_list);
5886 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5887
5888 /* block all schedulers and reset given job's ring */
5889 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5890
5891 amdgpu_device_set_mp1_state(tmp_adev);
5892
5893 /*
5894 * Try to put the audio codec into suspend state
5895 * before gpu reset started.
5896 *
5897 * Due to the power domain of the graphics device
5898 * is shared with AZ power domain. Without this,
5899 * we may change the audio hardware from behind
5900 * the audio driver's back. That will trigger
5901 * some audio codec errors.
5902 */
5903 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5904 audio_suspended = true;
5905
5906 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5907
5908 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5909
5910 amdgpu_amdkfd_pre_reset(tmp_adev, reset_context);
5911
5912 /*
5913 * Mark these ASICs to be reseted as untracked first
5914 * And add them back after reset completed
5915 */
5916 amdgpu_unregister_gpu_instance(tmp_adev);
5917
5918 drm_client_dev_suspend(adev_to_drm(tmp_adev), false);
5919
5920 /* disable ras on ALL IPs */
5921 if (!need_emergency_restart &&
5922 amdgpu_device_ip_need_full_reset(tmp_adev))
5923 amdgpu_ras_suspend(tmp_adev);
5924
5925 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5926 struct amdgpu_ring *ring = tmp_adev->rings[i];
5927
5928 if (!amdgpu_ring_sched_ready(ring))
5929 continue;
5930
5931 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5932
5933 if (need_emergency_restart)
5934 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5935 }
5936 atomic_inc(&tmp_adev->gpu_reset_counter);
5937 }
5938
5939 if (need_emergency_restart)
5940 goto skip_sched_resume;
5941
5942 /*
5943 * Must check guilty signal here since after this point all old
5944 * HW fences are force signaled.
5945 *
5946 * job->base holds a reference to parent fence
5947 */
5948 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5949 job_signaled = true;
5950 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5951 goto skip_hw_reset;
5952 }
5953
5954retry: /* Rest of adevs pre asic reset from XGMI hive. */
5955 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5956 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5957 /*TODO Should we stop ?*/
5958 if (r) {
5959 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5960 r, adev_to_drm(tmp_adev)->unique);
5961 tmp_adev->asic_reset_res = r;
5962 }
5963 }
5964
5965 /* Actual ASIC resets if needed.*/
5966 /* Host driver will handle XGMI hive reset for SRIOV */
5967 if (amdgpu_sriov_vf(adev)) {
5968 if (amdgpu_ras_get_fed_status(adev) || amdgpu_virt_rcvd_ras_interrupt(adev)) {
5969 dev_dbg(adev->dev, "Detected RAS error, wait for FLR completion\n");
5970 amdgpu_ras_set_fed(adev, true);
5971 set_bit(AMDGPU_HOST_FLR, &reset_context->flags);
5972 }
5973
5974 r = amdgpu_device_reset_sriov(adev, reset_context);
5975 if (AMDGPU_RETRY_SRIOV_RESET(r) && (retry_limit--) > 0) {
5976 amdgpu_virt_release_full_gpu(adev, true);
5977 goto retry;
5978 }
5979 if (r)
5980 adev->asic_reset_res = r;
5981 } else {
5982 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5983 if (r && r == -EAGAIN)
5984 goto retry;
5985 }
5986
5987 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5988 /*
5989 * Drop any pending non scheduler resets queued before reset is done.
5990 * Any reset scheduled after this point would be valid. Scheduler resets
5991 * were already dropped during drm_sched_stop and no new ones can come
5992 * in before drm_sched_start.
5993 */
5994 amdgpu_device_stop_pending_resets(tmp_adev);
5995 }
5996
5997skip_hw_reset:
5998
5999 /* Post ASIC reset for all devs .*/
6000 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
6001
6002 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6003 struct amdgpu_ring *ring = tmp_adev->rings[i];
6004
6005 if (!amdgpu_ring_sched_ready(ring))
6006 continue;
6007
6008 drm_sched_start(&ring->sched, 0);
6009 }
6010
6011 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
6012 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
6013
6014 if (tmp_adev->asic_reset_res)
6015 r = tmp_adev->asic_reset_res;
6016
6017 tmp_adev->asic_reset_res = 0;
6018
6019 if (r) {
6020 /* bad news, how to tell it to userspace ?
6021 * for ras error, we should report GPU bad status instead of
6022 * reset failure
6023 */
6024 if (reset_context->src != AMDGPU_RESET_SRC_RAS ||
6025 !amdgpu_ras_eeprom_check_err_threshold(tmp_adev))
6026 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n",
6027 atomic_read(&tmp_adev->gpu_reset_counter));
6028 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
6029 } else {
6030 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
6031 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
6032 DRM_WARN("smart shift update failed\n");
6033 }
6034 }
6035
6036skip_sched_resume:
6037 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
6038 /* unlock kfd: SRIOV would do it separately */
6039 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
6040 amdgpu_amdkfd_post_reset(tmp_adev);
6041
6042 /* kfd_post_reset will do nothing if kfd device is not initialized,
6043 * need to bring up kfd here if it's not be initialized before
6044 */
6045 if (!adev->kfd.init_complete)
6046 amdgpu_amdkfd_device_init(adev);
6047
6048 if (audio_suspended)
6049 amdgpu_device_resume_display_audio(tmp_adev);
6050
6051 amdgpu_device_unset_mp1_state(tmp_adev);
6052
6053 amdgpu_ras_set_error_query_ready(tmp_adev, true);
6054 }
6055
6056 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
6057 reset_list);
6058 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
6059
6060end_reset:
6061 if (hive) {
6062 mutex_unlock(&hive->hive_lock);
6063 amdgpu_put_xgmi_hive(hive);
6064 }
6065
6066 if (r)
6067 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
6068
6069 atomic_set(&adev->reset_domain->reset_res, r);
6070 return r;
6071}
6072
6073/**
6074 * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner
6075 *
6076 * @adev: amdgpu_device pointer
6077 * @speed: pointer to the speed of the link
6078 * @width: pointer to the width of the link
6079 *
6080 * Evaluate the hierarchy to find the speed and bandwidth capabilities of the
6081 * first physical partner to an AMD dGPU.
6082 * This will exclude any virtual switches and links.
6083 */
6084static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
6085 enum pci_bus_speed *speed,
6086 enum pcie_link_width *width)
6087{
6088 struct pci_dev *parent = adev->pdev;
6089
6090 if (!speed || !width)
6091 return;
6092
6093 *speed = PCI_SPEED_UNKNOWN;
6094 *width = PCIE_LNK_WIDTH_UNKNOWN;
6095
6096 if (amdgpu_device_pcie_dynamic_switching_supported(adev)) {
6097 while ((parent = pci_upstream_bridge(parent))) {
6098 /* skip upstream/downstream switches internal to dGPU*/
6099 if (parent->vendor == PCI_VENDOR_ID_ATI)
6100 continue;
6101 *speed = pcie_get_speed_cap(parent);
6102 *width = pcie_get_width_cap(parent);
6103 break;
6104 }
6105 } else {
6106 /* use the current speeds rather than max if switching is not supported */
6107 pcie_bandwidth_available(adev->pdev, NULL, speed, width);
6108 }
6109}
6110
6111/**
6112 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
6113 *
6114 * @adev: amdgpu_device pointer
6115 *
6116 * Fetchs and stores in the driver the PCIE capabilities (gen speed
6117 * and lanes) of the slot the device is in. Handles APUs and
6118 * virtualized environments where PCIE config space may not be available.
6119 */
6120static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
6121{
6122 struct pci_dev *pdev;
6123 enum pci_bus_speed speed_cap, platform_speed_cap;
6124 enum pcie_link_width platform_link_width;
6125
6126 if (amdgpu_pcie_gen_cap)
6127 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
6128
6129 if (amdgpu_pcie_lane_cap)
6130 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
6131
6132 /* covers APUs as well */
6133 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
6134 if (adev->pm.pcie_gen_mask == 0)
6135 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
6136 if (adev->pm.pcie_mlw_mask == 0)
6137 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
6138 return;
6139 }
6140
6141 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
6142 return;
6143
6144 amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
6145 &platform_link_width);
6146
6147 if (adev->pm.pcie_gen_mask == 0) {
6148 /* asic caps */
6149 pdev = adev->pdev;
6150 speed_cap = pcie_get_speed_cap(pdev);
6151 if (speed_cap == PCI_SPEED_UNKNOWN) {
6152 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6153 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6154 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
6155 } else {
6156 if (speed_cap == PCIE_SPEED_32_0GT)
6157 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6158 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6159 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6160 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
6161 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
6162 else if (speed_cap == PCIE_SPEED_16_0GT)
6163 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6164 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6165 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6166 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
6167 else if (speed_cap == PCIE_SPEED_8_0GT)
6168 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6169 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6170 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
6171 else if (speed_cap == PCIE_SPEED_5_0GT)
6172 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6173 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
6174 else
6175 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
6176 }
6177 /* platform caps */
6178 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
6179 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6180 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
6181 } else {
6182 if (platform_speed_cap == PCIE_SPEED_32_0GT)
6183 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6184 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6185 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6186 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
6187 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
6188 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
6189 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6190 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6191 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6192 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
6193 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
6194 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6195 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6196 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
6197 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
6198 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6199 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
6200 else
6201 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
6202
6203 }
6204 }
6205 if (adev->pm.pcie_mlw_mask == 0) {
6206 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
6207 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
6208 } else {
6209 switch (platform_link_width) {
6210 case PCIE_LNK_X32:
6211 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
6212 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6213 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6214 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6215 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6216 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6217 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6218 break;
6219 case PCIE_LNK_X16:
6220 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6221 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6222 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6223 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6224 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6225 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6226 break;
6227 case PCIE_LNK_X12:
6228 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6229 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6230 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6231 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6232 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6233 break;
6234 case PCIE_LNK_X8:
6235 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6236 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6237 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6238 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6239 break;
6240 case PCIE_LNK_X4:
6241 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6242 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6243 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6244 break;
6245 case PCIE_LNK_X2:
6246 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6247 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6248 break;
6249 case PCIE_LNK_X1:
6250 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
6251 break;
6252 default:
6253 break;
6254 }
6255 }
6256 }
6257}
6258
6259/**
6260 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
6261 *
6262 * @adev: amdgpu_device pointer
6263 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
6264 *
6265 * Return true if @peer_adev can access (DMA) @adev through the PCIe
6266 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
6267 * @peer_adev.
6268 */
6269bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
6270 struct amdgpu_device *peer_adev)
6271{
6272#ifdef CONFIG_HSA_AMD_P2P
6273 bool p2p_access =
6274 !adev->gmc.xgmi.connected_to_cpu &&
6275 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
6276 if (!p2p_access)
6277 dev_info(adev->dev, "PCIe P2P access from peer device %s is not supported by the chipset\n",
6278 pci_name(peer_adev->pdev));
6279
6280 bool is_large_bar = adev->gmc.visible_vram_size &&
6281 adev->gmc.real_vram_size == adev->gmc.visible_vram_size;
6282 bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev);
6283
6284 if (!p2p_addressable) {
6285 uint64_t address_mask = peer_adev->dev->dma_mask ?
6286 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
6287 resource_size_t aper_limit =
6288 adev->gmc.aper_base + adev->gmc.aper_size - 1;
6289
6290 p2p_addressable = !(adev->gmc.aper_base & address_mask ||
6291 aper_limit & address_mask);
6292 }
6293 return pcie_p2p && is_large_bar && p2p_access && p2p_addressable;
6294#else
6295 return false;
6296#endif
6297}
6298
6299int amdgpu_device_baco_enter(struct drm_device *dev)
6300{
6301 struct amdgpu_device *adev = drm_to_adev(dev);
6302 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6303
6304 if (!amdgpu_device_supports_baco(dev))
6305 return -ENOTSUPP;
6306
6307 if (ras && adev->ras_enabled &&
6308 adev->nbio.funcs->enable_doorbell_interrupt)
6309 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
6310
6311 return amdgpu_dpm_baco_enter(adev);
6312}
6313
6314int amdgpu_device_baco_exit(struct drm_device *dev)
6315{
6316 struct amdgpu_device *adev = drm_to_adev(dev);
6317 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6318 int ret = 0;
6319
6320 if (!amdgpu_device_supports_baco(dev))
6321 return -ENOTSUPP;
6322
6323 ret = amdgpu_dpm_baco_exit(adev);
6324 if (ret)
6325 return ret;
6326
6327 if (ras && adev->ras_enabled &&
6328 adev->nbio.funcs->enable_doorbell_interrupt)
6329 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
6330
6331 if (amdgpu_passthrough(adev) && adev->nbio.funcs &&
6332 adev->nbio.funcs->clear_doorbell_interrupt)
6333 adev->nbio.funcs->clear_doorbell_interrupt(adev);
6334
6335 return 0;
6336}
6337
6338/**
6339 * amdgpu_pci_error_detected - Called when a PCI error is detected.
6340 * @pdev: PCI device struct
6341 * @state: PCI channel state
6342 *
6343 * Description: Called when a PCI error is detected.
6344 *
6345 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
6346 */
6347pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6348{
6349 struct drm_device *dev = pci_get_drvdata(pdev);
6350 struct amdgpu_device *adev = drm_to_adev(dev);
6351 int i;
6352
6353 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
6354
6355 if (adev->gmc.xgmi.num_physical_nodes > 1) {
6356 DRM_WARN("No support for XGMI hive yet...");
6357 return PCI_ERS_RESULT_DISCONNECT;
6358 }
6359
6360 adev->pci_channel_state = state;
6361
6362 switch (state) {
6363 case pci_channel_io_normal:
6364 return PCI_ERS_RESULT_CAN_RECOVER;
6365 /* Fatal error, prepare for slot reset */
6366 case pci_channel_io_frozen:
6367 /*
6368 * Locking adev->reset_domain->sem will prevent any external access
6369 * to GPU during PCI error recovery
6370 */
6371 amdgpu_device_lock_reset_domain(adev->reset_domain);
6372 amdgpu_device_set_mp1_state(adev);
6373
6374 /*
6375 * Block any work scheduling as we do for regular GPU reset
6376 * for the duration of the recovery
6377 */
6378 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6379 struct amdgpu_ring *ring = adev->rings[i];
6380
6381 if (!amdgpu_ring_sched_ready(ring))
6382 continue;
6383
6384 drm_sched_stop(&ring->sched, NULL);
6385 }
6386 atomic_inc(&adev->gpu_reset_counter);
6387 return PCI_ERS_RESULT_NEED_RESET;
6388 case pci_channel_io_perm_failure:
6389 /* Permanent error, prepare for device removal */
6390 return PCI_ERS_RESULT_DISCONNECT;
6391 }
6392
6393 return PCI_ERS_RESULT_NEED_RESET;
6394}
6395
6396/**
6397 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6398 * @pdev: pointer to PCI device
6399 */
6400pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6401{
6402
6403 DRM_INFO("PCI error: mmio enabled callback!!\n");
6404
6405 /* TODO - dump whatever for debugging purposes */
6406
6407 /* This called only if amdgpu_pci_error_detected returns
6408 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6409 * works, no need to reset slot.
6410 */
6411
6412 return PCI_ERS_RESULT_RECOVERED;
6413}
6414
6415/**
6416 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6417 * @pdev: PCI device struct
6418 *
6419 * Description: This routine is called by the pci error recovery
6420 * code after the PCI slot has been reset, just before we
6421 * should resume normal operations.
6422 */
6423pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6424{
6425 struct drm_device *dev = pci_get_drvdata(pdev);
6426 struct amdgpu_device *adev = drm_to_adev(dev);
6427 int r, i;
6428 struct amdgpu_reset_context reset_context;
6429 u32 memsize;
6430 struct list_head device_list;
6431
6432 /* PCI error slot reset should be skipped During RAS recovery */
6433 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
6434 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) &&
6435 amdgpu_ras_in_recovery(adev))
6436 return PCI_ERS_RESULT_RECOVERED;
6437
6438 DRM_INFO("PCI error: slot reset callback!!\n");
6439
6440 memset(&reset_context, 0, sizeof(reset_context));
6441
6442 INIT_LIST_HEAD(&device_list);
6443 list_add_tail(&adev->reset_list, &device_list);
6444
6445 /* wait for asic to come out of reset */
6446 msleep(500);
6447
6448 /* Restore PCI confspace */
6449 amdgpu_device_load_pci_state(pdev);
6450
6451 /* confirm ASIC came out of reset */
6452 for (i = 0; i < adev->usec_timeout; i++) {
6453 memsize = amdgpu_asic_get_config_memsize(adev);
6454
6455 if (memsize != 0xffffffff)
6456 break;
6457 udelay(1);
6458 }
6459 if (memsize == 0xffffffff) {
6460 r = -ETIME;
6461 goto out;
6462 }
6463
6464 reset_context.method = AMD_RESET_METHOD_NONE;
6465 reset_context.reset_req_dev = adev;
6466 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6467 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6468
6469 adev->no_hw_access = true;
6470 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6471 adev->no_hw_access = false;
6472 if (r)
6473 goto out;
6474
6475 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6476
6477out:
6478 if (!r) {
6479 if (amdgpu_device_cache_pci_state(adev->pdev))
6480 pci_restore_state(adev->pdev);
6481
6482 DRM_INFO("PCIe error recovery succeeded\n");
6483 } else {
6484 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6485 amdgpu_device_unset_mp1_state(adev);
6486 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6487 }
6488
6489 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6490}
6491
6492/**
6493 * amdgpu_pci_resume() - resume normal ops after PCI reset
6494 * @pdev: pointer to PCI device
6495 *
6496 * Called when the error recovery driver tells us that its
6497 * OK to resume normal operation.
6498 */
6499void amdgpu_pci_resume(struct pci_dev *pdev)
6500{
6501 struct drm_device *dev = pci_get_drvdata(pdev);
6502 struct amdgpu_device *adev = drm_to_adev(dev);
6503 int i;
6504
6505
6506 DRM_INFO("PCI error: resume callback!!\n");
6507
6508 /* Only continue execution for the case of pci_channel_io_frozen */
6509 if (adev->pci_channel_state != pci_channel_io_frozen)
6510 return;
6511
6512 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6513 struct amdgpu_ring *ring = adev->rings[i];
6514
6515 if (!amdgpu_ring_sched_ready(ring))
6516 continue;
6517
6518 drm_sched_start(&ring->sched, 0);
6519 }
6520
6521 amdgpu_device_unset_mp1_state(adev);
6522 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6523}
6524
6525bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6526{
6527 struct drm_device *dev = pci_get_drvdata(pdev);
6528 struct amdgpu_device *adev = drm_to_adev(dev);
6529 int r;
6530
6531 if (amdgpu_sriov_vf(adev))
6532 return false;
6533
6534 r = pci_save_state(pdev);
6535 if (!r) {
6536 kfree(adev->pci_state);
6537
6538 adev->pci_state = pci_store_saved_state(pdev);
6539
6540 if (!adev->pci_state) {
6541 DRM_ERROR("Failed to store PCI saved state");
6542 return false;
6543 }
6544 } else {
6545 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6546 return false;
6547 }
6548
6549 return true;
6550}
6551
6552bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6553{
6554 struct drm_device *dev = pci_get_drvdata(pdev);
6555 struct amdgpu_device *adev = drm_to_adev(dev);
6556 int r;
6557
6558 if (!adev->pci_state)
6559 return false;
6560
6561 r = pci_load_saved_state(pdev, adev->pci_state);
6562
6563 if (!r) {
6564 pci_restore_state(pdev);
6565 } else {
6566 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6567 return false;
6568 }
6569
6570 return true;
6571}
6572
6573void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6574 struct amdgpu_ring *ring)
6575{
6576#ifdef CONFIG_X86_64
6577 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6578 return;
6579#endif
6580 if (adev->gmc.xgmi.connected_to_cpu)
6581 return;
6582
6583 if (ring && ring->funcs->emit_hdp_flush)
6584 amdgpu_ring_emit_hdp_flush(ring);
6585 else
6586 amdgpu_asic_flush_hdp(adev, ring);
6587}
6588
6589void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6590 struct amdgpu_ring *ring)
6591{
6592#ifdef CONFIG_X86_64
6593 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6594 return;
6595#endif
6596 if (adev->gmc.xgmi.connected_to_cpu)
6597 return;
6598
6599 amdgpu_asic_invalidate_hdp(adev, ring);
6600}
6601
6602int amdgpu_in_reset(struct amdgpu_device *adev)
6603{
6604 return atomic_read(&adev->reset_domain->in_gpu_reset);
6605}
6606
6607/**
6608 * amdgpu_device_halt() - bring hardware to some kind of halt state
6609 *
6610 * @adev: amdgpu_device pointer
6611 *
6612 * Bring hardware to some kind of halt state so that no one can touch it
6613 * any more. It will help to maintain error context when error occurred.
6614 * Compare to a simple hang, the system will keep stable at least for SSH
6615 * access. Then it should be trivial to inspect the hardware state and
6616 * see what's going on. Implemented as following:
6617 *
6618 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6619 * clears all CPU mappings to device, disallows remappings through page faults
6620 * 2. amdgpu_irq_disable_all() disables all interrupts
6621 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6622 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6623 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6624 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6625 * flush any in flight DMA operations
6626 */
6627void amdgpu_device_halt(struct amdgpu_device *adev)
6628{
6629 struct pci_dev *pdev = adev->pdev;
6630 struct drm_device *ddev = adev_to_drm(adev);
6631
6632 amdgpu_xcp_dev_unplug(adev);
6633 drm_dev_unplug(ddev);
6634
6635 amdgpu_irq_disable_all(adev);
6636
6637 amdgpu_fence_driver_hw_fini(adev);
6638
6639 adev->no_hw_access = true;
6640
6641 amdgpu_device_unmap_mmio(adev);
6642
6643 pci_disable_device(pdev);
6644 pci_wait_for_pending_transaction(pdev);
6645}
6646
6647u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6648 u32 reg)
6649{
6650 unsigned long flags, address, data;
6651 u32 r;
6652
6653 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6654 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6655
6656 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6657 WREG32(address, reg * 4);
6658 (void)RREG32(address);
6659 r = RREG32(data);
6660 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6661 return r;
6662}
6663
6664void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6665 u32 reg, u32 v)
6666{
6667 unsigned long flags, address, data;
6668
6669 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6670 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6671
6672 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6673 WREG32(address, reg * 4);
6674 (void)RREG32(address);
6675 WREG32(data, v);
6676 (void)RREG32(data);
6677 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6678}
6679
6680/**
6681 * amdgpu_device_get_gang - return a reference to the current gang
6682 * @adev: amdgpu_device pointer
6683 *
6684 * Returns: A new reference to the current gang leader.
6685 */
6686struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev)
6687{
6688 struct dma_fence *fence;
6689
6690 rcu_read_lock();
6691 fence = dma_fence_get_rcu_safe(&adev->gang_submit);
6692 rcu_read_unlock();
6693 return fence;
6694}
6695
6696/**
6697 * amdgpu_device_switch_gang - switch to a new gang
6698 * @adev: amdgpu_device pointer
6699 * @gang: the gang to switch to
6700 *
6701 * Try to switch to a new gang.
6702 * Returns: NULL if we switched to the new gang or a reference to the current
6703 * gang leader.
6704 */
6705struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6706 struct dma_fence *gang)
6707{
6708 struct dma_fence *old = NULL;
6709
6710 do {
6711 dma_fence_put(old);
6712 old = amdgpu_device_get_gang(adev);
6713 if (old == gang)
6714 break;
6715
6716 if (!dma_fence_is_signaled(old))
6717 return old;
6718
6719 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6720 old, gang) != old);
6721
6722 dma_fence_put(old);
6723 return NULL;
6724}
6725
6726bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6727{
6728 switch (adev->asic_type) {
6729#ifdef CONFIG_DRM_AMDGPU_SI
6730 case CHIP_HAINAN:
6731#endif
6732 case CHIP_TOPAZ:
6733 /* chips with no display hardware */
6734 return false;
6735#ifdef CONFIG_DRM_AMDGPU_SI
6736 case CHIP_TAHITI:
6737 case CHIP_PITCAIRN:
6738 case CHIP_VERDE:
6739 case CHIP_OLAND:
6740#endif
6741#ifdef CONFIG_DRM_AMDGPU_CIK
6742 case CHIP_BONAIRE:
6743 case CHIP_HAWAII:
6744 case CHIP_KAVERI:
6745 case CHIP_KABINI:
6746 case CHIP_MULLINS:
6747#endif
6748 case CHIP_TONGA:
6749 case CHIP_FIJI:
6750 case CHIP_POLARIS10:
6751 case CHIP_POLARIS11:
6752 case CHIP_POLARIS12:
6753 case CHIP_VEGAM:
6754 case CHIP_CARRIZO:
6755 case CHIP_STONEY:
6756 /* chips with display hardware */
6757 return true;
6758 default:
6759 /* IP discovery */
6760 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6761 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6762 return false;
6763 return true;
6764 }
6765}
6766
6767uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6768 uint32_t inst, uint32_t reg_addr, char reg_name[],
6769 uint32_t expected_value, uint32_t mask)
6770{
6771 uint32_t ret = 0;
6772 uint32_t old_ = 0;
6773 uint32_t tmp_ = RREG32(reg_addr);
6774 uint32_t loop = adev->usec_timeout;
6775
6776 while ((tmp_ & (mask)) != (expected_value)) {
6777 if (old_ != tmp_) {
6778 loop = adev->usec_timeout;
6779 old_ = tmp_;
6780 } else
6781 udelay(1);
6782 tmp_ = RREG32(reg_addr);
6783 loop--;
6784 if (!loop) {
6785 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6786 inst, reg_name, (uint32_t)expected_value,
6787 (uint32_t)(tmp_ & (mask)));
6788 ret = -ETIMEDOUT;
6789 break;
6790 }
6791 }
6792 return ret;
6793}
6794
6795ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring)
6796{
6797 ssize_t size = 0;
6798
6799 if (!ring || !ring->adev)
6800 return size;
6801
6802 if (amdgpu_device_should_recover_gpu(ring->adev))
6803 size |= AMDGPU_RESET_TYPE_FULL;
6804
6805 if (unlikely(!ring->adev->debug_disable_soft_recovery) &&
6806 !amdgpu_sriov_vf(ring->adev) && ring->funcs->soft_recovery)
6807 size |= AMDGPU_RESET_TYPE_SOFT_RESET;
6808
6809 return size;
6810}
6811
6812ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset)
6813{
6814 ssize_t size = 0;
6815
6816 if (supported_reset == 0) {
6817 size += sysfs_emit_at(buf, size, "unsupported");
6818 size += sysfs_emit_at(buf, size, "\n");
6819 return size;
6820
6821 }
6822
6823 if (supported_reset & AMDGPU_RESET_TYPE_SOFT_RESET)
6824 size += sysfs_emit_at(buf, size, "soft ");
6825
6826 if (supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
6827 size += sysfs_emit_at(buf, size, "queue ");
6828
6829 if (supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)
6830 size += sysfs_emit_at(buf, size, "pipe ");
6831
6832 if (supported_reset & AMDGPU_RESET_TYPE_FULL)
6833 size += sysfs_emit_at(buf, size, "full ");
6834
6835 size += sysfs_emit_at(buf, size, "\n");
6836 return size;
6837}