Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * KUnit test for the FPGA Manager
4 *
5 * Copyright (C) 2023 Red Hat, Inc.
6 *
7 * Author: Marco Pagani <marpagan@redhat.com>
8 */
9
10#include <kunit/test.h>
11#include <linux/device.h>
12#include <linux/fpga/fpga-mgr.h>
13#include <linux/module.h>
14#include <linux/scatterlist.h>
15#include <linux/types.h>
16
17#define HEADER_FILL 'H'
18#define IMAGE_FILL 'P'
19#define IMAGE_BLOCK 1024
20
21#define HEADER_SIZE IMAGE_BLOCK
22#define IMAGE_SIZE (IMAGE_BLOCK * 4)
23
24struct mgr_stats {
25 bool header_match;
26 bool image_match;
27 u32 seq_num;
28 u32 op_parse_header_seq;
29 u32 op_write_init_seq;
30 u32 op_write_seq;
31 u32 op_write_sg_seq;
32 u32 op_write_complete_seq;
33 enum fpga_mgr_states op_parse_header_state;
34 enum fpga_mgr_states op_write_init_state;
35 enum fpga_mgr_states op_write_state;
36 enum fpga_mgr_states op_write_sg_state;
37 enum fpga_mgr_states op_write_complete_state;
38};
39
40struct mgr_ctx {
41 struct fpga_image_info *img_info;
42 struct fpga_manager *mgr;
43 struct platform_device *pdev;
44 struct mgr_stats stats;
45};
46
47/**
48 * init_test_buffer() - Allocate and initialize a test image in a buffer.
49 * @test: KUnit test context object.
50 * @count: image size in bytes.
51 *
52 * Return: pointer to the newly allocated image.
53 */
54static char *init_test_buffer(struct kunit *test, size_t count)
55{
56 char *buf;
57
58 KUNIT_ASSERT_GE(test, count, HEADER_SIZE);
59
60 buf = kunit_kzalloc(test, count, GFP_KERNEL);
61 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf);
62
63 memset(buf, HEADER_FILL, HEADER_SIZE);
64 memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE);
65
66 return buf;
67}
68
69/*
70 * Check the image header. Do not return an error code if the image check fails
71 * since, in this case, it is a failure of the FPGA manager itself, not this
72 * op that tests it.
73 */
74static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info,
75 const char *buf, size_t count)
76{
77 struct mgr_stats *stats = mgr->priv;
78 size_t i;
79
80 stats->op_parse_header_state = mgr->state;
81 stats->op_parse_header_seq = stats->seq_num++;
82
83 /* Set header_size and data_size for later */
84 info->header_size = HEADER_SIZE;
85 info->data_size = info->count - HEADER_SIZE;
86
87 stats->header_match = true;
88 for (i = 0; i < info->header_size; i++) {
89 if (buf[i] != HEADER_FILL) {
90 stats->header_match = false;
91 break;
92 }
93 }
94
95 return 0;
96}
97
98static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info,
99 const char *buf, size_t count)
100{
101 struct mgr_stats *stats = mgr->priv;
102
103 stats->op_write_init_state = mgr->state;
104 stats->op_write_init_seq = stats->seq_num++;
105
106 return 0;
107}
108
109/*
110 * Check the image data. As with op_parse_header, do not return an error code
111 * if the image check fails.
112 */
113static int op_write(struct fpga_manager *mgr, const char *buf, size_t count)
114{
115 struct mgr_stats *stats = mgr->priv;
116 size_t i;
117
118 stats->op_write_state = mgr->state;
119 stats->op_write_seq = stats->seq_num++;
120
121 stats->image_match = true;
122 for (i = 0; i < count; i++) {
123 if (buf[i] != IMAGE_FILL) {
124 stats->image_match = false;
125 break;
126 }
127 }
128
129 return 0;
130}
131
132/*
133 * Check the image data, but first skip the header since write_sg will get
134 * the whole image in sg_table. As with op_parse_header, do not return an
135 * error code if the image check fails.
136 */
137static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt)
138{
139 struct mgr_stats *stats = mgr->priv;
140 struct sg_mapping_iter miter;
141 char *img;
142 size_t i;
143
144 stats->op_write_sg_state = mgr->state;
145 stats->op_write_sg_seq = stats->seq_num++;
146
147 stats->image_match = true;
148 sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
149
150 if (!sg_miter_skip(&miter, HEADER_SIZE)) {
151 stats->image_match = false;
152 goto out;
153 }
154
155 while (sg_miter_next(&miter)) {
156 img = miter.addr;
157 for (i = 0; i < miter.length; i++) {
158 if (img[i] != IMAGE_FILL) {
159 stats->image_match = false;
160 goto out;
161 }
162 }
163 }
164out:
165 sg_miter_stop(&miter);
166 return 0;
167}
168
169static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info)
170{
171 struct mgr_stats *stats = mgr->priv;
172
173 stats->op_write_complete_state = mgr->state;
174 stats->op_write_complete_seq = stats->seq_num++;
175
176 return 0;
177}
178
179/*
180 * Fake FPGA manager that implements all ops required to check the programming
181 * sequence using a single contiguous buffer and a scatter gather table.
182 */
183static const struct fpga_manager_ops fake_mgr_ops = {
184 .skip_header = true,
185 .parse_header = op_parse_header,
186 .write_init = op_write_init,
187 .write = op_write,
188 .write_sg = op_write_sg,
189 .write_complete = op_write_complete,
190};
191
192static void fpga_mgr_test_get(struct kunit *test)
193{
194 struct mgr_ctx *ctx = test->priv;
195 struct fpga_manager *mgr;
196
197 mgr = fpga_mgr_get(&ctx->pdev->dev);
198 KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr);
199
200 fpga_mgr_put(ctx->mgr);
201}
202
203static void fpga_mgr_test_lock(struct kunit *test)
204{
205 struct mgr_ctx *ctx = test->priv;
206 int ret;
207
208 ret = fpga_mgr_lock(ctx->mgr);
209 KUNIT_EXPECT_EQ(test, ret, 0);
210
211 ret = fpga_mgr_lock(ctx->mgr);
212 KUNIT_EXPECT_EQ(test, ret, -EBUSY);
213
214 fpga_mgr_unlock(ctx->mgr);
215}
216
217/* Check the programming sequence using an image in a buffer */
218static void fpga_mgr_test_img_load_buf(struct kunit *test)
219{
220 struct mgr_ctx *ctx = test->priv;
221 char *img_buf;
222 int ret;
223
224 img_buf = init_test_buffer(test, IMAGE_SIZE);
225
226 ctx->img_info->count = IMAGE_SIZE;
227 ctx->img_info->buf = img_buf;
228
229 ret = fpga_mgr_load(ctx->mgr, ctx->img_info);
230 KUNIT_EXPECT_EQ(test, ret, 0);
231
232 KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);
233 KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);
234
235 KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);
236 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);
237 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE);
238 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);
239
240 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);
241 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2);
242 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);
243}
244
245/* Check the programming sequence using an image in a scatter gather table */
246static void fpga_mgr_test_img_load_sgt(struct kunit *test)
247{
248 struct mgr_ctx *ctx = test->priv;
249 struct sg_table *sgt;
250 char *img_buf;
251 int ret;
252
253 img_buf = init_test_buffer(test, IMAGE_SIZE);
254
255 sgt = kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL);
256 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
257 KUNIT_ASSERT_EQ(test, ret, 0);
258 sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE);
259
260 ctx->img_info->sgt = sgt;
261
262 ret = fpga_mgr_load(ctx->mgr, ctx->img_info);
263 KUNIT_EXPECT_EQ(test, ret, 0);
264
265 KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);
266 KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);
267
268 KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);
269 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);
270 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE);
271 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);
272
273 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);
274 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2);
275 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);
276
277 sg_free_table(ctx->img_info->sgt);
278}
279
280static int fpga_mgr_test_init(struct kunit *test)
281{
282 struct mgr_ctx *ctx;
283
284 ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
285 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx);
286
287 ctx->pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0);
288 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev);
289
290 ctx->mgr = devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager", &fake_mgr_ops,
291 &ctx->stats);
292 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr));
293
294 ctx->img_info = fpga_image_info_alloc(&ctx->pdev->dev);
295 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info);
296
297 test->priv = ctx;
298
299 return 0;
300}
301
302static void fpga_mgr_test_exit(struct kunit *test)
303{
304 struct mgr_ctx *ctx = test->priv;
305
306 fpga_image_info_free(ctx->img_info);
307 platform_device_unregister(ctx->pdev);
308}
309
310static struct kunit_case fpga_mgr_test_cases[] = {
311 KUNIT_CASE(fpga_mgr_test_get),
312 KUNIT_CASE(fpga_mgr_test_lock),
313 KUNIT_CASE(fpga_mgr_test_img_load_buf),
314 KUNIT_CASE(fpga_mgr_test_img_load_sgt),
315 {}
316};
317
318static struct kunit_suite fpga_mgr_suite = {
319 .name = "fpga_mgr",
320 .init = fpga_mgr_test_init,
321 .exit = fpga_mgr_test_exit,
322 .test_cases = fpga_mgr_test_cases,
323};
324
325kunit_test_suite(fpga_mgr_suite);
326
327MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * KUnit test for the FPGA Manager
4 *
5 * Copyright (C) 2023 Red Hat, Inc.
6 *
7 * Author: Marco Pagani <marpagan@redhat.com>
8 */
9
10#include <kunit/device.h>
11#include <kunit/test.h>
12#include <linux/fpga/fpga-mgr.h>
13#include <linux/module.h>
14#include <linux/scatterlist.h>
15#include <linux/types.h>
16
17#define HEADER_FILL 'H'
18#define IMAGE_FILL 'P'
19#define IMAGE_BLOCK 1024
20
21#define HEADER_SIZE IMAGE_BLOCK
22#define IMAGE_SIZE (IMAGE_BLOCK * 4)
23
24struct mgr_stats {
25 bool header_match;
26 bool image_match;
27 u32 seq_num;
28 u32 op_parse_header_seq;
29 u32 op_write_init_seq;
30 u32 op_write_seq;
31 u32 op_write_sg_seq;
32 u32 op_write_complete_seq;
33 enum fpga_mgr_states op_parse_header_state;
34 enum fpga_mgr_states op_write_init_state;
35 enum fpga_mgr_states op_write_state;
36 enum fpga_mgr_states op_write_sg_state;
37 enum fpga_mgr_states op_write_complete_state;
38};
39
40struct mgr_ctx {
41 struct fpga_image_info *img_info;
42 struct fpga_manager *mgr;
43 struct device *dev;
44 struct mgr_stats stats;
45};
46
47/*
48 * Wrappers to avoid cast warnings when passing action functions directly
49 * to kunit_add_action().
50 */
51KUNIT_DEFINE_ACTION_WRAPPER(sg_free_table_wrapper, sg_free_table,
52 struct sg_table *);
53
54KUNIT_DEFINE_ACTION_WRAPPER(fpga_image_info_free_wrapper, fpga_image_info_free,
55 struct fpga_image_info *);
56
57/**
58 * init_test_buffer() - Allocate and initialize a test image in a buffer.
59 * @test: KUnit test context object.
60 * @count: image size in bytes.
61 *
62 * Return: pointer to the newly allocated image.
63 */
64static char *init_test_buffer(struct kunit *test, size_t count)
65{
66 char *buf;
67
68 KUNIT_ASSERT_GE(test, count, HEADER_SIZE);
69
70 buf = kunit_kzalloc(test, count, GFP_KERNEL);
71 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf);
72
73 memset(buf, HEADER_FILL, HEADER_SIZE);
74 memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE);
75
76 return buf;
77}
78
79/*
80 * Check the image header. Do not return an error code if the image check fails
81 * since, in this case, it is a failure of the FPGA manager itself, not this
82 * op that tests it.
83 */
84static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info,
85 const char *buf, size_t count)
86{
87 struct mgr_stats *stats = mgr->priv;
88 size_t i;
89
90 stats->op_parse_header_state = mgr->state;
91 stats->op_parse_header_seq = stats->seq_num++;
92
93 /* Set header_size and data_size for later */
94 info->header_size = HEADER_SIZE;
95 info->data_size = info->count - HEADER_SIZE;
96
97 stats->header_match = true;
98 for (i = 0; i < info->header_size; i++) {
99 if (buf[i] != HEADER_FILL) {
100 stats->header_match = false;
101 break;
102 }
103 }
104
105 return 0;
106}
107
108static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info,
109 const char *buf, size_t count)
110{
111 struct mgr_stats *stats = mgr->priv;
112
113 stats->op_write_init_state = mgr->state;
114 stats->op_write_init_seq = stats->seq_num++;
115
116 return 0;
117}
118
119/*
120 * Check the image data. As with op_parse_header, do not return an error code
121 * if the image check fails.
122 */
123static int op_write(struct fpga_manager *mgr, const char *buf, size_t count)
124{
125 struct mgr_stats *stats = mgr->priv;
126 size_t i;
127
128 stats->op_write_state = mgr->state;
129 stats->op_write_seq = stats->seq_num++;
130
131 stats->image_match = true;
132 for (i = 0; i < count; i++) {
133 if (buf[i] != IMAGE_FILL) {
134 stats->image_match = false;
135 break;
136 }
137 }
138
139 return 0;
140}
141
142/*
143 * Check the image data, but first skip the header since write_sg will get
144 * the whole image in sg_table. As with op_parse_header, do not return an
145 * error code if the image check fails.
146 */
147static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt)
148{
149 struct mgr_stats *stats = mgr->priv;
150 struct sg_mapping_iter miter;
151 char *img;
152 size_t i;
153
154 stats->op_write_sg_state = mgr->state;
155 stats->op_write_sg_seq = stats->seq_num++;
156
157 stats->image_match = true;
158 sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
159
160 if (!sg_miter_skip(&miter, HEADER_SIZE)) {
161 stats->image_match = false;
162 goto out;
163 }
164
165 while (sg_miter_next(&miter)) {
166 img = miter.addr;
167 for (i = 0; i < miter.length; i++) {
168 if (img[i] != IMAGE_FILL) {
169 stats->image_match = false;
170 goto out;
171 }
172 }
173 }
174out:
175 sg_miter_stop(&miter);
176 return 0;
177}
178
179static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info)
180{
181 struct mgr_stats *stats = mgr->priv;
182
183 stats->op_write_complete_state = mgr->state;
184 stats->op_write_complete_seq = stats->seq_num++;
185
186 return 0;
187}
188
189/*
190 * Fake FPGA manager that implements all ops required to check the programming
191 * sequence using a single contiguous buffer and a scatter gather table.
192 */
193static const struct fpga_manager_ops fake_mgr_ops = {
194 .skip_header = true,
195 .parse_header = op_parse_header,
196 .write_init = op_write_init,
197 .write = op_write,
198 .write_sg = op_write_sg,
199 .write_complete = op_write_complete,
200};
201
202static void fpga_mgr_test_get(struct kunit *test)
203{
204 struct mgr_ctx *ctx = test->priv;
205 struct fpga_manager *mgr;
206
207 mgr = fpga_mgr_get(ctx->dev);
208 KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr);
209
210 fpga_mgr_put(ctx->mgr);
211}
212
213static void fpga_mgr_test_lock(struct kunit *test)
214{
215 struct mgr_ctx *ctx = test->priv;
216 int ret;
217
218 ret = fpga_mgr_lock(ctx->mgr);
219 KUNIT_EXPECT_EQ(test, ret, 0);
220
221 ret = fpga_mgr_lock(ctx->mgr);
222 KUNIT_EXPECT_EQ(test, ret, -EBUSY);
223
224 fpga_mgr_unlock(ctx->mgr);
225}
226
227/* Check the programming sequence using an image in a buffer */
228static void fpga_mgr_test_img_load_buf(struct kunit *test)
229{
230 struct mgr_ctx *ctx = test->priv;
231 char *img_buf;
232 int ret;
233
234 img_buf = init_test_buffer(test, IMAGE_SIZE);
235
236 ctx->img_info->count = IMAGE_SIZE;
237 ctx->img_info->buf = img_buf;
238
239 ret = fpga_mgr_load(ctx->mgr, ctx->img_info);
240 KUNIT_EXPECT_EQ(test, ret, 0);
241
242 KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);
243 KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);
244
245 KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);
246 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);
247 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE);
248 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);
249
250 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);
251 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2);
252 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);
253}
254
255/* Check the programming sequence using an image in a scatter gather table */
256static void fpga_mgr_test_img_load_sgt(struct kunit *test)
257{
258 struct mgr_ctx *ctx = test->priv;
259 struct sg_table *sgt;
260 char *img_buf;
261 int ret;
262
263 img_buf = init_test_buffer(test, IMAGE_SIZE);
264
265 sgt = kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL);
266 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
267 KUNIT_ASSERT_EQ(test, ret, 0);
268 sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE);
269
270 ret = kunit_add_action_or_reset(test, sg_free_table_wrapper, sgt);
271 KUNIT_ASSERT_EQ(test, ret, 0);
272
273 ctx->img_info->sgt = sgt;
274
275 ret = fpga_mgr_load(ctx->mgr, ctx->img_info);
276 KUNIT_EXPECT_EQ(test, ret, 0);
277
278 KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);
279 KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);
280
281 KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);
282 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);
283 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE);
284 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);
285
286 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);
287 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2);
288 KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);
289}
290
291static int fpga_mgr_test_init(struct kunit *test)
292{
293 struct mgr_ctx *ctx;
294 int ret;
295
296 ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
297 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx);
298
299 ctx->dev = kunit_device_register(test, "fpga-manager-test-dev");
300 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->dev);
301
302 ctx->mgr = devm_fpga_mgr_register(ctx->dev, "Fake FPGA Manager", &fake_mgr_ops,
303 &ctx->stats);
304 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr));
305
306 ctx->img_info = fpga_image_info_alloc(ctx->dev);
307 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info);
308
309 ret = kunit_add_action_or_reset(test, fpga_image_info_free_wrapper, ctx->img_info);
310 KUNIT_ASSERT_EQ(test, ret, 0);
311
312 test->priv = ctx;
313
314 return 0;
315}
316
317static struct kunit_case fpga_mgr_test_cases[] = {
318 KUNIT_CASE(fpga_mgr_test_get),
319 KUNIT_CASE(fpga_mgr_test_lock),
320 KUNIT_CASE(fpga_mgr_test_img_load_buf),
321 KUNIT_CASE(fpga_mgr_test_img_load_sgt),
322 {}
323};
324
325static struct kunit_suite fpga_mgr_suite = {
326 .name = "fpga_mgr",
327 .init = fpga_mgr_test_init,
328 .test_cases = fpga_mgr_test_cases,
329};
330
331kunit_test_suite(fpga_mgr_suite);
332
333MODULE_LICENSE("GPL");