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1// SPDX-License-Identifier: GPL-2.0+
2/* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
4 *
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
7 */
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/platform_device.h>
13#include <linux/sys_soc.h>
14#include <linux/fsl/mc.h>
15
16#include "compat.h"
17#include "debugfs.h"
18#include "regs.h"
19#include "intern.h"
20#include "jr.h"
21#include "desc_constr.h"
22#include "ctrl.h"
23
24bool caam_dpaa2;
25EXPORT_SYMBOL(caam_dpaa2);
26
27#ifdef CONFIG_CAAM_QI
28#include "qi.h"
29#endif
30
31/*
32 * Descriptor to instantiate RNG State Handle 0 in normal mode and
33 * load the JDKEK, TDKEK and TDSK registers
34 */
35static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
36{
37 u32 *jump_cmd, op_flags;
38
39 init_job_desc(desc, 0);
40
41 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
42 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
43 OP_ALG_PR_ON;
44
45 /* INIT RNG in non-test mode */
46 append_operation(desc, op_flags);
47
48 if (!handle && do_sk) {
49 /*
50 * For SH0, Secure Keys must be generated as well
51 */
52
53 /* wait for done */
54 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
55 set_jump_tgt_here(desc, jump_cmd);
56
57 /*
58 * load 1 to clear written reg:
59 * resets the done interrupt and returns the RNG to idle.
60 */
61 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
62
63 /* Initialize State Handle */
64 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
65 OP_ALG_AAI_RNG4_SK);
66 }
67
68 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
69}
70
71/* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
72static void build_deinstantiation_desc(u32 *desc, int handle)
73{
74 init_job_desc(desc, 0);
75
76 /* Uninstantiate State Handle 0 */
77 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
78 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
79
80 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
81}
82
83static const struct of_device_id imx8m_machine_match[] = {
84 { .compatible = "fsl,imx8mm", },
85 { .compatible = "fsl,imx8mn", },
86 { .compatible = "fsl,imx8mp", },
87 { .compatible = "fsl,imx8mq", },
88 { .compatible = "fsl,imx8ulp", },
89 { }
90};
91
92/*
93 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
94 * the software (no JR/QI used).
95 * @ctrldev - pointer to device
96 * @status - descriptor status, after being run
97 *
98 * Return: - 0 if no error occurred
99 * - -ENODEV if the DECO couldn't be acquired
100 * - -EAGAIN if an error occurred while executing the descriptor
101 */
102static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
103 u32 *status)
104{
105 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
106 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
107 struct caam_deco __iomem *deco = ctrlpriv->deco;
108 unsigned int timeout = 100000;
109 u32 deco_dbg_reg, deco_state, flags;
110 int i;
111
112
113 if (ctrlpriv->virt_en == 1 ||
114 /*
115 * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1
116 * and the following steps should be performed regardless
117 */
118 of_match_node(imx8m_machine_match, of_root)) {
119 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
120
121 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
122 --timeout)
123 cpu_relax();
124
125 timeout = 100000;
126 }
127
128 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
129
130 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
131 --timeout)
132 cpu_relax();
133
134 if (!timeout) {
135 dev_err(ctrldev, "failed to acquire DECO 0\n");
136 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
137 return -ENODEV;
138 }
139
140 for (i = 0; i < desc_len(desc); i++)
141 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
142
143 flags = DECO_JQCR_WHL;
144 /*
145 * If the descriptor length is longer than 4 words, then the
146 * FOUR bit in JRCTRL register must be set.
147 */
148 if (desc_len(desc) >= 4)
149 flags |= DECO_JQCR_FOUR;
150
151 /* Instruct the DECO to execute it */
152 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
153
154 timeout = 10000000;
155 do {
156 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
157
158 if (ctrlpriv->era < 10)
159 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
160 DESC_DBG_DECO_STAT_SHIFT;
161 else
162 deco_state = (rd_reg32(&deco->dbg_exec) &
163 DESC_DER_DECO_STAT_MASK) >>
164 DESC_DER_DECO_STAT_SHIFT;
165
166 /*
167 * If an error occurred in the descriptor, then
168 * the DECO status field will be set to 0x0D
169 */
170 if (deco_state == DECO_STAT_HOST_ERR)
171 break;
172
173 cpu_relax();
174 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
175
176 *status = rd_reg32(&deco->op_status_hi) &
177 DECO_OP_STATUS_HI_ERR_MASK;
178
179 if (ctrlpriv->virt_en == 1)
180 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
181
182 /* Mark the DECO as free */
183 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
184
185 if (!timeout)
186 return -EAGAIN;
187
188 return 0;
189}
190
191/*
192 * deinstantiate_rng - builds and executes a descriptor on DECO0,
193 * which deinitializes the RNG block.
194 * @ctrldev - pointer to device
195 * @state_handle_mask - bitmask containing the instantiation status
196 * for the RNG4 state handles which exist in
197 * the RNG4 block: 1 if it's been instantiated
198 *
199 * Return: - 0 if no error occurred
200 * - -ENOMEM if there isn't enough memory to allocate the descriptor
201 * - -ENODEV if DECO0 couldn't be acquired
202 * - -EAGAIN if an error occurred when executing the descriptor
203 */
204static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
205{
206 u32 *desc, status;
207 int sh_idx, ret = 0;
208
209 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
210 if (!desc)
211 return -ENOMEM;
212
213 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
214 /*
215 * If the corresponding bit is set, then it means the state
216 * handle was initialized by us, and thus it needs to be
217 * deinitialized as well
218 */
219 if ((1 << sh_idx) & state_handle_mask) {
220 /*
221 * Create the descriptor for deinstantating this state
222 * handle
223 */
224 build_deinstantiation_desc(desc, sh_idx);
225
226 /* Try to run it through DECO0 */
227 ret = run_descriptor_deco0(ctrldev, desc, &status);
228
229 if (ret ||
230 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
231 dev_err(ctrldev,
232 "Failed to deinstantiate RNG4 SH%d\n",
233 sh_idx);
234 break;
235 }
236 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
237 }
238 }
239
240 kfree(desc);
241
242 return ret;
243}
244
245static void devm_deinstantiate_rng(void *data)
246{
247 struct device *ctrldev = data;
248 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
249
250 /*
251 * De-initialize RNG state handles initialized by this driver.
252 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
253 */
254 if (ctrlpriv->rng4_sh_init)
255 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
256}
257
258/*
259 * instantiate_rng - builds and executes a descriptor on DECO0,
260 * which initializes the RNG block.
261 * @ctrldev - pointer to device
262 * @state_handle_mask - bitmask containing the instantiation status
263 * for the RNG4 state handles which exist in
264 * the RNG4 block: 1 if it's been instantiated
265 * by an external entry, 0 otherwise.
266 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
267 * Caution: this can be done only once; if the keys need to be
268 * regenerated, a POR is required
269 *
270 * Return: - 0 if no error occurred
271 * - -ENOMEM if there isn't enough memory to allocate the descriptor
272 * - -ENODEV if DECO0 couldn't be acquired
273 * - -EAGAIN if an error occurred when executing the descriptor
274 * f.i. there was a RNG hardware error due to not "good enough"
275 * entropy being acquired.
276 */
277static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
278 int gen_sk)
279{
280 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
281 struct caam_ctrl __iomem *ctrl;
282 u32 *desc, status = 0, rdsta_val;
283 int ret = 0, sh_idx;
284
285 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
286 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
287 if (!desc)
288 return -ENOMEM;
289
290 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
291 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
292 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
293 const u32 rdsta_mask = rdsta_if | rdsta_pr;
294
295 /* Clear the contents before using the descriptor */
296 memset(desc, 0x00, CAAM_CMD_SZ * 7);
297
298 /*
299 * If the corresponding bit is set, this state handle
300 * was initialized by somebody else, so it's left alone.
301 */
302 if (rdsta_if & state_handle_mask) {
303 if (rdsta_pr & state_handle_mask)
304 continue;
305
306 dev_info(ctrldev,
307 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
308 sh_idx);
309
310 ret = deinstantiate_rng(ctrldev, rdsta_if);
311 if (ret)
312 break;
313 }
314
315 /* Create the descriptor for instantiating RNG State Handle */
316 build_instantiation_desc(desc, sh_idx, gen_sk);
317
318 /* Try to run it through DECO0 */
319 ret = run_descriptor_deco0(ctrldev, desc, &status);
320
321 /*
322 * If ret is not 0, or descriptor status is not 0, then
323 * something went wrong. No need to try the next state
324 * handle (if available), bail out here.
325 * Also, if for some reason, the State Handle didn't get
326 * instantiated although the descriptor has finished
327 * without any error (HW optimizations for later
328 * CAAM eras), then try again.
329 */
330 if (ret)
331 break;
332
333 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
334 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
335 (rdsta_val & rdsta_mask) != rdsta_mask) {
336 ret = -EAGAIN;
337 break;
338 }
339
340 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
341 }
342
343 kfree(desc);
344
345 if (ret)
346 return ret;
347
348 return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
349}
350
351/*
352 * kick_trng - sets the various parameters for enabling the initialization
353 * of the RNG4 block in CAAM
354 * @dev - pointer to the controller device
355 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
356 */
357static void kick_trng(struct device *dev, int ent_delay)
358{
359 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
360 struct caam_ctrl __iomem *ctrl;
361 struct rng4tst __iomem *r4tst;
362 u32 val, rtsdctl;
363
364 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
365 r4tst = &ctrl->r4tst[0];
366
367 /*
368 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
369 * properly invalidate the entropy in the entropy register and
370 * force re-generation.
371 */
372 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
373
374 /*
375 * Performance-wise, it does not make sense to
376 * set the delay to a value that is lower
377 * than the last one that worked (i.e. the state handles
378 * were instantiated properly).
379 */
380 rtsdctl = rd_reg32(&r4tst->rtsdctl);
381 val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT;
382 if (ent_delay > val) {
383 val = ent_delay;
384 /* min. freq. count, equal to 1/4 of the entropy sample length */
385 wr_reg32(&r4tst->rtfrqmin, val >> 2);
386 /* disable maximum frequency count */
387 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
388 }
389
390 wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |
391 RTSDCTL_SAMP_SIZE_VAL);
392
393 /*
394 * To avoid reprogramming the self-test parameters over and over again,
395 * use RTSDCTL[SAMP_SIZE] as an indicator.
396 */
397 if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) {
398 wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
399 wr_reg32(&r4tst->rtpkrrng, 570);
400 wr_reg32(&r4tst->rtpkrmax, 1600);
401 wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
402 wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);
403 wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);
404 wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);
405 wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);
406 wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);
407 wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);
408 }
409
410 /*
411 * select raw sampling in both entropy shifter
412 * and statistical checker; ; put RNG4 into run mode
413 */
414 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
415 RTMCTL_SAMP_MODE_RAW_ES_SC);
416}
417
418static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
419{
420 static const struct {
421 u16 ip_id;
422 u8 maj_rev;
423 u8 era;
424 } id[] = {
425 {0x0A10, 1, 1},
426 {0x0A10, 2, 2},
427 {0x0A12, 1, 3},
428 {0x0A14, 1, 3},
429 {0x0A14, 2, 4},
430 {0x0A16, 1, 4},
431 {0x0A10, 3, 4},
432 {0x0A11, 1, 4},
433 {0x0A18, 1, 4},
434 {0x0A11, 2, 5},
435 {0x0A12, 2, 5},
436 {0x0A13, 1, 5},
437 {0x0A1C, 1, 5}
438 };
439 u32 ccbvid, id_ms;
440 u8 maj_rev, era;
441 u16 ip_id;
442 int i;
443
444 ccbvid = rd_reg32(&perfmon->ccb_id);
445 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
446 if (era) /* This is '0' prior to CAAM ERA-6 */
447 return era;
448
449 id_ms = rd_reg32(&perfmon->caam_id_ms);
450 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
451 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
452
453 for (i = 0; i < ARRAY_SIZE(id); i++)
454 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
455 return id[i].era;
456
457 return -ENOTSUPP;
458}
459
460/**
461 * caam_get_era() - Return the ERA of the SEC on SoC, based
462 * on "sec-era" optional property in the DTS. This property is updated
463 * by u-boot.
464 * In case this property is not passed an attempt to retrieve the CAAM
465 * era via register reads will be made.
466 *
467 * @perfmon: Performance Monitor Registers
468 */
469static int caam_get_era(struct caam_perfmon __iomem *perfmon)
470{
471 struct device_node *caam_node;
472 int ret;
473 u32 prop;
474
475 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
476 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
477 of_node_put(caam_node);
478
479 if (!ret)
480 return prop;
481 else
482 return caam_get_era_from_hw(perfmon);
483}
484
485/*
486 * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
487 * have an issue wherein AXI bus transactions may not occur in the correct
488 * order. This isn't a problem running single descriptors, but can be if
489 * running multiple concurrent descriptors. Reworking the driver to throttle
490 * to single requests is impractical, thus the workaround is to limit the AXI
491 * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
492 * from occurring.
493 */
494static void handle_imx6_err005766(u32 __iomem *mcr)
495{
496 if (of_machine_is_compatible("fsl,imx6q") ||
497 of_machine_is_compatible("fsl,imx6dl") ||
498 of_machine_is_compatible("fsl,imx6qp"))
499 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
500 1 << MCFGR_AXIPIPE_SHIFT);
501}
502
503static const struct of_device_id caam_match[] = {
504 {
505 .compatible = "fsl,sec-v4.0",
506 },
507 {
508 .compatible = "fsl,sec4.0",
509 },
510 {},
511};
512MODULE_DEVICE_TABLE(of, caam_match);
513
514struct caam_imx_data {
515 const struct clk_bulk_data *clks;
516 int num_clks;
517};
518
519static const struct clk_bulk_data caam_imx6_clks[] = {
520 { .id = "ipg" },
521 { .id = "mem" },
522 { .id = "aclk" },
523 { .id = "emi_slow" },
524};
525
526static const struct caam_imx_data caam_imx6_data = {
527 .clks = caam_imx6_clks,
528 .num_clks = ARRAY_SIZE(caam_imx6_clks),
529};
530
531static const struct clk_bulk_data caam_imx7_clks[] = {
532 { .id = "ipg" },
533 { .id = "aclk" },
534};
535
536static const struct caam_imx_data caam_imx7_data = {
537 .clks = caam_imx7_clks,
538 .num_clks = ARRAY_SIZE(caam_imx7_clks),
539};
540
541static const struct clk_bulk_data caam_imx6ul_clks[] = {
542 { .id = "ipg" },
543 { .id = "mem" },
544 { .id = "aclk" },
545};
546
547static const struct caam_imx_data caam_imx6ul_data = {
548 .clks = caam_imx6ul_clks,
549 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
550};
551
552static const struct clk_bulk_data caam_vf610_clks[] = {
553 { .id = "ipg" },
554};
555
556static const struct caam_imx_data caam_vf610_data = {
557 .clks = caam_vf610_clks,
558 .num_clks = ARRAY_SIZE(caam_vf610_clks),
559};
560
561static const struct soc_device_attribute caam_imx_soc_table[] = {
562 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
563 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
564 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
565 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
566 { .soc_id = "VF*", .data = &caam_vf610_data },
567 { .family = "Freescale i.MX" },
568 { /* sentinel */ }
569};
570
571static void disable_clocks(void *data)
572{
573 struct caam_drv_private *ctrlpriv = data;
574
575 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
576}
577
578static int init_clocks(struct device *dev, const struct caam_imx_data *data)
579{
580 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
581 int ret;
582
583 ctrlpriv->num_clks = data->num_clks;
584 ctrlpriv->clks = devm_kmemdup(dev, data->clks,
585 data->num_clks * sizeof(data->clks[0]),
586 GFP_KERNEL);
587 if (!ctrlpriv->clks)
588 return -ENOMEM;
589
590 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
591 if (ret) {
592 dev_err(dev,
593 "Failed to request all necessary clocks\n");
594 return ret;
595 }
596
597 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
598 if (ret) {
599 dev_err(dev,
600 "Failed to prepare/enable all necessary clocks\n");
601 return ret;
602 }
603
604 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
605}
606
607static void caam_remove_debugfs(void *root)
608{
609 debugfs_remove_recursive(root);
610}
611
612#ifdef CONFIG_FSL_MC_BUS
613static bool check_version(struct fsl_mc_version *mc_version, u32 major,
614 u32 minor, u32 revision)
615{
616 if (mc_version->major > major)
617 return true;
618
619 if (mc_version->major == major) {
620 if (mc_version->minor > minor)
621 return true;
622
623 if (mc_version->minor == minor &&
624 mc_version->revision > revision)
625 return true;
626 }
627
628 return false;
629}
630#endif
631
632static bool needs_entropy_delay_adjustment(void)
633{
634 if (of_machine_is_compatible("fsl,imx6sx"))
635 return true;
636 return false;
637}
638
639static int caam_ctrl_rng_init(struct device *dev)
640{
641 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
642 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
643 int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
644 u8 rng_vid;
645
646 if (ctrlpriv->era < 10) {
647 struct caam_perfmon __iomem *perfmon;
648
649 perfmon = ctrlpriv->total_jobrs ?
650 (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
651 (struct caam_perfmon __iomem *)&ctrl->perfmon;
652
653 rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
654 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
655 } else {
656 struct version_regs __iomem *vreg;
657
658 vreg = ctrlpriv->total_jobrs ?
659 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
660 (struct version_regs __iomem *)&ctrl->vreg;
661
662 rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
663 CHA_VER_VID_SHIFT;
664 }
665
666 /*
667 * If SEC has RNG version >= 4 and RNG state handle has not been
668 * already instantiated, do RNG instantiation
669 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
670 */
671 if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) {
672 ctrlpriv->rng4_sh_init =
673 rd_reg32(&ctrl->r4tst[0].rdsta);
674 /*
675 * If the secure keys (TDKEK, JDKEK, TDSK), were already
676 * generated, signal this to the function that is instantiating
677 * the state handles. An error would occur if RNG4 attempts
678 * to regenerate these keys before the next POR.
679 */
680 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
681 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
682 do {
683 int inst_handles =
684 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
685 /*
686 * If either SH were instantiated by somebody else
687 * (e.g. u-boot) then it is assumed that the entropy
688 * parameters are properly set and thus the function
689 * setting these (kick_trng(...)) is skipped.
690 * Also, if a handle was instantiated, do not change
691 * the TRNG parameters.
692 */
693 if (needs_entropy_delay_adjustment())
694 ent_delay = 12000;
695 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
696 dev_info(dev,
697 "Entropy delay = %u\n",
698 ent_delay);
699 kick_trng(dev, ent_delay);
700 ent_delay += 400;
701 }
702 /*
703 * if instantiate_rng(...) fails, the loop will rerun
704 * and the kick_trng(...) function will modify the
705 * upper and lower limits of the entropy sampling
706 * interval, leading to a successful initialization of
707 * the RNG.
708 */
709 ret = instantiate_rng(dev, inst_handles,
710 gen_sk);
711 /*
712 * Entropy delay is determined via TRNG characterization.
713 * TRNG characterization is run across different voltages
714 * and temperatures.
715 * If worst case value for ent_dly is identified,
716 * the loop can be skipped for that platform.
717 */
718 if (needs_entropy_delay_adjustment())
719 break;
720 if (ret == -EAGAIN)
721 /*
722 * if here, the loop will rerun,
723 * so don't hog the CPU
724 */
725 cpu_relax();
726 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
727 if (ret) {
728 dev_err(dev, "failed to instantiate RNG");
729 return ret;
730 }
731 /*
732 * Set handles initialized by this module as the complement of
733 * the already initialized ones
734 */
735 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
736
737 /* Enable RDB bit so that RNG works faster */
738 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
739 }
740
741 return 0;
742}
743
744/* Indicate if the internal state of the CAAM is lost during PM */
745static int caam_off_during_pm(void)
746{
747 bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") ||
748 of_machine_is_compatible("fsl,imx6qp") ||
749 of_machine_is_compatible("fsl,imx6dl");
750
751 return not_off_during_pm ? 0 : 1;
752}
753
754static void caam_state_save(struct device *dev)
755{
756 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
757 struct caam_ctl_state *state = &ctrlpriv->state;
758 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
759 u32 deco_inst, jr_inst;
760 int i;
761
762 state->mcr = rd_reg32(&ctrl->mcr);
763 state->scfgr = rd_reg32(&ctrl->scfgr);
764
765 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
766 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
767 for (i = 0; i < deco_inst; i++) {
768 state->deco_mid[i].liodn_ms =
769 rd_reg32(&ctrl->deco_mid[i].liodn_ms);
770 state->deco_mid[i].liodn_ls =
771 rd_reg32(&ctrl->deco_mid[i].liodn_ls);
772 }
773
774 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
775 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
776 for (i = 0; i < jr_inst; i++) {
777 state->jr_mid[i].liodn_ms =
778 rd_reg32(&ctrl->jr_mid[i].liodn_ms);
779 state->jr_mid[i].liodn_ls =
780 rd_reg32(&ctrl->jr_mid[i].liodn_ls);
781 }
782}
783
784static void caam_state_restore(const struct device *dev)
785{
786 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
787 const struct caam_ctl_state *state = &ctrlpriv->state;
788 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
789 u32 deco_inst, jr_inst;
790 int i;
791
792 wr_reg32(&ctrl->mcr, state->mcr);
793 wr_reg32(&ctrl->scfgr, state->scfgr);
794
795 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
796 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
797 for (i = 0; i < deco_inst; i++) {
798 wr_reg32(&ctrl->deco_mid[i].liodn_ms,
799 state->deco_mid[i].liodn_ms);
800 wr_reg32(&ctrl->deco_mid[i].liodn_ls,
801 state->deco_mid[i].liodn_ls);
802 }
803
804 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
805 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
806 for (i = 0; i < jr_inst; i++) {
807 wr_reg32(&ctrl->jr_mid[i].liodn_ms,
808 state->jr_mid[i].liodn_ms);
809 wr_reg32(&ctrl->jr_mid[i].liodn_ls,
810 state->jr_mid[i].liodn_ls);
811 }
812
813 if (ctrlpriv->virt_en == 1)
814 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
815 JRSTART_JR1_START | JRSTART_JR2_START |
816 JRSTART_JR3_START);
817}
818
819static int caam_ctrl_suspend(struct device *dev)
820{
821 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
822
823 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en)
824 caam_state_save(dev);
825
826 return 0;
827}
828
829static int caam_ctrl_resume(struct device *dev)
830{
831 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
832 int ret = 0;
833
834 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) {
835 caam_state_restore(dev);
836
837 /* HW and rng will be reset so deinstantiation can be removed */
838 devm_remove_action(dev, devm_deinstantiate_rng, dev);
839 ret = caam_ctrl_rng_init(dev);
840 }
841
842 return ret;
843}
844
845static DEFINE_SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume);
846
847/* Probe routine for CAAM top (controller) level */
848static int caam_probe(struct platform_device *pdev)
849{
850 int ret, ring;
851 u64 caam_id;
852 const struct soc_device_attribute *imx_soc_match;
853 struct device *dev;
854 struct device_node *nprop, *np;
855 struct caam_ctrl __iomem *ctrl;
856 struct caam_drv_private *ctrlpriv;
857 struct caam_perfmon __iomem *perfmon;
858 struct dentry *dfs_root;
859 u32 scfgr, comp_params;
860 int pg_size;
861 int BLOCK_OFFSET = 0;
862 bool reg_access = true;
863
864 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
865 if (!ctrlpriv)
866 return -ENOMEM;
867
868 dev = &pdev->dev;
869 dev_set_drvdata(dev, ctrlpriv);
870 nprop = pdev->dev.of_node;
871
872 imx_soc_match = soc_device_match(caam_imx_soc_table);
873 if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root))
874 return -EPROBE_DEFER;
875
876 caam_imx = (bool)imx_soc_match;
877
878 ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm();
879
880 if (imx_soc_match) {
881 /*
882 * Until Layerscape and i.MX OP-TEE get in sync,
883 * only i.MX OP-TEE use cases disallow access to
884 * caam page 0 (controller) registers.
885 */
886 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
887 ctrlpriv->optee_en = !!np;
888 of_node_put(np);
889
890 reg_access = !ctrlpriv->optee_en;
891
892 if (!imx_soc_match->data) {
893 dev_err(dev, "No clock data provided for i.MX SoC");
894 return -EINVAL;
895 }
896
897 ret = init_clocks(dev, imx_soc_match->data);
898 if (ret)
899 return ret;
900 }
901
902
903 /* Get configuration properties from device tree */
904 /* First, get register page */
905 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
906 ret = PTR_ERR_OR_ZERO(ctrl);
907 if (ret) {
908 dev_err(dev, "caam: of_iomap() failed\n");
909 return ret;
910 }
911
912 ring = 0;
913 for_each_available_child_of_node(nprop, np)
914 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
915 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
916 u32 reg;
917
918 if (of_property_read_u32_index(np, "reg", 0, ®)) {
919 dev_err(dev, "%s read reg property error\n",
920 np->full_name);
921 continue;
922 }
923
924 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
925 ((__force uint8_t *)ctrl + reg);
926
927 ctrlpriv->total_jobrs++;
928 ring++;
929 }
930
931 /*
932 * Wherever possible, instead of accessing registers from the global page,
933 * use the alias registers in the first (cf. DT nodes order)
934 * job ring's page.
935 */
936 perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
937 (struct caam_perfmon __iomem *)&ctrl->perfmon;
938
939 caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
940 (CSTA_PLEND | CSTA_ALT_PLEND));
941 comp_params = rd_reg32(&perfmon->comp_parms_ms);
942 if (reg_access && comp_params & CTPR_MS_PS &&
943 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
944 caam_ptr_sz = sizeof(u64);
945 else
946 caam_ptr_sz = sizeof(u32);
947 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
948 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
949
950#ifdef CONFIG_CAAM_QI
951 /* If (DPAA 1.x) QI present, check whether dependencies are available */
952 if (ctrlpriv->qi_present && !caam_dpaa2) {
953 ret = qman_is_probed();
954 if (!ret) {
955 return -EPROBE_DEFER;
956 } else if (ret < 0) {
957 dev_err(dev, "failing probe due to qman probe error\n");
958 return -ENODEV;
959 }
960
961 ret = qman_portals_probed();
962 if (!ret) {
963 return -EPROBE_DEFER;
964 } else if (ret < 0) {
965 dev_err(dev, "failing probe due to qman portals probe error\n");
966 return -ENODEV;
967 }
968 }
969#endif
970
971 /* Allocating the BLOCK_OFFSET based on the supported page size on
972 * the platform
973 */
974 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
975 if (pg_size == 0)
976 BLOCK_OFFSET = PG_SIZE_4K;
977 else
978 BLOCK_OFFSET = PG_SIZE_64K;
979
980 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
981 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
982 ((__force uint8_t *)ctrl +
983 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
984 );
985 ctrlpriv->deco = (struct caam_deco __iomem __force *)
986 ((__force uint8_t *)ctrl +
987 BLOCK_OFFSET * DECO_BLOCK_NUMBER
988 );
989
990 /* Get the IRQ of the controller (for security violations only) */
991 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
992 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
993 ctrlpriv->mc_en = !!np;
994 of_node_put(np);
995
996#ifdef CONFIG_FSL_MC_BUS
997 if (ctrlpriv->mc_en) {
998 struct fsl_mc_version *mc_version;
999
1000 mc_version = fsl_mc_get_version();
1001 if (mc_version)
1002 ctrlpriv->pr_support = check_version(mc_version, 10, 20,
1003 0);
1004 else
1005 return -EPROBE_DEFER;
1006 }
1007#endif
1008
1009 if (!reg_access)
1010 goto set_dma_mask;
1011
1012 /*
1013 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
1014 * long pointers in master configuration register.
1015 * In case of SoCs with Management Complex, MC f/w performs
1016 * the configuration.
1017 */
1018 if (!ctrlpriv->mc_en)
1019 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
1020 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
1021 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
1022
1023 handle_imx6_err005766(&ctrl->mcr);
1024
1025 /*
1026 * Read the Compile Time parameters and SCFGR to determine
1027 * if virtualization is enabled for this platform
1028 */
1029 scfgr = rd_reg32(&ctrl->scfgr);
1030
1031 ctrlpriv->virt_en = 0;
1032 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
1033 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
1034 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
1035 */
1036 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
1037 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
1038 (scfgr & SCFGR_VIRT_EN)))
1039 ctrlpriv->virt_en = 1;
1040 } else {
1041 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
1042 if (comp_params & CTPR_MS_VIRT_EN_POR)
1043 ctrlpriv->virt_en = 1;
1044 }
1045
1046 if (ctrlpriv->virt_en == 1)
1047 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
1048 JRSTART_JR1_START | JRSTART_JR2_START |
1049 JRSTART_JR3_START);
1050
1051set_dma_mask:
1052 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
1053 if (ret) {
1054 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
1055 return ret;
1056 }
1057
1058 ctrlpriv->era = caam_get_era(perfmon);
1059 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
1060
1061 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
1062 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1063 ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
1064 dfs_root);
1065 if (ret)
1066 return ret;
1067 }
1068
1069 caam_debugfs_init(ctrlpriv, perfmon, dfs_root);
1070
1071 /* Check to see if (DPAA 1.x) QI present. If so, enable */
1072 if (ctrlpriv->qi_present && !caam_dpaa2) {
1073 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
1074 ((__force uint8_t *)ctrl +
1075 BLOCK_OFFSET * QI_BLOCK_NUMBER
1076 );
1077 /* This is all that's required to physically enable QI */
1078 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
1079
1080 /* If QMAN driver is present, init CAAM-QI backend */
1081#ifdef CONFIG_CAAM_QI
1082 ret = caam_qi_init(pdev);
1083 if (ret)
1084 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
1085#endif
1086 }
1087
1088 /* If no QI and no rings specified, quit and go home */
1089 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
1090 dev_err(dev, "no queues configured, terminating\n");
1091 return -ENOMEM;
1092 }
1093
1094 comp_params = rd_reg32(&perfmon->comp_parms_ls);
1095 ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);
1096
1097 /*
1098 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,
1099 * but fail when actually using it due to missing AES support, so
1100 * check both here.
1101 */
1102 if (ctrlpriv->era < 10) {
1103 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1104 (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);
1105 } else {
1106 struct version_regs __iomem *vreg;
1107
1108 vreg = ctrlpriv->total_jobrs ?
1109 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
1110 (struct version_regs __iomem *)&ctrl->vreg;
1111
1112 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1113 (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);
1114 }
1115
1116 if (reg_access) {
1117 ret = caam_ctrl_rng_init(dev);
1118 if (ret)
1119 return ret;
1120 }
1121
1122 caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
1123 (u64)rd_reg32(&perfmon->caam_id_ls);
1124
1125 /* Report "alive" for developer to see */
1126 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
1127 ctrlpriv->era);
1128 dev_info(dev, "job rings = %d, qi = %d\n",
1129 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
1130
1131 ret = devm_of_platform_populate(dev);
1132 if (ret)
1133 dev_err(dev, "JR platform devices creation error\n");
1134
1135 return ret;
1136}
1137
1138static struct platform_driver caam_driver = {
1139 .driver = {
1140 .name = "caam",
1141 .of_match_table = caam_match,
1142 .pm = pm_ptr(&caam_ctrl_pm_ops),
1143 },
1144 .probe = caam_probe,
1145};
1146
1147module_platform_driver(caam_driver);
1148
1149MODULE_LICENSE("GPL");
1150MODULE_DESCRIPTION("FSL CAAM request backend");
1151MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
1// SPDX-License-Identifier: GPL-2.0+
2/* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
4 *
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
7 */
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/platform_device.h>
13#include <linux/sys_soc.h>
14#include <linux/fsl/mc.h>
15
16#include "compat.h"
17#include "debugfs.h"
18#include "regs.h"
19#include "intern.h"
20#include "jr.h"
21#include "desc_constr.h"
22#include "ctrl.h"
23
24bool caam_dpaa2;
25EXPORT_SYMBOL(caam_dpaa2);
26
27#ifdef CONFIG_CAAM_QI
28#include "qi.h"
29#endif
30
31/*
32 * Descriptor to instantiate RNG State Handle 0 in normal mode and
33 * load the JDKEK, TDKEK and TDSK registers
34 */
35static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
36{
37 u32 *jump_cmd, op_flags;
38
39 init_job_desc(desc, 0);
40
41 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
42 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
43 OP_ALG_PR_ON;
44
45 /* INIT RNG in non-test mode */
46 append_operation(desc, op_flags);
47
48 if (!handle && do_sk) {
49 /*
50 * For SH0, Secure Keys must be generated as well
51 */
52
53 /* wait for done */
54 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
55 set_jump_tgt_here(desc, jump_cmd);
56
57 /*
58 * load 1 to clear written reg:
59 * resets the done interrupt and returns the RNG to idle.
60 */
61 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
62
63 /* Initialize State Handle */
64 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
65 OP_ALG_AAI_RNG4_SK);
66 }
67
68 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
69}
70
71/* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
72static void build_deinstantiation_desc(u32 *desc, int handle)
73{
74 init_job_desc(desc, 0);
75
76 /* Uninstantiate State Handle 0 */
77 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
78 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
79
80 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
81}
82
83#ifdef CONFIG_OF
84static const struct of_device_id imx8m_machine_match[] = {
85 { .compatible = "fsl,imx8mm", },
86 { .compatible = "fsl,imx8mn", },
87 { .compatible = "fsl,imx8mp", },
88 { .compatible = "fsl,imx8mq", },
89 { .compatible = "fsl,imx8ulp", },
90 { }
91};
92#endif
93
94/*
95 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
96 * the software (no JR/QI used).
97 * @ctrldev - pointer to device
98 * @status - descriptor status, after being run
99 *
100 * Return: - 0 if no error occurred
101 * - -ENODEV if the DECO couldn't be acquired
102 * - -EAGAIN if an error occurred while executing the descriptor
103 */
104static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
105 u32 *status)
106{
107 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
108 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
109 struct caam_deco __iomem *deco = ctrlpriv->deco;
110 unsigned int timeout = 100000;
111 u32 deco_dbg_reg, deco_state, flags;
112 int i;
113
114
115 if (ctrlpriv->virt_en == 1 ||
116 /*
117 * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1
118 * and the following steps should be performed regardless
119 */
120 of_match_node(imx8m_machine_match, of_root)) {
121 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
122
123 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
124 --timeout)
125 cpu_relax();
126
127 timeout = 100000;
128 }
129
130 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
131
132 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
133 --timeout)
134 cpu_relax();
135
136 if (!timeout) {
137 dev_err(ctrldev, "failed to acquire DECO 0\n");
138 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
139 return -ENODEV;
140 }
141
142 for (i = 0; i < desc_len(desc); i++)
143 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
144
145 flags = DECO_JQCR_WHL;
146 /*
147 * If the descriptor length is longer than 4 words, then the
148 * FOUR bit in JRCTRL register must be set.
149 */
150 if (desc_len(desc) >= 4)
151 flags |= DECO_JQCR_FOUR;
152
153 /* Instruct the DECO to execute it */
154 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
155
156 timeout = 10000000;
157 do {
158 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
159
160 if (ctrlpriv->era < 10)
161 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
162 DESC_DBG_DECO_STAT_SHIFT;
163 else
164 deco_state = (rd_reg32(&deco->dbg_exec) &
165 DESC_DER_DECO_STAT_MASK) >>
166 DESC_DER_DECO_STAT_SHIFT;
167
168 /*
169 * If an error occurred in the descriptor, then
170 * the DECO status field will be set to 0x0D
171 */
172 if (deco_state == DECO_STAT_HOST_ERR)
173 break;
174
175 cpu_relax();
176 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
177
178 *status = rd_reg32(&deco->op_status_hi) &
179 DECO_OP_STATUS_HI_ERR_MASK;
180
181 if (ctrlpriv->virt_en == 1)
182 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
183
184 /* Mark the DECO as free */
185 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
186
187 if (!timeout)
188 return -EAGAIN;
189
190 return 0;
191}
192
193/*
194 * deinstantiate_rng - builds and executes a descriptor on DECO0,
195 * which deinitializes the RNG block.
196 * @ctrldev - pointer to device
197 * @state_handle_mask - bitmask containing the instantiation status
198 * for the RNG4 state handles which exist in
199 * the RNG4 block: 1 if it's been instantiated
200 *
201 * Return: - 0 if no error occurred
202 * - -ENOMEM if there isn't enough memory to allocate the descriptor
203 * - -ENODEV if DECO0 couldn't be acquired
204 * - -EAGAIN if an error occurred when executing the descriptor
205 */
206static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
207{
208 u32 *desc, status;
209 int sh_idx, ret = 0;
210
211 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
212 if (!desc)
213 return -ENOMEM;
214
215 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
216 /*
217 * If the corresponding bit is set, then it means the state
218 * handle was initialized by us, and thus it needs to be
219 * deinitialized as well
220 */
221 if ((1 << sh_idx) & state_handle_mask) {
222 /*
223 * Create the descriptor for deinstantating this state
224 * handle
225 */
226 build_deinstantiation_desc(desc, sh_idx);
227
228 /* Try to run it through DECO0 */
229 ret = run_descriptor_deco0(ctrldev, desc, &status);
230
231 if (ret ||
232 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
233 dev_err(ctrldev,
234 "Failed to deinstantiate RNG4 SH%d\n",
235 sh_idx);
236 break;
237 }
238 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
239 }
240 }
241
242 kfree(desc);
243
244 return ret;
245}
246
247static void devm_deinstantiate_rng(void *data)
248{
249 struct device *ctrldev = data;
250 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
251
252 /*
253 * De-initialize RNG state handles initialized by this driver.
254 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
255 */
256 if (ctrlpriv->rng4_sh_init)
257 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
258}
259
260/*
261 * instantiate_rng - builds and executes a descriptor on DECO0,
262 * which initializes the RNG block.
263 * @ctrldev - pointer to device
264 * @state_handle_mask - bitmask containing the instantiation status
265 * for the RNG4 state handles which exist in
266 * the RNG4 block: 1 if it's been instantiated
267 * by an external entry, 0 otherwise.
268 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
269 * Caution: this can be done only once; if the keys need to be
270 * regenerated, a POR is required
271 *
272 * Return: - 0 if no error occurred
273 * - -ENOMEM if there isn't enough memory to allocate the descriptor
274 * - -ENODEV if DECO0 couldn't be acquired
275 * - -EAGAIN if an error occurred when executing the descriptor
276 * f.i. there was a RNG hardware error due to not "good enough"
277 * entropy being acquired.
278 */
279static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
280 int gen_sk)
281{
282 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
283 struct caam_ctrl __iomem *ctrl;
284 u32 *desc, status = 0, rdsta_val;
285 int ret = 0, sh_idx;
286
287 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
288 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
289 if (!desc)
290 return -ENOMEM;
291
292 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
293 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
294 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
295 const u32 rdsta_mask = rdsta_if | rdsta_pr;
296
297 /* Clear the contents before using the descriptor */
298 memset(desc, 0x00, CAAM_CMD_SZ * 7);
299
300 /*
301 * If the corresponding bit is set, this state handle
302 * was initialized by somebody else, so it's left alone.
303 */
304 if (rdsta_if & state_handle_mask) {
305 if (rdsta_pr & state_handle_mask)
306 continue;
307
308 dev_info(ctrldev,
309 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
310 sh_idx);
311
312 ret = deinstantiate_rng(ctrldev, rdsta_if);
313 if (ret)
314 break;
315 }
316
317 /* Create the descriptor for instantiating RNG State Handle */
318 build_instantiation_desc(desc, sh_idx, gen_sk);
319
320 /* Try to run it through DECO0 */
321 ret = run_descriptor_deco0(ctrldev, desc, &status);
322
323 /*
324 * If ret is not 0, or descriptor status is not 0, then
325 * something went wrong. No need to try the next state
326 * handle (if available), bail out here.
327 * Also, if for some reason, the State Handle didn't get
328 * instantiated although the descriptor has finished
329 * without any error (HW optimizations for later
330 * CAAM eras), then try again.
331 */
332 if (ret)
333 break;
334
335 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
336 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
337 (rdsta_val & rdsta_mask) != rdsta_mask) {
338 ret = -EAGAIN;
339 break;
340 }
341
342 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
343 }
344
345 kfree(desc);
346
347 if (ret)
348 return ret;
349
350 return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
351}
352
353/*
354 * kick_trng - sets the various parameters for enabling the initialization
355 * of the RNG4 block in CAAM
356 * @dev - pointer to the controller device
357 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
358 */
359static void kick_trng(struct device *dev, int ent_delay)
360{
361 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
362 struct caam_ctrl __iomem *ctrl;
363 struct rng4tst __iomem *r4tst;
364 u32 val, rtsdctl;
365
366 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
367 r4tst = &ctrl->r4tst[0];
368
369 /*
370 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
371 * properly invalidate the entropy in the entropy register and
372 * force re-generation.
373 */
374 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
375
376 /*
377 * Performance-wise, it does not make sense to
378 * set the delay to a value that is lower
379 * than the last one that worked (i.e. the state handles
380 * were instantiated properly).
381 */
382 rtsdctl = rd_reg32(&r4tst->rtsdctl);
383 val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT;
384 if (ent_delay > val) {
385 val = ent_delay;
386 /* min. freq. count, equal to 1/4 of the entropy sample length */
387 wr_reg32(&r4tst->rtfrqmin, val >> 2);
388 /* disable maximum frequency count */
389 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
390 }
391
392 wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |
393 RTSDCTL_SAMP_SIZE_VAL);
394
395 /*
396 * To avoid reprogramming the self-test parameters over and over again,
397 * use RTSDCTL[SAMP_SIZE] as an indicator.
398 */
399 if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) {
400 wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
401 wr_reg32(&r4tst->rtpkrrng, 570);
402 wr_reg32(&r4tst->rtpkrmax, 1600);
403 wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
404 wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);
405 wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);
406 wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);
407 wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);
408 wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);
409 wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);
410 }
411
412 /*
413 * select raw sampling in both entropy shifter
414 * and statistical checker; ; put RNG4 into run mode
415 */
416 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
417 RTMCTL_SAMP_MODE_RAW_ES_SC);
418}
419
420static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
421{
422 static const struct {
423 u16 ip_id;
424 u8 maj_rev;
425 u8 era;
426 } id[] = {
427 {0x0A10, 1, 1},
428 {0x0A10, 2, 2},
429 {0x0A12, 1, 3},
430 {0x0A14, 1, 3},
431 {0x0A14, 2, 4},
432 {0x0A16, 1, 4},
433 {0x0A10, 3, 4},
434 {0x0A11, 1, 4},
435 {0x0A18, 1, 4},
436 {0x0A11, 2, 5},
437 {0x0A12, 2, 5},
438 {0x0A13, 1, 5},
439 {0x0A1C, 1, 5}
440 };
441 u32 ccbvid, id_ms;
442 u8 maj_rev, era;
443 u16 ip_id;
444 int i;
445
446 ccbvid = rd_reg32(&perfmon->ccb_id);
447 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
448 if (era) /* This is '0' prior to CAAM ERA-6 */
449 return era;
450
451 id_ms = rd_reg32(&perfmon->caam_id_ms);
452 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
453 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
454
455 for (i = 0; i < ARRAY_SIZE(id); i++)
456 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
457 return id[i].era;
458
459 return -ENOTSUPP;
460}
461
462/**
463 * caam_get_era() - Return the ERA of the SEC on SoC, based
464 * on "sec-era" optional property in the DTS. This property is updated
465 * by u-boot.
466 * In case this property is not passed an attempt to retrieve the CAAM
467 * era via register reads will be made.
468 *
469 * @perfmon: Performance Monitor Registers
470 */
471static int caam_get_era(struct caam_perfmon __iomem *perfmon)
472{
473 struct device_node *caam_node;
474 int ret;
475 u32 prop;
476
477 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
478 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
479 of_node_put(caam_node);
480
481 if (!ret)
482 return prop;
483 else
484 return caam_get_era_from_hw(perfmon);
485}
486
487/*
488 * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
489 * have an issue wherein AXI bus transactions may not occur in the correct
490 * order. This isn't a problem running single descriptors, but can be if
491 * running multiple concurrent descriptors. Reworking the driver to throttle
492 * to single requests is impractical, thus the workaround is to limit the AXI
493 * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
494 * from occurring.
495 */
496static void handle_imx6_err005766(u32 __iomem *mcr)
497{
498 if (of_machine_is_compatible("fsl,imx6q") ||
499 of_machine_is_compatible("fsl,imx6dl") ||
500 of_machine_is_compatible("fsl,imx6qp"))
501 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
502 1 << MCFGR_AXIPIPE_SHIFT);
503}
504
505static const struct of_device_id caam_match[] = {
506 {
507 .compatible = "fsl,sec-v4.0",
508 },
509 {
510 .compatible = "fsl,sec4.0",
511 },
512 {},
513};
514MODULE_DEVICE_TABLE(of, caam_match);
515
516struct caam_imx_data {
517 bool page0_access;
518 const struct clk_bulk_data *clks;
519 int num_clks;
520};
521
522static const struct clk_bulk_data caam_imx6_clks[] = {
523 { .id = "ipg" },
524 { .id = "mem" },
525 { .id = "aclk" },
526 { .id = "emi_slow" },
527};
528
529static const struct caam_imx_data caam_imx6_data = {
530 .page0_access = true,
531 .clks = caam_imx6_clks,
532 .num_clks = ARRAY_SIZE(caam_imx6_clks),
533};
534
535static const struct clk_bulk_data caam_imx7_clks[] = {
536 { .id = "ipg" },
537 { .id = "aclk" },
538};
539
540static const struct caam_imx_data caam_imx7_data = {
541 .page0_access = true,
542 .clks = caam_imx7_clks,
543 .num_clks = ARRAY_SIZE(caam_imx7_clks),
544};
545
546static const struct clk_bulk_data caam_imx6ul_clks[] = {
547 { .id = "ipg" },
548 { .id = "mem" },
549 { .id = "aclk" },
550};
551
552static const struct caam_imx_data caam_imx6ul_data = {
553 .page0_access = true,
554 .clks = caam_imx6ul_clks,
555 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
556};
557
558static const struct clk_bulk_data caam_vf610_clks[] = {
559 { .id = "ipg" },
560};
561
562static const struct caam_imx_data caam_vf610_data = {
563 .page0_access = true,
564 .clks = caam_vf610_clks,
565 .num_clks = ARRAY_SIZE(caam_vf610_clks),
566};
567
568static const struct caam_imx_data caam_imx8ulp_data;
569
570static const struct soc_device_attribute caam_imx_soc_table[] = {
571 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
572 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
573 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
574 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
575 { .soc_id = "i.MX8ULP", .data = &caam_imx8ulp_data },
576 { .soc_id = "VF*", .data = &caam_vf610_data },
577 { .family = "Freescale i.MX" },
578 { /* sentinel */ }
579};
580
581static void disable_clocks(void *data)
582{
583 struct caam_drv_private *ctrlpriv = data;
584
585 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
586}
587
588static int init_clocks(struct device *dev, const struct caam_imx_data *data)
589{
590 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
591 int ret;
592
593 ctrlpriv->num_clks = data->num_clks;
594 ctrlpriv->clks = devm_kmemdup(dev, data->clks,
595 data->num_clks * sizeof(data->clks[0]),
596 GFP_KERNEL);
597 if (!ctrlpriv->clks)
598 return -ENOMEM;
599
600 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
601 if (ret) {
602 dev_err(dev,
603 "Failed to request all necessary clocks\n");
604 return ret;
605 }
606
607 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
608 if (ret) {
609 dev_err(dev,
610 "Failed to prepare/enable all necessary clocks\n");
611 return ret;
612 }
613
614 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
615}
616
617static void caam_remove_debugfs(void *root)
618{
619 debugfs_remove_recursive(root);
620}
621
622#ifdef CONFIG_FSL_MC_BUS
623static bool check_version(struct fsl_mc_version *mc_version, u32 major,
624 u32 minor, u32 revision)
625{
626 if (mc_version->major > major)
627 return true;
628
629 if (mc_version->major == major) {
630 if (mc_version->minor > minor)
631 return true;
632
633 if (mc_version->minor == minor &&
634 mc_version->revision > revision)
635 return true;
636 }
637
638 return false;
639}
640#endif
641
642static bool needs_entropy_delay_adjustment(void)
643{
644 if (of_machine_is_compatible("fsl,imx6sx"))
645 return true;
646 return false;
647}
648
649static int caam_ctrl_rng_init(struct device *dev)
650{
651 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
652 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
653 int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
654 u8 rng_vid;
655
656 if (ctrlpriv->era < 10) {
657 struct caam_perfmon __iomem *perfmon;
658
659 perfmon = ctrlpriv->total_jobrs ?
660 (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
661 (struct caam_perfmon __iomem *)&ctrl->perfmon;
662
663 rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
664 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
665 } else {
666 struct version_regs __iomem *vreg;
667
668 vreg = ctrlpriv->total_jobrs ?
669 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
670 (struct version_regs __iomem *)&ctrl->vreg;
671
672 rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
673 CHA_VER_VID_SHIFT;
674 }
675
676 /*
677 * If SEC has RNG version >= 4 and RNG state handle has not been
678 * already instantiated, do RNG instantiation
679 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
680 */
681 if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) {
682 ctrlpriv->rng4_sh_init =
683 rd_reg32(&ctrl->r4tst[0].rdsta);
684 /*
685 * If the secure keys (TDKEK, JDKEK, TDSK), were already
686 * generated, signal this to the function that is instantiating
687 * the state handles. An error would occur if RNG4 attempts
688 * to regenerate these keys before the next POR.
689 */
690 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
691 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
692 do {
693 int inst_handles =
694 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
695 /*
696 * If either SH were instantiated by somebody else
697 * (e.g. u-boot) then it is assumed that the entropy
698 * parameters are properly set and thus the function
699 * setting these (kick_trng(...)) is skipped.
700 * Also, if a handle was instantiated, do not change
701 * the TRNG parameters.
702 */
703 if (needs_entropy_delay_adjustment())
704 ent_delay = 12000;
705 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
706 dev_info(dev,
707 "Entropy delay = %u\n",
708 ent_delay);
709 kick_trng(dev, ent_delay);
710 ent_delay += 400;
711 }
712 /*
713 * if instantiate_rng(...) fails, the loop will rerun
714 * and the kick_trng(...) function will modify the
715 * upper and lower limits of the entropy sampling
716 * interval, leading to a successful initialization of
717 * the RNG.
718 */
719 ret = instantiate_rng(dev, inst_handles,
720 gen_sk);
721 /*
722 * Entropy delay is determined via TRNG characterization.
723 * TRNG characterization is run across different voltages
724 * and temperatures.
725 * If worst case value for ent_dly is identified,
726 * the loop can be skipped for that platform.
727 */
728 if (needs_entropy_delay_adjustment())
729 break;
730 if (ret == -EAGAIN)
731 /*
732 * if here, the loop will rerun,
733 * so don't hog the CPU
734 */
735 cpu_relax();
736 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
737 if (ret) {
738 dev_err(dev, "failed to instantiate RNG");
739 return ret;
740 }
741 /*
742 * Set handles initialized by this module as the complement of
743 * the already initialized ones
744 */
745 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
746
747 /* Enable RDB bit so that RNG works faster */
748 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
749 }
750
751 return 0;
752}
753
754/* Indicate if the internal state of the CAAM is lost during PM */
755static int caam_off_during_pm(void)
756{
757 bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") ||
758 of_machine_is_compatible("fsl,imx6qp") ||
759 of_machine_is_compatible("fsl,imx6dl");
760
761 return not_off_during_pm ? 0 : 1;
762}
763
764static void caam_state_save(struct device *dev)
765{
766 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
767 struct caam_ctl_state *state = &ctrlpriv->state;
768 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
769 u32 deco_inst, jr_inst;
770 int i;
771
772 state->mcr = rd_reg32(&ctrl->mcr);
773 state->scfgr = rd_reg32(&ctrl->scfgr);
774
775 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
776 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
777 for (i = 0; i < deco_inst; i++) {
778 state->deco_mid[i].liodn_ms =
779 rd_reg32(&ctrl->deco_mid[i].liodn_ms);
780 state->deco_mid[i].liodn_ls =
781 rd_reg32(&ctrl->deco_mid[i].liodn_ls);
782 }
783
784 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
785 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
786 for (i = 0; i < jr_inst; i++) {
787 state->jr_mid[i].liodn_ms =
788 rd_reg32(&ctrl->jr_mid[i].liodn_ms);
789 state->jr_mid[i].liodn_ls =
790 rd_reg32(&ctrl->jr_mid[i].liodn_ls);
791 }
792}
793
794static void caam_state_restore(const struct device *dev)
795{
796 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
797 const struct caam_ctl_state *state = &ctrlpriv->state;
798 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
799 u32 deco_inst, jr_inst;
800 int i;
801
802 wr_reg32(&ctrl->mcr, state->mcr);
803 wr_reg32(&ctrl->scfgr, state->scfgr);
804
805 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
806 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
807 for (i = 0; i < deco_inst; i++) {
808 wr_reg32(&ctrl->deco_mid[i].liodn_ms,
809 state->deco_mid[i].liodn_ms);
810 wr_reg32(&ctrl->deco_mid[i].liodn_ls,
811 state->deco_mid[i].liodn_ls);
812 }
813
814 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
815 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
816 for (i = 0; i < jr_inst; i++) {
817 wr_reg32(&ctrl->jr_mid[i].liodn_ms,
818 state->jr_mid[i].liodn_ms);
819 wr_reg32(&ctrl->jr_mid[i].liodn_ls,
820 state->jr_mid[i].liodn_ls);
821 }
822
823 if (ctrlpriv->virt_en == 1)
824 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
825 JRSTART_JR1_START | JRSTART_JR2_START |
826 JRSTART_JR3_START);
827}
828
829static int caam_ctrl_suspend(struct device *dev)
830{
831 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
832
833 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en)
834 caam_state_save(dev);
835
836 return 0;
837}
838
839static int caam_ctrl_resume(struct device *dev)
840{
841 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
842 int ret = 0;
843
844 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) {
845 caam_state_restore(dev);
846
847 /* HW and rng will be reset so deinstantiation can be removed */
848 devm_remove_action(dev, devm_deinstantiate_rng, dev);
849 ret = caam_ctrl_rng_init(dev);
850 }
851
852 return ret;
853}
854
855static DEFINE_SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume);
856
857/* Probe routine for CAAM top (controller) level */
858static int caam_probe(struct platform_device *pdev)
859{
860 int ret, ring;
861 u64 caam_id;
862 const struct soc_device_attribute *imx_soc_match;
863 struct device *dev;
864 struct device_node *nprop, *np;
865 struct caam_ctrl __iomem *ctrl;
866 struct caam_drv_private *ctrlpriv;
867 struct caam_perfmon __iomem *perfmon;
868 struct dentry *dfs_root;
869 u32 scfgr, comp_params;
870 int pg_size;
871 int BLOCK_OFFSET = 0;
872 bool reg_access = true;
873 const struct caam_imx_data *imx_soc_data;
874
875 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
876 if (!ctrlpriv)
877 return -ENOMEM;
878
879 dev = &pdev->dev;
880 dev_set_drvdata(dev, ctrlpriv);
881 nprop = pdev->dev.of_node;
882
883 imx_soc_match = soc_device_match(caam_imx_soc_table);
884 if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root))
885 return -EPROBE_DEFER;
886
887 caam_imx = (bool)imx_soc_match;
888
889 ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm();
890
891 if (imx_soc_match) {
892 /*
893 * Until Layerscape and i.MX OP-TEE get in sync,
894 * only i.MX OP-TEE use cases disallow access to
895 * caam page 0 (controller) registers.
896 */
897 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
898 ctrlpriv->optee_en = !!np;
899 of_node_put(np);
900
901 reg_access = !ctrlpriv->optee_en;
902
903 if (!imx_soc_match->data) {
904 dev_err(dev, "No clock data provided for i.MX SoC");
905 return -EINVAL;
906 }
907
908 imx_soc_data = imx_soc_match->data;
909 reg_access = reg_access && imx_soc_data->page0_access;
910 /*
911 * CAAM clocks cannot be controlled from kernel.
912 */
913 if (!imx_soc_data->num_clks)
914 goto iomap_ctrl;
915
916 ret = init_clocks(dev, imx_soc_match->data);
917 if (ret)
918 return ret;
919 }
920
921iomap_ctrl:
922 /* Get configuration properties from device tree */
923 /* First, get register page */
924 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
925 ret = PTR_ERR_OR_ZERO(ctrl);
926 if (ret) {
927 dev_err(dev, "caam: of_iomap() failed\n");
928 return ret;
929 }
930
931 ring = 0;
932 for_each_available_child_of_node(nprop, np)
933 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
934 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
935 u32 reg;
936
937 if (of_property_read_u32_index(np, "reg", 0, ®)) {
938 dev_err(dev, "%s read reg property error\n",
939 np->full_name);
940 continue;
941 }
942
943 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
944 ((__force uint8_t *)ctrl + reg);
945
946 ctrlpriv->total_jobrs++;
947 ring++;
948 }
949
950 /*
951 * Wherever possible, instead of accessing registers from the global page,
952 * use the alias registers in the first (cf. DT nodes order)
953 * job ring's page.
954 */
955 perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
956 (struct caam_perfmon __iomem *)&ctrl->perfmon;
957
958 caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
959 (CSTA_PLEND | CSTA_ALT_PLEND));
960 comp_params = rd_reg32(&perfmon->comp_parms_ms);
961 if (reg_access && comp_params & CTPR_MS_PS &&
962 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
963 caam_ptr_sz = sizeof(u64);
964 else
965 caam_ptr_sz = sizeof(u32);
966 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
967 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
968
969#ifdef CONFIG_CAAM_QI
970 /* If (DPAA 1.x) QI present, check whether dependencies are available */
971 if (ctrlpriv->qi_present && !caam_dpaa2) {
972 ret = qman_is_probed();
973 if (!ret) {
974 return -EPROBE_DEFER;
975 } else if (ret < 0) {
976 dev_err(dev, "failing probe due to qman probe error\n");
977 return -ENODEV;
978 }
979
980 ret = qman_portals_probed();
981 if (!ret) {
982 return -EPROBE_DEFER;
983 } else if (ret < 0) {
984 dev_err(dev, "failing probe due to qman portals probe error\n");
985 return -ENODEV;
986 }
987 }
988#endif
989
990 /* Allocating the BLOCK_OFFSET based on the supported page size on
991 * the platform
992 */
993 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
994 if (pg_size == 0)
995 BLOCK_OFFSET = PG_SIZE_4K;
996 else
997 BLOCK_OFFSET = PG_SIZE_64K;
998
999 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
1000 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
1001 ((__force uint8_t *)ctrl +
1002 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
1003 );
1004 ctrlpriv->deco = (struct caam_deco __iomem __force *)
1005 ((__force uint8_t *)ctrl +
1006 BLOCK_OFFSET * DECO_BLOCK_NUMBER
1007 );
1008
1009 /* Get the IRQ of the controller (for security violations only) */
1010 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
1011 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
1012 ctrlpriv->mc_en = !!np;
1013 of_node_put(np);
1014
1015#ifdef CONFIG_FSL_MC_BUS
1016 if (ctrlpriv->mc_en) {
1017 struct fsl_mc_version *mc_version;
1018
1019 mc_version = fsl_mc_get_version();
1020 if (mc_version)
1021 ctrlpriv->pr_support = check_version(mc_version, 10, 20,
1022 0);
1023 else
1024 return -EPROBE_DEFER;
1025 }
1026#endif
1027
1028 if (!reg_access)
1029 goto set_dma_mask;
1030
1031 /*
1032 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
1033 * long pointers in master configuration register.
1034 * In case of SoCs with Management Complex, MC f/w performs
1035 * the configuration.
1036 */
1037 if (!ctrlpriv->mc_en)
1038 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
1039 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
1040 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
1041
1042 handle_imx6_err005766(&ctrl->mcr);
1043
1044 /*
1045 * Read the Compile Time parameters and SCFGR to determine
1046 * if virtualization is enabled for this platform
1047 */
1048 scfgr = rd_reg32(&ctrl->scfgr);
1049
1050 ctrlpriv->virt_en = 0;
1051 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
1052 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
1053 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
1054 */
1055 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
1056 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
1057 (scfgr & SCFGR_VIRT_EN)))
1058 ctrlpriv->virt_en = 1;
1059 } else {
1060 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
1061 if (comp_params & CTPR_MS_VIRT_EN_POR)
1062 ctrlpriv->virt_en = 1;
1063 }
1064
1065 if (ctrlpriv->virt_en == 1)
1066 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
1067 JRSTART_JR1_START | JRSTART_JR2_START |
1068 JRSTART_JR3_START);
1069
1070set_dma_mask:
1071 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
1072 if (ret) {
1073 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
1074 return ret;
1075 }
1076
1077 ctrlpriv->era = caam_get_era(perfmon);
1078 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
1079
1080 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
1081 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1082 ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
1083 dfs_root);
1084 if (ret)
1085 return ret;
1086 }
1087
1088 caam_debugfs_init(ctrlpriv, perfmon, dfs_root);
1089
1090 /* Check to see if (DPAA 1.x) QI present. If so, enable */
1091 if (ctrlpriv->qi_present && !caam_dpaa2) {
1092 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
1093 ((__force uint8_t *)ctrl +
1094 BLOCK_OFFSET * QI_BLOCK_NUMBER
1095 );
1096 /* This is all that's required to physically enable QI */
1097 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
1098
1099 /* If QMAN driver is present, init CAAM-QI backend */
1100#ifdef CONFIG_CAAM_QI
1101 ret = caam_qi_init(pdev);
1102 if (ret)
1103 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
1104#endif
1105 }
1106
1107 /* If no QI and no rings specified, quit and go home */
1108 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
1109 dev_err(dev, "no queues configured, terminating\n");
1110 return -ENOMEM;
1111 }
1112
1113 comp_params = rd_reg32(&perfmon->comp_parms_ls);
1114 ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);
1115
1116 /*
1117 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,
1118 * but fail when actually using it due to missing AES support, so
1119 * check both here.
1120 */
1121 if (ctrlpriv->era < 10) {
1122 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1123 (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);
1124 } else {
1125 struct version_regs __iomem *vreg;
1126
1127 vreg = ctrlpriv->total_jobrs ?
1128 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
1129 (struct version_regs __iomem *)&ctrl->vreg;
1130
1131 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1132 (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);
1133 }
1134
1135 if (reg_access) {
1136 ret = caam_ctrl_rng_init(dev);
1137 if (ret)
1138 return ret;
1139 }
1140
1141 caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
1142 (u64)rd_reg32(&perfmon->caam_id_ls);
1143
1144 /* Report "alive" for developer to see */
1145 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
1146 ctrlpriv->era);
1147 dev_info(dev, "job rings = %d, qi = %d\n",
1148 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
1149
1150 ret = devm_of_platform_populate(dev);
1151 if (ret)
1152 dev_err(dev, "JR platform devices creation error\n");
1153
1154 return ret;
1155}
1156
1157static struct platform_driver caam_driver = {
1158 .driver = {
1159 .name = "caam",
1160 .of_match_table = caam_match,
1161 .pm = pm_ptr(&caam_ctrl_pm_ops),
1162 },
1163 .probe = caam_probe,
1164};
1165
1166module_platform_driver(caam_driver);
1167
1168MODULE_LICENSE("GPL");
1169MODULE_DESCRIPTION("FSL CAAM request backend");
1170MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");