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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/kernel.h>
12#include <linux/kernel_stat.h>
13#include <linux/module.h>
14#include <linux/ktime.h>
15#include <linux/hrtimer.h>
16#include <linux/tick.h>
17#include <linux/slab.h>
18#include <linux/sched/cpufreq.h>
19#include <linux/list.h>
20#include <linux/cpu.h>
21#include <linux/cpufreq.h>
22#include <linux/sysfs.h>
23#include <linux/types.h>
24#include <linux/fs.h>
25#include <linux/acpi.h>
26#include <linux/vmalloc.h>
27#include <linux/pm_qos.h>
28#include <trace/events/power.h>
29
30#include <asm/cpu.h>
31#include <asm/div64.h>
32#include <asm/msr.h>
33#include <asm/cpu_device_id.h>
34#include <asm/cpufeature.h>
35#include <asm/intel-family.h>
36#include "../drivers/thermal/intel/thermal_interrupt.h"
37
38#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
39
40#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41#define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
42#define INTEL_CPUFREQ_TRANSITION_DELAY 500
43
44#ifdef CONFIG_ACPI
45#include <acpi/processor.h>
46#include <acpi/cppc_acpi.h>
47#endif
48
49#define FRAC_BITS 8
50#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51#define fp_toint(X) ((X) >> FRAC_BITS)
52
53#define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
54
55#define EXT_BITS 6
56#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60static inline int32_t mul_fp(int32_t x, int32_t y)
61{
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63}
64
65static inline int32_t div_fp(s64 x, s64 y)
66{
67 return div64_s64((int64_t)x << FRAC_BITS, y);
68}
69
70static inline int ceiling_fp(int32_t x)
71{
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79}
80
81static inline u64 mul_ext_fp(u64 x, u64 y)
82{
83 return (x * y) >> EXT_FRAC_BITS;
84}
85
86static inline u64 div_ext_fp(u64 x, u64 y)
87{
88 return div64_u64(x << EXT_FRAC_BITS, y);
89}
90
91/**
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
103 * current sample
104 * @time: Current time from scheduler
105 *
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
108 */
109struct sample {
110 int32_t core_avg_perf;
111 int32_t busy_scaled;
112 u64 aperf;
113 u64 mperf;
114 u64 tsc;
115 u64 time;
116};
117
118/**
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
127 * @scaling: Scaling factor between performance and frequency
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @min_freq: @min_pstate frequency in cpufreq units
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
132 *
133 * Stores the per cpu model P state limits and current P state.
134 */
135struct pstate_data {
136 int current_pstate;
137 int min_pstate;
138 int max_pstate;
139 int max_pstate_physical;
140 int perf_ctl_scaling;
141 int scaling;
142 int turbo_pstate;
143 unsigned int min_freq;
144 unsigned int max_freq;
145 unsigned int turbo_freq;
146};
147
148/**
149 * struct vid_data - Stores voltage information data
150 * @min: VID data for this platform corresponding to
151 * the lowest P state
152 * @max: VID data corresponding to the highest P State.
153 * @turbo: VID data for turbo P state
154 * @ratio: Ratio of (vid max - vid min) /
155 * (max P state - Min P State)
156 *
157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
158 * This data is used in Atom platforms, where in addition to target P state,
159 * the voltage data needs to be specified to select next P State.
160 */
161struct vid_data {
162 int min;
163 int max;
164 int turbo;
165 int32_t ratio;
166};
167
168/**
169 * struct global_params - Global parameters, mostly tunable via sysfs.
170 * @no_turbo: Whether or not to use turbo P-states.
171 * @turbo_disabled: Whether or not turbo P-states are available at all,
172 * based on the MSR_IA32_MISC_ENABLE value and whether or
173 * not the maximum reported turbo P-state is different from
174 * the maximum reported non-turbo one.
175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
177 * P-state capacity.
178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
179 * P-state capacity.
180 */
181struct global_params {
182 bool no_turbo;
183 bool turbo_disabled;
184 bool turbo_disabled_mf;
185 int max_perf_pct;
186 int min_perf_pct;
187};
188
189/**
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @prev_cummulative_iowait: IO Wait time difference from last and
205 * current sample
206 * @sample: Storage for storing last Sample data
207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
209 * @acpi_perf_data: Stores ACPI perf information read from _PSS
210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
211 * @epp_powersave: Last saved HWP energy performance preference
212 * (EPP) or energy performance bias (EPB),
213 * when policy switched to performance
214 * @epp_policy: Last saved policy used to set EPP/EPB
215 * @epp_default: Power on default HWP energy performance
216 * preference/bias
217 * @epp_cached Cached HWP energy-performance preference value
218 * @hwp_req_cached: Cached value of the last HWP Request MSR
219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
220 * @last_io_update: Last time when IO wake flag was set
221 * @sched_flags: Store scheduler flags for possible cross CPU update
222 * @hwp_boost_min: Last HWP boosted min performance
223 * @suspended: Whether or not the driver has been suspended.
224 * @hwp_notify_work: workqueue for HWP notifications.
225 *
226 * This structure stores per CPU instance data for all CPUs.
227 */
228struct cpudata {
229 int cpu;
230
231 unsigned int policy;
232 struct update_util_data update_util;
233 bool update_util_set;
234
235 struct pstate_data pstate;
236 struct vid_data vid;
237
238 u64 last_update;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
241 u64 prev_aperf;
242 u64 prev_mperf;
243 u64 prev_tsc;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248#ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251#endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_cached;
257 u64 hwp_req_cached;
258 u64 hwp_cap_cached;
259 u64 last_io_update;
260 unsigned int sched_flags;
261 u32 hwp_boost_min;
262 bool suspended;
263 struct delayed_work hwp_notify_work;
264};
265
266static struct cpudata **all_cpu_data;
267
268/**
269 * struct pstate_funcs - Per CPU model specific callbacks
270 * @get_max: Callback to get maximum non turbo effective P state
271 * @get_max_physical: Callback to get maximum non turbo physical P state
272 * @get_min: Callback to get minimum P state
273 * @get_turbo: Callback to get turbo P state
274 * @get_scaling: Callback to get frequency scaling factor
275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
279 *
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
282 */
283struct pstate_funcs {
284 int (*get_max)(int cpu);
285 int (*get_max_physical)(int cpu);
286 int (*get_min)(int cpu);
287 int (*get_turbo)(int cpu);
288 int (*get_scaling)(void);
289 int (*get_cpu_scaling)(int cpu);
290 int (*get_aperf_mperf_shift)(void);
291 u64 (*get_val)(struct cpudata*, int pstate);
292 void (*get_vid)(struct cpudata *);
293};
294
295static struct pstate_funcs pstate_funcs __read_mostly;
296
297static int hwp_active __read_mostly;
298static int hwp_mode_bdw __read_mostly;
299static bool per_cpu_limits __read_mostly;
300static bool hwp_boost __read_mostly;
301static bool hwp_forced __read_mostly;
302
303static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304
305#define HYBRID_SCALING_FACTOR 78741
306#define HYBRID_SCALING_FACTOR_MTL 80000
307
308static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
309
310static inline int core_get_scaling(void)
311{
312 return 100000;
313}
314
315#ifdef CONFIG_ACPI
316static bool acpi_ppc;
317#endif
318
319static struct global_params global;
320
321static DEFINE_MUTEX(intel_pstate_driver_lock);
322static DEFINE_MUTEX(intel_pstate_limits_lock);
323
324#ifdef CONFIG_ACPI
325
326static bool intel_pstate_acpi_pm_profile_server(void)
327{
328 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
329 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
330 return true;
331
332 return false;
333}
334
335static bool intel_pstate_get_ppc_enable_status(void)
336{
337 if (intel_pstate_acpi_pm_profile_server())
338 return true;
339
340 return acpi_ppc;
341}
342
343#ifdef CONFIG_ACPI_CPPC_LIB
344
345/* The work item is needed to avoid CPU hotplug locking issues */
346static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
347{
348 sched_set_itmt_support();
349}
350
351static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
352
353#define CPPC_MAX_PERF U8_MAX
354
355static void intel_pstate_set_itmt_prio(int cpu)
356{
357 struct cppc_perf_caps cppc_perf;
358 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
359 int ret;
360
361 ret = cppc_get_perf_caps(cpu, &cppc_perf);
362 if (ret)
363 return;
364
365 /*
366 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
367 * In this case we can't use CPPC.highest_perf to enable ITMT.
368 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
369 */
370 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
371 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
372
373 /*
374 * The priorities can be set regardless of whether or not
375 * sched_set_itmt_support(true) has been called and it is valid to
376 * update them at any time after it has been called.
377 */
378 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
379
380 if (max_highest_perf <= min_highest_perf) {
381 if (cppc_perf.highest_perf > max_highest_perf)
382 max_highest_perf = cppc_perf.highest_perf;
383
384 if (cppc_perf.highest_perf < min_highest_perf)
385 min_highest_perf = cppc_perf.highest_perf;
386
387 if (max_highest_perf > min_highest_perf) {
388 /*
389 * This code can be run during CPU online under the
390 * CPU hotplug locks, so sched_set_itmt_support()
391 * cannot be called from here. Queue up a work item
392 * to invoke it.
393 */
394 schedule_work(&sched_itmt_work);
395 }
396 }
397}
398
399static int intel_pstate_get_cppc_guaranteed(int cpu)
400{
401 struct cppc_perf_caps cppc_perf;
402 int ret;
403
404 ret = cppc_get_perf_caps(cpu, &cppc_perf);
405 if (ret)
406 return ret;
407
408 if (cppc_perf.guaranteed_perf)
409 return cppc_perf.guaranteed_perf;
410
411 return cppc_perf.nominal_perf;
412}
413
414static int intel_pstate_cppc_get_scaling(int cpu)
415{
416 struct cppc_perf_caps cppc_perf;
417 int ret;
418
419 ret = cppc_get_perf_caps(cpu, &cppc_perf);
420
421 /*
422 * If the nominal frequency and the nominal performance are not
423 * zero and the ratio between them is not 100, return the hybrid
424 * scaling factor.
425 */
426 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
427 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
428 return hybrid_scaling_factor;
429
430 return core_get_scaling();
431}
432
433#else /* CONFIG_ACPI_CPPC_LIB */
434static inline void intel_pstate_set_itmt_prio(int cpu)
435{
436}
437#endif /* CONFIG_ACPI_CPPC_LIB */
438
439static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
440{
441 struct cpudata *cpu;
442 int ret;
443 int i;
444
445 if (hwp_active) {
446 intel_pstate_set_itmt_prio(policy->cpu);
447 return;
448 }
449
450 if (!intel_pstate_get_ppc_enable_status())
451 return;
452
453 cpu = all_cpu_data[policy->cpu];
454
455 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
456 policy->cpu);
457 if (ret)
458 return;
459
460 /*
461 * Check if the control value in _PSS is for PERF_CTL MSR, which should
462 * guarantee that the states returned by it map to the states in our
463 * list directly.
464 */
465 if (cpu->acpi_perf_data.control_register.space_id !=
466 ACPI_ADR_SPACE_FIXED_HARDWARE)
467 goto err;
468
469 /*
470 * If there is only one entry _PSS, simply ignore _PSS and continue as
471 * usual without taking _PSS into account
472 */
473 if (cpu->acpi_perf_data.state_count < 2)
474 goto err;
475
476 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
477 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
478 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
479 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
480 (u32) cpu->acpi_perf_data.states[i].core_frequency,
481 (u32) cpu->acpi_perf_data.states[i].power,
482 (u32) cpu->acpi_perf_data.states[i].control);
483 }
484
485 cpu->valid_pss_table = true;
486 pr_debug("_PPC limits will be enforced\n");
487
488 return;
489
490 err:
491 cpu->valid_pss_table = false;
492 acpi_processor_unregister_performance(policy->cpu);
493}
494
495static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
496{
497 struct cpudata *cpu;
498
499 cpu = all_cpu_data[policy->cpu];
500 if (!cpu->valid_pss_table)
501 return;
502
503 acpi_processor_unregister_performance(policy->cpu);
504}
505#else /* CONFIG_ACPI */
506static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
507{
508}
509
510static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
511{
512}
513
514static inline bool intel_pstate_acpi_pm_profile_server(void)
515{
516 return false;
517}
518#endif /* CONFIG_ACPI */
519
520#ifndef CONFIG_ACPI_CPPC_LIB
521static inline int intel_pstate_get_cppc_guaranteed(int cpu)
522{
523 return -ENOTSUPP;
524}
525
526static int intel_pstate_cppc_get_scaling(int cpu)
527{
528 return core_get_scaling();
529}
530#endif /* CONFIG_ACPI_CPPC_LIB */
531
532static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
533 unsigned int relation)
534{
535 if (freq == cpu->pstate.turbo_freq)
536 return cpu->pstate.turbo_pstate;
537
538 if (freq == cpu->pstate.max_freq)
539 return cpu->pstate.max_pstate;
540
541 switch (relation) {
542 case CPUFREQ_RELATION_H:
543 return freq / cpu->pstate.scaling;
544 case CPUFREQ_RELATION_C:
545 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
546 }
547
548 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
549}
550
551static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
552{
553 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
554}
555
556/**
557 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
558 * @cpu: Target CPU.
559 *
560 * On hybrid processors, HWP may expose more performance levels than there are
561 * P-states accessible through the PERF_CTL interface. If that happens, the
562 * scaling factor between HWP performance levels and CPU frequency will be less
563 * than the scaling factor between P-state values and CPU frequency.
564 *
565 * In that case, adjust the CPU parameters used in computations accordingly.
566 */
567static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
568{
569 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
570 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
571 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
572 int scaling = cpu->pstate.scaling;
573 int freq;
574
575 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
576 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
577 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
578 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
579 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
580 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
581
582 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
583 perf_ctl_scaling);
584 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
585 perf_ctl_scaling);
586
587 freq = perf_ctl_max_phys * perf_ctl_scaling;
588 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
589
590 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
591 cpu->pstate.min_freq = freq;
592 /*
593 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
594 * the effective range of HWP performance levels.
595 */
596 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
597}
598
599static inline void update_turbo_state(void)
600{
601 u64 misc_en;
602
603 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
604 global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
605}
606
607static int min_perf_pct_min(void)
608{
609 struct cpudata *cpu = all_cpu_data[0];
610 int turbo_pstate = cpu->pstate.turbo_pstate;
611
612 return turbo_pstate ?
613 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
614}
615
616static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
617{
618 u64 epb;
619 int ret;
620
621 if (!boot_cpu_has(X86_FEATURE_EPB))
622 return -ENXIO;
623
624 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
625 if (ret)
626 return (s16)ret;
627
628 return (s16)(epb & 0x0f);
629}
630
631static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
632{
633 s16 epp;
634
635 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
636 /*
637 * When hwp_req_data is 0, means that caller didn't read
638 * MSR_HWP_REQUEST, so need to read and get EPP.
639 */
640 if (!hwp_req_data) {
641 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
642 &hwp_req_data);
643 if (epp)
644 return epp;
645 }
646 epp = (hwp_req_data >> 24) & 0xff;
647 } else {
648 /* When there is no EPP present, HWP uses EPB settings */
649 epp = intel_pstate_get_epb(cpu_data);
650 }
651
652 return epp;
653}
654
655static int intel_pstate_set_epb(int cpu, s16 pref)
656{
657 u64 epb;
658 int ret;
659
660 if (!boot_cpu_has(X86_FEATURE_EPB))
661 return -ENXIO;
662
663 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
664 if (ret)
665 return ret;
666
667 epb = (epb & ~0x0f) | pref;
668 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
669
670 return 0;
671}
672
673/*
674 * EPP/EPB display strings corresponding to EPP index in the
675 * energy_perf_strings[]
676 * index String
677 *-------------------------------------
678 * 0 default
679 * 1 performance
680 * 2 balance_performance
681 * 3 balance_power
682 * 4 power
683 */
684
685enum energy_perf_value_index {
686 EPP_INDEX_DEFAULT = 0,
687 EPP_INDEX_PERFORMANCE,
688 EPP_INDEX_BALANCE_PERFORMANCE,
689 EPP_INDEX_BALANCE_POWERSAVE,
690 EPP_INDEX_POWERSAVE,
691};
692
693static const char * const energy_perf_strings[] = {
694 [EPP_INDEX_DEFAULT] = "default",
695 [EPP_INDEX_PERFORMANCE] = "performance",
696 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
697 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
698 [EPP_INDEX_POWERSAVE] = "power",
699 NULL
700};
701static unsigned int epp_values[] = {
702 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
703 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
704 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
705 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
706 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
707};
708
709static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
710{
711 s16 epp;
712 int index = -EINVAL;
713
714 *raw_epp = 0;
715 epp = intel_pstate_get_epp(cpu_data, 0);
716 if (epp < 0)
717 return epp;
718
719 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
720 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
721 return EPP_INDEX_PERFORMANCE;
722 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
723 return EPP_INDEX_BALANCE_PERFORMANCE;
724 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
725 return EPP_INDEX_BALANCE_POWERSAVE;
726 if (epp == epp_values[EPP_INDEX_POWERSAVE])
727 return EPP_INDEX_POWERSAVE;
728 *raw_epp = epp;
729 return 0;
730 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
731 /*
732 * Range:
733 * 0x00-0x03 : Performance
734 * 0x04-0x07 : Balance performance
735 * 0x08-0x0B : Balance power
736 * 0x0C-0x0F : Power
737 * The EPB is a 4 bit value, but our ranges restrict the
738 * value which can be set. Here only using top two bits
739 * effectively.
740 */
741 index = (epp >> 2) + 1;
742 }
743
744 return index;
745}
746
747static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
748{
749 int ret;
750
751 /*
752 * Use the cached HWP Request MSR value, because in the active mode the
753 * register itself may be updated by intel_pstate_hwp_boost_up() or
754 * intel_pstate_hwp_boost_down() at any time.
755 */
756 u64 value = READ_ONCE(cpu->hwp_req_cached);
757
758 value &= ~GENMASK_ULL(31, 24);
759 value |= (u64)epp << 24;
760 /*
761 * The only other updater of hwp_req_cached in the active mode,
762 * intel_pstate_hwp_set(), is called under the same lock as this
763 * function, so it cannot run in parallel with the update below.
764 */
765 WRITE_ONCE(cpu->hwp_req_cached, value);
766 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
767 if (!ret)
768 cpu->epp_cached = epp;
769
770 return ret;
771}
772
773static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
774 int pref_index, bool use_raw,
775 u32 raw_epp)
776{
777 int epp = -EINVAL;
778 int ret;
779
780 if (!pref_index)
781 epp = cpu_data->epp_default;
782
783 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
784 if (use_raw)
785 epp = raw_epp;
786 else if (epp == -EINVAL)
787 epp = epp_values[pref_index];
788
789 /*
790 * To avoid confusion, refuse to set EPP to any values different
791 * from 0 (performance) if the current policy is "performance",
792 * because those values would be overridden.
793 */
794 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
795 return -EBUSY;
796
797 ret = intel_pstate_set_epp(cpu_data, epp);
798 } else {
799 if (epp == -EINVAL)
800 epp = (pref_index - 1) << 2;
801 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
802 }
803
804 return ret;
805}
806
807static ssize_t show_energy_performance_available_preferences(
808 struct cpufreq_policy *policy, char *buf)
809{
810 int i = 0;
811 int ret = 0;
812
813 while (energy_perf_strings[i] != NULL)
814 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
815
816 ret += sprintf(&buf[ret], "\n");
817
818 return ret;
819}
820
821cpufreq_freq_attr_ro(energy_performance_available_preferences);
822
823static struct cpufreq_driver intel_pstate;
824
825static ssize_t store_energy_performance_preference(
826 struct cpufreq_policy *policy, const char *buf, size_t count)
827{
828 struct cpudata *cpu = all_cpu_data[policy->cpu];
829 char str_preference[21];
830 bool raw = false;
831 ssize_t ret;
832 u32 epp = 0;
833
834 ret = sscanf(buf, "%20s", str_preference);
835 if (ret != 1)
836 return -EINVAL;
837
838 ret = match_string(energy_perf_strings, -1, str_preference);
839 if (ret < 0) {
840 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
841 return ret;
842
843 ret = kstrtouint(buf, 10, &epp);
844 if (ret)
845 return ret;
846
847 if (epp > 255)
848 return -EINVAL;
849
850 raw = true;
851 }
852
853 /*
854 * This function runs with the policy R/W semaphore held, which
855 * guarantees that the driver pointer will not change while it is
856 * running.
857 */
858 if (!intel_pstate_driver)
859 return -EAGAIN;
860
861 mutex_lock(&intel_pstate_limits_lock);
862
863 if (intel_pstate_driver == &intel_pstate) {
864 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
865 } else {
866 /*
867 * In the passive mode the governor needs to be stopped on the
868 * target CPU before the EPP update and restarted after it,
869 * which is super-heavy-weight, so make sure it is worth doing
870 * upfront.
871 */
872 if (!raw)
873 epp = ret ? epp_values[ret] : cpu->epp_default;
874
875 if (cpu->epp_cached != epp) {
876 int err;
877
878 cpufreq_stop_governor(policy);
879 ret = intel_pstate_set_epp(cpu, epp);
880 err = cpufreq_start_governor(policy);
881 if (!ret)
882 ret = err;
883 } else {
884 ret = 0;
885 }
886 }
887
888 mutex_unlock(&intel_pstate_limits_lock);
889
890 return ret ?: count;
891}
892
893static ssize_t show_energy_performance_preference(
894 struct cpufreq_policy *policy, char *buf)
895{
896 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
897 int preference, raw_epp;
898
899 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
900 if (preference < 0)
901 return preference;
902
903 if (raw_epp)
904 return sprintf(buf, "%d\n", raw_epp);
905 else
906 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
907}
908
909cpufreq_freq_attr_rw(energy_performance_preference);
910
911static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
912{
913 struct cpudata *cpu = all_cpu_data[policy->cpu];
914 int ratio, freq;
915
916 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
917 if (ratio <= 0) {
918 u64 cap;
919
920 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
921 ratio = HWP_GUARANTEED_PERF(cap);
922 }
923
924 freq = ratio * cpu->pstate.scaling;
925 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
926 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
927
928 return sprintf(buf, "%d\n", freq);
929}
930
931cpufreq_freq_attr_ro(base_frequency);
932
933static struct freq_attr *hwp_cpufreq_attrs[] = {
934 &energy_performance_preference,
935 &energy_performance_available_preferences,
936 &base_frequency,
937 NULL,
938};
939
940static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
941{
942 u64 cap;
943
944 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
945 WRITE_ONCE(cpu->hwp_cap_cached, cap);
946 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
947 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
948}
949
950static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
951{
952 int scaling = cpu->pstate.scaling;
953
954 __intel_pstate_get_hwp_cap(cpu);
955
956 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
957 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
958 if (scaling != cpu->pstate.perf_ctl_scaling) {
959 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
960
961 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
962 perf_ctl_scaling);
963 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
964 perf_ctl_scaling);
965 }
966}
967
968static void intel_pstate_hwp_set(unsigned int cpu)
969{
970 struct cpudata *cpu_data = all_cpu_data[cpu];
971 int max, min;
972 u64 value;
973 s16 epp;
974
975 max = cpu_data->max_perf_ratio;
976 min = cpu_data->min_perf_ratio;
977
978 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
979 min = max;
980
981 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
982
983 value &= ~HWP_MIN_PERF(~0L);
984 value |= HWP_MIN_PERF(min);
985
986 value &= ~HWP_MAX_PERF(~0L);
987 value |= HWP_MAX_PERF(max);
988
989 if (cpu_data->epp_policy == cpu_data->policy)
990 goto skip_epp;
991
992 cpu_data->epp_policy = cpu_data->policy;
993
994 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
995 epp = intel_pstate_get_epp(cpu_data, value);
996 cpu_data->epp_powersave = epp;
997 /* If EPP read was failed, then don't try to write */
998 if (epp < 0)
999 goto skip_epp;
1000
1001 epp = 0;
1002 } else {
1003 /* skip setting EPP, when saved value is invalid */
1004 if (cpu_data->epp_powersave < 0)
1005 goto skip_epp;
1006
1007 /*
1008 * No need to restore EPP when it is not zero. This
1009 * means:
1010 * - Policy is not changed
1011 * - user has manually changed
1012 * - Error reading EPB
1013 */
1014 epp = intel_pstate_get_epp(cpu_data, value);
1015 if (epp)
1016 goto skip_epp;
1017
1018 epp = cpu_data->epp_powersave;
1019 }
1020 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1021 value &= ~GENMASK_ULL(31, 24);
1022 value |= (u64)epp << 24;
1023 } else {
1024 intel_pstate_set_epb(cpu, epp);
1025 }
1026skip_epp:
1027 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1028 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1029}
1030
1031static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1032
1033static void intel_pstate_hwp_offline(struct cpudata *cpu)
1034{
1035 u64 value = READ_ONCE(cpu->hwp_req_cached);
1036 int min_perf;
1037
1038 intel_pstate_disable_hwp_interrupt(cpu);
1039
1040 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1041 /*
1042 * In case the EPP has been set to "performance" by the
1043 * active mode "performance" scaling algorithm, replace that
1044 * temporary value with the cached EPP one.
1045 */
1046 value &= ~GENMASK_ULL(31, 24);
1047 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1048 /*
1049 * However, make sure that EPP will be set to "performance" when
1050 * the CPU is brought back online again and the "performance"
1051 * scaling algorithm is still in effect.
1052 */
1053 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1054 }
1055
1056 /*
1057 * Clear the desired perf field in the cached HWP request value to
1058 * prevent nonzero desired values from being leaked into the active
1059 * mode.
1060 */
1061 value &= ~HWP_DESIRED_PERF(~0L);
1062 WRITE_ONCE(cpu->hwp_req_cached, value);
1063
1064 value &= ~GENMASK_ULL(31, 0);
1065 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1066
1067 /* Set hwp_max = hwp_min */
1068 value |= HWP_MAX_PERF(min_perf);
1069 value |= HWP_MIN_PERF(min_perf);
1070
1071 /* Set EPP to min */
1072 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1073 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1074
1075 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1076}
1077
1078#define POWER_CTL_EE_ENABLE 1
1079#define POWER_CTL_EE_DISABLE 2
1080
1081static int power_ctl_ee_state;
1082
1083static void set_power_ctl_ee_state(bool input)
1084{
1085 u64 power_ctl;
1086
1087 mutex_lock(&intel_pstate_driver_lock);
1088 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1089 if (input) {
1090 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1091 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1092 } else {
1093 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1094 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1095 }
1096 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1097 mutex_unlock(&intel_pstate_driver_lock);
1098}
1099
1100static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1101
1102static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1103{
1104 intel_pstate_hwp_enable(cpu);
1105 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1106}
1107
1108static int intel_pstate_suspend(struct cpufreq_policy *policy)
1109{
1110 struct cpudata *cpu = all_cpu_data[policy->cpu];
1111
1112 pr_debug("CPU %d suspending\n", cpu->cpu);
1113
1114 cpu->suspended = true;
1115
1116 /* disable HWP interrupt and cancel any pending work */
1117 intel_pstate_disable_hwp_interrupt(cpu);
1118
1119 return 0;
1120}
1121
1122static int intel_pstate_resume(struct cpufreq_policy *policy)
1123{
1124 struct cpudata *cpu = all_cpu_data[policy->cpu];
1125
1126 pr_debug("CPU %d resuming\n", cpu->cpu);
1127
1128 /* Only restore if the system default is changed */
1129 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1130 set_power_ctl_ee_state(true);
1131 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1132 set_power_ctl_ee_state(false);
1133
1134 if (cpu->suspended && hwp_active) {
1135 mutex_lock(&intel_pstate_limits_lock);
1136
1137 /* Re-enable HWP, because "online" has not done that. */
1138 intel_pstate_hwp_reenable(cpu);
1139
1140 mutex_unlock(&intel_pstate_limits_lock);
1141 }
1142
1143 cpu->suspended = false;
1144
1145 return 0;
1146}
1147
1148static void intel_pstate_update_policies(void)
1149{
1150 int cpu;
1151
1152 for_each_possible_cpu(cpu)
1153 cpufreq_update_policy(cpu);
1154}
1155
1156static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1157 struct cpufreq_policy *policy)
1158{
1159 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1160 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1161 refresh_frequency_limits(policy);
1162}
1163
1164static void intel_pstate_update_max_freq(unsigned int cpu)
1165{
1166 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1167
1168 if (!policy)
1169 return;
1170
1171 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1172
1173 cpufreq_cpu_release(policy);
1174}
1175
1176static void intel_pstate_update_limits(unsigned int cpu)
1177{
1178 mutex_lock(&intel_pstate_driver_lock);
1179
1180 update_turbo_state();
1181 /*
1182 * If turbo has been turned on or off globally, policy limits for
1183 * all CPUs need to be updated to reflect that.
1184 */
1185 if (global.turbo_disabled_mf != global.turbo_disabled) {
1186 global.turbo_disabled_mf = global.turbo_disabled;
1187 arch_set_max_freq_ratio(global.turbo_disabled);
1188 for_each_possible_cpu(cpu)
1189 intel_pstate_update_max_freq(cpu);
1190 } else {
1191 cpufreq_update_policy(cpu);
1192 }
1193
1194 mutex_unlock(&intel_pstate_driver_lock);
1195}
1196
1197/************************** sysfs begin ************************/
1198#define show_one(file_name, object) \
1199 static ssize_t show_##file_name \
1200 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1201 { \
1202 return sprintf(buf, "%u\n", global.object); \
1203 }
1204
1205static ssize_t intel_pstate_show_status(char *buf);
1206static int intel_pstate_update_status(const char *buf, size_t size);
1207
1208static ssize_t show_status(struct kobject *kobj,
1209 struct kobj_attribute *attr, char *buf)
1210{
1211 ssize_t ret;
1212
1213 mutex_lock(&intel_pstate_driver_lock);
1214 ret = intel_pstate_show_status(buf);
1215 mutex_unlock(&intel_pstate_driver_lock);
1216
1217 return ret;
1218}
1219
1220static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1221 const char *buf, size_t count)
1222{
1223 char *p = memchr(buf, '\n', count);
1224 int ret;
1225
1226 mutex_lock(&intel_pstate_driver_lock);
1227 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1228 mutex_unlock(&intel_pstate_driver_lock);
1229
1230 return ret < 0 ? ret : count;
1231}
1232
1233static ssize_t show_turbo_pct(struct kobject *kobj,
1234 struct kobj_attribute *attr, char *buf)
1235{
1236 struct cpudata *cpu;
1237 int total, no_turbo, turbo_pct;
1238 uint32_t turbo_fp;
1239
1240 mutex_lock(&intel_pstate_driver_lock);
1241
1242 if (!intel_pstate_driver) {
1243 mutex_unlock(&intel_pstate_driver_lock);
1244 return -EAGAIN;
1245 }
1246
1247 cpu = all_cpu_data[0];
1248
1249 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1250 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1251 turbo_fp = div_fp(no_turbo, total);
1252 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1253
1254 mutex_unlock(&intel_pstate_driver_lock);
1255
1256 return sprintf(buf, "%u\n", turbo_pct);
1257}
1258
1259static ssize_t show_num_pstates(struct kobject *kobj,
1260 struct kobj_attribute *attr, char *buf)
1261{
1262 struct cpudata *cpu;
1263 int total;
1264
1265 mutex_lock(&intel_pstate_driver_lock);
1266
1267 if (!intel_pstate_driver) {
1268 mutex_unlock(&intel_pstate_driver_lock);
1269 return -EAGAIN;
1270 }
1271
1272 cpu = all_cpu_data[0];
1273 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1274
1275 mutex_unlock(&intel_pstate_driver_lock);
1276
1277 return sprintf(buf, "%u\n", total);
1278}
1279
1280static ssize_t show_no_turbo(struct kobject *kobj,
1281 struct kobj_attribute *attr, char *buf)
1282{
1283 ssize_t ret;
1284
1285 mutex_lock(&intel_pstate_driver_lock);
1286
1287 if (!intel_pstate_driver) {
1288 mutex_unlock(&intel_pstate_driver_lock);
1289 return -EAGAIN;
1290 }
1291
1292 update_turbo_state();
1293 if (global.turbo_disabled)
1294 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1295 else
1296 ret = sprintf(buf, "%u\n", global.no_turbo);
1297
1298 mutex_unlock(&intel_pstate_driver_lock);
1299
1300 return ret;
1301}
1302
1303static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1304 const char *buf, size_t count)
1305{
1306 unsigned int input;
1307 int ret;
1308
1309 ret = sscanf(buf, "%u", &input);
1310 if (ret != 1)
1311 return -EINVAL;
1312
1313 mutex_lock(&intel_pstate_driver_lock);
1314
1315 if (!intel_pstate_driver) {
1316 mutex_unlock(&intel_pstate_driver_lock);
1317 return -EAGAIN;
1318 }
1319
1320 mutex_lock(&intel_pstate_limits_lock);
1321
1322 update_turbo_state();
1323 if (global.turbo_disabled) {
1324 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1325 mutex_unlock(&intel_pstate_limits_lock);
1326 mutex_unlock(&intel_pstate_driver_lock);
1327 return -EPERM;
1328 }
1329
1330 global.no_turbo = clamp_t(int, input, 0, 1);
1331
1332 if (global.no_turbo) {
1333 struct cpudata *cpu = all_cpu_data[0];
1334 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1335
1336 /* Squash the global minimum into the permitted range. */
1337 if (global.min_perf_pct > pct)
1338 global.min_perf_pct = pct;
1339 }
1340
1341 mutex_unlock(&intel_pstate_limits_lock);
1342
1343 intel_pstate_update_policies();
1344 arch_set_max_freq_ratio(global.no_turbo);
1345
1346 mutex_unlock(&intel_pstate_driver_lock);
1347
1348 return count;
1349}
1350
1351static void update_qos_request(enum freq_qos_req_type type)
1352{
1353 struct freq_qos_request *req;
1354 struct cpufreq_policy *policy;
1355 int i;
1356
1357 for_each_possible_cpu(i) {
1358 struct cpudata *cpu = all_cpu_data[i];
1359 unsigned int freq, perf_pct;
1360
1361 policy = cpufreq_cpu_get(i);
1362 if (!policy)
1363 continue;
1364
1365 req = policy->driver_data;
1366 cpufreq_cpu_put(policy);
1367
1368 if (!req)
1369 continue;
1370
1371 if (hwp_active)
1372 intel_pstate_get_hwp_cap(cpu);
1373
1374 if (type == FREQ_QOS_MIN) {
1375 perf_pct = global.min_perf_pct;
1376 } else {
1377 req++;
1378 perf_pct = global.max_perf_pct;
1379 }
1380
1381 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1382
1383 if (freq_qos_update_request(req, freq) < 0)
1384 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1385 }
1386}
1387
1388static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1389 const char *buf, size_t count)
1390{
1391 unsigned int input;
1392 int ret;
1393
1394 ret = sscanf(buf, "%u", &input);
1395 if (ret != 1)
1396 return -EINVAL;
1397
1398 mutex_lock(&intel_pstate_driver_lock);
1399
1400 if (!intel_pstate_driver) {
1401 mutex_unlock(&intel_pstate_driver_lock);
1402 return -EAGAIN;
1403 }
1404
1405 mutex_lock(&intel_pstate_limits_lock);
1406
1407 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1408
1409 mutex_unlock(&intel_pstate_limits_lock);
1410
1411 if (intel_pstate_driver == &intel_pstate)
1412 intel_pstate_update_policies();
1413 else
1414 update_qos_request(FREQ_QOS_MAX);
1415
1416 mutex_unlock(&intel_pstate_driver_lock);
1417
1418 return count;
1419}
1420
1421static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1422 const char *buf, size_t count)
1423{
1424 unsigned int input;
1425 int ret;
1426
1427 ret = sscanf(buf, "%u", &input);
1428 if (ret != 1)
1429 return -EINVAL;
1430
1431 mutex_lock(&intel_pstate_driver_lock);
1432
1433 if (!intel_pstate_driver) {
1434 mutex_unlock(&intel_pstate_driver_lock);
1435 return -EAGAIN;
1436 }
1437
1438 mutex_lock(&intel_pstate_limits_lock);
1439
1440 global.min_perf_pct = clamp_t(int, input,
1441 min_perf_pct_min(), global.max_perf_pct);
1442
1443 mutex_unlock(&intel_pstate_limits_lock);
1444
1445 if (intel_pstate_driver == &intel_pstate)
1446 intel_pstate_update_policies();
1447 else
1448 update_qos_request(FREQ_QOS_MIN);
1449
1450 mutex_unlock(&intel_pstate_driver_lock);
1451
1452 return count;
1453}
1454
1455static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1456 struct kobj_attribute *attr, char *buf)
1457{
1458 return sprintf(buf, "%u\n", hwp_boost);
1459}
1460
1461static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1462 struct kobj_attribute *b,
1463 const char *buf, size_t count)
1464{
1465 unsigned int input;
1466 int ret;
1467
1468 ret = kstrtouint(buf, 10, &input);
1469 if (ret)
1470 return ret;
1471
1472 mutex_lock(&intel_pstate_driver_lock);
1473 hwp_boost = !!input;
1474 intel_pstate_update_policies();
1475 mutex_unlock(&intel_pstate_driver_lock);
1476
1477 return count;
1478}
1479
1480static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1481 char *buf)
1482{
1483 u64 power_ctl;
1484 int enable;
1485
1486 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1487 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1488 return sprintf(buf, "%d\n", !enable);
1489}
1490
1491static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1492 const char *buf, size_t count)
1493{
1494 bool input;
1495 int ret;
1496
1497 ret = kstrtobool(buf, &input);
1498 if (ret)
1499 return ret;
1500
1501 set_power_ctl_ee_state(input);
1502
1503 return count;
1504}
1505
1506show_one(max_perf_pct, max_perf_pct);
1507show_one(min_perf_pct, min_perf_pct);
1508
1509define_one_global_rw(status);
1510define_one_global_rw(no_turbo);
1511define_one_global_rw(max_perf_pct);
1512define_one_global_rw(min_perf_pct);
1513define_one_global_ro(turbo_pct);
1514define_one_global_ro(num_pstates);
1515define_one_global_rw(hwp_dynamic_boost);
1516define_one_global_rw(energy_efficiency);
1517
1518static struct attribute *intel_pstate_attributes[] = {
1519 &status.attr,
1520 &no_turbo.attr,
1521 NULL
1522};
1523
1524static const struct attribute_group intel_pstate_attr_group = {
1525 .attrs = intel_pstate_attributes,
1526};
1527
1528static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1529
1530static struct kobject *intel_pstate_kobject;
1531
1532static void __init intel_pstate_sysfs_expose_params(void)
1533{
1534 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1535 int rc;
1536
1537 if (dev_root) {
1538 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1539 put_device(dev_root);
1540 }
1541 if (WARN_ON(!intel_pstate_kobject))
1542 return;
1543
1544 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1545 if (WARN_ON(rc))
1546 return;
1547
1548 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1549 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1550 WARN_ON(rc);
1551
1552 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1553 WARN_ON(rc);
1554 }
1555
1556 /*
1557 * If per cpu limits are enforced there are no global limits, so
1558 * return without creating max/min_perf_pct attributes
1559 */
1560 if (per_cpu_limits)
1561 return;
1562
1563 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1564 WARN_ON(rc);
1565
1566 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1567 WARN_ON(rc);
1568
1569 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1570 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1571 WARN_ON(rc);
1572 }
1573}
1574
1575static void __init intel_pstate_sysfs_remove(void)
1576{
1577 if (!intel_pstate_kobject)
1578 return;
1579
1580 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1581
1582 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1583 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1584 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1585 }
1586
1587 if (!per_cpu_limits) {
1588 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1589 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1590
1591 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1592 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1593 }
1594
1595 kobject_put(intel_pstate_kobject);
1596}
1597
1598static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1599{
1600 int rc;
1601
1602 if (!hwp_active)
1603 return;
1604
1605 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1606 WARN_ON_ONCE(rc);
1607}
1608
1609static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1610{
1611 if (!hwp_active)
1612 return;
1613
1614 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1615}
1616
1617/************************** sysfs end ************************/
1618
1619static void intel_pstate_notify_work(struct work_struct *work)
1620{
1621 struct cpudata *cpudata =
1622 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1623 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1624
1625 if (policy) {
1626 intel_pstate_get_hwp_cap(cpudata);
1627 __intel_pstate_update_max_freq(cpudata, policy);
1628
1629 cpufreq_cpu_release(policy);
1630 }
1631
1632 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1633}
1634
1635static DEFINE_SPINLOCK(hwp_notify_lock);
1636static cpumask_t hwp_intr_enable_mask;
1637
1638void notify_hwp_interrupt(void)
1639{
1640 unsigned int this_cpu = smp_processor_id();
1641 struct cpudata *cpudata;
1642 unsigned long flags;
1643 u64 value;
1644
1645 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1646 return;
1647
1648 rdmsrl_safe(MSR_HWP_STATUS, &value);
1649 if (!(value & 0x01))
1650 return;
1651
1652 spin_lock_irqsave(&hwp_notify_lock, flags);
1653
1654 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1655 goto ack_intr;
1656
1657 /*
1658 * Currently we never free all_cpu_data. And we can't reach here
1659 * without this allocated. But for safety for future changes, added
1660 * check.
1661 */
1662 if (unlikely(!READ_ONCE(all_cpu_data)))
1663 goto ack_intr;
1664
1665 /*
1666 * The free is done during cleanup, when cpufreq registry is failed.
1667 * We wouldn't be here if it fails on init or switch status. But for
1668 * future changes, added check.
1669 */
1670 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1671 if (unlikely(!cpudata))
1672 goto ack_intr;
1673
1674 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1675
1676 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1677
1678 return;
1679
1680ack_intr:
1681 wrmsrl_safe(MSR_HWP_STATUS, 0);
1682 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1683}
1684
1685static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1686{
1687 unsigned long flags;
1688
1689 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1690 return;
1691
1692 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1693 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1694
1695 spin_lock_irqsave(&hwp_notify_lock, flags);
1696 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1697 cancel_delayed_work(&cpudata->hwp_notify_work);
1698 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1699}
1700
1701static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1702{
1703 /* Enable HWP notification interrupt for guaranteed performance change */
1704 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1705 unsigned long flags;
1706
1707 spin_lock_irqsave(&hwp_notify_lock, flags);
1708 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1709 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1710 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1711
1712 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1713 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1714 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1715 }
1716}
1717
1718static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1719{
1720 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1721
1722 /*
1723 * If the EPP is set by firmware, which means that firmware enabled HWP
1724 * - Is equal or less than 0x80 (default balance_perf EPP)
1725 * - But less performance oriented than performance EPP
1726 * then use this as new balance_perf EPP.
1727 */
1728 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1729 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1730 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1731 return;
1732 }
1733
1734 /*
1735 * If this CPU gen doesn't call for change in balance_perf
1736 * EPP return.
1737 */
1738 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1739 return;
1740
1741 /*
1742 * Use hard coded value per gen to update the balance_perf
1743 * and default EPP.
1744 */
1745 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1746 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1747}
1748
1749static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1750{
1751 /* First disable HWP notification interrupt till we activate again */
1752 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1753 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1754
1755 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1756
1757 intel_pstate_enable_hwp_interrupt(cpudata);
1758
1759 if (cpudata->epp_default >= 0)
1760 return;
1761
1762 intel_pstate_update_epp_defaults(cpudata);
1763}
1764
1765static int atom_get_min_pstate(int not_used)
1766{
1767 u64 value;
1768
1769 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1770 return (value >> 8) & 0x7F;
1771}
1772
1773static int atom_get_max_pstate(int not_used)
1774{
1775 u64 value;
1776
1777 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1778 return (value >> 16) & 0x7F;
1779}
1780
1781static int atom_get_turbo_pstate(int not_used)
1782{
1783 u64 value;
1784
1785 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1786 return value & 0x7F;
1787}
1788
1789static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1790{
1791 u64 val;
1792 int32_t vid_fp;
1793 u32 vid;
1794
1795 val = (u64)pstate << 8;
1796 if (global.no_turbo && !global.turbo_disabled)
1797 val |= (u64)1 << 32;
1798
1799 vid_fp = cpudata->vid.min + mul_fp(
1800 int_tofp(pstate - cpudata->pstate.min_pstate),
1801 cpudata->vid.ratio);
1802
1803 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1804 vid = ceiling_fp(vid_fp);
1805
1806 if (pstate > cpudata->pstate.max_pstate)
1807 vid = cpudata->vid.turbo;
1808
1809 return val | vid;
1810}
1811
1812static int silvermont_get_scaling(void)
1813{
1814 u64 value;
1815 int i;
1816 /* Defined in Table 35-6 from SDM (Sept 2015) */
1817 static int silvermont_freq_table[] = {
1818 83300, 100000, 133300, 116700, 80000};
1819
1820 rdmsrl(MSR_FSB_FREQ, value);
1821 i = value & 0x7;
1822 WARN_ON(i > 4);
1823
1824 return silvermont_freq_table[i];
1825}
1826
1827static int airmont_get_scaling(void)
1828{
1829 u64 value;
1830 int i;
1831 /* Defined in Table 35-10 from SDM (Sept 2015) */
1832 static int airmont_freq_table[] = {
1833 83300, 100000, 133300, 116700, 80000,
1834 93300, 90000, 88900, 87500};
1835
1836 rdmsrl(MSR_FSB_FREQ, value);
1837 i = value & 0xF;
1838 WARN_ON(i > 8);
1839
1840 return airmont_freq_table[i];
1841}
1842
1843static void atom_get_vid(struct cpudata *cpudata)
1844{
1845 u64 value;
1846
1847 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1848 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1849 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1850 cpudata->vid.ratio = div_fp(
1851 cpudata->vid.max - cpudata->vid.min,
1852 int_tofp(cpudata->pstate.max_pstate -
1853 cpudata->pstate.min_pstate));
1854
1855 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1856 cpudata->vid.turbo = value & 0x7f;
1857}
1858
1859static int core_get_min_pstate(int cpu)
1860{
1861 u64 value;
1862
1863 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1864 return (value >> 40) & 0xFF;
1865}
1866
1867static int core_get_max_pstate_physical(int cpu)
1868{
1869 u64 value;
1870
1871 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1872 return (value >> 8) & 0xFF;
1873}
1874
1875static int core_get_tdp_ratio(int cpu, u64 plat_info)
1876{
1877 /* Check how many TDP levels present */
1878 if (plat_info & 0x600000000) {
1879 u64 tdp_ctrl;
1880 u64 tdp_ratio;
1881 int tdp_msr;
1882 int err;
1883
1884 /* Get the TDP level (0, 1, 2) to get ratios */
1885 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1886 if (err)
1887 return err;
1888
1889 /* TDP MSR are continuous starting at 0x648 */
1890 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1891 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1892 if (err)
1893 return err;
1894
1895 /* For level 1 and 2, bits[23:16] contain the ratio */
1896 if (tdp_ctrl & 0x03)
1897 tdp_ratio >>= 16;
1898
1899 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1900 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1901
1902 return (int)tdp_ratio;
1903 }
1904
1905 return -ENXIO;
1906}
1907
1908static int core_get_max_pstate(int cpu)
1909{
1910 u64 tar;
1911 u64 plat_info;
1912 int max_pstate;
1913 int tdp_ratio;
1914 int err;
1915
1916 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1917 max_pstate = (plat_info >> 8) & 0xFF;
1918
1919 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1920 if (tdp_ratio <= 0)
1921 return max_pstate;
1922
1923 if (hwp_active) {
1924 /* Turbo activation ratio is not used on HWP platforms */
1925 return tdp_ratio;
1926 }
1927
1928 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1929 if (!err) {
1930 int tar_levels;
1931
1932 /* Do some sanity checking for safety */
1933 tar_levels = tar & 0xff;
1934 if (tdp_ratio - 1 == tar_levels) {
1935 max_pstate = tar_levels;
1936 pr_debug("max_pstate=TAC %x\n", max_pstate);
1937 }
1938 }
1939
1940 return max_pstate;
1941}
1942
1943static int core_get_turbo_pstate(int cpu)
1944{
1945 u64 value;
1946 int nont, ret;
1947
1948 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1949 nont = core_get_max_pstate(cpu);
1950 ret = (value) & 255;
1951 if (ret <= nont)
1952 ret = nont;
1953 return ret;
1954}
1955
1956static u64 core_get_val(struct cpudata *cpudata, int pstate)
1957{
1958 u64 val;
1959
1960 val = (u64)pstate << 8;
1961 if (global.no_turbo && !global.turbo_disabled)
1962 val |= (u64)1 << 32;
1963
1964 return val;
1965}
1966
1967static int knl_get_aperf_mperf_shift(void)
1968{
1969 return 10;
1970}
1971
1972static int knl_get_turbo_pstate(int cpu)
1973{
1974 u64 value;
1975 int nont, ret;
1976
1977 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1978 nont = core_get_max_pstate(cpu);
1979 ret = (((value) >> 8) & 0xFF);
1980 if (ret <= nont)
1981 ret = nont;
1982 return ret;
1983}
1984
1985static void hybrid_get_type(void *data)
1986{
1987 u8 *cpu_type = data;
1988
1989 *cpu_type = get_this_hybrid_cpu_type();
1990}
1991
1992static int hwp_get_cpu_scaling(int cpu)
1993{
1994 u8 cpu_type = 0;
1995
1996 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1997 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1998 if (cpu_type == 0x40)
1999 return hybrid_scaling_factor;
2000
2001 /* Use default core scaling for E-cores */
2002 if (cpu_type == 0x20)
2003 return core_get_scaling();
2004
2005 /*
2006 * If reached here, this system is either non-hybrid (like Tiger
2007 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2008 * no E cores (in which case CPUID for hybrid support is 0).
2009 *
2010 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2011 * so the default core scaling will be used for them.
2012 */
2013 return intel_pstate_cppc_get_scaling(cpu);
2014}
2015
2016static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2017{
2018 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2019 cpu->pstate.current_pstate = pstate;
2020 /*
2021 * Generally, there is no guarantee that this code will always run on
2022 * the CPU being updated, so force the register update to run on the
2023 * right CPU.
2024 */
2025 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2026 pstate_funcs.get_val(cpu, pstate));
2027}
2028
2029static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2030{
2031 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2032}
2033
2034static void intel_pstate_max_within_limits(struct cpudata *cpu)
2035{
2036 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2037
2038 update_turbo_state();
2039 intel_pstate_set_pstate(cpu, pstate);
2040}
2041
2042static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2043{
2044 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2045 int perf_ctl_scaling = pstate_funcs.get_scaling();
2046
2047 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2048 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2049 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2050
2051 if (hwp_active && !hwp_mode_bdw) {
2052 __intel_pstate_get_hwp_cap(cpu);
2053
2054 if (pstate_funcs.get_cpu_scaling) {
2055 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2056 if (cpu->pstate.scaling != perf_ctl_scaling)
2057 intel_pstate_hybrid_hwp_adjust(cpu);
2058 } else {
2059 cpu->pstate.scaling = perf_ctl_scaling;
2060 }
2061 } else {
2062 cpu->pstate.scaling = perf_ctl_scaling;
2063 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2064 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2065 }
2066
2067 if (cpu->pstate.scaling == perf_ctl_scaling) {
2068 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2069 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2070 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2071 }
2072
2073 if (pstate_funcs.get_aperf_mperf_shift)
2074 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2075
2076 if (pstate_funcs.get_vid)
2077 pstate_funcs.get_vid(cpu);
2078
2079 intel_pstate_set_min_pstate(cpu);
2080}
2081
2082/*
2083 * Long hold time will keep high perf limits for long time,
2084 * which negatively impacts perf/watt for some workloads,
2085 * like specpower. 3ms is based on experiements on some
2086 * workoads.
2087 */
2088static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2089
2090static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2091{
2092 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2093 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2094 u32 max_limit = (hwp_req & 0xff00) >> 8;
2095 u32 min_limit = (hwp_req & 0xff);
2096 u32 boost_level1;
2097
2098 /*
2099 * Cases to consider (User changes via sysfs or boot time):
2100 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2101 * No boost, return.
2102 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2103 * Should result in one level boost only for P0.
2104 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2105 * Should result in two level boost:
2106 * (min + p1)/2 and P1.
2107 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2108 * Should result in three level boost:
2109 * (min + p1)/2, P1 and P0.
2110 */
2111
2112 /* If max and min are equal or already at max, nothing to boost */
2113 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2114 return;
2115
2116 if (!cpu->hwp_boost_min)
2117 cpu->hwp_boost_min = min_limit;
2118
2119 /* level at half way mark between min and guranteed */
2120 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2121
2122 if (cpu->hwp_boost_min < boost_level1)
2123 cpu->hwp_boost_min = boost_level1;
2124 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2125 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2126 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2127 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2128 cpu->hwp_boost_min = max_limit;
2129 else
2130 return;
2131
2132 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2133 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2134 cpu->last_update = cpu->sample.time;
2135}
2136
2137static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2138{
2139 if (cpu->hwp_boost_min) {
2140 bool expired;
2141
2142 /* Check if we are idle for hold time to boost down */
2143 expired = time_after64(cpu->sample.time, cpu->last_update +
2144 hwp_boost_hold_time_ns);
2145 if (expired) {
2146 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2147 cpu->hwp_boost_min = 0;
2148 }
2149 }
2150 cpu->last_update = cpu->sample.time;
2151}
2152
2153static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2154 u64 time)
2155{
2156 cpu->sample.time = time;
2157
2158 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2159 bool do_io = false;
2160
2161 cpu->sched_flags = 0;
2162 /*
2163 * Set iowait_boost flag and update time. Since IO WAIT flag
2164 * is set all the time, we can't just conclude that there is
2165 * some IO bound activity is scheduled on this CPU with just
2166 * one occurrence. If we receive at least two in two
2167 * consecutive ticks, then we treat as boost candidate.
2168 */
2169 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2170 do_io = true;
2171
2172 cpu->last_io_update = time;
2173
2174 if (do_io)
2175 intel_pstate_hwp_boost_up(cpu);
2176
2177 } else {
2178 intel_pstate_hwp_boost_down(cpu);
2179 }
2180}
2181
2182static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2183 u64 time, unsigned int flags)
2184{
2185 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2186
2187 cpu->sched_flags |= flags;
2188
2189 if (smp_processor_id() == cpu->cpu)
2190 intel_pstate_update_util_hwp_local(cpu, time);
2191}
2192
2193static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2194{
2195 struct sample *sample = &cpu->sample;
2196
2197 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2198}
2199
2200static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2201{
2202 u64 aperf, mperf;
2203 unsigned long flags;
2204 u64 tsc;
2205
2206 local_irq_save(flags);
2207 rdmsrl(MSR_IA32_APERF, aperf);
2208 rdmsrl(MSR_IA32_MPERF, mperf);
2209 tsc = rdtsc();
2210 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2211 local_irq_restore(flags);
2212 return false;
2213 }
2214 local_irq_restore(flags);
2215
2216 cpu->last_sample_time = cpu->sample.time;
2217 cpu->sample.time = time;
2218 cpu->sample.aperf = aperf;
2219 cpu->sample.mperf = mperf;
2220 cpu->sample.tsc = tsc;
2221 cpu->sample.aperf -= cpu->prev_aperf;
2222 cpu->sample.mperf -= cpu->prev_mperf;
2223 cpu->sample.tsc -= cpu->prev_tsc;
2224
2225 cpu->prev_aperf = aperf;
2226 cpu->prev_mperf = mperf;
2227 cpu->prev_tsc = tsc;
2228 /*
2229 * First time this function is invoked in a given cycle, all of the
2230 * previous sample data fields are equal to zero or stale and they must
2231 * be populated with meaningful numbers for things to work, so assume
2232 * that sample.time will always be reset before setting the utilization
2233 * update hook and make the caller skip the sample then.
2234 */
2235 if (cpu->last_sample_time) {
2236 intel_pstate_calc_avg_perf(cpu);
2237 return true;
2238 }
2239 return false;
2240}
2241
2242static inline int32_t get_avg_frequency(struct cpudata *cpu)
2243{
2244 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2245}
2246
2247static inline int32_t get_avg_pstate(struct cpudata *cpu)
2248{
2249 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2250 cpu->sample.core_avg_perf);
2251}
2252
2253static inline int32_t get_target_pstate(struct cpudata *cpu)
2254{
2255 struct sample *sample = &cpu->sample;
2256 int32_t busy_frac;
2257 int target, avg_pstate;
2258
2259 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2260 sample->tsc);
2261
2262 if (busy_frac < cpu->iowait_boost)
2263 busy_frac = cpu->iowait_boost;
2264
2265 sample->busy_scaled = busy_frac * 100;
2266
2267 target = global.no_turbo || global.turbo_disabled ?
2268 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2269 target += target >> 2;
2270 target = mul_fp(target, busy_frac);
2271 if (target < cpu->pstate.min_pstate)
2272 target = cpu->pstate.min_pstate;
2273
2274 /*
2275 * If the average P-state during the previous cycle was higher than the
2276 * current target, add 50% of the difference to the target to reduce
2277 * possible performance oscillations and offset possible performance
2278 * loss related to moving the workload from one CPU to another within
2279 * a package/module.
2280 */
2281 avg_pstate = get_avg_pstate(cpu);
2282 if (avg_pstate > target)
2283 target += (avg_pstate - target) >> 1;
2284
2285 return target;
2286}
2287
2288static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2289{
2290 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2291 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2292
2293 return clamp_t(int, pstate, min_pstate, max_pstate);
2294}
2295
2296static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2297{
2298 if (pstate == cpu->pstate.current_pstate)
2299 return;
2300
2301 cpu->pstate.current_pstate = pstate;
2302 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2303}
2304
2305static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2306{
2307 int from = cpu->pstate.current_pstate;
2308 struct sample *sample;
2309 int target_pstate;
2310
2311 update_turbo_state();
2312
2313 target_pstate = get_target_pstate(cpu);
2314 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2315 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2316 intel_pstate_update_pstate(cpu, target_pstate);
2317
2318 sample = &cpu->sample;
2319 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2320 fp_toint(sample->busy_scaled),
2321 from,
2322 cpu->pstate.current_pstate,
2323 sample->mperf,
2324 sample->aperf,
2325 sample->tsc,
2326 get_avg_frequency(cpu),
2327 fp_toint(cpu->iowait_boost * 100));
2328}
2329
2330static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2331 unsigned int flags)
2332{
2333 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2334 u64 delta_ns;
2335
2336 /* Don't allow remote callbacks */
2337 if (smp_processor_id() != cpu->cpu)
2338 return;
2339
2340 delta_ns = time - cpu->last_update;
2341 if (flags & SCHED_CPUFREQ_IOWAIT) {
2342 /* Start over if the CPU may have been idle. */
2343 if (delta_ns > TICK_NSEC) {
2344 cpu->iowait_boost = ONE_EIGHTH_FP;
2345 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2346 cpu->iowait_boost <<= 1;
2347 if (cpu->iowait_boost > int_tofp(1))
2348 cpu->iowait_boost = int_tofp(1);
2349 } else {
2350 cpu->iowait_boost = ONE_EIGHTH_FP;
2351 }
2352 } else if (cpu->iowait_boost) {
2353 /* Clear iowait_boost if the CPU may have been idle. */
2354 if (delta_ns > TICK_NSEC)
2355 cpu->iowait_boost = 0;
2356 else
2357 cpu->iowait_boost >>= 1;
2358 }
2359 cpu->last_update = time;
2360 delta_ns = time - cpu->sample.time;
2361 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2362 return;
2363
2364 if (intel_pstate_sample(cpu, time))
2365 intel_pstate_adjust_pstate(cpu);
2366}
2367
2368static struct pstate_funcs core_funcs = {
2369 .get_max = core_get_max_pstate,
2370 .get_max_physical = core_get_max_pstate_physical,
2371 .get_min = core_get_min_pstate,
2372 .get_turbo = core_get_turbo_pstate,
2373 .get_scaling = core_get_scaling,
2374 .get_val = core_get_val,
2375};
2376
2377static const struct pstate_funcs silvermont_funcs = {
2378 .get_max = atom_get_max_pstate,
2379 .get_max_physical = atom_get_max_pstate,
2380 .get_min = atom_get_min_pstate,
2381 .get_turbo = atom_get_turbo_pstate,
2382 .get_val = atom_get_val,
2383 .get_scaling = silvermont_get_scaling,
2384 .get_vid = atom_get_vid,
2385};
2386
2387static const struct pstate_funcs airmont_funcs = {
2388 .get_max = atom_get_max_pstate,
2389 .get_max_physical = atom_get_max_pstate,
2390 .get_min = atom_get_min_pstate,
2391 .get_turbo = atom_get_turbo_pstate,
2392 .get_val = atom_get_val,
2393 .get_scaling = airmont_get_scaling,
2394 .get_vid = atom_get_vid,
2395};
2396
2397static const struct pstate_funcs knl_funcs = {
2398 .get_max = core_get_max_pstate,
2399 .get_max_physical = core_get_max_pstate_physical,
2400 .get_min = core_get_min_pstate,
2401 .get_turbo = knl_get_turbo_pstate,
2402 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2403 .get_scaling = core_get_scaling,
2404 .get_val = core_get_val,
2405};
2406
2407#define X86_MATCH(model, policy) \
2408 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2409 X86_FEATURE_APERFMPERF, &policy)
2410
2411static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2412 X86_MATCH(SANDYBRIDGE, core_funcs),
2413 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2414 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2415 X86_MATCH(IVYBRIDGE, core_funcs),
2416 X86_MATCH(HASWELL, core_funcs),
2417 X86_MATCH(BROADWELL, core_funcs),
2418 X86_MATCH(IVYBRIDGE_X, core_funcs),
2419 X86_MATCH(HASWELL_X, core_funcs),
2420 X86_MATCH(HASWELL_L, core_funcs),
2421 X86_MATCH(HASWELL_G, core_funcs),
2422 X86_MATCH(BROADWELL_G, core_funcs),
2423 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2424 X86_MATCH(SKYLAKE_L, core_funcs),
2425 X86_MATCH(BROADWELL_X, core_funcs),
2426 X86_MATCH(SKYLAKE, core_funcs),
2427 X86_MATCH(BROADWELL_D, core_funcs),
2428 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2429 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2430 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2431 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2432 X86_MATCH(SKYLAKE_X, core_funcs),
2433 X86_MATCH(COMETLAKE, core_funcs),
2434 X86_MATCH(ICELAKE_X, core_funcs),
2435 X86_MATCH(TIGERLAKE, core_funcs),
2436 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2437 X86_MATCH(EMERALDRAPIDS_X, core_funcs),
2438 {}
2439};
2440MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2441
2442static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2443 X86_MATCH(BROADWELL_D, core_funcs),
2444 X86_MATCH(BROADWELL_X, core_funcs),
2445 X86_MATCH(SKYLAKE_X, core_funcs),
2446 X86_MATCH(ICELAKE_X, core_funcs),
2447 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2448 {}
2449};
2450
2451static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2452 X86_MATCH(KABYLAKE, core_funcs),
2453 {}
2454};
2455
2456static int intel_pstate_init_cpu(unsigned int cpunum)
2457{
2458 struct cpudata *cpu;
2459
2460 cpu = all_cpu_data[cpunum];
2461
2462 if (!cpu) {
2463 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2464 if (!cpu)
2465 return -ENOMEM;
2466
2467 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2468
2469 cpu->cpu = cpunum;
2470
2471 cpu->epp_default = -EINVAL;
2472
2473 if (hwp_active) {
2474 intel_pstate_hwp_enable(cpu);
2475
2476 if (intel_pstate_acpi_pm_profile_server())
2477 hwp_boost = true;
2478 }
2479 } else if (hwp_active) {
2480 /*
2481 * Re-enable HWP in case this happens after a resume from ACPI
2482 * S3 if the CPU was offline during the whole system/resume
2483 * cycle.
2484 */
2485 intel_pstate_hwp_reenable(cpu);
2486 }
2487
2488 cpu->epp_powersave = -EINVAL;
2489 cpu->epp_policy = 0;
2490
2491 intel_pstate_get_cpu_pstates(cpu);
2492
2493 pr_debug("controlling: cpu %d\n", cpunum);
2494
2495 return 0;
2496}
2497
2498static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2499{
2500 struct cpudata *cpu = all_cpu_data[cpu_num];
2501
2502 if (hwp_active && !hwp_boost)
2503 return;
2504
2505 if (cpu->update_util_set)
2506 return;
2507
2508 /* Prevent intel_pstate_update_util() from using stale data. */
2509 cpu->sample.time = 0;
2510 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2511 (hwp_active ?
2512 intel_pstate_update_util_hwp :
2513 intel_pstate_update_util));
2514 cpu->update_util_set = true;
2515}
2516
2517static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2518{
2519 struct cpudata *cpu_data = all_cpu_data[cpu];
2520
2521 if (!cpu_data->update_util_set)
2522 return;
2523
2524 cpufreq_remove_update_util_hook(cpu);
2525 cpu_data->update_util_set = false;
2526 synchronize_rcu();
2527}
2528
2529static int intel_pstate_get_max_freq(struct cpudata *cpu)
2530{
2531 return global.turbo_disabled || global.no_turbo ?
2532 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2533}
2534
2535static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2536 unsigned int policy_min,
2537 unsigned int policy_max)
2538{
2539 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2540 int32_t max_policy_perf, min_policy_perf;
2541
2542 max_policy_perf = policy_max / perf_ctl_scaling;
2543 if (policy_max == policy_min) {
2544 min_policy_perf = max_policy_perf;
2545 } else {
2546 min_policy_perf = policy_min / perf_ctl_scaling;
2547 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2548 0, max_policy_perf);
2549 }
2550
2551 /*
2552 * HWP needs some special consideration, because HWP_REQUEST uses
2553 * abstract values to represent performance rather than pure ratios.
2554 */
2555 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2556 int freq;
2557
2558 freq = max_policy_perf * perf_ctl_scaling;
2559 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2560 freq = min_policy_perf * perf_ctl_scaling;
2561 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2562 }
2563
2564 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2565 cpu->cpu, min_policy_perf, max_policy_perf);
2566
2567 /* Normalize user input to [min_perf, max_perf] */
2568 if (per_cpu_limits) {
2569 cpu->min_perf_ratio = min_policy_perf;
2570 cpu->max_perf_ratio = max_policy_perf;
2571 } else {
2572 int turbo_max = cpu->pstate.turbo_pstate;
2573 int32_t global_min, global_max;
2574
2575 /* Global limits are in percent of the maximum turbo P-state. */
2576 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2577 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2578 global_min = clamp_t(int32_t, global_min, 0, global_max);
2579
2580 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2581 global_min, global_max);
2582
2583 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2584 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2585 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2586 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2587
2588 /* Make sure min_perf <= max_perf */
2589 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2590 cpu->max_perf_ratio);
2591
2592 }
2593 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2594 cpu->max_perf_ratio,
2595 cpu->min_perf_ratio);
2596}
2597
2598static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2599{
2600 struct cpudata *cpu;
2601
2602 if (!policy->cpuinfo.max_freq)
2603 return -ENODEV;
2604
2605 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2606 policy->cpuinfo.max_freq, policy->max);
2607
2608 cpu = all_cpu_data[policy->cpu];
2609 cpu->policy = policy->policy;
2610
2611 mutex_lock(&intel_pstate_limits_lock);
2612
2613 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2614
2615 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2616 /*
2617 * NOHZ_FULL CPUs need this as the governor callback may not
2618 * be invoked on them.
2619 */
2620 intel_pstate_clear_update_util_hook(policy->cpu);
2621 intel_pstate_max_within_limits(cpu);
2622 } else {
2623 intel_pstate_set_update_util_hook(policy->cpu);
2624 }
2625
2626 if (hwp_active) {
2627 /*
2628 * When hwp_boost was active before and dynamically it
2629 * was turned off, in that case we need to clear the
2630 * update util hook.
2631 */
2632 if (!hwp_boost)
2633 intel_pstate_clear_update_util_hook(policy->cpu);
2634 intel_pstate_hwp_set(policy->cpu);
2635 }
2636 /*
2637 * policy->cur is never updated with the intel_pstate driver, but it
2638 * is used as a stale frequency value. So, keep it within limits.
2639 */
2640 policy->cur = policy->min;
2641
2642 mutex_unlock(&intel_pstate_limits_lock);
2643
2644 return 0;
2645}
2646
2647static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2648 struct cpufreq_policy_data *policy)
2649{
2650 if (!hwp_active &&
2651 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2652 policy->max < policy->cpuinfo.max_freq &&
2653 policy->max > cpu->pstate.max_freq) {
2654 pr_debug("policy->max > max non turbo frequency\n");
2655 policy->max = policy->cpuinfo.max_freq;
2656 }
2657}
2658
2659static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2660 struct cpufreq_policy_data *policy)
2661{
2662 int max_freq;
2663
2664 update_turbo_state();
2665 if (hwp_active) {
2666 intel_pstate_get_hwp_cap(cpu);
2667 max_freq = global.no_turbo || global.turbo_disabled ?
2668 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2669 } else {
2670 max_freq = intel_pstate_get_max_freq(cpu);
2671 }
2672 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2673
2674 intel_pstate_adjust_policy_max(cpu, policy);
2675}
2676
2677static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2678{
2679 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2680
2681 return 0;
2682}
2683
2684static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2685{
2686 struct cpudata *cpu = all_cpu_data[policy->cpu];
2687
2688 pr_debug("CPU %d going offline\n", cpu->cpu);
2689
2690 if (cpu->suspended)
2691 return 0;
2692
2693 /*
2694 * If the CPU is an SMT thread and it goes offline with the performance
2695 * settings different from the minimum, it will prevent its sibling
2696 * from getting to lower performance levels, so force the minimum
2697 * performance on CPU offline to prevent that from happening.
2698 */
2699 if (hwp_active)
2700 intel_pstate_hwp_offline(cpu);
2701 else
2702 intel_pstate_set_min_pstate(cpu);
2703
2704 intel_pstate_exit_perf_limits(policy);
2705
2706 return 0;
2707}
2708
2709static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2710{
2711 struct cpudata *cpu = all_cpu_data[policy->cpu];
2712
2713 pr_debug("CPU %d going online\n", cpu->cpu);
2714
2715 intel_pstate_init_acpi_perf_limits(policy);
2716
2717 if (hwp_active) {
2718 /*
2719 * Re-enable HWP and clear the "suspended" flag to let "resume"
2720 * know that it need not do that.
2721 */
2722 intel_pstate_hwp_reenable(cpu);
2723 cpu->suspended = false;
2724 }
2725
2726 return 0;
2727}
2728
2729static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2730{
2731 intel_pstate_clear_update_util_hook(policy->cpu);
2732
2733 return intel_cpufreq_cpu_offline(policy);
2734}
2735
2736static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2737{
2738 pr_debug("CPU %d exiting\n", policy->cpu);
2739
2740 policy->fast_switch_possible = false;
2741
2742 return 0;
2743}
2744
2745static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2746{
2747 struct cpudata *cpu;
2748 int rc;
2749
2750 rc = intel_pstate_init_cpu(policy->cpu);
2751 if (rc)
2752 return rc;
2753
2754 cpu = all_cpu_data[policy->cpu];
2755
2756 cpu->max_perf_ratio = 0xFF;
2757 cpu->min_perf_ratio = 0;
2758
2759 /* cpuinfo and default policy values */
2760 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2761 update_turbo_state();
2762 global.turbo_disabled_mf = global.turbo_disabled;
2763 policy->cpuinfo.max_freq = global.turbo_disabled ?
2764 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2765
2766 policy->min = policy->cpuinfo.min_freq;
2767 policy->max = policy->cpuinfo.max_freq;
2768
2769 intel_pstate_init_acpi_perf_limits(policy);
2770
2771 policy->fast_switch_possible = true;
2772
2773 return 0;
2774}
2775
2776static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2777{
2778 int ret = __intel_pstate_cpu_init(policy);
2779
2780 if (ret)
2781 return ret;
2782
2783 /*
2784 * Set the policy to powersave to provide a valid fallback value in case
2785 * the default cpufreq governor is neither powersave nor performance.
2786 */
2787 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2788
2789 if (hwp_active) {
2790 struct cpudata *cpu = all_cpu_data[policy->cpu];
2791
2792 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2793 }
2794
2795 return 0;
2796}
2797
2798static struct cpufreq_driver intel_pstate = {
2799 .flags = CPUFREQ_CONST_LOOPS,
2800 .verify = intel_pstate_verify_policy,
2801 .setpolicy = intel_pstate_set_policy,
2802 .suspend = intel_pstate_suspend,
2803 .resume = intel_pstate_resume,
2804 .init = intel_pstate_cpu_init,
2805 .exit = intel_pstate_cpu_exit,
2806 .offline = intel_pstate_cpu_offline,
2807 .online = intel_pstate_cpu_online,
2808 .update_limits = intel_pstate_update_limits,
2809 .name = "intel_pstate",
2810};
2811
2812static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2813{
2814 struct cpudata *cpu = all_cpu_data[policy->cpu];
2815
2816 intel_pstate_verify_cpu_policy(cpu, policy);
2817 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2818
2819 return 0;
2820}
2821
2822/* Use of trace in passive mode:
2823 *
2824 * In passive mode the trace core_busy field (also known as the
2825 * performance field, and lablelled as such on the graphs; also known as
2826 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2827 * driver call was via the normal or fast switch path. Various graphs
2828 * output from the intel_pstate_tracer.py utility that include core_busy
2829 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2830 * so we use 10 to indicate the normal path through the driver, and
2831 * 90 to indicate the fast switch path through the driver.
2832 * The scaled_busy field is not used, and is set to 0.
2833 */
2834
2835#define INTEL_PSTATE_TRACE_TARGET 10
2836#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2837
2838static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2839{
2840 struct sample *sample;
2841
2842 if (!trace_pstate_sample_enabled())
2843 return;
2844
2845 if (!intel_pstate_sample(cpu, ktime_get()))
2846 return;
2847
2848 sample = &cpu->sample;
2849 trace_pstate_sample(trace_type,
2850 0,
2851 old_pstate,
2852 cpu->pstate.current_pstate,
2853 sample->mperf,
2854 sample->aperf,
2855 sample->tsc,
2856 get_avg_frequency(cpu),
2857 fp_toint(cpu->iowait_boost * 100));
2858}
2859
2860static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2861 u32 desired, bool fast_switch)
2862{
2863 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2864
2865 value &= ~HWP_MIN_PERF(~0L);
2866 value |= HWP_MIN_PERF(min);
2867
2868 value &= ~HWP_MAX_PERF(~0L);
2869 value |= HWP_MAX_PERF(max);
2870
2871 value &= ~HWP_DESIRED_PERF(~0L);
2872 value |= HWP_DESIRED_PERF(desired);
2873
2874 if (value == prev)
2875 return;
2876
2877 WRITE_ONCE(cpu->hwp_req_cached, value);
2878 if (fast_switch)
2879 wrmsrl(MSR_HWP_REQUEST, value);
2880 else
2881 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2882}
2883
2884static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2885 u32 target_pstate, bool fast_switch)
2886{
2887 if (fast_switch)
2888 wrmsrl(MSR_IA32_PERF_CTL,
2889 pstate_funcs.get_val(cpu, target_pstate));
2890 else
2891 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2892 pstate_funcs.get_val(cpu, target_pstate));
2893}
2894
2895static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2896 int target_pstate, bool fast_switch)
2897{
2898 struct cpudata *cpu = all_cpu_data[policy->cpu];
2899 int old_pstate = cpu->pstate.current_pstate;
2900
2901 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2902 if (hwp_active) {
2903 int max_pstate = policy->strict_target ?
2904 target_pstate : cpu->max_perf_ratio;
2905
2906 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2907 fast_switch);
2908 } else if (target_pstate != old_pstate) {
2909 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2910 }
2911
2912 cpu->pstate.current_pstate = target_pstate;
2913
2914 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2915 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2916
2917 return target_pstate;
2918}
2919
2920static int intel_cpufreq_target(struct cpufreq_policy *policy,
2921 unsigned int target_freq,
2922 unsigned int relation)
2923{
2924 struct cpudata *cpu = all_cpu_data[policy->cpu];
2925 struct cpufreq_freqs freqs;
2926 int target_pstate;
2927
2928 update_turbo_state();
2929
2930 freqs.old = policy->cur;
2931 freqs.new = target_freq;
2932
2933 cpufreq_freq_transition_begin(policy, &freqs);
2934
2935 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2936 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2937
2938 freqs.new = target_pstate * cpu->pstate.scaling;
2939
2940 cpufreq_freq_transition_end(policy, &freqs, false);
2941
2942 return 0;
2943}
2944
2945static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2946 unsigned int target_freq)
2947{
2948 struct cpudata *cpu = all_cpu_data[policy->cpu];
2949 int target_pstate;
2950
2951 update_turbo_state();
2952
2953 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2954
2955 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2956
2957 return target_pstate * cpu->pstate.scaling;
2958}
2959
2960static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2961 unsigned long min_perf,
2962 unsigned long target_perf,
2963 unsigned long capacity)
2964{
2965 struct cpudata *cpu = all_cpu_data[cpunum];
2966 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2967 int old_pstate = cpu->pstate.current_pstate;
2968 int cap_pstate, min_pstate, max_pstate, target_pstate;
2969
2970 update_turbo_state();
2971 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2972 HWP_HIGHEST_PERF(hwp_cap);
2973
2974 /* Optimization: Avoid unnecessary divisions. */
2975
2976 target_pstate = cap_pstate;
2977 if (target_perf < capacity)
2978 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2979
2980 min_pstate = cap_pstate;
2981 if (min_perf < capacity)
2982 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2983
2984 if (min_pstate < cpu->pstate.min_pstate)
2985 min_pstate = cpu->pstate.min_pstate;
2986
2987 if (min_pstate < cpu->min_perf_ratio)
2988 min_pstate = cpu->min_perf_ratio;
2989
2990 if (min_pstate > cpu->max_perf_ratio)
2991 min_pstate = cpu->max_perf_ratio;
2992
2993 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2994 if (max_pstate < min_pstate)
2995 max_pstate = min_pstate;
2996
2997 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2998
2999 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
3000
3001 cpu->pstate.current_pstate = target_pstate;
3002 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3003}
3004
3005static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3006{
3007 struct freq_qos_request *req;
3008 struct cpudata *cpu;
3009 struct device *dev;
3010 int ret, freq;
3011
3012 dev = get_cpu_device(policy->cpu);
3013 if (!dev)
3014 return -ENODEV;
3015
3016 ret = __intel_pstate_cpu_init(policy);
3017 if (ret)
3018 return ret;
3019
3020 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3021 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3022 policy->cur = policy->cpuinfo.min_freq;
3023
3024 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3025 if (!req) {
3026 ret = -ENOMEM;
3027 goto pstate_exit;
3028 }
3029
3030 cpu = all_cpu_data[policy->cpu];
3031
3032 if (hwp_active) {
3033 u64 value;
3034
3035 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3036
3037 intel_pstate_get_hwp_cap(cpu);
3038
3039 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3040 WRITE_ONCE(cpu->hwp_req_cached, value);
3041
3042 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3043 } else {
3044 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3045 }
3046
3047 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3048
3049 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3050 freq);
3051 if (ret < 0) {
3052 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3053 goto free_req;
3054 }
3055
3056 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3057
3058 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3059 freq);
3060 if (ret < 0) {
3061 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3062 goto remove_min_req;
3063 }
3064
3065 policy->driver_data = req;
3066
3067 return 0;
3068
3069remove_min_req:
3070 freq_qos_remove_request(req);
3071free_req:
3072 kfree(req);
3073pstate_exit:
3074 intel_pstate_exit_perf_limits(policy);
3075
3076 return ret;
3077}
3078
3079static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3080{
3081 struct freq_qos_request *req;
3082
3083 req = policy->driver_data;
3084
3085 freq_qos_remove_request(req + 1);
3086 freq_qos_remove_request(req);
3087 kfree(req);
3088
3089 return intel_pstate_cpu_exit(policy);
3090}
3091
3092static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3093{
3094 intel_pstate_suspend(policy);
3095
3096 if (hwp_active) {
3097 struct cpudata *cpu = all_cpu_data[policy->cpu];
3098 u64 value = READ_ONCE(cpu->hwp_req_cached);
3099
3100 /*
3101 * Clear the desired perf field in MSR_HWP_REQUEST in case
3102 * intel_cpufreq_adjust_perf() is in use and the last value
3103 * written by it may not be suitable.
3104 */
3105 value &= ~HWP_DESIRED_PERF(~0L);
3106 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3107 WRITE_ONCE(cpu->hwp_req_cached, value);
3108 }
3109
3110 return 0;
3111}
3112
3113static struct cpufreq_driver intel_cpufreq = {
3114 .flags = CPUFREQ_CONST_LOOPS,
3115 .verify = intel_cpufreq_verify_policy,
3116 .target = intel_cpufreq_target,
3117 .fast_switch = intel_cpufreq_fast_switch,
3118 .init = intel_cpufreq_cpu_init,
3119 .exit = intel_cpufreq_cpu_exit,
3120 .offline = intel_cpufreq_cpu_offline,
3121 .online = intel_pstate_cpu_online,
3122 .suspend = intel_cpufreq_suspend,
3123 .resume = intel_pstate_resume,
3124 .update_limits = intel_pstate_update_limits,
3125 .name = "intel_cpufreq",
3126};
3127
3128static struct cpufreq_driver *default_driver;
3129
3130static void intel_pstate_driver_cleanup(void)
3131{
3132 unsigned int cpu;
3133
3134 cpus_read_lock();
3135 for_each_online_cpu(cpu) {
3136 if (all_cpu_data[cpu]) {
3137 if (intel_pstate_driver == &intel_pstate)
3138 intel_pstate_clear_update_util_hook(cpu);
3139
3140 spin_lock(&hwp_notify_lock);
3141 kfree(all_cpu_data[cpu]);
3142 WRITE_ONCE(all_cpu_data[cpu], NULL);
3143 spin_unlock(&hwp_notify_lock);
3144 }
3145 }
3146 cpus_read_unlock();
3147
3148 intel_pstate_driver = NULL;
3149}
3150
3151static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3152{
3153 int ret;
3154
3155 if (driver == &intel_pstate)
3156 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3157
3158 memset(&global, 0, sizeof(global));
3159 global.max_perf_pct = 100;
3160
3161 intel_pstate_driver = driver;
3162 ret = cpufreq_register_driver(intel_pstate_driver);
3163 if (ret) {
3164 intel_pstate_driver_cleanup();
3165 return ret;
3166 }
3167
3168 global.min_perf_pct = min_perf_pct_min();
3169
3170 return 0;
3171}
3172
3173static ssize_t intel_pstate_show_status(char *buf)
3174{
3175 if (!intel_pstate_driver)
3176 return sprintf(buf, "off\n");
3177
3178 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3179 "active" : "passive");
3180}
3181
3182static int intel_pstate_update_status(const char *buf, size_t size)
3183{
3184 if (size == 3 && !strncmp(buf, "off", size)) {
3185 if (!intel_pstate_driver)
3186 return -EINVAL;
3187
3188 if (hwp_active)
3189 return -EBUSY;
3190
3191 cpufreq_unregister_driver(intel_pstate_driver);
3192 intel_pstate_driver_cleanup();
3193 return 0;
3194 }
3195
3196 if (size == 6 && !strncmp(buf, "active", size)) {
3197 if (intel_pstate_driver) {
3198 if (intel_pstate_driver == &intel_pstate)
3199 return 0;
3200
3201 cpufreq_unregister_driver(intel_pstate_driver);
3202 }
3203
3204 return intel_pstate_register_driver(&intel_pstate);
3205 }
3206
3207 if (size == 7 && !strncmp(buf, "passive", size)) {
3208 if (intel_pstate_driver) {
3209 if (intel_pstate_driver == &intel_cpufreq)
3210 return 0;
3211
3212 cpufreq_unregister_driver(intel_pstate_driver);
3213 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3214 }
3215
3216 return intel_pstate_register_driver(&intel_cpufreq);
3217 }
3218
3219 return -EINVAL;
3220}
3221
3222static int no_load __initdata;
3223static int no_hwp __initdata;
3224static int hwp_only __initdata;
3225static unsigned int force_load __initdata;
3226
3227static int __init intel_pstate_msrs_not_valid(void)
3228{
3229 if (!pstate_funcs.get_max(0) ||
3230 !pstate_funcs.get_min(0) ||
3231 !pstate_funcs.get_turbo(0))
3232 return -ENODEV;
3233
3234 return 0;
3235}
3236
3237static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3238{
3239 pstate_funcs.get_max = funcs->get_max;
3240 pstate_funcs.get_max_physical = funcs->get_max_physical;
3241 pstate_funcs.get_min = funcs->get_min;
3242 pstate_funcs.get_turbo = funcs->get_turbo;
3243 pstate_funcs.get_scaling = funcs->get_scaling;
3244 pstate_funcs.get_val = funcs->get_val;
3245 pstate_funcs.get_vid = funcs->get_vid;
3246 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3247}
3248
3249#ifdef CONFIG_ACPI
3250
3251static bool __init intel_pstate_no_acpi_pss(void)
3252{
3253 int i;
3254
3255 for_each_possible_cpu(i) {
3256 acpi_status status;
3257 union acpi_object *pss;
3258 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3259 struct acpi_processor *pr = per_cpu(processors, i);
3260
3261 if (!pr)
3262 continue;
3263
3264 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3265 if (ACPI_FAILURE(status))
3266 continue;
3267
3268 pss = buffer.pointer;
3269 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3270 kfree(pss);
3271 return false;
3272 }
3273
3274 kfree(pss);
3275 }
3276
3277 pr_debug("ACPI _PSS not found\n");
3278 return true;
3279}
3280
3281static bool __init intel_pstate_no_acpi_pcch(void)
3282{
3283 acpi_status status;
3284 acpi_handle handle;
3285
3286 status = acpi_get_handle(NULL, "\\_SB", &handle);
3287 if (ACPI_FAILURE(status))
3288 goto not_found;
3289
3290 if (acpi_has_method(handle, "PCCH"))
3291 return false;
3292
3293not_found:
3294 pr_debug("ACPI PCCH not found\n");
3295 return true;
3296}
3297
3298static bool __init intel_pstate_has_acpi_ppc(void)
3299{
3300 int i;
3301
3302 for_each_possible_cpu(i) {
3303 struct acpi_processor *pr = per_cpu(processors, i);
3304
3305 if (!pr)
3306 continue;
3307 if (acpi_has_method(pr->handle, "_PPC"))
3308 return true;
3309 }
3310 pr_debug("ACPI _PPC not found\n");
3311 return false;
3312}
3313
3314enum {
3315 PSS,
3316 PPC,
3317};
3318
3319/* Hardware vendor-specific info that has its own power management modes */
3320static struct acpi_platform_list plat_info[] __initdata = {
3321 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3322 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3334 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3335 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3336 { } /* End */
3337};
3338
3339#define BITMASK_OOB (BIT(8) | BIT(18))
3340
3341static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3342{
3343 const struct x86_cpu_id *id;
3344 u64 misc_pwr;
3345 int idx;
3346
3347 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3348 if (id) {
3349 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3350 if (misc_pwr & BITMASK_OOB) {
3351 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3352 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3353 return true;
3354 }
3355 }
3356
3357 idx = acpi_match_platform_list(plat_info);
3358 if (idx < 0)
3359 return false;
3360
3361 switch (plat_info[idx].data) {
3362 case PSS:
3363 if (!intel_pstate_no_acpi_pss())
3364 return false;
3365
3366 return intel_pstate_no_acpi_pcch();
3367 case PPC:
3368 return intel_pstate_has_acpi_ppc() && !force_load;
3369 }
3370
3371 return false;
3372}
3373
3374static void intel_pstate_request_control_from_smm(void)
3375{
3376 /*
3377 * It may be unsafe to request P-states control from SMM if _PPC support
3378 * has not been enabled.
3379 */
3380 if (acpi_ppc)
3381 acpi_processor_pstate_control();
3382}
3383#else /* CONFIG_ACPI not enabled */
3384static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3385static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3386static inline void intel_pstate_request_control_from_smm(void) {}
3387#endif /* CONFIG_ACPI */
3388
3389#define INTEL_PSTATE_HWP_BROADWELL 0x01
3390
3391#define X86_MATCH_HWP(model, hwp_mode) \
3392 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3393 X86_FEATURE_HWP, hwp_mode)
3394
3395static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3396 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3397 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3398 X86_MATCH_HWP(ANY, 0),
3399 {}
3400};
3401
3402static bool intel_pstate_hwp_is_enabled(void)
3403{
3404 u64 value;
3405
3406 rdmsrl(MSR_PM_ENABLE, value);
3407 return !!(value & 0x1);
3408}
3409
3410static const struct x86_cpu_id intel_epp_balance_perf[] = {
3411 /*
3412 * Set EPP value as 102, this is the max suggested EPP
3413 * which can result in one core turbo frequency for
3414 * AlderLake Mobile CPUs.
3415 */
3416 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3417 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3418 {}
3419};
3420
3421static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3422 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3423 {}
3424};
3425
3426static int __init intel_pstate_init(void)
3427{
3428 static struct cpudata **_all_cpu_data;
3429 const struct x86_cpu_id *id;
3430 int rc;
3431
3432 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3433 return -ENODEV;
3434
3435 id = x86_match_cpu(hwp_support_ids);
3436 if (id) {
3437 hwp_forced = intel_pstate_hwp_is_enabled();
3438
3439 if (hwp_forced)
3440 pr_info("HWP enabled by BIOS\n");
3441 else if (no_load)
3442 return -ENODEV;
3443
3444 copy_cpu_funcs(&core_funcs);
3445 /*
3446 * Avoid enabling HWP for processors without EPP support,
3447 * because that means incomplete HWP implementation which is a
3448 * corner case and supporting it is generally problematic.
3449 *
3450 * If HWP is enabled already, though, there is no choice but to
3451 * deal with it.
3452 */
3453 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3454 WRITE_ONCE(hwp_active, 1);
3455 hwp_mode_bdw = id->driver_data;
3456 intel_pstate.attr = hwp_cpufreq_attrs;
3457 intel_cpufreq.attr = hwp_cpufreq_attrs;
3458 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3459 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3460 if (!default_driver)
3461 default_driver = &intel_pstate;
3462
3463 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3464
3465 goto hwp_cpu_matched;
3466 }
3467 pr_info("HWP not enabled\n");
3468 } else {
3469 if (no_load)
3470 return -ENODEV;
3471
3472 id = x86_match_cpu(intel_pstate_cpu_ids);
3473 if (!id) {
3474 pr_info("CPU model not supported\n");
3475 return -ENODEV;
3476 }
3477
3478 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3479 }
3480
3481 if (intel_pstate_msrs_not_valid()) {
3482 pr_info("Invalid MSRs\n");
3483 return -ENODEV;
3484 }
3485 /* Without HWP start in the passive mode. */
3486 if (!default_driver)
3487 default_driver = &intel_cpufreq;
3488
3489hwp_cpu_matched:
3490 /*
3491 * The Intel pstate driver will be ignored if the platform
3492 * firmware has its own power management modes.
3493 */
3494 if (intel_pstate_platform_pwr_mgmt_exists()) {
3495 pr_info("P-states controlled by the platform\n");
3496 return -ENODEV;
3497 }
3498
3499 if (!hwp_active && hwp_only)
3500 return -ENOTSUPP;
3501
3502 pr_info("Intel P-state driver initializing\n");
3503
3504 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3505 if (!_all_cpu_data)
3506 return -ENOMEM;
3507
3508 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3509
3510 intel_pstate_request_control_from_smm();
3511
3512 intel_pstate_sysfs_expose_params();
3513
3514 if (hwp_active) {
3515 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3516 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3517
3518 if (id)
3519 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3520
3521 if (hybrid_id) {
3522 hybrid_scaling_factor = hybrid_id->driver_data;
3523 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3524 }
3525
3526 }
3527
3528 mutex_lock(&intel_pstate_driver_lock);
3529 rc = intel_pstate_register_driver(default_driver);
3530 mutex_unlock(&intel_pstate_driver_lock);
3531 if (rc) {
3532 intel_pstate_sysfs_remove();
3533 return rc;
3534 }
3535
3536 if (hwp_active) {
3537 const struct x86_cpu_id *id;
3538
3539 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3540 if (id) {
3541 set_power_ctl_ee_state(false);
3542 pr_info("Disabling energy efficiency optimization\n");
3543 }
3544
3545 pr_info("HWP enabled\n");
3546 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3547 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3548 }
3549
3550 return 0;
3551}
3552device_initcall(intel_pstate_init);
3553
3554static int __init intel_pstate_setup(char *str)
3555{
3556 if (!str)
3557 return -EINVAL;
3558
3559 if (!strcmp(str, "disable"))
3560 no_load = 1;
3561 else if (!strcmp(str, "active"))
3562 default_driver = &intel_pstate;
3563 else if (!strcmp(str, "passive"))
3564 default_driver = &intel_cpufreq;
3565
3566 if (!strcmp(str, "no_hwp"))
3567 no_hwp = 1;
3568
3569 if (!strcmp(str, "force"))
3570 force_load = 1;
3571 if (!strcmp(str, "hwp_only"))
3572 hwp_only = 1;
3573 if (!strcmp(str, "per_cpu_perf_limits"))
3574 per_cpu_limits = true;
3575
3576#ifdef CONFIG_ACPI
3577 if (!strcmp(str, "support_acpi_ppc"))
3578 acpi_ppc = true;
3579#endif
3580
3581 return 0;
3582}
3583early_param("intel_pstate", intel_pstate_setup);
3584
3585MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3586MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/kernel.h>
12#include <linux/kernel_stat.h>
13#include <linux/module.h>
14#include <linux/ktime.h>
15#include <linux/hrtimer.h>
16#include <linux/tick.h>
17#include <linux/slab.h>
18#include <linux/sched/cpufreq.h>
19#include <linux/sched/smt.h>
20#include <linux/list.h>
21#include <linux/cpu.h>
22#include <linux/cpufreq.h>
23#include <linux/sysfs.h>
24#include <linux/types.h>
25#include <linux/fs.h>
26#include <linux/acpi.h>
27#include <linux/vmalloc.h>
28#include <linux/pm_qos.h>
29#include <linux/bitfield.h>
30#include <trace/events/power.h>
31
32#include <asm/cpu.h>
33#include <asm/div64.h>
34#include <asm/msr.h>
35#include <asm/cpu_device_id.h>
36#include <asm/cpufeature.h>
37#include <asm/intel-family.h>
38#include "../drivers/thermal/intel/thermal_interrupt.h"
39
40#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41
42#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43#define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
44#define INTEL_CPUFREQ_TRANSITION_DELAY 500
45
46#ifdef CONFIG_ACPI
47#include <acpi/processor.h>
48#include <acpi/cppc_acpi.h>
49#endif
50
51#define FRAC_BITS 8
52#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53#define fp_toint(X) ((X) >> FRAC_BITS)
54
55#define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
56
57#define EXT_BITS 6
58#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
59#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
60#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
61
62static inline int32_t mul_fp(int32_t x, int32_t y)
63{
64 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
65}
66
67static inline int32_t div_fp(s64 x, s64 y)
68{
69 return div64_s64((int64_t)x << FRAC_BITS, y);
70}
71
72static inline int ceiling_fp(int32_t x)
73{
74 int mask, ret;
75
76 ret = fp_toint(x);
77 mask = (1 << FRAC_BITS) - 1;
78 if (x & mask)
79 ret += 1;
80 return ret;
81}
82
83static inline u64 mul_ext_fp(u64 x, u64 y)
84{
85 return (x * y) >> EXT_FRAC_BITS;
86}
87
88static inline u64 div_ext_fp(u64 x, u64 y)
89{
90 return div64_u64(x << EXT_FRAC_BITS, y);
91}
92
93/**
94 * struct sample - Store performance sample
95 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
96 * performance during last sample period
97 * @busy_scaled: Scaled busy value which is used to calculate next
98 * P state. This can be different than core_avg_perf
99 * to account for cpu idle period
100 * @aperf: Difference of actual performance frequency clock count
101 * read from APERF MSR between last and current sample
102 * @mperf: Difference of maximum performance frequency clock count
103 * read from MPERF MSR between last and current sample
104 * @tsc: Difference of time stamp counter between last and
105 * current sample
106 * @time: Current time from scheduler
107 *
108 * This structure is used in the cpudata structure to store performance sample
109 * data for choosing next P State.
110 */
111struct sample {
112 int32_t core_avg_perf;
113 int32_t busy_scaled;
114 u64 aperf;
115 u64 mperf;
116 u64 tsc;
117 u64 time;
118};
119
120/**
121 * struct pstate_data - Store P state data
122 * @current_pstate: Current requested P state
123 * @min_pstate: Min P state possible for this platform
124 * @max_pstate: Max P state possible for this platform
125 * @max_pstate_physical:This is physical Max P state for a processor
126 * This can be higher than the max_pstate which can
127 * be limited by platform thermal design power limits
128 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
129 * @scaling: Scaling factor between performance and frequency
130 * @turbo_pstate: Max Turbo P state possible for this platform
131 * @min_freq: @min_pstate frequency in cpufreq units
132 * @max_freq: @max_pstate frequency in cpufreq units
133 * @turbo_freq: @turbo_pstate frequency in cpufreq units
134 *
135 * Stores the per cpu model P state limits and current P state.
136 */
137struct pstate_data {
138 int current_pstate;
139 int min_pstate;
140 int max_pstate;
141 int max_pstate_physical;
142 int perf_ctl_scaling;
143 int scaling;
144 int turbo_pstate;
145 unsigned int min_freq;
146 unsigned int max_freq;
147 unsigned int turbo_freq;
148};
149
150/**
151 * struct vid_data - Stores voltage information data
152 * @min: VID data for this platform corresponding to
153 * the lowest P state
154 * @max: VID data corresponding to the highest P State.
155 * @turbo: VID data for turbo P state
156 * @ratio: Ratio of (vid max - vid min) /
157 * (max P state - Min P State)
158 *
159 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
160 * This data is used in Atom platforms, where in addition to target P state,
161 * the voltage data needs to be specified to select next P State.
162 */
163struct vid_data {
164 int min;
165 int max;
166 int turbo;
167 int32_t ratio;
168};
169
170/**
171 * struct global_params - Global parameters, mostly tunable via sysfs.
172 * @no_turbo: Whether or not to use turbo P-states.
173 * @turbo_disabled: Whether or not turbo P-states are available at all,
174 * based on the MSR_IA32_MISC_ENABLE value and whether or
175 * not the maximum reported turbo P-state is different from
176 * the maximum reported non-turbo one.
177 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178 * P-state capacity.
179 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
180 * P-state capacity.
181 */
182struct global_params {
183 bool no_turbo;
184 bool turbo_disabled;
185 int max_perf_pct;
186 int min_perf_pct;
187};
188
189/**
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @sample: Storage for storing last Sample data
205 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
206 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
207 * @acpi_perf_data: Stores ACPI perf information read from _PSS
208 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
209 * @epp_powersave: Last saved HWP energy performance preference
210 * (EPP) or energy performance bias (EPB),
211 * when policy switched to performance
212 * @epp_policy: Last saved policy used to set EPP/EPB
213 * @epp_default: Power on default HWP energy performance
214 * preference/bias
215 * @epp_cached: Cached HWP energy-performance preference value
216 * @hwp_req_cached: Cached value of the last HWP Request MSR
217 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
218 * @last_io_update: Last time when IO wake flag was set
219 * @capacity_perf: Highest perf used for scale invariance
220 * @sched_flags: Store scheduler flags for possible cross CPU update
221 * @hwp_boost_min: Last HWP boosted min performance
222 * @suspended: Whether or not the driver has been suspended.
223 * @hwp_notify_work: workqueue for HWP notifications.
224 *
225 * This structure stores per CPU instance data for all CPUs.
226 */
227struct cpudata {
228 int cpu;
229
230 unsigned int policy;
231 struct update_util_data update_util;
232 bool update_util_set;
233
234 struct pstate_data pstate;
235 struct vid_data vid;
236
237 u64 last_update;
238 u64 last_sample_time;
239 u64 aperf_mperf_shift;
240 u64 prev_aperf;
241 u64 prev_mperf;
242 u64 prev_tsc;
243 struct sample sample;
244 int32_t min_perf_ratio;
245 int32_t max_perf_ratio;
246#ifdef CONFIG_ACPI
247 struct acpi_processor_performance acpi_perf_data;
248 bool valid_pss_table;
249#endif
250 unsigned int iowait_boost;
251 s16 epp_powersave;
252 s16 epp_policy;
253 s16 epp_default;
254 s16 epp_cached;
255 u64 hwp_req_cached;
256 u64 hwp_cap_cached;
257 u64 last_io_update;
258 unsigned int capacity_perf;
259 unsigned int sched_flags;
260 u32 hwp_boost_min;
261 bool suspended;
262 struct delayed_work hwp_notify_work;
263};
264
265static struct cpudata **all_cpu_data;
266
267/**
268 * struct pstate_funcs - Per CPU model specific callbacks
269 * @get_max: Callback to get maximum non turbo effective P state
270 * @get_max_physical: Callback to get maximum non turbo physical P state
271 * @get_min: Callback to get minimum P state
272 * @get_turbo: Callback to get turbo P state
273 * @get_scaling: Callback to get frequency scaling factor
274 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
275 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
276 * @get_val: Callback to convert P state to actual MSR write value
277 * @get_vid: Callback to get VID data for Atom platforms
278 *
279 * Core and Atom CPU models have different way to get P State limits. This
280 * structure is used to store those callbacks.
281 */
282struct pstate_funcs {
283 int (*get_max)(int cpu);
284 int (*get_max_physical)(int cpu);
285 int (*get_min)(int cpu);
286 int (*get_turbo)(int cpu);
287 int (*get_scaling)(void);
288 int (*get_cpu_scaling)(int cpu);
289 int (*get_aperf_mperf_shift)(void);
290 u64 (*get_val)(struct cpudata*, int pstate);
291 void (*get_vid)(struct cpudata *);
292};
293
294static struct pstate_funcs pstate_funcs __read_mostly;
295
296static bool hwp_active __ro_after_init;
297static int hwp_mode_bdw __ro_after_init;
298static bool per_cpu_limits __ro_after_init;
299static bool hwp_forced __ro_after_init;
300static bool hwp_boost __read_mostly;
301static bool hwp_is_hybrid;
302
303static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304
305#define HYBRID_SCALING_FACTOR 78741
306#define HYBRID_SCALING_FACTOR_MTL 80000
307#define HYBRID_SCALING_FACTOR_LNL 86957
308
309static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
310
311static inline int core_get_scaling(void)
312{
313 return 100000;
314}
315
316#ifdef CONFIG_ACPI
317static bool acpi_ppc;
318#endif
319
320static struct global_params global;
321
322static DEFINE_MUTEX(intel_pstate_driver_lock);
323static DEFINE_MUTEX(intel_pstate_limits_lock);
324
325#ifdef CONFIG_ACPI
326
327static bool intel_pstate_acpi_pm_profile_server(void)
328{
329 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
330 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
331 return true;
332
333 return false;
334}
335
336static bool intel_pstate_get_ppc_enable_status(void)
337{
338 if (intel_pstate_acpi_pm_profile_server())
339 return true;
340
341 return acpi_ppc;
342}
343
344#ifdef CONFIG_ACPI_CPPC_LIB
345
346/* The work item is needed to avoid CPU hotplug locking issues */
347static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
348{
349 sched_set_itmt_support();
350}
351
352static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
353
354#define CPPC_MAX_PERF U8_MAX
355
356static void intel_pstate_set_itmt_prio(int cpu)
357{
358 struct cppc_perf_caps cppc_perf;
359 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
360 int ret;
361
362 ret = cppc_get_perf_caps(cpu, &cppc_perf);
363 /*
364 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0].
365 *
366 * Also, on some systems with overclocking enabled, CPPC.highest_perf is
367 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT.
368 * Fall back to MSR_HWP_CAPABILITIES then too.
369 */
370 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF)
371 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
372
373 /*
374 * The priorities can be set regardless of whether or not
375 * sched_set_itmt_support(true) has been called and it is valid to
376 * update them at any time after it has been called.
377 */
378 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
379
380 if (max_highest_perf <= min_highest_perf) {
381 if (cppc_perf.highest_perf > max_highest_perf)
382 max_highest_perf = cppc_perf.highest_perf;
383
384 if (cppc_perf.highest_perf < min_highest_perf)
385 min_highest_perf = cppc_perf.highest_perf;
386
387 if (max_highest_perf > min_highest_perf) {
388 /*
389 * This code can be run during CPU online under the
390 * CPU hotplug locks, so sched_set_itmt_support()
391 * cannot be called from here. Queue up a work item
392 * to invoke it.
393 */
394 schedule_work(&sched_itmt_work);
395 }
396 }
397}
398
399static int intel_pstate_get_cppc_guaranteed(int cpu)
400{
401 struct cppc_perf_caps cppc_perf;
402 int ret;
403
404 ret = cppc_get_perf_caps(cpu, &cppc_perf);
405 if (ret)
406 return ret;
407
408 if (cppc_perf.guaranteed_perf)
409 return cppc_perf.guaranteed_perf;
410
411 return cppc_perf.nominal_perf;
412}
413
414static int intel_pstate_cppc_get_scaling(int cpu)
415{
416 struct cppc_perf_caps cppc_perf;
417 int ret;
418
419 ret = cppc_get_perf_caps(cpu, &cppc_perf);
420
421 /*
422 * If the nominal frequency and the nominal performance are not
423 * zero and the ratio between them is not 100, return the hybrid
424 * scaling factor.
425 */
426 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
427 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
428 return hybrid_scaling_factor;
429
430 return core_get_scaling();
431}
432
433#else /* CONFIG_ACPI_CPPC_LIB */
434static inline void intel_pstate_set_itmt_prio(int cpu)
435{
436}
437#endif /* CONFIG_ACPI_CPPC_LIB */
438
439static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
440{
441 struct cpudata *cpu;
442 int ret;
443 int i;
444
445 if (hwp_active) {
446 intel_pstate_set_itmt_prio(policy->cpu);
447 return;
448 }
449
450 if (!intel_pstate_get_ppc_enable_status())
451 return;
452
453 cpu = all_cpu_data[policy->cpu];
454
455 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
456 policy->cpu);
457 if (ret)
458 return;
459
460 /*
461 * Check if the control value in _PSS is for PERF_CTL MSR, which should
462 * guarantee that the states returned by it map to the states in our
463 * list directly.
464 */
465 if (cpu->acpi_perf_data.control_register.space_id !=
466 ACPI_ADR_SPACE_FIXED_HARDWARE)
467 goto err;
468
469 /*
470 * If there is only one entry _PSS, simply ignore _PSS and continue as
471 * usual without taking _PSS into account
472 */
473 if (cpu->acpi_perf_data.state_count < 2)
474 goto err;
475
476 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
477 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
478 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
479 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
480 (u32) cpu->acpi_perf_data.states[i].core_frequency,
481 (u32) cpu->acpi_perf_data.states[i].power,
482 (u32) cpu->acpi_perf_data.states[i].control);
483 }
484
485 cpu->valid_pss_table = true;
486 pr_debug("_PPC limits will be enforced\n");
487
488 return;
489
490 err:
491 cpu->valid_pss_table = false;
492 acpi_processor_unregister_performance(policy->cpu);
493}
494
495static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
496{
497 struct cpudata *cpu;
498
499 cpu = all_cpu_data[policy->cpu];
500 if (!cpu->valid_pss_table)
501 return;
502
503 acpi_processor_unregister_performance(policy->cpu);
504}
505#else /* CONFIG_ACPI */
506static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
507{
508}
509
510static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
511{
512}
513
514static inline bool intel_pstate_acpi_pm_profile_server(void)
515{
516 return false;
517}
518#endif /* CONFIG_ACPI */
519
520#ifndef CONFIG_ACPI_CPPC_LIB
521static inline int intel_pstate_get_cppc_guaranteed(int cpu)
522{
523 return -ENOTSUPP;
524}
525
526static int intel_pstate_cppc_get_scaling(int cpu)
527{
528 return core_get_scaling();
529}
530#endif /* CONFIG_ACPI_CPPC_LIB */
531
532static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
533 unsigned int relation)
534{
535 if (freq == cpu->pstate.turbo_freq)
536 return cpu->pstate.turbo_pstate;
537
538 if (freq == cpu->pstate.max_freq)
539 return cpu->pstate.max_pstate;
540
541 switch (relation) {
542 case CPUFREQ_RELATION_H:
543 return freq / cpu->pstate.scaling;
544 case CPUFREQ_RELATION_C:
545 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
546 }
547
548 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
549}
550
551static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
552{
553 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
554}
555
556/**
557 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
558 * @cpu: Target CPU.
559 *
560 * On hybrid processors, HWP may expose more performance levels than there are
561 * P-states accessible through the PERF_CTL interface. If that happens, the
562 * scaling factor between HWP performance levels and CPU frequency will be less
563 * than the scaling factor between P-state values and CPU frequency.
564 *
565 * In that case, adjust the CPU parameters used in computations accordingly.
566 */
567static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
568{
569 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
570 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
571 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
572 int scaling = cpu->pstate.scaling;
573 int freq;
574
575 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
576 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
577 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
578 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
579 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
580 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
581
582 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
583 perf_ctl_scaling);
584 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
585 perf_ctl_scaling);
586
587 freq = perf_ctl_max_phys * perf_ctl_scaling;
588 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
589
590 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
591 cpu->pstate.min_freq = freq;
592 /*
593 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
594 * the effective range of HWP performance levels.
595 */
596 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
597}
598
599static bool turbo_is_disabled(void)
600{
601 u64 misc_en;
602
603 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
604
605 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
606}
607
608static int min_perf_pct_min(void)
609{
610 struct cpudata *cpu = all_cpu_data[0];
611 int turbo_pstate = cpu->pstate.turbo_pstate;
612
613 return turbo_pstate ?
614 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
615}
616
617static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
618{
619 u64 epb;
620 int ret;
621
622 if (!boot_cpu_has(X86_FEATURE_EPB))
623 return -ENXIO;
624
625 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
626 if (ret)
627 return (s16)ret;
628
629 return (s16)(epb & 0x0f);
630}
631
632static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
633{
634 s16 epp;
635
636 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
637 /*
638 * When hwp_req_data is 0, means that caller didn't read
639 * MSR_HWP_REQUEST, so need to read and get EPP.
640 */
641 if (!hwp_req_data) {
642 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
643 &hwp_req_data);
644 if (epp)
645 return epp;
646 }
647 epp = (hwp_req_data >> 24) & 0xff;
648 } else {
649 /* When there is no EPP present, HWP uses EPB settings */
650 epp = intel_pstate_get_epb(cpu_data);
651 }
652
653 return epp;
654}
655
656static int intel_pstate_set_epb(int cpu, s16 pref)
657{
658 u64 epb;
659 int ret;
660
661 if (!boot_cpu_has(X86_FEATURE_EPB))
662 return -ENXIO;
663
664 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
665 if (ret)
666 return ret;
667
668 epb = (epb & ~0x0f) | pref;
669 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
670
671 return 0;
672}
673
674/*
675 * EPP/EPB display strings corresponding to EPP index in the
676 * energy_perf_strings[]
677 * index String
678 *-------------------------------------
679 * 0 default
680 * 1 performance
681 * 2 balance_performance
682 * 3 balance_power
683 * 4 power
684 */
685
686enum energy_perf_value_index {
687 EPP_INDEX_DEFAULT = 0,
688 EPP_INDEX_PERFORMANCE,
689 EPP_INDEX_BALANCE_PERFORMANCE,
690 EPP_INDEX_BALANCE_POWERSAVE,
691 EPP_INDEX_POWERSAVE,
692};
693
694static const char * const energy_perf_strings[] = {
695 [EPP_INDEX_DEFAULT] = "default",
696 [EPP_INDEX_PERFORMANCE] = "performance",
697 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
698 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
699 [EPP_INDEX_POWERSAVE] = "power",
700 NULL
701};
702static unsigned int epp_values[] = {
703 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
704 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
705 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
706 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
707 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
708};
709
710static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
711{
712 s16 epp;
713 int index = -EINVAL;
714
715 *raw_epp = 0;
716 epp = intel_pstate_get_epp(cpu_data, 0);
717 if (epp < 0)
718 return epp;
719
720 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
721 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
722 return EPP_INDEX_PERFORMANCE;
723 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
724 return EPP_INDEX_BALANCE_PERFORMANCE;
725 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
726 return EPP_INDEX_BALANCE_POWERSAVE;
727 if (epp == epp_values[EPP_INDEX_POWERSAVE])
728 return EPP_INDEX_POWERSAVE;
729 *raw_epp = epp;
730 return 0;
731 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
732 /*
733 * Range:
734 * 0x00-0x03 : Performance
735 * 0x04-0x07 : Balance performance
736 * 0x08-0x0B : Balance power
737 * 0x0C-0x0F : Power
738 * The EPB is a 4 bit value, but our ranges restrict the
739 * value which can be set. Here only using top two bits
740 * effectively.
741 */
742 index = (epp >> 2) + 1;
743 }
744
745 return index;
746}
747
748static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
749{
750 int ret;
751
752 /*
753 * Use the cached HWP Request MSR value, because in the active mode the
754 * register itself may be updated by intel_pstate_hwp_boost_up() or
755 * intel_pstate_hwp_boost_down() at any time.
756 */
757 u64 value = READ_ONCE(cpu->hwp_req_cached);
758
759 value &= ~GENMASK_ULL(31, 24);
760 value |= (u64)epp << 24;
761 /*
762 * The only other updater of hwp_req_cached in the active mode,
763 * intel_pstate_hwp_set(), is called under the same lock as this
764 * function, so it cannot run in parallel with the update below.
765 */
766 WRITE_ONCE(cpu->hwp_req_cached, value);
767 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
768 if (!ret)
769 cpu->epp_cached = epp;
770
771 return ret;
772}
773
774static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
775 int pref_index, bool use_raw,
776 u32 raw_epp)
777{
778 int epp = -EINVAL;
779 int ret;
780
781 if (!pref_index)
782 epp = cpu_data->epp_default;
783
784 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
785 if (use_raw)
786 epp = raw_epp;
787 else if (epp == -EINVAL)
788 epp = epp_values[pref_index];
789
790 /*
791 * To avoid confusion, refuse to set EPP to any values different
792 * from 0 (performance) if the current policy is "performance",
793 * because those values would be overridden.
794 */
795 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
796 return -EBUSY;
797
798 ret = intel_pstate_set_epp(cpu_data, epp);
799 } else {
800 if (epp == -EINVAL)
801 epp = (pref_index - 1) << 2;
802 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
803 }
804
805 return ret;
806}
807
808static ssize_t show_energy_performance_available_preferences(
809 struct cpufreq_policy *policy, char *buf)
810{
811 int i = 0;
812 int ret = 0;
813
814 while (energy_perf_strings[i] != NULL)
815 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
816
817 ret += sprintf(&buf[ret], "\n");
818
819 return ret;
820}
821
822cpufreq_freq_attr_ro(energy_performance_available_preferences);
823
824static struct cpufreq_driver intel_pstate;
825
826static ssize_t store_energy_performance_preference(
827 struct cpufreq_policy *policy, const char *buf, size_t count)
828{
829 struct cpudata *cpu = all_cpu_data[policy->cpu];
830 char str_preference[21];
831 bool raw = false;
832 ssize_t ret;
833 u32 epp = 0;
834
835 ret = sscanf(buf, "%20s", str_preference);
836 if (ret != 1)
837 return -EINVAL;
838
839 ret = match_string(energy_perf_strings, -1, str_preference);
840 if (ret < 0) {
841 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
842 return ret;
843
844 ret = kstrtouint(buf, 10, &epp);
845 if (ret)
846 return ret;
847
848 if (epp > 255)
849 return -EINVAL;
850
851 raw = true;
852 }
853
854 /*
855 * This function runs with the policy R/W semaphore held, which
856 * guarantees that the driver pointer will not change while it is
857 * running.
858 */
859 if (!intel_pstate_driver)
860 return -EAGAIN;
861
862 mutex_lock(&intel_pstate_limits_lock);
863
864 if (intel_pstate_driver == &intel_pstate) {
865 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
866 } else {
867 /*
868 * In the passive mode the governor needs to be stopped on the
869 * target CPU before the EPP update and restarted after it,
870 * which is super-heavy-weight, so make sure it is worth doing
871 * upfront.
872 */
873 if (!raw)
874 epp = ret ? epp_values[ret] : cpu->epp_default;
875
876 if (cpu->epp_cached != epp) {
877 int err;
878
879 cpufreq_stop_governor(policy);
880 ret = intel_pstate_set_epp(cpu, epp);
881 err = cpufreq_start_governor(policy);
882 if (!ret)
883 ret = err;
884 } else {
885 ret = 0;
886 }
887 }
888
889 mutex_unlock(&intel_pstate_limits_lock);
890
891 return ret ?: count;
892}
893
894static ssize_t show_energy_performance_preference(
895 struct cpufreq_policy *policy, char *buf)
896{
897 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
898 int preference, raw_epp;
899
900 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
901 if (preference < 0)
902 return preference;
903
904 if (raw_epp)
905 return sprintf(buf, "%d\n", raw_epp);
906 else
907 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
908}
909
910cpufreq_freq_attr_rw(energy_performance_preference);
911
912static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
913{
914 struct cpudata *cpu = all_cpu_data[policy->cpu];
915 int ratio, freq;
916
917 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
918 if (ratio <= 0) {
919 u64 cap;
920
921 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
922 ratio = HWP_GUARANTEED_PERF(cap);
923 }
924
925 freq = ratio * cpu->pstate.scaling;
926 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
927 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
928
929 return sprintf(buf, "%d\n", freq);
930}
931
932cpufreq_freq_attr_ro(base_frequency);
933
934static struct freq_attr *hwp_cpufreq_attrs[] = {
935 &energy_performance_preference,
936 &energy_performance_available_preferences,
937 &base_frequency,
938 NULL,
939};
940
941static struct cpudata *hybrid_max_perf_cpu __read_mostly;
942/*
943 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata,
944 * and the x86 arch scale-invariance information from concurrent updates.
945 */
946static DEFINE_MUTEX(hybrid_capacity_lock);
947
948static void hybrid_set_cpu_capacity(struct cpudata *cpu)
949{
950 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf,
951 hybrid_max_perf_cpu->capacity_perf,
952 cpu->capacity_perf,
953 cpu->pstate.max_pstate_physical);
954
955 pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu,
956 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf,
957 cpu->pstate.max_pstate_physical);
958}
959
960static void hybrid_clear_cpu_capacity(unsigned int cpunum)
961{
962 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1);
963}
964
965static void hybrid_get_capacity_perf(struct cpudata *cpu)
966{
967 if (READ_ONCE(global.no_turbo)) {
968 cpu->capacity_perf = cpu->pstate.max_pstate_physical;
969 return;
970 }
971
972 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
973}
974
975static void hybrid_set_capacity_of_cpus(void)
976{
977 int cpunum;
978
979 for_each_online_cpu(cpunum) {
980 struct cpudata *cpu = all_cpu_data[cpunum];
981
982 if (cpu)
983 hybrid_set_cpu_capacity(cpu);
984 }
985}
986
987static void hybrid_update_cpu_capacity_scaling(void)
988{
989 struct cpudata *max_perf_cpu = NULL;
990 unsigned int max_cap_perf = 0;
991 int cpunum;
992
993 for_each_online_cpu(cpunum) {
994 struct cpudata *cpu = all_cpu_data[cpunum];
995
996 if (!cpu)
997 continue;
998
999 /*
1000 * During initialization, CPU performance at full capacity needs
1001 * to be determined.
1002 */
1003 if (!hybrid_max_perf_cpu)
1004 hybrid_get_capacity_perf(cpu);
1005
1006 /*
1007 * If hybrid_max_perf_cpu is not NULL at this point, it is
1008 * being replaced, so don't take it into account when looking
1009 * for the new one.
1010 */
1011 if (cpu == hybrid_max_perf_cpu)
1012 continue;
1013
1014 if (cpu->capacity_perf > max_cap_perf) {
1015 max_cap_perf = cpu->capacity_perf;
1016 max_perf_cpu = cpu;
1017 }
1018 }
1019
1020 if (max_perf_cpu) {
1021 hybrid_max_perf_cpu = max_perf_cpu;
1022 hybrid_set_capacity_of_cpus();
1023 } else {
1024 pr_info("Found no CPUs with nonzero maximum performance\n");
1025 /* Revert to the flat CPU capacity structure. */
1026 for_each_online_cpu(cpunum)
1027 hybrid_clear_cpu_capacity(cpunum);
1028 }
1029}
1030
1031static void __hybrid_refresh_cpu_capacity_scaling(void)
1032{
1033 hybrid_max_perf_cpu = NULL;
1034 hybrid_update_cpu_capacity_scaling();
1035}
1036
1037static void hybrid_refresh_cpu_capacity_scaling(void)
1038{
1039 guard(mutex)(&hybrid_capacity_lock);
1040
1041 __hybrid_refresh_cpu_capacity_scaling();
1042}
1043
1044static void hybrid_init_cpu_capacity_scaling(bool refresh)
1045{
1046 /*
1047 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity
1048 * scaling has been enabled already and the driver is just changing the
1049 * operation mode.
1050 */
1051 if (refresh) {
1052 hybrid_refresh_cpu_capacity_scaling();
1053 return;
1054 }
1055
1056 /*
1057 * On hybrid systems, use asym capacity instead of ITMT, but because
1058 * the capacity of SMT threads is not deterministic even approximately,
1059 * do not do that when SMT is in use.
1060 */
1061 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) {
1062 hybrid_refresh_cpu_capacity_scaling();
1063 /*
1064 * Disabling ITMT causes sched domains to be rebuilt to disable asym
1065 * packing and enable asym capacity.
1066 */
1067 sched_clear_itmt_support();
1068 }
1069}
1070
1071static bool hybrid_clear_max_perf_cpu(void)
1072{
1073 bool ret;
1074
1075 guard(mutex)(&hybrid_capacity_lock);
1076
1077 ret = !!hybrid_max_perf_cpu;
1078 hybrid_max_perf_cpu = NULL;
1079
1080 return ret;
1081}
1082
1083static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
1084{
1085 u64 cap;
1086
1087 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
1088 WRITE_ONCE(cpu->hwp_cap_cached, cap);
1089 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
1090 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
1091}
1092
1093static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
1094{
1095 int scaling = cpu->pstate.scaling;
1096
1097 __intel_pstate_get_hwp_cap(cpu);
1098
1099 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
1100 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
1101 if (scaling != cpu->pstate.perf_ctl_scaling) {
1102 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
1103
1104 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
1105 perf_ctl_scaling);
1106 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
1107 perf_ctl_scaling);
1108 }
1109}
1110
1111static void hybrid_update_capacity(struct cpudata *cpu)
1112{
1113 unsigned int max_cap_perf;
1114
1115 mutex_lock(&hybrid_capacity_lock);
1116
1117 if (!hybrid_max_perf_cpu)
1118 goto unlock;
1119
1120 /*
1121 * The maximum performance of the CPU may have changed, but assume
1122 * that the performance of the other CPUs has not changed.
1123 */
1124 max_cap_perf = hybrid_max_perf_cpu->capacity_perf;
1125
1126 intel_pstate_get_hwp_cap(cpu);
1127
1128 hybrid_get_capacity_perf(cpu);
1129 /* Should hybrid_max_perf_cpu be replaced by this CPU? */
1130 if (cpu->capacity_perf > max_cap_perf) {
1131 hybrid_max_perf_cpu = cpu;
1132 hybrid_set_capacity_of_cpus();
1133 goto unlock;
1134 }
1135
1136 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */
1137 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) {
1138 hybrid_update_cpu_capacity_scaling();
1139 goto unlock;
1140 }
1141
1142 hybrid_set_cpu_capacity(cpu);
1143
1144unlock:
1145 mutex_unlock(&hybrid_capacity_lock);
1146}
1147
1148static void intel_pstate_hwp_set(unsigned int cpu)
1149{
1150 struct cpudata *cpu_data = all_cpu_data[cpu];
1151 int max, min;
1152 u64 value;
1153 s16 epp;
1154
1155 max = cpu_data->max_perf_ratio;
1156 min = cpu_data->min_perf_ratio;
1157
1158 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
1159 min = max;
1160
1161 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
1162
1163 value &= ~HWP_MIN_PERF(~0L);
1164 value |= HWP_MIN_PERF(min);
1165
1166 value &= ~HWP_MAX_PERF(~0L);
1167 value |= HWP_MAX_PERF(max);
1168
1169 if (cpu_data->epp_policy == cpu_data->policy)
1170 goto skip_epp;
1171
1172 cpu_data->epp_policy = cpu_data->policy;
1173
1174 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
1175 epp = intel_pstate_get_epp(cpu_data, value);
1176 cpu_data->epp_powersave = epp;
1177 /* If EPP read was failed, then don't try to write */
1178 if (epp < 0)
1179 goto skip_epp;
1180
1181 epp = 0;
1182 } else {
1183 /* skip setting EPP, when saved value is invalid */
1184 if (cpu_data->epp_powersave < 0)
1185 goto skip_epp;
1186
1187 /*
1188 * No need to restore EPP when it is not zero. This
1189 * means:
1190 * - Policy is not changed
1191 * - user has manually changed
1192 * - Error reading EPB
1193 */
1194 epp = intel_pstate_get_epp(cpu_data, value);
1195 if (epp)
1196 goto skip_epp;
1197
1198 epp = cpu_data->epp_powersave;
1199 }
1200 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1201 value &= ~GENMASK_ULL(31, 24);
1202 value |= (u64)epp << 24;
1203 } else {
1204 intel_pstate_set_epb(cpu, epp);
1205 }
1206skip_epp:
1207 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1208 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1209}
1210
1211static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1212
1213static void intel_pstate_hwp_offline(struct cpudata *cpu)
1214{
1215 u64 value = READ_ONCE(cpu->hwp_req_cached);
1216 int min_perf;
1217
1218 intel_pstate_disable_hwp_interrupt(cpu);
1219
1220 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1221 /*
1222 * In case the EPP has been set to "performance" by the
1223 * active mode "performance" scaling algorithm, replace that
1224 * temporary value with the cached EPP one.
1225 */
1226 value &= ~GENMASK_ULL(31, 24);
1227 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1228 /*
1229 * However, make sure that EPP will be set to "performance" when
1230 * the CPU is brought back online again and the "performance"
1231 * scaling algorithm is still in effect.
1232 */
1233 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1234 }
1235
1236 /*
1237 * Clear the desired perf field in the cached HWP request value to
1238 * prevent nonzero desired values from being leaked into the active
1239 * mode.
1240 */
1241 value &= ~HWP_DESIRED_PERF(~0L);
1242 WRITE_ONCE(cpu->hwp_req_cached, value);
1243
1244 value &= ~GENMASK_ULL(31, 0);
1245 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1246
1247 /* Set hwp_max = hwp_min */
1248 value |= HWP_MAX_PERF(min_perf);
1249 value |= HWP_MIN_PERF(min_perf);
1250
1251 /* Set EPP to min */
1252 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1253 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1254
1255 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1256
1257 mutex_lock(&hybrid_capacity_lock);
1258
1259 if (!hybrid_max_perf_cpu) {
1260 mutex_unlock(&hybrid_capacity_lock);
1261
1262 return;
1263 }
1264
1265 if (hybrid_max_perf_cpu == cpu)
1266 hybrid_update_cpu_capacity_scaling();
1267
1268 mutex_unlock(&hybrid_capacity_lock);
1269
1270 /* Reset the capacity of the CPU going offline to the initial value. */
1271 hybrid_clear_cpu_capacity(cpu->cpu);
1272}
1273
1274#define POWER_CTL_EE_ENABLE 1
1275#define POWER_CTL_EE_DISABLE 2
1276
1277static int power_ctl_ee_state;
1278
1279static void set_power_ctl_ee_state(bool input)
1280{
1281 u64 power_ctl;
1282
1283 mutex_lock(&intel_pstate_driver_lock);
1284 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1285 if (input) {
1286 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1287 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1288 } else {
1289 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1290 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1291 }
1292 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1293 mutex_unlock(&intel_pstate_driver_lock);
1294}
1295
1296static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1297
1298static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1299{
1300 intel_pstate_hwp_enable(cpu);
1301 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1302}
1303
1304static int intel_pstate_suspend(struct cpufreq_policy *policy)
1305{
1306 struct cpudata *cpu = all_cpu_data[policy->cpu];
1307
1308 pr_debug("CPU %d suspending\n", cpu->cpu);
1309
1310 cpu->suspended = true;
1311
1312 /* disable HWP interrupt and cancel any pending work */
1313 intel_pstate_disable_hwp_interrupt(cpu);
1314
1315 return 0;
1316}
1317
1318static int intel_pstate_resume(struct cpufreq_policy *policy)
1319{
1320 struct cpudata *cpu = all_cpu_data[policy->cpu];
1321
1322 pr_debug("CPU %d resuming\n", cpu->cpu);
1323
1324 /* Only restore if the system default is changed */
1325 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1326 set_power_ctl_ee_state(true);
1327 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1328 set_power_ctl_ee_state(false);
1329
1330 if (cpu->suspended && hwp_active) {
1331 mutex_lock(&intel_pstate_limits_lock);
1332
1333 /* Re-enable HWP, because "online" has not done that. */
1334 intel_pstate_hwp_reenable(cpu);
1335
1336 mutex_unlock(&intel_pstate_limits_lock);
1337 }
1338
1339 cpu->suspended = false;
1340
1341 return 0;
1342}
1343
1344static void intel_pstate_update_policies(void)
1345{
1346 int cpu;
1347
1348 for_each_possible_cpu(cpu)
1349 cpufreq_update_policy(cpu);
1350}
1351
1352static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1353 struct cpufreq_policy *policy)
1354{
1355 if (hwp_active)
1356 intel_pstate_get_hwp_cap(cpudata);
1357
1358 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
1359 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1360
1361 refresh_frequency_limits(policy);
1362}
1363
1364static void intel_pstate_update_limits(unsigned int cpu)
1365{
1366 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1367 struct cpudata *cpudata;
1368
1369 if (!policy)
1370 return;
1371
1372 cpudata = all_cpu_data[cpu];
1373
1374 __intel_pstate_update_max_freq(cpudata, policy);
1375
1376 /* Prevent the driver from being unregistered now. */
1377 mutex_lock(&intel_pstate_driver_lock);
1378
1379 cpufreq_cpu_release(policy);
1380
1381 hybrid_update_capacity(cpudata);
1382
1383 mutex_unlock(&intel_pstate_driver_lock);
1384}
1385
1386static void intel_pstate_update_limits_for_all(void)
1387{
1388 int cpu;
1389
1390 for_each_possible_cpu(cpu) {
1391 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1392
1393 if (!policy)
1394 continue;
1395
1396 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1397
1398 cpufreq_cpu_release(policy);
1399 }
1400
1401 mutex_lock(&hybrid_capacity_lock);
1402
1403 if (hybrid_max_perf_cpu)
1404 __hybrid_refresh_cpu_capacity_scaling();
1405
1406 mutex_unlock(&hybrid_capacity_lock);
1407}
1408
1409/************************** sysfs begin ************************/
1410#define show_one(file_name, object) \
1411 static ssize_t show_##file_name \
1412 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1413 { \
1414 return sprintf(buf, "%u\n", global.object); \
1415 }
1416
1417static ssize_t intel_pstate_show_status(char *buf);
1418static int intel_pstate_update_status(const char *buf, size_t size);
1419
1420static ssize_t show_status(struct kobject *kobj,
1421 struct kobj_attribute *attr, char *buf)
1422{
1423 ssize_t ret;
1424
1425 mutex_lock(&intel_pstate_driver_lock);
1426 ret = intel_pstate_show_status(buf);
1427 mutex_unlock(&intel_pstate_driver_lock);
1428
1429 return ret;
1430}
1431
1432static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1433 const char *buf, size_t count)
1434{
1435 char *p = memchr(buf, '\n', count);
1436 int ret;
1437
1438 mutex_lock(&intel_pstate_driver_lock);
1439 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1440 mutex_unlock(&intel_pstate_driver_lock);
1441
1442 return ret < 0 ? ret : count;
1443}
1444
1445static ssize_t show_turbo_pct(struct kobject *kobj,
1446 struct kobj_attribute *attr, char *buf)
1447{
1448 struct cpudata *cpu;
1449 int total, no_turbo, turbo_pct;
1450 uint32_t turbo_fp;
1451
1452 mutex_lock(&intel_pstate_driver_lock);
1453
1454 if (!intel_pstate_driver) {
1455 mutex_unlock(&intel_pstate_driver_lock);
1456 return -EAGAIN;
1457 }
1458
1459 cpu = all_cpu_data[0];
1460
1461 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1462 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1463 turbo_fp = div_fp(no_turbo, total);
1464 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1465
1466 mutex_unlock(&intel_pstate_driver_lock);
1467
1468 return sprintf(buf, "%u\n", turbo_pct);
1469}
1470
1471static ssize_t show_num_pstates(struct kobject *kobj,
1472 struct kobj_attribute *attr, char *buf)
1473{
1474 struct cpudata *cpu;
1475 int total;
1476
1477 mutex_lock(&intel_pstate_driver_lock);
1478
1479 if (!intel_pstate_driver) {
1480 mutex_unlock(&intel_pstate_driver_lock);
1481 return -EAGAIN;
1482 }
1483
1484 cpu = all_cpu_data[0];
1485 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1486
1487 mutex_unlock(&intel_pstate_driver_lock);
1488
1489 return sprintf(buf, "%u\n", total);
1490}
1491
1492static ssize_t show_no_turbo(struct kobject *kobj,
1493 struct kobj_attribute *attr, char *buf)
1494{
1495 ssize_t ret;
1496
1497 mutex_lock(&intel_pstate_driver_lock);
1498
1499 if (!intel_pstate_driver) {
1500 mutex_unlock(&intel_pstate_driver_lock);
1501 return -EAGAIN;
1502 }
1503
1504 ret = sprintf(buf, "%u\n", global.no_turbo);
1505
1506 mutex_unlock(&intel_pstate_driver_lock);
1507
1508 return ret;
1509}
1510
1511static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1512 const char *buf, size_t count)
1513{
1514 unsigned int input;
1515 bool no_turbo;
1516
1517 if (sscanf(buf, "%u", &input) != 1)
1518 return -EINVAL;
1519
1520 mutex_lock(&intel_pstate_driver_lock);
1521
1522 if (!intel_pstate_driver) {
1523 count = -EAGAIN;
1524 goto unlock_driver;
1525 }
1526
1527 no_turbo = !!clamp_t(int, input, 0, 1);
1528
1529 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled());
1530 if (global.turbo_disabled && !no_turbo) {
1531 pr_notice("Turbo disabled by BIOS or unavailable on processor\n");
1532 count = -EPERM;
1533 if (global.no_turbo)
1534 goto unlock_driver;
1535 else
1536 no_turbo = 1;
1537 }
1538
1539 if (no_turbo == global.no_turbo) {
1540 goto unlock_driver;
1541 }
1542
1543 WRITE_ONCE(global.no_turbo, no_turbo);
1544
1545 mutex_lock(&intel_pstate_limits_lock);
1546
1547 if (no_turbo) {
1548 struct cpudata *cpu = all_cpu_data[0];
1549 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1550
1551 /* Squash the global minimum into the permitted range. */
1552 if (global.min_perf_pct > pct)
1553 global.min_perf_pct = pct;
1554 }
1555
1556 mutex_unlock(&intel_pstate_limits_lock);
1557
1558 intel_pstate_update_limits_for_all();
1559 arch_set_max_freq_ratio(no_turbo);
1560
1561unlock_driver:
1562 mutex_unlock(&intel_pstate_driver_lock);
1563
1564 return count;
1565}
1566
1567static void update_qos_request(enum freq_qos_req_type type)
1568{
1569 struct freq_qos_request *req;
1570 struct cpufreq_policy *policy;
1571 int i;
1572
1573 for_each_possible_cpu(i) {
1574 struct cpudata *cpu = all_cpu_data[i];
1575 unsigned int freq, perf_pct;
1576
1577 policy = cpufreq_cpu_get(i);
1578 if (!policy)
1579 continue;
1580
1581 req = policy->driver_data;
1582 cpufreq_cpu_put(policy);
1583
1584 if (!req)
1585 continue;
1586
1587 if (hwp_active)
1588 intel_pstate_get_hwp_cap(cpu);
1589
1590 if (type == FREQ_QOS_MIN) {
1591 perf_pct = global.min_perf_pct;
1592 } else {
1593 req++;
1594 perf_pct = global.max_perf_pct;
1595 }
1596
1597 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1598
1599 if (freq_qos_update_request(req, freq) < 0)
1600 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1601 }
1602}
1603
1604static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1605 const char *buf, size_t count)
1606{
1607 unsigned int input;
1608 int ret;
1609
1610 ret = sscanf(buf, "%u", &input);
1611 if (ret != 1)
1612 return -EINVAL;
1613
1614 mutex_lock(&intel_pstate_driver_lock);
1615
1616 if (!intel_pstate_driver) {
1617 mutex_unlock(&intel_pstate_driver_lock);
1618 return -EAGAIN;
1619 }
1620
1621 mutex_lock(&intel_pstate_limits_lock);
1622
1623 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1624
1625 mutex_unlock(&intel_pstate_limits_lock);
1626
1627 if (intel_pstate_driver == &intel_pstate)
1628 intel_pstate_update_policies();
1629 else
1630 update_qos_request(FREQ_QOS_MAX);
1631
1632 mutex_unlock(&intel_pstate_driver_lock);
1633
1634 return count;
1635}
1636
1637static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1638 const char *buf, size_t count)
1639{
1640 unsigned int input;
1641 int ret;
1642
1643 ret = sscanf(buf, "%u", &input);
1644 if (ret != 1)
1645 return -EINVAL;
1646
1647 mutex_lock(&intel_pstate_driver_lock);
1648
1649 if (!intel_pstate_driver) {
1650 mutex_unlock(&intel_pstate_driver_lock);
1651 return -EAGAIN;
1652 }
1653
1654 mutex_lock(&intel_pstate_limits_lock);
1655
1656 global.min_perf_pct = clamp_t(int, input,
1657 min_perf_pct_min(), global.max_perf_pct);
1658
1659 mutex_unlock(&intel_pstate_limits_lock);
1660
1661 if (intel_pstate_driver == &intel_pstate)
1662 intel_pstate_update_policies();
1663 else
1664 update_qos_request(FREQ_QOS_MIN);
1665
1666 mutex_unlock(&intel_pstate_driver_lock);
1667
1668 return count;
1669}
1670
1671static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1672 struct kobj_attribute *attr, char *buf)
1673{
1674 return sprintf(buf, "%u\n", hwp_boost);
1675}
1676
1677static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1678 struct kobj_attribute *b,
1679 const char *buf, size_t count)
1680{
1681 unsigned int input;
1682 int ret;
1683
1684 ret = kstrtouint(buf, 10, &input);
1685 if (ret)
1686 return ret;
1687
1688 mutex_lock(&intel_pstate_driver_lock);
1689 hwp_boost = !!input;
1690 intel_pstate_update_policies();
1691 mutex_unlock(&intel_pstate_driver_lock);
1692
1693 return count;
1694}
1695
1696static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1697 char *buf)
1698{
1699 u64 power_ctl;
1700 int enable;
1701
1702 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1703 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1704 return sprintf(buf, "%d\n", !enable);
1705}
1706
1707static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1708 const char *buf, size_t count)
1709{
1710 bool input;
1711 int ret;
1712
1713 ret = kstrtobool(buf, &input);
1714 if (ret)
1715 return ret;
1716
1717 set_power_ctl_ee_state(input);
1718
1719 return count;
1720}
1721
1722show_one(max_perf_pct, max_perf_pct);
1723show_one(min_perf_pct, min_perf_pct);
1724
1725define_one_global_rw(status);
1726define_one_global_rw(no_turbo);
1727define_one_global_rw(max_perf_pct);
1728define_one_global_rw(min_perf_pct);
1729define_one_global_ro(turbo_pct);
1730define_one_global_ro(num_pstates);
1731define_one_global_rw(hwp_dynamic_boost);
1732define_one_global_rw(energy_efficiency);
1733
1734static struct attribute *intel_pstate_attributes[] = {
1735 &status.attr,
1736 &no_turbo.attr,
1737 NULL
1738};
1739
1740static const struct attribute_group intel_pstate_attr_group = {
1741 .attrs = intel_pstate_attributes,
1742};
1743
1744static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1745
1746static struct kobject *intel_pstate_kobject;
1747
1748static void __init intel_pstate_sysfs_expose_params(void)
1749{
1750 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1751 int rc;
1752
1753 if (dev_root) {
1754 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1755 put_device(dev_root);
1756 }
1757 if (WARN_ON(!intel_pstate_kobject))
1758 return;
1759
1760 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1761 if (WARN_ON(rc))
1762 return;
1763
1764 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1765 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1766 WARN_ON(rc);
1767
1768 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1769 WARN_ON(rc);
1770 }
1771
1772 /*
1773 * If per cpu limits are enforced there are no global limits, so
1774 * return without creating max/min_perf_pct attributes
1775 */
1776 if (per_cpu_limits)
1777 return;
1778
1779 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1780 WARN_ON(rc);
1781
1782 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1783 WARN_ON(rc);
1784
1785 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1786 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1787 WARN_ON(rc);
1788 }
1789}
1790
1791static void __init intel_pstate_sysfs_remove(void)
1792{
1793 if (!intel_pstate_kobject)
1794 return;
1795
1796 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1797
1798 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1799 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1800 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1801 }
1802
1803 if (!per_cpu_limits) {
1804 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1805 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1806
1807 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1808 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1809 }
1810
1811 kobject_put(intel_pstate_kobject);
1812}
1813
1814static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1815{
1816 int rc;
1817
1818 if (!hwp_active)
1819 return;
1820
1821 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1822 WARN_ON_ONCE(rc);
1823}
1824
1825static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1826{
1827 if (!hwp_active)
1828 return;
1829
1830 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1831}
1832
1833/************************** sysfs end ************************/
1834
1835static void intel_pstate_notify_work(struct work_struct *work)
1836{
1837 struct cpudata *cpudata =
1838 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1839 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1840
1841 if (policy) {
1842 __intel_pstate_update_max_freq(cpudata, policy);
1843
1844 cpufreq_cpu_release(policy);
1845
1846 /*
1847 * The driver will not be unregistered while this function is
1848 * running, so update the capacity without acquiring the driver
1849 * lock.
1850 */
1851 hybrid_update_capacity(cpudata);
1852 }
1853
1854 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1855}
1856
1857static DEFINE_RAW_SPINLOCK(hwp_notify_lock);
1858static cpumask_t hwp_intr_enable_mask;
1859
1860#define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0)
1861#define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3)
1862
1863void notify_hwp_interrupt(void)
1864{
1865 unsigned int this_cpu = smp_processor_id();
1866 u64 value, status_mask;
1867 unsigned long flags;
1868
1869 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1870 return;
1871
1872 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS;
1873 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1874 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
1875
1876 rdmsrl_safe(MSR_HWP_STATUS, &value);
1877 if (!(value & status_mask))
1878 return;
1879
1880 raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1881
1882 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1883 goto ack_intr;
1884
1885 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work,
1886 msecs_to_jiffies(10));
1887
1888 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1889
1890 return;
1891
1892ack_intr:
1893 wrmsrl_safe(MSR_HWP_STATUS, 0);
1894 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1895}
1896
1897static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1898{
1899 bool cancel_work;
1900
1901 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1902 return;
1903
1904 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1905 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1906
1907 raw_spin_lock_irq(&hwp_notify_lock);
1908 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1909 raw_spin_unlock_irq(&hwp_notify_lock);
1910
1911 if (cancel_work)
1912 cancel_delayed_work_sync(&cpudata->hwp_notify_work);
1913}
1914
1915#define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0)
1916#define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2)
1917
1918static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1919{
1920 /* Enable HWP notification interrupt for performance change */
1921 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1922 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ;
1923
1924 raw_spin_lock_irq(&hwp_notify_lock);
1925 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1926 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1927 raw_spin_unlock_irq(&hwp_notify_lock);
1928
1929 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1930 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
1931
1932 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1933 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
1934 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1935 }
1936}
1937
1938static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1939{
1940 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1941
1942 /*
1943 * If the EPP is set by firmware, which means that firmware enabled HWP
1944 * - Is equal or less than 0x80 (default balance_perf EPP)
1945 * - But less performance oriented than performance EPP
1946 * then use this as new balance_perf EPP.
1947 */
1948 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1949 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1950 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1951 return;
1952 }
1953
1954 /*
1955 * If this CPU gen doesn't call for change in balance_perf
1956 * EPP return.
1957 */
1958 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1959 return;
1960
1961 /*
1962 * Use hard coded value per gen to update the balance_perf
1963 * and default EPP.
1964 */
1965 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1966 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1967}
1968
1969static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1970{
1971 /* First disable HWP notification interrupt till we activate again */
1972 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1973 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1974
1975 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1976
1977 intel_pstate_enable_hwp_interrupt(cpudata);
1978
1979 if (cpudata->epp_default >= 0)
1980 return;
1981
1982 intel_pstate_update_epp_defaults(cpudata);
1983}
1984
1985static int atom_get_min_pstate(int not_used)
1986{
1987 u64 value;
1988
1989 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1990 return (value >> 8) & 0x7F;
1991}
1992
1993static int atom_get_max_pstate(int not_used)
1994{
1995 u64 value;
1996
1997 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1998 return (value >> 16) & 0x7F;
1999}
2000
2001static int atom_get_turbo_pstate(int not_used)
2002{
2003 u64 value;
2004
2005 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
2006 return value & 0x7F;
2007}
2008
2009static u64 atom_get_val(struct cpudata *cpudata, int pstate)
2010{
2011 u64 val;
2012 int32_t vid_fp;
2013 u32 vid;
2014
2015 val = (u64)pstate << 8;
2016 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled))
2017 val |= (u64)1 << 32;
2018
2019 vid_fp = cpudata->vid.min + mul_fp(
2020 int_tofp(pstate - cpudata->pstate.min_pstate),
2021 cpudata->vid.ratio);
2022
2023 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
2024 vid = ceiling_fp(vid_fp);
2025
2026 if (pstate > cpudata->pstate.max_pstate)
2027 vid = cpudata->vid.turbo;
2028
2029 return val | vid;
2030}
2031
2032static int silvermont_get_scaling(void)
2033{
2034 u64 value;
2035 int i;
2036 /* Defined in Table 35-6 from SDM (Sept 2015) */
2037 static int silvermont_freq_table[] = {
2038 83300, 100000, 133300, 116700, 80000};
2039
2040 rdmsrl(MSR_FSB_FREQ, value);
2041 i = value & 0x7;
2042 WARN_ON(i > 4);
2043
2044 return silvermont_freq_table[i];
2045}
2046
2047static int airmont_get_scaling(void)
2048{
2049 u64 value;
2050 int i;
2051 /* Defined in Table 35-10 from SDM (Sept 2015) */
2052 static int airmont_freq_table[] = {
2053 83300, 100000, 133300, 116700, 80000,
2054 93300, 90000, 88900, 87500};
2055
2056 rdmsrl(MSR_FSB_FREQ, value);
2057 i = value & 0xF;
2058 WARN_ON(i > 8);
2059
2060 return airmont_freq_table[i];
2061}
2062
2063static void atom_get_vid(struct cpudata *cpudata)
2064{
2065 u64 value;
2066
2067 rdmsrl(MSR_ATOM_CORE_VIDS, value);
2068 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
2069 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
2070 cpudata->vid.ratio = div_fp(
2071 cpudata->vid.max - cpudata->vid.min,
2072 int_tofp(cpudata->pstate.max_pstate -
2073 cpudata->pstate.min_pstate));
2074
2075 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
2076 cpudata->vid.turbo = value & 0x7f;
2077}
2078
2079static int core_get_min_pstate(int cpu)
2080{
2081 u64 value;
2082
2083 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2084 return (value >> 40) & 0xFF;
2085}
2086
2087static int core_get_max_pstate_physical(int cpu)
2088{
2089 u64 value;
2090
2091 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2092 return (value >> 8) & 0xFF;
2093}
2094
2095static int core_get_tdp_ratio(int cpu, u64 plat_info)
2096{
2097 /* Check how many TDP levels present */
2098 if (plat_info & 0x600000000) {
2099 u64 tdp_ctrl;
2100 u64 tdp_ratio;
2101 int tdp_msr;
2102 int err;
2103
2104 /* Get the TDP level (0, 1, 2) to get ratios */
2105 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
2106 if (err)
2107 return err;
2108
2109 /* TDP MSR are continuous starting at 0x648 */
2110 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
2111 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
2112 if (err)
2113 return err;
2114
2115 /* For level 1 and 2, bits[23:16] contain the ratio */
2116 if (tdp_ctrl & 0x03)
2117 tdp_ratio >>= 16;
2118
2119 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
2120 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
2121
2122 return (int)tdp_ratio;
2123 }
2124
2125 return -ENXIO;
2126}
2127
2128static int core_get_max_pstate(int cpu)
2129{
2130 u64 tar;
2131 u64 plat_info;
2132 int max_pstate;
2133 int tdp_ratio;
2134 int err;
2135
2136 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
2137 max_pstate = (plat_info >> 8) & 0xFF;
2138
2139 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
2140 if (tdp_ratio <= 0)
2141 return max_pstate;
2142
2143 if (hwp_active) {
2144 /* Turbo activation ratio is not used on HWP platforms */
2145 return tdp_ratio;
2146 }
2147
2148 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
2149 if (!err) {
2150 int tar_levels;
2151
2152 /* Do some sanity checking for safety */
2153 tar_levels = tar & 0xff;
2154 if (tdp_ratio - 1 == tar_levels) {
2155 max_pstate = tar_levels;
2156 pr_debug("max_pstate=TAC %x\n", max_pstate);
2157 }
2158 }
2159
2160 return max_pstate;
2161}
2162
2163static int core_get_turbo_pstate(int cpu)
2164{
2165 u64 value;
2166 int nont, ret;
2167
2168 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2169 nont = core_get_max_pstate(cpu);
2170 ret = (value) & 255;
2171 if (ret <= nont)
2172 ret = nont;
2173 return ret;
2174}
2175
2176static u64 core_get_val(struct cpudata *cpudata, int pstate)
2177{
2178 u64 val;
2179
2180 val = (u64)pstate << 8;
2181 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled))
2182 val |= (u64)1 << 32;
2183
2184 return val;
2185}
2186
2187static int knl_get_aperf_mperf_shift(void)
2188{
2189 return 10;
2190}
2191
2192static int knl_get_turbo_pstate(int cpu)
2193{
2194 u64 value;
2195 int nont, ret;
2196
2197 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2198 nont = core_get_max_pstate(cpu);
2199 ret = (((value) >> 8) & 0xFF);
2200 if (ret <= nont)
2201 ret = nont;
2202 return ret;
2203}
2204
2205static void hybrid_get_type(void *data)
2206{
2207 u8 *cpu_type = data;
2208
2209 *cpu_type = get_this_hybrid_cpu_type();
2210}
2211
2212static int hwp_get_cpu_scaling(int cpu)
2213{
2214 u8 cpu_type = 0;
2215
2216 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
2217 /* P-cores have a smaller perf level-to-freqency scaling factor. */
2218 if (cpu_type == 0x40)
2219 return hybrid_scaling_factor;
2220
2221 /* Use default core scaling for E-cores */
2222 if (cpu_type == 0x20)
2223 return core_get_scaling();
2224
2225 /*
2226 * If reached here, this system is either non-hybrid (like Tiger
2227 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2228 * no E cores (in which case CPUID for hybrid support is 0).
2229 *
2230 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2231 * so the default core scaling will be used for them.
2232 */
2233 return intel_pstate_cppc_get_scaling(cpu);
2234}
2235
2236static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2237{
2238 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2239 cpu->pstate.current_pstate = pstate;
2240 /*
2241 * Generally, there is no guarantee that this code will always run on
2242 * the CPU being updated, so force the register update to run on the
2243 * right CPU.
2244 */
2245 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2246 pstate_funcs.get_val(cpu, pstate));
2247}
2248
2249static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2250{
2251 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2252}
2253
2254static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2255{
2256 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2257 int perf_ctl_scaling = pstate_funcs.get_scaling();
2258
2259 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2260 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2261 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2262
2263 if (hwp_active && !hwp_mode_bdw) {
2264 __intel_pstate_get_hwp_cap(cpu);
2265
2266 if (pstate_funcs.get_cpu_scaling) {
2267 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2268 if (cpu->pstate.scaling != perf_ctl_scaling) {
2269 intel_pstate_hybrid_hwp_adjust(cpu);
2270 hwp_is_hybrid = true;
2271 }
2272 } else {
2273 cpu->pstate.scaling = perf_ctl_scaling;
2274 }
2275 /*
2276 * If the CPU is going online for the first time and it was
2277 * offline initially, asym capacity scaling needs to be updated.
2278 */
2279 hybrid_update_capacity(cpu);
2280 } else {
2281 cpu->pstate.scaling = perf_ctl_scaling;
2282 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2283 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2284 }
2285
2286 if (cpu->pstate.scaling == perf_ctl_scaling) {
2287 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2288 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2289 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2290 }
2291
2292 if (pstate_funcs.get_aperf_mperf_shift)
2293 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2294
2295 if (pstate_funcs.get_vid)
2296 pstate_funcs.get_vid(cpu);
2297
2298 intel_pstate_set_min_pstate(cpu);
2299}
2300
2301/*
2302 * Long hold time will keep high perf limits for long time,
2303 * which negatively impacts perf/watt for some workloads,
2304 * like specpower. 3ms is based on experiements on some
2305 * workoads.
2306 */
2307static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2308
2309static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2310{
2311 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2312 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2313 u32 max_limit = (hwp_req & 0xff00) >> 8;
2314 u32 min_limit = (hwp_req & 0xff);
2315 u32 boost_level1;
2316
2317 /*
2318 * Cases to consider (User changes via sysfs or boot time):
2319 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2320 * No boost, return.
2321 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2322 * Should result in one level boost only for P0.
2323 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2324 * Should result in two level boost:
2325 * (min + p1)/2 and P1.
2326 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2327 * Should result in three level boost:
2328 * (min + p1)/2, P1 and P0.
2329 */
2330
2331 /* If max and min are equal or already at max, nothing to boost */
2332 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2333 return;
2334
2335 if (!cpu->hwp_boost_min)
2336 cpu->hwp_boost_min = min_limit;
2337
2338 /* level at half way mark between min and guranteed */
2339 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2340
2341 if (cpu->hwp_boost_min < boost_level1)
2342 cpu->hwp_boost_min = boost_level1;
2343 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2344 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2345 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2346 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2347 cpu->hwp_boost_min = max_limit;
2348 else
2349 return;
2350
2351 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2352 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2353 cpu->last_update = cpu->sample.time;
2354}
2355
2356static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2357{
2358 if (cpu->hwp_boost_min) {
2359 bool expired;
2360
2361 /* Check if we are idle for hold time to boost down */
2362 expired = time_after64(cpu->sample.time, cpu->last_update +
2363 hwp_boost_hold_time_ns);
2364 if (expired) {
2365 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2366 cpu->hwp_boost_min = 0;
2367 }
2368 }
2369 cpu->last_update = cpu->sample.time;
2370}
2371
2372static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2373 u64 time)
2374{
2375 cpu->sample.time = time;
2376
2377 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2378 bool do_io = false;
2379
2380 cpu->sched_flags = 0;
2381 /*
2382 * Set iowait_boost flag and update time. Since IO WAIT flag
2383 * is set all the time, we can't just conclude that there is
2384 * some IO bound activity is scheduled on this CPU with just
2385 * one occurrence. If we receive at least two in two
2386 * consecutive ticks, then we treat as boost candidate.
2387 */
2388 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2389 do_io = true;
2390
2391 cpu->last_io_update = time;
2392
2393 if (do_io)
2394 intel_pstate_hwp_boost_up(cpu);
2395
2396 } else {
2397 intel_pstate_hwp_boost_down(cpu);
2398 }
2399}
2400
2401static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2402 u64 time, unsigned int flags)
2403{
2404 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2405
2406 cpu->sched_flags |= flags;
2407
2408 if (smp_processor_id() == cpu->cpu)
2409 intel_pstate_update_util_hwp_local(cpu, time);
2410}
2411
2412static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2413{
2414 struct sample *sample = &cpu->sample;
2415
2416 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2417}
2418
2419static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2420{
2421 u64 aperf, mperf;
2422 unsigned long flags;
2423 u64 tsc;
2424
2425 local_irq_save(flags);
2426 rdmsrl(MSR_IA32_APERF, aperf);
2427 rdmsrl(MSR_IA32_MPERF, mperf);
2428 tsc = rdtsc();
2429 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2430 local_irq_restore(flags);
2431 return false;
2432 }
2433 local_irq_restore(flags);
2434
2435 cpu->last_sample_time = cpu->sample.time;
2436 cpu->sample.time = time;
2437 cpu->sample.aperf = aperf;
2438 cpu->sample.mperf = mperf;
2439 cpu->sample.tsc = tsc;
2440 cpu->sample.aperf -= cpu->prev_aperf;
2441 cpu->sample.mperf -= cpu->prev_mperf;
2442 cpu->sample.tsc -= cpu->prev_tsc;
2443
2444 cpu->prev_aperf = aperf;
2445 cpu->prev_mperf = mperf;
2446 cpu->prev_tsc = tsc;
2447 /*
2448 * First time this function is invoked in a given cycle, all of the
2449 * previous sample data fields are equal to zero or stale and they must
2450 * be populated with meaningful numbers for things to work, so assume
2451 * that sample.time will always be reset before setting the utilization
2452 * update hook and make the caller skip the sample then.
2453 */
2454 if (cpu->last_sample_time) {
2455 intel_pstate_calc_avg_perf(cpu);
2456 return true;
2457 }
2458 return false;
2459}
2460
2461static inline int32_t get_avg_frequency(struct cpudata *cpu)
2462{
2463 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2464}
2465
2466static inline int32_t get_avg_pstate(struct cpudata *cpu)
2467{
2468 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2469 cpu->sample.core_avg_perf);
2470}
2471
2472static inline int32_t get_target_pstate(struct cpudata *cpu)
2473{
2474 struct sample *sample = &cpu->sample;
2475 int32_t busy_frac;
2476 int target, avg_pstate;
2477
2478 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2479 sample->tsc);
2480
2481 if (busy_frac < cpu->iowait_boost)
2482 busy_frac = cpu->iowait_boost;
2483
2484 sample->busy_scaled = busy_frac * 100;
2485
2486 target = READ_ONCE(global.no_turbo) ?
2487 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2488 target += target >> 2;
2489 target = mul_fp(target, busy_frac);
2490 if (target < cpu->pstate.min_pstate)
2491 target = cpu->pstate.min_pstate;
2492
2493 /*
2494 * If the average P-state during the previous cycle was higher than the
2495 * current target, add 50% of the difference to the target to reduce
2496 * possible performance oscillations and offset possible performance
2497 * loss related to moving the workload from one CPU to another within
2498 * a package/module.
2499 */
2500 avg_pstate = get_avg_pstate(cpu);
2501 if (avg_pstate > target)
2502 target += (avg_pstate - target) >> 1;
2503
2504 return target;
2505}
2506
2507static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2508{
2509 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2510 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2511
2512 return clamp_t(int, pstate, min_pstate, max_pstate);
2513}
2514
2515static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2516{
2517 if (pstate == cpu->pstate.current_pstate)
2518 return;
2519
2520 cpu->pstate.current_pstate = pstate;
2521 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2522}
2523
2524static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2525{
2526 int from = cpu->pstate.current_pstate;
2527 struct sample *sample;
2528 int target_pstate;
2529
2530 target_pstate = get_target_pstate(cpu);
2531 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2532 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2533 intel_pstate_update_pstate(cpu, target_pstate);
2534
2535 sample = &cpu->sample;
2536 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2537 fp_toint(sample->busy_scaled),
2538 from,
2539 cpu->pstate.current_pstate,
2540 sample->mperf,
2541 sample->aperf,
2542 sample->tsc,
2543 get_avg_frequency(cpu),
2544 fp_toint(cpu->iowait_boost * 100));
2545}
2546
2547static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2548 unsigned int flags)
2549{
2550 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2551 u64 delta_ns;
2552
2553 /* Don't allow remote callbacks */
2554 if (smp_processor_id() != cpu->cpu)
2555 return;
2556
2557 delta_ns = time - cpu->last_update;
2558 if (flags & SCHED_CPUFREQ_IOWAIT) {
2559 /* Start over if the CPU may have been idle. */
2560 if (delta_ns > TICK_NSEC) {
2561 cpu->iowait_boost = ONE_EIGHTH_FP;
2562 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2563 cpu->iowait_boost <<= 1;
2564 if (cpu->iowait_boost > int_tofp(1))
2565 cpu->iowait_boost = int_tofp(1);
2566 } else {
2567 cpu->iowait_boost = ONE_EIGHTH_FP;
2568 }
2569 } else if (cpu->iowait_boost) {
2570 /* Clear iowait_boost if the CPU may have been idle. */
2571 if (delta_ns > TICK_NSEC)
2572 cpu->iowait_boost = 0;
2573 else
2574 cpu->iowait_boost >>= 1;
2575 }
2576 cpu->last_update = time;
2577 delta_ns = time - cpu->sample.time;
2578 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2579 return;
2580
2581 if (intel_pstate_sample(cpu, time))
2582 intel_pstate_adjust_pstate(cpu);
2583}
2584
2585static struct pstate_funcs core_funcs = {
2586 .get_max = core_get_max_pstate,
2587 .get_max_physical = core_get_max_pstate_physical,
2588 .get_min = core_get_min_pstate,
2589 .get_turbo = core_get_turbo_pstate,
2590 .get_scaling = core_get_scaling,
2591 .get_val = core_get_val,
2592};
2593
2594static const struct pstate_funcs silvermont_funcs = {
2595 .get_max = atom_get_max_pstate,
2596 .get_max_physical = atom_get_max_pstate,
2597 .get_min = atom_get_min_pstate,
2598 .get_turbo = atom_get_turbo_pstate,
2599 .get_val = atom_get_val,
2600 .get_scaling = silvermont_get_scaling,
2601 .get_vid = atom_get_vid,
2602};
2603
2604static const struct pstate_funcs airmont_funcs = {
2605 .get_max = atom_get_max_pstate,
2606 .get_max_physical = atom_get_max_pstate,
2607 .get_min = atom_get_min_pstate,
2608 .get_turbo = atom_get_turbo_pstate,
2609 .get_val = atom_get_val,
2610 .get_scaling = airmont_get_scaling,
2611 .get_vid = atom_get_vid,
2612};
2613
2614static const struct pstate_funcs knl_funcs = {
2615 .get_max = core_get_max_pstate,
2616 .get_max_physical = core_get_max_pstate_physical,
2617 .get_min = core_get_min_pstate,
2618 .get_turbo = knl_get_turbo_pstate,
2619 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2620 .get_scaling = core_get_scaling,
2621 .get_val = core_get_val,
2622};
2623
2624#define X86_MATCH(vfm, policy) \
2625 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy)
2626
2627static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2628 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs),
2629 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs),
2630 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs),
2631 X86_MATCH(INTEL_IVYBRIDGE, core_funcs),
2632 X86_MATCH(INTEL_HASWELL, core_funcs),
2633 X86_MATCH(INTEL_BROADWELL, core_funcs),
2634 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs),
2635 X86_MATCH(INTEL_HASWELL_X, core_funcs),
2636 X86_MATCH(INTEL_HASWELL_L, core_funcs),
2637 X86_MATCH(INTEL_HASWELL_G, core_funcs),
2638 X86_MATCH(INTEL_BROADWELL_G, core_funcs),
2639 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs),
2640 X86_MATCH(INTEL_SKYLAKE_L, core_funcs),
2641 X86_MATCH(INTEL_BROADWELL_X, core_funcs),
2642 X86_MATCH(INTEL_SKYLAKE, core_funcs),
2643 X86_MATCH(INTEL_BROADWELL_D, core_funcs),
2644 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs),
2645 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs),
2646 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs),
2647 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs),
2648 X86_MATCH(INTEL_SKYLAKE_X, core_funcs),
2649 X86_MATCH(INTEL_COMETLAKE, core_funcs),
2650 X86_MATCH(INTEL_ICELAKE_X, core_funcs),
2651 X86_MATCH(INTEL_TIGERLAKE, core_funcs),
2652 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs),
2653 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs),
2654 {}
2655};
2656MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2657
2658#ifdef CONFIG_ACPI
2659static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2660 X86_MATCH(INTEL_BROADWELL_D, core_funcs),
2661 X86_MATCH(INTEL_BROADWELL_X, core_funcs),
2662 X86_MATCH(INTEL_SKYLAKE_X, core_funcs),
2663 X86_MATCH(INTEL_ICELAKE_X, core_funcs),
2664 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs),
2665 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs),
2666 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs),
2667 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs),
2668 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs),
2669 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs),
2670 {}
2671};
2672#endif
2673
2674static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2675 X86_MATCH(INTEL_KABYLAKE, core_funcs),
2676 {}
2677};
2678
2679static int intel_pstate_init_cpu(unsigned int cpunum)
2680{
2681 struct cpudata *cpu;
2682
2683 cpu = all_cpu_data[cpunum];
2684
2685 if (!cpu) {
2686 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2687 if (!cpu)
2688 return -ENOMEM;
2689
2690 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2691
2692 cpu->cpu = cpunum;
2693
2694 cpu->epp_default = -EINVAL;
2695
2696 if (hwp_active) {
2697 intel_pstate_hwp_enable(cpu);
2698
2699 if (intel_pstate_acpi_pm_profile_server())
2700 hwp_boost = true;
2701 }
2702 } else if (hwp_active) {
2703 /*
2704 * Re-enable HWP in case this happens after a resume from ACPI
2705 * S3 if the CPU was offline during the whole system/resume
2706 * cycle.
2707 */
2708 intel_pstate_hwp_reenable(cpu);
2709 }
2710
2711 cpu->epp_powersave = -EINVAL;
2712 cpu->epp_policy = 0;
2713
2714 intel_pstate_get_cpu_pstates(cpu);
2715
2716 pr_debug("controlling: cpu %d\n", cpunum);
2717
2718 return 0;
2719}
2720
2721static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2722{
2723 struct cpudata *cpu = all_cpu_data[cpu_num];
2724
2725 if (hwp_active && !hwp_boost)
2726 return;
2727
2728 if (cpu->update_util_set)
2729 return;
2730
2731 /* Prevent intel_pstate_update_util() from using stale data. */
2732 cpu->sample.time = 0;
2733 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2734 (hwp_active ?
2735 intel_pstate_update_util_hwp :
2736 intel_pstate_update_util));
2737 cpu->update_util_set = true;
2738}
2739
2740static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2741{
2742 struct cpudata *cpu_data = all_cpu_data[cpu];
2743
2744 if (!cpu_data->update_util_set)
2745 return;
2746
2747 cpufreq_remove_update_util_hook(cpu);
2748 cpu_data->update_util_set = false;
2749 synchronize_rcu();
2750}
2751
2752static int intel_pstate_get_max_freq(struct cpudata *cpu)
2753{
2754 return READ_ONCE(global.no_turbo) ?
2755 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2756}
2757
2758static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2759 unsigned int policy_min,
2760 unsigned int policy_max)
2761{
2762 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2763 int32_t max_policy_perf, min_policy_perf;
2764
2765 max_policy_perf = policy_max / perf_ctl_scaling;
2766 if (policy_max == policy_min) {
2767 min_policy_perf = max_policy_perf;
2768 } else {
2769 min_policy_perf = policy_min / perf_ctl_scaling;
2770 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2771 0, max_policy_perf);
2772 }
2773
2774 /*
2775 * HWP needs some special consideration, because HWP_REQUEST uses
2776 * abstract values to represent performance rather than pure ratios.
2777 */
2778 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2779 int freq;
2780
2781 freq = max_policy_perf * perf_ctl_scaling;
2782 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2783 freq = min_policy_perf * perf_ctl_scaling;
2784 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2785 }
2786
2787 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2788 cpu->cpu, min_policy_perf, max_policy_perf);
2789
2790 /* Normalize user input to [min_perf, max_perf] */
2791 if (per_cpu_limits) {
2792 cpu->min_perf_ratio = min_policy_perf;
2793 cpu->max_perf_ratio = max_policy_perf;
2794 } else {
2795 int turbo_max = cpu->pstate.turbo_pstate;
2796 int32_t global_min, global_max;
2797
2798 /* Global limits are in percent of the maximum turbo P-state. */
2799 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2800 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2801 global_min = clamp_t(int32_t, global_min, 0, global_max);
2802
2803 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2804 global_min, global_max);
2805
2806 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2807 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2808 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2809 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2810
2811 /* Make sure min_perf <= max_perf */
2812 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2813 cpu->max_perf_ratio);
2814
2815 }
2816 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2817 cpu->max_perf_ratio,
2818 cpu->min_perf_ratio);
2819}
2820
2821static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2822{
2823 struct cpudata *cpu;
2824
2825 if (!policy->cpuinfo.max_freq)
2826 return -ENODEV;
2827
2828 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2829 policy->cpuinfo.max_freq, policy->max);
2830
2831 cpu = all_cpu_data[policy->cpu];
2832 cpu->policy = policy->policy;
2833
2834 mutex_lock(&intel_pstate_limits_lock);
2835
2836 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2837
2838 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2839 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2840
2841 /*
2842 * NOHZ_FULL CPUs need this as the governor callback may not
2843 * be invoked on them.
2844 */
2845 intel_pstate_clear_update_util_hook(policy->cpu);
2846 intel_pstate_set_pstate(cpu, pstate);
2847 } else {
2848 intel_pstate_set_update_util_hook(policy->cpu);
2849 }
2850
2851 if (hwp_active) {
2852 /*
2853 * When hwp_boost was active before and dynamically it
2854 * was turned off, in that case we need to clear the
2855 * update util hook.
2856 */
2857 if (!hwp_boost)
2858 intel_pstate_clear_update_util_hook(policy->cpu);
2859 intel_pstate_hwp_set(policy->cpu);
2860 }
2861 /*
2862 * policy->cur is never updated with the intel_pstate driver, but it
2863 * is used as a stale frequency value. So, keep it within limits.
2864 */
2865 policy->cur = policy->min;
2866
2867 mutex_unlock(&intel_pstate_limits_lock);
2868
2869 return 0;
2870}
2871
2872static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2873 struct cpufreq_policy_data *policy)
2874{
2875 if (!hwp_active &&
2876 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2877 policy->max < policy->cpuinfo.max_freq &&
2878 policy->max > cpu->pstate.max_freq) {
2879 pr_debug("policy->max > max non turbo frequency\n");
2880 policy->max = policy->cpuinfo.max_freq;
2881 }
2882}
2883
2884static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2885 struct cpufreq_policy_data *policy)
2886{
2887 int max_freq;
2888
2889 if (hwp_active) {
2890 intel_pstate_get_hwp_cap(cpu);
2891 max_freq = READ_ONCE(global.no_turbo) ?
2892 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2893 } else {
2894 max_freq = intel_pstate_get_max_freq(cpu);
2895 }
2896 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2897
2898 intel_pstate_adjust_policy_max(cpu, policy);
2899}
2900
2901static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2902{
2903 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2904
2905 return 0;
2906}
2907
2908static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2909{
2910 struct cpudata *cpu = all_cpu_data[policy->cpu];
2911
2912 pr_debug("CPU %d going offline\n", cpu->cpu);
2913
2914 if (cpu->suspended)
2915 return 0;
2916
2917 /*
2918 * If the CPU is an SMT thread and it goes offline with the performance
2919 * settings different from the minimum, it will prevent its sibling
2920 * from getting to lower performance levels, so force the minimum
2921 * performance on CPU offline to prevent that from happening.
2922 */
2923 if (hwp_active)
2924 intel_pstate_hwp_offline(cpu);
2925 else
2926 intel_pstate_set_min_pstate(cpu);
2927
2928 intel_pstate_exit_perf_limits(policy);
2929
2930 return 0;
2931}
2932
2933static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2934{
2935 struct cpudata *cpu = all_cpu_data[policy->cpu];
2936
2937 pr_debug("CPU %d going online\n", cpu->cpu);
2938
2939 intel_pstate_init_acpi_perf_limits(policy);
2940
2941 if (hwp_active) {
2942 /*
2943 * Re-enable HWP and clear the "suspended" flag to let "resume"
2944 * know that it need not do that.
2945 */
2946 intel_pstate_hwp_reenable(cpu);
2947 cpu->suspended = false;
2948
2949 hybrid_update_capacity(cpu);
2950 }
2951
2952 return 0;
2953}
2954
2955static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2956{
2957 intel_pstate_clear_update_util_hook(policy->cpu);
2958
2959 return intel_cpufreq_cpu_offline(policy);
2960}
2961
2962static void intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2963{
2964 pr_debug("CPU %d exiting\n", policy->cpu);
2965
2966 policy->fast_switch_possible = false;
2967}
2968
2969static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2970{
2971 struct cpudata *cpu;
2972 int rc;
2973
2974 rc = intel_pstate_init_cpu(policy->cpu);
2975 if (rc)
2976 return rc;
2977
2978 cpu = all_cpu_data[policy->cpu];
2979
2980 cpu->max_perf_ratio = 0xFF;
2981 cpu->min_perf_ratio = 0;
2982
2983 /* cpuinfo and default policy values */
2984 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2985 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
2986 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2987
2988 policy->min = policy->cpuinfo.min_freq;
2989 policy->max = policy->cpuinfo.max_freq;
2990
2991 intel_pstate_init_acpi_perf_limits(policy);
2992
2993 policy->fast_switch_possible = true;
2994
2995 return 0;
2996}
2997
2998static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2999{
3000 int ret = __intel_pstate_cpu_init(policy);
3001
3002 if (ret)
3003 return ret;
3004
3005 /*
3006 * Set the policy to powersave to provide a valid fallback value in case
3007 * the default cpufreq governor is neither powersave nor performance.
3008 */
3009 policy->policy = CPUFREQ_POLICY_POWERSAVE;
3010
3011 if (hwp_active) {
3012 struct cpudata *cpu = all_cpu_data[policy->cpu];
3013
3014 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
3015 }
3016
3017 return 0;
3018}
3019
3020static struct cpufreq_driver intel_pstate = {
3021 .flags = CPUFREQ_CONST_LOOPS,
3022 .verify = intel_pstate_verify_policy,
3023 .setpolicy = intel_pstate_set_policy,
3024 .suspend = intel_pstate_suspend,
3025 .resume = intel_pstate_resume,
3026 .init = intel_pstate_cpu_init,
3027 .exit = intel_pstate_cpu_exit,
3028 .offline = intel_pstate_cpu_offline,
3029 .online = intel_pstate_cpu_online,
3030 .update_limits = intel_pstate_update_limits,
3031 .name = "intel_pstate",
3032};
3033
3034static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
3035{
3036 struct cpudata *cpu = all_cpu_data[policy->cpu];
3037
3038 intel_pstate_verify_cpu_policy(cpu, policy);
3039 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
3040
3041 return 0;
3042}
3043
3044/* Use of trace in passive mode:
3045 *
3046 * In passive mode the trace core_busy field (also known as the
3047 * performance field, and lablelled as such on the graphs; also known as
3048 * core_avg_perf) is not needed and so is re-assigned to indicate if the
3049 * driver call was via the normal or fast switch path. Various graphs
3050 * output from the intel_pstate_tracer.py utility that include core_busy
3051 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
3052 * so we use 10 to indicate the normal path through the driver, and
3053 * 90 to indicate the fast switch path through the driver.
3054 * The scaled_busy field is not used, and is set to 0.
3055 */
3056
3057#define INTEL_PSTATE_TRACE_TARGET 10
3058#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
3059
3060static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
3061{
3062 struct sample *sample;
3063
3064 if (!trace_pstate_sample_enabled())
3065 return;
3066
3067 if (!intel_pstate_sample(cpu, ktime_get()))
3068 return;
3069
3070 sample = &cpu->sample;
3071 trace_pstate_sample(trace_type,
3072 0,
3073 old_pstate,
3074 cpu->pstate.current_pstate,
3075 sample->mperf,
3076 sample->aperf,
3077 sample->tsc,
3078 get_avg_frequency(cpu),
3079 fp_toint(cpu->iowait_boost * 100));
3080}
3081
3082static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
3083 u32 desired, bool fast_switch)
3084{
3085 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
3086
3087 value &= ~HWP_MIN_PERF(~0L);
3088 value |= HWP_MIN_PERF(min);
3089
3090 value &= ~HWP_MAX_PERF(~0L);
3091 value |= HWP_MAX_PERF(max);
3092
3093 value &= ~HWP_DESIRED_PERF(~0L);
3094 value |= HWP_DESIRED_PERF(desired);
3095
3096 if (value == prev)
3097 return;
3098
3099 WRITE_ONCE(cpu->hwp_req_cached, value);
3100 if (fast_switch)
3101 wrmsrl(MSR_HWP_REQUEST, value);
3102 else
3103 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3104}
3105
3106static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
3107 u32 target_pstate, bool fast_switch)
3108{
3109 if (fast_switch)
3110 wrmsrl(MSR_IA32_PERF_CTL,
3111 pstate_funcs.get_val(cpu, target_pstate));
3112 else
3113 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
3114 pstate_funcs.get_val(cpu, target_pstate));
3115}
3116
3117static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
3118 int target_pstate, bool fast_switch)
3119{
3120 struct cpudata *cpu = all_cpu_data[policy->cpu];
3121 int old_pstate = cpu->pstate.current_pstate;
3122
3123 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
3124 if (hwp_active) {
3125 int max_pstate = policy->strict_target ?
3126 target_pstate : cpu->max_perf_ratio;
3127
3128 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
3129 fast_switch);
3130 } else if (target_pstate != old_pstate) {
3131 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
3132 }
3133
3134 cpu->pstate.current_pstate = target_pstate;
3135
3136 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
3137 INTEL_PSTATE_TRACE_TARGET, old_pstate);
3138
3139 return target_pstate;
3140}
3141
3142static int intel_cpufreq_target(struct cpufreq_policy *policy,
3143 unsigned int target_freq,
3144 unsigned int relation)
3145{
3146 struct cpudata *cpu = all_cpu_data[policy->cpu];
3147 struct cpufreq_freqs freqs;
3148 int target_pstate;
3149
3150 freqs.old = policy->cur;
3151 freqs.new = target_freq;
3152
3153 cpufreq_freq_transition_begin(policy, &freqs);
3154
3155 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
3156 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
3157
3158 freqs.new = target_pstate * cpu->pstate.scaling;
3159
3160 cpufreq_freq_transition_end(policy, &freqs, false);
3161
3162 return 0;
3163}
3164
3165static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
3166 unsigned int target_freq)
3167{
3168 struct cpudata *cpu = all_cpu_data[policy->cpu];
3169 int target_pstate;
3170
3171 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
3172
3173 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
3174
3175 return target_pstate * cpu->pstate.scaling;
3176}
3177
3178static void intel_cpufreq_adjust_perf(unsigned int cpunum,
3179 unsigned long min_perf,
3180 unsigned long target_perf,
3181 unsigned long capacity)
3182{
3183 struct cpudata *cpu = all_cpu_data[cpunum];
3184 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
3185 int old_pstate = cpu->pstate.current_pstate;
3186 int cap_pstate, min_pstate, max_pstate, target_pstate;
3187
3188 cap_pstate = READ_ONCE(global.no_turbo) ?
3189 HWP_GUARANTEED_PERF(hwp_cap) :
3190 HWP_HIGHEST_PERF(hwp_cap);
3191
3192 /* Optimization: Avoid unnecessary divisions. */
3193
3194 target_pstate = cap_pstate;
3195 if (target_perf < capacity)
3196 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
3197
3198 min_pstate = cap_pstate;
3199 if (min_perf < capacity)
3200 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
3201
3202 if (min_pstate < cpu->pstate.min_pstate)
3203 min_pstate = cpu->pstate.min_pstate;
3204
3205 if (min_pstate < cpu->min_perf_ratio)
3206 min_pstate = cpu->min_perf_ratio;
3207
3208 if (min_pstate > cpu->max_perf_ratio)
3209 min_pstate = cpu->max_perf_ratio;
3210
3211 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
3212 if (max_pstate < min_pstate)
3213 max_pstate = min_pstate;
3214
3215 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
3216
3217 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
3218
3219 cpu->pstate.current_pstate = target_pstate;
3220 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3221}
3222
3223static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3224{
3225 struct freq_qos_request *req;
3226 struct cpudata *cpu;
3227 struct device *dev;
3228 int ret, freq;
3229
3230 dev = get_cpu_device(policy->cpu);
3231 if (!dev)
3232 return -ENODEV;
3233
3234 ret = __intel_pstate_cpu_init(policy);
3235 if (ret)
3236 return ret;
3237
3238 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3239 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3240 policy->cur = policy->cpuinfo.min_freq;
3241
3242 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3243 if (!req) {
3244 ret = -ENOMEM;
3245 goto pstate_exit;
3246 }
3247
3248 cpu = all_cpu_data[policy->cpu];
3249
3250 if (hwp_active) {
3251 u64 value;
3252
3253 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3254
3255 intel_pstate_get_hwp_cap(cpu);
3256
3257 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3258 WRITE_ONCE(cpu->hwp_req_cached, value);
3259
3260 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3261 } else {
3262 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3263 }
3264
3265 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3266
3267 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3268 freq);
3269 if (ret < 0) {
3270 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3271 goto free_req;
3272 }
3273
3274 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3275
3276 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3277 freq);
3278 if (ret < 0) {
3279 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3280 goto remove_min_req;
3281 }
3282
3283 policy->driver_data = req;
3284
3285 return 0;
3286
3287remove_min_req:
3288 freq_qos_remove_request(req);
3289free_req:
3290 kfree(req);
3291pstate_exit:
3292 intel_pstate_exit_perf_limits(policy);
3293
3294 return ret;
3295}
3296
3297static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3298{
3299 struct freq_qos_request *req;
3300
3301 req = policy->driver_data;
3302
3303 freq_qos_remove_request(req + 1);
3304 freq_qos_remove_request(req);
3305 kfree(req);
3306
3307 intel_pstate_cpu_exit(policy);
3308}
3309
3310static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3311{
3312 intel_pstate_suspend(policy);
3313
3314 if (hwp_active) {
3315 struct cpudata *cpu = all_cpu_data[policy->cpu];
3316 u64 value = READ_ONCE(cpu->hwp_req_cached);
3317
3318 /*
3319 * Clear the desired perf field in MSR_HWP_REQUEST in case
3320 * intel_cpufreq_adjust_perf() is in use and the last value
3321 * written by it may not be suitable.
3322 */
3323 value &= ~HWP_DESIRED_PERF(~0L);
3324 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3325 WRITE_ONCE(cpu->hwp_req_cached, value);
3326 }
3327
3328 return 0;
3329}
3330
3331static struct cpufreq_driver intel_cpufreq = {
3332 .flags = CPUFREQ_CONST_LOOPS,
3333 .verify = intel_cpufreq_verify_policy,
3334 .target = intel_cpufreq_target,
3335 .fast_switch = intel_cpufreq_fast_switch,
3336 .init = intel_cpufreq_cpu_init,
3337 .exit = intel_cpufreq_cpu_exit,
3338 .offline = intel_cpufreq_cpu_offline,
3339 .online = intel_pstate_cpu_online,
3340 .suspend = intel_cpufreq_suspend,
3341 .resume = intel_pstate_resume,
3342 .update_limits = intel_pstate_update_limits,
3343 .name = "intel_cpufreq",
3344};
3345
3346static struct cpufreq_driver *default_driver;
3347
3348static void intel_pstate_driver_cleanup(void)
3349{
3350 unsigned int cpu;
3351
3352 cpus_read_lock();
3353 for_each_online_cpu(cpu) {
3354 if (all_cpu_data[cpu]) {
3355 if (intel_pstate_driver == &intel_pstate)
3356 intel_pstate_clear_update_util_hook(cpu);
3357
3358 kfree(all_cpu_data[cpu]);
3359 WRITE_ONCE(all_cpu_data[cpu], NULL);
3360 }
3361 }
3362 cpus_read_unlock();
3363
3364 intel_pstate_driver = NULL;
3365}
3366
3367static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3368{
3369 bool refresh_cpu_cap_scaling;
3370 int ret;
3371
3372 if (driver == &intel_pstate)
3373 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3374
3375 memset(&global, 0, sizeof(global));
3376 global.max_perf_pct = 100;
3377 global.turbo_disabled = turbo_is_disabled();
3378 global.no_turbo = global.turbo_disabled;
3379
3380 arch_set_max_freq_ratio(global.turbo_disabled);
3381
3382 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu();
3383
3384 intel_pstate_driver = driver;
3385 ret = cpufreq_register_driver(intel_pstate_driver);
3386 if (ret) {
3387 intel_pstate_driver_cleanup();
3388 return ret;
3389 }
3390
3391 global.min_perf_pct = min_perf_pct_min();
3392
3393 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling);
3394
3395 return 0;
3396}
3397
3398static ssize_t intel_pstate_show_status(char *buf)
3399{
3400 if (!intel_pstate_driver)
3401 return sprintf(buf, "off\n");
3402
3403 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3404 "active" : "passive");
3405}
3406
3407static int intel_pstate_update_status(const char *buf, size_t size)
3408{
3409 if (size == 3 && !strncmp(buf, "off", size)) {
3410 if (!intel_pstate_driver)
3411 return -EINVAL;
3412
3413 if (hwp_active)
3414 return -EBUSY;
3415
3416 cpufreq_unregister_driver(intel_pstate_driver);
3417 intel_pstate_driver_cleanup();
3418 return 0;
3419 }
3420
3421 if (size == 6 && !strncmp(buf, "active", size)) {
3422 if (intel_pstate_driver) {
3423 if (intel_pstate_driver == &intel_pstate)
3424 return 0;
3425
3426 cpufreq_unregister_driver(intel_pstate_driver);
3427 }
3428
3429 return intel_pstate_register_driver(&intel_pstate);
3430 }
3431
3432 if (size == 7 && !strncmp(buf, "passive", size)) {
3433 if (intel_pstate_driver) {
3434 if (intel_pstate_driver == &intel_cpufreq)
3435 return 0;
3436
3437 cpufreq_unregister_driver(intel_pstate_driver);
3438 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3439 }
3440
3441 return intel_pstate_register_driver(&intel_cpufreq);
3442 }
3443
3444 return -EINVAL;
3445}
3446
3447static int no_load __initdata;
3448static int no_hwp __initdata;
3449static int hwp_only __initdata;
3450static unsigned int force_load __initdata;
3451
3452static int __init intel_pstate_msrs_not_valid(void)
3453{
3454 if (!pstate_funcs.get_max(0) ||
3455 !pstate_funcs.get_min(0) ||
3456 !pstate_funcs.get_turbo(0))
3457 return -ENODEV;
3458
3459 return 0;
3460}
3461
3462static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3463{
3464 pstate_funcs.get_max = funcs->get_max;
3465 pstate_funcs.get_max_physical = funcs->get_max_physical;
3466 pstate_funcs.get_min = funcs->get_min;
3467 pstate_funcs.get_turbo = funcs->get_turbo;
3468 pstate_funcs.get_scaling = funcs->get_scaling;
3469 pstate_funcs.get_val = funcs->get_val;
3470 pstate_funcs.get_vid = funcs->get_vid;
3471 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3472}
3473
3474#ifdef CONFIG_ACPI
3475
3476static bool __init intel_pstate_no_acpi_pss(void)
3477{
3478 int i;
3479
3480 for_each_possible_cpu(i) {
3481 acpi_status status;
3482 union acpi_object *pss;
3483 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3484 struct acpi_processor *pr = per_cpu(processors, i);
3485
3486 if (!pr)
3487 continue;
3488
3489 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3490 if (ACPI_FAILURE(status))
3491 continue;
3492
3493 pss = buffer.pointer;
3494 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3495 kfree(pss);
3496 return false;
3497 }
3498
3499 kfree(pss);
3500 }
3501
3502 pr_debug("ACPI _PSS not found\n");
3503 return true;
3504}
3505
3506static bool __init intel_pstate_no_acpi_pcch(void)
3507{
3508 acpi_status status;
3509 acpi_handle handle;
3510
3511 status = acpi_get_handle(NULL, "\\_SB", &handle);
3512 if (ACPI_FAILURE(status))
3513 goto not_found;
3514
3515 if (acpi_has_method(handle, "PCCH"))
3516 return false;
3517
3518not_found:
3519 pr_debug("ACPI PCCH not found\n");
3520 return true;
3521}
3522
3523static bool __init intel_pstate_has_acpi_ppc(void)
3524{
3525 int i;
3526
3527 for_each_possible_cpu(i) {
3528 struct acpi_processor *pr = per_cpu(processors, i);
3529
3530 if (!pr)
3531 continue;
3532 if (acpi_has_method(pr->handle, "_PPC"))
3533 return true;
3534 }
3535 pr_debug("ACPI _PPC not found\n");
3536 return false;
3537}
3538
3539enum {
3540 PSS,
3541 PPC,
3542};
3543
3544/* Hardware vendor-specific info that has its own power management modes */
3545static struct acpi_platform_list plat_info[] __initdata = {
3546 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3547 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3548 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3549 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3550 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3551 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3552 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3553 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3554 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3555 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3556 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3557 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3558 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3559 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3560 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3561 { } /* End */
3562};
3563
3564#define BITMASK_OOB (BIT(8) | BIT(18))
3565
3566static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3567{
3568 const struct x86_cpu_id *id;
3569 u64 misc_pwr;
3570 int idx;
3571
3572 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3573 if (id) {
3574 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3575 if (misc_pwr & BITMASK_OOB) {
3576 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3577 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3578 return true;
3579 }
3580 }
3581
3582 idx = acpi_match_platform_list(plat_info);
3583 if (idx < 0)
3584 return false;
3585
3586 switch (plat_info[idx].data) {
3587 case PSS:
3588 if (!intel_pstate_no_acpi_pss())
3589 return false;
3590
3591 return intel_pstate_no_acpi_pcch();
3592 case PPC:
3593 return intel_pstate_has_acpi_ppc() && !force_load;
3594 }
3595
3596 return false;
3597}
3598
3599static void intel_pstate_request_control_from_smm(void)
3600{
3601 /*
3602 * It may be unsafe to request P-states control from SMM if _PPC support
3603 * has not been enabled.
3604 */
3605 if (acpi_ppc)
3606 acpi_processor_pstate_control();
3607}
3608#else /* CONFIG_ACPI not enabled */
3609static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3610static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3611static inline void intel_pstate_request_control_from_smm(void) {}
3612#endif /* CONFIG_ACPI */
3613
3614#define INTEL_PSTATE_HWP_BROADWELL 0x01
3615
3616#define X86_MATCH_HWP(vfm, hwp_mode) \
3617 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode)
3618
3619static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3620 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3621 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3622 X86_MATCH_HWP(INTEL_ANY, 0),
3623 {}
3624};
3625
3626static bool intel_pstate_hwp_is_enabled(void)
3627{
3628 u64 value;
3629
3630 rdmsrl(MSR_PM_ENABLE, value);
3631 return !!(value & 0x1);
3632}
3633
3634#define POWERSAVE_MASK GENMASK(7, 0)
3635#define BALANCE_POWER_MASK GENMASK(15, 8)
3636#define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3637#define PERFORMANCE_MASK GENMASK(31, 24)
3638
3639#define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3640 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3641 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3642 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3643 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3644
3645#define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3646 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3647 balance_perf, HWP_EPP_PERFORMANCE))
3648
3649static const struct x86_cpu_id intel_epp_default[] = {
3650 /*
3651 * Set EPP value as 102, this is the max suggested EPP
3652 * which can result in one core turbo frequency for
3653 * AlderLake Mobile CPUs.
3654 */
3655 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3656 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3657 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3658 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3659 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3660 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3661 179, 64, 16)),
3662 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3663 179, 64, 16)),
3664 {}
3665};
3666
3667static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3668 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3669 X86_MATCH_VFM(INTEL_ARROWLAKE, HYBRID_SCALING_FACTOR_MTL),
3670 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL),
3671 {}
3672};
3673
3674static int __init intel_pstate_init(void)
3675{
3676 static struct cpudata **_all_cpu_data;
3677 const struct x86_cpu_id *id;
3678 int rc;
3679
3680 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3681 return -ENODEV;
3682
3683 id = x86_match_cpu(hwp_support_ids);
3684 if (id) {
3685 hwp_forced = intel_pstate_hwp_is_enabled();
3686
3687 if (hwp_forced)
3688 pr_info("HWP enabled by BIOS\n");
3689 else if (no_load)
3690 return -ENODEV;
3691
3692 copy_cpu_funcs(&core_funcs);
3693 /*
3694 * Avoid enabling HWP for processors without EPP support,
3695 * because that means incomplete HWP implementation which is a
3696 * corner case and supporting it is generally problematic.
3697 *
3698 * If HWP is enabled already, though, there is no choice but to
3699 * deal with it.
3700 */
3701 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3702 hwp_active = true;
3703 hwp_mode_bdw = id->driver_data;
3704 intel_pstate.attr = hwp_cpufreq_attrs;
3705 intel_cpufreq.attr = hwp_cpufreq_attrs;
3706 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3707 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3708 if (!default_driver)
3709 default_driver = &intel_pstate;
3710
3711 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3712
3713 goto hwp_cpu_matched;
3714 }
3715 pr_info("HWP not enabled\n");
3716 } else {
3717 if (no_load)
3718 return -ENODEV;
3719
3720 id = x86_match_cpu(intel_pstate_cpu_ids);
3721 if (!id) {
3722 pr_info("CPU model not supported\n");
3723 return -ENODEV;
3724 }
3725
3726 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3727 }
3728
3729 if (intel_pstate_msrs_not_valid()) {
3730 pr_info("Invalid MSRs\n");
3731 return -ENODEV;
3732 }
3733 /* Without HWP start in the passive mode. */
3734 if (!default_driver)
3735 default_driver = &intel_cpufreq;
3736
3737hwp_cpu_matched:
3738 /*
3739 * The Intel pstate driver will be ignored if the platform
3740 * firmware has its own power management modes.
3741 */
3742 if (intel_pstate_platform_pwr_mgmt_exists()) {
3743 pr_info("P-states controlled by the platform\n");
3744 return -ENODEV;
3745 }
3746
3747 if (!hwp_active && hwp_only)
3748 return -ENOTSUPP;
3749
3750 pr_info("Intel P-state driver initializing\n");
3751
3752 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3753 if (!_all_cpu_data)
3754 return -ENOMEM;
3755
3756 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3757
3758 intel_pstate_request_control_from_smm();
3759
3760 intel_pstate_sysfs_expose_params();
3761
3762 if (hwp_active) {
3763 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
3764 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3765
3766 if (id) {
3767 epp_values[EPP_INDEX_POWERSAVE] =
3768 FIELD_GET(POWERSAVE_MASK, id->driver_data);
3769 epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3770 FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3771 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3772 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3773 epp_values[EPP_INDEX_PERFORMANCE] =
3774 FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3775 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3776 epp_values[EPP_INDEX_POWERSAVE],
3777 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3778 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3779 epp_values[EPP_INDEX_PERFORMANCE]);
3780 }
3781
3782 if (hybrid_id) {
3783 hybrid_scaling_factor = hybrid_id->driver_data;
3784 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3785 }
3786
3787 }
3788
3789 mutex_lock(&intel_pstate_driver_lock);
3790 rc = intel_pstate_register_driver(default_driver);
3791 mutex_unlock(&intel_pstate_driver_lock);
3792 if (rc) {
3793 intel_pstate_sysfs_remove();
3794 return rc;
3795 }
3796
3797 if (hwp_active) {
3798 const struct x86_cpu_id *id;
3799
3800 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3801 if (id) {
3802 set_power_ctl_ee_state(false);
3803 pr_info("Disabling energy efficiency optimization\n");
3804 }
3805
3806 pr_info("HWP enabled\n");
3807 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3808 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3809 }
3810
3811 return 0;
3812}
3813device_initcall(intel_pstate_init);
3814
3815static int __init intel_pstate_setup(char *str)
3816{
3817 if (!str)
3818 return -EINVAL;
3819
3820 if (!strcmp(str, "disable"))
3821 no_load = 1;
3822 else if (!strcmp(str, "active"))
3823 default_driver = &intel_pstate;
3824 else if (!strcmp(str, "passive"))
3825 default_driver = &intel_cpufreq;
3826
3827 if (!strcmp(str, "no_hwp"))
3828 no_hwp = 1;
3829
3830 if (!strcmp(str, "force"))
3831 force_load = 1;
3832 if (!strcmp(str, "hwp_only"))
3833 hwp_only = 1;
3834 if (!strcmp(str, "per_cpu_perf_limits"))
3835 per_cpu_limits = true;
3836
3837#ifdef CONFIG_ACPI
3838 if (!strcmp(str, "support_acpi_ppc"))
3839 acpi_ppc = true;
3840#endif
3841
3842 return 0;
3843}
3844early_param("intel_pstate", intel_pstate_setup);
3845
3846MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3847MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");