Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek xHCI Host Controller Driver
4 *
5 * Copyright (c) 2015 MediaTek Inc.
6 * Author:
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10#include <linux/bitfield.h>
11#include <linux/dma-mapping.h>
12#include <linux/iopoll.h>
13#include <linux/kernel.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/pm_wakeirq.h>
20#include <linux/regmap.h>
21#include <linux/regulator/consumer.h>
22#include <linux/reset.h>
23
24#include "xhci.h"
25#include "xhci-mtk.h"
26
27/* ip_pw_ctrl0 register */
28#define CTRL0_IP_SW_RST BIT(0)
29
30/* ip_pw_ctrl1 register */
31#define CTRL1_IP_HOST_PDN BIT(0)
32
33/* ip_pw_ctrl2 register */
34#define CTRL2_IP_DEV_PDN BIT(0)
35
36/* ip_pw_sts1 register */
37#define STS1_IP_SLEEP_STS BIT(30)
38#define STS1_U3_MAC_RST BIT(16)
39#define STS1_XHCI_RST BIT(11)
40#define STS1_SYS125_RST BIT(10)
41#define STS1_REF_RST BIT(8)
42#define STS1_SYSPLL_STABLE BIT(0)
43
44/* ip_xhci_cap register */
45#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
46#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
47
48/* u3_ctrl_p register */
49#define CTRL_U3_PORT_HOST_SEL BIT(2)
50#define CTRL_U3_PORT_PDN BIT(1)
51#define CTRL_U3_PORT_DIS BIT(0)
52
53/* u2_ctrl_p register */
54#define CTRL_U2_PORT_HOST_SEL BIT(2)
55#define CTRL_U2_PORT_PDN BIT(1)
56#define CTRL_U2_PORT_DIS BIT(0)
57
58/* u2_phy_pll register */
59#define CTRL_U2_FORCE_PLL_STB BIT(28)
60
61/* xHCI CSR */
62#define LS_EOF_CFG 0x930
63#define LSEOF_OFFSET 0x89
64
65#define FS_EOF_CFG 0x934
66#define FSEOF_OFFSET 0x2e
67
68#define SS_GEN1_EOF_CFG 0x93c
69#define SSG1EOF_OFFSET 0x78
70
71#define HFCNTR_CFG 0x944
72#define ITP_DELTA_CLK (0xa << 1)
73#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
74#define FRMCNT_LEV1_RANG (0x12b << 8)
75#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
76
77#define HSCH_CFG1 0x960
78#define SCH3_RXFIFO_DEPTH_MASK GENMASK(21, 20)
79
80#define SS_GEN2_EOF_CFG 0x990
81#define SSG2EOF_OFFSET 0x3c
82
83#define XSEOF_OFFSET_MASK GENMASK(11, 0)
84
85/* usb remote wakeup registers in syscon */
86
87/* mt8173 etc */
88#define PERI_WK_CTRL1 0x4
89#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
90#define WC1_IS_EN BIT(25)
91#define WC1_IS_P BIT(6) /* polarity for ip sleep */
92
93/* mt8183 */
94#define PERI_WK_CTRL0 0x0
95#define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
96#define WC0_IS_P BIT(12) /* polarity */
97#define WC0_IS_EN BIT(6)
98
99/* mt8192 */
100#define WC0_SSUSB0_CDEN BIT(6)
101#define WC0_IS_SPM_EN BIT(1)
102
103/* mt8195 */
104#define PERI_WK_CTRL0_8195 0x04
105#define WC0_IS_P_95 BIT(30) /* polarity */
106#define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27))
107#define WC0_IS_EN_P3_95 BIT(26)
108#define WC0_IS_EN_P2_95 BIT(25)
109#define WC0_IS_EN_P1_95 BIT(24)
110
111#define PERI_WK_CTRL1_8195 0x20
112#define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28))
113#define WC1_IS_P_95 BIT(12)
114#define WC1_IS_EN_P0_95 BIT(6)
115
116/* mt2712 etc */
117#define PERI_SSUSB_SPM_CTRL 0x0
118#define SSC_IP_SLEEP_EN BIT(4)
119#define SSC_SPM_INT_EN BIT(1)
120
121#define SCH_FIFO_TO_KB(x) ((x) >> 10)
122
123enum ssusb_uwk_vers {
124 SSUSB_UWK_V1 = 1,
125 SSUSB_UWK_V2,
126 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
127 SSUSB_UWK_V1_2, /* specific revision 1.2 */
128 SSUSB_UWK_V1_3, /* mt8195 IP0 */
129 SSUSB_UWK_V1_4, /* mt8195 IP1 */
130 SSUSB_UWK_V1_5, /* mt8195 IP2 */
131 SSUSB_UWK_V1_6, /* mt8195 IP3 */
132};
133
134/*
135 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
136 * is calculated from the frame counter clock 24M, but in fact, the clock
137 * is 48M, add workaround for it.
138 */
139static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
140{
141 struct device *dev = mtk->dev;
142 struct usb_hcd *hcd = mtk->hcd;
143 u32 value;
144
145 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
146 return;
147
148 value = readl(hcd->regs + HFCNTR_CFG);
149 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
150 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
151 writel(value, hcd->regs + HFCNTR_CFG);
152
153 value = readl(hcd->regs + LS_EOF_CFG);
154 value &= ~XSEOF_OFFSET_MASK;
155 value |= LSEOF_OFFSET;
156 writel(value, hcd->regs + LS_EOF_CFG);
157
158 value = readl(hcd->regs + FS_EOF_CFG);
159 value &= ~XSEOF_OFFSET_MASK;
160 value |= FSEOF_OFFSET;
161 writel(value, hcd->regs + FS_EOF_CFG);
162
163 value = readl(hcd->regs + SS_GEN1_EOF_CFG);
164 value &= ~XSEOF_OFFSET_MASK;
165 value |= SSG1EOF_OFFSET;
166 writel(value, hcd->regs + SS_GEN1_EOF_CFG);
167
168 value = readl(hcd->regs + SS_GEN2_EOF_CFG);
169 value &= ~XSEOF_OFFSET_MASK;
170 value |= SSG2EOF_OFFSET;
171 writel(value, hcd->regs + SS_GEN2_EOF_CFG);
172}
173
174/*
175 * workaround: usb3.2 gen1 isoc rx hw issue
176 * host send out unexpected ACK afer device fininsh a burst transfer with
177 * a short packet.
178 */
179static void xhci_mtk_rxfifo_depth_set(struct xhci_hcd_mtk *mtk)
180{
181 struct usb_hcd *hcd = mtk->hcd;
182 u32 value;
183
184 if (!mtk->rxfifo_depth)
185 return;
186
187 value = readl(hcd->regs + HSCH_CFG1);
188 value &= ~SCH3_RXFIFO_DEPTH_MASK;
189 value |= FIELD_PREP(SCH3_RXFIFO_DEPTH_MASK,
190 SCH_FIFO_TO_KB(mtk->rxfifo_depth) - 1);
191 writel(value, hcd->regs + HSCH_CFG1);
192}
193
194static void xhci_mtk_init_quirk(struct xhci_hcd_mtk *mtk)
195{
196 /* workaround only for mt8195 */
197 xhci_mtk_set_frame_interval(mtk);
198
199 /* workaround for SoCs using SSUSB about before IPM v1.6.0 */
200 xhci_mtk_rxfifo_depth_set(mtk);
201}
202
203static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
204{
205 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
206 u32 value, check_val;
207 int u3_ports_disabled = 0;
208 int ret;
209 int i;
210
211 if (!mtk->has_ippc)
212 return 0;
213
214 /* power on host ip */
215 value = readl(&ippc->ip_pw_ctr1);
216 value &= ~CTRL1_IP_HOST_PDN;
217 writel(value, &ippc->ip_pw_ctr1);
218
219 /* power on and enable u3 ports except skipped ones */
220 for (i = 0; i < mtk->num_u3_ports; i++) {
221 if ((0x1 << i) & mtk->u3p_dis_msk) {
222 u3_ports_disabled++;
223 continue;
224 }
225
226 value = readl(&ippc->u3_ctrl_p[i]);
227 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
228 value |= CTRL_U3_PORT_HOST_SEL;
229 writel(value, &ippc->u3_ctrl_p[i]);
230 }
231
232 /* power on and enable all u2 ports except skipped ones */
233 for (i = 0; i < mtk->num_u2_ports; i++) {
234 if (BIT(i) & mtk->u2p_dis_msk)
235 continue;
236
237 value = readl(&ippc->u2_ctrl_p[i]);
238 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
239 value |= CTRL_U2_PORT_HOST_SEL;
240 writel(value, &ippc->u2_ctrl_p[i]);
241 }
242
243 /*
244 * wait for clocks to be stable, and clock domains reset to
245 * be inactive after power on and enable ports
246 */
247 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
248 STS1_SYS125_RST | STS1_XHCI_RST;
249
250 if (mtk->num_u3_ports > u3_ports_disabled)
251 check_val |= STS1_U3_MAC_RST;
252
253 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
254 (check_val == (value & check_val)), 100, 20000);
255 if (ret) {
256 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
257 return ret;
258 }
259
260 return 0;
261}
262
263static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
264{
265 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
266 u32 value;
267 int ret;
268 int i;
269
270 if (!mtk->has_ippc)
271 return 0;
272
273 /* power down u3 ports except skipped ones */
274 for (i = 0; i < mtk->num_u3_ports; i++) {
275 if ((0x1 << i) & mtk->u3p_dis_msk)
276 continue;
277
278 value = readl(&ippc->u3_ctrl_p[i]);
279 value |= CTRL_U3_PORT_PDN;
280 writel(value, &ippc->u3_ctrl_p[i]);
281 }
282
283 /* power down all u2 ports except skipped ones */
284 for (i = 0; i < mtk->num_u2_ports; i++) {
285 if (BIT(i) & mtk->u2p_dis_msk)
286 continue;
287
288 value = readl(&ippc->u2_ctrl_p[i]);
289 value |= CTRL_U2_PORT_PDN;
290 writel(value, &ippc->u2_ctrl_p[i]);
291 }
292
293 /* power down host ip */
294 value = readl(&ippc->ip_pw_ctr1);
295 value |= CTRL1_IP_HOST_PDN;
296 writel(value, &ippc->ip_pw_ctr1);
297
298 /* wait for host ip to sleep */
299 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
300 (value & STS1_IP_SLEEP_STS), 100, 100000);
301 if (ret)
302 dev_err(mtk->dev, "ip sleep failed!!!\n");
303 else /* workaound for platforms using low level latch */
304 usleep_range(100, 200);
305
306 return ret;
307}
308
309static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
310{
311 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
312 u32 value;
313
314 if (!mtk->has_ippc)
315 return 0;
316
317 /* reset whole ip */
318 value = readl(&ippc->ip_pw_ctr0);
319 value |= CTRL0_IP_SW_RST;
320 writel(value, &ippc->ip_pw_ctr0);
321 udelay(1);
322 value = readl(&ippc->ip_pw_ctr0);
323 value &= ~CTRL0_IP_SW_RST;
324 writel(value, &ippc->ip_pw_ctr0);
325
326 /*
327 * device ip is default power-on in fact
328 * power down device ip, otherwise ip-sleep will fail
329 */
330 value = readl(&ippc->ip_pw_ctr2);
331 value |= CTRL2_IP_DEV_PDN;
332 writel(value, &ippc->ip_pw_ctr2);
333
334 value = readl(&ippc->ip_xhci_cap);
335 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
336 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
337 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
338 mtk->num_u2_ports, mtk->num_u3_ports);
339
340 return xhci_mtk_host_enable(mtk);
341}
342
343/* only clocks can be turn off for ip-sleep wakeup mode */
344static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
345{
346 u32 reg, msk, val;
347
348 switch (mtk->uwk_vers) {
349 case SSUSB_UWK_V1:
350 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
351 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
352 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
353 break;
354 case SSUSB_UWK_V1_1:
355 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
356 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
357 val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
358 break;
359 case SSUSB_UWK_V1_2:
360 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
361 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
362 val = enable ? msk : 0;
363 break;
364 case SSUSB_UWK_V1_3:
365 reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
366 msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
367 val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
368 break;
369 case SSUSB_UWK_V1_4:
370 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
371 msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
372 val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
373 break;
374 case SSUSB_UWK_V1_5:
375 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
376 msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
377 val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
378 break;
379 case SSUSB_UWK_V1_6:
380 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
381 msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
382 val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
383 break;
384 case SSUSB_UWK_V2:
385 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
386 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
387 val = enable ? msk : 0;
388 break;
389 default:
390 return;
391 }
392 regmap_update_bits(mtk->uwk, reg, msk, val);
393}
394
395static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
396 struct device_node *dn)
397{
398 struct of_phandle_args args;
399 int ret;
400
401 /* Wakeup function is optional */
402 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
403 if (!mtk->uwk_en)
404 return 0;
405
406 ret = of_parse_phandle_with_fixed_args(dn,
407 "mediatek,syscon-wakeup", 2, 0, &args);
408 if (ret)
409 return ret;
410
411 mtk->uwk_reg_base = args.args[0];
412 mtk->uwk_vers = args.args[1];
413 mtk->uwk = syscon_node_to_regmap(args.np);
414 of_node_put(args.np);
415 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
416 mtk->uwk_reg_base, mtk->uwk_vers);
417
418 return PTR_ERR_OR_ZERO(mtk->uwk);
419}
420
421static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
422{
423 if (mtk->uwk_en)
424 usb_wakeup_ip_sleep_set(mtk, enable);
425}
426
427static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
428{
429 struct clk_bulk_data *clks = mtk->clks;
430
431 clks[0].id = "sys_ck";
432 clks[1].id = "xhci_ck";
433 clks[2].id = "ref_ck";
434 clks[3].id = "mcu_ck";
435 clks[4].id = "dma_ck";
436 clks[5].id = "frmcnt_ck";
437
438 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
439}
440
441static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk)
442{
443 struct regulator_bulk_data *supplies = mtk->supplies;
444
445 supplies[0].supply = "vbus";
446 supplies[1].supply = "vusb33";
447
448 return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies);
449}
450
451static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
452{
453 struct usb_hcd *hcd = xhci_to_hcd(xhci);
454 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
455
456 xhci->quirks |= XHCI_MTK_HOST;
457 /*
458 * MTK host controller gives a spurious successful event after a
459 * short transfer. Ignore it.
460 */
461 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
462 if (mtk->lpm_support)
463 xhci->quirks |= XHCI_LPM_SUPPORT;
464 if (mtk->u2_lpm_disable)
465 xhci->quirks |= XHCI_HW_LPM_DISABLE;
466
467 /*
468 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
469 * and it's 3 when support it.
470 */
471 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
472 xhci->quirks |= XHCI_BROKEN_STREAMS;
473}
474
475/* called during probe() after chip reset completes */
476static int xhci_mtk_setup(struct usb_hcd *hcd)
477{
478 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
479 int ret;
480
481 if (usb_hcd_is_primary_hcd(hcd)) {
482 ret = xhci_mtk_ssusb_config(mtk);
483 if (ret)
484 return ret;
485
486 xhci_mtk_init_quirk(mtk);
487 }
488
489 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
490 if (ret)
491 return ret;
492
493 if (usb_hcd_is_primary_hcd(hcd))
494 ret = xhci_mtk_sch_init(mtk);
495
496 return ret;
497}
498
499static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
500 .reset = xhci_mtk_setup,
501 .add_endpoint = xhci_mtk_add_ep,
502 .drop_endpoint = xhci_mtk_drop_ep,
503 .check_bandwidth = xhci_mtk_check_bandwidth,
504 .reset_bandwidth = xhci_mtk_reset_bandwidth,
505};
506
507static struct hc_driver __read_mostly xhci_mtk_hc_driver;
508
509static int xhci_mtk_probe(struct platform_device *pdev)
510{
511 struct device *dev = &pdev->dev;
512 struct device_node *node = dev->of_node;
513 struct xhci_hcd_mtk *mtk;
514 const struct hc_driver *driver;
515 struct xhci_hcd *xhci;
516 struct resource *res;
517 struct usb_hcd *usb3_hcd;
518 struct usb_hcd *hcd;
519 int ret = -ENODEV;
520 int wakeup_irq;
521 int irq;
522
523 if (usb_disabled())
524 return -ENODEV;
525
526 driver = &xhci_mtk_hc_driver;
527 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
528 if (!mtk)
529 return -ENOMEM;
530
531 mtk->dev = dev;
532
533 ret = xhci_mtk_vregs_get(mtk);
534 if (ret)
535 return dev_err_probe(dev, ret, "Failed to get regulators\n");
536
537 ret = xhci_mtk_clks_get(mtk);
538 if (ret)
539 return ret;
540
541 irq = platform_get_irq_byname_optional(pdev, "host");
542 if (irq < 0) {
543 if (irq == -EPROBE_DEFER)
544 return irq;
545
546 /* for backward compatibility */
547 irq = platform_get_irq(pdev, 0);
548 if (irq < 0)
549 return irq;
550 }
551
552 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
553 if (wakeup_irq == -EPROBE_DEFER)
554 return wakeup_irq;
555
556 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
557 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
558 /* optional property, ignore the error if it does not exist */
559 of_property_read_u32(node, "mediatek,u3p-dis-msk",
560 &mtk->u3p_dis_msk);
561 of_property_read_u32(node, "mediatek,u2p-dis-msk",
562 &mtk->u2p_dis_msk);
563
564 of_property_read_u32(node, "rx-fifo-depth", &mtk->rxfifo_depth);
565
566 ret = usb_wakeup_of_property_parse(mtk, node);
567 if (ret) {
568 dev_err(dev, "failed to parse uwk property\n");
569 return ret;
570 }
571
572 pm_runtime_set_active(dev);
573 pm_runtime_use_autosuspend(dev);
574 pm_runtime_set_autosuspend_delay(dev, 4000);
575 pm_runtime_enable(dev);
576 pm_runtime_get_sync(dev);
577
578 ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies);
579 if (ret)
580 goto disable_pm;
581
582 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
583 if (ret)
584 goto disable_ldos;
585
586 ret = device_reset_optional(dev);
587 if (ret) {
588 dev_err_probe(dev, ret, "failed to reset controller\n");
589 goto disable_clk;
590 }
591
592 hcd = usb_create_hcd(driver, dev, dev_name(dev));
593 if (!hcd) {
594 ret = -ENOMEM;
595 goto disable_clk;
596 }
597
598 /*
599 * USB 2.0 roothub is stored in the platform_device.
600 * Swap it with mtk HCD.
601 */
602 mtk->hcd = platform_get_drvdata(pdev);
603 platform_set_drvdata(pdev, mtk);
604
605 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
606 hcd->regs = devm_ioremap_resource(dev, res);
607 if (IS_ERR(hcd->regs)) {
608 ret = PTR_ERR(hcd->regs);
609 goto put_usb2_hcd;
610 }
611 hcd->rsrc_start = res->start;
612 hcd->rsrc_len = resource_size(res);
613
614 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
615 if (res) { /* ippc register is optional */
616 mtk->ippc_regs = devm_ioremap_resource(dev, res);
617 if (IS_ERR(mtk->ippc_regs)) {
618 ret = PTR_ERR(mtk->ippc_regs);
619 goto put_usb2_hcd;
620 }
621 mtk->has_ippc = true;
622 }
623
624 device_init_wakeup(dev, true);
625 dma_set_max_seg_size(dev, UINT_MAX);
626
627 xhci = hcd_to_xhci(hcd);
628 xhci->main_hcd = hcd;
629 xhci->allow_single_roothub = 1;
630
631 /*
632 * imod_interval is the interrupt moderation value in nanoseconds.
633 * The increment interval is 8 times as much as that defined in
634 * the xHCI spec on MTK's controller.
635 */
636 xhci->imod_interval = 5000;
637 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
638
639 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
640 if (ret)
641 goto disable_device_wakeup;
642
643 if (!xhci_has_one_roothub(xhci)) {
644 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
645 dev_name(dev), hcd);
646 if (!xhci->shared_hcd) {
647 ret = -ENOMEM;
648 goto dealloc_usb2_hcd;
649 }
650 }
651
652 usb3_hcd = xhci_get_usb3_hcd(xhci);
653 if (usb3_hcd && HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
654 !(xhci->quirks & XHCI_BROKEN_STREAMS))
655 usb3_hcd->can_do_streams = 1;
656
657 if (xhci->shared_hcd) {
658 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
659 if (ret)
660 goto put_usb3_hcd;
661 }
662
663 if (wakeup_irq > 0) {
664 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
665 if (ret) {
666 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
667 goto dealloc_usb3_hcd;
668 }
669 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
670 }
671
672 device_enable_async_suspend(dev);
673 pm_runtime_mark_last_busy(dev);
674 pm_runtime_put_autosuspend(dev);
675 pm_runtime_forbid(dev);
676
677 return 0;
678
679dealloc_usb3_hcd:
680 usb_remove_hcd(xhci->shared_hcd);
681
682put_usb3_hcd:
683 usb_put_hcd(xhci->shared_hcd);
684
685dealloc_usb2_hcd:
686 xhci_mtk_sch_exit(mtk);
687 usb_remove_hcd(hcd);
688
689disable_device_wakeup:
690 device_init_wakeup(dev, false);
691
692put_usb2_hcd:
693 usb_put_hcd(hcd);
694
695disable_clk:
696 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
697
698disable_ldos:
699 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
700
701disable_pm:
702 pm_runtime_put_noidle(dev);
703 pm_runtime_disable(dev);
704 return ret;
705}
706
707static void xhci_mtk_remove(struct platform_device *pdev)
708{
709 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
710 struct usb_hcd *hcd = mtk->hcd;
711 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
712 struct usb_hcd *shared_hcd = xhci->shared_hcd;
713 struct device *dev = &pdev->dev;
714
715 pm_runtime_get_sync(dev);
716 xhci->xhc_state |= XHCI_STATE_REMOVING;
717 dev_pm_clear_wake_irq(dev);
718 device_init_wakeup(dev, false);
719
720 if (shared_hcd) {
721 usb_remove_hcd(shared_hcd);
722 xhci->shared_hcd = NULL;
723 }
724 usb_remove_hcd(hcd);
725
726 if (shared_hcd)
727 usb_put_hcd(shared_hcd);
728
729 usb_put_hcd(hcd);
730 xhci_mtk_sch_exit(mtk);
731 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
732 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
733
734 pm_runtime_disable(dev);
735 pm_runtime_put_noidle(dev);
736 pm_runtime_set_suspended(dev);
737}
738
739static int __maybe_unused xhci_mtk_suspend(struct device *dev)
740{
741 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
742 struct usb_hcd *hcd = mtk->hcd;
743 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
744 struct usb_hcd *shared_hcd = xhci->shared_hcd;
745 int ret;
746
747 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
748 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
749 del_timer_sync(&hcd->rh_timer);
750 if (shared_hcd) {
751 clear_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
752 del_timer_sync(&shared_hcd->rh_timer);
753 }
754
755 ret = xhci_mtk_host_disable(mtk);
756 if (ret)
757 goto restart_poll_rh;
758
759 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
760 usb_wakeup_set(mtk, true);
761 return 0;
762
763restart_poll_rh:
764 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
765 if (shared_hcd) {
766 set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
767 usb_hcd_poll_rh_status(shared_hcd);
768 }
769 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
770 usb_hcd_poll_rh_status(hcd);
771 return ret;
772}
773
774static int __maybe_unused xhci_mtk_resume(struct device *dev)
775{
776 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
777 struct usb_hcd *hcd = mtk->hcd;
778 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
779 struct usb_hcd *shared_hcd = xhci->shared_hcd;
780 int ret;
781
782 usb_wakeup_set(mtk, false);
783 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
784 if (ret)
785 goto enable_wakeup;
786
787 ret = xhci_mtk_host_enable(mtk);
788 if (ret)
789 goto disable_clks;
790
791 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
792 if (shared_hcd) {
793 set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
794 usb_hcd_poll_rh_status(shared_hcd);
795 }
796 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
797 usb_hcd_poll_rh_status(hcd);
798 return 0;
799
800disable_clks:
801 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
802enable_wakeup:
803 usb_wakeup_set(mtk, true);
804 return ret;
805}
806
807static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
808{
809 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
810 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
811 int ret = 0;
812
813 if (xhci->xhc_state)
814 return -ESHUTDOWN;
815
816 if (device_may_wakeup(dev))
817 ret = xhci_mtk_suspend(dev);
818
819 /* -EBUSY: let PM automatically reschedule another autosuspend */
820 return ret ? -EBUSY : 0;
821}
822
823static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
824{
825 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
826 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
827 int ret = 0;
828
829 if (xhci->xhc_state)
830 return -ESHUTDOWN;
831
832 if (device_may_wakeup(dev))
833 ret = xhci_mtk_resume(dev);
834
835 return ret;
836}
837
838static const struct dev_pm_ops xhci_mtk_pm_ops = {
839 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
840 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
841 xhci_mtk_runtime_resume, NULL)
842};
843
844#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
845
846static const struct of_device_id mtk_xhci_of_match[] = {
847 { .compatible = "mediatek,mt8173-xhci"},
848 { .compatible = "mediatek,mt8195-xhci"},
849 { .compatible = "mediatek,mtk-xhci"},
850 { },
851};
852MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
853
854static struct platform_driver mtk_xhci_driver = {
855 .probe = xhci_mtk_probe,
856 .remove_new = xhci_mtk_remove,
857 .driver = {
858 .name = "xhci-mtk",
859 .pm = DEV_PM_OPS,
860 .of_match_table = mtk_xhci_of_match,
861 },
862};
863
864static int __init xhci_mtk_init(void)
865{
866 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
867 return platform_driver_register(&mtk_xhci_driver);
868}
869module_init(xhci_mtk_init);
870
871static void __exit xhci_mtk_exit(void)
872{
873 platform_driver_unregister(&mtk_xhci_driver);
874}
875module_exit(xhci_mtk_exit);
876
877MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
878MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
879MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek xHCI Host Controller Driver
4 *
5 * Copyright (c) 2015 MediaTek Inc.
6 * Author:
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/iopoll.h>
13#include <linux/kernel.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21
22#include "xhci.h"
23#include "xhci-mtk.h"
24
25/* ip_pw_ctrl0 register */
26#define CTRL0_IP_SW_RST BIT(0)
27
28/* ip_pw_ctrl1 register */
29#define CTRL1_IP_HOST_PDN BIT(0)
30
31/* ip_pw_ctrl2 register */
32#define CTRL2_IP_DEV_PDN BIT(0)
33
34/* ip_pw_sts1 register */
35#define STS1_IP_SLEEP_STS BIT(30)
36#define STS1_U3_MAC_RST BIT(16)
37#define STS1_XHCI_RST BIT(11)
38#define STS1_SYS125_RST BIT(10)
39#define STS1_REF_RST BIT(8)
40#define STS1_SYSPLL_STABLE BIT(0)
41
42/* ip_xhci_cap register */
43#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
44#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
45
46/* u3_ctrl_p register */
47#define CTRL_U3_PORT_HOST_SEL BIT(2)
48#define CTRL_U3_PORT_PDN BIT(1)
49#define CTRL_U3_PORT_DIS BIT(0)
50
51/* u2_ctrl_p register */
52#define CTRL_U2_PORT_HOST_SEL BIT(2)
53#define CTRL_U2_PORT_PDN BIT(1)
54#define CTRL_U2_PORT_DIS BIT(0)
55
56/* u2_phy_pll register */
57#define CTRL_U2_FORCE_PLL_STB BIT(28)
58
59/* usb remote wakeup registers in syscon */
60/* mt8173 etc */
61#define PERI_WK_CTRL1 0x4
62#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
63#define WC1_IS_EN BIT(25)
64#define WC1_IS_P BIT(6) /* polarity for ip sleep */
65
66/* mt2712 etc */
67#define PERI_SSUSB_SPM_CTRL 0x0
68#define SSC_IP_SLEEP_EN BIT(4)
69#define SSC_SPM_INT_EN BIT(1)
70
71enum ssusb_uwk_vers {
72 SSUSB_UWK_V1 = 1,
73 SSUSB_UWK_V2,
74};
75
76static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
77{
78 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
79 u32 value, check_val;
80 int u3_ports_disabed = 0;
81 int ret;
82 int i;
83
84 if (!mtk->has_ippc)
85 return 0;
86
87 /* power on host ip */
88 value = readl(&ippc->ip_pw_ctr1);
89 value &= ~CTRL1_IP_HOST_PDN;
90 writel(value, &ippc->ip_pw_ctr1);
91
92 /* power on and enable u3 ports except skipped ones */
93 for (i = 0; i < mtk->num_u3_ports; i++) {
94 if ((0x1 << i) & mtk->u3p_dis_msk) {
95 u3_ports_disabed++;
96 continue;
97 }
98
99 value = readl(&ippc->u3_ctrl_p[i]);
100 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
101 value |= CTRL_U3_PORT_HOST_SEL;
102 writel(value, &ippc->u3_ctrl_p[i]);
103 }
104
105 /* power on and enable all u2 ports */
106 for (i = 0; i < mtk->num_u2_ports; i++) {
107 value = readl(&ippc->u2_ctrl_p[i]);
108 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
109 value |= CTRL_U2_PORT_HOST_SEL;
110 writel(value, &ippc->u2_ctrl_p[i]);
111 }
112
113 /*
114 * wait for clocks to be stable, and clock domains reset to
115 * be inactive after power on and enable ports
116 */
117 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
118 STS1_SYS125_RST | STS1_XHCI_RST;
119
120 if (mtk->num_u3_ports > u3_ports_disabed)
121 check_val |= STS1_U3_MAC_RST;
122
123 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
124 (check_val == (value & check_val)), 100, 20000);
125 if (ret) {
126 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
127 return ret;
128 }
129
130 return 0;
131}
132
133static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
134{
135 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
136 u32 value;
137 int ret;
138 int i;
139
140 if (!mtk->has_ippc)
141 return 0;
142
143 /* power down u3 ports except skipped ones */
144 for (i = 0; i < mtk->num_u3_ports; i++) {
145 if ((0x1 << i) & mtk->u3p_dis_msk)
146 continue;
147
148 value = readl(&ippc->u3_ctrl_p[i]);
149 value |= CTRL_U3_PORT_PDN;
150 writel(value, &ippc->u3_ctrl_p[i]);
151 }
152
153 /* power down all u2 ports */
154 for (i = 0; i < mtk->num_u2_ports; i++) {
155 value = readl(&ippc->u2_ctrl_p[i]);
156 value |= CTRL_U2_PORT_PDN;
157 writel(value, &ippc->u2_ctrl_p[i]);
158 }
159
160 /* power down host ip */
161 value = readl(&ippc->ip_pw_ctr1);
162 value |= CTRL1_IP_HOST_PDN;
163 writel(value, &ippc->ip_pw_ctr1);
164
165 /* wait for host ip to sleep */
166 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
167 (value & STS1_IP_SLEEP_STS), 100, 100000);
168 if (ret) {
169 dev_err(mtk->dev, "ip sleep failed!!!\n");
170 return ret;
171 }
172 return 0;
173}
174
175static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
176{
177 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
178 u32 value;
179
180 if (!mtk->has_ippc)
181 return 0;
182
183 /* reset whole ip */
184 value = readl(&ippc->ip_pw_ctr0);
185 value |= CTRL0_IP_SW_RST;
186 writel(value, &ippc->ip_pw_ctr0);
187 udelay(1);
188 value = readl(&ippc->ip_pw_ctr0);
189 value &= ~CTRL0_IP_SW_RST;
190 writel(value, &ippc->ip_pw_ctr0);
191
192 /*
193 * device ip is default power-on in fact
194 * power down device ip, otherwise ip-sleep will fail
195 */
196 value = readl(&ippc->ip_pw_ctr2);
197 value |= CTRL2_IP_DEV_PDN;
198 writel(value, &ippc->ip_pw_ctr2);
199
200 value = readl(&ippc->ip_xhci_cap);
201 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
202 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
203 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
204 mtk->num_u2_ports, mtk->num_u3_ports);
205
206 return xhci_mtk_host_enable(mtk);
207}
208
209static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
210{
211 struct device *dev = mtk->dev;
212
213 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
214 if (IS_ERR(mtk->sys_clk)) {
215 dev_err(dev, "fail to get sys_ck\n");
216 return PTR_ERR(mtk->sys_clk);
217 }
218
219 mtk->xhci_clk = devm_clk_get_optional(dev, "xhci_ck");
220 if (IS_ERR(mtk->xhci_clk))
221 return PTR_ERR(mtk->xhci_clk);
222
223 mtk->ref_clk = devm_clk_get_optional(dev, "ref_ck");
224 if (IS_ERR(mtk->ref_clk))
225 return PTR_ERR(mtk->ref_clk);
226
227 mtk->mcu_clk = devm_clk_get_optional(dev, "mcu_ck");
228 if (IS_ERR(mtk->mcu_clk))
229 return PTR_ERR(mtk->mcu_clk);
230
231 mtk->dma_clk = devm_clk_get_optional(dev, "dma_ck");
232 return PTR_ERR_OR_ZERO(mtk->dma_clk);
233}
234
235static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
236{
237 int ret;
238
239 ret = clk_prepare_enable(mtk->ref_clk);
240 if (ret) {
241 dev_err(mtk->dev, "failed to enable ref_clk\n");
242 goto ref_clk_err;
243 }
244
245 ret = clk_prepare_enable(mtk->sys_clk);
246 if (ret) {
247 dev_err(mtk->dev, "failed to enable sys_clk\n");
248 goto sys_clk_err;
249 }
250
251 ret = clk_prepare_enable(mtk->xhci_clk);
252 if (ret) {
253 dev_err(mtk->dev, "failed to enable xhci_clk\n");
254 goto xhci_clk_err;
255 }
256
257 ret = clk_prepare_enable(mtk->mcu_clk);
258 if (ret) {
259 dev_err(mtk->dev, "failed to enable mcu_clk\n");
260 goto mcu_clk_err;
261 }
262
263 ret = clk_prepare_enable(mtk->dma_clk);
264 if (ret) {
265 dev_err(mtk->dev, "failed to enable dma_clk\n");
266 goto dma_clk_err;
267 }
268
269 return 0;
270
271dma_clk_err:
272 clk_disable_unprepare(mtk->mcu_clk);
273mcu_clk_err:
274 clk_disable_unprepare(mtk->xhci_clk);
275xhci_clk_err:
276 clk_disable_unprepare(mtk->sys_clk);
277sys_clk_err:
278 clk_disable_unprepare(mtk->ref_clk);
279ref_clk_err:
280 return ret;
281}
282
283static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
284{
285 clk_disable_unprepare(mtk->dma_clk);
286 clk_disable_unprepare(mtk->mcu_clk);
287 clk_disable_unprepare(mtk->xhci_clk);
288 clk_disable_unprepare(mtk->sys_clk);
289 clk_disable_unprepare(mtk->ref_clk);
290}
291
292/* only clocks can be turn off for ip-sleep wakeup mode */
293static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
294{
295 u32 reg, msk, val;
296
297 switch (mtk->uwk_vers) {
298 case SSUSB_UWK_V1:
299 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
300 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
301 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
302 break;
303 case SSUSB_UWK_V2:
304 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
305 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
306 val = enable ? msk : 0;
307 break;
308 default:
309 return;
310 }
311 regmap_update_bits(mtk->uwk, reg, msk, val);
312}
313
314static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
315 struct device_node *dn)
316{
317 struct of_phandle_args args;
318 int ret;
319
320 /* Wakeup function is optional */
321 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
322 if (!mtk->uwk_en)
323 return 0;
324
325 ret = of_parse_phandle_with_fixed_args(dn,
326 "mediatek,syscon-wakeup", 2, 0, &args);
327 if (ret)
328 return ret;
329
330 mtk->uwk_reg_base = args.args[0];
331 mtk->uwk_vers = args.args[1];
332 mtk->uwk = syscon_node_to_regmap(args.np);
333 of_node_put(args.np);
334 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
335 mtk->uwk_reg_base, mtk->uwk_vers);
336
337 return PTR_ERR_OR_ZERO(mtk->uwk);
338
339}
340
341static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
342{
343 if (mtk->uwk_en)
344 usb_wakeup_ip_sleep_set(mtk, enable);
345}
346
347static int xhci_mtk_setup(struct usb_hcd *hcd);
348static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
349 .reset = xhci_mtk_setup,
350};
351
352static struct hc_driver __read_mostly xhci_mtk_hc_driver;
353
354static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
355{
356 int ret;
357
358 ret = regulator_enable(mtk->vbus);
359 if (ret) {
360 dev_err(mtk->dev, "failed to enable vbus\n");
361 return ret;
362 }
363
364 ret = regulator_enable(mtk->vusb33);
365 if (ret) {
366 dev_err(mtk->dev, "failed to enable vusb33\n");
367 regulator_disable(mtk->vbus);
368 return ret;
369 }
370 return 0;
371}
372
373static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
374{
375 regulator_disable(mtk->vbus);
376 regulator_disable(mtk->vusb33);
377}
378
379static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
380{
381 struct usb_hcd *hcd = xhci_to_hcd(xhci);
382 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
383
384 /*
385 * As of now platform drivers don't provide MSI support so we ensure
386 * here that the generic code does not try to make a pci_dev from our
387 * dev struct in order to setup MSI
388 */
389 xhci->quirks |= XHCI_PLAT;
390 xhci->quirks |= XHCI_MTK_HOST;
391 /*
392 * MTK host controller gives a spurious successful event after a
393 * short transfer. Ignore it.
394 */
395 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
396 if (mtk->lpm_support)
397 xhci->quirks |= XHCI_LPM_SUPPORT;
398}
399
400/* called during probe() after chip reset completes */
401static int xhci_mtk_setup(struct usb_hcd *hcd)
402{
403 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
404 int ret;
405
406 if (usb_hcd_is_primary_hcd(hcd)) {
407 ret = xhci_mtk_ssusb_config(mtk);
408 if (ret)
409 return ret;
410 }
411
412 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
413 if (ret)
414 return ret;
415
416 if (usb_hcd_is_primary_hcd(hcd)) {
417 ret = xhci_mtk_sch_init(mtk);
418 if (ret)
419 return ret;
420 }
421
422 return ret;
423}
424
425static int xhci_mtk_probe(struct platform_device *pdev)
426{
427 struct device *dev = &pdev->dev;
428 struct device_node *node = dev->of_node;
429 struct xhci_hcd_mtk *mtk;
430 const struct hc_driver *driver;
431 struct xhci_hcd *xhci;
432 struct resource *res;
433 struct usb_hcd *hcd;
434 int ret = -ENODEV;
435 int irq;
436
437 if (usb_disabled())
438 return -ENODEV;
439
440 driver = &xhci_mtk_hc_driver;
441 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
442 if (!mtk)
443 return -ENOMEM;
444
445 mtk->dev = dev;
446 mtk->vbus = devm_regulator_get(dev, "vbus");
447 if (IS_ERR(mtk->vbus)) {
448 dev_err(dev, "fail to get vbus\n");
449 return PTR_ERR(mtk->vbus);
450 }
451
452 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
453 if (IS_ERR(mtk->vusb33)) {
454 dev_err(dev, "fail to get vusb33\n");
455 return PTR_ERR(mtk->vusb33);
456 }
457
458 ret = xhci_mtk_clks_get(mtk);
459 if (ret)
460 return ret;
461
462 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
463 /* optional property, ignore the error if it does not exist */
464 of_property_read_u32(node, "mediatek,u3p-dis-msk",
465 &mtk->u3p_dis_msk);
466
467 ret = usb_wakeup_of_property_parse(mtk, node);
468 if (ret) {
469 dev_err(dev, "failed to parse uwk property\n");
470 return ret;
471 }
472
473 pm_runtime_enable(dev);
474 pm_runtime_get_sync(dev);
475 device_enable_async_suspend(dev);
476
477 ret = xhci_mtk_ldos_enable(mtk);
478 if (ret)
479 goto disable_pm;
480
481 ret = xhci_mtk_clks_enable(mtk);
482 if (ret)
483 goto disable_ldos;
484
485 irq = platform_get_irq(pdev, 0);
486 if (irq < 0) {
487 ret = irq;
488 goto disable_clk;
489 }
490
491 hcd = usb_create_hcd(driver, dev, dev_name(dev));
492 if (!hcd) {
493 ret = -ENOMEM;
494 goto disable_clk;
495 }
496
497 /*
498 * USB 2.0 roothub is stored in the platform_device.
499 * Swap it with mtk HCD.
500 */
501 mtk->hcd = platform_get_drvdata(pdev);
502 platform_set_drvdata(pdev, mtk);
503
504 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
505 hcd->regs = devm_ioremap_resource(dev, res);
506 if (IS_ERR(hcd->regs)) {
507 ret = PTR_ERR(hcd->regs);
508 goto put_usb2_hcd;
509 }
510 hcd->rsrc_start = res->start;
511 hcd->rsrc_len = resource_size(res);
512
513 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
514 if (res) { /* ippc register is optional */
515 mtk->ippc_regs = devm_ioremap_resource(dev, res);
516 if (IS_ERR(mtk->ippc_regs)) {
517 ret = PTR_ERR(mtk->ippc_regs);
518 goto put_usb2_hcd;
519 }
520 mtk->has_ippc = true;
521 } else {
522 mtk->has_ippc = false;
523 }
524
525 device_init_wakeup(dev, true);
526
527 xhci = hcd_to_xhci(hcd);
528 xhci->main_hcd = hcd;
529
530 /*
531 * imod_interval is the interrupt moderation value in nanoseconds.
532 * The increment interval is 8 times as much as that defined in
533 * the xHCI spec on MTK's controller.
534 */
535 xhci->imod_interval = 5000;
536 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
537
538 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
539 dev_name(dev), hcd);
540 if (!xhci->shared_hcd) {
541 ret = -ENOMEM;
542 goto disable_device_wakeup;
543 }
544
545 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
546 if (ret)
547 goto put_usb3_hcd;
548
549 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
550 xhci->shared_hcd->can_do_streams = 1;
551
552 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
553 if (ret)
554 goto dealloc_usb2_hcd;
555
556 return 0;
557
558dealloc_usb2_hcd:
559 usb_remove_hcd(hcd);
560
561put_usb3_hcd:
562 xhci_mtk_sch_exit(mtk);
563 usb_put_hcd(xhci->shared_hcd);
564
565disable_device_wakeup:
566 device_init_wakeup(dev, false);
567
568put_usb2_hcd:
569 usb_put_hcd(hcd);
570
571disable_clk:
572 xhci_mtk_clks_disable(mtk);
573
574disable_ldos:
575 xhci_mtk_ldos_disable(mtk);
576
577disable_pm:
578 pm_runtime_put_sync(dev);
579 pm_runtime_disable(dev);
580 return ret;
581}
582
583static int xhci_mtk_remove(struct platform_device *dev)
584{
585 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
586 struct usb_hcd *hcd = mtk->hcd;
587 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
588 struct usb_hcd *shared_hcd = xhci->shared_hcd;
589
590 pm_runtime_put_noidle(&dev->dev);
591 pm_runtime_disable(&dev->dev);
592
593 usb_remove_hcd(shared_hcd);
594 xhci->shared_hcd = NULL;
595 device_init_wakeup(&dev->dev, false);
596
597 usb_remove_hcd(hcd);
598 usb_put_hcd(shared_hcd);
599 usb_put_hcd(hcd);
600 xhci_mtk_sch_exit(mtk);
601 xhci_mtk_clks_disable(mtk);
602 xhci_mtk_ldos_disable(mtk);
603
604 return 0;
605}
606
607/*
608 * if ip sleep fails, and all clocks are disabled, access register will hang
609 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
610 * and no need to check whether ip sleep failed or not; this will cause SPM
611 * to wake up system immediately after system suspend complete if ip sleep
612 * fails, it is what we wanted.
613 */
614static int __maybe_unused xhci_mtk_suspend(struct device *dev)
615{
616 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
617 struct usb_hcd *hcd = mtk->hcd;
618 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
619
620 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
621 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
622 del_timer_sync(&hcd->rh_timer);
623 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
624 del_timer_sync(&xhci->shared_hcd->rh_timer);
625
626 xhci_mtk_host_disable(mtk);
627 xhci_mtk_clks_disable(mtk);
628 usb_wakeup_set(mtk, true);
629 return 0;
630}
631
632static int __maybe_unused xhci_mtk_resume(struct device *dev)
633{
634 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
635 struct usb_hcd *hcd = mtk->hcd;
636 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
637
638 usb_wakeup_set(mtk, false);
639 xhci_mtk_clks_enable(mtk);
640 xhci_mtk_host_enable(mtk);
641
642 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
643 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
644 usb_hcd_poll_rh_status(xhci->shared_hcd);
645 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
646 usb_hcd_poll_rh_status(hcd);
647 return 0;
648}
649
650static const struct dev_pm_ops xhci_mtk_pm_ops = {
651 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
652};
653#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
654
655#ifdef CONFIG_OF
656static const struct of_device_id mtk_xhci_of_match[] = {
657 { .compatible = "mediatek,mt8173-xhci"},
658 { .compatible = "mediatek,mtk-xhci"},
659 { },
660};
661MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
662#endif
663
664static struct platform_driver mtk_xhci_driver = {
665 .probe = xhci_mtk_probe,
666 .remove = xhci_mtk_remove,
667 .driver = {
668 .name = "xhci-mtk",
669 .pm = DEV_PM_OPS,
670 .of_match_table = of_match_ptr(mtk_xhci_of_match),
671 },
672};
673MODULE_ALIAS("platform:xhci-mtk");
674
675static int __init xhci_mtk_init(void)
676{
677 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
678 return platform_driver_register(&mtk_xhci_driver);
679}
680module_init(xhci_mtk_init);
681
682static void __exit xhci_mtk_exit(void)
683{
684 platform_driver_unregister(&mtk_xhci_driver);
685}
686module_exit(xhci_mtk_exit);
687
688MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
689MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
690MODULE_LICENSE("GPL v2");