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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Based on drivers/serial/8250.c by Russell King.
4 *
5 * Author: Nicolas Pitre
6 * Created: Feb 20, 2003
7 * Copyright: (C) 2003 Monta Vista Software, Inc.
8 *
9 * Note 1: This driver is made separate from the already too overloaded
10 * 8250.c because it needs some kirks of its own and that'll make it
11 * easier to add DMA support.
12 *
13 * Note 2: I'm too sick of device allocation policies for serial ports.
14 * If someone else wants to request an "official" allocation of major/minor
15 * for this driver please be my guest. And don't forget that new hardware
16 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17 * hope for a better port registration and dynamic device allocation scheme
18 * with the serial core maintainer satisfaction to appear soon.
19 */
20
21
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/sysrq.h>
26#include <linux/serial.h>
27#include <linux/serial_reg.h>
28#include <linux/circ_buf.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
31#include <linux/of.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36#include <linux/clk.h>
37#include <linux/io.h>
38#include <linux/slab.h>
39
40#define PXA_NAME_LEN 8
41
42struct uart_pxa_port {
43 struct uart_port port;
44 unsigned char ier;
45 unsigned char lcr;
46 unsigned char mcr;
47 unsigned int lsr_break_flag;
48 struct clk *clk;
49 char name[PXA_NAME_LEN];
50};
51
52static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
53{
54 offset <<= 2;
55 return readl(up->port.membase + offset);
56}
57
58static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
59{
60 offset <<= 2;
61 writel(value, up->port.membase + offset);
62}
63
64static void serial_pxa_enable_ms(struct uart_port *port)
65{
66 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
67
68 up->ier |= UART_IER_MSI;
69 serial_out(up, UART_IER, up->ier);
70}
71
72static void serial_pxa_stop_tx(struct uart_port *port)
73{
74 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
75
76 if (up->ier & UART_IER_THRI) {
77 up->ier &= ~UART_IER_THRI;
78 serial_out(up, UART_IER, up->ier);
79 }
80}
81
82static void serial_pxa_stop_rx(struct uart_port *port)
83{
84 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
85
86 up->ier &= ~UART_IER_RLSI;
87 up->port.read_status_mask &= ~UART_LSR_DR;
88 serial_out(up, UART_IER, up->ier);
89}
90
91static inline void receive_chars(struct uart_pxa_port *up, int *status)
92{
93 u8 ch, flag;
94 int max_count = 256;
95
96 do {
97 /* work around Errata #20 according to
98 * Intel(R) PXA27x Processor Family
99 * Specification Update (May 2005)
100 *
101 * Step 2
102 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
103 */
104 up->ier &= ~UART_IER_RTOIE;
105 serial_out(up, UART_IER, up->ier);
106
107 ch = serial_in(up, UART_RX);
108 flag = TTY_NORMAL;
109 up->port.icount.rx++;
110
111 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
112 UART_LSR_FE | UART_LSR_OE))) {
113 /*
114 * For statistics only
115 */
116 if (*status & UART_LSR_BI) {
117 *status &= ~(UART_LSR_FE | UART_LSR_PE);
118 up->port.icount.brk++;
119 /*
120 * We do the SysRQ and SAK checking
121 * here because otherwise the break
122 * may get masked by ignore_status_mask
123 * or read_status_mask.
124 */
125 if (uart_handle_break(&up->port))
126 goto ignore_char;
127 } else if (*status & UART_LSR_PE)
128 up->port.icount.parity++;
129 else if (*status & UART_LSR_FE)
130 up->port.icount.frame++;
131 if (*status & UART_LSR_OE)
132 up->port.icount.overrun++;
133
134 /*
135 * Mask off conditions which should be ignored.
136 */
137 *status &= up->port.read_status_mask;
138
139#ifdef CONFIG_SERIAL_PXA_CONSOLE
140 if (up->port.line == up->port.cons->index) {
141 /* Recover the break flag from console xmit */
142 *status |= up->lsr_break_flag;
143 up->lsr_break_flag = 0;
144 }
145#endif
146 if (*status & UART_LSR_BI) {
147 flag = TTY_BREAK;
148 } else if (*status & UART_LSR_PE)
149 flag = TTY_PARITY;
150 else if (*status & UART_LSR_FE)
151 flag = TTY_FRAME;
152 }
153
154 if (uart_handle_sysrq_char(&up->port, ch))
155 goto ignore_char;
156
157 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
158
159 ignore_char:
160 *status = serial_in(up, UART_LSR);
161 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
162 tty_flip_buffer_push(&up->port.state->port);
163
164 /* work around Errata #20 according to
165 * Intel(R) PXA27x Processor Family
166 * Specification Update (May 2005)
167 *
168 * Step 6:
169 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
170 */
171 up->ier |= UART_IER_RTOIE;
172 serial_out(up, UART_IER, up->ier);
173}
174
175static void transmit_chars(struct uart_pxa_port *up)
176{
177 u8 ch;
178
179 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 2,
180 true,
181 serial_out(up, UART_TX, ch),
182 ({}));
183}
184
185static void serial_pxa_start_tx(struct uart_port *port)
186{
187 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
188
189 if (!(up->ier & UART_IER_THRI)) {
190 up->ier |= UART_IER_THRI;
191 serial_out(up, UART_IER, up->ier);
192 }
193}
194
195/* should hold up->port.lock */
196static inline void check_modem_status(struct uart_pxa_port *up)
197{
198 int status;
199
200 status = serial_in(up, UART_MSR);
201
202 if ((status & UART_MSR_ANY_DELTA) == 0)
203 return;
204
205 if (status & UART_MSR_TERI)
206 up->port.icount.rng++;
207 if (status & UART_MSR_DDSR)
208 up->port.icount.dsr++;
209 if (status & UART_MSR_DDCD)
210 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
211 if (status & UART_MSR_DCTS)
212 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
213
214 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
215}
216
217/*
218 * This handles the interrupt from one port.
219 */
220static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
221{
222 struct uart_pxa_port *up = dev_id;
223 unsigned int iir, lsr;
224
225 iir = serial_in(up, UART_IIR);
226 if (iir & UART_IIR_NO_INT)
227 return IRQ_NONE;
228 uart_port_lock(&up->port);
229 lsr = serial_in(up, UART_LSR);
230 if (lsr & UART_LSR_DR)
231 receive_chars(up, &lsr);
232 check_modem_status(up);
233 if (lsr & UART_LSR_THRE)
234 transmit_chars(up);
235 uart_port_unlock(&up->port);
236 return IRQ_HANDLED;
237}
238
239static unsigned int serial_pxa_tx_empty(struct uart_port *port)
240{
241 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
242 unsigned long flags;
243 unsigned int ret;
244
245 uart_port_lock_irqsave(&up->port, &flags);
246 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
247 uart_port_unlock_irqrestore(&up->port, flags);
248
249 return ret;
250}
251
252static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
253{
254 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
255 unsigned char status;
256 unsigned int ret;
257
258 status = serial_in(up, UART_MSR);
259
260 ret = 0;
261 if (status & UART_MSR_DCD)
262 ret |= TIOCM_CAR;
263 if (status & UART_MSR_RI)
264 ret |= TIOCM_RNG;
265 if (status & UART_MSR_DSR)
266 ret |= TIOCM_DSR;
267 if (status & UART_MSR_CTS)
268 ret |= TIOCM_CTS;
269 return ret;
270}
271
272static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
273{
274 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
275 unsigned char mcr = 0;
276
277 if (mctrl & TIOCM_RTS)
278 mcr |= UART_MCR_RTS;
279 if (mctrl & TIOCM_DTR)
280 mcr |= UART_MCR_DTR;
281 if (mctrl & TIOCM_OUT1)
282 mcr |= UART_MCR_OUT1;
283 if (mctrl & TIOCM_OUT2)
284 mcr |= UART_MCR_OUT2;
285 if (mctrl & TIOCM_LOOP)
286 mcr |= UART_MCR_LOOP;
287
288 mcr |= up->mcr;
289
290 serial_out(up, UART_MCR, mcr);
291}
292
293static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
294{
295 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
296 unsigned long flags;
297
298 uart_port_lock_irqsave(&up->port, &flags);
299 if (break_state == -1)
300 up->lcr |= UART_LCR_SBC;
301 else
302 up->lcr &= ~UART_LCR_SBC;
303 serial_out(up, UART_LCR, up->lcr);
304 uart_port_unlock_irqrestore(&up->port, flags);
305}
306
307static int serial_pxa_startup(struct uart_port *port)
308{
309 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
310 unsigned long flags;
311 int retval;
312
313 if (port->line == 3) /* HWUART */
314 up->mcr |= UART_MCR_AFE;
315 else
316 up->mcr = 0;
317
318 up->port.uartclk = clk_get_rate(up->clk);
319
320 /*
321 * Allocate the IRQ
322 */
323 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
324 if (retval)
325 return retval;
326
327 /*
328 * Clear the FIFO buffers and disable them.
329 * (they will be reenabled in set_termios())
330 */
331 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
332 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
333 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
334 serial_out(up, UART_FCR, 0);
335
336 /*
337 * Clear the interrupt registers.
338 */
339 (void) serial_in(up, UART_LSR);
340 (void) serial_in(up, UART_RX);
341 (void) serial_in(up, UART_IIR);
342 (void) serial_in(up, UART_MSR);
343
344 /*
345 * Now, initialize the UART
346 */
347 serial_out(up, UART_LCR, UART_LCR_WLEN8);
348
349 uart_port_lock_irqsave(&up->port, &flags);
350 up->port.mctrl |= TIOCM_OUT2;
351 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
352 uart_port_unlock_irqrestore(&up->port, flags);
353
354 /*
355 * Finally, enable interrupts. Note: Modem status interrupts
356 * are set via set_termios(), which will be occurring imminently
357 * anyway, so we don't enable them here.
358 */
359 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
360 serial_out(up, UART_IER, up->ier);
361
362 /*
363 * And clear the interrupt registers again for luck.
364 */
365 (void) serial_in(up, UART_LSR);
366 (void) serial_in(up, UART_RX);
367 (void) serial_in(up, UART_IIR);
368 (void) serial_in(up, UART_MSR);
369
370 return 0;
371}
372
373static void serial_pxa_shutdown(struct uart_port *port)
374{
375 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
376 unsigned long flags;
377
378 free_irq(up->port.irq, up);
379
380 /*
381 * Disable interrupts from this port
382 */
383 up->ier = 0;
384 serial_out(up, UART_IER, 0);
385
386 uart_port_lock_irqsave(&up->port, &flags);
387 up->port.mctrl &= ~TIOCM_OUT2;
388 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
389 uart_port_unlock_irqrestore(&up->port, flags);
390
391 /*
392 * Disable break condition and FIFOs
393 */
394 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
395 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
396 UART_FCR_CLEAR_RCVR |
397 UART_FCR_CLEAR_XMIT);
398 serial_out(up, UART_FCR, 0);
399}
400
401static void
402serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
403 const struct ktermios *old)
404{
405 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
406 unsigned char cval, fcr = 0;
407 unsigned long flags;
408 unsigned int baud, quot;
409 unsigned int dll;
410
411 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
412
413 if (termios->c_cflag & CSTOPB)
414 cval |= UART_LCR_STOP;
415 if (termios->c_cflag & PARENB)
416 cval |= UART_LCR_PARITY;
417 if (!(termios->c_cflag & PARODD))
418 cval |= UART_LCR_EPAR;
419
420 /*
421 * Ask the core to calculate the divisor for us.
422 */
423 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
424 quot = uart_get_divisor(port, baud);
425
426 if ((up->port.uartclk / quot) < (2400 * 16))
427 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
428 else if ((up->port.uartclk / quot) < (230400 * 16))
429 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
430 else
431 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
432
433 /*
434 * Ok, we're now changing the port state. Do it with
435 * interrupts disabled.
436 */
437 uart_port_lock_irqsave(&up->port, &flags);
438
439 /*
440 * Ensure the port will be enabled.
441 * This is required especially for serial console.
442 */
443 up->ier |= UART_IER_UUE;
444
445 /*
446 * Update the per-port timeout.
447 */
448 uart_update_timeout(port, termios->c_cflag, baud);
449
450 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
451 if (termios->c_iflag & INPCK)
452 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
453 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
454 up->port.read_status_mask |= UART_LSR_BI;
455
456 /*
457 * Characters to ignore
458 */
459 up->port.ignore_status_mask = 0;
460 if (termios->c_iflag & IGNPAR)
461 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
462 if (termios->c_iflag & IGNBRK) {
463 up->port.ignore_status_mask |= UART_LSR_BI;
464 /*
465 * If we're ignoring parity and break indicators,
466 * ignore overruns too (for real raw support).
467 */
468 if (termios->c_iflag & IGNPAR)
469 up->port.ignore_status_mask |= UART_LSR_OE;
470 }
471
472 /*
473 * ignore all characters if CREAD is not set
474 */
475 if ((termios->c_cflag & CREAD) == 0)
476 up->port.ignore_status_mask |= UART_LSR_DR;
477
478 /*
479 * CTS flow control flag and modem status interrupts
480 */
481 up->ier &= ~UART_IER_MSI;
482 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
483 up->ier |= UART_IER_MSI;
484
485 serial_out(up, UART_IER, up->ier);
486
487 if (termios->c_cflag & CRTSCTS)
488 up->mcr |= UART_MCR_AFE;
489 else
490 up->mcr &= ~UART_MCR_AFE;
491
492 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
493 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
494
495 /*
496 * work around Errata #75 according to Intel(R) PXA27x Processor Family
497 * Specification Update (Nov 2005)
498 */
499 dll = serial_in(up, UART_DLL);
500 WARN_ON(dll != (quot & 0xff));
501
502 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
503 serial_out(up, UART_LCR, cval); /* reset DLAB */
504 up->lcr = cval; /* Save LCR */
505 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
506 serial_out(up, UART_FCR, fcr);
507 uart_port_unlock_irqrestore(&up->port, flags);
508}
509
510static void
511serial_pxa_pm(struct uart_port *port, unsigned int state,
512 unsigned int oldstate)
513{
514 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
515
516 if (!state)
517 clk_prepare_enable(up->clk);
518 else
519 clk_disable_unprepare(up->clk);
520}
521
522static void serial_pxa_release_port(struct uart_port *port)
523{
524}
525
526static int serial_pxa_request_port(struct uart_port *port)
527{
528 return 0;
529}
530
531static void serial_pxa_config_port(struct uart_port *port, int flags)
532{
533 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
534 up->port.type = PORT_PXA;
535}
536
537static int
538serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
539{
540 /* we don't want the core code to modify any port params */
541 return -EINVAL;
542}
543
544static const char *
545serial_pxa_type(struct uart_port *port)
546{
547 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
548 return up->name;
549}
550
551static struct uart_pxa_port *serial_pxa_ports[4];
552static struct uart_driver serial_pxa_reg;
553
554#ifdef CONFIG_SERIAL_PXA_CONSOLE
555
556/*
557 * Wait for transmitter & holding register to empty
558 */
559static void wait_for_xmitr(struct uart_pxa_port *up)
560{
561 unsigned int status, tmout = 10000;
562
563 /* Wait up to 10ms for the character(s) to be sent. */
564 do {
565 status = serial_in(up, UART_LSR);
566
567 if (status & UART_LSR_BI)
568 up->lsr_break_flag = UART_LSR_BI;
569
570 if (--tmout == 0)
571 break;
572 udelay(1);
573 } while (!uart_lsr_tx_empty(status));
574
575 /* Wait up to 1s for flow control if necessary */
576 if (up->port.flags & UPF_CONS_FLOW) {
577 tmout = 1000000;
578 while (--tmout &&
579 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
580 udelay(1);
581 }
582}
583
584static void serial_pxa_console_putchar(struct uart_port *port, unsigned char ch)
585{
586 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
587
588 wait_for_xmitr(up);
589 serial_out(up, UART_TX, ch);
590}
591
592/*
593 * Print a string to the serial port trying not to disturb
594 * any possible real use of the port...
595 *
596 * The console_lock must be held when we get here.
597 */
598static void
599serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
600{
601 struct uart_pxa_port *up = serial_pxa_ports[co->index];
602 unsigned int ier;
603 unsigned long flags;
604 int locked = 1;
605
606 clk_enable(up->clk);
607 local_irq_save(flags);
608 if (up->port.sysrq)
609 locked = 0;
610 else if (oops_in_progress)
611 locked = uart_port_trylock(&up->port);
612 else
613 uart_port_lock(&up->port);
614
615 /*
616 * First save the IER then disable the interrupts
617 */
618 ier = serial_in(up, UART_IER);
619 serial_out(up, UART_IER, UART_IER_UUE);
620
621 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
622
623 /*
624 * Finally, wait for transmitter to become empty
625 * and restore the IER
626 */
627 wait_for_xmitr(up);
628 serial_out(up, UART_IER, ier);
629
630 if (locked)
631 uart_port_unlock(&up->port);
632 local_irq_restore(flags);
633 clk_disable(up->clk);
634
635}
636
637#ifdef CONFIG_CONSOLE_POLL
638/*
639 * Console polling routines for writing and reading from the uart while
640 * in an interrupt or debug context.
641 */
642
643static int serial_pxa_get_poll_char(struct uart_port *port)
644{
645 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
646 unsigned char lsr = serial_in(up, UART_LSR);
647
648 while (!(lsr & UART_LSR_DR))
649 lsr = serial_in(up, UART_LSR);
650
651 return serial_in(up, UART_RX);
652}
653
654
655static void serial_pxa_put_poll_char(struct uart_port *port,
656 unsigned char c)
657{
658 unsigned int ier;
659 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
660
661 /*
662 * First save the IER then disable the interrupts
663 */
664 ier = serial_in(up, UART_IER);
665 serial_out(up, UART_IER, UART_IER_UUE);
666
667 wait_for_xmitr(up);
668 /*
669 * Send the character out.
670 */
671 serial_out(up, UART_TX, c);
672
673 /*
674 * Finally, wait for transmitter to become empty
675 * and restore the IER
676 */
677 wait_for_xmitr(up);
678 serial_out(up, UART_IER, ier);
679}
680
681#endif /* CONFIG_CONSOLE_POLL */
682
683static int __init
684serial_pxa_console_setup(struct console *co, char *options)
685{
686 struct uart_pxa_port *up;
687 int baud = 9600;
688 int bits = 8;
689 int parity = 'n';
690 int flow = 'n';
691
692 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
693 co->index = 0;
694 up = serial_pxa_ports[co->index];
695 if (!up)
696 return -ENODEV;
697
698 if (options)
699 uart_parse_options(options, &baud, &parity, &bits, &flow);
700
701 return uart_set_options(&up->port, co, baud, parity, bits, flow);
702}
703
704static struct console serial_pxa_console = {
705 .name = "ttyS",
706 .write = serial_pxa_console_write,
707 .device = uart_console_device,
708 .setup = serial_pxa_console_setup,
709 .flags = CON_PRINTBUFFER,
710 .index = -1,
711 .data = &serial_pxa_reg,
712};
713
714#define PXA_CONSOLE &serial_pxa_console
715#else
716#define PXA_CONSOLE NULL
717#endif
718
719static const struct uart_ops serial_pxa_pops = {
720 .tx_empty = serial_pxa_tx_empty,
721 .set_mctrl = serial_pxa_set_mctrl,
722 .get_mctrl = serial_pxa_get_mctrl,
723 .stop_tx = serial_pxa_stop_tx,
724 .start_tx = serial_pxa_start_tx,
725 .stop_rx = serial_pxa_stop_rx,
726 .enable_ms = serial_pxa_enable_ms,
727 .break_ctl = serial_pxa_break_ctl,
728 .startup = serial_pxa_startup,
729 .shutdown = serial_pxa_shutdown,
730 .set_termios = serial_pxa_set_termios,
731 .pm = serial_pxa_pm,
732 .type = serial_pxa_type,
733 .release_port = serial_pxa_release_port,
734 .request_port = serial_pxa_request_port,
735 .config_port = serial_pxa_config_port,
736 .verify_port = serial_pxa_verify_port,
737#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
738 .poll_get_char = serial_pxa_get_poll_char,
739 .poll_put_char = serial_pxa_put_poll_char,
740#endif
741};
742
743static struct uart_driver serial_pxa_reg = {
744 .owner = THIS_MODULE,
745 .driver_name = "PXA serial",
746 .dev_name = "ttyS",
747 .major = TTY_MAJOR,
748 .minor = 64,
749 .nr = 4,
750 .cons = PXA_CONSOLE,
751};
752
753#ifdef CONFIG_PM
754static int serial_pxa_suspend(struct device *dev)
755{
756 struct uart_pxa_port *sport = dev_get_drvdata(dev);
757
758 if (sport)
759 uart_suspend_port(&serial_pxa_reg, &sport->port);
760
761 return 0;
762}
763
764static int serial_pxa_resume(struct device *dev)
765{
766 struct uart_pxa_port *sport = dev_get_drvdata(dev);
767
768 if (sport)
769 uart_resume_port(&serial_pxa_reg, &sport->port);
770
771 return 0;
772}
773
774static const struct dev_pm_ops serial_pxa_pm_ops = {
775 .suspend = serial_pxa_suspend,
776 .resume = serial_pxa_resume,
777};
778#endif
779
780static const struct of_device_id serial_pxa_dt_ids[] = {
781 { .compatible = "mrvl,pxa-uart", },
782 { .compatible = "mrvl,mmp-uart", },
783 {}
784};
785
786static int serial_pxa_probe_dt(struct platform_device *pdev,
787 struct uart_pxa_port *sport)
788{
789 struct device_node *np = pdev->dev.of_node;
790 int ret;
791
792 if (!np)
793 return 1;
794
795 ret = of_alias_get_id(np, "serial");
796 if (ret < 0) {
797 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
798 return ret;
799 }
800 sport->port.line = ret;
801 return 0;
802}
803
804static int serial_pxa_probe(struct platform_device *dev)
805{
806 struct uart_pxa_port *sport;
807 struct resource *mmres;
808 int ret;
809 int irq;
810
811 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
812 if (!mmres)
813 return -ENODEV;
814
815 irq = platform_get_irq(dev, 0);
816 if (irq < 0)
817 return irq;
818
819 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
820 if (!sport)
821 return -ENOMEM;
822
823 sport->clk = clk_get(&dev->dev, NULL);
824 if (IS_ERR(sport->clk)) {
825 ret = PTR_ERR(sport->clk);
826 goto err_free;
827 }
828
829 ret = clk_prepare(sport->clk);
830 if (ret) {
831 clk_put(sport->clk);
832 goto err_free;
833 }
834
835 sport->port.type = PORT_PXA;
836 sport->port.iotype = UPIO_MEM;
837 sport->port.mapbase = mmres->start;
838 sport->port.irq = irq;
839 sport->port.fifosize = 64;
840 sport->port.ops = &serial_pxa_pops;
841 sport->port.dev = &dev->dev;
842 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
843 sport->port.uartclk = clk_get_rate(sport->clk);
844 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE);
845
846 ret = serial_pxa_probe_dt(dev, sport);
847 if (ret > 0)
848 sport->port.line = dev->id;
849 else if (ret < 0)
850 goto err_clk;
851 if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
852 dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
853 ret = -EINVAL;
854 goto err_clk;
855 }
856 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
857
858 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
859 if (!sport->port.membase) {
860 ret = -ENOMEM;
861 goto err_clk;
862 }
863
864 serial_pxa_ports[sport->port.line] = sport;
865
866 uart_add_one_port(&serial_pxa_reg, &sport->port);
867 platform_set_drvdata(dev, sport);
868
869 return 0;
870
871 err_clk:
872 clk_unprepare(sport->clk);
873 clk_put(sport->clk);
874 err_free:
875 kfree(sport);
876 return ret;
877}
878
879static struct platform_driver serial_pxa_driver = {
880 .probe = serial_pxa_probe,
881
882 .driver = {
883 .name = "pxa2xx-uart",
884#ifdef CONFIG_PM
885 .pm = &serial_pxa_pm_ops,
886#endif
887 .suppress_bind_attrs = true,
888 .of_match_table = serial_pxa_dt_ids,
889 },
890};
891
892
893/* 8250 driver for PXA serial ports should be used */
894static int __init serial_pxa_init(void)
895{
896 int ret;
897
898 ret = uart_register_driver(&serial_pxa_reg);
899 if (ret != 0)
900 return ret;
901
902 ret = platform_driver_register(&serial_pxa_driver);
903 if (ret != 0)
904 uart_unregister_driver(&serial_pxa_reg);
905
906 return ret;
907}
908device_initcall(serial_pxa_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Based on drivers/serial/8250.c by Russell King.
4 *
5 * Author: Nicolas Pitre
6 * Created: Feb 20, 2003
7 * Copyright: (C) 2003 Monta Vista Software, Inc.
8 *
9 * Note 1: This driver is made separate from the already too overloaded
10 * 8250.c because it needs some kirks of its own and that'll make it
11 * easier to add DMA support.
12 *
13 * Note 2: I'm too sick of device allocation policies for serial ports.
14 * If someone else wants to request an "official" allocation of major/minor
15 * for this driver please be my guest. And don't forget that new hardware
16 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17 * hope for a better port registration and dynamic device allocation scheme
18 * with the serial core maintainer satisfaction to appear soon.
19 */
20
21
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/sysrq.h>
26#include <linux/serial_reg.h>
27#include <linux/circ_buf.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/of.h>
31#include <linux/platform_device.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_core.h>
35#include <linux/clk.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38
39#define PXA_NAME_LEN 8
40
41struct uart_pxa_port {
42 struct uart_port port;
43 unsigned char ier;
44 unsigned char lcr;
45 unsigned char mcr;
46 unsigned int lsr_break_flag;
47 struct clk *clk;
48 char name[PXA_NAME_LEN];
49};
50
51static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
52{
53 offset <<= 2;
54 return readl(up->port.membase + offset);
55}
56
57static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
58{
59 offset <<= 2;
60 writel(value, up->port.membase + offset);
61}
62
63static void serial_pxa_enable_ms(struct uart_port *port)
64{
65 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
66
67 up->ier |= UART_IER_MSI;
68 serial_out(up, UART_IER, up->ier);
69}
70
71static void serial_pxa_stop_tx(struct uart_port *port)
72{
73 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
74
75 if (up->ier & UART_IER_THRI) {
76 up->ier &= ~UART_IER_THRI;
77 serial_out(up, UART_IER, up->ier);
78 }
79}
80
81static void serial_pxa_stop_rx(struct uart_port *port)
82{
83 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
84
85 up->ier &= ~UART_IER_RLSI;
86 up->port.read_status_mask &= ~UART_LSR_DR;
87 serial_out(up, UART_IER, up->ier);
88}
89
90static inline void receive_chars(struct uart_pxa_port *up, int *status)
91{
92 unsigned int ch, flag;
93 int max_count = 256;
94
95 do {
96 /* work around Errata #20 according to
97 * Intel(R) PXA27x Processor Family
98 * Specification Update (May 2005)
99 *
100 * Step 2
101 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
102 */
103 up->ier &= ~UART_IER_RTOIE;
104 serial_out(up, UART_IER, up->ier);
105
106 ch = serial_in(up, UART_RX);
107 flag = TTY_NORMAL;
108 up->port.icount.rx++;
109
110 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
111 UART_LSR_FE | UART_LSR_OE))) {
112 /*
113 * For statistics only
114 */
115 if (*status & UART_LSR_BI) {
116 *status &= ~(UART_LSR_FE | UART_LSR_PE);
117 up->port.icount.brk++;
118 /*
119 * We do the SysRQ and SAK checking
120 * here because otherwise the break
121 * may get masked by ignore_status_mask
122 * or read_status_mask.
123 */
124 if (uart_handle_break(&up->port))
125 goto ignore_char;
126 } else if (*status & UART_LSR_PE)
127 up->port.icount.parity++;
128 else if (*status & UART_LSR_FE)
129 up->port.icount.frame++;
130 if (*status & UART_LSR_OE)
131 up->port.icount.overrun++;
132
133 /*
134 * Mask off conditions which should be ignored.
135 */
136 *status &= up->port.read_status_mask;
137
138#ifdef CONFIG_SERIAL_PXA_CONSOLE
139 if (up->port.line == up->port.cons->index) {
140 /* Recover the break flag from console xmit */
141 *status |= up->lsr_break_flag;
142 up->lsr_break_flag = 0;
143 }
144#endif
145 if (*status & UART_LSR_BI) {
146 flag = TTY_BREAK;
147 } else if (*status & UART_LSR_PE)
148 flag = TTY_PARITY;
149 else if (*status & UART_LSR_FE)
150 flag = TTY_FRAME;
151 }
152
153 if (uart_handle_sysrq_char(&up->port, ch))
154 goto ignore_char;
155
156 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
157
158 ignore_char:
159 *status = serial_in(up, UART_LSR);
160 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
161 tty_flip_buffer_push(&up->port.state->port);
162
163 /* work around Errata #20 according to
164 * Intel(R) PXA27x Processor Family
165 * Specification Update (May 2005)
166 *
167 * Step 6:
168 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
169 */
170 up->ier |= UART_IER_RTOIE;
171 serial_out(up, UART_IER, up->ier);
172}
173
174static void transmit_chars(struct uart_pxa_port *up)
175{
176 struct circ_buf *xmit = &up->port.state->xmit;
177 int count;
178
179 if (up->port.x_char) {
180 serial_out(up, UART_TX, up->port.x_char);
181 up->port.icount.tx++;
182 up->port.x_char = 0;
183 return;
184 }
185 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
186 serial_pxa_stop_tx(&up->port);
187 return;
188 }
189
190 count = up->port.fifosize / 2;
191 do {
192 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
194 up->port.icount.tx++;
195 if (uart_circ_empty(xmit))
196 break;
197 } while (--count > 0);
198
199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
200 uart_write_wakeup(&up->port);
201
202
203 if (uart_circ_empty(xmit))
204 serial_pxa_stop_tx(&up->port);
205}
206
207static void serial_pxa_start_tx(struct uart_port *port)
208{
209 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
210
211 if (!(up->ier & UART_IER_THRI)) {
212 up->ier |= UART_IER_THRI;
213 serial_out(up, UART_IER, up->ier);
214 }
215}
216
217/* should hold up->port.lock */
218static inline void check_modem_status(struct uart_pxa_port *up)
219{
220 int status;
221
222 status = serial_in(up, UART_MSR);
223
224 if ((status & UART_MSR_ANY_DELTA) == 0)
225 return;
226
227 if (status & UART_MSR_TERI)
228 up->port.icount.rng++;
229 if (status & UART_MSR_DDSR)
230 up->port.icount.dsr++;
231 if (status & UART_MSR_DDCD)
232 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
233 if (status & UART_MSR_DCTS)
234 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
235
236 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
237}
238
239/*
240 * This handles the interrupt from one port.
241 */
242static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
243{
244 struct uart_pxa_port *up = dev_id;
245 unsigned int iir, lsr;
246
247 iir = serial_in(up, UART_IIR);
248 if (iir & UART_IIR_NO_INT)
249 return IRQ_NONE;
250 spin_lock(&up->port.lock);
251 lsr = serial_in(up, UART_LSR);
252 if (lsr & UART_LSR_DR)
253 receive_chars(up, &lsr);
254 check_modem_status(up);
255 if (lsr & UART_LSR_THRE)
256 transmit_chars(up);
257 spin_unlock(&up->port.lock);
258 return IRQ_HANDLED;
259}
260
261static unsigned int serial_pxa_tx_empty(struct uart_port *port)
262{
263 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
264 unsigned long flags;
265 unsigned int ret;
266
267 spin_lock_irqsave(&up->port.lock, flags);
268 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
269 spin_unlock_irqrestore(&up->port.lock, flags);
270
271 return ret;
272}
273
274static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
275{
276 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
277 unsigned char status;
278 unsigned int ret;
279
280 status = serial_in(up, UART_MSR);
281
282 ret = 0;
283 if (status & UART_MSR_DCD)
284 ret |= TIOCM_CAR;
285 if (status & UART_MSR_RI)
286 ret |= TIOCM_RNG;
287 if (status & UART_MSR_DSR)
288 ret |= TIOCM_DSR;
289 if (status & UART_MSR_CTS)
290 ret |= TIOCM_CTS;
291 return ret;
292}
293
294static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
295{
296 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
297 unsigned char mcr = 0;
298
299 if (mctrl & TIOCM_RTS)
300 mcr |= UART_MCR_RTS;
301 if (mctrl & TIOCM_DTR)
302 mcr |= UART_MCR_DTR;
303 if (mctrl & TIOCM_OUT1)
304 mcr |= UART_MCR_OUT1;
305 if (mctrl & TIOCM_OUT2)
306 mcr |= UART_MCR_OUT2;
307 if (mctrl & TIOCM_LOOP)
308 mcr |= UART_MCR_LOOP;
309
310 mcr |= up->mcr;
311
312 serial_out(up, UART_MCR, mcr);
313}
314
315static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
316{
317 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
318 unsigned long flags;
319
320 spin_lock_irqsave(&up->port.lock, flags);
321 if (break_state == -1)
322 up->lcr |= UART_LCR_SBC;
323 else
324 up->lcr &= ~UART_LCR_SBC;
325 serial_out(up, UART_LCR, up->lcr);
326 spin_unlock_irqrestore(&up->port.lock, flags);
327}
328
329static int serial_pxa_startup(struct uart_port *port)
330{
331 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
332 unsigned long flags;
333 int retval;
334
335 if (port->line == 3) /* HWUART */
336 up->mcr |= UART_MCR_AFE;
337 else
338 up->mcr = 0;
339
340 up->port.uartclk = clk_get_rate(up->clk);
341
342 /*
343 * Allocate the IRQ
344 */
345 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
346 if (retval)
347 return retval;
348
349 /*
350 * Clear the FIFO buffers and disable them.
351 * (they will be reenabled in set_termios())
352 */
353 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
354 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
355 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
356 serial_out(up, UART_FCR, 0);
357
358 /*
359 * Clear the interrupt registers.
360 */
361 (void) serial_in(up, UART_LSR);
362 (void) serial_in(up, UART_RX);
363 (void) serial_in(up, UART_IIR);
364 (void) serial_in(up, UART_MSR);
365
366 /*
367 * Now, initialize the UART
368 */
369 serial_out(up, UART_LCR, UART_LCR_WLEN8);
370
371 spin_lock_irqsave(&up->port.lock, flags);
372 up->port.mctrl |= TIOCM_OUT2;
373 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
374 spin_unlock_irqrestore(&up->port.lock, flags);
375
376 /*
377 * Finally, enable interrupts. Note: Modem status interrupts
378 * are set via set_termios(), which will be occurring imminently
379 * anyway, so we don't enable them here.
380 */
381 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
382 serial_out(up, UART_IER, up->ier);
383
384 /*
385 * And clear the interrupt registers again for luck.
386 */
387 (void) serial_in(up, UART_LSR);
388 (void) serial_in(up, UART_RX);
389 (void) serial_in(up, UART_IIR);
390 (void) serial_in(up, UART_MSR);
391
392 return 0;
393}
394
395static void serial_pxa_shutdown(struct uart_port *port)
396{
397 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
398 unsigned long flags;
399
400 free_irq(up->port.irq, up);
401
402 /*
403 * Disable interrupts from this port
404 */
405 up->ier = 0;
406 serial_out(up, UART_IER, 0);
407
408 spin_lock_irqsave(&up->port.lock, flags);
409 up->port.mctrl &= ~TIOCM_OUT2;
410 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
411 spin_unlock_irqrestore(&up->port.lock, flags);
412
413 /*
414 * Disable break condition and FIFOs
415 */
416 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
417 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
418 UART_FCR_CLEAR_RCVR |
419 UART_FCR_CLEAR_XMIT);
420 serial_out(up, UART_FCR, 0);
421}
422
423static void
424serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
425 struct ktermios *old)
426{
427 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
428 unsigned char cval, fcr = 0;
429 unsigned long flags;
430 unsigned int baud, quot;
431 unsigned int dll;
432
433 switch (termios->c_cflag & CSIZE) {
434 case CS5:
435 cval = UART_LCR_WLEN5;
436 break;
437 case CS6:
438 cval = UART_LCR_WLEN6;
439 break;
440 case CS7:
441 cval = UART_LCR_WLEN7;
442 break;
443 default:
444 case CS8:
445 cval = UART_LCR_WLEN8;
446 break;
447 }
448
449 if (termios->c_cflag & CSTOPB)
450 cval |= UART_LCR_STOP;
451 if (termios->c_cflag & PARENB)
452 cval |= UART_LCR_PARITY;
453 if (!(termios->c_cflag & PARODD))
454 cval |= UART_LCR_EPAR;
455
456 /*
457 * Ask the core to calculate the divisor for us.
458 */
459 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
460 quot = uart_get_divisor(port, baud);
461
462 if ((up->port.uartclk / quot) < (2400 * 16))
463 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
464 else if ((up->port.uartclk / quot) < (230400 * 16))
465 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
466 else
467 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
468
469 /*
470 * Ok, we're now changing the port state. Do it with
471 * interrupts disabled.
472 */
473 spin_lock_irqsave(&up->port.lock, flags);
474
475 /*
476 * Ensure the port will be enabled.
477 * This is required especially for serial console.
478 */
479 up->ier |= UART_IER_UUE;
480
481 /*
482 * Update the per-port timeout.
483 */
484 uart_update_timeout(port, termios->c_cflag, baud);
485
486 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
487 if (termios->c_iflag & INPCK)
488 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
489 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
490 up->port.read_status_mask |= UART_LSR_BI;
491
492 /*
493 * Characters to ignore
494 */
495 up->port.ignore_status_mask = 0;
496 if (termios->c_iflag & IGNPAR)
497 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
498 if (termios->c_iflag & IGNBRK) {
499 up->port.ignore_status_mask |= UART_LSR_BI;
500 /*
501 * If we're ignoring parity and break indicators,
502 * ignore overruns too (for real raw support).
503 */
504 if (termios->c_iflag & IGNPAR)
505 up->port.ignore_status_mask |= UART_LSR_OE;
506 }
507
508 /*
509 * ignore all characters if CREAD is not set
510 */
511 if ((termios->c_cflag & CREAD) == 0)
512 up->port.ignore_status_mask |= UART_LSR_DR;
513
514 /*
515 * CTS flow control flag and modem status interrupts
516 */
517 up->ier &= ~UART_IER_MSI;
518 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
519 up->ier |= UART_IER_MSI;
520
521 serial_out(up, UART_IER, up->ier);
522
523 if (termios->c_cflag & CRTSCTS)
524 up->mcr |= UART_MCR_AFE;
525 else
526 up->mcr &= ~UART_MCR_AFE;
527
528 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
529 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
530
531 /*
532 * work around Errata #75 according to Intel(R) PXA27x Processor Family
533 * Specification Update (Nov 2005)
534 */
535 dll = serial_in(up, UART_DLL);
536 WARN_ON(dll != (quot & 0xff));
537
538 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
539 serial_out(up, UART_LCR, cval); /* reset DLAB */
540 up->lcr = cval; /* Save LCR */
541 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
542 serial_out(up, UART_FCR, fcr);
543 spin_unlock_irqrestore(&up->port.lock, flags);
544}
545
546static void
547serial_pxa_pm(struct uart_port *port, unsigned int state,
548 unsigned int oldstate)
549{
550 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
551
552 if (!state)
553 clk_prepare_enable(up->clk);
554 else
555 clk_disable_unprepare(up->clk);
556}
557
558static void serial_pxa_release_port(struct uart_port *port)
559{
560}
561
562static int serial_pxa_request_port(struct uart_port *port)
563{
564 return 0;
565}
566
567static void serial_pxa_config_port(struct uart_port *port, int flags)
568{
569 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
570 up->port.type = PORT_PXA;
571}
572
573static int
574serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
575{
576 /* we don't want the core code to modify any port params */
577 return -EINVAL;
578}
579
580static const char *
581serial_pxa_type(struct uart_port *port)
582{
583 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
584 return up->name;
585}
586
587static struct uart_pxa_port *serial_pxa_ports[4];
588static struct uart_driver serial_pxa_reg;
589
590#ifdef CONFIG_SERIAL_PXA_CONSOLE
591
592#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
593
594/*
595 * Wait for transmitter & holding register to empty
596 */
597static void wait_for_xmitr(struct uart_pxa_port *up)
598{
599 unsigned int status, tmout = 10000;
600
601 /* Wait up to 10ms for the character(s) to be sent. */
602 do {
603 status = serial_in(up, UART_LSR);
604
605 if (status & UART_LSR_BI)
606 up->lsr_break_flag = UART_LSR_BI;
607
608 if (--tmout == 0)
609 break;
610 udelay(1);
611 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
612
613 /* Wait up to 1s for flow control if necessary */
614 if (up->port.flags & UPF_CONS_FLOW) {
615 tmout = 1000000;
616 while (--tmout &&
617 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
618 udelay(1);
619 }
620}
621
622static void serial_pxa_console_putchar(struct uart_port *port, int ch)
623{
624 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
625
626 wait_for_xmitr(up);
627 serial_out(up, UART_TX, ch);
628}
629
630/*
631 * Print a string to the serial port trying not to disturb
632 * any possible real use of the port...
633 *
634 * The console_lock must be held when we get here.
635 */
636static void
637serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
638{
639 struct uart_pxa_port *up = serial_pxa_ports[co->index];
640 unsigned int ier;
641 unsigned long flags;
642 int locked = 1;
643
644 clk_enable(up->clk);
645 local_irq_save(flags);
646 if (up->port.sysrq)
647 locked = 0;
648 else if (oops_in_progress)
649 locked = spin_trylock(&up->port.lock);
650 else
651 spin_lock(&up->port.lock);
652
653 /*
654 * First save the IER then disable the interrupts
655 */
656 ier = serial_in(up, UART_IER);
657 serial_out(up, UART_IER, UART_IER_UUE);
658
659 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
660
661 /*
662 * Finally, wait for transmitter to become empty
663 * and restore the IER
664 */
665 wait_for_xmitr(up);
666 serial_out(up, UART_IER, ier);
667
668 if (locked)
669 spin_unlock(&up->port.lock);
670 local_irq_restore(flags);
671 clk_disable(up->clk);
672
673}
674
675#ifdef CONFIG_CONSOLE_POLL
676/*
677 * Console polling routines for writing and reading from the uart while
678 * in an interrupt or debug context.
679 */
680
681static int serial_pxa_get_poll_char(struct uart_port *port)
682{
683 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
684 unsigned char lsr = serial_in(up, UART_LSR);
685
686 while (!(lsr & UART_LSR_DR))
687 lsr = serial_in(up, UART_LSR);
688
689 return serial_in(up, UART_RX);
690}
691
692
693static void serial_pxa_put_poll_char(struct uart_port *port,
694 unsigned char c)
695{
696 unsigned int ier;
697 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
698
699 /*
700 * First save the IER then disable the interrupts
701 */
702 ier = serial_in(up, UART_IER);
703 serial_out(up, UART_IER, UART_IER_UUE);
704
705 wait_for_xmitr(up);
706 /*
707 * Send the character out.
708 */
709 serial_out(up, UART_TX, c);
710
711 /*
712 * Finally, wait for transmitter to become empty
713 * and restore the IER
714 */
715 wait_for_xmitr(up);
716 serial_out(up, UART_IER, ier);
717}
718
719#endif /* CONFIG_CONSOLE_POLL */
720
721static int __init
722serial_pxa_console_setup(struct console *co, char *options)
723{
724 struct uart_pxa_port *up;
725 int baud = 9600;
726 int bits = 8;
727 int parity = 'n';
728 int flow = 'n';
729
730 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
731 co->index = 0;
732 up = serial_pxa_ports[co->index];
733 if (!up)
734 return -ENODEV;
735
736 if (options)
737 uart_parse_options(options, &baud, &parity, &bits, &flow);
738
739 return uart_set_options(&up->port, co, baud, parity, bits, flow);
740}
741
742static struct console serial_pxa_console = {
743 .name = "ttyS",
744 .write = serial_pxa_console_write,
745 .device = uart_console_device,
746 .setup = serial_pxa_console_setup,
747 .flags = CON_PRINTBUFFER,
748 .index = -1,
749 .data = &serial_pxa_reg,
750};
751
752#define PXA_CONSOLE &serial_pxa_console
753#else
754#define PXA_CONSOLE NULL
755#endif
756
757static const struct uart_ops serial_pxa_pops = {
758 .tx_empty = serial_pxa_tx_empty,
759 .set_mctrl = serial_pxa_set_mctrl,
760 .get_mctrl = serial_pxa_get_mctrl,
761 .stop_tx = serial_pxa_stop_tx,
762 .start_tx = serial_pxa_start_tx,
763 .stop_rx = serial_pxa_stop_rx,
764 .enable_ms = serial_pxa_enable_ms,
765 .break_ctl = serial_pxa_break_ctl,
766 .startup = serial_pxa_startup,
767 .shutdown = serial_pxa_shutdown,
768 .set_termios = serial_pxa_set_termios,
769 .pm = serial_pxa_pm,
770 .type = serial_pxa_type,
771 .release_port = serial_pxa_release_port,
772 .request_port = serial_pxa_request_port,
773 .config_port = serial_pxa_config_port,
774 .verify_port = serial_pxa_verify_port,
775#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
776 .poll_get_char = serial_pxa_get_poll_char,
777 .poll_put_char = serial_pxa_put_poll_char,
778#endif
779};
780
781static struct uart_driver serial_pxa_reg = {
782 .owner = THIS_MODULE,
783 .driver_name = "PXA serial",
784 .dev_name = "ttyS",
785 .major = TTY_MAJOR,
786 .minor = 64,
787 .nr = 4,
788 .cons = PXA_CONSOLE,
789};
790
791#ifdef CONFIG_PM
792static int serial_pxa_suspend(struct device *dev)
793{
794 struct uart_pxa_port *sport = dev_get_drvdata(dev);
795
796 if (sport)
797 uart_suspend_port(&serial_pxa_reg, &sport->port);
798
799 return 0;
800}
801
802static int serial_pxa_resume(struct device *dev)
803{
804 struct uart_pxa_port *sport = dev_get_drvdata(dev);
805
806 if (sport)
807 uart_resume_port(&serial_pxa_reg, &sport->port);
808
809 return 0;
810}
811
812static const struct dev_pm_ops serial_pxa_pm_ops = {
813 .suspend = serial_pxa_suspend,
814 .resume = serial_pxa_resume,
815};
816#endif
817
818static const struct of_device_id serial_pxa_dt_ids[] = {
819 { .compatible = "mrvl,pxa-uart", },
820 { .compatible = "mrvl,mmp-uart", },
821 {}
822};
823
824static int serial_pxa_probe_dt(struct platform_device *pdev,
825 struct uart_pxa_port *sport)
826{
827 struct device_node *np = pdev->dev.of_node;
828 int ret;
829
830 if (!np)
831 return 1;
832
833 ret = of_alias_get_id(np, "serial");
834 if (ret < 0) {
835 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
836 return ret;
837 }
838 sport->port.line = ret;
839 return 0;
840}
841
842static int serial_pxa_probe(struct platform_device *dev)
843{
844 struct uart_pxa_port *sport;
845 struct resource *mmres, *irqres;
846 int ret;
847
848 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
849 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
850 if (!mmres || !irqres)
851 return -ENODEV;
852
853 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
854 if (!sport)
855 return -ENOMEM;
856
857 sport->clk = clk_get(&dev->dev, NULL);
858 if (IS_ERR(sport->clk)) {
859 ret = PTR_ERR(sport->clk);
860 goto err_free;
861 }
862
863 ret = clk_prepare(sport->clk);
864 if (ret) {
865 clk_put(sport->clk);
866 goto err_free;
867 }
868
869 sport->port.type = PORT_PXA;
870 sport->port.iotype = UPIO_MEM;
871 sport->port.mapbase = mmres->start;
872 sport->port.irq = irqres->start;
873 sport->port.fifosize = 64;
874 sport->port.ops = &serial_pxa_pops;
875 sport->port.dev = &dev->dev;
876 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
877 sport->port.uartclk = clk_get_rate(sport->clk);
878 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE);
879
880 ret = serial_pxa_probe_dt(dev, sport);
881 if (ret > 0)
882 sport->port.line = dev->id;
883 else if (ret < 0)
884 goto err_clk;
885 if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
886 dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
887 ret = -EINVAL;
888 goto err_clk;
889 }
890 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
891
892 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
893 if (!sport->port.membase) {
894 ret = -ENOMEM;
895 goto err_clk;
896 }
897
898 serial_pxa_ports[sport->port.line] = sport;
899
900 uart_add_one_port(&serial_pxa_reg, &sport->port);
901 platform_set_drvdata(dev, sport);
902
903 return 0;
904
905 err_clk:
906 clk_unprepare(sport->clk);
907 clk_put(sport->clk);
908 err_free:
909 kfree(sport);
910 return ret;
911}
912
913static struct platform_driver serial_pxa_driver = {
914 .probe = serial_pxa_probe,
915
916 .driver = {
917 .name = "pxa2xx-uart",
918#ifdef CONFIG_PM
919 .pm = &serial_pxa_pm_ops,
920#endif
921 .suppress_bind_attrs = true,
922 .of_match_table = serial_pxa_dt_ids,
923 },
924};
925
926
927/* 8250 driver for PXA serial ports should be used */
928static int __init serial_pxa_init(void)
929{
930 int ret;
931
932 ret = uart_register_driver(&serial_pxa_reg);
933 if (ret != 0)
934 return ret;
935
936 ret = platform_driver_register(&serial_pxa_driver);
937 if (ret != 0)
938 uart_unregister_driver(&serial_pxa_reg);
939
940 return ret;
941}
942device_initcall(serial_pxa_init);