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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/console.h>
22#include <linux/serial.h>
23#include <linux/serial_reg.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/platform_device.h>
29#include <linux/io.h>
30#include <linux/clk.h>
31#include <linux/serial_core.h>
32#include <linux/irq.h>
33#include <linux/pm_runtime.h>
34#include <linux/pm_wakeirq.h>
35#include <linux/of.h>
36#include <linux/of_irq.h>
37#include <linux/gpio/consumer.h>
38#include <linux/platform_data/serial-omap.h>
39
40#define OMAP_MAX_HSUART_PORTS 10
41
42#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
43
44#define OMAP_UART_REV_42 0x0402
45#define OMAP_UART_REV_46 0x0406
46#define OMAP_UART_REV_52 0x0502
47#define OMAP_UART_REV_63 0x0603
48
49#define OMAP_UART_TX_WAKEUP_EN BIT(7)
50
51/* Feature flags */
52#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
53
54#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
55#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
56
57#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
58
59/* SCR register bitmasks */
60#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
61#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
62#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
63
64/* FCR register bitmasks */
65#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
66#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
67
68/* MVR register bitmasks */
69#define OMAP_UART_MVR_SCHEME_SHIFT 30
70
71#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
72#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
73#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
74
75#define OMAP_UART_MVR_MAJ_MASK 0x700
76#define OMAP_UART_MVR_MAJ_SHIFT 8
77#define OMAP_UART_MVR_MIN_MASK 0x3f
78
79#define OMAP_UART_DMA_CH_FREE -1
80
81#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
82#define OMAP_MODE13X_SPEED 230400
83
84/* WER = 0x7F
85 * Enable module level wakeup in WER reg
86 */
87#define OMAP_UART_WER_MOD_WKUP 0x7F
88
89/* Enable XON/XOFF flow control on output */
90#define OMAP_UART_SW_TX 0x08
91
92/* Enable XON/XOFF flow control on input */
93#define OMAP_UART_SW_RX 0x02
94
95#define OMAP_UART_SW_CLR 0xF0
96
97#define OMAP_UART_TCR_TRIG 0x0F
98
99struct uart_omap_dma {
100 u8 uart_dma_tx;
101 u8 uart_dma_rx;
102 int rx_dma_channel;
103 int tx_dma_channel;
104 dma_addr_t rx_buf_dma_phys;
105 dma_addr_t tx_buf_dma_phys;
106 unsigned int uart_base;
107 /*
108 * Buffer for rx dma. It is not required for tx because the buffer
109 * comes from port structure.
110 */
111 unsigned char *rx_buf;
112 unsigned int prev_rx_dma_pos;
113 int tx_buf_size;
114 int tx_dma_used;
115 int rx_dma_used;
116 spinlock_t tx_lock;
117 spinlock_t rx_lock;
118 /* timer to poll activity on rx dma */
119 struct timer_list rx_timer;
120 unsigned int rx_buf_size;
121 unsigned int rx_poll_rate;
122 unsigned int rx_timeout;
123};
124
125struct uart_omap_port {
126 struct uart_port port;
127 struct uart_omap_dma uart_dma;
128 struct device *dev;
129 int wakeirq;
130
131 unsigned char ier;
132 unsigned char lcr;
133 unsigned char mcr;
134 unsigned char fcr;
135 unsigned char efr;
136 unsigned char dll;
137 unsigned char dlh;
138 unsigned char mdr1;
139 unsigned char scr;
140 unsigned char wer;
141
142 int use_dma;
143 /*
144 * Some bits in registers are cleared on a read, so they must
145 * be saved whenever the register is read, but the bits will not
146 * be immediately processed.
147 */
148 unsigned int lsr_break_flag;
149 unsigned char msr_saved_flags;
150 char name[20];
151 unsigned long port_activity;
152 int context_loss_cnt;
153 u32 errata;
154 u32 features;
155
156 struct gpio_desc *rts_gpiod;
157
158 struct pm_qos_request pm_qos_request;
159 u32 latency;
160 u32 calc_latency;
161 struct work_struct qos_work;
162 bool is_suspending;
163
164 unsigned int rs485_tx_filter_count;
165};
166
167#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
168
169static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
170
171/* Forward declaration of functions */
172static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
173
174static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
175{
176 offset <<= up->port.regshift;
177 return readw(up->port.membase + offset);
178}
179
180static inline void serial_out(struct uart_omap_port *up, int offset, int value)
181{
182 offset <<= up->port.regshift;
183 writew(value, up->port.membase + offset);
184}
185
186static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
187{
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
191 serial_out(up, UART_FCR, 0);
192}
193
194#ifdef CONFIG_PM
195static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
196{
197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
198
199 if (!pdata || !pdata->get_context_loss_count)
200 return -EINVAL;
201
202 return pdata->get_context_loss_count(up->dev);
203}
204
205/* REVISIT: Remove this when omap3 boots in device tree only mode */
206static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
207{
208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
209
210 if (!pdata || !pdata->enable_wakeup)
211 return;
212
213 pdata->enable_wakeup(up->dev, enable);
214}
215#endif /* CONFIG_PM */
216
217/*
218 * Calculate the absolute difference between the desired and actual baud
219 * rate for the given mode.
220 */
221static inline int calculate_baud_abs_diff(struct uart_port *port,
222 unsigned int baud, unsigned int mode)
223{
224 unsigned int n = port->uartclk / (mode * baud);
225
226 if (n == 0)
227 n = 1;
228
229 return abs_diff(baud, port->uartclk / (mode * n));
230}
231
232/*
233 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
234 * @port: uart port info
235 * @baud: baudrate for which mode needs to be determined
236 *
237 * Returns true if baud rate is MODE16X and false if MODE13X
238 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
239 * and Error Rates" determines modes not for all common baud rates.
240 * E.g. for 1000000 baud rate mode must be 16x, but according to that
241 * table it's determined as 13x.
242 */
243static bool
244serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
245{
246 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
247 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
248
249 return (abs_diff_13 >= abs_diff_16);
250}
251
252/*
253 * serial_omap_get_divisor - calculate divisor value
254 * @port: uart port info
255 * @baud: baudrate for which divisor needs to be calculated.
256 */
257static unsigned int
258serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
259{
260 unsigned int mode;
261
262 if (!serial_omap_baud_is_mode16(port, baud))
263 mode = 13;
264 else
265 mode = 16;
266 return port->uartclk/(mode * baud);
267}
268
269static void serial_omap_enable_ms(struct uart_port *port)
270{
271 struct uart_omap_port *up = to_uart_omap_port(port);
272
273 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
274
275 up->ier |= UART_IER_MSI;
276 serial_out(up, UART_IER, up->ier);
277}
278
279static void serial_omap_stop_tx(struct uart_port *port)
280{
281 struct uart_omap_port *up = to_uart_omap_port(port);
282 int res;
283
284 /* Handle RS-485 */
285 if (port->rs485.flags & SER_RS485_ENABLED) {
286 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
287 /* THR interrupt is fired when both TX FIFO and TX
288 * shift register are empty. This means there's nothing
289 * left to transmit now, so make sure the THR interrupt
290 * is fired when TX FIFO is below the trigger level,
291 * disable THR interrupts and toggle the RS-485 GPIO
292 * data direction pin if needed.
293 */
294 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
295 serial_out(up, UART_OMAP_SCR, up->scr);
296 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
297 1 : 0;
298 if (gpiod_get_value(up->rts_gpiod) != res) {
299 if (port->rs485.delay_rts_after_send > 0)
300 mdelay(
301 port->rs485.delay_rts_after_send);
302 gpiod_set_value(up->rts_gpiod, res);
303 }
304 } else {
305 /* We're asked to stop, but there's still stuff in the
306 * UART FIFO, so make sure the THR interrupt is fired
307 * when both TX FIFO and TX shift register are empty.
308 * The next THR interrupt (if no transmission is started
309 * in the meantime) will indicate the end of a
310 * transmission. Therefore we _don't_ disable THR
311 * interrupts in this situation.
312 */
313 up->scr |= OMAP_UART_SCR_TX_EMPTY;
314 serial_out(up, UART_OMAP_SCR, up->scr);
315 return;
316 }
317 }
318
319 if (up->ier & UART_IER_THRI) {
320 up->ier &= ~UART_IER_THRI;
321 serial_out(up, UART_IER, up->ier);
322 }
323}
324
325static void serial_omap_stop_rx(struct uart_port *port)
326{
327 struct uart_omap_port *up = to_uart_omap_port(port);
328
329 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
330 up->port.read_status_mask &= ~UART_LSR_DR;
331 serial_out(up, UART_IER, up->ier);
332}
333
334static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch)
335{
336 serial_out(up, UART_TX, ch);
337
338 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
339 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
340 up->rs485_tx_filter_count++;
341}
342
343static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
344{
345 u8 ch;
346
347 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4,
348 true,
349 serial_omap_put_char(up, ch),
350 ({}));
351}
352
353static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
354{
355 if (!(up->ier & UART_IER_THRI)) {
356 up->ier |= UART_IER_THRI;
357 serial_out(up, UART_IER, up->ier);
358 }
359}
360
361static void serial_omap_start_tx(struct uart_port *port)
362{
363 struct uart_omap_port *up = to_uart_omap_port(port);
364 int res;
365
366 /* Handle RS-485 */
367 if (port->rs485.flags & SER_RS485_ENABLED) {
368 /* Fire THR interrupts when FIFO is below trigger level */
369 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
370 serial_out(up, UART_OMAP_SCR, up->scr);
371
372 /* if rts not already enabled */
373 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
374 if (gpiod_get_value(up->rts_gpiod) != res) {
375 gpiod_set_value(up->rts_gpiod, res);
376 if (port->rs485.delay_rts_before_send > 0)
377 mdelay(port->rs485.delay_rts_before_send);
378 }
379 }
380
381 if ((port->rs485.flags & SER_RS485_ENABLED) &&
382 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
383 up->rs485_tx_filter_count = 0;
384
385 serial_omap_enable_ier_thri(up);
386}
387
388static void serial_omap_throttle(struct uart_port *port)
389{
390 struct uart_omap_port *up = to_uart_omap_port(port);
391 unsigned long flags;
392
393 uart_port_lock_irqsave(&up->port, &flags);
394 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
395 serial_out(up, UART_IER, up->ier);
396 uart_port_unlock_irqrestore(&up->port, flags);
397}
398
399static void serial_omap_unthrottle(struct uart_port *port)
400{
401 struct uart_omap_port *up = to_uart_omap_port(port);
402 unsigned long flags;
403
404 uart_port_lock_irqsave(&up->port, &flags);
405 up->ier |= UART_IER_RLSI | UART_IER_RDI;
406 serial_out(up, UART_IER, up->ier);
407 uart_port_unlock_irqrestore(&up->port, flags);
408}
409
410static unsigned int check_modem_status(struct uart_omap_port *up)
411{
412 unsigned int status;
413
414 status = serial_in(up, UART_MSR);
415 status |= up->msr_saved_flags;
416 up->msr_saved_flags = 0;
417 if ((status & UART_MSR_ANY_DELTA) == 0)
418 return status;
419
420 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
421 up->port.state != NULL) {
422 if (status & UART_MSR_TERI)
423 up->port.icount.rng++;
424 if (status & UART_MSR_DDSR)
425 up->port.icount.dsr++;
426 if (status & UART_MSR_DDCD)
427 uart_handle_dcd_change
428 (&up->port, status & UART_MSR_DCD);
429 if (status & UART_MSR_DCTS)
430 uart_handle_cts_change
431 (&up->port, status & UART_MSR_CTS);
432 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
433 }
434
435 return status;
436}
437
438static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
439{
440 u8 flag;
441
442 /*
443 * Read one data character out to avoid stalling the receiver according
444 * to the table 23-246 of the omap4 TRM.
445 */
446 if (likely(lsr & UART_LSR_DR)) {
447 serial_in(up, UART_RX);
448 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
449 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
450 up->rs485_tx_filter_count)
451 up->rs485_tx_filter_count--;
452 }
453
454 up->port.icount.rx++;
455 flag = TTY_NORMAL;
456
457 if (lsr & UART_LSR_BI) {
458 flag = TTY_BREAK;
459 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
460 up->port.icount.brk++;
461 /*
462 * We do the SysRQ and SAK checking
463 * here because otherwise the break
464 * may get masked by ignore_status_mask
465 * or read_status_mask.
466 */
467 if (uart_handle_break(&up->port))
468 return;
469
470 }
471
472 if (lsr & UART_LSR_PE) {
473 flag = TTY_PARITY;
474 up->port.icount.parity++;
475 }
476
477 if (lsr & UART_LSR_FE) {
478 flag = TTY_FRAME;
479 up->port.icount.frame++;
480 }
481
482 if (lsr & UART_LSR_OE)
483 up->port.icount.overrun++;
484
485#ifdef CONFIG_SERIAL_OMAP_CONSOLE
486 if (up->port.line == up->port.cons->index) {
487 /* Recover the break flag from console xmit */
488 lsr |= up->lsr_break_flag;
489 }
490#endif
491 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
492}
493
494static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
495{
496 u8 ch;
497
498 if (!(lsr & UART_LSR_DR))
499 return;
500
501 ch = serial_in(up, UART_RX);
502 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
503 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
504 up->rs485_tx_filter_count) {
505 up->rs485_tx_filter_count--;
506 return;
507 }
508
509 up->port.icount.rx++;
510
511 if (uart_handle_sysrq_char(&up->port, ch))
512 return;
513
514 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, TTY_NORMAL);
515}
516
517/**
518 * serial_omap_irq() - This handles the interrupt from one port
519 * @irq: uart port irq number
520 * @dev_id: uart port info
521 */
522static irqreturn_t serial_omap_irq(int irq, void *dev_id)
523{
524 struct uart_omap_port *up = dev_id;
525 unsigned int iir, lsr;
526 unsigned int type;
527 irqreturn_t ret = IRQ_NONE;
528 int max_count = 256;
529
530 uart_port_lock(&up->port);
531
532 do {
533 iir = serial_in(up, UART_IIR);
534 if (iir & UART_IIR_NO_INT)
535 break;
536
537 ret = IRQ_HANDLED;
538 lsr = serial_in(up, UART_LSR);
539
540 /* extract IRQ type from IIR register */
541 type = iir & 0x3e;
542
543 switch (type) {
544 case UART_IIR_MSI:
545 check_modem_status(up);
546 break;
547 case UART_IIR_THRI:
548 transmit_chars(up, lsr);
549 break;
550 case UART_IIR_RX_TIMEOUT:
551 case UART_IIR_RDI:
552 serial_omap_rdi(up, lsr);
553 break;
554 case UART_IIR_RLSI:
555 serial_omap_rlsi(up, lsr);
556 break;
557 case UART_IIR_CTS_RTS_DSR:
558 /* simply try again */
559 break;
560 case UART_IIR_XOFF:
561 default:
562 break;
563 }
564 } while (max_count--);
565
566 uart_port_unlock(&up->port);
567
568 tty_flip_buffer_push(&up->port.state->port);
569
570 up->port_activity = jiffies;
571
572 return ret;
573}
574
575static unsigned int serial_omap_tx_empty(struct uart_port *port)
576{
577 struct uart_omap_port *up = to_uart_omap_port(port);
578 unsigned long flags;
579 unsigned int ret = 0;
580
581 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
582 uart_port_lock_irqsave(&up->port, &flags);
583 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
584 uart_port_unlock_irqrestore(&up->port, flags);
585
586 return ret;
587}
588
589static unsigned int serial_omap_get_mctrl(struct uart_port *port)
590{
591 struct uart_omap_port *up = to_uart_omap_port(port);
592 unsigned int status;
593 unsigned int ret = 0;
594
595 status = check_modem_status(up);
596
597 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
598
599 if (status & UART_MSR_DCD)
600 ret |= TIOCM_CAR;
601 if (status & UART_MSR_RI)
602 ret |= TIOCM_RNG;
603 if (status & UART_MSR_DSR)
604 ret |= TIOCM_DSR;
605 if (status & UART_MSR_CTS)
606 ret |= TIOCM_CTS;
607 return ret;
608}
609
610static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
611{
612 struct uart_omap_port *up = to_uart_omap_port(port);
613 unsigned char mcr = 0, old_mcr, lcr;
614
615 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
616 if (mctrl & TIOCM_RTS)
617 mcr |= UART_MCR_RTS;
618 if (mctrl & TIOCM_DTR)
619 mcr |= UART_MCR_DTR;
620 if (mctrl & TIOCM_OUT1)
621 mcr |= UART_MCR_OUT1;
622 if (mctrl & TIOCM_OUT2)
623 mcr |= UART_MCR_OUT2;
624 if (mctrl & TIOCM_LOOP)
625 mcr |= UART_MCR_LOOP;
626
627 old_mcr = serial_in(up, UART_MCR);
628 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
629 UART_MCR_DTR | UART_MCR_RTS);
630 up->mcr = old_mcr | mcr;
631 serial_out(up, UART_MCR, up->mcr);
632
633 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
634 lcr = serial_in(up, UART_LCR);
635 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
636 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
637 up->efr |= UART_EFR_RTS;
638 else
639 up->efr &= ~UART_EFR_RTS;
640 serial_out(up, UART_EFR, up->efr);
641 serial_out(up, UART_LCR, lcr);
642}
643
644static void serial_omap_break_ctl(struct uart_port *port, int break_state)
645{
646 struct uart_omap_port *up = to_uart_omap_port(port);
647 unsigned long flags;
648
649 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
650 uart_port_lock_irqsave(&up->port, &flags);
651 if (break_state == -1)
652 up->lcr |= UART_LCR_SBC;
653 else
654 up->lcr &= ~UART_LCR_SBC;
655 serial_out(up, UART_LCR, up->lcr);
656 uart_port_unlock_irqrestore(&up->port, flags);
657}
658
659static int serial_omap_startup(struct uart_port *port)
660{
661 struct uart_omap_port *up = to_uart_omap_port(port);
662 unsigned long flags;
663 int retval;
664
665 /*
666 * Allocate the IRQ
667 */
668 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
669 up->name, up);
670 if (retval)
671 return retval;
672
673 /* Optional wake-up IRQ */
674 if (up->wakeirq) {
675 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
676 if (retval) {
677 free_irq(up->port.irq, up);
678 return retval;
679 }
680 }
681
682 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
683
684 pm_runtime_get_sync(up->dev);
685 /*
686 * Clear the FIFO buffers and disable them.
687 * (they will be reenabled in set_termios())
688 */
689 serial_omap_clear_fifos(up);
690
691 /*
692 * Clear the interrupt registers.
693 */
694 (void) serial_in(up, UART_LSR);
695 if (serial_in(up, UART_LSR) & UART_LSR_DR)
696 (void) serial_in(up, UART_RX);
697 (void) serial_in(up, UART_IIR);
698 (void) serial_in(up, UART_MSR);
699
700 /*
701 * Now, initialize the UART
702 */
703 serial_out(up, UART_LCR, UART_LCR_WLEN8);
704 uart_port_lock_irqsave(&up->port, &flags);
705 /*
706 * Most PC uarts need OUT2 raised to enable interrupts.
707 */
708 up->port.mctrl |= TIOCM_OUT2;
709 serial_omap_set_mctrl(&up->port, up->port.mctrl);
710 uart_port_unlock_irqrestore(&up->port, flags);
711
712 up->msr_saved_flags = 0;
713 /*
714 * Finally, enable interrupts. Note: Modem status interrupts
715 * are set via set_termios(), which will be occurring imminently
716 * anyway, so we don't enable them here.
717 */
718 up->ier = UART_IER_RLSI | UART_IER_RDI;
719 serial_out(up, UART_IER, up->ier);
720
721 /* Enable module level wake up */
722 up->wer = OMAP_UART_WER_MOD_WKUP;
723 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
724 up->wer |= OMAP_UART_TX_WAKEUP_EN;
725
726 serial_out(up, UART_OMAP_WER, up->wer);
727
728 up->port_activity = jiffies;
729 return 0;
730}
731
732static void serial_omap_shutdown(struct uart_port *port)
733{
734 struct uart_omap_port *up = to_uart_omap_port(port);
735 unsigned long flags;
736
737 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
738
739 /*
740 * Disable interrupts from this port
741 */
742 up->ier = 0;
743 serial_out(up, UART_IER, 0);
744
745 uart_port_lock_irqsave(&up->port, &flags);
746 up->port.mctrl &= ~TIOCM_OUT2;
747 serial_omap_set_mctrl(&up->port, up->port.mctrl);
748 uart_port_unlock_irqrestore(&up->port, flags);
749
750 /*
751 * Disable break condition and FIFOs
752 */
753 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
754 serial_omap_clear_fifos(up);
755
756 /*
757 * Read data port to reset things, and then free the irq
758 */
759 if (serial_in(up, UART_LSR) & UART_LSR_DR)
760 (void) serial_in(up, UART_RX);
761
762 pm_runtime_put_sync(up->dev);
763 free_irq(up->port.irq, up);
764 dev_pm_clear_wake_irq(up->dev);
765}
766
767static void serial_omap_uart_qos_work(struct work_struct *work)
768{
769 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
770 qos_work);
771
772 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
773}
774
775static void
776serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
777 const struct ktermios *old)
778{
779 struct uart_omap_port *up = to_uart_omap_port(port);
780 unsigned char cval = 0;
781 unsigned long flags;
782 unsigned int baud, quot;
783
784 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
785
786 if (termios->c_cflag & CSTOPB)
787 cval |= UART_LCR_STOP;
788 if (termios->c_cflag & PARENB)
789 cval |= UART_LCR_PARITY;
790 if (!(termios->c_cflag & PARODD))
791 cval |= UART_LCR_EPAR;
792 if (termios->c_cflag & CMSPAR)
793 cval |= UART_LCR_SPAR;
794
795 /*
796 * Ask the core to calculate the divisor for us.
797 */
798
799 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
800 quot = serial_omap_get_divisor(port, baud);
801
802 /* calculate wakeup latency constraint */
803 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
804 up->latency = up->calc_latency;
805 schedule_work(&up->qos_work);
806
807 up->dll = quot & 0xff;
808 up->dlh = quot >> 8;
809 up->mdr1 = UART_OMAP_MDR1_DISABLE;
810
811 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
812 UART_FCR_ENABLE_FIFO;
813
814 /*
815 * Ok, we're now changing the port state. Do it with
816 * interrupts disabled.
817 */
818 uart_port_lock_irqsave(&up->port, &flags);
819
820 /*
821 * Update the per-port timeout.
822 */
823 uart_update_timeout(port, termios->c_cflag, baud);
824
825 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
826 if (termios->c_iflag & INPCK)
827 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
828 if (termios->c_iflag & (BRKINT | PARMRK))
829 up->port.read_status_mask |= UART_LSR_BI;
830
831 /*
832 * Characters to ignore
833 */
834 up->port.ignore_status_mask = 0;
835 if (termios->c_iflag & IGNPAR)
836 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
837 if (termios->c_iflag & IGNBRK) {
838 up->port.ignore_status_mask |= UART_LSR_BI;
839 /*
840 * If we're ignoring parity and break indicators,
841 * ignore overruns too (for real raw support).
842 */
843 if (termios->c_iflag & IGNPAR)
844 up->port.ignore_status_mask |= UART_LSR_OE;
845 }
846
847 /*
848 * ignore all characters if CREAD is not set
849 */
850 if ((termios->c_cflag & CREAD) == 0)
851 up->port.ignore_status_mask |= UART_LSR_DR;
852
853 /*
854 * Modem status interrupts
855 */
856 up->ier &= ~UART_IER_MSI;
857 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
858 up->ier |= UART_IER_MSI;
859 serial_out(up, UART_IER, up->ier);
860 serial_out(up, UART_LCR, cval); /* reset DLAB */
861 up->lcr = cval;
862 up->scr = 0;
863
864 /* FIFOs and DMA Settings */
865
866 /* FCR can be changed only when the
867 * baud clock is not running
868 * DLL_REG and DLH_REG set to 0.
869 */
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
871 serial_out(up, UART_DLL, 0);
872 serial_out(up, UART_DLM, 0);
873 serial_out(up, UART_LCR, 0);
874
875 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
876
877 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
878 up->efr &= ~UART_EFR_SCD;
879 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
880
881 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
882 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
883 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
884 /* FIFO ENABLE, DMA MODE */
885
886 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
887 /*
888 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
889 * sets Enables the granularity of 1 for TRIGGER RX
890 * level. Along with setting RX FIFO trigger level
891 * to 1 (as noted below, 16 characters) and TLR[3:0]
892 * to zero this will result RX FIFO threshold level
893 * to 1 character, instead of 16 as noted in comment
894 * below.
895 */
896
897 /* Set receive FIFO threshold to 16 characters and
898 * transmit FIFO threshold to 32 spaces
899 */
900 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
901 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
902 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
903 UART_FCR_ENABLE_FIFO;
904
905 serial_out(up, UART_FCR, up->fcr);
906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
907
908 serial_out(up, UART_OMAP_SCR, up->scr);
909
910 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
911 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
912 serial_out(up, UART_MCR, up->mcr);
913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
914 serial_out(up, UART_EFR, up->efr);
915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
916
917 /* Protocol, Baud Rate, and Interrupt Settings */
918
919 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
920 serial_omap_mdr1_errataset(up, up->mdr1);
921 else
922 serial_out(up, UART_OMAP_MDR1, up->mdr1);
923
924 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
925 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
926
927 serial_out(up, UART_LCR, 0);
928 serial_out(up, UART_IER, 0);
929 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
930
931 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
932 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
933
934 serial_out(up, UART_LCR, 0);
935 serial_out(up, UART_IER, up->ier);
936 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
937
938 serial_out(up, UART_EFR, up->efr);
939 serial_out(up, UART_LCR, cval);
940
941 if (!serial_omap_baud_is_mode16(port, baud))
942 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
943 else
944 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
945
946 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
947 serial_omap_mdr1_errataset(up, up->mdr1);
948 else
949 serial_out(up, UART_OMAP_MDR1, up->mdr1);
950
951 /* Configure flow control */
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
953
954 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
955 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
956 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
957
958 /* Enable access to TCR/TLR */
959 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
960 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
961 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
962
963 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
964
965 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
966
967 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
968 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
969 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
970 up->efr |= UART_EFR_CTS;
971 } else {
972 /* Disable AUTORTS and AUTOCTS */
973 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
974 }
975
976 if (up->port.flags & UPF_SOFT_FLOW) {
977 /* clear SW control mode bits */
978 up->efr &= OMAP_UART_SW_CLR;
979
980 /*
981 * IXON Flag:
982 * Enable XON/XOFF flow control on input.
983 * Receiver compares XON1, XOFF1.
984 */
985 if (termios->c_iflag & IXON)
986 up->efr |= OMAP_UART_SW_RX;
987
988 /*
989 * IXOFF Flag:
990 * Enable XON/XOFF flow control on output.
991 * Transmit XON1, XOFF1
992 */
993 if (termios->c_iflag & IXOFF) {
994 up->port.status |= UPSTAT_AUTOXOFF;
995 up->efr |= OMAP_UART_SW_TX;
996 }
997
998 /*
999 * IXANY Flag:
1000 * Enable any character to restart output.
1001 * Operation resumes after receiving any
1002 * character after recognition of the XOFF character
1003 */
1004 if (termios->c_iflag & IXANY)
1005 up->mcr |= UART_MCR_XONANY;
1006 else
1007 up->mcr &= ~UART_MCR_XONANY;
1008 }
1009 serial_out(up, UART_MCR, up->mcr);
1010 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1011 serial_out(up, UART_EFR, up->efr);
1012 serial_out(up, UART_LCR, up->lcr);
1013
1014 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1015
1016 uart_port_unlock_irqrestore(&up->port, flags);
1017 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1018}
1019
1020static void
1021serial_omap_pm(struct uart_port *port, unsigned int state,
1022 unsigned int oldstate)
1023{
1024 struct uart_omap_port *up = to_uart_omap_port(port);
1025 unsigned char efr;
1026
1027 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1028
1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 efr = serial_in(up, UART_EFR);
1031 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1032 serial_out(up, UART_LCR, 0);
1033
1034 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1035 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1036 serial_out(up, UART_EFR, efr);
1037 serial_out(up, UART_LCR, 0);
1038}
1039
1040static void serial_omap_release_port(struct uart_port *port)
1041{
1042 dev_dbg(port->dev, "serial_omap_release_port+\n");
1043}
1044
1045static int serial_omap_request_port(struct uart_port *port)
1046{
1047 dev_dbg(port->dev, "serial_omap_request_port+\n");
1048 return 0;
1049}
1050
1051static void serial_omap_config_port(struct uart_port *port, int flags)
1052{
1053 struct uart_omap_port *up = to_uart_omap_port(port);
1054
1055 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1056 up->port.line);
1057 up->port.type = PORT_OMAP;
1058 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1059}
1060
1061static int
1062serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1063{
1064 /* we don't want the core code to modify any port params */
1065 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1066 return -EINVAL;
1067}
1068
1069static const char *
1070serial_omap_type(struct uart_port *port)
1071{
1072 struct uart_omap_port *up = to_uart_omap_port(port);
1073
1074 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1075 return up->name;
1076}
1077
1078static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1079{
1080 unsigned int status, tmout = 10000;
1081
1082 /* Wait up to 10ms for the character(s) to be sent. */
1083 do {
1084 status = serial_in(up, UART_LSR);
1085
1086 if (status & UART_LSR_BI)
1087 up->lsr_break_flag = UART_LSR_BI;
1088
1089 if (--tmout == 0)
1090 break;
1091 udelay(1);
1092 } while (!uart_lsr_tx_empty(status));
1093
1094 /* Wait up to 1s for flow control if necessary */
1095 if (up->port.flags & UPF_CONS_FLOW) {
1096 tmout = 1000000;
1097 for (tmout = 1000000; tmout; tmout--) {
1098 unsigned int msr = serial_in(up, UART_MSR);
1099
1100 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1101 if (msr & UART_MSR_CTS)
1102 break;
1103
1104 udelay(1);
1105 }
1106 }
1107}
1108
1109#ifdef CONFIG_CONSOLE_POLL
1110
1111static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1112{
1113 struct uart_omap_port *up = to_uart_omap_port(port);
1114
1115 wait_for_xmitr(up);
1116 serial_out(up, UART_TX, ch);
1117}
1118
1119static int serial_omap_poll_get_char(struct uart_port *port)
1120{
1121 struct uart_omap_port *up = to_uart_omap_port(port);
1122 unsigned int status;
1123
1124 status = serial_in(up, UART_LSR);
1125 if (!(status & UART_LSR_DR)) {
1126 status = NO_POLL_CHAR;
1127 goto out;
1128 }
1129
1130 status = serial_in(up, UART_RX);
1131
1132out:
1133 return status;
1134}
1135
1136#endif /* CONFIG_CONSOLE_POLL */
1137
1138#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1139
1140#ifdef CONFIG_SERIAL_EARLYCON
1141static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1142{
1143 offset <<= port->regshift;
1144 return readw(port->membase + offset);
1145}
1146
1147static void omap_serial_early_out(struct uart_port *port, int offset,
1148 int value)
1149{
1150 offset <<= port->regshift;
1151 writew(value, port->membase + offset);
1152}
1153
1154static void omap_serial_early_putc(struct uart_port *port, unsigned char c)
1155{
1156 unsigned int status;
1157
1158 for (;;) {
1159 status = omap_serial_early_in(port, UART_LSR);
1160 if (uart_lsr_tx_empty(status))
1161 break;
1162 cpu_relax();
1163 }
1164 omap_serial_early_out(port, UART_TX, c);
1165}
1166
1167static void early_omap_serial_write(struct console *console, const char *s,
1168 unsigned int count)
1169{
1170 struct earlycon_device *device = console->data;
1171 struct uart_port *port = &device->port;
1172
1173 uart_console_write(port, s, count, omap_serial_early_putc);
1174}
1175
1176static int __init early_omap_serial_setup(struct earlycon_device *device,
1177 const char *options)
1178{
1179 struct uart_port *port = &device->port;
1180
1181 if (!(device->port.membase || device->port.iobase))
1182 return -ENODEV;
1183
1184 port->regshift = 2;
1185 device->con->write = early_omap_serial_write;
1186 return 0;
1187}
1188
1189OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1190OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1191OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1192#endif /* CONFIG_SERIAL_EARLYCON */
1193
1194static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1195
1196static struct uart_driver serial_omap_reg;
1197
1198static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch)
1199{
1200 struct uart_omap_port *up = to_uart_omap_port(port);
1201
1202 wait_for_xmitr(up);
1203 serial_out(up, UART_TX, ch);
1204}
1205
1206static void
1207serial_omap_console_write(struct console *co, const char *s,
1208 unsigned int count)
1209{
1210 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1211 unsigned long flags;
1212 unsigned int ier;
1213 int locked = 1;
1214
1215 local_irq_save(flags);
1216 if (up->port.sysrq)
1217 locked = 0;
1218 else if (oops_in_progress)
1219 locked = uart_port_trylock(&up->port);
1220 else
1221 uart_port_lock(&up->port);
1222
1223 /*
1224 * First save the IER then disable the interrupts
1225 */
1226 ier = serial_in(up, UART_IER);
1227 serial_out(up, UART_IER, 0);
1228
1229 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1230
1231 /*
1232 * Finally, wait for transmitter to become empty
1233 * and restore the IER
1234 */
1235 wait_for_xmitr(up);
1236 serial_out(up, UART_IER, ier);
1237 /*
1238 * The receive handling will happen properly because the
1239 * receive ready bit will still be set; it is not cleared
1240 * on read. However, modem control will not, we must
1241 * call it if we have saved something in the saved flags
1242 * while processing with interrupts off.
1243 */
1244 if (up->msr_saved_flags)
1245 check_modem_status(up);
1246
1247 if (locked)
1248 uart_port_unlock(&up->port);
1249 local_irq_restore(flags);
1250}
1251
1252static int __init
1253serial_omap_console_setup(struct console *co, char *options)
1254{
1255 struct uart_omap_port *up;
1256 int baud = 115200;
1257 int bits = 8;
1258 int parity = 'n';
1259 int flow = 'n';
1260
1261 if (serial_omap_console_ports[co->index] == NULL)
1262 return -ENODEV;
1263 up = serial_omap_console_ports[co->index];
1264
1265 if (options)
1266 uart_parse_options(options, &baud, &parity, &bits, &flow);
1267
1268 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1269}
1270
1271static struct console serial_omap_console = {
1272 .name = OMAP_SERIAL_NAME,
1273 .write = serial_omap_console_write,
1274 .device = uart_console_device,
1275 .setup = serial_omap_console_setup,
1276 .flags = CON_PRINTBUFFER,
1277 .index = -1,
1278 .data = &serial_omap_reg,
1279};
1280
1281static void serial_omap_add_console_port(struct uart_omap_port *up)
1282{
1283 serial_omap_console_ports[up->port.line] = up;
1284}
1285
1286#define OMAP_CONSOLE (&serial_omap_console)
1287
1288#else
1289
1290#define OMAP_CONSOLE NULL
1291
1292static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1293{}
1294
1295#endif
1296
1297/* Enable or disable the rs485 support */
1298static int
1299serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios,
1300 struct serial_rs485 *rs485)
1301{
1302 struct uart_omap_port *up = to_uart_omap_port(port);
1303 unsigned int mode;
1304 int val;
1305
1306 /* Disable interrupts from this port */
1307 mode = up->ier;
1308 up->ier = 0;
1309 serial_out(up, UART_IER, 0);
1310
1311 /* enable / disable rts */
1312 val = (rs485->flags & SER_RS485_ENABLED) ?
1313 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1314 val = (rs485->flags & val) ? 1 : 0;
1315 gpiod_set_value(up->rts_gpiod, val);
1316
1317 /* Enable interrupts */
1318 up->ier = mode;
1319 serial_out(up, UART_IER, up->ier);
1320
1321 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1322 * TX FIFO is below the trigger level.
1323 */
1324 if (!(rs485->flags & SER_RS485_ENABLED) &&
1325 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1326 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1327 serial_out(up, UART_OMAP_SCR, up->scr);
1328 }
1329
1330 return 0;
1331}
1332
1333static const struct uart_ops serial_omap_pops = {
1334 .tx_empty = serial_omap_tx_empty,
1335 .set_mctrl = serial_omap_set_mctrl,
1336 .get_mctrl = serial_omap_get_mctrl,
1337 .stop_tx = serial_omap_stop_tx,
1338 .start_tx = serial_omap_start_tx,
1339 .throttle = serial_omap_throttle,
1340 .unthrottle = serial_omap_unthrottle,
1341 .stop_rx = serial_omap_stop_rx,
1342 .enable_ms = serial_omap_enable_ms,
1343 .break_ctl = serial_omap_break_ctl,
1344 .startup = serial_omap_startup,
1345 .shutdown = serial_omap_shutdown,
1346 .set_termios = serial_omap_set_termios,
1347 .pm = serial_omap_pm,
1348 .type = serial_omap_type,
1349 .release_port = serial_omap_release_port,
1350 .request_port = serial_omap_request_port,
1351 .config_port = serial_omap_config_port,
1352 .verify_port = serial_omap_verify_port,
1353#ifdef CONFIG_CONSOLE_POLL
1354 .poll_put_char = serial_omap_poll_put_char,
1355 .poll_get_char = serial_omap_poll_get_char,
1356#endif
1357};
1358
1359static struct uart_driver serial_omap_reg = {
1360 .owner = THIS_MODULE,
1361 .driver_name = "OMAP-SERIAL",
1362 .dev_name = OMAP_SERIAL_NAME,
1363 .nr = OMAP_MAX_HSUART_PORTS,
1364 .cons = OMAP_CONSOLE,
1365};
1366
1367#ifdef CONFIG_PM_SLEEP
1368static int serial_omap_prepare(struct device *dev)
1369{
1370 struct uart_omap_port *up = dev_get_drvdata(dev);
1371
1372 up->is_suspending = true;
1373
1374 return 0;
1375}
1376
1377static void serial_omap_complete(struct device *dev)
1378{
1379 struct uart_omap_port *up = dev_get_drvdata(dev);
1380
1381 up->is_suspending = false;
1382}
1383
1384static int serial_omap_suspend(struct device *dev)
1385{
1386 struct uart_omap_port *up = dev_get_drvdata(dev);
1387
1388 uart_suspend_port(&serial_omap_reg, &up->port);
1389 flush_work(&up->qos_work);
1390
1391 if (device_may_wakeup(dev))
1392 serial_omap_enable_wakeup(up, true);
1393 else
1394 serial_omap_enable_wakeup(up, false);
1395
1396 return 0;
1397}
1398
1399static int serial_omap_resume(struct device *dev)
1400{
1401 struct uart_omap_port *up = dev_get_drvdata(dev);
1402
1403 if (device_may_wakeup(dev))
1404 serial_omap_enable_wakeup(up, false);
1405
1406 uart_resume_port(&serial_omap_reg, &up->port);
1407
1408 return 0;
1409}
1410#else
1411#define serial_omap_prepare NULL
1412#define serial_omap_complete NULL
1413#endif /* CONFIG_PM_SLEEP */
1414
1415static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1416{
1417 u32 mvr, scheme;
1418 u16 revision, major, minor;
1419
1420 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1421
1422 /* Check revision register scheme */
1423 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1424
1425 switch (scheme) {
1426 case 0: /* Legacy Scheme: OMAP2/3 */
1427 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1428 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1429 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1430 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1431 break;
1432 case 1:
1433 /* New Scheme: OMAP4+ */
1434 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1435 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1436 OMAP_UART_MVR_MAJ_SHIFT;
1437 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1438 break;
1439 default:
1440 dev_warn(up->dev,
1441 "Unknown %s revision, defaulting to highest\n",
1442 up->name);
1443 /* highest possible revision */
1444 major = 0xff;
1445 minor = 0xff;
1446 }
1447
1448 /* normalize revision for the driver */
1449 revision = UART_BUILD_REVISION(major, minor);
1450
1451 switch (revision) {
1452 case OMAP_UART_REV_46:
1453 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1454 UART_ERRATA_i291_DMA_FORCEIDLE);
1455 break;
1456 case OMAP_UART_REV_52:
1457 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1458 UART_ERRATA_i291_DMA_FORCEIDLE);
1459 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1460 break;
1461 case OMAP_UART_REV_63:
1462 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1463 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1464 break;
1465 default:
1466 break;
1467 }
1468}
1469
1470static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1471{
1472 struct omap_uart_port_info *omap_up_info;
1473
1474 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1475 if (!omap_up_info)
1476 return NULL; /* out of memory */
1477
1478 of_property_read_u32(dev->of_node, "clock-frequency",
1479 &omap_up_info->uartclk);
1480
1481 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1482
1483 return omap_up_info;
1484}
1485
1486static const struct serial_rs485 serial_omap_rs485_supported = {
1487 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1488 SER_RS485_RX_DURING_TX,
1489 .delay_rts_before_send = 1,
1490 .delay_rts_after_send = 1,
1491};
1492
1493static int serial_omap_probe_rs485(struct uart_omap_port *up,
1494 struct device *dev)
1495{
1496 struct serial_rs485 *rs485conf = &up->port.rs485;
1497 struct device_node *np = dev->of_node;
1498 enum gpiod_flags gflags;
1499 int ret;
1500
1501 rs485conf->flags = 0;
1502 up->rts_gpiod = NULL;
1503
1504 if (!np)
1505 return 0;
1506
1507 up->port.rs485_config = serial_omap_config_rs485;
1508 up->port.rs485_supported = serial_omap_rs485_supported;
1509
1510 ret = uart_get_rs485_mode(&up->port);
1511 if (ret)
1512 return ret;
1513
1514 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1515 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1516 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1517 } else {
1518 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1519 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1520 }
1521
1522 /* check for tx enable gpio */
1523 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1524 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1525 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1526 if (IS_ERR(up->rts_gpiod)) {
1527 ret = PTR_ERR(up->rts_gpiod);
1528 if (ret == -EPROBE_DEFER)
1529 return ret;
1530
1531 up->rts_gpiod = NULL;
1532 up->port.rs485_supported = (const struct serial_rs485) { };
1533 if (rs485conf->flags & SER_RS485_ENABLED) {
1534 dev_err(dev, "disabling RS-485 (rts-gpio missing in device tree)\n");
1535 memset(rs485conf, 0, sizeof(*rs485conf));
1536 }
1537 } else {
1538 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1539 }
1540
1541 return 0;
1542}
1543
1544static int serial_omap_probe(struct platform_device *pdev)
1545{
1546 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1547 struct uart_omap_port *up;
1548 struct resource *mem;
1549 void __iomem *base;
1550 int uartirq = 0;
1551 int wakeirq = 0;
1552 int ret;
1553
1554 /* The optional wakeirq may be specified in the board dts file */
1555 if (pdev->dev.of_node) {
1556 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1557 if (!uartirq)
1558 return -EPROBE_DEFER;
1559 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1560 omap_up_info = of_get_uart_port_info(&pdev->dev);
1561 pdev->dev.platform_data = omap_up_info;
1562 } else {
1563 uartirq = platform_get_irq(pdev, 0);
1564 if (uartirq < 0)
1565 return -EPROBE_DEFER;
1566 }
1567
1568 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1569 if (!up)
1570 return -ENOMEM;
1571
1572 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
1573 if (IS_ERR(base))
1574 return PTR_ERR(base);
1575
1576 up->dev = &pdev->dev;
1577 up->port.dev = &pdev->dev;
1578 up->port.type = PORT_OMAP;
1579 up->port.iotype = UPIO_MEM;
1580 up->port.irq = uartirq;
1581 up->port.regshift = 2;
1582 up->port.fifosize = 64;
1583 up->port.ops = &serial_omap_pops;
1584 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1585
1586 if (pdev->dev.of_node)
1587 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1588 else
1589 ret = pdev->id;
1590
1591 if (ret < 0) {
1592 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1593 ret);
1594 goto err_port_line;
1595 }
1596 up->port.line = ret;
1597
1598 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1599 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1600 OMAP_MAX_HSUART_PORTS);
1601 ret = -ENXIO;
1602 goto err_port_line;
1603 }
1604
1605 up->wakeirq = wakeirq;
1606 if (!up->wakeirq)
1607 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1608 up->port.line);
1609
1610 sprintf(up->name, "OMAP UART%d", up->port.line);
1611 up->port.mapbase = mem->start;
1612 up->port.membase = base;
1613 up->port.flags = omap_up_info->flags;
1614 up->port.uartclk = omap_up_info->uartclk;
1615 if (!up->port.uartclk) {
1616 up->port.uartclk = DEFAULT_CLK_SPEED;
1617 dev_warn(&pdev->dev,
1618 "No clock speed specified: using default: %d\n",
1619 DEFAULT_CLK_SPEED);
1620 }
1621
1622 ret = serial_omap_probe_rs485(up, &pdev->dev);
1623 if (ret < 0)
1624 goto err_rs485;
1625
1626 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1627 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1628 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1629 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1630
1631 platform_set_drvdata(pdev, up);
1632 if (omap_up_info->autosuspend_timeout == 0)
1633 omap_up_info->autosuspend_timeout = -1;
1634
1635 device_init_wakeup(up->dev, true);
1636
1637 pm_runtime_enable(&pdev->dev);
1638
1639 pm_runtime_get_sync(&pdev->dev);
1640
1641 omap_serial_fill_features_erratas(up);
1642
1643 ui[up->port.line] = up;
1644 serial_omap_add_console_port(up);
1645
1646 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1647 if (ret != 0)
1648 goto err_add_port;
1649
1650 return 0;
1651
1652err_add_port:
1653 pm_runtime_put_sync(&pdev->dev);
1654 pm_runtime_disable(&pdev->dev);
1655 cpu_latency_qos_remove_request(&up->pm_qos_request);
1656 device_init_wakeup(up->dev, false);
1657err_rs485:
1658err_port_line:
1659 return ret;
1660}
1661
1662static void serial_omap_remove(struct platform_device *dev)
1663{
1664 struct uart_omap_port *up = platform_get_drvdata(dev);
1665
1666 pm_runtime_get_sync(up->dev);
1667
1668 uart_remove_one_port(&serial_omap_reg, &up->port);
1669
1670 pm_runtime_put_sync(up->dev);
1671 pm_runtime_disable(up->dev);
1672 cpu_latency_qos_remove_request(&up->pm_qos_request);
1673 device_init_wakeup(&dev->dev, false);
1674}
1675
1676/*
1677 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1678 * The access to uart register after MDR1 Access
1679 * causes UART to corrupt data.
1680 *
1681 * Need a delay =
1682 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1683 * give 10 times as much
1684 */
1685static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1686{
1687 u8 timeout = 255;
1688
1689 serial_out(up, UART_OMAP_MDR1, mdr1);
1690 udelay(2);
1691 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1692 UART_FCR_CLEAR_RCVR);
1693 /*
1694 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1695 * TX_FIFO_E bit is 1.
1696 */
1697 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1698 (UART_LSR_THRE | UART_LSR_DR))) {
1699 timeout--;
1700 if (!timeout) {
1701 /* Should *never* happen. we warn and carry on */
1702 dev_crit(up->dev, "Errata i202: timedout %x\n",
1703 serial_in(up, UART_LSR));
1704 break;
1705 }
1706 udelay(1);
1707 }
1708}
1709
1710#ifdef CONFIG_PM
1711static void serial_omap_restore_context(struct uart_omap_port *up)
1712{
1713 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1714 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1715 else
1716 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1717
1718 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1719 serial_out(up, UART_EFR, UART_EFR_ECB);
1720 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1721 serial_out(up, UART_IER, 0x0);
1722 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1723 serial_out(up, UART_DLL, up->dll);
1724 serial_out(up, UART_DLM, up->dlh);
1725 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1726 serial_out(up, UART_IER, up->ier);
1727 serial_out(up, UART_FCR, up->fcr);
1728 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1729 serial_out(up, UART_MCR, up->mcr);
1730 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1731 serial_out(up, UART_OMAP_SCR, up->scr);
1732 serial_out(up, UART_EFR, up->efr);
1733 serial_out(up, UART_LCR, up->lcr);
1734 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1735 serial_omap_mdr1_errataset(up, up->mdr1);
1736 else
1737 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1738 serial_out(up, UART_OMAP_WER, up->wer);
1739}
1740
1741static int serial_omap_runtime_suspend(struct device *dev)
1742{
1743 struct uart_omap_port *up = dev_get_drvdata(dev);
1744
1745 if (!up)
1746 return -EINVAL;
1747
1748 /*
1749 * When using 'no_console_suspend', the console UART must not be
1750 * suspended. Since driver suspend is managed by runtime suspend,
1751 * preventing runtime suspend (by returning error) will keep device
1752 * active during suspend.
1753 */
1754 if (up->is_suspending && !console_suspend_enabled &&
1755 uart_console(&up->port))
1756 return -EBUSY;
1757
1758 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1759
1760 serial_omap_enable_wakeup(up, true);
1761
1762 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1763 schedule_work(&up->qos_work);
1764
1765 return 0;
1766}
1767
1768static int serial_omap_runtime_resume(struct device *dev)
1769{
1770 struct uart_omap_port *up = dev_get_drvdata(dev);
1771
1772 int loss_cnt = serial_omap_get_context_loss_count(up);
1773
1774 serial_omap_enable_wakeup(up, false);
1775
1776 if (loss_cnt < 0) {
1777 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1778 loss_cnt);
1779 serial_omap_restore_context(up);
1780 } else if (up->context_loss_cnt != loss_cnt) {
1781 serial_omap_restore_context(up);
1782 }
1783 up->latency = up->calc_latency;
1784 schedule_work(&up->qos_work);
1785
1786 return 0;
1787}
1788#endif
1789
1790static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1791 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1792 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1793 serial_omap_runtime_resume, NULL)
1794 .prepare = serial_omap_prepare,
1795 .complete = serial_omap_complete,
1796};
1797
1798#if defined(CONFIG_OF)
1799static const struct of_device_id omap_serial_of_match[] = {
1800 { .compatible = "ti,omap2-uart" },
1801 { .compatible = "ti,omap3-uart" },
1802 { .compatible = "ti,omap4-uart" },
1803 {},
1804};
1805MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1806#endif
1807
1808static struct platform_driver serial_omap_driver = {
1809 .probe = serial_omap_probe,
1810 .remove_new = serial_omap_remove,
1811 .driver = {
1812 .name = OMAP_SERIAL_DRIVER_NAME,
1813 .pm = &serial_omap_dev_pm_ops,
1814 .of_match_table = of_match_ptr(omap_serial_of_match),
1815 },
1816};
1817
1818static int __init serial_omap_init(void)
1819{
1820 int ret;
1821
1822 ret = uart_register_driver(&serial_omap_reg);
1823 if (ret != 0)
1824 return ret;
1825 ret = platform_driver_register(&serial_omap_driver);
1826 if (ret != 0)
1827 uart_unregister_driver(&serial_omap_reg);
1828 return ret;
1829}
1830
1831static void __exit serial_omap_exit(void)
1832{
1833 platform_driver_unregister(&serial_omap_driver);
1834 uart_unregister_driver(&serial_omap_reg);
1835}
1836
1837module_init(serial_omap_init);
1838module_exit(serial_omap_exit);
1839
1840MODULE_DESCRIPTION("OMAP High Speed UART driver");
1841MODULE_LICENSE("GPL");
1842MODULE_AUTHOR("Texas Instruments Inc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/console.h>
22#include <linux/serial_reg.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/serial_core.h>
31#include <linux/irq.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/gpio/consumer.h>
37#include <linux/platform_data/serial-omap.h>
38
39#define OMAP_MAX_HSUART_PORTS 10
40
41#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
42
43#define OMAP_UART_REV_42 0x0402
44#define OMAP_UART_REV_46 0x0406
45#define OMAP_UART_REV_52 0x0502
46#define OMAP_UART_REV_63 0x0603
47
48#define OMAP_UART_TX_WAKEUP_EN BIT(7)
49
50/* Feature flags */
51#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
52
53#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
54#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
55
56#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
57
58/* SCR register bitmasks */
59#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
60#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
61#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
62
63/* FCR register bitmasks */
64#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
65#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
66
67/* MVR register bitmasks */
68#define OMAP_UART_MVR_SCHEME_SHIFT 30
69
70#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
71#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
72#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
73
74#define OMAP_UART_MVR_MAJ_MASK 0x700
75#define OMAP_UART_MVR_MAJ_SHIFT 8
76#define OMAP_UART_MVR_MIN_MASK 0x3f
77
78#define OMAP_UART_DMA_CH_FREE -1
79
80#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
81#define OMAP_MODE13X_SPEED 230400
82
83/* WER = 0x7F
84 * Enable module level wakeup in WER reg
85 */
86#define OMAP_UART_WER_MOD_WKUP 0x7F
87
88/* Enable XON/XOFF flow control on output */
89#define OMAP_UART_SW_TX 0x08
90
91/* Enable XON/XOFF flow control on input */
92#define OMAP_UART_SW_RX 0x02
93
94#define OMAP_UART_SW_CLR 0xF0
95
96#define OMAP_UART_TCR_TRIG 0x0F
97
98struct uart_omap_dma {
99 u8 uart_dma_tx;
100 u8 uart_dma_rx;
101 int rx_dma_channel;
102 int tx_dma_channel;
103 dma_addr_t rx_buf_dma_phys;
104 dma_addr_t tx_buf_dma_phys;
105 unsigned int uart_base;
106 /*
107 * Buffer for rx dma. It is not required for tx because the buffer
108 * comes from port structure.
109 */
110 unsigned char *rx_buf;
111 unsigned int prev_rx_dma_pos;
112 int tx_buf_size;
113 int tx_dma_used;
114 int rx_dma_used;
115 spinlock_t tx_lock;
116 spinlock_t rx_lock;
117 /* timer to poll activity on rx dma */
118 struct timer_list rx_timer;
119 unsigned int rx_buf_size;
120 unsigned int rx_poll_rate;
121 unsigned int rx_timeout;
122};
123
124struct uart_omap_port {
125 struct uart_port port;
126 struct uart_omap_dma uart_dma;
127 struct device *dev;
128 int wakeirq;
129
130 unsigned char ier;
131 unsigned char lcr;
132 unsigned char mcr;
133 unsigned char fcr;
134 unsigned char efr;
135 unsigned char dll;
136 unsigned char dlh;
137 unsigned char mdr1;
138 unsigned char scr;
139 unsigned char wer;
140
141 int use_dma;
142 /*
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read, but the bits will not
145 * be immediately processed.
146 */
147 unsigned int lsr_break_flag;
148 unsigned char msr_saved_flags;
149 char name[20];
150 unsigned long port_activity;
151 int context_loss_cnt;
152 u32 errata;
153 u32 features;
154
155 struct gpio_desc *rts_gpiod;
156
157 struct pm_qos_request pm_qos_request;
158 u32 latency;
159 u32 calc_latency;
160 struct work_struct qos_work;
161 bool is_suspending;
162};
163
164#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
165
166static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
167
168/* Forward declaration of functions */
169static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
170
171static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
172{
173 offset <<= up->port.regshift;
174 return readw(up->port.membase + offset);
175}
176
177static inline void serial_out(struct uart_omap_port *up, int offset, int value)
178{
179 offset <<= up->port.regshift;
180 writew(value, up->port.membase + offset);
181}
182
183static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
184{
185 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
186 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
187 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
188 serial_out(up, UART_FCR, 0);
189}
190
191#ifdef CONFIG_PM
192static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
193{
194 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
195
196 if (!pdata || !pdata->get_context_loss_count)
197 return -EINVAL;
198
199 return pdata->get_context_loss_count(up->dev);
200}
201
202/* REVISIT: Remove this when omap3 boots in device tree only mode */
203static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
204{
205 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
206
207 if (!pdata || !pdata->enable_wakeup)
208 return;
209
210 pdata->enable_wakeup(up->dev, enable);
211}
212#endif /* CONFIG_PM */
213
214/*
215 * Calculate the absolute difference between the desired and actual baud
216 * rate for the given mode.
217 */
218static inline int calculate_baud_abs_diff(struct uart_port *port,
219 unsigned int baud, unsigned int mode)
220{
221 unsigned int n = port->uartclk / (mode * baud);
222 int abs_diff;
223
224 if (n == 0)
225 n = 1;
226
227 abs_diff = baud - (port->uartclk / (mode * n));
228 if (abs_diff < 0)
229 abs_diff = -abs_diff;
230
231 return abs_diff;
232}
233
234/*
235 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
236 * @port: uart port info
237 * @baud: baudrate for which mode needs to be determined
238 *
239 * Returns true if baud rate is MODE16X and false if MODE13X
240 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
241 * and Error Rates" determines modes not for all common baud rates.
242 * E.g. for 1000000 baud rate mode must be 16x, but according to that
243 * table it's determined as 13x.
244 */
245static bool
246serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
247{
248 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
249 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
250
251 return (abs_diff_13 >= abs_diff_16);
252}
253
254/*
255 * serial_omap_get_divisor - calculate divisor value
256 * @port: uart port info
257 * @baud: baudrate for which divisor needs to be calculated.
258 */
259static unsigned int
260serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
261{
262 unsigned int mode;
263
264 if (!serial_omap_baud_is_mode16(port, baud))
265 mode = 13;
266 else
267 mode = 16;
268 return port->uartclk/(mode * baud);
269}
270
271static void serial_omap_enable_ms(struct uart_port *port)
272{
273 struct uart_omap_port *up = to_uart_omap_port(port);
274
275 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
276
277 pm_runtime_get_sync(up->dev);
278 up->ier |= UART_IER_MSI;
279 serial_out(up, UART_IER, up->ier);
280 pm_runtime_mark_last_busy(up->dev);
281 pm_runtime_put_autosuspend(up->dev);
282}
283
284static void serial_omap_stop_tx(struct uart_port *port)
285{
286 struct uart_omap_port *up = to_uart_omap_port(port);
287 int res;
288
289 pm_runtime_get_sync(up->dev);
290
291 /* Handle RS-485 */
292 if (port->rs485.flags & SER_RS485_ENABLED) {
293 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
294 /* THR interrupt is fired when both TX FIFO and TX
295 * shift register are empty. This means there's nothing
296 * left to transmit now, so make sure the THR interrupt
297 * is fired when TX FIFO is below the trigger level,
298 * disable THR interrupts and toggle the RS-485 GPIO
299 * data direction pin if needed.
300 */
301 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
302 serial_out(up, UART_OMAP_SCR, up->scr);
303 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
304 1 : 0;
305 if (gpiod_get_value(up->rts_gpiod) != res) {
306 if (port->rs485.delay_rts_after_send > 0)
307 mdelay(
308 port->rs485.delay_rts_after_send);
309 gpiod_set_value(up->rts_gpiod, res);
310 }
311 } else {
312 /* We're asked to stop, but there's still stuff in the
313 * UART FIFO, so make sure the THR interrupt is fired
314 * when both TX FIFO and TX shift register are empty.
315 * The next THR interrupt (if no transmission is started
316 * in the meantime) will indicate the end of a
317 * transmission. Therefore we _don't_ disable THR
318 * interrupts in this situation.
319 */
320 up->scr |= OMAP_UART_SCR_TX_EMPTY;
321 serial_out(up, UART_OMAP_SCR, up->scr);
322 return;
323 }
324 }
325
326 if (up->ier & UART_IER_THRI) {
327 up->ier &= ~UART_IER_THRI;
328 serial_out(up, UART_IER, up->ier);
329 }
330
331 if ((port->rs485.flags & SER_RS485_ENABLED) &&
332 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
333 /*
334 * Empty the RX FIFO, we are not interested in anything
335 * received during the half-duplex transmission.
336 */
337 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
338 /* Re-enable RX interrupts */
339 up->ier |= UART_IER_RLSI | UART_IER_RDI;
340 up->port.read_status_mask |= UART_LSR_DR;
341 serial_out(up, UART_IER, up->ier);
342 }
343
344 pm_runtime_mark_last_busy(up->dev);
345 pm_runtime_put_autosuspend(up->dev);
346}
347
348static void serial_omap_stop_rx(struct uart_port *port)
349{
350 struct uart_omap_port *up = to_uart_omap_port(port);
351
352 pm_runtime_get_sync(up->dev);
353 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
354 up->port.read_status_mask &= ~UART_LSR_DR;
355 serial_out(up, UART_IER, up->ier);
356 pm_runtime_mark_last_busy(up->dev);
357 pm_runtime_put_autosuspend(up->dev);
358}
359
360static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
361{
362 struct circ_buf *xmit = &up->port.state->xmit;
363 int count;
364
365 if (up->port.x_char) {
366 serial_out(up, UART_TX, up->port.x_char);
367 up->port.icount.tx++;
368 up->port.x_char = 0;
369 return;
370 }
371 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
372 serial_omap_stop_tx(&up->port);
373 return;
374 }
375 count = up->port.fifosize / 4;
376 do {
377 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
379 up->port.icount.tx++;
380 if (uart_circ_empty(xmit))
381 break;
382 } while (--count > 0);
383
384 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
385 uart_write_wakeup(&up->port);
386
387 if (uart_circ_empty(xmit))
388 serial_omap_stop_tx(&up->port);
389}
390
391static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
392{
393 if (!(up->ier & UART_IER_THRI)) {
394 up->ier |= UART_IER_THRI;
395 serial_out(up, UART_IER, up->ier);
396 }
397}
398
399static void serial_omap_start_tx(struct uart_port *port)
400{
401 struct uart_omap_port *up = to_uart_omap_port(port);
402 int res;
403
404 pm_runtime_get_sync(up->dev);
405
406 /* Handle RS-485 */
407 if (port->rs485.flags & SER_RS485_ENABLED) {
408 /* Fire THR interrupts when FIFO is below trigger level */
409 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
410 serial_out(up, UART_OMAP_SCR, up->scr);
411
412 /* if rts not already enabled */
413 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
414 if (gpiod_get_value(up->rts_gpiod) != res) {
415 gpiod_set_value(up->rts_gpiod, res);
416 if (port->rs485.delay_rts_before_send > 0)
417 mdelay(port->rs485.delay_rts_before_send);
418 }
419 }
420
421 if ((port->rs485.flags & SER_RS485_ENABLED) &&
422 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
423 serial_omap_stop_rx(port);
424
425 serial_omap_enable_ier_thri(up);
426 pm_runtime_mark_last_busy(up->dev);
427 pm_runtime_put_autosuspend(up->dev);
428}
429
430static void serial_omap_throttle(struct uart_port *port)
431{
432 struct uart_omap_port *up = to_uart_omap_port(port);
433 unsigned long flags;
434
435 pm_runtime_get_sync(up->dev);
436 spin_lock_irqsave(&up->port.lock, flags);
437 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
438 serial_out(up, UART_IER, up->ier);
439 spin_unlock_irqrestore(&up->port.lock, flags);
440 pm_runtime_mark_last_busy(up->dev);
441 pm_runtime_put_autosuspend(up->dev);
442}
443
444static void serial_omap_unthrottle(struct uart_port *port)
445{
446 struct uart_omap_port *up = to_uart_omap_port(port);
447 unsigned long flags;
448
449 pm_runtime_get_sync(up->dev);
450 spin_lock_irqsave(&up->port.lock, flags);
451 up->ier |= UART_IER_RLSI | UART_IER_RDI;
452 serial_out(up, UART_IER, up->ier);
453 spin_unlock_irqrestore(&up->port.lock, flags);
454 pm_runtime_mark_last_busy(up->dev);
455 pm_runtime_put_autosuspend(up->dev);
456}
457
458static unsigned int check_modem_status(struct uart_omap_port *up)
459{
460 unsigned int status;
461
462 status = serial_in(up, UART_MSR);
463 status |= up->msr_saved_flags;
464 up->msr_saved_flags = 0;
465 if ((status & UART_MSR_ANY_DELTA) == 0)
466 return status;
467
468 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
469 up->port.state != NULL) {
470 if (status & UART_MSR_TERI)
471 up->port.icount.rng++;
472 if (status & UART_MSR_DDSR)
473 up->port.icount.dsr++;
474 if (status & UART_MSR_DDCD)
475 uart_handle_dcd_change
476 (&up->port, status & UART_MSR_DCD);
477 if (status & UART_MSR_DCTS)
478 uart_handle_cts_change
479 (&up->port, status & UART_MSR_CTS);
480 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
481 }
482
483 return status;
484}
485
486static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
487{
488 unsigned int flag;
489
490 /*
491 * Read one data character out to avoid stalling the receiver according
492 * to the table 23-246 of the omap4 TRM.
493 */
494 if (likely(lsr & UART_LSR_DR))
495 serial_in(up, UART_RX);
496
497 up->port.icount.rx++;
498 flag = TTY_NORMAL;
499
500 if (lsr & UART_LSR_BI) {
501 flag = TTY_BREAK;
502 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
503 up->port.icount.brk++;
504 /*
505 * We do the SysRQ and SAK checking
506 * here because otherwise the break
507 * may get masked by ignore_status_mask
508 * or read_status_mask.
509 */
510 if (uart_handle_break(&up->port))
511 return;
512
513 }
514
515 if (lsr & UART_LSR_PE) {
516 flag = TTY_PARITY;
517 up->port.icount.parity++;
518 }
519
520 if (lsr & UART_LSR_FE) {
521 flag = TTY_FRAME;
522 up->port.icount.frame++;
523 }
524
525 if (lsr & UART_LSR_OE)
526 up->port.icount.overrun++;
527
528#ifdef CONFIG_SERIAL_OMAP_CONSOLE
529 if (up->port.line == up->port.cons->index) {
530 /* Recover the break flag from console xmit */
531 lsr |= up->lsr_break_flag;
532 }
533#endif
534 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
535}
536
537static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
538{
539 unsigned char ch = 0;
540 unsigned int flag;
541
542 if (!(lsr & UART_LSR_DR))
543 return;
544
545 ch = serial_in(up, UART_RX);
546 flag = TTY_NORMAL;
547 up->port.icount.rx++;
548
549 if (uart_handle_sysrq_char(&up->port, ch))
550 return;
551
552 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
553}
554
555/**
556 * serial_omap_irq() - This handles the interrupt from one port
557 * @irq: uart port irq number
558 * @dev_id: uart port info
559 */
560static irqreturn_t serial_omap_irq(int irq, void *dev_id)
561{
562 struct uart_omap_port *up = dev_id;
563 unsigned int iir, lsr;
564 unsigned int type;
565 irqreturn_t ret = IRQ_NONE;
566 int max_count = 256;
567
568 spin_lock(&up->port.lock);
569 pm_runtime_get_sync(up->dev);
570
571 do {
572 iir = serial_in(up, UART_IIR);
573 if (iir & UART_IIR_NO_INT)
574 break;
575
576 ret = IRQ_HANDLED;
577 lsr = serial_in(up, UART_LSR);
578
579 /* extract IRQ type from IIR register */
580 type = iir & 0x3e;
581
582 switch (type) {
583 case UART_IIR_MSI:
584 check_modem_status(up);
585 break;
586 case UART_IIR_THRI:
587 transmit_chars(up, lsr);
588 break;
589 case UART_IIR_RX_TIMEOUT:
590 case UART_IIR_RDI:
591 serial_omap_rdi(up, lsr);
592 break;
593 case UART_IIR_RLSI:
594 serial_omap_rlsi(up, lsr);
595 break;
596 case UART_IIR_CTS_RTS_DSR:
597 /* simply try again */
598 break;
599 case UART_IIR_XOFF:
600 default:
601 break;
602 }
603 } while (max_count--);
604
605 spin_unlock(&up->port.lock);
606
607 tty_flip_buffer_push(&up->port.state->port);
608
609 pm_runtime_mark_last_busy(up->dev);
610 pm_runtime_put_autosuspend(up->dev);
611 up->port_activity = jiffies;
612
613 return ret;
614}
615
616static unsigned int serial_omap_tx_empty(struct uart_port *port)
617{
618 struct uart_omap_port *up = to_uart_omap_port(port);
619 unsigned long flags = 0;
620 unsigned int ret = 0;
621
622 pm_runtime_get_sync(up->dev);
623 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
624 spin_lock_irqsave(&up->port.lock, flags);
625 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
626 spin_unlock_irqrestore(&up->port.lock, flags);
627 pm_runtime_mark_last_busy(up->dev);
628 pm_runtime_put_autosuspend(up->dev);
629 return ret;
630}
631
632static unsigned int serial_omap_get_mctrl(struct uart_port *port)
633{
634 struct uart_omap_port *up = to_uart_omap_port(port);
635 unsigned int status;
636 unsigned int ret = 0;
637
638 pm_runtime_get_sync(up->dev);
639 status = check_modem_status(up);
640 pm_runtime_mark_last_busy(up->dev);
641 pm_runtime_put_autosuspend(up->dev);
642
643 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
644
645 if (status & UART_MSR_DCD)
646 ret |= TIOCM_CAR;
647 if (status & UART_MSR_RI)
648 ret |= TIOCM_RNG;
649 if (status & UART_MSR_DSR)
650 ret |= TIOCM_DSR;
651 if (status & UART_MSR_CTS)
652 ret |= TIOCM_CTS;
653 return ret;
654}
655
656static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
657{
658 struct uart_omap_port *up = to_uart_omap_port(port);
659 unsigned char mcr = 0, old_mcr, lcr;
660
661 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
662 if (mctrl & TIOCM_RTS)
663 mcr |= UART_MCR_RTS;
664 if (mctrl & TIOCM_DTR)
665 mcr |= UART_MCR_DTR;
666 if (mctrl & TIOCM_OUT1)
667 mcr |= UART_MCR_OUT1;
668 if (mctrl & TIOCM_OUT2)
669 mcr |= UART_MCR_OUT2;
670 if (mctrl & TIOCM_LOOP)
671 mcr |= UART_MCR_LOOP;
672
673 pm_runtime_get_sync(up->dev);
674 old_mcr = serial_in(up, UART_MCR);
675 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
676 UART_MCR_DTR | UART_MCR_RTS);
677 up->mcr = old_mcr | mcr;
678 serial_out(up, UART_MCR, up->mcr);
679
680 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
681 lcr = serial_in(up, UART_LCR);
682 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
683 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
684 up->efr |= UART_EFR_RTS;
685 else
686 up->efr &= ~UART_EFR_RTS;
687 serial_out(up, UART_EFR, up->efr);
688 serial_out(up, UART_LCR, lcr);
689
690 pm_runtime_mark_last_busy(up->dev);
691 pm_runtime_put_autosuspend(up->dev);
692}
693
694static void serial_omap_break_ctl(struct uart_port *port, int break_state)
695{
696 struct uart_omap_port *up = to_uart_omap_port(port);
697 unsigned long flags = 0;
698
699 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
700 pm_runtime_get_sync(up->dev);
701 spin_lock_irqsave(&up->port.lock, flags);
702 if (break_state == -1)
703 up->lcr |= UART_LCR_SBC;
704 else
705 up->lcr &= ~UART_LCR_SBC;
706 serial_out(up, UART_LCR, up->lcr);
707 spin_unlock_irqrestore(&up->port.lock, flags);
708 pm_runtime_mark_last_busy(up->dev);
709 pm_runtime_put_autosuspend(up->dev);
710}
711
712static int serial_omap_startup(struct uart_port *port)
713{
714 struct uart_omap_port *up = to_uart_omap_port(port);
715 unsigned long flags = 0;
716 int retval;
717
718 /*
719 * Allocate the IRQ
720 */
721 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
722 up->name, up);
723 if (retval)
724 return retval;
725
726 /* Optional wake-up IRQ */
727 if (up->wakeirq) {
728 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
729 if (retval) {
730 free_irq(up->port.irq, up);
731 return retval;
732 }
733 }
734
735 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
736
737 pm_runtime_get_sync(up->dev);
738 /*
739 * Clear the FIFO buffers and disable them.
740 * (they will be reenabled in set_termios())
741 */
742 serial_omap_clear_fifos(up);
743
744 /*
745 * Clear the interrupt registers.
746 */
747 (void) serial_in(up, UART_LSR);
748 if (serial_in(up, UART_LSR) & UART_LSR_DR)
749 (void) serial_in(up, UART_RX);
750 (void) serial_in(up, UART_IIR);
751 (void) serial_in(up, UART_MSR);
752
753 /*
754 * Now, initialize the UART
755 */
756 serial_out(up, UART_LCR, UART_LCR_WLEN8);
757 spin_lock_irqsave(&up->port.lock, flags);
758 /*
759 * Most PC uarts need OUT2 raised to enable interrupts.
760 */
761 up->port.mctrl |= TIOCM_OUT2;
762 serial_omap_set_mctrl(&up->port, up->port.mctrl);
763 spin_unlock_irqrestore(&up->port.lock, flags);
764
765 up->msr_saved_flags = 0;
766 /*
767 * Finally, enable interrupts. Note: Modem status interrupts
768 * are set via set_termios(), which will be occurring imminently
769 * anyway, so we don't enable them here.
770 */
771 up->ier = UART_IER_RLSI | UART_IER_RDI;
772 serial_out(up, UART_IER, up->ier);
773
774 /* Enable module level wake up */
775 up->wer = OMAP_UART_WER_MOD_WKUP;
776 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
777 up->wer |= OMAP_UART_TX_WAKEUP_EN;
778
779 serial_out(up, UART_OMAP_WER, up->wer);
780
781 pm_runtime_mark_last_busy(up->dev);
782 pm_runtime_put_autosuspend(up->dev);
783 up->port_activity = jiffies;
784 return 0;
785}
786
787static void serial_omap_shutdown(struct uart_port *port)
788{
789 struct uart_omap_port *up = to_uart_omap_port(port);
790 unsigned long flags = 0;
791
792 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
793
794 pm_runtime_get_sync(up->dev);
795 /*
796 * Disable interrupts from this port
797 */
798 up->ier = 0;
799 serial_out(up, UART_IER, 0);
800
801 spin_lock_irqsave(&up->port.lock, flags);
802 up->port.mctrl &= ~TIOCM_OUT2;
803 serial_omap_set_mctrl(&up->port, up->port.mctrl);
804 spin_unlock_irqrestore(&up->port.lock, flags);
805
806 /*
807 * Disable break condition and FIFOs
808 */
809 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
810 serial_omap_clear_fifos(up);
811
812 /*
813 * Read data port to reset things, and then free the irq
814 */
815 if (serial_in(up, UART_LSR) & UART_LSR_DR)
816 (void) serial_in(up, UART_RX);
817
818 pm_runtime_mark_last_busy(up->dev);
819 pm_runtime_put_autosuspend(up->dev);
820 free_irq(up->port.irq, up);
821 dev_pm_clear_wake_irq(up->dev);
822}
823
824static void serial_omap_uart_qos_work(struct work_struct *work)
825{
826 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
827 qos_work);
828
829 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
830}
831
832static void
833serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
834 struct ktermios *old)
835{
836 struct uart_omap_port *up = to_uart_omap_port(port);
837 unsigned char cval = 0;
838 unsigned long flags = 0;
839 unsigned int baud, quot;
840
841 switch (termios->c_cflag & CSIZE) {
842 case CS5:
843 cval = UART_LCR_WLEN5;
844 break;
845 case CS6:
846 cval = UART_LCR_WLEN6;
847 break;
848 case CS7:
849 cval = UART_LCR_WLEN7;
850 break;
851 default:
852 case CS8:
853 cval = UART_LCR_WLEN8;
854 break;
855 }
856
857 if (termios->c_cflag & CSTOPB)
858 cval |= UART_LCR_STOP;
859 if (termios->c_cflag & PARENB)
860 cval |= UART_LCR_PARITY;
861 if (!(termios->c_cflag & PARODD))
862 cval |= UART_LCR_EPAR;
863 if (termios->c_cflag & CMSPAR)
864 cval |= UART_LCR_SPAR;
865
866 /*
867 * Ask the core to calculate the divisor for us.
868 */
869
870 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
871 quot = serial_omap_get_divisor(port, baud);
872
873 /* calculate wakeup latency constraint */
874 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
875 up->latency = up->calc_latency;
876 schedule_work(&up->qos_work);
877
878 up->dll = quot & 0xff;
879 up->dlh = quot >> 8;
880 up->mdr1 = UART_OMAP_MDR1_DISABLE;
881
882 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
883 UART_FCR_ENABLE_FIFO;
884
885 /*
886 * Ok, we're now changing the port state. Do it with
887 * interrupts disabled.
888 */
889 pm_runtime_get_sync(up->dev);
890 spin_lock_irqsave(&up->port.lock, flags);
891
892 /*
893 * Update the per-port timeout.
894 */
895 uart_update_timeout(port, termios->c_cflag, baud);
896
897 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
898 if (termios->c_iflag & INPCK)
899 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
900 if (termios->c_iflag & (BRKINT | PARMRK))
901 up->port.read_status_mask |= UART_LSR_BI;
902
903 /*
904 * Characters to ignore
905 */
906 up->port.ignore_status_mask = 0;
907 if (termios->c_iflag & IGNPAR)
908 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
909 if (termios->c_iflag & IGNBRK) {
910 up->port.ignore_status_mask |= UART_LSR_BI;
911 /*
912 * If we're ignoring parity and break indicators,
913 * ignore overruns too (for real raw support).
914 */
915 if (termios->c_iflag & IGNPAR)
916 up->port.ignore_status_mask |= UART_LSR_OE;
917 }
918
919 /*
920 * ignore all characters if CREAD is not set
921 */
922 if ((termios->c_cflag & CREAD) == 0)
923 up->port.ignore_status_mask |= UART_LSR_DR;
924
925 /*
926 * Modem status interrupts
927 */
928 up->ier &= ~UART_IER_MSI;
929 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
930 up->ier |= UART_IER_MSI;
931 serial_out(up, UART_IER, up->ier);
932 serial_out(up, UART_LCR, cval); /* reset DLAB */
933 up->lcr = cval;
934 up->scr = 0;
935
936 /* FIFOs and DMA Settings */
937
938 /* FCR can be changed only when the
939 * baud clock is not running
940 * DLL_REG and DLH_REG set to 0.
941 */
942 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
943 serial_out(up, UART_DLL, 0);
944 serial_out(up, UART_DLM, 0);
945 serial_out(up, UART_LCR, 0);
946
947 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
948
949 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
950 up->efr &= ~UART_EFR_SCD;
951 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
952
953 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
954 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
955 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
956 /* FIFO ENABLE, DMA MODE */
957
958 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
959 /*
960 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
961 * sets Enables the granularity of 1 for TRIGGER RX
962 * level. Along with setting RX FIFO trigger level
963 * to 1 (as noted below, 16 characters) and TLR[3:0]
964 * to zero this will result RX FIFO threshold level
965 * to 1 character, instead of 16 as noted in comment
966 * below.
967 */
968
969 /* Set receive FIFO threshold to 16 characters and
970 * transmit FIFO threshold to 32 spaces
971 */
972 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
973 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
974 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
975 UART_FCR_ENABLE_FIFO;
976
977 serial_out(up, UART_FCR, up->fcr);
978 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
979
980 serial_out(up, UART_OMAP_SCR, up->scr);
981
982 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
983 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
984 serial_out(up, UART_MCR, up->mcr);
985 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
986 serial_out(up, UART_EFR, up->efr);
987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
988
989 /* Protocol, Baud Rate, and Interrupt Settings */
990
991 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
992 serial_omap_mdr1_errataset(up, up->mdr1);
993 else
994 serial_out(up, UART_OMAP_MDR1, up->mdr1);
995
996 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
997 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
998
999 serial_out(up, UART_LCR, 0);
1000 serial_out(up, UART_IER, 0);
1001 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1002
1003 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1004 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1005
1006 serial_out(up, UART_LCR, 0);
1007 serial_out(up, UART_IER, up->ier);
1008 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1009
1010 serial_out(up, UART_EFR, up->efr);
1011 serial_out(up, UART_LCR, cval);
1012
1013 if (!serial_omap_baud_is_mode16(port, baud))
1014 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1015 else
1016 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1017
1018 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1019 serial_omap_mdr1_errataset(up, up->mdr1);
1020 else
1021 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1022
1023 /* Configure flow control */
1024 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1025
1026 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1027 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1028 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1029
1030 /* Enable access to TCR/TLR */
1031 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1032 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1033 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1034
1035 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1036
1037 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1038
1039 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1040 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1041 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1042 up->efr |= UART_EFR_CTS;
1043 } else {
1044 /* Disable AUTORTS and AUTOCTS */
1045 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1046 }
1047
1048 if (up->port.flags & UPF_SOFT_FLOW) {
1049 /* clear SW control mode bits */
1050 up->efr &= OMAP_UART_SW_CLR;
1051
1052 /*
1053 * IXON Flag:
1054 * Enable XON/XOFF flow control on input.
1055 * Receiver compares XON1, XOFF1.
1056 */
1057 if (termios->c_iflag & IXON)
1058 up->efr |= OMAP_UART_SW_RX;
1059
1060 /*
1061 * IXOFF Flag:
1062 * Enable XON/XOFF flow control on output.
1063 * Transmit XON1, XOFF1
1064 */
1065 if (termios->c_iflag & IXOFF) {
1066 up->port.status |= UPSTAT_AUTOXOFF;
1067 up->efr |= OMAP_UART_SW_TX;
1068 }
1069
1070 /*
1071 * IXANY Flag:
1072 * Enable any character to restart output.
1073 * Operation resumes after receiving any
1074 * character after recognition of the XOFF character
1075 */
1076 if (termios->c_iflag & IXANY)
1077 up->mcr |= UART_MCR_XONANY;
1078 else
1079 up->mcr &= ~UART_MCR_XONANY;
1080 }
1081 serial_out(up, UART_MCR, up->mcr);
1082 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1083 serial_out(up, UART_EFR, up->efr);
1084 serial_out(up, UART_LCR, up->lcr);
1085
1086 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1087
1088 spin_unlock_irqrestore(&up->port.lock, flags);
1089 pm_runtime_mark_last_busy(up->dev);
1090 pm_runtime_put_autosuspend(up->dev);
1091 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1092}
1093
1094static void
1095serial_omap_pm(struct uart_port *port, unsigned int state,
1096 unsigned int oldstate)
1097{
1098 struct uart_omap_port *up = to_uart_omap_port(port);
1099 unsigned char efr;
1100
1101 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1102
1103 pm_runtime_get_sync(up->dev);
1104 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1105 efr = serial_in(up, UART_EFR);
1106 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1107 serial_out(up, UART_LCR, 0);
1108
1109 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1110 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1111 serial_out(up, UART_EFR, efr);
1112 serial_out(up, UART_LCR, 0);
1113
1114 pm_runtime_mark_last_busy(up->dev);
1115 pm_runtime_put_autosuspend(up->dev);
1116}
1117
1118static void serial_omap_release_port(struct uart_port *port)
1119{
1120 dev_dbg(port->dev, "serial_omap_release_port+\n");
1121}
1122
1123static int serial_omap_request_port(struct uart_port *port)
1124{
1125 dev_dbg(port->dev, "serial_omap_request_port+\n");
1126 return 0;
1127}
1128
1129static void serial_omap_config_port(struct uart_port *port, int flags)
1130{
1131 struct uart_omap_port *up = to_uart_omap_port(port);
1132
1133 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1134 up->port.line);
1135 up->port.type = PORT_OMAP;
1136 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1137}
1138
1139static int
1140serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1141{
1142 /* we don't want the core code to modify any port params */
1143 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1144 return -EINVAL;
1145}
1146
1147static const char *
1148serial_omap_type(struct uart_port *port)
1149{
1150 struct uart_omap_port *up = to_uart_omap_port(port);
1151
1152 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1153 return up->name;
1154}
1155
1156#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1157
1158static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1159{
1160 unsigned int status, tmout = 10000;
1161
1162 /* Wait up to 10ms for the character(s) to be sent. */
1163 do {
1164 status = serial_in(up, UART_LSR);
1165
1166 if (status & UART_LSR_BI)
1167 up->lsr_break_flag = UART_LSR_BI;
1168
1169 if (--tmout == 0)
1170 break;
1171 udelay(1);
1172 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1173
1174 /* Wait up to 1s for flow control if necessary */
1175 if (up->port.flags & UPF_CONS_FLOW) {
1176 tmout = 1000000;
1177 for (tmout = 1000000; tmout; tmout--) {
1178 unsigned int msr = serial_in(up, UART_MSR);
1179
1180 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1181 if (msr & UART_MSR_CTS)
1182 break;
1183
1184 udelay(1);
1185 }
1186 }
1187}
1188
1189#ifdef CONFIG_CONSOLE_POLL
1190
1191static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1192{
1193 struct uart_omap_port *up = to_uart_omap_port(port);
1194
1195 pm_runtime_get_sync(up->dev);
1196 wait_for_xmitr(up);
1197 serial_out(up, UART_TX, ch);
1198 pm_runtime_mark_last_busy(up->dev);
1199 pm_runtime_put_autosuspend(up->dev);
1200}
1201
1202static int serial_omap_poll_get_char(struct uart_port *port)
1203{
1204 struct uart_omap_port *up = to_uart_omap_port(port);
1205 unsigned int status;
1206
1207 pm_runtime_get_sync(up->dev);
1208 status = serial_in(up, UART_LSR);
1209 if (!(status & UART_LSR_DR)) {
1210 status = NO_POLL_CHAR;
1211 goto out;
1212 }
1213
1214 status = serial_in(up, UART_RX);
1215
1216out:
1217 pm_runtime_mark_last_busy(up->dev);
1218 pm_runtime_put_autosuspend(up->dev);
1219
1220 return status;
1221}
1222
1223#endif /* CONFIG_CONSOLE_POLL */
1224
1225#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1226
1227#ifdef CONFIG_SERIAL_EARLYCON
1228static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1229{
1230 offset <<= port->regshift;
1231 return readw(port->membase + offset);
1232}
1233
1234static void omap_serial_early_out(struct uart_port *port, int offset,
1235 int value)
1236{
1237 offset <<= port->regshift;
1238 writew(value, port->membase + offset);
1239}
1240
1241static void omap_serial_early_putc(struct uart_port *port, int c)
1242{
1243 unsigned int status;
1244
1245 for (;;) {
1246 status = omap_serial_early_in(port, UART_LSR);
1247 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1248 break;
1249 cpu_relax();
1250 }
1251 omap_serial_early_out(port, UART_TX, c);
1252}
1253
1254static void early_omap_serial_write(struct console *console, const char *s,
1255 unsigned int count)
1256{
1257 struct earlycon_device *device = console->data;
1258 struct uart_port *port = &device->port;
1259
1260 uart_console_write(port, s, count, omap_serial_early_putc);
1261}
1262
1263static int __init early_omap_serial_setup(struct earlycon_device *device,
1264 const char *options)
1265{
1266 struct uart_port *port = &device->port;
1267
1268 if (!(device->port.membase || device->port.iobase))
1269 return -ENODEV;
1270
1271 port->regshift = 2;
1272 device->con->write = early_omap_serial_write;
1273 return 0;
1274}
1275
1276OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1277OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1278OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1279#endif /* CONFIG_SERIAL_EARLYCON */
1280
1281static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1282
1283static struct uart_driver serial_omap_reg;
1284
1285static void serial_omap_console_putchar(struct uart_port *port, int ch)
1286{
1287 struct uart_omap_port *up = to_uart_omap_port(port);
1288
1289 wait_for_xmitr(up);
1290 serial_out(up, UART_TX, ch);
1291}
1292
1293static void
1294serial_omap_console_write(struct console *co, const char *s,
1295 unsigned int count)
1296{
1297 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1298 unsigned long flags;
1299 unsigned int ier;
1300 int locked = 1;
1301
1302 pm_runtime_get_sync(up->dev);
1303
1304 local_irq_save(flags);
1305 if (up->port.sysrq)
1306 locked = 0;
1307 else if (oops_in_progress)
1308 locked = spin_trylock(&up->port.lock);
1309 else
1310 spin_lock(&up->port.lock);
1311
1312 /*
1313 * First save the IER then disable the interrupts
1314 */
1315 ier = serial_in(up, UART_IER);
1316 serial_out(up, UART_IER, 0);
1317
1318 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1319
1320 /*
1321 * Finally, wait for transmitter to become empty
1322 * and restore the IER
1323 */
1324 wait_for_xmitr(up);
1325 serial_out(up, UART_IER, ier);
1326 /*
1327 * The receive handling will happen properly because the
1328 * receive ready bit will still be set; it is not cleared
1329 * on read. However, modem control will not, we must
1330 * call it if we have saved something in the saved flags
1331 * while processing with interrupts off.
1332 */
1333 if (up->msr_saved_flags)
1334 check_modem_status(up);
1335
1336 pm_runtime_mark_last_busy(up->dev);
1337 pm_runtime_put_autosuspend(up->dev);
1338 if (locked)
1339 spin_unlock(&up->port.lock);
1340 local_irq_restore(flags);
1341}
1342
1343static int __init
1344serial_omap_console_setup(struct console *co, char *options)
1345{
1346 struct uart_omap_port *up;
1347 int baud = 115200;
1348 int bits = 8;
1349 int parity = 'n';
1350 int flow = 'n';
1351
1352 if (serial_omap_console_ports[co->index] == NULL)
1353 return -ENODEV;
1354 up = serial_omap_console_ports[co->index];
1355
1356 if (options)
1357 uart_parse_options(options, &baud, &parity, &bits, &flow);
1358
1359 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1360}
1361
1362static struct console serial_omap_console = {
1363 .name = OMAP_SERIAL_NAME,
1364 .write = serial_omap_console_write,
1365 .device = uart_console_device,
1366 .setup = serial_omap_console_setup,
1367 .flags = CON_PRINTBUFFER,
1368 .index = -1,
1369 .data = &serial_omap_reg,
1370};
1371
1372static void serial_omap_add_console_port(struct uart_omap_port *up)
1373{
1374 serial_omap_console_ports[up->port.line] = up;
1375}
1376
1377#define OMAP_CONSOLE (&serial_omap_console)
1378
1379#else
1380
1381#define OMAP_CONSOLE NULL
1382
1383static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1384{}
1385
1386#endif
1387
1388/* Enable or disable the rs485 support */
1389static int
1390serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1391{
1392 struct uart_omap_port *up = to_uart_omap_port(port);
1393 unsigned int mode;
1394 int val;
1395
1396 pm_runtime_get_sync(up->dev);
1397
1398 /* Disable interrupts from this port */
1399 mode = up->ier;
1400 up->ier = 0;
1401 serial_out(up, UART_IER, 0);
1402
1403 /* Clamp the delays to [0, 100ms] */
1404 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1405 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1406
1407 /* store new config */
1408 port->rs485 = *rs485;
1409
1410 /*
1411 * Just as a precaution, only allow rs485
1412 * to be enabled if the gpio pin is valid
1413 */
1414 if (up->rts_gpiod) {
1415 /* enable / disable rts */
1416 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1417 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1418 val = (port->rs485.flags & val) ? 1 : 0;
1419 gpiod_set_value(up->rts_gpiod, val);
1420 } else
1421 port->rs485.flags &= ~SER_RS485_ENABLED;
1422
1423 /* Enable interrupts */
1424 up->ier = mode;
1425 serial_out(up, UART_IER, up->ier);
1426
1427 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1428 * TX FIFO is below the trigger level.
1429 */
1430 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1431 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1432 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1433 serial_out(up, UART_OMAP_SCR, up->scr);
1434 }
1435
1436 pm_runtime_mark_last_busy(up->dev);
1437 pm_runtime_put_autosuspend(up->dev);
1438
1439 return 0;
1440}
1441
1442static const struct uart_ops serial_omap_pops = {
1443 .tx_empty = serial_omap_tx_empty,
1444 .set_mctrl = serial_omap_set_mctrl,
1445 .get_mctrl = serial_omap_get_mctrl,
1446 .stop_tx = serial_omap_stop_tx,
1447 .start_tx = serial_omap_start_tx,
1448 .throttle = serial_omap_throttle,
1449 .unthrottle = serial_omap_unthrottle,
1450 .stop_rx = serial_omap_stop_rx,
1451 .enable_ms = serial_omap_enable_ms,
1452 .break_ctl = serial_omap_break_ctl,
1453 .startup = serial_omap_startup,
1454 .shutdown = serial_omap_shutdown,
1455 .set_termios = serial_omap_set_termios,
1456 .pm = serial_omap_pm,
1457 .type = serial_omap_type,
1458 .release_port = serial_omap_release_port,
1459 .request_port = serial_omap_request_port,
1460 .config_port = serial_omap_config_port,
1461 .verify_port = serial_omap_verify_port,
1462#ifdef CONFIG_CONSOLE_POLL
1463 .poll_put_char = serial_omap_poll_put_char,
1464 .poll_get_char = serial_omap_poll_get_char,
1465#endif
1466};
1467
1468static struct uart_driver serial_omap_reg = {
1469 .owner = THIS_MODULE,
1470 .driver_name = "OMAP-SERIAL",
1471 .dev_name = OMAP_SERIAL_NAME,
1472 .nr = OMAP_MAX_HSUART_PORTS,
1473 .cons = OMAP_CONSOLE,
1474};
1475
1476#ifdef CONFIG_PM_SLEEP
1477static int serial_omap_prepare(struct device *dev)
1478{
1479 struct uart_omap_port *up = dev_get_drvdata(dev);
1480
1481 up->is_suspending = true;
1482
1483 return 0;
1484}
1485
1486static void serial_omap_complete(struct device *dev)
1487{
1488 struct uart_omap_port *up = dev_get_drvdata(dev);
1489
1490 up->is_suspending = false;
1491}
1492
1493static int serial_omap_suspend(struct device *dev)
1494{
1495 struct uart_omap_port *up = dev_get_drvdata(dev);
1496
1497 uart_suspend_port(&serial_omap_reg, &up->port);
1498 flush_work(&up->qos_work);
1499
1500 if (device_may_wakeup(dev))
1501 serial_omap_enable_wakeup(up, true);
1502 else
1503 serial_omap_enable_wakeup(up, false);
1504
1505 return 0;
1506}
1507
1508static int serial_omap_resume(struct device *dev)
1509{
1510 struct uart_omap_port *up = dev_get_drvdata(dev);
1511
1512 if (device_may_wakeup(dev))
1513 serial_omap_enable_wakeup(up, false);
1514
1515 uart_resume_port(&serial_omap_reg, &up->port);
1516
1517 return 0;
1518}
1519#else
1520#define serial_omap_prepare NULL
1521#define serial_omap_complete NULL
1522#endif /* CONFIG_PM_SLEEP */
1523
1524static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1525{
1526 u32 mvr, scheme;
1527 u16 revision, major, minor;
1528
1529 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1530
1531 /* Check revision register scheme */
1532 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1533
1534 switch (scheme) {
1535 case 0: /* Legacy Scheme: OMAP2/3 */
1536 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1537 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1538 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1539 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1540 break;
1541 case 1:
1542 /* New Scheme: OMAP4+ */
1543 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1544 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1545 OMAP_UART_MVR_MAJ_SHIFT;
1546 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1547 break;
1548 default:
1549 dev_warn(up->dev,
1550 "Unknown %s revision, defaulting to highest\n",
1551 up->name);
1552 /* highest possible revision */
1553 major = 0xff;
1554 minor = 0xff;
1555 }
1556
1557 /* normalize revision for the driver */
1558 revision = UART_BUILD_REVISION(major, minor);
1559
1560 switch (revision) {
1561 case OMAP_UART_REV_46:
1562 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1563 UART_ERRATA_i291_DMA_FORCEIDLE);
1564 break;
1565 case OMAP_UART_REV_52:
1566 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1567 UART_ERRATA_i291_DMA_FORCEIDLE);
1568 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1569 break;
1570 case OMAP_UART_REV_63:
1571 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1572 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1573 break;
1574 default:
1575 break;
1576 }
1577}
1578
1579static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1580{
1581 struct omap_uart_port_info *omap_up_info;
1582
1583 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1584 if (!omap_up_info)
1585 return NULL; /* out of memory */
1586
1587 of_property_read_u32(dev->of_node, "clock-frequency",
1588 &omap_up_info->uartclk);
1589
1590 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1591
1592 return omap_up_info;
1593}
1594
1595static int serial_omap_probe_rs485(struct uart_omap_port *up,
1596 struct device *dev)
1597{
1598 struct serial_rs485 *rs485conf = &up->port.rs485;
1599 struct device_node *np = dev->of_node;
1600 enum gpiod_flags gflags;
1601 int ret;
1602
1603 rs485conf->flags = 0;
1604 up->rts_gpiod = NULL;
1605
1606 if (!np)
1607 return 0;
1608
1609 ret = uart_get_rs485_mode(&up->port);
1610 if (ret)
1611 return ret;
1612
1613 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1614 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1615 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1616 } else {
1617 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1618 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1619 }
1620
1621 /* check for tx enable gpio */
1622 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1623 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1624 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1625 if (IS_ERR(up->rts_gpiod)) {
1626 ret = PTR_ERR(up->rts_gpiod);
1627 if (ret == -EPROBE_DEFER)
1628 return ret;
1629 /*
1630 * FIXME: the code historically ignored any other error than
1631 * -EPROBE_DEFER and just went on without GPIO.
1632 */
1633 up->rts_gpiod = NULL;
1634 } else {
1635 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1636 }
1637
1638 return 0;
1639}
1640
1641static int serial_omap_probe(struct platform_device *pdev)
1642{
1643 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1644 struct uart_omap_port *up;
1645 struct resource *mem;
1646 void __iomem *base;
1647 int uartirq = 0;
1648 int wakeirq = 0;
1649 int ret;
1650
1651 /* The optional wakeirq may be specified in the board dts file */
1652 if (pdev->dev.of_node) {
1653 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1654 if (!uartirq)
1655 return -EPROBE_DEFER;
1656 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1657 omap_up_info = of_get_uart_port_info(&pdev->dev);
1658 pdev->dev.platform_data = omap_up_info;
1659 } else {
1660 uartirq = platform_get_irq(pdev, 0);
1661 if (uartirq < 0)
1662 return -EPROBE_DEFER;
1663 }
1664
1665 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1666 if (!up)
1667 return -ENOMEM;
1668
1669 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 base = devm_ioremap_resource(&pdev->dev, mem);
1671 if (IS_ERR(base))
1672 return PTR_ERR(base);
1673
1674 up->dev = &pdev->dev;
1675 up->port.dev = &pdev->dev;
1676 up->port.type = PORT_OMAP;
1677 up->port.iotype = UPIO_MEM;
1678 up->port.irq = uartirq;
1679 up->port.regshift = 2;
1680 up->port.fifosize = 64;
1681 up->port.ops = &serial_omap_pops;
1682 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1683
1684 if (pdev->dev.of_node)
1685 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1686 else
1687 ret = pdev->id;
1688
1689 if (ret < 0) {
1690 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1691 ret);
1692 goto err_port_line;
1693 }
1694 up->port.line = ret;
1695
1696 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1697 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1698 OMAP_MAX_HSUART_PORTS);
1699 ret = -ENXIO;
1700 goto err_port_line;
1701 }
1702
1703 up->wakeirq = wakeirq;
1704 if (!up->wakeirq)
1705 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1706 up->port.line);
1707
1708 ret = serial_omap_probe_rs485(up, &pdev->dev);
1709 if (ret < 0)
1710 goto err_rs485;
1711
1712 sprintf(up->name, "OMAP UART%d", up->port.line);
1713 up->port.mapbase = mem->start;
1714 up->port.membase = base;
1715 up->port.flags = omap_up_info->flags;
1716 up->port.uartclk = omap_up_info->uartclk;
1717 up->port.rs485_config = serial_omap_config_rs485;
1718 if (!up->port.uartclk) {
1719 up->port.uartclk = DEFAULT_CLK_SPEED;
1720 dev_warn(&pdev->dev,
1721 "No clock speed specified: using default: %d\n",
1722 DEFAULT_CLK_SPEED);
1723 }
1724
1725 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1726 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1727 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1728 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1729
1730 platform_set_drvdata(pdev, up);
1731 if (omap_up_info->autosuspend_timeout == 0)
1732 omap_up_info->autosuspend_timeout = -1;
1733
1734 device_init_wakeup(up->dev, true);
1735 pm_runtime_use_autosuspend(&pdev->dev);
1736 pm_runtime_set_autosuspend_delay(&pdev->dev,
1737 omap_up_info->autosuspend_timeout);
1738
1739 pm_runtime_irq_safe(&pdev->dev);
1740 pm_runtime_enable(&pdev->dev);
1741
1742 pm_runtime_get_sync(&pdev->dev);
1743
1744 omap_serial_fill_features_erratas(up);
1745
1746 ui[up->port.line] = up;
1747 serial_omap_add_console_port(up);
1748
1749 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1750 if (ret != 0)
1751 goto err_add_port;
1752
1753 pm_runtime_mark_last_busy(up->dev);
1754 pm_runtime_put_autosuspend(up->dev);
1755 return 0;
1756
1757err_add_port:
1758 pm_runtime_dont_use_autosuspend(&pdev->dev);
1759 pm_runtime_put_sync(&pdev->dev);
1760 pm_runtime_disable(&pdev->dev);
1761 cpu_latency_qos_remove_request(&up->pm_qos_request);
1762 device_init_wakeup(up->dev, false);
1763err_rs485:
1764err_port_line:
1765 return ret;
1766}
1767
1768static int serial_omap_remove(struct platform_device *dev)
1769{
1770 struct uart_omap_port *up = platform_get_drvdata(dev);
1771
1772 pm_runtime_get_sync(up->dev);
1773
1774 uart_remove_one_port(&serial_omap_reg, &up->port);
1775
1776 pm_runtime_dont_use_autosuspend(up->dev);
1777 pm_runtime_put_sync(up->dev);
1778 pm_runtime_disable(up->dev);
1779 cpu_latency_qos_remove_request(&up->pm_qos_request);
1780 device_init_wakeup(&dev->dev, false);
1781
1782 return 0;
1783}
1784
1785/*
1786 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1787 * The access to uart register after MDR1 Access
1788 * causes UART to corrupt data.
1789 *
1790 * Need a delay =
1791 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1792 * give 10 times as much
1793 */
1794static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1795{
1796 u8 timeout = 255;
1797
1798 serial_out(up, UART_OMAP_MDR1, mdr1);
1799 udelay(2);
1800 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1801 UART_FCR_CLEAR_RCVR);
1802 /*
1803 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1804 * TX_FIFO_E bit is 1.
1805 */
1806 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1807 (UART_LSR_THRE | UART_LSR_DR))) {
1808 timeout--;
1809 if (!timeout) {
1810 /* Should *never* happen. we warn and carry on */
1811 dev_crit(up->dev, "Errata i202: timedout %x\n",
1812 serial_in(up, UART_LSR));
1813 break;
1814 }
1815 udelay(1);
1816 }
1817}
1818
1819#ifdef CONFIG_PM
1820static void serial_omap_restore_context(struct uart_omap_port *up)
1821{
1822 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1823 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1824 else
1825 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1826
1827 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1828 serial_out(up, UART_EFR, UART_EFR_ECB);
1829 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1830 serial_out(up, UART_IER, 0x0);
1831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1832 serial_out(up, UART_DLL, up->dll);
1833 serial_out(up, UART_DLM, up->dlh);
1834 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1835 serial_out(up, UART_IER, up->ier);
1836 serial_out(up, UART_FCR, up->fcr);
1837 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1838 serial_out(up, UART_MCR, up->mcr);
1839 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1840 serial_out(up, UART_OMAP_SCR, up->scr);
1841 serial_out(up, UART_EFR, up->efr);
1842 serial_out(up, UART_LCR, up->lcr);
1843 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1844 serial_omap_mdr1_errataset(up, up->mdr1);
1845 else
1846 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1847 serial_out(up, UART_OMAP_WER, up->wer);
1848}
1849
1850static int serial_omap_runtime_suspend(struct device *dev)
1851{
1852 struct uart_omap_port *up = dev_get_drvdata(dev);
1853
1854 if (!up)
1855 return -EINVAL;
1856
1857 /*
1858 * When using 'no_console_suspend', the console UART must not be
1859 * suspended. Since driver suspend is managed by runtime suspend,
1860 * preventing runtime suspend (by returning error) will keep device
1861 * active during suspend.
1862 */
1863 if (up->is_suspending && !console_suspend_enabled &&
1864 uart_console(&up->port))
1865 return -EBUSY;
1866
1867 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1868
1869 serial_omap_enable_wakeup(up, true);
1870
1871 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1872 schedule_work(&up->qos_work);
1873
1874 return 0;
1875}
1876
1877static int serial_omap_runtime_resume(struct device *dev)
1878{
1879 struct uart_omap_port *up = dev_get_drvdata(dev);
1880
1881 int loss_cnt = serial_omap_get_context_loss_count(up);
1882
1883 serial_omap_enable_wakeup(up, false);
1884
1885 if (loss_cnt < 0) {
1886 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1887 loss_cnt);
1888 serial_omap_restore_context(up);
1889 } else if (up->context_loss_cnt != loss_cnt) {
1890 serial_omap_restore_context(up);
1891 }
1892 up->latency = up->calc_latency;
1893 schedule_work(&up->qos_work);
1894
1895 return 0;
1896}
1897#endif
1898
1899static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1900 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1901 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1902 serial_omap_runtime_resume, NULL)
1903 .prepare = serial_omap_prepare,
1904 .complete = serial_omap_complete,
1905};
1906
1907#if defined(CONFIG_OF)
1908static const struct of_device_id omap_serial_of_match[] = {
1909 { .compatible = "ti,omap2-uart" },
1910 { .compatible = "ti,omap3-uart" },
1911 { .compatible = "ti,omap4-uart" },
1912 {},
1913};
1914MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1915#endif
1916
1917static struct platform_driver serial_omap_driver = {
1918 .probe = serial_omap_probe,
1919 .remove = serial_omap_remove,
1920 .driver = {
1921 .name = OMAP_SERIAL_DRIVER_NAME,
1922 .pm = &serial_omap_dev_pm_ops,
1923 .of_match_table = of_match_ptr(omap_serial_of_match),
1924 },
1925};
1926
1927static int __init serial_omap_init(void)
1928{
1929 int ret;
1930
1931 ret = uart_register_driver(&serial_omap_reg);
1932 if (ret != 0)
1933 return ret;
1934 ret = platform_driver_register(&serial_omap_driver);
1935 if (ret != 0)
1936 uart_unregister_driver(&serial_omap_reg);
1937 return ret;
1938}
1939
1940static void __exit serial_omap_exit(void)
1941{
1942 platform_driver_unregister(&serial_omap_driver);
1943 uart_unregister_driver(&serial_omap_reg);
1944}
1945
1946module_init(serial_omap_init);
1947module_exit(serial_omap_exit);
1948
1949MODULE_DESCRIPTION("OMAP High Speed UART driver");
1950MODULE_LICENSE("GPL");
1951MODULE_AUTHOR("Texas Instruments Inc");