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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3#include <linux/module.h>
4#include <linux/io.h>
5#include <linux/platform_device.h>
6#include <linux/console.h>
7#include <linux/sysrq.h>
8#include <linux/serial_core.h>
9#include <linux/tty_flip.h>
10#include <linux/slab.h>
11#include <linux/clk.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14
15#include <linux/platform_data/efm32-uart.h>
16
17#define DRIVER_NAME "efm32-uart"
18#define DEV_NAME "ttyefm"
19
20#define UARTn_CTRL 0x00
21#define UARTn_CTRL_SYNC 0x0001
22#define UARTn_CTRL_TXBIL 0x1000
23
24#define UARTn_FRAME 0x04
25#define UARTn_FRAME_DATABITS__MASK 0x000f
26#define UARTn_FRAME_DATABITS(n) ((n) - 3)
27#define UARTn_FRAME_PARITY__MASK 0x0300
28#define UARTn_FRAME_PARITY_NONE 0x0000
29#define UARTn_FRAME_PARITY_EVEN 0x0200
30#define UARTn_FRAME_PARITY_ODD 0x0300
31#define UARTn_FRAME_STOPBITS_HALF 0x0000
32#define UARTn_FRAME_STOPBITS_ONE 0x1000
33#define UARTn_FRAME_STOPBITS_TWO 0x3000
34
35#define UARTn_CMD 0x0c
36#define UARTn_CMD_RXEN 0x0001
37#define UARTn_CMD_RXDIS 0x0002
38#define UARTn_CMD_TXEN 0x0004
39#define UARTn_CMD_TXDIS 0x0008
40
41#define UARTn_STATUS 0x10
42#define UARTn_STATUS_TXENS 0x0002
43#define UARTn_STATUS_TXC 0x0020
44#define UARTn_STATUS_TXBL 0x0040
45#define UARTn_STATUS_RXDATAV 0x0080
46
47#define UARTn_CLKDIV 0x14
48
49#define UARTn_RXDATAX 0x18
50#define UARTn_RXDATAX_RXDATA__MASK 0x01ff
51#define UARTn_RXDATAX_PERR 0x4000
52#define UARTn_RXDATAX_FERR 0x8000
53/*
54 * This is a software only flag used for ignore_status_mask and
55 * read_status_mask! It's used for breaks that the hardware doesn't report
56 * explicitly.
57 */
58#define SW_UARTn_RXDATAX_BERR 0x2000
59
60#define UARTn_TXDATA 0x34
61
62#define UARTn_IF 0x40
63#define UARTn_IF_TXC 0x0001
64#define UARTn_IF_TXBL 0x0002
65#define UARTn_IF_RXDATAV 0x0004
66#define UARTn_IF_RXOF 0x0010
67
68#define UARTn_IFS 0x44
69#define UARTn_IFC 0x48
70#define UARTn_IEN 0x4c
71
72#define UARTn_ROUTE 0x54
73#define UARTn_ROUTE_LOCATION__MASK 0x0700
74#define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
75#define UARTn_ROUTE_RXPEN 0x0001
76#define UARTn_ROUTE_TXPEN 0x0002
77
78struct efm32_uart_port {
79 struct uart_port port;
80 unsigned int txirq;
81 struct clk *clk;
82 struct efm32_uart_pdata pdata;
83};
84#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
85#define efm_debug(efm_port, format, arg...) \
86 dev_dbg(efm_port->port.dev, format, ##arg)
87
88static void efm32_uart_write32(struct efm32_uart_port *efm_port,
89 u32 value, unsigned offset)
90{
91 writel_relaxed(value, efm_port->port.membase + offset);
92}
93
94static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
95 unsigned offset)
96{
97 return readl_relaxed(efm_port->port.membase + offset);
98}
99
100static unsigned int efm32_uart_tx_empty(struct uart_port *port)
101{
102 struct efm32_uart_port *efm_port = to_efm_port(port);
103 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
104
105 if (status & UARTn_STATUS_TXC)
106 return TIOCSER_TEMT;
107 else
108 return 0;
109}
110
111static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
112{
113 /* sorry, neither handshaking lines nor loop functionallity */
114}
115
116static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
117{
118 /* sorry, no handshaking lines available */
119 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
120}
121
122static void efm32_uart_stop_tx(struct uart_port *port)
123{
124 struct efm32_uart_port *efm_port = to_efm_port(port);
125 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
126
127 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
128 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
129 efm32_uart_write32(efm_port, ien, UARTn_IEN);
130}
131
132static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
133{
134 struct uart_port *port = &efm_port->port;
135 struct circ_buf *xmit = &port->state->xmit;
136
137 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
138 UARTn_STATUS_TXBL) {
139 if (port->x_char) {
140 port->icount.tx++;
141 efm32_uart_write32(efm_port, port->x_char,
142 UARTn_TXDATA);
143 port->x_char = 0;
144 continue;
145 }
146 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
147 port->icount.tx++;
148 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
149 UARTn_TXDATA);
150 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
151 } else
152 break;
153 }
154
155 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
156 uart_write_wakeup(port);
157
158 if (!port->x_char && uart_circ_empty(xmit) &&
159 efm32_uart_read32(efm_port, UARTn_STATUS) &
160 UARTn_STATUS_TXC)
161 efm32_uart_stop_tx(port);
162}
163
164static void efm32_uart_start_tx(struct uart_port *port)
165{
166 struct efm32_uart_port *efm_port = to_efm_port(port);
167 u32 ien;
168
169 efm32_uart_write32(efm_port,
170 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
171 ien = efm32_uart_read32(efm_port, UARTn_IEN);
172 efm32_uart_write32(efm_port,
173 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
174 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
175
176 efm32_uart_tx_chars(efm_port);
177}
178
179static void efm32_uart_stop_rx(struct uart_port *port)
180{
181 struct efm32_uart_port *efm_port = to_efm_port(port);
182
183 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
184}
185
186static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
187{
188 /* not possible without fiddling with gpios */
189}
190
191static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
192{
193 struct uart_port *port = &efm_port->port;
194
195 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
196 UARTn_STATUS_RXDATAV) {
197 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
198 int flag = 0;
199
200 /*
201 * This is a reserved bit and I only saw it read as 0. But to be
202 * sure not to be confused too much by new devices adhere to the
203 * warning in the reference manual that reserved bits might
204 * read as 1 in the future.
205 */
206 rxdata &= ~SW_UARTn_RXDATAX_BERR;
207
208 port->icount.rx++;
209
210 if ((rxdata & UARTn_RXDATAX_FERR) &&
211 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
212 rxdata |= SW_UARTn_RXDATAX_BERR;
213 port->icount.brk++;
214 if (uart_handle_break(port))
215 continue;
216 } else if (rxdata & UARTn_RXDATAX_PERR)
217 port->icount.parity++;
218 else if (rxdata & UARTn_RXDATAX_FERR)
219 port->icount.frame++;
220
221 rxdata &= port->read_status_mask;
222
223 if (rxdata & SW_UARTn_RXDATAX_BERR)
224 flag = TTY_BREAK;
225 else if (rxdata & UARTn_RXDATAX_PERR)
226 flag = TTY_PARITY;
227 else if (rxdata & UARTn_RXDATAX_FERR)
228 flag = TTY_FRAME;
229 else if (uart_handle_sysrq_char(port,
230 rxdata & UARTn_RXDATAX_RXDATA__MASK))
231 continue;
232
233 if ((rxdata & port->ignore_status_mask) == 0)
234 tty_insert_flip_char(&port->state->port,
235 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
236 }
237}
238
239static irqreturn_t efm32_uart_rxirq(int irq, void *data)
240{
241 struct efm32_uart_port *efm_port = data;
242 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
243 int handled = IRQ_NONE;
244 struct uart_port *port = &efm_port->port;
245 struct tty_port *tport = &port->state->port;
246
247 spin_lock(&port->lock);
248
249 if (irqflag & UARTn_IF_RXDATAV) {
250 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
251 efm32_uart_rx_chars(efm_port);
252
253 handled = IRQ_HANDLED;
254 }
255
256 if (irqflag & UARTn_IF_RXOF) {
257 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
258 port->icount.overrun++;
259 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
260
261 handled = IRQ_HANDLED;
262 }
263
264 spin_unlock(&port->lock);
265
266 tty_flip_buffer_push(tport);
267
268 return handled;
269}
270
271static irqreturn_t efm32_uart_txirq(int irq, void *data)
272{
273 struct efm32_uart_port *efm_port = data;
274 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
275
276 /* TXBL doesn't need to be cleared */
277 if (irqflag & UARTn_IF_TXC)
278 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
279
280 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
281 efm32_uart_tx_chars(efm_port);
282 return IRQ_HANDLED;
283 } else
284 return IRQ_NONE;
285}
286
287static int efm32_uart_startup(struct uart_port *port)
288{
289 struct efm32_uart_port *efm_port = to_efm_port(port);
290 int ret;
291
292 ret = clk_enable(efm_port->clk);
293 if (ret) {
294 efm_debug(efm_port, "failed to enable clk\n");
295 goto err_clk_enable;
296 }
297 port->uartclk = clk_get_rate(efm_port->clk);
298
299 /* Enable pins at configured location */
300 efm32_uart_write32(efm_port,
301 UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
302 UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
303 UARTn_ROUTE);
304
305 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
306 DRIVER_NAME, efm_port);
307 if (ret) {
308 efm_debug(efm_port, "failed to register rxirq\n");
309 goto err_request_irq_rx;
310 }
311
312 /* disable all irqs */
313 efm32_uart_write32(efm_port, 0, UARTn_IEN);
314
315 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
316 DRIVER_NAME, efm_port);
317 if (ret) {
318 efm_debug(efm_port, "failed to register txirq\n");
319 free_irq(port->irq, efm_port);
320err_request_irq_rx:
321
322 clk_disable(efm_port->clk);
323 } else {
324 efm32_uart_write32(efm_port,
325 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
326 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
327 }
328
329err_clk_enable:
330 return ret;
331}
332
333static void efm32_uart_shutdown(struct uart_port *port)
334{
335 struct efm32_uart_port *efm_port = to_efm_port(port);
336
337 efm32_uart_write32(efm_port, 0, UARTn_IEN);
338 free_irq(port->irq, efm_port);
339
340 clk_disable(efm_port->clk);
341}
342
343static void efm32_uart_set_termios(struct uart_port *port,
344 struct ktermios *new, struct ktermios *old)
345{
346 struct efm32_uart_port *efm_port = to_efm_port(port);
347 unsigned long flags;
348 unsigned baud;
349 u32 clkdiv;
350 u32 frame = 0;
351
352 /* no modem control lines */
353 new->c_cflag &= ~(CRTSCTS | CMSPAR);
354
355 baud = uart_get_baud_rate(port, new, old,
356 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
357 DIV_ROUND_CLOSEST(port->uartclk, 16));
358
359 switch (new->c_cflag & CSIZE) {
360 case CS5:
361 frame |= UARTn_FRAME_DATABITS(5);
362 break;
363 case CS6:
364 frame |= UARTn_FRAME_DATABITS(6);
365 break;
366 case CS7:
367 frame |= UARTn_FRAME_DATABITS(7);
368 break;
369 case CS8:
370 frame |= UARTn_FRAME_DATABITS(8);
371 break;
372 }
373
374 if (new->c_cflag & CSTOPB)
375 /* the receiver only verifies the first stop bit */
376 frame |= UARTn_FRAME_STOPBITS_TWO;
377 else
378 frame |= UARTn_FRAME_STOPBITS_ONE;
379
380 if (new->c_cflag & PARENB) {
381 if (new->c_cflag & PARODD)
382 frame |= UARTn_FRAME_PARITY_ODD;
383 else
384 frame |= UARTn_FRAME_PARITY_EVEN;
385 } else
386 frame |= UARTn_FRAME_PARITY_NONE;
387
388 /*
389 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
390 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
391 */
392 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
393
394 spin_lock_irqsave(&port->lock, flags);
395
396 efm32_uart_write32(efm_port,
397 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
398
399 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
400 if (new->c_iflag & INPCK)
401 port->read_status_mask |=
402 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
403 if (new->c_iflag & (IGNBRK | BRKINT | PARMRK))
404 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
405
406 port->ignore_status_mask = 0;
407 if (new->c_iflag & IGNPAR)
408 port->ignore_status_mask |=
409 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
410 if (new->c_iflag & IGNBRK)
411 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
412
413 uart_update_timeout(port, new->c_cflag, baud);
414
415 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
416 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
417 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
418
419 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
420 UARTn_CMD);
421
422 spin_unlock_irqrestore(&port->lock, flags);
423}
424
425static const char *efm32_uart_type(struct uart_port *port)
426{
427 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
428}
429
430static void efm32_uart_release_port(struct uart_port *port)
431{
432 struct efm32_uart_port *efm_port = to_efm_port(port);
433
434 clk_unprepare(efm_port->clk);
435 clk_put(efm_port->clk);
436 iounmap(port->membase);
437}
438
439static int efm32_uart_request_port(struct uart_port *port)
440{
441 struct efm32_uart_port *efm_port = to_efm_port(port);
442 int ret;
443
444 port->membase = ioremap(port->mapbase, 60);
445 if (!efm_port->port.membase) {
446 ret = -ENOMEM;
447 efm_debug(efm_port, "failed to remap\n");
448 goto err_ioremap;
449 }
450
451 efm_port->clk = clk_get(port->dev, NULL);
452 if (IS_ERR(efm_port->clk)) {
453 ret = PTR_ERR(efm_port->clk);
454 efm_debug(efm_port, "failed to get clock\n");
455 goto err_clk_get;
456 }
457
458 ret = clk_prepare(efm_port->clk);
459 if (ret) {
460 clk_put(efm_port->clk);
461err_clk_get:
462
463 iounmap(port->membase);
464err_ioremap:
465 return ret;
466 }
467 return 0;
468}
469
470static void efm32_uart_config_port(struct uart_port *port, int type)
471{
472 if (type & UART_CONFIG_TYPE &&
473 !efm32_uart_request_port(port))
474 port->type = PORT_EFMUART;
475}
476
477static int efm32_uart_verify_port(struct uart_port *port,
478 struct serial_struct *serinfo)
479{
480 int ret = 0;
481
482 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
483 ret = -EINVAL;
484
485 return ret;
486}
487
488static const struct uart_ops efm32_uart_pops = {
489 .tx_empty = efm32_uart_tx_empty,
490 .set_mctrl = efm32_uart_set_mctrl,
491 .get_mctrl = efm32_uart_get_mctrl,
492 .stop_tx = efm32_uart_stop_tx,
493 .start_tx = efm32_uart_start_tx,
494 .stop_rx = efm32_uart_stop_rx,
495 .break_ctl = efm32_uart_break_ctl,
496 .startup = efm32_uart_startup,
497 .shutdown = efm32_uart_shutdown,
498 .set_termios = efm32_uart_set_termios,
499 .type = efm32_uart_type,
500 .release_port = efm32_uart_release_port,
501 .request_port = efm32_uart_request_port,
502 .config_port = efm32_uart_config_port,
503 .verify_port = efm32_uart_verify_port,
504};
505
506static struct efm32_uart_port *efm32_uart_ports[5];
507
508#ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
509static void efm32_uart_console_putchar(struct uart_port *port, int ch)
510{
511 struct efm32_uart_port *efm_port = to_efm_port(port);
512 unsigned int timeout = 0x400;
513 u32 status;
514
515 while (1) {
516 status = efm32_uart_read32(efm_port, UARTn_STATUS);
517
518 if (status & UARTn_STATUS_TXBL)
519 break;
520 if (!timeout--)
521 return;
522 }
523 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
524}
525
526static void efm32_uart_console_write(struct console *co, const char *s,
527 unsigned int count)
528{
529 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
530 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
531 unsigned int timeout = 0x400;
532
533 if (!(status & UARTn_STATUS_TXENS))
534 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
535
536 uart_console_write(&efm_port->port, s, count,
537 efm32_uart_console_putchar);
538
539 /* Wait for the transmitter to become empty */
540 while (1) {
541 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
542 if (status & UARTn_STATUS_TXC)
543 break;
544 if (!timeout--)
545 break;
546 }
547
548 if (!(status & UARTn_STATUS_TXENS))
549 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
550}
551
552static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
553 int *baud, int *parity, int *bits)
554{
555 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
556 u32 route, clkdiv, frame;
557
558 if (ctrl & UARTn_CTRL_SYNC)
559 /* not operating in async mode */
560 return;
561
562 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
563 if (!(route & UARTn_ROUTE_TXPEN))
564 /* tx pin not routed */
565 return;
566
567 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
568
569 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
570 16 * (4 + (clkdiv >> 6)));
571
572 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
573 switch (frame & UARTn_FRAME_PARITY__MASK) {
574 case UARTn_FRAME_PARITY_ODD:
575 *parity = 'o';
576 break;
577 case UARTn_FRAME_PARITY_EVEN:
578 *parity = 'e';
579 break;
580 default:
581 *parity = 'n';
582 }
583
584 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
585 UARTn_FRAME_DATABITS(4) + 4;
586
587 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
588 *baud, *parity, *bits);
589}
590
591static int efm32_uart_console_setup(struct console *co, char *options)
592{
593 struct efm32_uart_port *efm_port;
594 int baud = 115200;
595 int bits = 8;
596 int parity = 'n';
597 int flow = 'n';
598 int ret;
599
600 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
601 unsigned i;
602 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
603 if (efm32_uart_ports[i]) {
604 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
605 i, co->index);
606 co->index = i;
607 break;
608 }
609 }
610 }
611
612 efm_port = efm32_uart_ports[co->index];
613 if (!efm_port) {
614 pr_warn("efm32-console: No port at %d\n", co->index);
615 return -ENODEV;
616 }
617
618 ret = clk_prepare(efm_port->clk);
619 if (ret) {
620 dev_warn(efm_port->port.dev,
621 "console: clk_prepare failed: %d\n", ret);
622 return ret;
623 }
624
625 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
626
627 if (options)
628 uart_parse_options(options, &baud, &parity, &bits, &flow);
629 else
630 efm32_uart_console_get_options(efm_port,
631 &baud, &parity, &bits);
632
633 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
634}
635
636static struct uart_driver efm32_uart_reg;
637
638static struct console efm32_uart_console = {
639 .name = DEV_NAME,
640 .write = efm32_uart_console_write,
641 .device = uart_console_device,
642 .setup = efm32_uart_console_setup,
643 .flags = CON_PRINTBUFFER,
644 .index = -1,
645 .data = &efm32_uart_reg,
646};
647
648#else
649#define efm32_uart_console (*(struct console *)NULL)
650#endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
651
652static struct uart_driver efm32_uart_reg = {
653 .owner = THIS_MODULE,
654 .driver_name = DRIVER_NAME,
655 .dev_name = DEV_NAME,
656 .nr = ARRAY_SIZE(efm32_uart_ports),
657 .cons = &efm32_uart_console,
658};
659
660static int efm32_uart_probe_dt(struct platform_device *pdev,
661 struct efm32_uart_port *efm_port)
662{
663 struct device_node *np = pdev->dev.of_node;
664 u32 location;
665 int ret;
666
667 if (!np)
668 return 1;
669
670 ret = of_property_read_u32(np, "energymicro,location", &location);
671
672 if (ret)
673 /* fall back to wrongly namespaced property */
674 ret = of_property_read_u32(np, "efm32,location", &location);
675
676 if (ret)
677 /* fall back to old and (wrongly) generic property "location" */
678 ret = of_property_read_u32(np, "location", &location);
679
680 if (!ret) {
681 if (location > 5) {
682 dev_err(&pdev->dev, "invalid location\n");
683 return -EINVAL;
684 }
685 efm_debug(efm_port, "using location %u\n", location);
686 efm_port->pdata.location = location;
687 } else {
688 efm_debug(efm_port, "fall back to location 0\n");
689 }
690
691 ret = of_alias_get_id(np, "serial");
692 if (ret < 0) {
693 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
694 return ret;
695 } else {
696 efm_port->port.line = ret;
697 return 0;
698 }
699
700}
701
702static int efm32_uart_probe(struct platform_device *pdev)
703{
704 struct efm32_uart_port *efm_port;
705 struct resource *res;
706 unsigned int line;
707 int ret;
708
709 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
710 if (!efm_port) {
711 dev_dbg(&pdev->dev, "failed to allocate private data\n");
712 return -ENOMEM;
713 }
714
715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716 if (!res) {
717 ret = -ENODEV;
718 dev_dbg(&pdev->dev, "failed to determine base address\n");
719 goto err_get_base;
720 }
721
722 if (resource_size(res) < 60) {
723 ret = -EINVAL;
724 dev_dbg(&pdev->dev, "memory resource too small\n");
725 goto err_too_small;
726 }
727
728 ret = platform_get_irq(pdev, 0);
729 if (ret <= 0) {
730 dev_dbg(&pdev->dev, "failed to get rx irq\n");
731 goto err_get_rxirq;
732 }
733
734 efm_port->port.irq = ret;
735
736 ret = platform_get_irq(pdev, 1);
737 if (ret <= 0)
738 ret = efm_port->port.irq + 1;
739
740 efm_port->txirq = ret;
741
742 efm_port->port.dev = &pdev->dev;
743 efm_port->port.mapbase = res->start;
744 efm_port->port.type = PORT_EFMUART;
745 efm_port->port.iotype = UPIO_MEM32;
746 efm_port->port.fifosize = 2;
747 efm_port->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_EFM32_UART_CONSOLE);
748 efm_port->port.ops = &efm32_uart_pops;
749 efm_port->port.flags = UPF_BOOT_AUTOCONF;
750
751 ret = efm32_uart_probe_dt(pdev, efm_port);
752 if (ret > 0) {
753 /* not created by device tree */
754 const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
755
756 efm_port->port.line = pdev->id;
757
758 if (pdata)
759 efm_port->pdata = *pdata;
760 } else if (ret < 0)
761 goto err_probe_dt;
762
763 line = efm_port->port.line;
764
765 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
766 efm32_uart_ports[line] = efm_port;
767
768 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
769 if (ret) {
770 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
771
772 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
773 efm32_uart_ports[line] = NULL;
774err_probe_dt:
775err_get_rxirq:
776err_too_small:
777err_get_base:
778 kfree(efm_port);
779 } else {
780 platform_set_drvdata(pdev, efm_port);
781 dev_dbg(&pdev->dev, "\\o/\n");
782 }
783
784 return ret;
785}
786
787static int efm32_uart_remove(struct platform_device *pdev)
788{
789 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
790 unsigned int line = efm_port->port.line;
791
792 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
793
794 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
795 efm32_uart_ports[line] = NULL;
796
797 kfree(efm_port);
798
799 return 0;
800}
801
802static const struct of_device_id efm32_uart_dt_ids[] = {
803 {
804 .compatible = "energymicro,efm32-uart",
805 }, {
806 /* doesn't follow the "vendor,device" scheme, don't use */
807 .compatible = "efm32,uart",
808 }, {
809 /* sentinel */
810 }
811};
812MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
813
814static struct platform_driver efm32_uart_driver = {
815 .probe = efm32_uart_probe,
816 .remove = efm32_uart_remove,
817
818 .driver = {
819 .name = DRIVER_NAME,
820 .of_match_table = efm32_uart_dt_ids,
821 },
822};
823
824static int __init efm32_uart_init(void)
825{
826 int ret;
827
828 ret = uart_register_driver(&efm32_uart_reg);
829 if (ret)
830 return ret;
831
832 ret = platform_driver_register(&efm32_uart_driver);
833 if (ret)
834 uart_unregister_driver(&efm32_uart_reg);
835
836 pr_info("EFM32 UART/USART driver\n");
837
838 return ret;
839}
840module_init(efm32_uart_init);
841
842static void __exit efm32_uart_exit(void)
843{
844 platform_driver_unregister(&efm32_uart_driver);
845 uart_unregister_driver(&efm32_uart_reg);
846}
847module_exit(efm32_uart_exit);
848
849MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
850MODULE_DESCRIPTION("EFM32 UART/USART driver");
851MODULE_LICENSE("GPL v2");
852MODULE_ALIAS("platform:" DRIVER_NAME);