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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/platform_device.h>
24#include <linux/sysrq.h>
25#include <linux/device.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/amba/bus.h>
31#include <linux/amba/serial.h>
32#include <linux/clk.h>
33#include <linux/slab.h>
34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/scatterlist.h>
37#include <linux/delay.h>
38#include <linux/types.h>
39#include <linux/of.h>
40#include <linux/pinctrl/consumer.h>
41#include <linux/sizes.h>
42#include <linux/io.h>
43#include <linux/acpi.h>
44
45#define UART_NR 14
46
47#define SERIAL_AMBA_MAJOR 204
48#define SERIAL_AMBA_MINOR 64
49#define SERIAL_AMBA_NR UART_NR
50
51#define AMBA_ISR_PASS_LIMIT 256
52
53#define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE)
54#define UART_DUMMY_DR_RX BIT(16)
55
56enum {
57 REG_DR,
58 REG_ST_DMAWM,
59 REG_ST_TIMEOUT,
60 REG_FR,
61 REG_LCRH_RX,
62 REG_LCRH_TX,
63 REG_IBRD,
64 REG_FBRD,
65 REG_CR,
66 REG_IFLS,
67 REG_IMSC,
68 REG_RIS,
69 REG_MIS,
70 REG_ICR,
71 REG_DMACR,
72 REG_ST_XFCR,
73 REG_ST_XON1,
74 REG_ST_XON2,
75 REG_ST_XOFF1,
76 REG_ST_XOFF2,
77 REG_ST_ITCR,
78 REG_ST_ITIP,
79 REG_ST_ABCR,
80 REG_ST_ABIMSC,
81
82 /* The size of the array - must be last */
83 REG_ARRAY_SIZE,
84};
85
86static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
87 [REG_DR] = UART01x_DR,
88 [REG_FR] = UART01x_FR,
89 [REG_LCRH_RX] = UART011_LCRH,
90 [REG_LCRH_TX] = UART011_LCRH,
91 [REG_IBRD] = UART011_IBRD,
92 [REG_FBRD] = UART011_FBRD,
93 [REG_CR] = UART011_CR,
94 [REG_IFLS] = UART011_IFLS,
95 [REG_IMSC] = UART011_IMSC,
96 [REG_RIS] = UART011_RIS,
97 [REG_MIS] = UART011_MIS,
98 [REG_ICR] = UART011_ICR,
99 [REG_DMACR] = UART011_DMACR,
100};
101
102/* There is by now at least one vendor with differing details, so handle it */
103struct vendor_data {
104 const u16 *reg_offset;
105 unsigned int ifls;
106 unsigned int fr_busy;
107 unsigned int fr_dsr;
108 unsigned int fr_cts;
109 unsigned int fr_ri;
110 unsigned int inv_fr;
111 bool access_32b;
112 bool oversampling;
113 bool dma_threshold;
114 bool cts_event_workaround;
115 bool always_enabled;
116 bool fixed_options;
117
118 unsigned int (*get_fifosize)(struct amba_device *dev);
119};
120
121static unsigned int get_fifosize_arm(struct amba_device *dev)
122{
123 return amba_rev(dev) < 3 ? 16 : 32;
124}
125
126static struct vendor_data vendor_arm = {
127 .reg_offset = pl011_std_offsets,
128 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8,
129 .fr_busy = UART01x_FR_BUSY,
130 .fr_dsr = UART01x_FR_DSR,
131 .fr_cts = UART01x_FR_CTS,
132 .fr_ri = UART011_FR_RI,
133 .oversampling = false,
134 .dma_threshold = false,
135 .cts_event_workaround = false,
136 .always_enabled = false,
137 .fixed_options = false,
138 .get_fifosize = get_fifosize_arm,
139};
140
141static const struct vendor_data vendor_sbsa = {
142 .reg_offset = pl011_std_offsets,
143 .fr_busy = UART01x_FR_BUSY,
144 .fr_dsr = UART01x_FR_DSR,
145 .fr_cts = UART01x_FR_CTS,
146 .fr_ri = UART011_FR_RI,
147 .access_32b = true,
148 .oversampling = false,
149 .dma_threshold = false,
150 .cts_event_workaround = false,
151 .always_enabled = true,
152 .fixed_options = true,
153};
154
155#ifdef CONFIG_ACPI_SPCR_TABLE
156static const struct vendor_data vendor_qdt_qdf2400_e44 = {
157 .reg_offset = pl011_std_offsets,
158 .fr_busy = UART011_FR_TXFE,
159 .fr_dsr = UART01x_FR_DSR,
160 .fr_cts = UART01x_FR_CTS,
161 .fr_ri = UART011_FR_RI,
162 .inv_fr = UART011_FR_TXFE,
163 .access_32b = true,
164 .oversampling = false,
165 .dma_threshold = false,
166 .cts_event_workaround = false,
167 .always_enabled = true,
168 .fixed_options = true,
169};
170#endif
171
172static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
173 [REG_DR] = UART01x_DR,
174 [REG_ST_DMAWM] = ST_UART011_DMAWM,
175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
176 [REG_FR] = UART01x_FR,
177 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
178 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
179 [REG_IBRD] = UART011_IBRD,
180 [REG_FBRD] = UART011_FBRD,
181 [REG_CR] = UART011_CR,
182 [REG_IFLS] = UART011_IFLS,
183 [REG_IMSC] = UART011_IMSC,
184 [REG_RIS] = UART011_RIS,
185 [REG_MIS] = UART011_MIS,
186 [REG_ICR] = UART011_ICR,
187 [REG_DMACR] = UART011_DMACR,
188 [REG_ST_XFCR] = ST_UART011_XFCR,
189 [REG_ST_XON1] = ST_UART011_XON1,
190 [REG_ST_XON2] = ST_UART011_XON2,
191 [REG_ST_XOFF1] = ST_UART011_XOFF1,
192 [REG_ST_XOFF2] = ST_UART011_XOFF2,
193 [REG_ST_ITCR] = ST_UART011_ITCR,
194 [REG_ST_ITIP] = ST_UART011_ITIP,
195 [REG_ST_ABCR] = ST_UART011_ABCR,
196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
197};
198
199static unsigned int get_fifosize_st(struct amba_device *dev)
200{
201 return 64;
202}
203
204static struct vendor_data vendor_st = {
205 .reg_offset = pl011_st_offsets,
206 .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF,
207 .fr_busy = UART01x_FR_BUSY,
208 .fr_dsr = UART01x_FR_DSR,
209 .fr_cts = UART01x_FR_CTS,
210 .fr_ri = UART011_FR_RI,
211 .oversampling = true,
212 .dma_threshold = true,
213 .cts_event_workaround = true,
214 .always_enabled = false,
215 .fixed_options = false,
216 .get_fifosize = get_fifosize_st,
217};
218
219/* Deals with DMA transactions */
220
221struct pl011_dmabuf {
222 dma_addr_t dma;
223 size_t len;
224 char *buf;
225};
226
227struct pl011_dmarx_data {
228 struct dma_chan *chan;
229 struct completion complete;
230 bool use_buf_b;
231 struct pl011_dmabuf dbuf_a;
232 struct pl011_dmabuf dbuf_b;
233 dma_cookie_t cookie;
234 bool running;
235 struct timer_list timer;
236 unsigned int last_residue;
237 unsigned long last_jiffies;
238 bool auto_poll_rate;
239 unsigned int poll_rate;
240 unsigned int poll_timeout;
241};
242
243struct pl011_dmatx_data {
244 struct dma_chan *chan;
245 dma_addr_t dma;
246 size_t len;
247 char *buf;
248 bool queued;
249};
250
251/*
252 * We wrap our port structure around the generic uart_port.
253 */
254struct uart_amba_port {
255 struct uart_port port;
256 const u16 *reg_offset;
257 struct clk *clk;
258 const struct vendor_data *vendor;
259 unsigned int dmacr; /* dma control reg */
260 unsigned int im; /* interrupt mask */
261 unsigned int old_status;
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
264 char type[12];
265 bool rs485_tx_started;
266 unsigned int rs485_tx_drain_interval; /* usecs */
267#ifdef CONFIG_DMA_ENGINE
268 /* DMA stuff */
269 bool using_tx_dma;
270 bool using_rx_dma;
271 struct pl011_dmarx_data dmarx;
272 struct pl011_dmatx_data dmatx;
273 bool dma_probed;
274#endif
275};
276
277static unsigned int pl011_tx_empty(struct uart_port *port);
278
279static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
280 unsigned int reg)
281{
282 return uap->reg_offset[reg];
283}
284
285static unsigned int pl011_read(const struct uart_amba_port *uap,
286 unsigned int reg)
287{
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
289
290 return (uap->port.iotype == UPIO_MEM32) ?
291 readl_relaxed(addr) : readw_relaxed(addr);
292}
293
294static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
295 unsigned int reg)
296{
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
298
299 if (uap->port.iotype == UPIO_MEM32)
300 writel_relaxed(val, addr);
301 else
302 writew_relaxed(val, addr);
303}
304
305/*
306 * Reads up to 256 characters from the FIFO or until it's empty and
307 * inserts them into the TTY layer. Returns the number of characters
308 * read from the FIFO.
309 */
310static int pl011_fifo_to_tty(struct uart_amba_port *uap)
311{
312 unsigned int ch, fifotaken;
313 int sysrq;
314 u16 status;
315 u8 flag;
316
317 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
318 status = pl011_read(uap, REG_FR);
319 if (status & UART01x_FR_RXFE)
320 break;
321
322 /* Take chars from the FIFO and update status */
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
324 flag = TTY_NORMAL;
325 uap->port.icount.rx++;
326
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
332 continue;
333 } else if (ch & UART011_DR_PE) {
334 uap->port.icount.parity++;
335 } else if (ch & UART011_DR_FE) {
336 uap->port.icount.frame++;
337 }
338 if (ch & UART011_DR_OE)
339 uap->port.icount.overrun++;
340
341 ch &= uap->port.read_status_mask;
342
343 if (ch & UART011_DR_BE)
344 flag = TTY_BREAK;
345 else if (ch & UART011_DR_PE)
346 flag = TTY_PARITY;
347 else if (ch & UART011_DR_FE)
348 flag = TTY_FRAME;
349 }
350
351 uart_port_unlock(&uap->port);
352 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
353 uart_port_lock(&uap->port);
354
355 if (!sysrq)
356 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
357 }
358
359 return fifotaken;
360}
361
362/*
363 * All the DMA operation mode stuff goes inside this ifdef.
364 * This assumes that you have a generic DMA device interface,
365 * no custom DMA interfaces are supported.
366 */
367#ifdef CONFIG_DMA_ENGINE
368
369#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
370
371static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db,
372 enum dma_data_direction dir)
373{
374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
375 &db->dma, GFP_KERNEL);
376 if (!db->buf)
377 return -ENOMEM;
378 db->len = PL011_DMA_BUFFER_SIZE;
379
380 return 0;
381}
382
383static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db,
384 enum dma_data_direction dir)
385{
386 if (db->buf) {
387 dma_free_coherent(chan->device->dev,
388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma);
389 }
390}
391
392static void pl011_dma_probe(struct uart_amba_port *uap)
393{
394 /* DMA is the sole user of the platform data right now */
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
396 struct device *dev = uap->port.dev;
397 struct dma_slave_config tx_conf = {
398 .dst_addr = uap->port.mapbase +
399 pl011_reg_to_offset(uap, REG_DR),
400 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
401 .direction = DMA_MEM_TO_DEV,
402 .dst_maxburst = uap->fifosize >> 1,
403 .device_fc = false,
404 };
405 struct dma_chan *chan;
406 dma_cap_mask_t mask;
407
408 uap->dma_probed = true;
409 chan = dma_request_chan(dev, "tx");
410 if (IS_ERR(chan)) {
411 if (PTR_ERR(chan) == -EPROBE_DEFER) {
412 uap->dma_probed = false;
413 return;
414 }
415
416 /* We need platform data */
417 if (!plat || !plat->dma_filter) {
418 dev_dbg(uap->port.dev, "no DMA platform data\n");
419 return;
420 }
421
422 /* Try to acquire a generic DMA engine slave TX channel */
423 dma_cap_zero(mask);
424 dma_cap_set(DMA_SLAVE, mask);
425
426 chan = dma_request_channel(mask, plat->dma_filter,
427 plat->dma_tx_param);
428 if (!chan) {
429 dev_err(uap->port.dev, "no TX DMA channel!\n");
430 return;
431 }
432 }
433
434 dmaengine_slave_config(chan, &tx_conf);
435 uap->dmatx.chan = chan;
436
437 dev_info(uap->port.dev, "DMA channel TX %s\n",
438 dma_chan_name(uap->dmatx.chan));
439
440 /* Optionally make use of an RX channel as well */
441 chan = dma_request_chan(dev, "rx");
442
443 if (IS_ERR(chan) && plat && plat->dma_rx_param) {
444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
445
446 if (!chan) {
447 dev_err(uap->port.dev, "no RX DMA channel!\n");
448 return;
449 }
450 }
451
452 if (!IS_ERR(chan)) {
453 struct dma_slave_config rx_conf = {
454 .src_addr = uap->port.mapbase +
455 pl011_reg_to_offset(uap, REG_DR),
456 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
457 .direction = DMA_DEV_TO_MEM,
458 .src_maxburst = uap->fifosize >> 2,
459 .device_fc = false,
460 };
461 struct dma_slave_caps caps;
462
463 /*
464 * Some DMA controllers provide information on their capabilities.
465 * If the controller does, check for suitable residue processing
466 * otherwise assime all is well.
467 */
468 if (dma_get_slave_caps(chan, &caps) == 0) {
469 if (caps.residue_granularity ==
470 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
471 dma_release_channel(chan);
472 dev_info(uap->port.dev,
473 "RX DMA disabled - no residue processing\n");
474 return;
475 }
476 }
477 dmaengine_slave_config(chan, &rx_conf);
478 uap->dmarx.chan = chan;
479
480 uap->dmarx.auto_poll_rate = false;
481 if (plat && plat->dma_rx_poll_enable) {
482 /* Set poll rate if specified. */
483 if (plat->dma_rx_poll_rate) {
484 uap->dmarx.auto_poll_rate = false;
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
486 } else {
487 /*
488 * 100 ms defaults to poll rate if not
489 * specified. This will be adjusted with
490 * the baud rate at set_termios.
491 */
492 uap->dmarx.auto_poll_rate = true;
493 uap->dmarx.poll_rate = 100;
494 }
495 /* 3 secs defaults poll_timeout if not specified. */
496 if (plat->dma_rx_poll_timeout)
497 uap->dmarx.poll_timeout =
498 plat->dma_rx_poll_timeout;
499 else
500 uap->dmarx.poll_timeout = 3000;
501 } else if (!plat && dev->of_node) {
502 uap->dmarx.auto_poll_rate =
503 of_property_read_bool(dev->of_node, "auto-poll");
504 if (uap->dmarx.auto_poll_rate) {
505 u32 x;
506
507 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0)
508 uap->dmarx.poll_rate = x;
509 else
510 uap->dmarx.poll_rate = 100;
511 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0)
512 uap->dmarx.poll_timeout = x;
513 else
514 uap->dmarx.poll_timeout = 3000;
515 }
516 }
517 dev_info(uap->port.dev, "DMA channel RX %s\n",
518 dma_chan_name(uap->dmarx.chan));
519 }
520}
521
522static void pl011_dma_remove(struct uart_amba_port *uap)
523{
524 if (uap->dmatx.chan)
525 dma_release_channel(uap->dmatx.chan);
526 if (uap->dmarx.chan)
527 dma_release_channel(uap->dmarx.chan);
528}
529
530/* Forward declare these for the refill routine */
531static int pl011_dma_tx_refill(struct uart_amba_port *uap);
532static void pl011_start_tx_pio(struct uart_amba_port *uap);
533
534/*
535 * The current DMA TX buffer has been sent.
536 * Try to queue up another DMA buffer.
537 */
538static void pl011_dma_tx_callback(void *data)
539{
540 struct uart_amba_port *uap = data;
541 struct pl011_dmatx_data *dmatx = &uap->dmatx;
542 unsigned long flags;
543 u16 dmacr;
544
545 uart_port_lock_irqsave(&uap->port, &flags);
546 if (uap->dmatx.queued)
547 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
548 dmatx->len, DMA_TO_DEVICE);
549
550 dmacr = uap->dmacr;
551 uap->dmacr = dmacr & ~UART011_TXDMAE;
552 pl011_write(uap->dmacr, uap, REG_DMACR);
553
554 /*
555 * If TX DMA was disabled, it means that we've stopped the DMA for
556 * some reason (eg, XOFF received, or we want to send an X-char.)
557 *
558 * Note: we need to be careful here of a potential race between DMA
559 * and the rest of the driver - if the driver disables TX DMA while
560 * a TX buffer completing, we must update the tx queued status to
561 * get further refills (hence we check dmacr).
562 */
563 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
564 uart_circ_empty(&uap->port.state->xmit)) {
565 uap->dmatx.queued = false;
566 uart_port_unlock_irqrestore(&uap->port, flags);
567 return;
568 }
569
570 if (pl011_dma_tx_refill(uap) <= 0)
571 /*
572 * We didn't queue a DMA buffer for some reason, but we
573 * have data pending to be sent. Re-enable the TX IRQ.
574 */
575 pl011_start_tx_pio(uap);
576
577 uart_port_unlock_irqrestore(&uap->port, flags);
578}
579
580/*
581 * Try to refill the TX DMA buffer.
582 * Locking: called with port lock held and IRQs disabled.
583 * Returns:
584 * 1 if we queued up a TX DMA buffer.
585 * 0 if we didn't want to handle this by DMA
586 * <0 on error
587 */
588static int pl011_dma_tx_refill(struct uart_amba_port *uap)
589{
590 struct pl011_dmatx_data *dmatx = &uap->dmatx;
591 struct dma_chan *chan = dmatx->chan;
592 struct dma_device *dma_dev = chan->device;
593 struct dma_async_tx_descriptor *desc;
594 struct circ_buf *xmit = &uap->port.state->xmit;
595 unsigned int count;
596
597 /*
598 * Try to avoid the overhead involved in using DMA if the
599 * transaction fits in the first half of the FIFO, by using
600 * the standard interrupt handling. This ensures that we
601 * issue a uart_write_wakeup() at the appropriate time.
602 */
603 count = uart_circ_chars_pending(xmit);
604 if (count < (uap->fifosize >> 1)) {
605 uap->dmatx.queued = false;
606 return 0;
607 }
608
609 /*
610 * Bodge: don't send the last character by DMA, as this
611 * will prevent XON from notifying us to restart DMA.
612 */
613 count -= 1;
614
615 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
616 if (count > PL011_DMA_BUFFER_SIZE)
617 count = PL011_DMA_BUFFER_SIZE;
618
619 if (xmit->tail < xmit->head) {
620 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
621 } else {
622 size_t first = UART_XMIT_SIZE - xmit->tail;
623 size_t second;
624
625 if (first > count)
626 first = count;
627 second = count - first;
628
629 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
630 if (second)
631 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
632 }
633
634 dmatx->len = count;
635 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
636 DMA_TO_DEVICE);
637 if (dmatx->dma == DMA_MAPPING_ERROR) {
638 uap->dmatx.queued = false;
639 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
640 return -EBUSY;
641 }
642
643 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
644 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
645 if (!desc) {
646 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
647 uap->dmatx.queued = false;
648 /*
649 * If DMA cannot be used right now, we complete this
650 * transaction via IRQ and let the TTY layer retry.
651 */
652 dev_dbg(uap->port.dev, "TX DMA busy\n");
653 return -EBUSY;
654 }
655
656 /* Some data to go along to the callback */
657 desc->callback = pl011_dma_tx_callback;
658 desc->callback_param = uap;
659
660 /* All errors should happen at prepare time */
661 dmaengine_submit(desc);
662
663 /* Fire the DMA transaction */
664 dma_dev->device_issue_pending(chan);
665
666 uap->dmacr |= UART011_TXDMAE;
667 pl011_write(uap->dmacr, uap, REG_DMACR);
668 uap->dmatx.queued = true;
669
670 /*
671 * Now we know that DMA will fire, so advance the ring buffer
672 * with the stuff we just dispatched.
673 */
674 uart_xmit_advance(&uap->port, count);
675
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(&uap->port);
678
679 return 1;
680}
681
682/*
683 * We received a transmit interrupt without a pending X-char but with
684 * pending characters.
685 * Locking: called with port lock held and IRQs disabled.
686 * Returns:
687 * false if we want to use PIO to transmit
688 * true if we queued a DMA buffer
689 */
690static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
691{
692 if (!uap->using_tx_dma)
693 return false;
694
695 /*
696 * If we already have a TX buffer queued, but received a
697 * TX interrupt, it will be because we've just sent an X-char.
698 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
699 */
700 if (uap->dmatx.queued) {
701 uap->dmacr |= UART011_TXDMAE;
702 pl011_write(uap->dmacr, uap, REG_DMACR);
703 uap->im &= ~UART011_TXIM;
704 pl011_write(uap->im, uap, REG_IMSC);
705 return true;
706 }
707
708 /*
709 * We don't have a TX buffer queued, so try to queue one.
710 * If we successfully queued a buffer, mask the TX IRQ.
711 */
712 if (pl011_dma_tx_refill(uap) > 0) {
713 uap->im &= ~UART011_TXIM;
714 pl011_write(uap->im, uap, REG_IMSC);
715 return true;
716 }
717 return false;
718}
719
720/*
721 * Stop the DMA transmit (eg, due to received XOFF).
722 * Locking: called with port lock held and IRQs disabled.
723 */
724static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
725{
726 if (uap->dmatx.queued) {
727 uap->dmacr &= ~UART011_TXDMAE;
728 pl011_write(uap->dmacr, uap, REG_DMACR);
729 }
730}
731
732/*
733 * Try to start a DMA transmit, or in the case of an XON/OFF
734 * character queued for send, try to get that character out ASAP.
735 * Locking: called with port lock held and IRQs disabled.
736 * Returns:
737 * false if we want the TX IRQ to be enabled
738 * true if we have a buffer queued
739 */
740static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
741{
742 u16 dmacr;
743
744 if (!uap->using_tx_dma)
745 return false;
746
747 if (!uap->port.x_char) {
748 /* no X-char, try to push chars out in DMA mode */
749 bool ret = true;
750
751 if (!uap->dmatx.queued) {
752 if (pl011_dma_tx_refill(uap) > 0) {
753 uap->im &= ~UART011_TXIM;
754 pl011_write(uap->im, uap, REG_IMSC);
755 } else {
756 ret = false;
757 }
758 } else if (!(uap->dmacr & UART011_TXDMAE)) {
759 uap->dmacr |= UART011_TXDMAE;
760 pl011_write(uap->dmacr, uap, REG_DMACR);
761 }
762 return ret;
763 }
764
765 /*
766 * We have an X-char to send. Disable DMA to prevent it loading
767 * the TX fifo, and then see if we can stuff it into the FIFO.
768 */
769 dmacr = uap->dmacr;
770 uap->dmacr &= ~UART011_TXDMAE;
771 pl011_write(uap->dmacr, uap, REG_DMACR);
772
773 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
774 /*
775 * No space in the FIFO, so enable the transmit interrupt
776 * so we know when there is space. Note that once we've
777 * loaded the character, we should just re-enable DMA.
778 */
779 return false;
780 }
781
782 pl011_write(uap->port.x_char, uap, REG_DR);
783 uap->port.icount.tx++;
784 uap->port.x_char = 0;
785
786 /* Success - restore the DMA state */
787 uap->dmacr = dmacr;
788 pl011_write(dmacr, uap, REG_DMACR);
789
790 return true;
791}
792
793/*
794 * Flush the transmit buffer.
795 * Locking: called with port lock held and IRQs disabled.
796 */
797static void pl011_dma_flush_buffer(struct uart_port *port)
798__releases(&uap->port.lock)
799__acquires(&uap->port.lock)
800{
801 struct uart_amba_port *uap =
802 container_of(port, struct uart_amba_port, port);
803
804 if (!uap->using_tx_dma)
805 return;
806
807 dmaengine_terminate_async(uap->dmatx.chan);
808
809 if (uap->dmatx.queued) {
810 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
811 uap->dmatx.len, DMA_TO_DEVICE);
812 uap->dmatx.queued = false;
813 uap->dmacr &= ~UART011_TXDMAE;
814 pl011_write(uap->dmacr, uap, REG_DMACR);
815 }
816}
817
818static void pl011_dma_rx_callback(void *data);
819
820static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
821{
822 struct dma_chan *rxchan = uap->dmarx.chan;
823 struct pl011_dmarx_data *dmarx = &uap->dmarx;
824 struct dma_async_tx_descriptor *desc;
825 struct pl011_dmabuf *dbuf;
826
827 if (!rxchan)
828 return -EIO;
829
830 /* Start the RX DMA job */
831 dbuf = uap->dmarx.use_buf_b ?
832 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
833 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len,
834 DMA_DEV_TO_MEM,
835 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
836 /*
837 * If the DMA engine is busy and cannot prepare a
838 * channel, no big deal, the driver will fall back
839 * to interrupt mode as a result of this error code.
840 */
841 if (!desc) {
842 uap->dmarx.running = false;
843 dmaengine_terminate_all(rxchan);
844 return -EBUSY;
845 }
846
847 /* Some data to go along to the callback */
848 desc->callback = pl011_dma_rx_callback;
849 desc->callback_param = uap;
850 dmarx->cookie = dmaengine_submit(desc);
851 dma_async_issue_pending(rxchan);
852
853 uap->dmacr |= UART011_RXDMAE;
854 pl011_write(uap->dmacr, uap, REG_DMACR);
855 uap->dmarx.running = true;
856
857 uap->im &= ~UART011_RXIM;
858 pl011_write(uap->im, uap, REG_IMSC);
859
860 return 0;
861}
862
863/*
864 * This is called when either the DMA job is complete, or
865 * the FIFO timeout interrupt occurred. This must be called
866 * with the port spinlock uap->port.lock held.
867 */
868static void pl011_dma_rx_chars(struct uart_amba_port *uap,
869 u32 pending, bool use_buf_b,
870 bool readfifo)
871{
872 struct tty_port *port = &uap->port.state->port;
873 struct pl011_dmabuf *dbuf = use_buf_b ?
874 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
875 int dma_count = 0;
876 u32 fifotaken = 0; /* only used for vdbg() */
877
878 struct pl011_dmarx_data *dmarx = &uap->dmarx;
879 int dmataken = 0;
880
881 if (uap->dmarx.poll_rate) {
882 /* The data can be taken by polling */
883 dmataken = dbuf->len - dmarx->last_residue;
884 /* Recalculate the pending size */
885 if (pending >= dmataken)
886 pending -= dmataken;
887 }
888
889 /* Pick the remain data from the DMA */
890 if (pending) {
891 /*
892 * First take all chars in the DMA pipe, then look in the FIFO.
893 * Note that tty_insert_flip_buf() tries to take as many chars
894 * as it can.
895 */
896 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending);
897
898 uap->port.icount.rx += dma_count;
899 if (dma_count < pending)
900 dev_warn(uap->port.dev,
901 "couldn't insert all characters (TTY is full?)\n");
902 }
903
904 /* Reset the last_residue for Rx DMA poll */
905 if (uap->dmarx.poll_rate)
906 dmarx->last_residue = dbuf->len;
907
908 /*
909 * Only continue with trying to read the FIFO if all DMA chars have
910 * been taken first.
911 */
912 if (dma_count == pending && readfifo) {
913 /* Clear any error flags */
914 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
915 UART011_FEIS, uap, REG_ICR);
916
917 /*
918 * If we read all the DMA'd characters, and we had an
919 * incomplete buffer, that could be due to an rx error, or
920 * maybe we just timed out. Read any pending chars and check
921 * the error status.
922 *
923 * Error conditions will only occur in the FIFO, these will
924 * trigger an immediate interrupt and stop the DMA job, so we
925 * will always find the error in the FIFO, never in the DMA
926 * buffer.
927 */
928 fifotaken = pl011_fifo_to_tty(uap);
929 }
930
931 dev_vdbg(uap->port.dev,
932 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
933 dma_count, fifotaken);
934 tty_flip_buffer_push(port);
935}
936
937static void pl011_dma_rx_irq(struct uart_amba_port *uap)
938{
939 struct pl011_dmarx_data *dmarx = &uap->dmarx;
940 struct dma_chan *rxchan = dmarx->chan;
941 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
942 &dmarx->dbuf_b : &dmarx->dbuf_a;
943 size_t pending;
944 struct dma_tx_state state;
945 enum dma_status dmastat;
946
947 /*
948 * Pause the transfer so we can trust the current counter,
949 * do this before we pause the PL011 block, else we may
950 * overflow the FIFO.
951 */
952 if (dmaengine_pause(rxchan))
953 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
954 dmastat = rxchan->device->device_tx_status(rxchan,
955 dmarx->cookie, &state);
956 if (dmastat != DMA_PAUSED)
957 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
958
959 /* Disable RX DMA - incoming data will wait in the FIFO */
960 uap->dmacr &= ~UART011_RXDMAE;
961 pl011_write(uap->dmacr, uap, REG_DMACR);
962 uap->dmarx.running = false;
963
964 pending = dbuf->len - state.residue;
965 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
966 /* Then we terminate the transfer - we now know our residue */
967 dmaengine_terminate_all(rxchan);
968
969 /*
970 * This will take the chars we have so far and insert
971 * into the framework.
972 */
973 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
974
975 /* Switch buffer & re-trigger DMA job */
976 dmarx->use_buf_b = !dmarx->use_buf_b;
977 if (pl011_dma_rx_trigger_dma(uap)) {
978 dev_dbg(uap->port.dev,
979 "could not retrigger RX DMA job fall back to interrupt mode\n");
980 uap->im |= UART011_RXIM;
981 pl011_write(uap->im, uap, REG_IMSC);
982 }
983}
984
985static void pl011_dma_rx_callback(void *data)
986{
987 struct uart_amba_port *uap = data;
988 struct pl011_dmarx_data *dmarx = &uap->dmarx;
989 struct dma_chan *rxchan = dmarx->chan;
990 bool lastbuf = dmarx->use_buf_b;
991 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
992 &dmarx->dbuf_b : &dmarx->dbuf_a;
993 size_t pending;
994 struct dma_tx_state state;
995 int ret;
996
997 /*
998 * This completion interrupt occurs typically when the
999 * RX buffer is totally stuffed but no timeout has yet
1000 * occurred. When that happens, we just want the RX
1001 * routine to flush out the secondary DMA buffer while
1002 * we immediately trigger the next DMA job.
1003 */
1004 uart_port_lock_irq(&uap->port);
1005 /*
1006 * Rx data can be taken by the UART interrupts during
1007 * the DMA irq handler. So we check the residue here.
1008 */
1009 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1010 pending = dbuf->len - state.residue;
1011 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1012 /* Then we terminate the transfer - we now know our residue */
1013 dmaengine_terminate_all(rxchan);
1014
1015 uap->dmarx.running = false;
1016 dmarx->use_buf_b = !lastbuf;
1017 ret = pl011_dma_rx_trigger_dma(uap);
1018
1019 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1020 uart_port_unlock_irq(&uap->port);
1021 /*
1022 * Do this check after we picked the DMA chars so we don't
1023 * get some IRQ immediately from RX.
1024 */
1025 if (ret) {
1026 dev_dbg(uap->port.dev,
1027 "could not retrigger RX DMA job fall back to interrupt mode\n");
1028 uap->im |= UART011_RXIM;
1029 pl011_write(uap->im, uap, REG_IMSC);
1030 }
1031}
1032
1033/*
1034 * Stop accepting received characters, when we're shutting down or
1035 * suspending this port.
1036 * Locking: called with port lock held and IRQs disabled.
1037 */
1038static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1039{
1040 if (!uap->using_rx_dma)
1041 return;
1042
1043 /* FIXME. Just disable the DMA enable */
1044 uap->dmacr &= ~UART011_RXDMAE;
1045 pl011_write(uap->dmacr, uap, REG_DMACR);
1046}
1047
1048/*
1049 * Timer handler for Rx DMA polling.
1050 * Every polling, It checks the residue in the dma buffer and transfer
1051 * data to the tty. Also, last_residue is updated for the next polling.
1052 */
1053static void pl011_dma_rx_poll(struct timer_list *t)
1054{
1055 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1056 struct tty_port *port = &uap->port.state->port;
1057 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1058 struct dma_chan *rxchan = uap->dmarx.chan;
1059 unsigned long flags;
1060 unsigned int dmataken = 0;
1061 unsigned int size = 0;
1062 struct pl011_dmabuf *dbuf;
1063 int dma_count;
1064 struct dma_tx_state state;
1065
1066 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1067 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1068 if (likely(state.residue < dmarx->last_residue)) {
1069 dmataken = dbuf->len - dmarx->last_residue;
1070 size = dmarx->last_residue - state.residue;
1071 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,
1072 size);
1073 if (dma_count == size)
1074 dmarx->last_residue = state.residue;
1075 dmarx->last_jiffies = jiffies;
1076 }
1077 tty_flip_buffer_push(port);
1078
1079 /*
1080 * If no data is received in poll_timeout, the driver will fall back
1081 * to interrupt mode. We will retrigger DMA at the first interrupt.
1082 */
1083 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1084 > uap->dmarx.poll_timeout) {
1085 uart_port_lock_irqsave(&uap->port, &flags);
1086 pl011_dma_rx_stop(uap);
1087 uap->im |= UART011_RXIM;
1088 pl011_write(uap->im, uap, REG_IMSC);
1089 uart_port_unlock_irqrestore(&uap->port, flags);
1090
1091 uap->dmarx.running = false;
1092 dmaengine_terminate_all(rxchan);
1093 del_timer(&uap->dmarx.timer);
1094 } else {
1095 mod_timer(&uap->dmarx.timer,
1096 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1097 }
1098}
1099
1100static void pl011_dma_startup(struct uart_amba_port *uap)
1101{
1102 int ret;
1103
1104 if (!uap->dma_probed)
1105 pl011_dma_probe(uap);
1106
1107 if (!uap->dmatx.chan)
1108 return;
1109
1110 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1111 if (!uap->dmatx.buf) {
1112 uap->port.fifosize = uap->fifosize;
1113 return;
1114 }
1115
1116 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1117
1118 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1119 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1120 uap->using_tx_dma = true;
1121
1122 if (!uap->dmarx.chan)
1123 goto skip_rx;
1124
1125 /* Allocate and map DMA RX buffers */
1126 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1127 DMA_FROM_DEVICE);
1128 if (ret) {
1129 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1130 "RX buffer A", ret);
1131 goto skip_rx;
1132 }
1133
1134 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1135 DMA_FROM_DEVICE);
1136 if (ret) {
1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1138 "RX buffer B", ret);
1139 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1140 DMA_FROM_DEVICE);
1141 goto skip_rx;
1142 }
1143
1144 uap->using_rx_dma = true;
1145
1146skip_rx:
1147 /* Turn on DMA error (RX/TX will be enabled on demand) */
1148 uap->dmacr |= UART011_DMAONERR;
1149 pl011_write(uap->dmacr, uap, REG_DMACR);
1150
1151 /*
1152 * ST Micro variants has some specific dma burst threshold
1153 * compensation. Set this to 16 bytes, so burst will only
1154 * be issued above/below 16 bytes.
1155 */
1156 if (uap->vendor->dma_threshold)
1157 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1158 uap, REG_ST_DMAWM);
1159
1160 if (uap->using_rx_dma) {
1161 if (pl011_dma_rx_trigger_dma(uap))
1162 dev_dbg(uap->port.dev,
1163 "could not trigger initial RX DMA job, fall back to interrupt mode\n");
1164 if (uap->dmarx.poll_rate) {
1165 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1166 mod_timer(&uap->dmarx.timer,
1167 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1168 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1169 uap->dmarx.last_jiffies = jiffies;
1170 }
1171 }
1172}
1173
1174static void pl011_dma_shutdown(struct uart_amba_port *uap)
1175{
1176 if (!(uap->using_tx_dma || uap->using_rx_dma))
1177 return;
1178
1179 /* Disable RX and TX DMA */
1180 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1181 cpu_relax();
1182
1183 uart_port_lock_irq(&uap->port);
1184 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1185 pl011_write(uap->dmacr, uap, REG_DMACR);
1186 uart_port_unlock_irq(&uap->port);
1187
1188 if (uap->using_tx_dma) {
1189 /* In theory, this should already be done by pl011_dma_flush_buffer */
1190 dmaengine_terminate_all(uap->dmatx.chan);
1191 if (uap->dmatx.queued) {
1192 dma_unmap_single(uap->dmatx.chan->device->dev,
1193 uap->dmatx.dma, uap->dmatx.len,
1194 DMA_TO_DEVICE);
1195 uap->dmatx.queued = false;
1196 }
1197
1198 kfree(uap->dmatx.buf);
1199 uap->using_tx_dma = false;
1200 }
1201
1202 if (uap->using_rx_dma) {
1203 dmaengine_terminate_all(uap->dmarx.chan);
1204 /* Clean up the RX DMA */
1205 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1206 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1207 if (uap->dmarx.poll_rate)
1208 del_timer_sync(&uap->dmarx.timer);
1209 uap->using_rx_dma = false;
1210 }
1211}
1212
1213static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1214{
1215 return uap->using_rx_dma;
1216}
1217
1218static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1219{
1220 return uap->using_rx_dma && uap->dmarx.running;
1221}
1222
1223#else
1224/* Blank functions if the DMA engine is not available */
1225static inline void pl011_dma_remove(struct uart_amba_port *uap)
1226{
1227}
1228
1229static inline void pl011_dma_startup(struct uart_amba_port *uap)
1230{
1231}
1232
1233static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1234{
1235}
1236
1237static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1238{
1239 return false;
1240}
1241
1242static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1243{
1244}
1245
1246static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1247{
1248 return false;
1249}
1250
1251static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1256{
1257}
1258
1259static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1260{
1261 return -EIO;
1262}
1263
1264static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1265{
1266 return false;
1267}
1268
1269static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1270{
1271 return false;
1272}
1273
1274#define pl011_dma_flush_buffer NULL
1275#endif
1276
1277static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1278{
1279 /*
1280 * To be on the safe side only time out after twice as many iterations
1281 * as fifo size.
1282 */
1283 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
1284 struct uart_port *port = &uap->port;
1285 int i = 0;
1286 u32 cr;
1287
1288 /* Wait until hardware tx queue is empty */
1289 while (!pl011_tx_empty(port)) {
1290 if (i > MAX_TX_DRAIN_ITERS) {
1291 dev_warn(port->dev,
1292 "timeout while draining hardware tx queue\n");
1293 break;
1294 }
1295
1296 udelay(uap->rs485_tx_drain_interval);
1297 i++;
1298 }
1299
1300 if (port->rs485.delay_rts_after_send)
1301 mdelay(port->rs485.delay_rts_after_send);
1302
1303 cr = pl011_read(uap, REG_CR);
1304
1305 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1306 cr &= ~UART011_CR_RTS;
1307 else
1308 cr |= UART011_CR_RTS;
1309
1310 /* Disable the transmitter and reenable the transceiver */
1311 cr &= ~UART011_CR_TXE;
1312 cr |= UART011_CR_RXE;
1313 pl011_write(cr, uap, REG_CR);
1314
1315 uap->rs485_tx_started = false;
1316}
1317
1318static void pl011_stop_tx(struct uart_port *port)
1319{
1320 struct uart_amba_port *uap =
1321 container_of(port, struct uart_amba_port, port);
1322
1323 uap->im &= ~UART011_TXIM;
1324 pl011_write(uap->im, uap, REG_IMSC);
1325 pl011_dma_tx_stop(uap);
1326
1327 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1328 pl011_rs485_tx_stop(uap);
1329}
1330
1331static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1332
1333/* Start TX with programmed I/O only (no DMA) */
1334static void pl011_start_tx_pio(struct uart_amba_port *uap)
1335{
1336 if (pl011_tx_chars(uap, false)) {
1337 uap->im |= UART011_TXIM;
1338 pl011_write(uap->im, uap, REG_IMSC);
1339 }
1340}
1341
1342static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1343{
1344 struct uart_port *port = &uap->port;
1345 u32 cr;
1346
1347 /* Enable transmitter */
1348 cr = pl011_read(uap, REG_CR);
1349 cr |= UART011_CR_TXE;
1350
1351 /* Disable receiver if half-duplex */
1352 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1353 cr &= ~UART011_CR_RXE;
1354
1355 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1356 cr &= ~UART011_CR_RTS;
1357 else
1358 cr |= UART011_CR_RTS;
1359
1360 pl011_write(cr, uap, REG_CR);
1361
1362 if (port->rs485.delay_rts_before_send)
1363 mdelay(port->rs485.delay_rts_before_send);
1364
1365 uap->rs485_tx_started = true;
1366}
1367
1368static void pl011_start_tx(struct uart_port *port)
1369{
1370 struct uart_amba_port *uap =
1371 container_of(port, struct uart_amba_port, port);
1372
1373 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1374 !uap->rs485_tx_started)
1375 pl011_rs485_tx_start(uap);
1376
1377 if (!pl011_dma_tx_start(uap))
1378 pl011_start_tx_pio(uap);
1379}
1380
1381static void pl011_stop_rx(struct uart_port *port)
1382{
1383 struct uart_amba_port *uap =
1384 container_of(port, struct uart_amba_port, port);
1385
1386 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM |
1387 UART011_PEIM | UART011_BEIM | UART011_OEIM);
1388 pl011_write(uap->im, uap, REG_IMSC);
1389
1390 pl011_dma_rx_stop(uap);
1391}
1392
1393static void pl011_throttle_rx(struct uart_port *port)
1394{
1395 unsigned long flags;
1396
1397 uart_port_lock_irqsave(port, &flags);
1398 pl011_stop_rx(port);
1399 uart_port_unlock_irqrestore(port, flags);
1400}
1401
1402static void pl011_enable_ms(struct uart_port *port)
1403{
1404 struct uart_amba_port *uap =
1405 container_of(port, struct uart_amba_port, port);
1406
1407 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM;
1408 pl011_write(uap->im, uap, REG_IMSC);
1409}
1410
1411static void pl011_rx_chars(struct uart_amba_port *uap)
1412__releases(&uap->port.lock)
1413__acquires(&uap->port.lock)
1414{
1415 pl011_fifo_to_tty(uap);
1416
1417 uart_port_unlock(&uap->port);
1418 tty_flip_buffer_push(&uap->port.state->port);
1419 /*
1420 * If we were temporarily out of DMA mode for a while,
1421 * attempt to switch back to DMA mode again.
1422 */
1423 if (pl011_dma_rx_available(uap)) {
1424 if (pl011_dma_rx_trigger_dma(uap)) {
1425 dev_dbg(uap->port.dev,
1426 "could not trigger RX DMA job fall back to interrupt mode again\n");
1427 uap->im |= UART011_RXIM;
1428 pl011_write(uap->im, uap, REG_IMSC);
1429 } else {
1430#ifdef CONFIG_DMA_ENGINE
1431 /* Start Rx DMA poll */
1432 if (uap->dmarx.poll_rate) {
1433 uap->dmarx.last_jiffies = jiffies;
1434 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1435 mod_timer(&uap->dmarx.timer,
1436 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1437 }
1438#endif
1439 }
1440 }
1441 uart_port_lock(&uap->port);
1442}
1443
1444static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1445 bool from_irq)
1446{
1447 if (unlikely(!from_irq) &&
1448 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1449 return false; /* unable to transmit character */
1450
1451 pl011_write(c, uap, REG_DR);
1452 uap->port.icount.tx++;
1453
1454 return true;
1455}
1456
1457/* Returns true if tx interrupts have to be (kept) enabled */
1458static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1459{
1460 struct circ_buf *xmit = &uap->port.state->xmit;
1461 int count = uap->fifosize >> 1;
1462
1463 if (uap->port.x_char) {
1464 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1465 return true;
1466 uap->port.x_char = 0;
1467 --count;
1468 }
1469 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1470 pl011_stop_tx(&uap->port);
1471 return false;
1472 }
1473
1474 /* If we are using DMA mode, try to send some characters. */
1475 if (pl011_dma_tx_irq(uap))
1476 return true;
1477
1478 do {
1479 if (likely(from_irq) && count-- == 0)
1480 break;
1481
1482 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1483 break;
1484
1485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486 } while (!uart_circ_empty(xmit));
1487
1488 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1489 uart_write_wakeup(&uap->port);
1490
1491 if (uart_circ_empty(xmit)) {
1492 pl011_stop_tx(&uap->port);
1493 return false;
1494 }
1495 return true;
1496}
1497
1498static void pl011_modem_status(struct uart_amba_port *uap)
1499{
1500 unsigned int status, delta;
1501
1502 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1503
1504 delta = status ^ uap->old_status;
1505 uap->old_status = status;
1506
1507 if (!delta)
1508 return;
1509
1510 if (delta & UART01x_FR_DCD)
1511 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1512
1513 if (delta & uap->vendor->fr_dsr)
1514 uap->port.icount.dsr++;
1515
1516 if (delta & uap->vendor->fr_cts)
1517 uart_handle_cts_change(&uap->port,
1518 status & uap->vendor->fr_cts);
1519
1520 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1521}
1522
1523static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1524{
1525 if (!uap->vendor->cts_event_workaround)
1526 return;
1527
1528 /* workaround to make sure that all bits are unlocked.. */
1529 pl011_write(0x00, uap, REG_ICR);
1530
1531 /*
1532 * WA: introduce 26ns(1 uart clk) delay before W1C;
1533 * single apb access will incur 2 pclk(133.12Mhz) delay,
1534 * so add 2 dummy reads
1535 */
1536 pl011_read(uap, REG_ICR);
1537 pl011_read(uap, REG_ICR);
1538}
1539
1540static irqreturn_t pl011_int(int irq, void *dev_id)
1541{
1542 struct uart_amba_port *uap = dev_id;
1543 unsigned long flags;
1544 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1545 int handled = 0;
1546
1547 uart_port_lock_irqsave(&uap->port, &flags);
1548 status = pl011_read(uap, REG_RIS) & uap->im;
1549 if (status) {
1550 do {
1551 check_apply_cts_event_workaround(uap);
1552
1553 pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS),
1554 uap, REG_ICR);
1555
1556 if (status & (UART011_RTIS | UART011_RXIS)) {
1557 if (pl011_dma_rx_running(uap))
1558 pl011_dma_rx_irq(uap);
1559 else
1560 pl011_rx_chars(uap);
1561 }
1562 if (status & (UART011_DSRMIS | UART011_DCDMIS |
1563 UART011_CTSMIS | UART011_RIMIS))
1564 pl011_modem_status(uap);
1565 if (status & UART011_TXIS)
1566 pl011_tx_chars(uap, true);
1567
1568 if (pass_counter-- == 0)
1569 break;
1570
1571 status = pl011_read(uap, REG_RIS) & uap->im;
1572 } while (status != 0);
1573 handled = 1;
1574 }
1575
1576 uart_port_unlock_irqrestore(&uap->port, flags);
1577
1578 return IRQ_RETVAL(handled);
1579}
1580
1581static unsigned int pl011_tx_empty(struct uart_port *port)
1582{
1583 struct uart_amba_port *uap =
1584 container_of(port, struct uart_amba_port, port);
1585
1586 /* Allow feature register bits to be inverted to work around errata */
1587 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1588
1589 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1590 0 : TIOCSER_TEMT;
1591}
1592
1593static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask)
1594{
1595 if (cond)
1596 *ptr |= mask;
1597}
1598
1599static unsigned int pl011_get_mctrl(struct uart_port *port)
1600{
1601 struct uart_amba_port *uap =
1602 container_of(port, struct uart_amba_port, port);
1603 unsigned int result = 0;
1604 unsigned int status = pl011_read(uap, REG_FR);
1605
1606 pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR);
1607 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR);
1608 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS);
1609 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG);
1610
1611 return result;
1612}
1613
1614static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask)
1615{
1616 if (cond)
1617 *ptr |= mask;
1618 else
1619 *ptr &= ~mask;
1620}
1621
1622static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1623{
1624 struct uart_amba_port *uap =
1625 container_of(port, struct uart_amba_port, port);
1626 unsigned int cr;
1627
1628 cr = pl011_read(uap, REG_CR);
1629
1630 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS);
1631 pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR);
1632 pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1);
1633 pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2);
1634 pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE);
1635
1636 if (port->status & UPSTAT_AUTORTS) {
1637 /* We need to disable auto-RTS if we want to turn RTS off */
1638 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN);
1639 }
1640
1641 pl011_write(cr, uap, REG_CR);
1642}
1643
1644static void pl011_break_ctl(struct uart_port *port, int break_state)
1645{
1646 struct uart_amba_port *uap =
1647 container_of(port, struct uart_amba_port, port);
1648 unsigned long flags;
1649 unsigned int lcr_h;
1650
1651 uart_port_lock_irqsave(&uap->port, &flags);
1652 lcr_h = pl011_read(uap, REG_LCRH_TX);
1653 if (break_state == -1)
1654 lcr_h |= UART01x_LCRH_BRK;
1655 else
1656 lcr_h &= ~UART01x_LCRH_BRK;
1657 pl011_write(lcr_h, uap, REG_LCRH_TX);
1658 uart_port_unlock_irqrestore(&uap->port, flags);
1659}
1660
1661#ifdef CONFIG_CONSOLE_POLL
1662
1663static void pl011_quiesce_irqs(struct uart_port *port)
1664{
1665 struct uart_amba_port *uap =
1666 container_of(port, struct uart_amba_port, port);
1667
1668 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1669 /*
1670 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1671 * we simply mask it. start_tx() will unmask it.
1672 *
1673 * Note we can race with start_tx(), and if the race happens, the
1674 * polling user might get another interrupt just after we clear it.
1675 * But it should be OK and can happen even w/o the race, e.g.
1676 * controller immediately got some new data and raised the IRQ.
1677 *
1678 * And whoever uses polling routines assumes that it manages the device
1679 * (including tx queue), so we're also fine with start_tx()'s caller
1680 * side.
1681 */
1682 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1683 REG_IMSC);
1684}
1685
1686static int pl011_get_poll_char(struct uart_port *port)
1687{
1688 struct uart_amba_port *uap =
1689 container_of(port, struct uart_amba_port, port);
1690 unsigned int status;
1691
1692 /*
1693 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1694 * debugger.
1695 */
1696 pl011_quiesce_irqs(port);
1697
1698 status = pl011_read(uap, REG_FR);
1699 if (status & UART01x_FR_RXFE)
1700 return NO_POLL_CHAR;
1701
1702 return pl011_read(uap, REG_DR);
1703}
1704
1705static void pl011_put_poll_char(struct uart_port *port, unsigned char ch)
1706{
1707 struct uart_amba_port *uap =
1708 container_of(port, struct uart_amba_port, port);
1709
1710 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1711 cpu_relax();
1712
1713 pl011_write(ch, uap, REG_DR);
1714}
1715
1716#endif /* CONFIG_CONSOLE_POLL */
1717
1718static int pl011_hwinit(struct uart_port *port)
1719{
1720 struct uart_amba_port *uap =
1721 container_of(port, struct uart_amba_port, port);
1722 int retval;
1723
1724 /* Optionaly enable pins to be muxed in and configured */
1725 pinctrl_pm_select_default_state(port->dev);
1726
1727 /*
1728 * Try to enable the clock producer.
1729 */
1730 retval = clk_prepare_enable(uap->clk);
1731 if (retval)
1732 return retval;
1733
1734 uap->port.uartclk = clk_get_rate(uap->clk);
1735
1736 /* Clear pending error and receive interrupts */
1737 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1738 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1739 uap, REG_ICR);
1740
1741 /*
1742 * Save interrupts enable mask, and enable RX interrupts in case if
1743 * the interrupt is used for NMI entry.
1744 */
1745 uap->im = pl011_read(uap, REG_IMSC);
1746 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1747
1748 if (dev_get_platdata(uap->port.dev)) {
1749 struct amba_pl011_data *plat;
1750
1751 plat = dev_get_platdata(uap->port.dev);
1752 if (plat->init)
1753 plat->init();
1754 }
1755 return 0;
1756}
1757
1758static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1759{
1760 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1761 pl011_reg_to_offset(uap, REG_LCRH_TX);
1762}
1763
1764static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1765{
1766 pl011_write(lcr_h, uap, REG_LCRH_RX);
1767 if (pl011_split_lcrh(uap)) {
1768 int i;
1769 /*
1770 * Wait 10 PCLKs before writing LCRH_TX register,
1771 * to get this delay write read only register 10 times
1772 */
1773 for (i = 0; i < 10; ++i)
1774 pl011_write(0xff, uap, REG_MIS);
1775 pl011_write(lcr_h, uap, REG_LCRH_TX);
1776 }
1777}
1778
1779static int pl011_allocate_irq(struct uart_amba_port *uap)
1780{
1781 pl011_write(uap->im, uap, REG_IMSC);
1782
1783 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1784}
1785
1786/*
1787 * Enable interrupts, only timeouts when using DMA
1788 * if initial RX DMA job failed, start in interrupt mode
1789 * as well.
1790 */
1791static void pl011_enable_interrupts(struct uart_amba_port *uap)
1792{
1793 unsigned long flags;
1794 unsigned int i;
1795
1796 uart_port_lock_irqsave(&uap->port, &flags);
1797
1798 /* Clear out any spuriously appearing RX interrupts */
1799 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1800
1801 /*
1802 * RXIS is asserted only when the RX FIFO transitions from below
1803 * to above the trigger threshold. If the RX FIFO is already
1804 * full to the threshold this can't happen and RXIS will now be
1805 * stuck off. Drain the RX FIFO explicitly to fix this:
1806 */
1807 for (i = 0; i < uap->fifosize * 2; ++i) {
1808 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1809 break;
1810
1811 pl011_read(uap, REG_DR);
1812 }
1813
1814 uap->im = UART011_RTIM;
1815 if (!pl011_dma_rx_running(uap))
1816 uap->im |= UART011_RXIM;
1817 pl011_write(uap->im, uap, REG_IMSC);
1818 uart_port_unlock_irqrestore(&uap->port, flags);
1819}
1820
1821static void pl011_unthrottle_rx(struct uart_port *port)
1822{
1823 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1824 unsigned long flags;
1825
1826 uart_port_lock_irqsave(&uap->port, &flags);
1827
1828 uap->im = UART011_RTIM;
1829 if (!pl011_dma_rx_running(uap))
1830 uap->im |= UART011_RXIM;
1831
1832 pl011_write(uap->im, uap, REG_IMSC);
1833
1834 uart_port_unlock_irqrestore(&uap->port, flags);
1835}
1836
1837static int pl011_startup(struct uart_port *port)
1838{
1839 struct uart_amba_port *uap =
1840 container_of(port, struct uart_amba_port, port);
1841 unsigned int cr;
1842 int retval;
1843
1844 retval = pl011_hwinit(port);
1845 if (retval)
1846 goto clk_dis;
1847
1848 retval = pl011_allocate_irq(uap);
1849 if (retval)
1850 goto clk_dis;
1851
1852 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1853
1854 uart_port_lock_irq(&uap->port);
1855
1856 cr = pl011_read(uap, REG_CR);
1857 cr &= UART011_CR_RTS | UART011_CR_DTR;
1858 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1859
1860 if (!(port->rs485.flags & SER_RS485_ENABLED))
1861 cr |= UART011_CR_TXE;
1862
1863 pl011_write(cr, uap, REG_CR);
1864
1865 uart_port_unlock_irq(&uap->port);
1866
1867 /*
1868 * initialise the old status of the modem signals
1869 */
1870 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1871
1872 /* Startup DMA */
1873 pl011_dma_startup(uap);
1874
1875 pl011_enable_interrupts(uap);
1876
1877 return 0;
1878
1879 clk_dis:
1880 clk_disable_unprepare(uap->clk);
1881 return retval;
1882}
1883
1884static int sbsa_uart_startup(struct uart_port *port)
1885{
1886 struct uart_amba_port *uap =
1887 container_of(port, struct uart_amba_port, port);
1888 int retval;
1889
1890 retval = pl011_hwinit(port);
1891 if (retval)
1892 return retval;
1893
1894 retval = pl011_allocate_irq(uap);
1895 if (retval)
1896 return retval;
1897
1898 /* The SBSA UART does not support any modem status lines. */
1899 uap->old_status = 0;
1900
1901 pl011_enable_interrupts(uap);
1902
1903 return 0;
1904}
1905
1906static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh)
1907{
1908 unsigned long val;
1909
1910 val = pl011_read(uap, lcrh);
1911 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1912 pl011_write(val, uap, lcrh);
1913}
1914
1915/*
1916 * disable the port. It should not disable RTS and DTR.
1917 * Also RTS and DTR state should be preserved to restore
1918 * it during startup().
1919 */
1920static void pl011_disable_uart(struct uart_amba_port *uap)
1921{
1922 unsigned int cr;
1923
1924 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1925 uart_port_lock_irq(&uap->port);
1926 cr = pl011_read(uap, REG_CR);
1927 cr &= UART011_CR_RTS | UART011_CR_DTR;
1928 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1929 pl011_write(cr, uap, REG_CR);
1930 uart_port_unlock_irq(&uap->port);
1931
1932 /*
1933 * disable break condition and fifos
1934 */
1935 pl011_shutdown_channel(uap, REG_LCRH_RX);
1936 if (pl011_split_lcrh(uap))
1937 pl011_shutdown_channel(uap, REG_LCRH_TX);
1938}
1939
1940static void pl011_disable_interrupts(struct uart_amba_port *uap)
1941{
1942 uart_port_lock_irq(&uap->port);
1943
1944 /* mask all interrupts and clear all pending ones */
1945 uap->im = 0;
1946 pl011_write(uap->im, uap, REG_IMSC);
1947 pl011_write(0xffff, uap, REG_ICR);
1948
1949 uart_port_unlock_irq(&uap->port);
1950}
1951
1952static void pl011_shutdown(struct uart_port *port)
1953{
1954 struct uart_amba_port *uap =
1955 container_of(port, struct uart_amba_port, port);
1956
1957 pl011_disable_interrupts(uap);
1958
1959 pl011_dma_shutdown(uap);
1960
1961 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1962 pl011_rs485_tx_stop(uap);
1963
1964 free_irq(uap->port.irq, uap);
1965
1966 pl011_disable_uart(uap);
1967
1968 /*
1969 * Shut down the clock producer
1970 */
1971 clk_disable_unprepare(uap->clk);
1972 /* Optionally let pins go into sleep states */
1973 pinctrl_pm_select_sleep_state(port->dev);
1974
1975 if (dev_get_platdata(uap->port.dev)) {
1976 struct amba_pl011_data *plat;
1977
1978 plat = dev_get_platdata(uap->port.dev);
1979 if (plat->exit)
1980 plat->exit();
1981 }
1982
1983 if (uap->port.ops->flush_buffer)
1984 uap->port.ops->flush_buffer(port);
1985}
1986
1987static void sbsa_uart_shutdown(struct uart_port *port)
1988{
1989 struct uart_amba_port *uap =
1990 container_of(port, struct uart_amba_port, port);
1991
1992 pl011_disable_interrupts(uap);
1993
1994 free_irq(uap->port.irq, uap);
1995
1996 if (uap->port.ops->flush_buffer)
1997 uap->port.ops->flush_buffer(port);
1998}
1999
2000static void
2001pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
2002{
2003 port->read_status_mask = UART011_DR_OE | 255;
2004 if (termios->c_iflag & INPCK)
2005 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
2006 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2007 port->read_status_mask |= UART011_DR_BE;
2008
2009 /*
2010 * Characters to ignore
2011 */
2012 port->ignore_status_mask = 0;
2013 if (termios->c_iflag & IGNPAR)
2014 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
2015 if (termios->c_iflag & IGNBRK) {
2016 port->ignore_status_mask |= UART011_DR_BE;
2017 /*
2018 * If we're ignoring parity and break indicators,
2019 * ignore overruns too (for real raw support).
2020 */
2021 if (termios->c_iflag & IGNPAR)
2022 port->ignore_status_mask |= UART011_DR_OE;
2023 }
2024
2025 /*
2026 * Ignore all characters if CREAD is not set.
2027 */
2028 if ((termios->c_cflag & CREAD) == 0)
2029 port->ignore_status_mask |= UART_DUMMY_DR_RX;
2030}
2031
2032static void
2033pl011_set_termios(struct uart_port *port, struct ktermios *termios,
2034 const struct ktermios *old)
2035{
2036 struct uart_amba_port *uap =
2037 container_of(port, struct uart_amba_port, port);
2038 unsigned int lcr_h, old_cr;
2039 unsigned long flags;
2040 unsigned int baud, quot, clkdiv;
2041 unsigned int bits;
2042
2043 if (uap->vendor->oversampling)
2044 clkdiv = 8;
2045 else
2046 clkdiv = 16;
2047
2048 /*
2049 * Ask the core to calculate the divisor for us.
2050 */
2051 baud = uart_get_baud_rate(port, termios, old, 0,
2052 port->uartclk / clkdiv);
2053#ifdef CONFIG_DMA_ENGINE
2054 /*
2055 * Adjust RX DMA polling rate with baud rate if not specified.
2056 */
2057 if (uap->dmarx.auto_poll_rate)
2058 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2059#endif
2060
2061 if (baud > port->uartclk / 16)
2062 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2063 else
2064 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2065
2066 switch (termios->c_cflag & CSIZE) {
2067 case CS5:
2068 lcr_h = UART01x_LCRH_WLEN_5;
2069 break;
2070 case CS6:
2071 lcr_h = UART01x_LCRH_WLEN_6;
2072 break;
2073 case CS7:
2074 lcr_h = UART01x_LCRH_WLEN_7;
2075 break;
2076 default: // CS8
2077 lcr_h = UART01x_LCRH_WLEN_8;
2078 break;
2079 }
2080 if (termios->c_cflag & CSTOPB)
2081 lcr_h |= UART01x_LCRH_STP2;
2082 if (termios->c_cflag & PARENB) {
2083 lcr_h |= UART01x_LCRH_PEN;
2084 if (!(termios->c_cflag & PARODD))
2085 lcr_h |= UART01x_LCRH_EPS;
2086 if (termios->c_cflag & CMSPAR)
2087 lcr_h |= UART011_LCRH_SPS;
2088 }
2089 if (uap->fifosize > 1)
2090 lcr_h |= UART01x_LCRH_FEN;
2091
2092 bits = tty_get_frame_size(termios->c_cflag);
2093
2094 uart_port_lock_irqsave(port, &flags);
2095
2096 /*
2097 * Update the per-port timeout.
2098 */
2099 uart_update_timeout(port, termios->c_cflag, baud);
2100
2101 /*
2102 * Calculate the approximated time it takes to transmit one character
2103 * with the given baud rate. We use this as the poll interval when we
2104 * wait for the tx queue to empty.
2105 */
2106 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
2107
2108 pl011_setup_status_masks(port, termios);
2109
2110 if (UART_ENABLE_MS(port, termios->c_cflag))
2111 pl011_enable_ms(port);
2112
2113 if (port->rs485.flags & SER_RS485_ENABLED)
2114 termios->c_cflag &= ~CRTSCTS;
2115
2116 old_cr = pl011_read(uap, REG_CR);
2117
2118 if (termios->c_cflag & CRTSCTS) {
2119 if (old_cr & UART011_CR_RTS)
2120 old_cr |= UART011_CR_RTSEN;
2121
2122 old_cr |= UART011_CR_CTSEN;
2123 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2124 } else {
2125 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2126 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2127 }
2128
2129 if (uap->vendor->oversampling) {
2130 if (baud > port->uartclk / 16)
2131 old_cr |= ST_UART011_CR_OVSFACT;
2132 else
2133 old_cr &= ~ST_UART011_CR_OVSFACT;
2134 }
2135
2136 /*
2137 * Workaround for the ST Micro oversampling variants to
2138 * increase the bitrate slightly, by lowering the divisor,
2139 * to avoid delayed sampling of start bit at high speeds,
2140 * else we see data corruption.
2141 */
2142 if (uap->vendor->oversampling) {
2143 if (baud >= 3000000 && baud < 3250000 && quot > 1)
2144 quot -= 1;
2145 else if (baud > 3250000 && quot > 2)
2146 quot -= 2;
2147 }
2148 /* Set baud rate */
2149 pl011_write(quot & 0x3f, uap, REG_FBRD);
2150 pl011_write(quot >> 6, uap, REG_IBRD);
2151
2152 /*
2153 * ----------v----------v----------v----------v-----
2154 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2155 * REG_FBRD & REG_IBRD.
2156 * ----------^----------^----------^----------^-----
2157 */
2158 pl011_write_lcr_h(uap, lcr_h);
2159
2160 /*
2161 * Receive was disabled by pl011_disable_uart during shutdown.
2162 * Need to reenable receive if you need to use a tty_driver
2163 * returns from tty_find_polling_driver() after a port shutdown.
2164 */
2165 old_cr |= UART011_CR_RXE;
2166 pl011_write(old_cr, uap, REG_CR);
2167
2168 uart_port_unlock_irqrestore(port, flags);
2169}
2170
2171static void
2172sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2173 const struct ktermios *old)
2174{
2175 struct uart_amba_port *uap =
2176 container_of(port, struct uart_amba_port, port);
2177 unsigned long flags;
2178
2179 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2180
2181 /* The SBSA UART only supports 8n1 without hardware flow control. */
2182 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2183 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2184 termios->c_cflag |= CS8 | CLOCAL;
2185
2186 uart_port_lock_irqsave(port, &flags);
2187 uart_update_timeout(port, CS8, uap->fixed_baud);
2188 pl011_setup_status_masks(port, termios);
2189 uart_port_unlock_irqrestore(port, flags);
2190}
2191
2192static const char *pl011_type(struct uart_port *port)
2193{
2194 struct uart_amba_port *uap =
2195 container_of(port, struct uart_amba_port, port);
2196 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2197}
2198
2199/*
2200 * Configure/autoconfigure the port.
2201 */
2202static void pl011_config_port(struct uart_port *port, int flags)
2203{
2204 if (flags & UART_CONFIG_TYPE)
2205 port->type = PORT_AMBA;
2206}
2207
2208/*
2209 * verify the new serial_struct (for TIOCSSERIAL).
2210 */
2211static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2212{
2213 int ret = 0;
2214
2215 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2216 ret = -EINVAL;
2217 if (ser->irq < 0 || ser->irq >= nr_irqs)
2218 ret = -EINVAL;
2219 if (ser->baud_base < 9600)
2220 ret = -EINVAL;
2221 if (port->mapbase != (unsigned long)ser->iomem_base)
2222 ret = -EINVAL;
2223 return ret;
2224}
2225
2226static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,
2227 struct serial_rs485 *rs485)
2228{
2229 struct uart_amba_port *uap =
2230 container_of(port, struct uart_amba_port, port);
2231
2232 if (port->rs485.flags & SER_RS485_ENABLED)
2233 pl011_rs485_tx_stop(uap);
2234
2235 /* Make sure auto RTS is disabled */
2236 if (rs485->flags & SER_RS485_ENABLED) {
2237 u32 cr = pl011_read(uap, REG_CR);
2238
2239 cr &= ~UART011_CR_RTSEN;
2240 pl011_write(cr, uap, REG_CR);
2241 port->status &= ~UPSTAT_AUTORTS;
2242 }
2243
2244 return 0;
2245}
2246
2247static const struct uart_ops amba_pl011_pops = {
2248 .tx_empty = pl011_tx_empty,
2249 .set_mctrl = pl011_set_mctrl,
2250 .get_mctrl = pl011_get_mctrl,
2251 .stop_tx = pl011_stop_tx,
2252 .start_tx = pl011_start_tx,
2253 .stop_rx = pl011_stop_rx,
2254 .throttle = pl011_throttle_rx,
2255 .unthrottle = pl011_unthrottle_rx,
2256 .enable_ms = pl011_enable_ms,
2257 .break_ctl = pl011_break_ctl,
2258 .startup = pl011_startup,
2259 .shutdown = pl011_shutdown,
2260 .flush_buffer = pl011_dma_flush_buffer,
2261 .set_termios = pl011_set_termios,
2262 .type = pl011_type,
2263 .config_port = pl011_config_port,
2264 .verify_port = pl011_verify_port,
2265#ifdef CONFIG_CONSOLE_POLL
2266 .poll_init = pl011_hwinit,
2267 .poll_get_char = pl011_get_poll_char,
2268 .poll_put_char = pl011_put_poll_char,
2269#endif
2270};
2271
2272static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2273{
2274}
2275
2276static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2277{
2278 return 0;
2279}
2280
2281static const struct uart_ops sbsa_uart_pops = {
2282 .tx_empty = pl011_tx_empty,
2283 .set_mctrl = sbsa_uart_set_mctrl,
2284 .get_mctrl = sbsa_uart_get_mctrl,
2285 .stop_tx = pl011_stop_tx,
2286 .start_tx = pl011_start_tx,
2287 .stop_rx = pl011_stop_rx,
2288 .startup = sbsa_uart_startup,
2289 .shutdown = sbsa_uart_shutdown,
2290 .set_termios = sbsa_uart_set_termios,
2291 .type = pl011_type,
2292 .config_port = pl011_config_port,
2293 .verify_port = pl011_verify_port,
2294#ifdef CONFIG_CONSOLE_POLL
2295 .poll_init = pl011_hwinit,
2296 .poll_get_char = pl011_get_poll_char,
2297 .poll_put_char = pl011_put_poll_char,
2298#endif
2299};
2300
2301static struct uart_amba_port *amba_ports[UART_NR];
2302
2303#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2304
2305static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
2306{
2307 struct uart_amba_port *uap =
2308 container_of(port, struct uart_amba_port, port);
2309
2310 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2311 cpu_relax();
2312 pl011_write(ch, uap, REG_DR);
2313}
2314
2315static void
2316pl011_console_write(struct console *co, const char *s, unsigned int count)
2317{
2318 struct uart_amba_port *uap = amba_ports[co->index];
2319 unsigned int old_cr = 0, new_cr;
2320 unsigned long flags;
2321 int locked = 1;
2322
2323 clk_enable(uap->clk);
2324
2325 local_irq_save(flags);
2326 if (uap->port.sysrq)
2327 locked = 0;
2328 else if (oops_in_progress)
2329 locked = uart_port_trylock(&uap->port);
2330 else
2331 uart_port_lock(&uap->port);
2332
2333 /*
2334 * First save the CR then disable the interrupts
2335 */
2336 if (!uap->vendor->always_enabled) {
2337 old_cr = pl011_read(uap, REG_CR);
2338 new_cr = old_cr & ~UART011_CR_CTSEN;
2339 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2340 pl011_write(new_cr, uap, REG_CR);
2341 }
2342
2343 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2344
2345 /*
2346 * Finally, wait for transmitter to become empty and restore the
2347 * TCR. Allow feature register bits to be inverted to work around
2348 * errata.
2349 */
2350 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2351 & uap->vendor->fr_busy)
2352 cpu_relax();
2353 if (!uap->vendor->always_enabled)
2354 pl011_write(old_cr, uap, REG_CR);
2355
2356 if (locked)
2357 uart_port_unlock(&uap->port);
2358 local_irq_restore(flags);
2359
2360 clk_disable(uap->clk);
2361}
2362
2363static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2364 int *parity, int *bits)
2365{
2366 unsigned int lcr_h, ibrd, fbrd;
2367
2368 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN))
2369 return;
2370
2371 lcr_h = pl011_read(uap, REG_LCRH_TX);
2372
2373 *parity = 'n';
2374 if (lcr_h & UART01x_LCRH_PEN) {
2375 if (lcr_h & UART01x_LCRH_EPS)
2376 *parity = 'e';
2377 else
2378 *parity = 'o';
2379 }
2380
2381 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2382 *bits = 7;
2383 else
2384 *bits = 8;
2385
2386 ibrd = pl011_read(uap, REG_IBRD);
2387 fbrd = pl011_read(uap, REG_FBRD);
2388
2389 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2390
2391 if (uap->vendor->oversampling &&
2392 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT))
2393 *baud *= 2;
2394}
2395
2396static int pl011_console_setup(struct console *co, char *options)
2397{
2398 struct uart_amba_port *uap;
2399 int baud = 38400;
2400 int bits = 8;
2401 int parity = 'n';
2402 int flow = 'n';
2403 int ret;
2404
2405 /*
2406 * Check whether an invalid uart number has been specified, and
2407 * if so, search for the first available port that does have
2408 * console support.
2409 */
2410 if (co->index >= UART_NR)
2411 co->index = 0;
2412 uap = amba_ports[co->index];
2413 if (!uap)
2414 return -ENODEV;
2415
2416 /* Allow pins to be muxed in and configured */
2417 pinctrl_pm_select_default_state(uap->port.dev);
2418
2419 ret = clk_prepare(uap->clk);
2420 if (ret)
2421 return ret;
2422
2423 if (dev_get_platdata(uap->port.dev)) {
2424 struct amba_pl011_data *plat;
2425
2426 plat = dev_get_platdata(uap->port.dev);
2427 if (plat->init)
2428 plat->init();
2429 }
2430
2431 uap->port.uartclk = clk_get_rate(uap->clk);
2432
2433 if (uap->vendor->fixed_options) {
2434 baud = uap->fixed_baud;
2435 } else {
2436 if (options)
2437 uart_parse_options(options,
2438 &baud, &parity, &bits, &flow);
2439 else
2440 pl011_console_get_options(uap, &baud, &parity, &bits);
2441 }
2442
2443 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2444}
2445
2446/**
2447 * pl011_console_match - non-standard console matching
2448 * @co: registering console
2449 * @name: name from console command line
2450 * @idx: index from console command line
2451 * @options: ptr to option string from console command line
2452 *
2453 * Only attempts to match console command lines of the form:
2454 * console=pl011,mmio|mmio32,<addr>[,<options>]
2455 * console=pl011,0x<addr>[,<options>]
2456 * This form is used to register an initial earlycon boot console and
2457 * replace it with the amba_console at pl011 driver init.
2458 *
2459 * Performs console setup for a match (as required by interface)
2460 * If no <options> are specified, then assume the h/w is already setup.
2461 *
2462 * Returns 0 if console matches; otherwise non-zero to use default matching
2463 */
2464static int pl011_console_match(struct console *co, char *name, int idx,
2465 char *options)
2466{
2467 unsigned char iotype;
2468 resource_size_t addr;
2469 int i;
2470
2471 /*
2472 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2473 * have a distinct console name, so make sure we check for that.
2474 * The actual implementation of the erratum occurs in the probe
2475 * function.
2476 */
2477 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2478 return -ENODEV;
2479
2480 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2481 return -ENODEV;
2482
2483 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2484 return -ENODEV;
2485
2486 /* try to match the port specified on the command line */
2487 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2488 struct uart_port *port;
2489
2490 if (!amba_ports[i])
2491 continue;
2492
2493 port = &amba_ports[i]->port;
2494
2495 if (port->mapbase != addr)
2496 continue;
2497
2498 co->index = i;
2499 port->cons = co;
2500 return pl011_console_setup(co, options);
2501 }
2502
2503 return -ENODEV;
2504}
2505
2506static struct uart_driver amba_reg;
2507static struct console amba_console = {
2508 .name = "ttyAMA",
2509 .write = pl011_console_write,
2510 .device = uart_console_device,
2511 .setup = pl011_console_setup,
2512 .match = pl011_console_match,
2513 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2514 .index = -1,
2515 .data = &amba_reg,
2516};
2517
2518#define AMBA_CONSOLE (&amba_console)
2519
2520static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
2521{
2522 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2523 cpu_relax();
2524 writel(c, port->membase + UART01x_DR);
2525 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2526 cpu_relax();
2527}
2528
2529static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n)
2530{
2531 struct earlycon_device *dev = con->data;
2532
2533 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2534}
2535
2536static void pl011_putc(struct uart_port *port, unsigned char c)
2537{
2538 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2539 cpu_relax();
2540 if (port->iotype == UPIO_MEM32)
2541 writel(c, port->membase + UART01x_DR);
2542 else
2543 writeb(c, port->membase + UART01x_DR);
2544 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2545 cpu_relax();
2546}
2547
2548static void pl011_early_write(struct console *con, const char *s, unsigned int n)
2549{
2550 struct earlycon_device *dev = con->data;
2551
2552 uart_console_write(&dev->port, s, n, pl011_putc);
2553}
2554
2555#ifdef CONFIG_CONSOLE_POLL
2556static int pl011_getc(struct uart_port *port)
2557{
2558 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2559 return NO_POLL_CHAR;
2560
2561 if (port->iotype == UPIO_MEM32)
2562 return readl(port->membase + UART01x_DR);
2563 else
2564 return readb(port->membase + UART01x_DR);
2565}
2566
2567static int pl011_early_read(struct console *con, char *s, unsigned int n)
2568{
2569 struct earlycon_device *dev = con->data;
2570 int ch, num_read = 0;
2571
2572 while (num_read < n) {
2573 ch = pl011_getc(&dev->port);
2574 if (ch == NO_POLL_CHAR)
2575 break;
2576
2577 s[num_read++] = ch;
2578 }
2579
2580 return num_read;
2581}
2582#else
2583#define pl011_early_read NULL
2584#endif
2585
2586/*
2587 * On non-ACPI systems, earlycon is enabled by specifying
2588 * "earlycon=pl011,<address>" on the kernel command line.
2589 *
2590 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2591 * by specifying only "earlycon" on the command line. Because it requires
2592 * SPCR, the console starts after ACPI is parsed, which is later than a
2593 * traditional early console.
2594 *
2595 * To get the traditional early console that starts before ACPI is parsed,
2596 * specify the full "earlycon=pl011,<address>" option.
2597 */
2598static int __init pl011_early_console_setup(struct earlycon_device *device,
2599 const char *opt)
2600{
2601 if (!device->port.membase)
2602 return -ENODEV;
2603
2604 device->con->write = pl011_early_write;
2605 device->con->read = pl011_early_read;
2606
2607 return 0;
2608}
2609
2610OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2611
2612OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2613
2614/*
2615 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2616 * Erratum 44, traditional earlycon can be enabled by specifying
2617 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2618 *
2619 * Alternatively, you can just specify "earlycon", and the early console
2620 * will be enabled with the information from the SPCR table. In this
2621 * case, the SPCR code will detect the need for the E44 work-around,
2622 * and set the console name to "qdf2400_e44".
2623 */
2624static int __init
2625qdf2400_e44_early_console_setup(struct earlycon_device *device,
2626 const char *opt)
2627{
2628 if (!device->port.membase)
2629 return -ENODEV;
2630
2631 device->con->write = qdf2400_e44_early_write;
2632 return 0;
2633}
2634
2635EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2636
2637#else
2638#define AMBA_CONSOLE NULL
2639#endif
2640
2641static struct uart_driver amba_reg = {
2642 .owner = THIS_MODULE,
2643 .driver_name = "ttyAMA",
2644 .dev_name = "ttyAMA",
2645 .major = SERIAL_AMBA_MAJOR,
2646 .minor = SERIAL_AMBA_MINOR,
2647 .nr = UART_NR,
2648 .cons = AMBA_CONSOLE,
2649};
2650
2651static int pl011_probe_dt_alias(int index, struct device *dev)
2652{
2653 struct device_node *np;
2654 static bool seen_dev_with_alias;
2655 static bool seen_dev_without_alias;
2656 int ret = index;
2657
2658 if (!IS_ENABLED(CONFIG_OF))
2659 return ret;
2660
2661 np = dev->of_node;
2662 if (!np)
2663 return ret;
2664
2665 ret = of_alias_get_id(np, "serial");
2666 if (ret < 0) {
2667 seen_dev_without_alias = true;
2668 ret = index;
2669 } else {
2670 seen_dev_with_alias = true;
2671 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) {
2672 dev_warn(dev, "requested serial port %d not available.\n", ret);
2673 ret = index;
2674 }
2675 }
2676
2677 if (seen_dev_with_alias && seen_dev_without_alias)
2678 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2679
2680 return ret;
2681}
2682
2683/* unregisters the driver also if no more ports are left */
2684static void pl011_unregister_port(struct uart_amba_port *uap)
2685{
2686 int i;
2687 bool busy = false;
2688
2689 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2690 if (amba_ports[i] == uap)
2691 amba_ports[i] = NULL;
2692 else if (amba_ports[i])
2693 busy = true;
2694 }
2695 pl011_dma_remove(uap);
2696 if (!busy)
2697 uart_unregister_driver(&amba_reg);
2698}
2699
2700static int pl011_find_free_port(void)
2701{
2702 int i;
2703
2704 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2705 if (!amba_ports[i])
2706 return i;
2707
2708 return -EBUSY;
2709}
2710
2711static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2712{
2713 struct uart_port *port = &uap->port;
2714 int ret;
2715
2716 ret = uart_get_rs485_mode(port);
2717 if (ret)
2718 return ret;
2719
2720 return 0;
2721}
2722
2723static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2724 struct resource *mmiobase, int index)
2725{
2726 void __iomem *base;
2727 int ret;
2728
2729 base = devm_ioremap_resource(dev, mmiobase);
2730 if (IS_ERR(base))
2731 return PTR_ERR(base);
2732
2733 index = pl011_probe_dt_alias(index, dev);
2734
2735 uap->port.dev = dev;
2736 uap->port.mapbase = mmiobase->start;
2737 uap->port.membase = base;
2738 uap->port.fifosize = uap->fifosize;
2739 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2740 uap->port.flags = UPF_BOOT_AUTOCONF;
2741 uap->port.line = index;
2742
2743 ret = pl011_get_rs485_mode(uap);
2744 if (ret)
2745 return ret;
2746
2747 amba_ports[index] = uap;
2748
2749 return 0;
2750}
2751
2752static int pl011_register_port(struct uart_amba_port *uap)
2753{
2754 int ret, i;
2755
2756 /* Ensure interrupts from this UART are masked and cleared */
2757 pl011_write(0, uap, REG_IMSC);
2758 pl011_write(0xffff, uap, REG_ICR);
2759
2760 if (!amba_reg.state) {
2761 ret = uart_register_driver(&amba_reg);
2762 if (ret < 0) {
2763 dev_err(uap->port.dev,
2764 "Failed to register AMBA-PL011 driver\n");
2765 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2766 if (amba_ports[i] == uap)
2767 amba_ports[i] = NULL;
2768 return ret;
2769 }
2770 }
2771
2772 ret = uart_add_one_port(&amba_reg, &uap->port);
2773 if (ret)
2774 pl011_unregister_port(uap);
2775
2776 return ret;
2777}
2778
2779static const struct serial_rs485 pl011_rs485_supported = {
2780 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2781 SER_RS485_RX_DURING_TX,
2782 .delay_rts_before_send = 1,
2783 .delay_rts_after_send = 1,
2784};
2785
2786static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2787{
2788 struct uart_amba_port *uap;
2789 struct vendor_data *vendor = id->data;
2790 int portnr, ret;
2791 u32 val;
2792
2793 portnr = pl011_find_free_port();
2794 if (portnr < 0)
2795 return portnr;
2796
2797 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2798 GFP_KERNEL);
2799 if (!uap)
2800 return -ENOMEM;
2801
2802 uap->clk = devm_clk_get(&dev->dev, NULL);
2803 if (IS_ERR(uap->clk))
2804 return PTR_ERR(uap->clk);
2805
2806 uap->reg_offset = vendor->reg_offset;
2807 uap->vendor = vendor;
2808 uap->fifosize = vendor->get_fifosize(dev);
2809 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2810 uap->port.irq = dev->irq[0];
2811 uap->port.ops = &amba_pl011_pops;
2812 uap->port.rs485_config = pl011_rs485_config;
2813 uap->port.rs485_supported = pl011_rs485_supported;
2814 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2815
2816 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
2817 switch (val) {
2818 case 1:
2819 uap->port.iotype = UPIO_MEM;
2820 break;
2821 case 4:
2822 uap->port.iotype = UPIO_MEM32;
2823 break;
2824 default:
2825 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
2826 val);
2827 return -EINVAL;
2828 }
2829 }
2830
2831 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2832 if (ret)
2833 return ret;
2834
2835 amba_set_drvdata(dev, uap);
2836
2837 return pl011_register_port(uap);
2838}
2839
2840static void pl011_remove(struct amba_device *dev)
2841{
2842 struct uart_amba_port *uap = amba_get_drvdata(dev);
2843
2844 uart_remove_one_port(&amba_reg, &uap->port);
2845 pl011_unregister_port(uap);
2846}
2847
2848#ifdef CONFIG_PM_SLEEP
2849static int pl011_suspend(struct device *dev)
2850{
2851 struct uart_amba_port *uap = dev_get_drvdata(dev);
2852
2853 if (!uap)
2854 return -EINVAL;
2855
2856 return uart_suspend_port(&amba_reg, &uap->port);
2857}
2858
2859static int pl011_resume(struct device *dev)
2860{
2861 struct uart_amba_port *uap = dev_get_drvdata(dev);
2862
2863 if (!uap)
2864 return -EINVAL;
2865
2866 return uart_resume_port(&amba_reg, &uap->port);
2867}
2868#endif
2869
2870static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2871
2872#ifdef CONFIG_ACPI_SPCR_TABLE
2873static void qpdf2400_erratum44_workaround(struct device *dev,
2874 struct uart_amba_port *uap)
2875{
2876 if (!qdf2400_e44_present)
2877 return;
2878
2879 dev_info(dev, "working around QDF2400 SoC erratum 44\n");
2880 uap->vendor = &vendor_qdt_qdf2400_e44;
2881}
2882#else
2883static void qpdf2400_erratum44_workaround(struct device *dev,
2884 struct uart_amba_port *uap)
2885{ /* empty */ }
2886#endif
2887
2888static int sbsa_uart_probe(struct platform_device *pdev)
2889{
2890 struct uart_amba_port *uap;
2891 struct resource *r;
2892 int portnr, ret;
2893 int baudrate;
2894
2895 /*
2896 * Check the mandatory baud rate parameter in the DT node early
2897 * so that we can easily exit with the error.
2898 */
2899 if (pdev->dev.of_node) {
2900 struct device_node *np = pdev->dev.of_node;
2901
2902 ret = of_property_read_u32(np, "current-speed", &baudrate);
2903 if (ret)
2904 return ret;
2905 } else {
2906 baudrate = 115200;
2907 }
2908
2909 portnr = pl011_find_free_port();
2910 if (portnr < 0)
2911 return portnr;
2912
2913 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2914 GFP_KERNEL);
2915 if (!uap)
2916 return -ENOMEM;
2917
2918 ret = platform_get_irq(pdev, 0);
2919 if (ret < 0)
2920 return ret;
2921 uap->port.irq = ret;
2922
2923 uap->vendor = &vendor_sbsa;
2924 qpdf2400_erratum44_workaround(&pdev->dev, uap);
2925
2926 uap->reg_offset = uap->vendor->reg_offset;
2927 uap->fifosize = 32;
2928 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2929 uap->port.ops = &sbsa_uart_pops;
2930 uap->fixed_baud = baudrate;
2931
2932 snprintf(uap->type, sizeof(uap->type), "SBSA");
2933
2934 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2935
2936 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2937 if (ret)
2938 return ret;
2939
2940 platform_set_drvdata(pdev, uap);
2941
2942 return pl011_register_port(uap);
2943}
2944
2945static void sbsa_uart_remove(struct platform_device *pdev)
2946{
2947 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2948
2949 uart_remove_one_port(&amba_reg, &uap->port);
2950 pl011_unregister_port(uap);
2951}
2952
2953static const struct of_device_id sbsa_uart_of_match[] = {
2954 { .compatible = "arm,sbsa-uart", },
2955 {},
2956};
2957MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2958
2959static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
2960 { "ARMH0011", 0 },
2961 { "ARMHB000", 0 },
2962 {},
2963};
2964MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2965
2966static struct platform_driver arm_sbsa_uart_platform_driver = {
2967 .probe = sbsa_uart_probe,
2968 .remove_new = sbsa_uart_remove,
2969 .driver = {
2970 .name = "sbsa-uart",
2971 .pm = &pl011_dev_pm_ops,
2972 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2973 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2974 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2975 },
2976};
2977
2978static const struct amba_id pl011_ids[] = {
2979 {
2980 .id = 0x00041011,
2981 .mask = 0x000fffff,
2982 .data = &vendor_arm,
2983 },
2984 {
2985 .id = 0x00380802,
2986 .mask = 0x00ffffff,
2987 .data = &vendor_st,
2988 },
2989 { 0, 0 },
2990};
2991
2992MODULE_DEVICE_TABLE(amba, pl011_ids);
2993
2994static struct amba_driver pl011_driver = {
2995 .drv = {
2996 .name = "uart-pl011",
2997 .pm = &pl011_dev_pm_ops,
2998 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2999 },
3000 .id_table = pl011_ids,
3001 .probe = pl011_probe,
3002 .remove = pl011_remove,
3003};
3004
3005static int __init pl011_init(void)
3006{
3007 pr_info("Serial: AMBA PL011 UART driver\n");
3008
3009 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
3010 pr_warn("could not register SBSA UART platform driver\n");
3011 return amba_driver_register(&pl011_driver);
3012}
3013
3014static void __exit pl011_exit(void)
3015{
3016 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
3017 amba_driver_unregister(&pl011_driver);
3018}
3019
3020/*
3021 * While this can be a module, if builtin it's most likely the console
3022 * So let's leave module_exit but move module_init to an earlier place
3023 */
3024arch_initcall(pl011_init);
3025module_exit(pl011_exit);
3026
3027MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
3028MODULE_DESCRIPTION("ARM AMBA serial port driver");
3029MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/device.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/amba/bus.h>
30#include <linux/amba/serial.h>
31#include <linux/clk.h>
32#include <linux/slab.h>
33#include <linux/dmaengine.h>
34#include <linux/dma-mapping.h>
35#include <linux/scatterlist.h>
36#include <linux/delay.h>
37#include <linux/types.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/pinctrl/consumer.h>
41#include <linux/sizes.h>
42#include <linux/io.h>
43#include <linux/acpi.h>
44
45#include "amba-pl011.h"
46
47#define UART_NR 14
48
49#define SERIAL_AMBA_MAJOR 204
50#define SERIAL_AMBA_MINOR 64
51#define SERIAL_AMBA_NR UART_NR
52
53#define AMBA_ISR_PASS_LIMIT 256
54
55#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
56#define UART_DUMMY_DR_RX (1 << 16)
57
58static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
59 [REG_DR] = UART01x_DR,
60 [REG_FR] = UART01x_FR,
61 [REG_LCRH_RX] = UART011_LCRH,
62 [REG_LCRH_TX] = UART011_LCRH,
63 [REG_IBRD] = UART011_IBRD,
64 [REG_FBRD] = UART011_FBRD,
65 [REG_CR] = UART011_CR,
66 [REG_IFLS] = UART011_IFLS,
67 [REG_IMSC] = UART011_IMSC,
68 [REG_RIS] = UART011_RIS,
69 [REG_MIS] = UART011_MIS,
70 [REG_ICR] = UART011_ICR,
71 [REG_DMACR] = UART011_DMACR,
72};
73
74/* There is by now at least one vendor with differing details, so handle it */
75struct vendor_data {
76 const u16 *reg_offset;
77 unsigned int ifls;
78 unsigned int fr_busy;
79 unsigned int fr_dsr;
80 unsigned int fr_cts;
81 unsigned int fr_ri;
82 unsigned int inv_fr;
83 bool access_32b;
84 bool oversampling;
85 bool dma_threshold;
86 bool cts_event_workaround;
87 bool always_enabled;
88 bool fixed_options;
89
90 unsigned int (*get_fifosize)(struct amba_device *dev);
91};
92
93static unsigned int get_fifosize_arm(struct amba_device *dev)
94{
95 return amba_rev(dev) < 3 ? 16 : 32;
96}
97
98static struct vendor_data vendor_arm = {
99 .reg_offset = pl011_std_offsets,
100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
101 .fr_busy = UART01x_FR_BUSY,
102 .fr_dsr = UART01x_FR_DSR,
103 .fr_cts = UART01x_FR_CTS,
104 .fr_ri = UART011_FR_RI,
105 .oversampling = false,
106 .dma_threshold = false,
107 .cts_event_workaround = false,
108 .always_enabled = false,
109 .fixed_options = false,
110 .get_fifosize = get_fifosize_arm,
111};
112
113static const struct vendor_data vendor_sbsa = {
114 .reg_offset = pl011_std_offsets,
115 .fr_busy = UART01x_FR_BUSY,
116 .fr_dsr = UART01x_FR_DSR,
117 .fr_cts = UART01x_FR_CTS,
118 .fr_ri = UART011_FR_RI,
119 .access_32b = true,
120 .oversampling = false,
121 .dma_threshold = false,
122 .cts_event_workaround = false,
123 .always_enabled = true,
124 .fixed_options = true,
125};
126
127#ifdef CONFIG_ACPI_SPCR_TABLE
128static const struct vendor_data vendor_qdt_qdf2400_e44 = {
129 .reg_offset = pl011_std_offsets,
130 .fr_busy = UART011_FR_TXFE,
131 .fr_dsr = UART01x_FR_DSR,
132 .fr_cts = UART01x_FR_CTS,
133 .fr_ri = UART011_FR_RI,
134 .inv_fr = UART011_FR_TXFE,
135 .access_32b = true,
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
141};
142#endif
143
144static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
169};
170
171static unsigned int get_fifosize_st(struct amba_device *dev)
172{
173 return 64;
174}
175
176static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
189};
190
191static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205};
206
207static unsigned int get_fifosize_zte(struct amba_device *dev)
208{
209 return 16;
210}
211
212static struct vendor_data vendor_zte = {
213 .reg_offset = pl011_zte_offsets,
214 .access_32b = true,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
220 .get_fifosize = get_fifosize_zte,
221};
222
223/* Deals with DMA transactions */
224
225struct pl011_sgbuf {
226 struct scatterlist sg;
227 char *buf;
228};
229
230struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
233 bool use_buf_b;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
236 dma_cookie_t cookie;
237 bool running;
238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
241 bool auto_poll_rate;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
244};
245
246struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
249 char *buf;
250 bool queued;
251};
252
253/*
254 * We wrap our port structure around the generic uart_port.
255 */
256struct uart_amba_port {
257 struct uart_port port;
258 const u16 *reg_offset;
259 struct clk *clk;
260 const struct vendor_data *vendor;
261 unsigned int dmacr; /* dma control reg */
262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
264 unsigned int fifosize; /* vendor-specific */
265 unsigned int old_cr; /* state during shutdown */
266 unsigned int fixed_baud; /* vendor-set fixed baud rate */
267 char type[12];
268#ifdef CONFIG_DMA_ENGINE
269 /* DMA stuff */
270 bool using_tx_dma;
271 bool using_rx_dma;
272 struct pl011_dmarx_data dmarx;
273 struct pl011_dmatx_data dmatx;
274 bool dma_probed;
275#endif
276};
277
278static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
279 unsigned int reg)
280{
281 return uap->reg_offset[reg];
282}
283
284static unsigned int pl011_read(const struct uart_amba_port *uap,
285 unsigned int reg)
286{
287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
288
289 return (uap->port.iotype == UPIO_MEM32) ?
290 readl_relaxed(addr) : readw_relaxed(addr);
291}
292
293static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
294 unsigned int reg)
295{
296 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
297
298 if (uap->port.iotype == UPIO_MEM32)
299 writel_relaxed(val, addr);
300 else
301 writew_relaxed(val, addr);
302}
303
304/*
305 * Reads up to 256 characters from the FIFO or until it's empty and
306 * inserts them into the TTY layer. Returns the number of characters
307 * read from the FIFO.
308 */
309static int pl011_fifo_to_tty(struct uart_amba_port *uap)
310{
311 u16 status;
312 unsigned int ch, flag, fifotaken;
313
314 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
315 status = pl011_read(uap, REG_FR);
316 if (status & UART01x_FR_RXFE)
317 break;
318
319 /* Take chars from the FIFO and update status */
320 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
321 flag = TTY_NORMAL;
322 uap->port.icount.rx++;
323
324 if (unlikely(ch & UART_DR_ERROR)) {
325 if (ch & UART011_DR_BE) {
326 ch &= ~(UART011_DR_FE | UART011_DR_PE);
327 uap->port.icount.brk++;
328 if (uart_handle_break(&uap->port))
329 continue;
330 } else if (ch & UART011_DR_PE)
331 uap->port.icount.parity++;
332 else if (ch & UART011_DR_FE)
333 uap->port.icount.frame++;
334 if (ch & UART011_DR_OE)
335 uap->port.icount.overrun++;
336
337 ch &= uap->port.read_status_mask;
338
339 if (ch & UART011_DR_BE)
340 flag = TTY_BREAK;
341 else if (ch & UART011_DR_PE)
342 flag = TTY_PARITY;
343 else if (ch & UART011_DR_FE)
344 flag = TTY_FRAME;
345 }
346
347 if (uart_handle_sysrq_char(&uap->port, ch & 255))
348 continue;
349
350 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
351 }
352
353 return fifotaken;
354}
355
356
357/*
358 * All the DMA operation mode stuff goes inside this ifdef.
359 * This assumes that you have a generic DMA device interface,
360 * no custom DMA interfaces are supported.
361 */
362#ifdef CONFIG_DMA_ENGINE
363
364#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
365
366static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
367 enum dma_data_direction dir)
368{
369 dma_addr_t dma_addr;
370
371 sg->buf = dma_alloc_coherent(chan->device->dev,
372 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
373 if (!sg->buf)
374 return -ENOMEM;
375
376 sg_init_table(&sg->sg, 1);
377 sg_set_page(&sg->sg, phys_to_page(dma_addr),
378 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
379 sg_dma_address(&sg->sg) = dma_addr;
380 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
381
382 return 0;
383}
384
385static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
386 enum dma_data_direction dir)
387{
388 if (sg->buf) {
389 dma_free_coherent(chan->device->dev,
390 PL011_DMA_BUFFER_SIZE, sg->buf,
391 sg_dma_address(&sg->sg));
392 }
393}
394
395static void pl011_dma_probe(struct uart_amba_port *uap)
396{
397 /* DMA is the sole user of the platform data right now */
398 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
399 struct device *dev = uap->port.dev;
400 struct dma_slave_config tx_conf = {
401 .dst_addr = uap->port.mapbase +
402 pl011_reg_to_offset(uap, REG_DR),
403 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
404 .direction = DMA_MEM_TO_DEV,
405 .dst_maxburst = uap->fifosize >> 1,
406 .device_fc = false,
407 };
408 struct dma_chan *chan;
409 dma_cap_mask_t mask;
410
411 uap->dma_probed = true;
412 chan = dma_request_chan(dev, "tx");
413 if (IS_ERR(chan)) {
414 if (PTR_ERR(chan) == -EPROBE_DEFER) {
415 uap->dma_probed = false;
416 return;
417 }
418
419 /* We need platform data */
420 if (!plat || !plat->dma_filter) {
421 dev_info(uap->port.dev, "no DMA platform data\n");
422 return;
423 }
424
425 /* Try to acquire a generic DMA engine slave TX channel */
426 dma_cap_zero(mask);
427 dma_cap_set(DMA_SLAVE, mask);
428
429 chan = dma_request_channel(mask, plat->dma_filter,
430 plat->dma_tx_param);
431 if (!chan) {
432 dev_err(uap->port.dev, "no TX DMA channel!\n");
433 return;
434 }
435 }
436
437 dmaengine_slave_config(chan, &tx_conf);
438 uap->dmatx.chan = chan;
439
440 dev_info(uap->port.dev, "DMA channel TX %s\n",
441 dma_chan_name(uap->dmatx.chan));
442
443 /* Optionally make use of an RX channel as well */
444 chan = dma_request_slave_channel(dev, "rx");
445
446 if (!chan && plat && plat->dma_rx_param) {
447 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
448
449 if (!chan) {
450 dev_err(uap->port.dev, "no RX DMA channel!\n");
451 return;
452 }
453 }
454
455 if (chan) {
456 struct dma_slave_config rx_conf = {
457 .src_addr = uap->port.mapbase +
458 pl011_reg_to_offset(uap, REG_DR),
459 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
460 .direction = DMA_DEV_TO_MEM,
461 .src_maxburst = uap->fifosize >> 2,
462 .device_fc = false,
463 };
464 struct dma_slave_caps caps;
465
466 /*
467 * Some DMA controllers provide information on their capabilities.
468 * If the controller does, check for suitable residue processing
469 * otherwise assime all is well.
470 */
471 if (0 == dma_get_slave_caps(chan, &caps)) {
472 if (caps.residue_granularity ==
473 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
474 dma_release_channel(chan);
475 dev_info(uap->port.dev,
476 "RX DMA disabled - no residue processing\n");
477 return;
478 }
479 }
480 dmaengine_slave_config(chan, &rx_conf);
481 uap->dmarx.chan = chan;
482
483 uap->dmarx.auto_poll_rate = false;
484 if (plat && plat->dma_rx_poll_enable) {
485 /* Set poll rate if specified. */
486 if (plat->dma_rx_poll_rate) {
487 uap->dmarx.auto_poll_rate = false;
488 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
489 } else {
490 /*
491 * 100 ms defaults to poll rate if not
492 * specified. This will be adjusted with
493 * the baud rate at set_termios.
494 */
495 uap->dmarx.auto_poll_rate = true;
496 uap->dmarx.poll_rate = 100;
497 }
498 /* 3 secs defaults poll_timeout if not specified. */
499 if (plat->dma_rx_poll_timeout)
500 uap->dmarx.poll_timeout =
501 plat->dma_rx_poll_timeout;
502 else
503 uap->dmarx.poll_timeout = 3000;
504 } else if (!plat && dev->of_node) {
505 uap->dmarx.auto_poll_rate = of_property_read_bool(
506 dev->of_node, "auto-poll");
507 if (uap->dmarx.auto_poll_rate) {
508 u32 x;
509
510 if (0 == of_property_read_u32(dev->of_node,
511 "poll-rate-ms", &x))
512 uap->dmarx.poll_rate = x;
513 else
514 uap->dmarx.poll_rate = 100;
515 if (0 == of_property_read_u32(dev->of_node,
516 "poll-timeout-ms", &x))
517 uap->dmarx.poll_timeout = x;
518 else
519 uap->dmarx.poll_timeout = 3000;
520 }
521 }
522 dev_info(uap->port.dev, "DMA channel RX %s\n",
523 dma_chan_name(uap->dmarx.chan));
524 }
525}
526
527static void pl011_dma_remove(struct uart_amba_port *uap)
528{
529 if (uap->dmatx.chan)
530 dma_release_channel(uap->dmatx.chan);
531 if (uap->dmarx.chan)
532 dma_release_channel(uap->dmarx.chan);
533}
534
535/* Forward declare these for the refill routine */
536static int pl011_dma_tx_refill(struct uart_amba_port *uap);
537static void pl011_start_tx_pio(struct uart_amba_port *uap);
538
539/*
540 * The current DMA TX buffer has been sent.
541 * Try to queue up another DMA buffer.
542 */
543static void pl011_dma_tx_callback(void *data)
544{
545 struct uart_amba_port *uap = data;
546 struct pl011_dmatx_data *dmatx = &uap->dmatx;
547 unsigned long flags;
548 u16 dmacr;
549
550 spin_lock_irqsave(&uap->port.lock, flags);
551 if (uap->dmatx.queued)
552 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
553 DMA_TO_DEVICE);
554
555 dmacr = uap->dmacr;
556 uap->dmacr = dmacr & ~UART011_TXDMAE;
557 pl011_write(uap->dmacr, uap, REG_DMACR);
558
559 /*
560 * If TX DMA was disabled, it means that we've stopped the DMA for
561 * some reason (eg, XOFF received, or we want to send an X-char.)
562 *
563 * Note: we need to be careful here of a potential race between DMA
564 * and the rest of the driver - if the driver disables TX DMA while
565 * a TX buffer completing, we must update the tx queued status to
566 * get further refills (hence we check dmacr).
567 */
568 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
569 uart_circ_empty(&uap->port.state->xmit)) {
570 uap->dmatx.queued = false;
571 spin_unlock_irqrestore(&uap->port.lock, flags);
572 return;
573 }
574
575 if (pl011_dma_tx_refill(uap) <= 0)
576 /*
577 * We didn't queue a DMA buffer for some reason, but we
578 * have data pending to be sent. Re-enable the TX IRQ.
579 */
580 pl011_start_tx_pio(uap);
581
582 spin_unlock_irqrestore(&uap->port.lock, flags);
583}
584
585/*
586 * Try to refill the TX DMA buffer.
587 * Locking: called with port lock held and IRQs disabled.
588 * Returns:
589 * 1 if we queued up a TX DMA buffer.
590 * 0 if we didn't want to handle this by DMA
591 * <0 on error
592 */
593static int pl011_dma_tx_refill(struct uart_amba_port *uap)
594{
595 struct pl011_dmatx_data *dmatx = &uap->dmatx;
596 struct dma_chan *chan = dmatx->chan;
597 struct dma_device *dma_dev = chan->device;
598 struct dma_async_tx_descriptor *desc;
599 struct circ_buf *xmit = &uap->port.state->xmit;
600 unsigned int count;
601
602 /*
603 * Try to avoid the overhead involved in using DMA if the
604 * transaction fits in the first half of the FIFO, by using
605 * the standard interrupt handling. This ensures that we
606 * issue a uart_write_wakeup() at the appropriate time.
607 */
608 count = uart_circ_chars_pending(xmit);
609 if (count < (uap->fifosize >> 1)) {
610 uap->dmatx.queued = false;
611 return 0;
612 }
613
614 /*
615 * Bodge: don't send the last character by DMA, as this
616 * will prevent XON from notifying us to restart DMA.
617 */
618 count -= 1;
619
620 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
621 if (count > PL011_DMA_BUFFER_SIZE)
622 count = PL011_DMA_BUFFER_SIZE;
623
624 if (xmit->tail < xmit->head)
625 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
626 else {
627 size_t first = UART_XMIT_SIZE - xmit->tail;
628 size_t second;
629
630 if (first > count)
631 first = count;
632 second = count - first;
633
634 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
635 if (second)
636 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
637 }
638
639 dmatx->sg.length = count;
640
641 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
642 uap->dmatx.queued = false;
643 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
644 return -EBUSY;
645 }
646
647 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
648 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
649 if (!desc) {
650 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
651 uap->dmatx.queued = false;
652 /*
653 * If DMA cannot be used right now, we complete this
654 * transaction via IRQ and let the TTY layer retry.
655 */
656 dev_dbg(uap->port.dev, "TX DMA busy\n");
657 return -EBUSY;
658 }
659
660 /* Some data to go along to the callback */
661 desc->callback = pl011_dma_tx_callback;
662 desc->callback_param = uap;
663
664 /* All errors should happen at prepare time */
665 dmaengine_submit(desc);
666
667 /* Fire the DMA transaction */
668 dma_dev->device_issue_pending(chan);
669
670 uap->dmacr |= UART011_TXDMAE;
671 pl011_write(uap->dmacr, uap, REG_DMACR);
672 uap->dmatx.queued = true;
673
674 /*
675 * Now we know that DMA will fire, so advance the ring buffer
676 * with the stuff we just dispatched.
677 */
678 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
679 uap->port.icount.tx += count;
680
681 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
682 uart_write_wakeup(&uap->port);
683
684 return 1;
685}
686
687/*
688 * We received a transmit interrupt without a pending X-char but with
689 * pending characters.
690 * Locking: called with port lock held and IRQs disabled.
691 * Returns:
692 * false if we want to use PIO to transmit
693 * true if we queued a DMA buffer
694 */
695static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
696{
697 if (!uap->using_tx_dma)
698 return false;
699
700 /*
701 * If we already have a TX buffer queued, but received a
702 * TX interrupt, it will be because we've just sent an X-char.
703 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
704 */
705 if (uap->dmatx.queued) {
706 uap->dmacr |= UART011_TXDMAE;
707 pl011_write(uap->dmacr, uap, REG_DMACR);
708 uap->im &= ~UART011_TXIM;
709 pl011_write(uap->im, uap, REG_IMSC);
710 return true;
711 }
712
713 /*
714 * We don't have a TX buffer queued, so try to queue one.
715 * If we successfully queued a buffer, mask the TX IRQ.
716 */
717 if (pl011_dma_tx_refill(uap) > 0) {
718 uap->im &= ~UART011_TXIM;
719 pl011_write(uap->im, uap, REG_IMSC);
720 return true;
721 }
722 return false;
723}
724
725/*
726 * Stop the DMA transmit (eg, due to received XOFF).
727 * Locking: called with port lock held and IRQs disabled.
728 */
729static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
730{
731 if (uap->dmatx.queued) {
732 uap->dmacr &= ~UART011_TXDMAE;
733 pl011_write(uap->dmacr, uap, REG_DMACR);
734 }
735}
736
737/*
738 * Try to start a DMA transmit, or in the case of an XON/OFF
739 * character queued for send, try to get that character out ASAP.
740 * Locking: called with port lock held and IRQs disabled.
741 * Returns:
742 * false if we want the TX IRQ to be enabled
743 * true if we have a buffer queued
744 */
745static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
746{
747 u16 dmacr;
748
749 if (!uap->using_tx_dma)
750 return false;
751
752 if (!uap->port.x_char) {
753 /* no X-char, try to push chars out in DMA mode */
754 bool ret = true;
755
756 if (!uap->dmatx.queued) {
757 if (pl011_dma_tx_refill(uap) > 0) {
758 uap->im &= ~UART011_TXIM;
759 pl011_write(uap->im, uap, REG_IMSC);
760 } else
761 ret = false;
762 } else if (!(uap->dmacr & UART011_TXDMAE)) {
763 uap->dmacr |= UART011_TXDMAE;
764 pl011_write(uap->dmacr, uap, REG_DMACR);
765 }
766 return ret;
767 }
768
769 /*
770 * We have an X-char to send. Disable DMA to prevent it loading
771 * the TX fifo, and then see if we can stuff it into the FIFO.
772 */
773 dmacr = uap->dmacr;
774 uap->dmacr &= ~UART011_TXDMAE;
775 pl011_write(uap->dmacr, uap, REG_DMACR);
776
777 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
778 /*
779 * No space in the FIFO, so enable the transmit interrupt
780 * so we know when there is space. Note that once we've
781 * loaded the character, we should just re-enable DMA.
782 */
783 return false;
784 }
785
786 pl011_write(uap->port.x_char, uap, REG_DR);
787 uap->port.icount.tx++;
788 uap->port.x_char = 0;
789
790 /* Success - restore the DMA state */
791 uap->dmacr = dmacr;
792 pl011_write(dmacr, uap, REG_DMACR);
793
794 return true;
795}
796
797/*
798 * Flush the transmit buffer.
799 * Locking: called with port lock held and IRQs disabled.
800 */
801static void pl011_dma_flush_buffer(struct uart_port *port)
802__releases(&uap->port.lock)
803__acquires(&uap->port.lock)
804{
805 struct uart_amba_port *uap =
806 container_of(port, struct uart_amba_port, port);
807
808 if (!uap->using_tx_dma)
809 return;
810
811 dmaengine_terminate_async(uap->dmatx.chan);
812
813 if (uap->dmatx.queued) {
814 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
815 DMA_TO_DEVICE);
816 uap->dmatx.queued = false;
817 uap->dmacr &= ~UART011_TXDMAE;
818 pl011_write(uap->dmacr, uap, REG_DMACR);
819 }
820}
821
822static void pl011_dma_rx_callback(void *data);
823
824static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
825{
826 struct dma_chan *rxchan = uap->dmarx.chan;
827 struct pl011_dmarx_data *dmarx = &uap->dmarx;
828 struct dma_async_tx_descriptor *desc;
829 struct pl011_sgbuf *sgbuf;
830
831 if (!rxchan)
832 return -EIO;
833
834 /* Start the RX DMA job */
835 sgbuf = uap->dmarx.use_buf_b ?
836 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
837 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
838 DMA_DEV_TO_MEM,
839 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
840 /*
841 * If the DMA engine is busy and cannot prepare a
842 * channel, no big deal, the driver will fall back
843 * to interrupt mode as a result of this error code.
844 */
845 if (!desc) {
846 uap->dmarx.running = false;
847 dmaengine_terminate_all(rxchan);
848 return -EBUSY;
849 }
850
851 /* Some data to go along to the callback */
852 desc->callback = pl011_dma_rx_callback;
853 desc->callback_param = uap;
854 dmarx->cookie = dmaengine_submit(desc);
855 dma_async_issue_pending(rxchan);
856
857 uap->dmacr |= UART011_RXDMAE;
858 pl011_write(uap->dmacr, uap, REG_DMACR);
859 uap->dmarx.running = true;
860
861 uap->im &= ~UART011_RXIM;
862 pl011_write(uap->im, uap, REG_IMSC);
863
864 return 0;
865}
866
867/*
868 * This is called when either the DMA job is complete, or
869 * the FIFO timeout interrupt occurred. This must be called
870 * with the port spinlock uap->port.lock held.
871 */
872static void pl011_dma_rx_chars(struct uart_amba_port *uap,
873 u32 pending, bool use_buf_b,
874 bool readfifo)
875{
876 struct tty_port *port = &uap->port.state->port;
877 struct pl011_sgbuf *sgbuf = use_buf_b ?
878 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
879 int dma_count = 0;
880 u32 fifotaken = 0; /* only used for vdbg() */
881
882 struct pl011_dmarx_data *dmarx = &uap->dmarx;
883 int dmataken = 0;
884
885 if (uap->dmarx.poll_rate) {
886 /* The data can be taken by polling */
887 dmataken = sgbuf->sg.length - dmarx->last_residue;
888 /* Recalculate the pending size */
889 if (pending >= dmataken)
890 pending -= dmataken;
891 }
892
893 /* Pick the remain data from the DMA */
894 if (pending) {
895
896 /*
897 * First take all chars in the DMA pipe, then look in the FIFO.
898 * Note that tty_insert_flip_buf() tries to take as many chars
899 * as it can.
900 */
901 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
902 pending);
903
904 uap->port.icount.rx += dma_count;
905 if (dma_count < pending)
906 dev_warn(uap->port.dev,
907 "couldn't insert all characters (TTY is full?)\n");
908 }
909
910 /* Reset the last_residue for Rx DMA poll */
911 if (uap->dmarx.poll_rate)
912 dmarx->last_residue = sgbuf->sg.length;
913
914 /*
915 * Only continue with trying to read the FIFO if all DMA chars have
916 * been taken first.
917 */
918 if (dma_count == pending && readfifo) {
919 /* Clear any error flags */
920 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
921 UART011_FEIS, uap, REG_ICR);
922
923 /*
924 * If we read all the DMA'd characters, and we had an
925 * incomplete buffer, that could be due to an rx error, or
926 * maybe we just timed out. Read any pending chars and check
927 * the error status.
928 *
929 * Error conditions will only occur in the FIFO, these will
930 * trigger an immediate interrupt and stop the DMA job, so we
931 * will always find the error in the FIFO, never in the DMA
932 * buffer.
933 */
934 fifotaken = pl011_fifo_to_tty(uap);
935 }
936
937 spin_unlock(&uap->port.lock);
938 dev_vdbg(uap->port.dev,
939 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
940 dma_count, fifotaken);
941 tty_flip_buffer_push(port);
942 spin_lock(&uap->port.lock);
943}
944
945static void pl011_dma_rx_irq(struct uart_amba_port *uap)
946{
947 struct pl011_dmarx_data *dmarx = &uap->dmarx;
948 struct dma_chan *rxchan = dmarx->chan;
949 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
950 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
951 size_t pending;
952 struct dma_tx_state state;
953 enum dma_status dmastat;
954
955 /*
956 * Pause the transfer so we can trust the current counter,
957 * do this before we pause the PL011 block, else we may
958 * overflow the FIFO.
959 */
960 if (dmaengine_pause(rxchan))
961 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
962 dmastat = rxchan->device->device_tx_status(rxchan,
963 dmarx->cookie, &state);
964 if (dmastat != DMA_PAUSED)
965 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
966
967 /* Disable RX DMA - incoming data will wait in the FIFO */
968 uap->dmacr &= ~UART011_RXDMAE;
969 pl011_write(uap->dmacr, uap, REG_DMACR);
970 uap->dmarx.running = false;
971
972 pending = sgbuf->sg.length - state.residue;
973 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
974 /* Then we terminate the transfer - we now know our residue */
975 dmaengine_terminate_all(rxchan);
976
977 /*
978 * This will take the chars we have so far and insert
979 * into the framework.
980 */
981 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
982
983 /* Switch buffer & re-trigger DMA job */
984 dmarx->use_buf_b = !dmarx->use_buf_b;
985 if (pl011_dma_rx_trigger_dma(uap)) {
986 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
987 "fall back to interrupt mode\n");
988 uap->im |= UART011_RXIM;
989 pl011_write(uap->im, uap, REG_IMSC);
990 }
991}
992
993static void pl011_dma_rx_callback(void *data)
994{
995 struct uart_amba_port *uap = data;
996 struct pl011_dmarx_data *dmarx = &uap->dmarx;
997 struct dma_chan *rxchan = dmarx->chan;
998 bool lastbuf = dmarx->use_buf_b;
999 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1000 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1001 size_t pending;
1002 struct dma_tx_state state;
1003 int ret;
1004
1005 /*
1006 * This completion interrupt occurs typically when the
1007 * RX buffer is totally stuffed but no timeout has yet
1008 * occurred. When that happens, we just want the RX
1009 * routine to flush out the secondary DMA buffer while
1010 * we immediately trigger the next DMA job.
1011 */
1012 spin_lock_irq(&uap->port.lock);
1013 /*
1014 * Rx data can be taken by the UART interrupts during
1015 * the DMA irq handler. So we check the residue here.
1016 */
1017 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1018 pending = sgbuf->sg.length - state.residue;
1019 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1020 /* Then we terminate the transfer - we now know our residue */
1021 dmaengine_terminate_all(rxchan);
1022
1023 uap->dmarx.running = false;
1024 dmarx->use_buf_b = !lastbuf;
1025 ret = pl011_dma_rx_trigger_dma(uap);
1026
1027 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1028 spin_unlock_irq(&uap->port.lock);
1029 /*
1030 * Do this check after we picked the DMA chars so we don't
1031 * get some IRQ immediately from RX.
1032 */
1033 if (ret) {
1034 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1035 "fall back to interrupt mode\n");
1036 uap->im |= UART011_RXIM;
1037 pl011_write(uap->im, uap, REG_IMSC);
1038 }
1039}
1040
1041/*
1042 * Stop accepting received characters, when we're shutting down or
1043 * suspending this port.
1044 * Locking: called with port lock held and IRQs disabled.
1045 */
1046static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1047{
1048 /* FIXME. Just disable the DMA enable */
1049 uap->dmacr &= ~UART011_RXDMAE;
1050 pl011_write(uap->dmacr, uap, REG_DMACR);
1051}
1052
1053/*
1054 * Timer handler for Rx DMA polling.
1055 * Every polling, It checks the residue in the dma buffer and transfer
1056 * data to the tty. Also, last_residue is updated for the next polling.
1057 */
1058static void pl011_dma_rx_poll(struct timer_list *t)
1059{
1060 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1061 struct tty_port *port = &uap->port.state->port;
1062 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1063 struct dma_chan *rxchan = uap->dmarx.chan;
1064 unsigned long flags = 0;
1065 unsigned int dmataken = 0;
1066 unsigned int size = 0;
1067 struct pl011_sgbuf *sgbuf;
1068 int dma_count;
1069 struct dma_tx_state state;
1070
1071 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1072 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1073 if (likely(state.residue < dmarx->last_residue)) {
1074 dmataken = sgbuf->sg.length - dmarx->last_residue;
1075 size = dmarx->last_residue - state.residue;
1076 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1077 size);
1078 if (dma_count == size)
1079 dmarx->last_residue = state.residue;
1080 dmarx->last_jiffies = jiffies;
1081 }
1082 tty_flip_buffer_push(port);
1083
1084 /*
1085 * If no data is received in poll_timeout, the driver will fall back
1086 * to interrupt mode. We will retrigger DMA at the first interrupt.
1087 */
1088 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1089 > uap->dmarx.poll_timeout) {
1090
1091 spin_lock_irqsave(&uap->port.lock, flags);
1092 pl011_dma_rx_stop(uap);
1093 uap->im |= UART011_RXIM;
1094 pl011_write(uap->im, uap, REG_IMSC);
1095 spin_unlock_irqrestore(&uap->port.lock, flags);
1096
1097 uap->dmarx.running = false;
1098 dmaengine_terminate_all(rxchan);
1099 del_timer(&uap->dmarx.timer);
1100 } else {
1101 mod_timer(&uap->dmarx.timer,
1102 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1103 }
1104}
1105
1106static void pl011_dma_startup(struct uart_amba_port *uap)
1107{
1108 int ret;
1109
1110 if (!uap->dma_probed)
1111 pl011_dma_probe(uap);
1112
1113 if (!uap->dmatx.chan)
1114 return;
1115
1116 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1117 if (!uap->dmatx.buf) {
1118 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1119 uap->port.fifosize = uap->fifosize;
1120 return;
1121 }
1122
1123 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1124
1125 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1126 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1127 uap->using_tx_dma = true;
1128
1129 if (!uap->dmarx.chan)
1130 goto skip_rx;
1131
1132 /* Allocate and map DMA RX buffers */
1133 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1134 DMA_FROM_DEVICE);
1135 if (ret) {
1136 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1137 "RX buffer A", ret);
1138 goto skip_rx;
1139 }
1140
1141 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1142 DMA_FROM_DEVICE);
1143 if (ret) {
1144 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1145 "RX buffer B", ret);
1146 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1147 DMA_FROM_DEVICE);
1148 goto skip_rx;
1149 }
1150
1151 uap->using_rx_dma = true;
1152
1153skip_rx:
1154 /* Turn on DMA error (RX/TX will be enabled on demand) */
1155 uap->dmacr |= UART011_DMAONERR;
1156 pl011_write(uap->dmacr, uap, REG_DMACR);
1157
1158 /*
1159 * ST Micro variants has some specific dma burst threshold
1160 * compensation. Set this to 16 bytes, so burst will only
1161 * be issued above/below 16 bytes.
1162 */
1163 if (uap->vendor->dma_threshold)
1164 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1165 uap, REG_ST_DMAWM);
1166
1167 if (uap->using_rx_dma) {
1168 if (pl011_dma_rx_trigger_dma(uap))
1169 dev_dbg(uap->port.dev, "could not trigger initial "
1170 "RX DMA job, fall back to interrupt mode\n");
1171 if (uap->dmarx.poll_rate) {
1172 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1173 mod_timer(&uap->dmarx.timer,
1174 jiffies +
1175 msecs_to_jiffies(uap->dmarx.poll_rate));
1176 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1177 uap->dmarx.last_jiffies = jiffies;
1178 }
1179 }
1180}
1181
1182static void pl011_dma_shutdown(struct uart_amba_port *uap)
1183{
1184 if (!(uap->using_tx_dma || uap->using_rx_dma))
1185 return;
1186
1187 /* Disable RX and TX DMA */
1188 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1189 cpu_relax();
1190
1191 spin_lock_irq(&uap->port.lock);
1192 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1193 pl011_write(uap->dmacr, uap, REG_DMACR);
1194 spin_unlock_irq(&uap->port.lock);
1195
1196 if (uap->using_tx_dma) {
1197 /* In theory, this should already be done by pl011_dma_flush_buffer */
1198 dmaengine_terminate_all(uap->dmatx.chan);
1199 if (uap->dmatx.queued) {
1200 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1201 DMA_TO_DEVICE);
1202 uap->dmatx.queued = false;
1203 }
1204
1205 kfree(uap->dmatx.buf);
1206 uap->using_tx_dma = false;
1207 }
1208
1209 if (uap->using_rx_dma) {
1210 dmaengine_terminate_all(uap->dmarx.chan);
1211 /* Clean up the RX DMA */
1212 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1213 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1214 if (uap->dmarx.poll_rate)
1215 del_timer_sync(&uap->dmarx.timer);
1216 uap->using_rx_dma = false;
1217 }
1218}
1219
1220static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1221{
1222 return uap->using_rx_dma;
1223}
1224
1225static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1226{
1227 return uap->using_rx_dma && uap->dmarx.running;
1228}
1229
1230#else
1231/* Blank functions if the DMA engine is not available */
1232static inline void pl011_dma_remove(struct uart_amba_port *uap)
1233{
1234}
1235
1236static inline void pl011_dma_startup(struct uart_amba_port *uap)
1237{
1238}
1239
1240static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1241{
1242}
1243
1244static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1245{
1246 return false;
1247}
1248
1249static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1250{
1251}
1252
1253static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1254{
1255 return false;
1256}
1257
1258static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1259{
1260}
1261
1262static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1263{
1264}
1265
1266static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1267{
1268 return -EIO;
1269}
1270
1271static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1272{
1273 return false;
1274}
1275
1276static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1277{
1278 return false;
1279}
1280
1281#define pl011_dma_flush_buffer NULL
1282#endif
1283
1284static void pl011_stop_tx(struct uart_port *port)
1285{
1286 struct uart_amba_port *uap =
1287 container_of(port, struct uart_amba_port, port);
1288
1289 uap->im &= ~UART011_TXIM;
1290 pl011_write(uap->im, uap, REG_IMSC);
1291 pl011_dma_tx_stop(uap);
1292}
1293
1294static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1295
1296/* Start TX with programmed I/O only (no DMA) */
1297static void pl011_start_tx_pio(struct uart_amba_port *uap)
1298{
1299 if (pl011_tx_chars(uap, false)) {
1300 uap->im |= UART011_TXIM;
1301 pl011_write(uap->im, uap, REG_IMSC);
1302 }
1303}
1304
1305static void pl011_start_tx(struct uart_port *port)
1306{
1307 struct uart_amba_port *uap =
1308 container_of(port, struct uart_amba_port, port);
1309
1310 if (!pl011_dma_tx_start(uap))
1311 pl011_start_tx_pio(uap);
1312}
1313
1314static void pl011_stop_rx(struct uart_port *port)
1315{
1316 struct uart_amba_port *uap =
1317 container_of(port, struct uart_amba_port, port);
1318
1319 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1320 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1321 pl011_write(uap->im, uap, REG_IMSC);
1322
1323 pl011_dma_rx_stop(uap);
1324}
1325
1326static void pl011_enable_ms(struct uart_port *port)
1327{
1328 struct uart_amba_port *uap =
1329 container_of(port, struct uart_amba_port, port);
1330
1331 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1332 pl011_write(uap->im, uap, REG_IMSC);
1333}
1334
1335static void pl011_rx_chars(struct uart_amba_port *uap)
1336__releases(&uap->port.lock)
1337__acquires(&uap->port.lock)
1338{
1339 pl011_fifo_to_tty(uap);
1340
1341 spin_unlock(&uap->port.lock);
1342 tty_flip_buffer_push(&uap->port.state->port);
1343 /*
1344 * If we were temporarily out of DMA mode for a while,
1345 * attempt to switch back to DMA mode again.
1346 */
1347 if (pl011_dma_rx_available(uap)) {
1348 if (pl011_dma_rx_trigger_dma(uap)) {
1349 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1350 "fall back to interrupt mode again\n");
1351 uap->im |= UART011_RXIM;
1352 pl011_write(uap->im, uap, REG_IMSC);
1353 } else {
1354#ifdef CONFIG_DMA_ENGINE
1355 /* Start Rx DMA poll */
1356 if (uap->dmarx.poll_rate) {
1357 uap->dmarx.last_jiffies = jiffies;
1358 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1359 mod_timer(&uap->dmarx.timer,
1360 jiffies +
1361 msecs_to_jiffies(uap->dmarx.poll_rate));
1362 }
1363#endif
1364 }
1365 }
1366 spin_lock(&uap->port.lock);
1367}
1368
1369static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1370 bool from_irq)
1371{
1372 if (unlikely(!from_irq) &&
1373 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1374 return false; /* unable to transmit character */
1375
1376 pl011_write(c, uap, REG_DR);
1377 uap->port.icount.tx++;
1378
1379 return true;
1380}
1381
1382/* Returns true if tx interrupts have to be (kept) enabled */
1383static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1384{
1385 struct circ_buf *xmit = &uap->port.state->xmit;
1386 int count = uap->fifosize >> 1;
1387
1388 if (uap->port.x_char) {
1389 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1390 return true;
1391 uap->port.x_char = 0;
1392 --count;
1393 }
1394 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1395 pl011_stop_tx(&uap->port);
1396 return false;
1397 }
1398
1399 /* If we are using DMA mode, try to send some characters. */
1400 if (pl011_dma_tx_irq(uap))
1401 return true;
1402
1403 do {
1404 if (likely(from_irq) && count-- == 0)
1405 break;
1406
1407 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1408 break;
1409
1410 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1411 } while (!uart_circ_empty(xmit));
1412
1413 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1414 uart_write_wakeup(&uap->port);
1415
1416 if (uart_circ_empty(xmit)) {
1417 pl011_stop_tx(&uap->port);
1418 return false;
1419 }
1420 return true;
1421}
1422
1423static void pl011_modem_status(struct uart_amba_port *uap)
1424{
1425 unsigned int status, delta;
1426
1427 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1428
1429 delta = status ^ uap->old_status;
1430 uap->old_status = status;
1431
1432 if (!delta)
1433 return;
1434
1435 if (delta & UART01x_FR_DCD)
1436 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1437
1438 if (delta & uap->vendor->fr_dsr)
1439 uap->port.icount.dsr++;
1440
1441 if (delta & uap->vendor->fr_cts)
1442 uart_handle_cts_change(&uap->port,
1443 status & uap->vendor->fr_cts);
1444
1445 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1446}
1447
1448static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1449{
1450 if (!uap->vendor->cts_event_workaround)
1451 return;
1452
1453 /* workaround to make sure that all bits are unlocked.. */
1454 pl011_write(0x00, uap, REG_ICR);
1455
1456 /*
1457 * WA: introduce 26ns(1 uart clk) delay before W1C;
1458 * single apb access will incur 2 pclk(133.12Mhz) delay,
1459 * so add 2 dummy reads
1460 */
1461 pl011_read(uap, REG_ICR);
1462 pl011_read(uap, REG_ICR);
1463}
1464
1465static irqreturn_t pl011_int(int irq, void *dev_id)
1466{
1467 struct uart_amba_port *uap = dev_id;
1468 unsigned long flags;
1469 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1470 int handled = 0;
1471
1472 spin_lock_irqsave(&uap->port.lock, flags);
1473 status = pl011_read(uap, REG_RIS) & uap->im;
1474 if (status) {
1475 do {
1476 check_apply_cts_event_workaround(uap);
1477
1478 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1479 UART011_RXIS),
1480 uap, REG_ICR);
1481
1482 if (status & (UART011_RTIS|UART011_RXIS)) {
1483 if (pl011_dma_rx_running(uap))
1484 pl011_dma_rx_irq(uap);
1485 else
1486 pl011_rx_chars(uap);
1487 }
1488 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1489 UART011_CTSMIS|UART011_RIMIS))
1490 pl011_modem_status(uap);
1491 if (status & UART011_TXIS)
1492 pl011_tx_chars(uap, true);
1493
1494 if (pass_counter-- == 0)
1495 break;
1496
1497 status = pl011_read(uap, REG_RIS) & uap->im;
1498 } while (status != 0);
1499 handled = 1;
1500 }
1501
1502 spin_unlock_irqrestore(&uap->port.lock, flags);
1503
1504 return IRQ_RETVAL(handled);
1505}
1506
1507static unsigned int pl011_tx_empty(struct uart_port *port)
1508{
1509 struct uart_amba_port *uap =
1510 container_of(port, struct uart_amba_port, port);
1511
1512 /* Allow feature register bits to be inverted to work around errata */
1513 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1514
1515 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1516 0 : TIOCSER_TEMT;
1517}
1518
1519static unsigned int pl011_get_mctrl(struct uart_port *port)
1520{
1521 struct uart_amba_port *uap =
1522 container_of(port, struct uart_amba_port, port);
1523 unsigned int result = 0;
1524 unsigned int status = pl011_read(uap, REG_FR);
1525
1526#define TIOCMBIT(uartbit, tiocmbit) \
1527 if (status & uartbit) \
1528 result |= tiocmbit
1529
1530 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1531 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1532 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1533 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1534#undef TIOCMBIT
1535 return result;
1536}
1537
1538static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1539{
1540 struct uart_amba_port *uap =
1541 container_of(port, struct uart_amba_port, port);
1542 unsigned int cr;
1543
1544 cr = pl011_read(uap, REG_CR);
1545
1546#define TIOCMBIT(tiocmbit, uartbit) \
1547 if (mctrl & tiocmbit) \
1548 cr |= uartbit; \
1549 else \
1550 cr &= ~uartbit
1551
1552 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1553 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1554 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1555 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1556 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1557
1558 if (port->status & UPSTAT_AUTORTS) {
1559 /* We need to disable auto-RTS if we want to turn RTS off */
1560 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1561 }
1562#undef TIOCMBIT
1563
1564 pl011_write(cr, uap, REG_CR);
1565}
1566
1567static void pl011_break_ctl(struct uart_port *port, int break_state)
1568{
1569 struct uart_amba_port *uap =
1570 container_of(port, struct uart_amba_port, port);
1571 unsigned long flags;
1572 unsigned int lcr_h;
1573
1574 spin_lock_irqsave(&uap->port.lock, flags);
1575 lcr_h = pl011_read(uap, REG_LCRH_TX);
1576 if (break_state == -1)
1577 lcr_h |= UART01x_LCRH_BRK;
1578 else
1579 lcr_h &= ~UART01x_LCRH_BRK;
1580 pl011_write(lcr_h, uap, REG_LCRH_TX);
1581 spin_unlock_irqrestore(&uap->port.lock, flags);
1582}
1583
1584#ifdef CONFIG_CONSOLE_POLL
1585
1586static void pl011_quiesce_irqs(struct uart_port *port)
1587{
1588 struct uart_amba_port *uap =
1589 container_of(port, struct uart_amba_port, port);
1590
1591 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1592 /*
1593 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1594 * we simply mask it. start_tx() will unmask it.
1595 *
1596 * Note we can race with start_tx(), and if the race happens, the
1597 * polling user might get another interrupt just after we clear it.
1598 * But it should be OK and can happen even w/o the race, e.g.
1599 * controller immediately got some new data and raised the IRQ.
1600 *
1601 * And whoever uses polling routines assumes that it manages the device
1602 * (including tx queue), so we're also fine with start_tx()'s caller
1603 * side.
1604 */
1605 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1606 REG_IMSC);
1607}
1608
1609static int pl011_get_poll_char(struct uart_port *port)
1610{
1611 struct uart_amba_port *uap =
1612 container_of(port, struct uart_amba_port, port);
1613 unsigned int status;
1614
1615 /*
1616 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1617 * debugger.
1618 */
1619 pl011_quiesce_irqs(port);
1620
1621 status = pl011_read(uap, REG_FR);
1622 if (status & UART01x_FR_RXFE)
1623 return NO_POLL_CHAR;
1624
1625 return pl011_read(uap, REG_DR);
1626}
1627
1628static void pl011_put_poll_char(struct uart_port *port,
1629 unsigned char ch)
1630{
1631 struct uart_amba_port *uap =
1632 container_of(port, struct uart_amba_port, port);
1633
1634 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1635 cpu_relax();
1636
1637 pl011_write(ch, uap, REG_DR);
1638}
1639
1640#endif /* CONFIG_CONSOLE_POLL */
1641
1642static int pl011_hwinit(struct uart_port *port)
1643{
1644 struct uart_amba_port *uap =
1645 container_of(port, struct uart_amba_port, port);
1646 int retval;
1647
1648 /* Optionaly enable pins to be muxed in and configured */
1649 pinctrl_pm_select_default_state(port->dev);
1650
1651 /*
1652 * Try to enable the clock producer.
1653 */
1654 retval = clk_prepare_enable(uap->clk);
1655 if (retval)
1656 return retval;
1657
1658 uap->port.uartclk = clk_get_rate(uap->clk);
1659
1660 /* Clear pending error and receive interrupts */
1661 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1662 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1663 uap, REG_ICR);
1664
1665 /*
1666 * Save interrupts enable mask, and enable RX interrupts in case if
1667 * the interrupt is used for NMI entry.
1668 */
1669 uap->im = pl011_read(uap, REG_IMSC);
1670 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1671
1672 if (dev_get_platdata(uap->port.dev)) {
1673 struct amba_pl011_data *plat;
1674
1675 plat = dev_get_platdata(uap->port.dev);
1676 if (plat->init)
1677 plat->init();
1678 }
1679 return 0;
1680}
1681
1682static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1683{
1684 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1685 pl011_reg_to_offset(uap, REG_LCRH_TX);
1686}
1687
1688static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1689{
1690 pl011_write(lcr_h, uap, REG_LCRH_RX);
1691 if (pl011_split_lcrh(uap)) {
1692 int i;
1693 /*
1694 * Wait 10 PCLKs before writing LCRH_TX register,
1695 * to get this delay write read only register 10 times
1696 */
1697 for (i = 0; i < 10; ++i)
1698 pl011_write(0xff, uap, REG_MIS);
1699 pl011_write(lcr_h, uap, REG_LCRH_TX);
1700 }
1701}
1702
1703static int pl011_allocate_irq(struct uart_amba_port *uap)
1704{
1705 pl011_write(uap->im, uap, REG_IMSC);
1706
1707 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1708}
1709
1710/*
1711 * Enable interrupts, only timeouts when using DMA
1712 * if initial RX DMA job failed, start in interrupt mode
1713 * as well.
1714 */
1715static void pl011_enable_interrupts(struct uart_amba_port *uap)
1716{
1717 unsigned int i;
1718
1719 spin_lock_irq(&uap->port.lock);
1720
1721 /* Clear out any spuriously appearing RX interrupts */
1722 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1723
1724 /*
1725 * RXIS is asserted only when the RX FIFO transitions from below
1726 * to above the trigger threshold. If the RX FIFO is already
1727 * full to the threshold this can't happen and RXIS will now be
1728 * stuck off. Drain the RX FIFO explicitly to fix this:
1729 */
1730 for (i = 0; i < uap->fifosize * 2; ++i) {
1731 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1732 break;
1733
1734 pl011_read(uap, REG_DR);
1735 }
1736
1737 uap->im = UART011_RTIM;
1738 if (!pl011_dma_rx_running(uap))
1739 uap->im |= UART011_RXIM;
1740 pl011_write(uap->im, uap, REG_IMSC);
1741 spin_unlock_irq(&uap->port.lock);
1742}
1743
1744static int pl011_startup(struct uart_port *port)
1745{
1746 struct uart_amba_port *uap =
1747 container_of(port, struct uart_amba_port, port);
1748 unsigned int cr;
1749 int retval;
1750
1751 retval = pl011_hwinit(port);
1752 if (retval)
1753 goto clk_dis;
1754
1755 retval = pl011_allocate_irq(uap);
1756 if (retval)
1757 goto clk_dis;
1758
1759 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1760
1761 spin_lock_irq(&uap->port.lock);
1762
1763 /* restore RTS and DTR */
1764 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1765 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1766 pl011_write(cr, uap, REG_CR);
1767
1768 spin_unlock_irq(&uap->port.lock);
1769
1770 /*
1771 * initialise the old status of the modem signals
1772 */
1773 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1774
1775 /* Startup DMA */
1776 pl011_dma_startup(uap);
1777
1778 pl011_enable_interrupts(uap);
1779
1780 return 0;
1781
1782 clk_dis:
1783 clk_disable_unprepare(uap->clk);
1784 return retval;
1785}
1786
1787static int sbsa_uart_startup(struct uart_port *port)
1788{
1789 struct uart_amba_port *uap =
1790 container_of(port, struct uart_amba_port, port);
1791 int retval;
1792
1793 retval = pl011_hwinit(port);
1794 if (retval)
1795 return retval;
1796
1797 retval = pl011_allocate_irq(uap);
1798 if (retval)
1799 return retval;
1800
1801 /* The SBSA UART does not support any modem status lines. */
1802 uap->old_status = 0;
1803
1804 pl011_enable_interrupts(uap);
1805
1806 return 0;
1807}
1808
1809static void pl011_shutdown_channel(struct uart_amba_port *uap,
1810 unsigned int lcrh)
1811{
1812 unsigned long val;
1813
1814 val = pl011_read(uap, lcrh);
1815 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1816 pl011_write(val, uap, lcrh);
1817}
1818
1819/*
1820 * disable the port. It should not disable RTS and DTR.
1821 * Also RTS and DTR state should be preserved to restore
1822 * it during startup().
1823 */
1824static void pl011_disable_uart(struct uart_amba_port *uap)
1825{
1826 unsigned int cr;
1827
1828 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1829 spin_lock_irq(&uap->port.lock);
1830 cr = pl011_read(uap, REG_CR);
1831 uap->old_cr = cr;
1832 cr &= UART011_CR_RTS | UART011_CR_DTR;
1833 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1834 pl011_write(cr, uap, REG_CR);
1835 spin_unlock_irq(&uap->port.lock);
1836
1837 /*
1838 * disable break condition and fifos
1839 */
1840 pl011_shutdown_channel(uap, REG_LCRH_RX);
1841 if (pl011_split_lcrh(uap))
1842 pl011_shutdown_channel(uap, REG_LCRH_TX);
1843}
1844
1845static void pl011_disable_interrupts(struct uart_amba_port *uap)
1846{
1847 spin_lock_irq(&uap->port.lock);
1848
1849 /* mask all interrupts and clear all pending ones */
1850 uap->im = 0;
1851 pl011_write(uap->im, uap, REG_IMSC);
1852 pl011_write(0xffff, uap, REG_ICR);
1853
1854 spin_unlock_irq(&uap->port.lock);
1855}
1856
1857static void pl011_shutdown(struct uart_port *port)
1858{
1859 struct uart_amba_port *uap =
1860 container_of(port, struct uart_amba_port, port);
1861
1862 pl011_disable_interrupts(uap);
1863
1864 pl011_dma_shutdown(uap);
1865
1866 free_irq(uap->port.irq, uap);
1867
1868 pl011_disable_uart(uap);
1869
1870 /*
1871 * Shut down the clock producer
1872 */
1873 clk_disable_unprepare(uap->clk);
1874 /* Optionally let pins go into sleep states */
1875 pinctrl_pm_select_sleep_state(port->dev);
1876
1877 if (dev_get_platdata(uap->port.dev)) {
1878 struct amba_pl011_data *plat;
1879
1880 plat = dev_get_platdata(uap->port.dev);
1881 if (plat->exit)
1882 plat->exit();
1883 }
1884
1885 if (uap->port.ops->flush_buffer)
1886 uap->port.ops->flush_buffer(port);
1887}
1888
1889static void sbsa_uart_shutdown(struct uart_port *port)
1890{
1891 struct uart_amba_port *uap =
1892 container_of(port, struct uart_amba_port, port);
1893
1894 pl011_disable_interrupts(uap);
1895
1896 free_irq(uap->port.irq, uap);
1897
1898 if (uap->port.ops->flush_buffer)
1899 uap->port.ops->flush_buffer(port);
1900}
1901
1902static void
1903pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1904{
1905 port->read_status_mask = UART011_DR_OE | 255;
1906 if (termios->c_iflag & INPCK)
1907 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1908 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1909 port->read_status_mask |= UART011_DR_BE;
1910
1911 /*
1912 * Characters to ignore
1913 */
1914 port->ignore_status_mask = 0;
1915 if (termios->c_iflag & IGNPAR)
1916 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1917 if (termios->c_iflag & IGNBRK) {
1918 port->ignore_status_mask |= UART011_DR_BE;
1919 /*
1920 * If we're ignoring parity and break indicators,
1921 * ignore overruns too (for real raw support).
1922 */
1923 if (termios->c_iflag & IGNPAR)
1924 port->ignore_status_mask |= UART011_DR_OE;
1925 }
1926
1927 /*
1928 * Ignore all characters if CREAD is not set.
1929 */
1930 if ((termios->c_cflag & CREAD) == 0)
1931 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1932}
1933
1934static void
1935pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1936 struct ktermios *old)
1937{
1938 struct uart_amba_port *uap =
1939 container_of(port, struct uart_amba_port, port);
1940 unsigned int lcr_h, old_cr;
1941 unsigned long flags;
1942 unsigned int baud, quot, clkdiv;
1943
1944 if (uap->vendor->oversampling)
1945 clkdiv = 8;
1946 else
1947 clkdiv = 16;
1948
1949 /*
1950 * Ask the core to calculate the divisor for us.
1951 */
1952 baud = uart_get_baud_rate(port, termios, old, 0,
1953 port->uartclk / clkdiv);
1954#ifdef CONFIG_DMA_ENGINE
1955 /*
1956 * Adjust RX DMA polling rate with baud rate if not specified.
1957 */
1958 if (uap->dmarx.auto_poll_rate)
1959 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1960#endif
1961
1962 if (baud > port->uartclk/16)
1963 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1964 else
1965 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1966
1967 switch (termios->c_cflag & CSIZE) {
1968 case CS5:
1969 lcr_h = UART01x_LCRH_WLEN_5;
1970 break;
1971 case CS6:
1972 lcr_h = UART01x_LCRH_WLEN_6;
1973 break;
1974 case CS7:
1975 lcr_h = UART01x_LCRH_WLEN_7;
1976 break;
1977 default: // CS8
1978 lcr_h = UART01x_LCRH_WLEN_8;
1979 break;
1980 }
1981 if (termios->c_cflag & CSTOPB)
1982 lcr_h |= UART01x_LCRH_STP2;
1983 if (termios->c_cflag & PARENB) {
1984 lcr_h |= UART01x_LCRH_PEN;
1985 if (!(termios->c_cflag & PARODD))
1986 lcr_h |= UART01x_LCRH_EPS;
1987 if (termios->c_cflag & CMSPAR)
1988 lcr_h |= UART011_LCRH_SPS;
1989 }
1990 if (uap->fifosize > 1)
1991 lcr_h |= UART01x_LCRH_FEN;
1992
1993 spin_lock_irqsave(&port->lock, flags);
1994
1995 /*
1996 * Update the per-port timeout.
1997 */
1998 uart_update_timeout(port, termios->c_cflag, baud);
1999
2000 pl011_setup_status_masks(port, termios);
2001
2002 if (UART_ENABLE_MS(port, termios->c_cflag))
2003 pl011_enable_ms(port);
2004
2005 /* first, disable everything */
2006 old_cr = pl011_read(uap, REG_CR);
2007 pl011_write(0, uap, REG_CR);
2008
2009 if (termios->c_cflag & CRTSCTS) {
2010 if (old_cr & UART011_CR_RTS)
2011 old_cr |= UART011_CR_RTSEN;
2012
2013 old_cr |= UART011_CR_CTSEN;
2014 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2015 } else {
2016 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2017 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2018 }
2019
2020 if (uap->vendor->oversampling) {
2021 if (baud > port->uartclk / 16)
2022 old_cr |= ST_UART011_CR_OVSFACT;
2023 else
2024 old_cr &= ~ST_UART011_CR_OVSFACT;
2025 }
2026
2027 /*
2028 * Workaround for the ST Micro oversampling variants to
2029 * increase the bitrate slightly, by lowering the divisor,
2030 * to avoid delayed sampling of start bit at high speeds,
2031 * else we see data corruption.
2032 */
2033 if (uap->vendor->oversampling) {
2034 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2035 quot -= 1;
2036 else if ((baud > 3250000) && (quot > 2))
2037 quot -= 2;
2038 }
2039 /* Set baud rate */
2040 pl011_write(quot & 0x3f, uap, REG_FBRD);
2041 pl011_write(quot >> 6, uap, REG_IBRD);
2042
2043 /*
2044 * ----------v----------v----------v----------v-----
2045 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2046 * REG_FBRD & REG_IBRD.
2047 * ----------^----------^----------^----------^-----
2048 */
2049 pl011_write_lcr_h(uap, lcr_h);
2050 pl011_write(old_cr, uap, REG_CR);
2051
2052 spin_unlock_irqrestore(&port->lock, flags);
2053}
2054
2055static void
2056sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2057 struct ktermios *old)
2058{
2059 struct uart_amba_port *uap =
2060 container_of(port, struct uart_amba_port, port);
2061 unsigned long flags;
2062
2063 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2064
2065 /* The SBSA UART only supports 8n1 without hardware flow control. */
2066 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2067 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2068 termios->c_cflag |= CS8 | CLOCAL;
2069
2070 spin_lock_irqsave(&port->lock, flags);
2071 uart_update_timeout(port, CS8, uap->fixed_baud);
2072 pl011_setup_status_masks(port, termios);
2073 spin_unlock_irqrestore(&port->lock, flags);
2074}
2075
2076static const char *pl011_type(struct uart_port *port)
2077{
2078 struct uart_amba_port *uap =
2079 container_of(port, struct uart_amba_port, port);
2080 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2081}
2082
2083/*
2084 * Release the memory region(s) being used by 'port'
2085 */
2086static void pl011_release_port(struct uart_port *port)
2087{
2088 release_mem_region(port->mapbase, SZ_4K);
2089}
2090
2091/*
2092 * Request the memory region(s) being used by 'port'
2093 */
2094static int pl011_request_port(struct uart_port *port)
2095{
2096 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2097 != NULL ? 0 : -EBUSY;
2098}
2099
2100/*
2101 * Configure/autoconfigure the port.
2102 */
2103static void pl011_config_port(struct uart_port *port, int flags)
2104{
2105 if (flags & UART_CONFIG_TYPE) {
2106 port->type = PORT_AMBA;
2107 pl011_request_port(port);
2108 }
2109}
2110
2111/*
2112 * verify the new serial_struct (for TIOCSSERIAL).
2113 */
2114static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2115{
2116 int ret = 0;
2117 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2118 ret = -EINVAL;
2119 if (ser->irq < 0 || ser->irq >= nr_irqs)
2120 ret = -EINVAL;
2121 if (ser->baud_base < 9600)
2122 ret = -EINVAL;
2123 return ret;
2124}
2125
2126static const struct uart_ops amba_pl011_pops = {
2127 .tx_empty = pl011_tx_empty,
2128 .set_mctrl = pl011_set_mctrl,
2129 .get_mctrl = pl011_get_mctrl,
2130 .stop_tx = pl011_stop_tx,
2131 .start_tx = pl011_start_tx,
2132 .stop_rx = pl011_stop_rx,
2133 .enable_ms = pl011_enable_ms,
2134 .break_ctl = pl011_break_ctl,
2135 .startup = pl011_startup,
2136 .shutdown = pl011_shutdown,
2137 .flush_buffer = pl011_dma_flush_buffer,
2138 .set_termios = pl011_set_termios,
2139 .type = pl011_type,
2140 .release_port = pl011_release_port,
2141 .request_port = pl011_request_port,
2142 .config_port = pl011_config_port,
2143 .verify_port = pl011_verify_port,
2144#ifdef CONFIG_CONSOLE_POLL
2145 .poll_init = pl011_hwinit,
2146 .poll_get_char = pl011_get_poll_char,
2147 .poll_put_char = pl011_put_poll_char,
2148#endif
2149};
2150
2151static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2152{
2153}
2154
2155static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2156{
2157 return 0;
2158}
2159
2160static const struct uart_ops sbsa_uart_pops = {
2161 .tx_empty = pl011_tx_empty,
2162 .set_mctrl = sbsa_uart_set_mctrl,
2163 .get_mctrl = sbsa_uart_get_mctrl,
2164 .stop_tx = pl011_stop_tx,
2165 .start_tx = pl011_start_tx,
2166 .stop_rx = pl011_stop_rx,
2167 .startup = sbsa_uart_startup,
2168 .shutdown = sbsa_uart_shutdown,
2169 .set_termios = sbsa_uart_set_termios,
2170 .type = pl011_type,
2171 .release_port = pl011_release_port,
2172 .request_port = pl011_request_port,
2173 .config_port = pl011_config_port,
2174 .verify_port = pl011_verify_port,
2175#ifdef CONFIG_CONSOLE_POLL
2176 .poll_init = pl011_hwinit,
2177 .poll_get_char = pl011_get_poll_char,
2178 .poll_put_char = pl011_put_poll_char,
2179#endif
2180};
2181
2182static struct uart_amba_port *amba_ports[UART_NR];
2183
2184#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2185
2186static void pl011_console_putchar(struct uart_port *port, int ch)
2187{
2188 struct uart_amba_port *uap =
2189 container_of(port, struct uart_amba_port, port);
2190
2191 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2192 cpu_relax();
2193 pl011_write(ch, uap, REG_DR);
2194}
2195
2196static void
2197pl011_console_write(struct console *co, const char *s, unsigned int count)
2198{
2199 struct uart_amba_port *uap = amba_ports[co->index];
2200 unsigned int old_cr = 0, new_cr;
2201 unsigned long flags;
2202 int locked = 1;
2203
2204 clk_enable(uap->clk);
2205
2206 local_irq_save(flags);
2207 if (uap->port.sysrq)
2208 locked = 0;
2209 else if (oops_in_progress)
2210 locked = spin_trylock(&uap->port.lock);
2211 else
2212 spin_lock(&uap->port.lock);
2213
2214 /*
2215 * First save the CR then disable the interrupts
2216 */
2217 if (!uap->vendor->always_enabled) {
2218 old_cr = pl011_read(uap, REG_CR);
2219 new_cr = old_cr & ~UART011_CR_CTSEN;
2220 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2221 pl011_write(new_cr, uap, REG_CR);
2222 }
2223
2224 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2225
2226 /*
2227 * Finally, wait for transmitter to become empty and restore the
2228 * TCR. Allow feature register bits to be inverted to work around
2229 * errata.
2230 */
2231 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2232 & uap->vendor->fr_busy)
2233 cpu_relax();
2234 if (!uap->vendor->always_enabled)
2235 pl011_write(old_cr, uap, REG_CR);
2236
2237 if (locked)
2238 spin_unlock(&uap->port.lock);
2239 local_irq_restore(flags);
2240
2241 clk_disable(uap->clk);
2242}
2243
2244static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2245 int *parity, int *bits)
2246{
2247 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2248 unsigned int lcr_h, ibrd, fbrd;
2249
2250 lcr_h = pl011_read(uap, REG_LCRH_TX);
2251
2252 *parity = 'n';
2253 if (lcr_h & UART01x_LCRH_PEN) {
2254 if (lcr_h & UART01x_LCRH_EPS)
2255 *parity = 'e';
2256 else
2257 *parity = 'o';
2258 }
2259
2260 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2261 *bits = 7;
2262 else
2263 *bits = 8;
2264
2265 ibrd = pl011_read(uap, REG_IBRD);
2266 fbrd = pl011_read(uap, REG_FBRD);
2267
2268 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2269
2270 if (uap->vendor->oversampling) {
2271 if (pl011_read(uap, REG_CR)
2272 & ST_UART011_CR_OVSFACT)
2273 *baud *= 2;
2274 }
2275 }
2276}
2277
2278static int pl011_console_setup(struct console *co, char *options)
2279{
2280 struct uart_amba_port *uap;
2281 int baud = 38400;
2282 int bits = 8;
2283 int parity = 'n';
2284 int flow = 'n';
2285 int ret;
2286
2287 /*
2288 * Check whether an invalid uart number has been specified, and
2289 * if so, search for the first available port that does have
2290 * console support.
2291 */
2292 if (co->index >= UART_NR)
2293 co->index = 0;
2294 uap = amba_ports[co->index];
2295 if (!uap)
2296 return -ENODEV;
2297
2298 /* Allow pins to be muxed in and configured */
2299 pinctrl_pm_select_default_state(uap->port.dev);
2300
2301 ret = clk_prepare(uap->clk);
2302 if (ret)
2303 return ret;
2304
2305 if (dev_get_platdata(uap->port.dev)) {
2306 struct amba_pl011_data *plat;
2307
2308 plat = dev_get_platdata(uap->port.dev);
2309 if (plat->init)
2310 plat->init();
2311 }
2312
2313 uap->port.uartclk = clk_get_rate(uap->clk);
2314
2315 if (uap->vendor->fixed_options) {
2316 baud = uap->fixed_baud;
2317 } else {
2318 if (options)
2319 uart_parse_options(options,
2320 &baud, &parity, &bits, &flow);
2321 else
2322 pl011_console_get_options(uap, &baud, &parity, &bits);
2323 }
2324
2325 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2326}
2327
2328/**
2329 * pl011_console_match - non-standard console matching
2330 * @co: registering console
2331 * @name: name from console command line
2332 * @idx: index from console command line
2333 * @options: ptr to option string from console command line
2334 *
2335 * Only attempts to match console command lines of the form:
2336 * console=pl011,mmio|mmio32,<addr>[,<options>]
2337 * console=pl011,0x<addr>[,<options>]
2338 * This form is used to register an initial earlycon boot console and
2339 * replace it with the amba_console at pl011 driver init.
2340 *
2341 * Performs console setup for a match (as required by interface)
2342 * If no <options> are specified, then assume the h/w is already setup.
2343 *
2344 * Returns 0 if console matches; otherwise non-zero to use default matching
2345 */
2346static int pl011_console_match(struct console *co, char *name, int idx,
2347 char *options)
2348{
2349 unsigned char iotype;
2350 resource_size_t addr;
2351 int i;
2352
2353 /*
2354 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2355 * have a distinct console name, so make sure we check for that.
2356 * The actual implementation of the erratum occurs in the probe
2357 * function.
2358 */
2359 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2360 return -ENODEV;
2361
2362 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2363 return -ENODEV;
2364
2365 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2366 return -ENODEV;
2367
2368 /* try to match the port specified on the command line */
2369 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2370 struct uart_port *port;
2371
2372 if (!amba_ports[i])
2373 continue;
2374
2375 port = &amba_ports[i]->port;
2376
2377 if (port->mapbase != addr)
2378 continue;
2379
2380 co->index = i;
2381 port->cons = co;
2382 return pl011_console_setup(co, options);
2383 }
2384
2385 return -ENODEV;
2386}
2387
2388static struct uart_driver amba_reg;
2389static struct console amba_console = {
2390 .name = "ttyAMA",
2391 .write = pl011_console_write,
2392 .device = uart_console_device,
2393 .setup = pl011_console_setup,
2394 .match = pl011_console_match,
2395 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2396 .index = -1,
2397 .data = &amba_reg,
2398};
2399
2400#define AMBA_CONSOLE (&amba_console)
2401
2402static void qdf2400_e44_putc(struct uart_port *port, int c)
2403{
2404 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2405 cpu_relax();
2406 writel(c, port->membase + UART01x_DR);
2407 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2408 cpu_relax();
2409}
2410
2411static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2412{
2413 struct earlycon_device *dev = con->data;
2414
2415 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2416}
2417
2418static void pl011_putc(struct uart_port *port, int c)
2419{
2420 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2421 cpu_relax();
2422 if (port->iotype == UPIO_MEM32)
2423 writel(c, port->membase + UART01x_DR);
2424 else
2425 writeb(c, port->membase + UART01x_DR);
2426 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2427 cpu_relax();
2428}
2429
2430static void pl011_early_write(struct console *con, const char *s, unsigned n)
2431{
2432 struct earlycon_device *dev = con->data;
2433
2434 uart_console_write(&dev->port, s, n, pl011_putc);
2435}
2436
2437#ifdef CONFIG_CONSOLE_POLL
2438static int pl011_getc(struct uart_port *port)
2439{
2440 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2441 return NO_POLL_CHAR;
2442
2443 if (port->iotype == UPIO_MEM32)
2444 return readl(port->membase + UART01x_DR);
2445 else
2446 return readb(port->membase + UART01x_DR);
2447}
2448
2449static int pl011_early_read(struct console *con, char *s, unsigned int n)
2450{
2451 struct earlycon_device *dev = con->data;
2452 int ch, num_read = 0;
2453
2454 while (num_read < n) {
2455 ch = pl011_getc(&dev->port);
2456 if (ch == NO_POLL_CHAR)
2457 break;
2458
2459 s[num_read++] = ch;
2460 }
2461
2462 return num_read;
2463}
2464#else
2465#define pl011_early_read NULL
2466#endif
2467
2468/*
2469 * On non-ACPI systems, earlycon is enabled by specifying
2470 * "earlycon=pl011,<address>" on the kernel command line.
2471 *
2472 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2473 * by specifying only "earlycon" on the command line. Because it requires
2474 * SPCR, the console starts after ACPI is parsed, which is later than a
2475 * traditional early console.
2476 *
2477 * To get the traditional early console that starts before ACPI is parsed,
2478 * specify the full "earlycon=pl011,<address>" option.
2479 */
2480static int __init pl011_early_console_setup(struct earlycon_device *device,
2481 const char *opt)
2482{
2483 if (!device->port.membase)
2484 return -ENODEV;
2485
2486 device->con->write = pl011_early_write;
2487 device->con->read = pl011_early_read;
2488
2489 return 0;
2490}
2491OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2492OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2493
2494/*
2495 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2496 * Erratum 44, traditional earlycon can be enabled by specifying
2497 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2498 *
2499 * Alternatively, you can just specify "earlycon", and the early console
2500 * will be enabled with the information from the SPCR table. In this
2501 * case, the SPCR code will detect the need for the E44 work-around,
2502 * and set the console name to "qdf2400_e44".
2503 */
2504static int __init
2505qdf2400_e44_early_console_setup(struct earlycon_device *device,
2506 const char *opt)
2507{
2508 if (!device->port.membase)
2509 return -ENODEV;
2510
2511 device->con->write = qdf2400_e44_early_write;
2512 return 0;
2513}
2514EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2515
2516#else
2517#define AMBA_CONSOLE NULL
2518#endif
2519
2520static struct uart_driver amba_reg = {
2521 .owner = THIS_MODULE,
2522 .driver_name = "ttyAMA",
2523 .dev_name = "ttyAMA",
2524 .major = SERIAL_AMBA_MAJOR,
2525 .minor = SERIAL_AMBA_MINOR,
2526 .nr = UART_NR,
2527 .cons = AMBA_CONSOLE,
2528};
2529
2530static int pl011_probe_dt_alias(int index, struct device *dev)
2531{
2532 struct device_node *np;
2533 static bool seen_dev_with_alias = false;
2534 static bool seen_dev_without_alias = false;
2535 int ret = index;
2536
2537 if (!IS_ENABLED(CONFIG_OF))
2538 return ret;
2539
2540 np = dev->of_node;
2541 if (!np)
2542 return ret;
2543
2544 ret = of_alias_get_id(np, "serial");
2545 if (ret < 0) {
2546 seen_dev_without_alias = true;
2547 ret = index;
2548 } else {
2549 seen_dev_with_alias = true;
2550 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2551 dev_warn(dev, "requested serial port %d not available.\n", ret);
2552 ret = index;
2553 }
2554 }
2555
2556 if (seen_dev_with_alias && seen_dev_without_alias)
2557 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2558
2559 return ret;
2560}
2561
2562/* unregisters the driver also if no more ports are left */
2563static void pl011_unregister_port(struct uart_amba_port *uap)
2564{
2565 int i;
2566 bool busy = false;
2567
2568 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2569 if (amba_ports[i] == uap)
2570 amba_ports[i] = NULL;
2571 else if (amba_ports[i])
2572 busy = true;
2573 }
2574 pl011_dma_remove(uap);
2575 if (!busy)
2576 uart_unregister_driver(&amba_reg);
2577}
2578
2579static int pl011_find_free_port(void)
2580{
2581 int i;
2582
2583 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2584 if (amba_ports[i] == NULL)
2585 return i;
2586
2587 return -EBUSY;
2588}
2589
2590static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2591 struct resource *mmiobase, int index)
2592{
2593 void __iomem *base;
2594
2595 base = devm_ioremap_resource(dev, mmiobase);
2596 if (IS_ERR(base))
2597 return PTR_ERR(base);
2598
2599 index = pl011_probe_dt_alias(index, dev);
2600
2601 uap->old_cr = 0;
2602 uap->port.dev = dev;
2603 uap->port.mapbase = mmiobase->start;
2604 uap->port.membase = base;
2605 uap->port.fifosize = uap->fifosize;
2606 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2607 uap->port.flags = UPF_BOOT_AUTOCONF;
2608 uap->port.line = index;
2609
2610 amba_ports[index] = uap;
2611
2612 return 0;
2613}
2614
2615static int pl011_register_port(struct uart_amba_port *uap)
2616{
2617 int ret, i;
2618
2619 /* Ensure interrupts from this UART are masked and cleared */
2620 pl011_write(0, uap, REG_IMSC);
2621 pl011_write(0xffff, uap, REG_ICR);
2622
2623 if (!amba_reg.state) {
2624 ret = uart_register_driver(&amba_reg);
2625 if (ret < 0) {
2626 dev_err(uap->port.dev,
2627 "Failed to register AMBA-PL011 driver\n");
2628 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2629 if (amba_ports[i] == uap)
2630 amba_ports[i] = NULL;
2631 return ret;
2632 }
2633 }
2634
2635 ret = uart_add_one_port(&amba_reg, &uap->port);
2636 if (ret)
2637 pl011_unregister_port(uap);
2638
2639 return ret;
2640}
2641
2642static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2643{
2644 struct uart_amba_port *uap;
2645 struct vendor_data *vendor = id->data;
2646 int portnr, ret;
2647
2648 portnr = pl011_find_free_port();
2649 if (portnr < 0)
2650 return portnr;
2651
2652 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2653 GFP_KERNEL);
2654 if (!uap)
2655 return -ENOMEM;
2656
2657 uap->clk = devm_clk_get(&dev->dev, NULL);
2658 if (IS_ERR(uap->clk))
2659 return PTR_ERR(uap->clk);
2660
2661 uap->reg_offset = vendor->reg_offset;
2662 uap->vendor = vendor;
2663 uap->fifosize = vendor->get_fifosize(dev);
2664 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2665 uap->port.irq = dev->irq[0];
2666 uap->port.ops = &amba_pl011_pops;
2667
2668 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2669
2670 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2671 if (ret)
2672 return ret;
2673
2674 amba_set_drvdata(dev, uap);
2675
2676 return pl011_register_port(uap);
2677}
2678
2679static int pl011_remove(struct amba_device *dev)
2680{
2681 struct uart_amba_port *uap = amba_get_drvdata(dev);
2682
2683 uart_remove_one_port(&amba_reg, &uap->port);
2684 pl011_unregister_port(uap);
2685 return 0;
2686}
2687
2688#ifdef CONFIG_PM_SLEEP
2689static int pl011_suspend(struct device *dev)
2690{
2691 struct uart_amba_port *uap = dev_get_drvdata(dev);
2692
2693 if (!uap)
2694 return -EINVAL;
2695
2696 return uart_suspend_port(&amba_reg, &uap->port);
2697}
2698
2699static int pl011_resume(struct device *dev)
2700{
2701 struct uart_amba_port *uap = dev_get_drvdata(dev);
2702
2703 if (!uap)
2704 return -EINVAL;
2705
2706 return uart_resume_port(&amba_reg, &uap->port);
2707}
2708#endif
2709
2710static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2711
2712static int sbsa_uart_probe(struct platform_device *pdev)
2713{
2714 struct uart_amba_port *uap;
2715 struct resource *r;
2716 int portnr, ret;
2717 int baudrate;
2718
2719 /*
2720 * Check the mandatory baud rate parameter in the DT node early
2721 * so that we can easily exit with the error.
2722 */
2723 if (pdev->dev.of_node) {
2724 struct device_node *np = pdev->dev.of_node;
2725
2726 ret = of_property_read_u32(np, "current-speed", &baudrate);
2727 if (ret)
2728 return ret;
2729 } else {
2730 baudrate = 115200;
2731 }
2732
2733 portnr = pl011_find_free_port();
2734 if (portnr < 0)
2735 return portnr;
2736
2737 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2738 GFP_KERNEL);
2739 if (!uap)
2740 return -ENOMEM;
2741
2742 ret = platform_get_irq(pdev, 0);
2743 if (ret < 0)
2744 return ret;
2745 uap->port.irq = ret;
2746
2747#ifdef CONFIG_ACPI_SPCR_TABLE
2748 if (qdf2400_e44_present) {
2749 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2750 uap->vendor = &vendor_qdt_qdf2400_e44;
2751 } else
2752#endif
2753 uap->vendor = &vendor_sbsa;
2754
2755 uap->reg_offset = uap->vendor->reg_offset;
2756 uap->fifosize = 32;
2757 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2758 uap->port.ops = &sbsa_uart_pops;
2759 uap->fixed_baud = baudrate;
2760
2761 snprintf(uap->type, sizeof(uap->type), "SBSA");
2762
2763 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2764
2765 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2766 if (ret)
2767 return ret;
2768
2769 platform_set_drvdata(pdev, uap);
2770
2771 return pl011_register_port(uap);
2772}
2773
2774static int sbsa_uart_remove(struct platform_device *pdev)
2775{
2776 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2777
2778 uart_remove_one_port(&amba_reg, &uap->port);
2779 pl011_unregister_port(uap);
2780 return 0;
2781}
2782
2783static const struct of_device_id sbsa_uart_of_match[] = {
2784 { .compatible = "arm,sbsa-uart", },
2785 {},
2786};
2787MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2788
2789static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2790 { "ARMH0011", 0 },
2791 {},
2792};
2793MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2794
2795static struct platform_driver arm_sbsa_uart_platform_driver = {
2796 .probe = sbsa_uart_probe,
2797 .remove = sbsa_uart_remove,
2798 .driver = {
2799 .name = "sbsa-uart",
2800 .pm = &pl011_dev_pm_ops,
2801 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2802 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2803 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2804 },
2805};
2806
2807static const struct amba_id pl011_ids[] = {
2808 {
2809 .id = 0x00041011,
2810 .mask = 0x000fffff,
2811 .data = &vendor_arm,
2812 },
2813 {
2814 .id = 0x00380802,
2815 .mask = 0x00ffffff,
2816 .data = &vendor_st,
2817 },
2818 {
2819 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2820 .mask = 0x00ffffff,
2821 .data = &vendor_zte,
2822 },
2823 { 0, 0 },
2824};
2825
2826MODULE_DEVICE_TABLE(amba, pl011_ids);
2827
2828static struct amba_driver pl011_driver = {
2829 .drv = {
2830 .name = "uart-pl011",
2831 .pm = &pl011_dev_pm_ops,
2832 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2833 },
2834 .id_table = pl011_ids,
2835 .probe = pl011_probe,
2836 .remove = pl011_remove,
2837};
2838
2839static int __init pl011_init(void)
2840{
2841 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2842
2843 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2844 pr_warn("could not register SBSA UART platform driver\n");
2845 return amba_driver_register(&pl011_driver);
2846}
2847
2848static void __exit pl011_exit(void)
2849{
2850 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2851 amba_driver_unregister(&pl011_driver);
2852}
2853
2854/*
2855 * While this can be a module, if builtin it's most likely the console
2856 * So let's leave module_exit but move module_init to an earlier place
2857 */
2858arch_initcall(pl011_init);
2859module_exit(pl011_exit);
2860
2861MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2862MODULE_DESCRIPTION("ARM AMBA serial port driver");
2863MODULE_LICENSE("GPL");