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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Thunderbolt driver - NHI driver
4 *
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
7 *
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
10 */
11
12#include <linux/pm_runtime.h>
13#include <linux/slab.h>
14#include <linux/errno.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
18#include <linux/iommu.h>
19#include <linux/module.h>
20#include <linux/delay.h>
21#include <linux/property.h>
22#include <linux/string_helpers.h>
23
24#include "nhi.h"
25#include "nhi_regs.h"
26#include "tb.h"
27
28#define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
29
30#define RING_FIRST_USABLE_HOPID 1
31/*
32 * Used with QUIRK_E2E to specify an unused HopID the Rx credits are
33 * transferred.
34 */
35#define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID
36/*
37 * Minimal number of vectors when we use MSI-X. Two for control channel
38 * Rx/Tx and the rest four are for cross domain DMA paths.
39 */
40#define MSIX_MIN_VECS 6
41#define MSIX_MAX_VECS 16
42
43#define NHI_MAILBOX_TIMEOUT 500 /* ms */
44
45/* Host interface quirks */
46#define QUIRK_AUTO_CLEAR_INT BIT(0)
47#define QUIRK_E2E BIT(1)
48
49static bool host_reset = true;
50module_param(host_reset, bool, 0444);
51MODULE_PARM_DESC(host_reset, "reset USBv2 host router (default: true)");
52
53static int ring_interrupt_index(const struct tb_ring *ring)
54{
55 int bit = ring->hop;
56 if (!ring->is_tx)
57 bit += ring->nhi->hop_count;
58 return bit;
59}
60
61static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring)
62{
63 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) {
64 u32 val;
65
66 val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
67 iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring);
68 } else {
69 iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring);
70 }
71}
72
73static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring)
74{
75 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT)
76 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring);
77 else
78 iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring);
79}
80
81/*
82 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
83 *
84 * ring->nhi->lock must be held.
85 */
86static void ring_interrupt_active(struct tb_ring *ring, bool active)
87{
88 int index = ring_interrupt_index(ring) / 32 * 4;
89 int reg = REG_RING_INTERRUPT_BASE + index;
90 int interrupt_bit = ring_interrupt_index(ring) & 31;
91 int mask = 1 << interrupt_bit;
92 u32 old, new;
93
94 if (ring->irq > 0) {
95 u32 step, shift, ivr, misc;
96 void __iomem *ivr_base;
97 int auto_clear_bit;
98 int index;
99
100 if (ring->is_tx)
101 index = ring->hop;
102 else
103 index = ring->hop + ring->nhi->hop_count;
104
105 /*
106 * Intel routers support a bit that isn't part of
107 * the USB4 spec to ask the hardware to clear
108 * interrupt status bits automatically since
109 * we already know which interrupt was triggered.
110 *
111 * Other routers explicitly disable auto-clear
112 * to prevent conditions that may occur where two
113 * MSIX interrupts are simultaneously active and
114 * reading the register clears both of them.
115 */
116 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
117 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
118 auto_clear_bit = REG_DMA_MISC_INT_AUTO_CLEAR;
119 else
120 auto_clear_bit = REG_DMA_MISC_DISABLE_AUTO_CLEAR;
121 if (!(misc & auto_clear_bit))
122 iowrite32(misc | auto_clear_bit,
123 ring->nhi->iobase + REG_DMA_MISC);
124
125 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
126 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
127 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
128 ivr = ioread32(ivr_base + step);
129 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
130 if (active)
131 ivr |= ring->vector << shift;
132 iowrite32(ivr, ivr_base + step);
133 }
134
135 old = ioread32(ring->nhi->iobase + reg);
136 if (active)
137 new = old | mask;
138 else
139 new = old & ~mask;
140
141 dev_dbg(&ring->nhi->pdev->dev,
142 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
143 active ? "enabling" : "disabling", reg, interrupt_bit, old, new);
144
145 if (new == old)
146 dev_WARN(&ring->nhi->pdev->dev,
147 "interrupt for %s %d is already %s\n",
148 RING_TYPE(ring), ring->hop,
149 active ? "enabled" : "disabled");
150
151 if (active)
152 iowrite32(new, ring->nhi->iobase + reg);
153 else
154 nhi_mask_interrupt(ring->nhi, mask, index);
155}
156
157/*
158 * nhi_disable_interrupts() - disable interrupts for all rings
159 *
160 * Use only during init and shutdown.
161 */
162static void nhi_disable_interrupts(struct tb_nhi *nhi)
163{
164 int i = 0;
165 /* disable interrupts */
166 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
167 nhi_mask_interrupt(nhi, ~0, 4 * i);
168
169 /* clear interrupt status bits */
170 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
171 nhi_clear_interrupt(nhi, 4 * i);
172}
173
174/* ring helper methods */
175
176static void __iomem *ring_desc_base(struct tb_ring *ring)
177{
178 void __iomem *io = ring->nhi->iobase;
179 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
180 io += ring->hop * 16;
181 return io;
182}
183
184static void __iomem *ring_options_base(struct tb_ring *ring)
185{
186 void __iomem *io = ring->nhi->iobase;
187 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
188 io += ring->hop * 32;
189 return io;
190}
191
192static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
193{
194 /*
195 * The other 16-bits in the register is read-only and writes to it
196 * are ignored by the hardware so we can save one ioread32() by
197 * filling the read-only bits with zeroes.
198 */
199 iowrite32(cons, ring_desc_base(ring) + 8);
200}
201
202static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
203{
204 /* See ring_iowrite_cons() above for explanation */
205 iowrite32(prod << 16, ring_desc_base(ring) + 8);
206}
207
208static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
209{
210 iowrite32(value, ring_desc_base(ring) + offset);
211}
212
213static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
214{
215 iowrite32(value, ring_desc_base(ring) + offset);
216 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
217}
218
219static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
220{
221 iowrite32(value, ring_options_base(ring) + offset);
222}
223
224static bool ring_full(struct tb_ring *ring)
225{
226 return ((ring->head + 1) % ring->size) == ring->tail;
227}
228
229static bool ring_empty(struct tb_ring *ring)
230{
231 return ring->head == ring->tail;
232}
233
234/*
235 * ring_write_descriptors() - post frames from ring->queue to the controller
236 *
237 * ring->lock is held.
238 */
239static void ring_write_descriptors(struct tb_ring *ring)
240{
241 struct ring_frame *frame, *n;
242 struct ring_desc *descriptor;
243 list_for_each_entry_safe(frame, n, &ring->queue, list) {
244 if (ring_full(ring))
245 break;
246 list_move_tail(&frame->list, &ring->in_flight);
247 descriptor = &ring->descriptors[ring->head];
248 descriptor->phys = frame->buffer_phy;
249 descriptor->time = 0;
250 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
251 if (ring->is_tx) {
252 descriptor->length = frame->size;
253 descriptor->eof = frame->eof;
254 descriptor->sof = frame->sof;
255 }
256 ring->head = (ring->head + 1) % ring->size;
257 if (ring->is_tx)
258 ring_iowrite_prod(ring, ring->head);
259 else
260 ring_iowrite_cons(ring, ring->head);
261 }
262}
263
264/*
265 * ring_work() - progress completed frames
266 *
267 * If the ring is shutting down then all frames are marked as canceled and
268 * their callbacks are invoked.
269 *
270 * Otherwise we collect all completed frame from the ring buffer, write new
271 * frame to the ring buffer and invoke the callbacks for the completed frames.
272 */
273static void ring_work(struct work_struct *work)
274{
275 struct tb_ring *ring = container_of(work, typeof(*ring), work);
276 struct ring_frame *frame;
277 bool canceled = false;
278 unsigned long flags;
279 LIST_HEAD(done);
280
281 spin_lock_irqsave(&ring->lock, flags);
282
283 if (!ring->running) {
284 /* Move all frames to done and mark them as canceled. */
285 list_splice_tail_init(&ring->in_flight, &done);
286 list_splice_tail_init(&ring->queue, &done);
287 canceled = true;
288 goto invoke_callback;
289 }
290
291 while (!ring_empty(ring)) {
292 if (!(ring->descriptors[ring->tail].flags
293 & RING_DESC_COMPLETED))
294 break;
295 frame = list_first_entry(&ring->in_flight, typeof(*frame),
296 list);
297 list_move_tail(&frame->list, &done);
298 if (!ring->is_tx) {
299 frame->size = ring->descriptors[ring->tail].length;
300 frame->eof = ring->descriptors[ring->tail].eof;
301 frame->sof = ring->descriptors[ring->tail].sof;
302 frame->flags = ring->descriptors[ring->tail].flags;
303 }
304 ring->tail = (ring->tail + 1) % ring->size;
305 }
306 ring_write_descriptors(ring);
307
308invoke_callback:
309 /* allow callbacks to schedule new work */
310 spin_unlock_irqrestore(&ring->lock, flags);
311 while (!list_empty(&done)) {
312 frame = list_first_entry(&done, typeof(*frame), list);
313 /*
314 * The callback may reenqueue or delete frame.
315 * Do not hold on to it.
316 */
317 list_del_init(&frame->list);
318 if (frame->callback)
319 frame->callback(ring, frame, canceled);
320 }
321}
322
323int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
324{
325 unsigned long flags;
326 int ret = 0;
327
328 spin_lock_irqsave(&ring->lock, flags);
329 if (ring->running) {
330 list_add_tail(&frame->list, &ring->queue);
331 ring_write_descriptors(ring);
332 } else {
333 ret = -ESHUTDOWN;
334 }
335 spin_unlock_irqrestore(&ring->lock, flags);
336 return ret;
337}
338EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
339
340/**
341 * tb_ring_poll() - Poll one completed frame from the ring
342 * @ring: Ring to poll
343 *
344 * This function can be called when @start_poll callback of the @ring
345 * has been called. It will read one completed frame from the ring and
346 * return it to the caller. Returns %NULL if there is no more completed
347 * frames.
348 */
349struct ring_frame *tb_ring_poll(struct tb_ring *ring)
350{
351 struct ring_frame *frame = NULL;
352 unsigned long flags;
353
354 spin_lock_irqsave(&ring->lock, flags);
355 if (!ring->running)
356 goto unlock;
357 if (ring_empty(ring))
358 goto unlock;
359
360 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
361 frame = list_first_entry(&ring->in_flight, typeof(*frame),
362 list);
363 list_del_init(&frame->list);
364
365 if (!ring->is_tx) {
366 frame->size = ring->descriptors[ring->tail].length;
367 frame->eof = ring->descriptors[ring->tail].eof;
368 frame->sof = ring->descriptors[ring->tail].sof;
369 frame->flags = ring->descriptors[ring->tail].flags;
370 }
371
372 ring->tail = (ring->tail + 1) % ring->size;
373 }
374
375unlock:
376 spin_unlock_irqrestore(&ring->lock, flags);
377 return frame;
378}
379EXPORT_SYMBOL_GPL(tb_ring_poll);
380
381static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
382{
383 int idx = ring_interrupt_index(ring);
384 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
385 int bit = idx % 32;
386 u32 val;
387
388 val = ioread32(ring->nhi->iobase + reg);
389 if (mask)
390 val &= ~BIT(bit);
391 else
392 val |= BIT(bit);
393 iowrite32(val, ring->nhi->iobase + reg);
394}
395
396/* Both @nhi->lock and @ring->lock should be held */
397static void __ring_interrupt(struct tb_ring *ring)
398{
399 if (!ring->running)
400 return;
401
402 if (ring->start_poll) {
403 __ring_interrupt_mask(ring, true);
404 ring->start_poll(ring->poll_data);
405 } else {
406 schedule_work(&ring->work);
407 }
408}
409
410/**
411 * tb_ring_poll_complete() - Re-start interrupt for the ring
412 * @ring: Ring to re-start the interrupt
413 *
414 * This will re-start (unmask) the ring interrupt once the user is done
415 * with polling.
416 */
417void tb_ring_poll_complete(struct tb_ring *ring)
418{
419 unsigned long flags;
420
421 spin_lock_irqsave(&ring->nhi->lock, flags);
422 spin_lock(&ring->lock);
423 if (ring->start_poll)
424 __ring_interrupt_mask(ring, false);
425 spin_unlock(&ring->lock);
426 spin_unlock_irqrestore(&ring->nhi->lock, flags);
427}
428EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
429
430static void ring_clear_msix(const struct tb_ring *ring)
431{
432 int bit;
433
434 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
435 return;
436
437 bit = ring_interrupt_index(ring) & 31;
438 if (ring->is_tx)
439 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR);
440 else
441 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR +
442 4 * (ring->nhi->hop_count / 32));
443}
444
445static irqreturn_t ring_msix(int irq, void *data)
446{
447 struct tb_ring *ring = data;
448
449 spin_lock(&ring->nhi->lock);
450 ring_clear_msix(ring);
451 spin_lock(&ring->lock);
452 __ring_interrupt(ring);
453 spin_unlock(&ring->lock);
454 spin_unlock(&ring->nhi->lock);
455
456 return IRQ_HANDLED;
457}
458
459static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
460{
461 struct tb_nhi *nhi = ring->nhi;
462 unsigned long irqflags;
463 int ret;
464
465 if (!nhi->pdev->msix_enabled)
466 return 0;
467
468 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
469 if (ret < 0)
470 return ret;
471
472 ring->vector = ret;
473
474 ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
475 if (ret < 0)
476 goto err_ida_remove;
477
478 ring->irq = ret;
479
480 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
481 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
482 if (ret)
483 goto err_ida_remove;
484
485 return 0;
486
487err_ida_remove:
488 ida_simple_remove(&nhi->msix_ida, ring->vector);
489
490 return ret;
491}
492
493static void ring_release_msix(struct tb_ring *ring)
494{
495 if (ring->irq <= 0)
496 return;
497
498 free_irq(ring->irq, ring);
499 ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
500 ring->vector = 0;
501 ring->irq = 0;
502}
503
504static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
505{
506 unsigned int start_hop = RING_FIRST_USABLE_HOPID;
507 int ret = 0;
508
509 if (nhi->quirks & QUIRK_E2E) {
510 start_hop = RING_FIRST_USABLE_HOPID + 1;
511 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) {
512 dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n",
513 ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID);
514 ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID;
515 }
516 }
517
518 spin_lock_irq(&nhi->lock);
519
520 if (ring->hop < 0) {
521 unsigned int i;
522
523 /*
524 * Automatically allocate HopID from the non-reserved
525 * range 1 .. hop_count - 1.
526 */
527 for (i = start_hop; i < nhi->hop_count; i++) {
528 if (ring->is_tx) {
529 if (!nhi->tx_rings[i]) {
530 ring->hop = i;
531 break;
532 }
533 } else {
534 if (!nhi->rx_rings[i]) {
535 ring->hop = i;
536 break;
537 }
538 }
539 }
540 }
541
542 if (ring->hop > 0 && ring->hop < start_hop) {
543 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
544 ret = -EINVAL;
545 goto err_unlock;
546 }
547 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
548 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
549 ret = -EINVAL;
550 goto err_unlock;
551 }
552 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
553 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
554 ring->hop);
555 ret = -EBUSY;
556 goto err_unlock;
557 }
558 if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
559 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
560 ring->hop);
561 ret = -EBUSY;
562 goto err_unlock;
563 }
564
565 if (ring->is_tx)
566 nhi->tx_rings[ring->hop] = ring;
567 else
568 nhi->rx_rings[ring->hop] = ring;
569
570err_unlock:
571 spin_unlock_irq(&nhi->lock);
572
573 return ret;
574}
575
576static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
577 bool transmit, unsigned int flags,
578 int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
579 void (*start_poll)(void *),
580 void *poll_data)
581{
582 struct tb_ring *ring = NULL;
583
584 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
585 transmit ? "TX" : "RX", hop, size);
586
587 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
588 if (!ring)
589 return NULL;
590
591 spin_lock_init(&ring->lock);
592 INIT_LIST_HEAD(&ring->queue);
593 INIT_LIST_HEAD(&ring->in_flight);
594 INIT_WORK(&ring->work, ring_work);
595
596 ring->nhi = nhi;
597 ring->hop = hop;
598 ring->is_tx = transmit;
599 ring->size = size;
600 ring->flags = flags;
601 ring->e2e_tx_hop = e2e_tx_hop;
602 ring->sof_mask = sof_mask;
603 ring->eof_mask = eof_mask;
604 ring->head = 0;
605 ring->tail = 0;
606 ring->running = false;
607 ring->start_poll = start_poll;
608 ring->poll_data = poll_data;
609
610 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
611 size * sizeof(*ring->descriptors),
612 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
613 if (!ring->descriptors)
614 goto err_free_ring;
615
616 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
617 goto err_free_descs;
618
619 if (nhi_alloc_hop(nhi, ring))
620 goto err_release_msix;
621
622 return ring;
623
624err_release_msix:
625 ring_release_msix(ring);
626err_free_descs:
627 dma_free_coherent(&ring->nhi->pdev->dev,
628 ring->size * sizeof(*ring->descriptors),
629 ring->descriptors, ring->descriptors_dma);
630err_free_ring:
631 kfree(ring);
632
633 return NULL;
634}
635
636/**
637 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
638 * @nhi: Pointer to the NHI the ring is to be allocated
639 * @hop: HopID (ring) to allocate
640 * @size: Number of entries in the ring
641 * @flags: Flags for the ring
642 */
643struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
644 unsigned int flags)
645{
646 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
647}
648EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
649
650/**
651 * tb_ring_alloc_rx() - Allocate DMA ring for receive
652 * @nhi: Pointer to the NHI the ring is to be allocated
653 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
654 * @size: Number of entries in the ring
655 * @flags: Flags for the ring
656 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
657 * @sof_mask: Mask of PDF values that start a frame
658 * @eof_mask: Mask of PDF values that end a frame
659 * @start_poll: If not %NULL the ring will call this function when an
660 * interrupt is triggered and masked, instead of callback
661 * in each Rx frame.
662 * @poll_data: Optional data passed to @start_poll
663 */
664struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
665 unsigned int flags, int e2e_tx_hop,
666 u16 sof_mask, u16 eof_mask,
667 void (*start_poll)(void *), void *poll_data)
668{
669 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
670 start_poll, poll_data);
671}
672EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
673
674/**
675 * tb_ring_start() - enable a ring
676 * @ring: Ring to start
677 *
678 * Must not be invoked in parallel with tb_ring_stop().
679 */
680void tb_ring_start(struct tb_ring *ring)
681{
682 u16 frame_size;
683 u32 flags;
684
685 spin_lock_irq(&ring->nhi->lock);
686 spin_lock(&ring->lock);
687 if (ring->nhi->going_away)
688 goto err;
689 if (ring->running) {
690 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
691 goto err;
692 }
693 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
694 RING_TYPE(ring), ring->hop);
695
696 if (ring->flags & RING_FLAG_FRAME) {
697 /* Means 4096 */
698 frame_size = 0;
699 flags = RING_FLAG_ENABLE;
700 } else {
701 frame_size = TB_FRAME_SIZE;
702 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
703 }
704
705 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
706 if (ring->is_tx) {
707 ring_iowrite32desc(ring, ring->size, 12);
708 ring_iowrite32options(ring, 0, 4); /* time releated ? */
709 ring_iowrite32options(ring, flags, 0);
710 } else {
711 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
712
713 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
714 ring_iowrite32options(ring, sof_eof_mask, 4);
715 ring_iowrite32options(ring, flags, 0);
716 }
717
718 /*
719 * Now that the ring valid bit is set we can configure E2E if
720 * enabled for the ring.
721 */
722 if (ring->flags & RING_FLAG_E2E) {
723 if (!ring->is_tx) {
724 u32 hop;
725
726 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
727 hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
728 flags |= hop;
729
730 dev_dbg(&ring->nhi->pdev->dev,
731 "enabling E2E for %s %d with TX HopID %d\n",
732 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
733 } else {
734 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
735 RING_TYPE(ring), ring->hop);
736 }
737
738 flags |= RING_FLAG_E2E_FLOW_CONTROL;
739 ring_iowrite32options(ring, flags, 0);
740 }
741
742 ring_interrupt_active(ring, true);
743 ring->running = true;
744err:
745 spin_unlock(&ring->lock);
746 spin_unlock_irq(&ring->nhi->lock);
747}
748EXPORT_SYMBOL_GPL(tb_ring_start);
749
750/**
751 * tb_ring_stop() - shutdown a ring
752 * @ring: Ring to stop
753 *
754 * Must not be invoked from a callback.
755 *
756 * This method will disable the ring. Further calls to
757 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
758 * called.
759 *
760 * All enqueued frames will be canceled and their callbacks will be executed
761 * with frame->canceled set to true (on the callback thread). This method
762 * returns only after all callback invocations have finished.
763 */
764void tb_ring_stop(struct tb_ring *ring)
765{
766 spin_lock_irq(&ring->nhi->lock);
767 spin_lock(&ring->lock);
768 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
769 RING_TYPE(ring), ring->hop);
770 if (ring->nhi->going_away)
771 goto err;
772 if (!ring->running) {
773 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
774 RING_TYPE(ring), ring->hop);
775 goto err;
776 }
777 ring_interrupt_active(ring, false);
778
779 ring_iowrite32options(ring, 0, 0);
780 ring_iowrite64desc(ring, 0, 0);
781 ring_iowrite32desc(ring, 0, 8);
782 ring_iowrite32desc(ring, 0, 12);
783 ring->head = 0;
784 ring->tail = 0;
785 ring->running = false;
786
787err:
788 spin_unlock(&ring->lock);
789 spin_unlock_irq(&ring->nhi->lock);
790
791 /*
792 * schedule ring->work to invoke callbacks on all remaining frames.
793 */
794 schedule_work(&ring->work);
795 flush_work(&ring->work);
796}
797EXPORT_SYMBOL_GPL(tb_ring_stop);
798
799/*
800 * tb_ring_free() - free ring
801 *
802 * When this method returns all invocations of ring->callback will have
803 * finished.
804 *
805 * Ring must be stopped.
806 *
807 * Must NOT be called from ring_frame->callback!
808 */
809void tb_ring_free(struct tb_ring *ring)
810{
811 spin_lock_irq(&ring->nhi->lock);
812 /*
813 * Dissociate the ring from the NHI. This also ensures that
814 * nhi_interrupt_work cannot reschedule ring->work.
815 */
816 if (ring->is_tx)
817 ring->nhi->tx_rings[ring->hop] = NULL;
818 else
819 ring->nhi->rx_rings[ring->hop] = NULL;
820
821 if (ring->running) {
822 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
823 RING_TYPE(ring), ring->hop);
824 }
825 spin_unlock_irq(&ring->nhi->lock);
826
827 ring_release_msix(ring);
828
829 dma_free_coherent(&ring->nhi->pdev->dev,
830 ring->size * sizeof(*ring->descriptors),
831 ring->descriptors, ring->descriptors_dma);
832
833 ring->descriptors = NULL;
834 ring->descriptors_dma = 0;
835
836
837 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
838 ring->hop);
839
840 /*
841 * ring->work can no longer be scheduled (it is scheduled only
842 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
843 * to finish before freeing the ring.
844 */
845 flush_work(&ring->work);
846 kfree(ring);
847}
848EXPORT_SYMBOL_GPL(tb_ring_free);
849
850/**
851 * nhi_mailbox_cmd() - Send a command through NHI mailbox
852 * @nhi: Pointer to the NHI structure
853 * @cmd: Command to send
854 * @data: Data to be send with the command
855 *
856 * Sends mailbox command to the firmware running on NHI. Returns %0 in
857 * case of success and negative errno in case of failure.
858 */
859int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
860{
861 ktime_t timeout;
862 u32 val;
863
864 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
865
866 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
867 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
868 val |= REG_INMAIL_OP_REQUEST | cmd;
869 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
870
871 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
872 do {
873 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
874 if (!(val & REG_INMAIL_OP_REQUEST))
875 break;
876 usleep_range(10, 20);
877 } while (ktime_before(ktime_get(), timeout));
878
879 if (val & REG_INMAIL_OP_REQUEST)
880 return -ETIMEDOUT;
881 if (val & REG_INMAIL_ERROR)
882 return -EIO;
883
884 return 0;
885}
886
887/**
888 * nhi_mailbox_mode() - Return current firmware operation mode
889 * @nhi: Pointer to the NHI structure
890 *
891 * The function reads current firmware operation mode using NHI mailbox
892 * registers and returns it to the caller.
893 */
894enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
895{
896 u32 val;
897
898 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
899 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
900 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
901
902 return (enum nhi_fw_mode)val;
903}
904
905static void nhi_interrupt_work(struct work_struct *work)
906{
907 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
908 int value = 0; /* Suppress uninitialized usage warning. */
909 int bit;
910 int hop = -1;
911 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
912 struct tb_ring *ring;
913
914 spin_lock_irq(&nhi->lock);
915
916 /*
917 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
918 * (TX, RX, RX overflow). We iterate over the bits and read a new
919 * dwords as required. The registers are cleared on read.
920 */
921 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
922 if (bit % 32 == 0)
923 value = ioread32(nhi->iobase
924 + REG_RING_NOTIFY_BASE
925 + 4 * (bit / 32));
926 if (++hop == nhi->hop_count) {
927 hop = 0;
928 type++;
929 }
930 if ((value & (1 << (bit % 32))) == 0)
931 continue;
932 if (type == 2) {
933 dev_warn(&nhi->pdev->dev,
934 "RX overflow for ring %d\n",
935 hop);
936 continue;
937 }
938 if (type == 0)
939 ring = nhi->tx_rings[hop];
940 else
941 ring = nhi->rx_rings[hop];
942 if (ring == NULL) {
943 dev_warn(&nhi->pdev->dev,
944 "got interrupt for inactive %s ring %d\n",
945 type ? "RX" : "TX",
946 hop);
947 continue;
948 }
949
950 spin_lock(&ring->lock);
951 __ring_interrupt(ring);
952 spin_unlock(&ring->lock);
953 }
954 spin_unlock_irq(&nhi->lock);
955}
956
957static irqreturn_t nhi_msi(int irq, void *data)
958{
959 struct tb_nhi *nhi = data;
960 schedule_work(&nhi->interrupt_work);
961 return IRQ_HANDLED;
962}
963
964static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
965{
966 struct pci_dev *pdev = to_pci_dev(dev);
967 struct tb *tb = pci_get_drvdata(pdev);
968 struct tb_nhi *nhi = tb->nhi;
969 int ret;
970
971 ret = tb_domain_suspend_noirq(tb);
972 if (ret)
973 return ret;
974
975 if (nhi->ops && nhi->ops->suspend_noirq) {
976 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
977 if (ret)
978 return ret;
979 }
980
981 return 0;
982}
983
984static int nhi_suspend_noirq(struct device *dev)
985{
986 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
987}
988
989static int nhi_freeze_noirq(struct device *dev)
990{
991 struct pci_dev *pdev = to_pci_dev(dev);
992 struct tb *tb = pci_get_drvdata(pdev);
993
994 return tb_domain_freeze_noirq(tb);
995}
996
997static int nhi_thaw_noirq(struct device *dev)
998{
999 struct pci_dev *pdev = to_pci_dev(dev);
1000 struct tb *tb = pci_get_drvdata(pdev);
1001
1002 return tb_domain_thaw_noirq(tb);
1003}
1004
1005static bool nhi_wake_supported(struct pci_dev *pdev)
1006{
1007 u8 val;
1008
1009 /*
1010 * If power rails are sustainable for wakeup from S4 this
1011 * property is set by the BIOS.
1012 */
1013 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
1014 return !!val;
1015
1016 return true;
1017}
1018
1019static int nhi_poweroff_noirq(struct device *dev)
1020{
1021 struct pci_dev *pdev = to_pci_dev(dev);
1022 bool wakeup;
1023
1024 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
1025 return __nhi_suspend_noirq(dev, wakeup);
1026}
1027
1028static void nhi_enable_int_throttling(struct tb_nhi *nhi)
1029{
1030 /* Throttling is specified in 256ns increments */
1031 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
1032 unsigned int i;
1033
1034 /*
1035 * Configure interrupt throttling for all vectors even if we
1036 * only use few.
1037 */
1038 for (i = 0; i < MSIX_MAX_VECS; i++) {
1039 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
1040 iowrite32(throttle, nhi->iobase + reg);
1041 }
1042}
1043
1044static int nhi_resume_noirq(struct device *dev)
1045{
1046 struct pci_dev *pdev = to_pci_dev(dev);
1047 struct tb *tb = pci_get_drvdata(pdev);
1048 struct tb_nhi *nhi = tb->nhi;
1049 int ret;
1050
1051 /*
1052 * Check that the device is still there. It may be that the user
1053 * unplugged last device which causes the host controller to go
1054 * away on PCs.
1055 */
1056 if (!pci_device_is_present(pdev)) {
1057 nhi->going_away = true;
1058 } else {
1059 if (nhi->ops && nhi->ops->resume_noirq) {
1060 ret = nhi->ops->resume_noirq(nhi);
1061 if (ret)
1062 return ret;
1063 }
1064 nhi_enable_int_throttling(tb->nhi);
1065 }
1066
1067 return tb_domain_resume_noirq(tb);
1068}
1069
1070static int nhi_suspend(struct device *dev)
1071{
1072 struct pci_dev *pdev = to_pci_dev(dev);
1073 struct tb *tb = pci_get_drvdata(pdev);
1074
1075 return tb_domain_suspend(tb);
1076}
1077
1078static void nhi_complete(struct device *dev)
1079{
1080 struct pci_dev *pdev = to_pci_dev(dev);
1081 struct tb *tb = pci_get_drvdata(pdev);
1082
1083 /*
1084 * If we were runtime suspended when system suspend started,
1085 * schedule runtime resume now. It should bring the domain back
1086 * to functional state.
1087 */
1088 if (pm_runtime_suspended(&pdev->dev))
1089 pm_runtime_resume(&pdev->dev);
1090 else
1091 tb_domain_complete(tb);
1092}
1093
1094static int nhi_runtime_suspend(struct device *dev)
1095{
1096 struct pci_dev *pdev = to_pci_dev(dev);
1097 struct tb *tb = pci_get_drvdata(pdev);
1098 struct tb_nhi *nhi = tb->nhi;
1099 int ret;
1100
1101 ret = tb_domain_runtime_suspend(tb);
1102 if (ret)
1103 return ret;
1104
1105 if (nhi->ops && nhi->ops->runtime_suspend) {
1106 ret = nhi->ops->runtime_suspend(tb->nhi);
1107 if (ret)
1108 return ret;
1109 }
1110 return 0;
1111}
1112
1113static int nhi_runtime_resume(struct device *dev)
1114{
1115 struct pci_dev *pdev = to_pci_dev(dev);
1116 struct tb *tb = pci_get_drvdata(pdev);
1117 struct tb_nhi *nhi = tb->nhi;
1118 int ret;
1119
1120 if (nhi->ops && nhi->ops->runtime_resume) {
1121 ret = nhi->ops->runtime_resume(nhi);
1122 if (ret)
1123 return ret;
1124 }
1125
1126 nhi_enable_int_throttling(nhi);
1127 return tb_domain_runtime_resume(tb);
1128}
1129
1130static void nhi_shutdown(struct tb_nhi *nhi)
1131{
1132 int i;
1133
1134 dev_dbg(&nhi->pdev->dev, "shutdown\n");
1135
1136 for (i = 0; i < nhi->hop_count; i++) {
1137 if (nhi->tx_rings[i])
1138 dev_WARN(&nhi->pdev->dev,
1139 "TX ring %d is still active\n", i);
1140 if (nhi->rx_rings[i])
1141 dev_WARN(&nhi->pdev->dev,
1142 "RX ring %d is still active\n", i);
1143 }
1144 nhi_disable_interrupts(nhi);
1145 /*
1146 * We have to release the irq before calling flush_work. Otherwise an
1147 * already executing IRQ handler could call schedule_work again.
1148 */
1149 if (!nhi->pdev->msix_enabled) {
1150 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1151 flush_work(&nhi->interrupt_work);
1152 }
1153 ida_destroy(&nhi->msix_ida);
1154
1155 if (nhi->ops && nhi->ops->shutdown)
1156 nhi->ops->shutdown(nhi);
1157}
1158
1159static void nhi_check_quirks(struct tb_nhi *nhi)
1160{
1161 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) {
1162 /*
1163 * Intel hardware supports auto clear of the interrupt
1164 * status register right after interrupt is being
1165 * issued.
1166 */
1167 nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
1168
1169 switch (nhi->pdev->device) {
1170 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
1171 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
1172 /*
1173 * Falcon Ridge controller needs the end-to-end
1174 * flow control workaround to avoid losing Rx
1175 * packets when RING_FLAG_E2E is set.
1176 */
1177 nhi->quirks |= QUIRK_E2E;
1178 break;
1179 }
1180 }
1181}
1182
1183static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data)
1184{
1185 if (!pdev->external_facing ||
1186 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION))
1187 return 0;
1188 *(bool *)data = true;
1189 return 1; /* Stop walking */
1190}
1191
1192static void nhi_check_iommu(struct tb_nhi *nhi)
1193{
1194 struct pci_bus *bus = nhi->pdev->bus;
1195 bool port_ok = false;
1196
1197 /*
1198 * Ideally what we'd do here is grab every PCI device that
1199 * represents a tunnelling adapter for this NHI and check their
1200 * status directly, but unfortunately USB4 seems to make it
1201 * obnoxiously difficult to reliably make any correlation.
1202 *
1203 * So for now we'll have to bodge it... Hoping that the system
1204 * is at least sane enough that an adapter is in the same PCI
1205 * segment as its NHI, if we can find *something* on that segment
1206 * which meets the requirements for Kernel DMA Protection, we'll
1207 * take that to imply that firmware is aware and has (hopefully)
1208 * done the right thing in general. We need to know that the PCI
1209 * layer has seen the ExternalFacingPort property which will then
1210 * inform the IOMMU layer to enforce the complete "untrusted DMA"
1211 * flow, but also that the IOMMU driver itself can be trusted not
1212 * to have been subverted by a pre-boot DMA attack.
1213 */
1214 while (bus->parent)
1215 bus = bus->parent;
1216
1217 pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok);
1218
1219 nhi->iommu_dma_protection = port_ok;
1220 dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n",
1221 str_enabled_disabled(port_ok));
1222}
1223
1224static void nhi_reset(struct tb_nhi *nhi)
1225{
1226 ktime_t timeout;
1227 u32 val;
1228
1229 val = ioread32(nhi->iobase + REG_CAPS);
1230 /* Reset only v2 and later routers */
1231 if (FIELD_GET(REG_CAPS_VERSION_MASK, val) < REG_CAPS_VERSION_2)
1232 return;
1233
1234 if (!host_reset) {
1235 dev_dbg(&nhi->pdev->dev, "skipping host router reset\n");
1236 return;
1237 }
1238
1239 iowrite32(REG_RESET_HRR, nhi->iobase + REG_RESET);
1240 msleep(100);
1241
1242 timeout = ktime_add_ms(ktime_get(), 500);
1243 do {
1244 val = ioread32(nhi->iobase + REG_RESET);
1245 if (!(val & REG_RESET_HRR)) {
1246 dev_warn(&nhi->pdev->dev, "host router reset successful\n");
1247 return;
1248 }
1249 usleep_range(10, 20);
1250 } while (ktime_before(ktime_get(), timeout));
1251
1252 dev_warn(&nhi->pdev->dev, "timeout resetting host router\n");
1253}
1254
1255static int nhi_init_msi(struct tb_nhi *nhi)
1256{
1257 struct pci_dev *pdev = nhi->pdev;
1258 struct device *dev = &pdev->dev;
1259 int res, irq, nvec;
1260
1261 /* In case someone left them on. */
1262 nhi_disable_interrupts(nhi);
1263
1264 nhi_enable_int_throttling(nhi);
1265
1266 ida_init(&nhi->msix_ida);
1267
1268 /*
1269 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1270 * get all MSI-X vectors and if we succeed, each ring will have
1271 * one MSI-X. If for some reason that does not work out, we
1272 * fallback to a single MSI.
1273 */
1274 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1275 PCI_IRQ_MSIX);
1276 if (nvec < 0) {
1277 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1278 if (nvec < 0)
1279 return nvec;
1280
1281 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1282
1283 irq = pci_irq_vector(nhi->pdev, 0);
1284 if (irq < 0)
1285 return irq;
1286
1287 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1288 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1289 if (res)
1290 return dev_err_probe(dev, res, "request_irq failed, aborting\n");
1291 }
1292
1293 return 0;
1294}
1295
1296static bool nhi_imr_valid(struct pci_dev *pdev)
1297{
1298 u8 val;
1299
1300 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1301 return !!val;
1302
1303 return true;
1304}
1305
1306static struct tb *nhi_select_cm(struct tb_nhi *nhi)
1307{
1308 struct tb *tb;
1309
1310 /*
1311 * USB4 case is simple. If we got control of any of the
1312 * capabilities, we use software CM.
1313 */
1314 if (tb_acpi_is_native())
1315 return tb_probe(nhi);
1316
1317 /*
1318 * Either firmware based CM is running (we did not get control
1319 * from the firmware) or this is pre-USB4 PC so try first
1320 * firmware CM and then fallback to software CM.
1321 */
1322 tb = icm_probe(nhi);
1323 if (!tb)
1324 tb = tb_probe(nhi);
1325
1326 return tb;
1327}
1328
1329static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1330{
1331 struct device *dev = &pdev->dev;
1332 struct tb_nhi *nhi;
1333 struct tb *tb;
1334 int res;
1335
1336 if (!nhi_imr_valid(pdev))
1337 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n");
1338
1339 res = pcim_enable_device(pdev);
1340 if (res)
1341 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n");
1342
1343 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1344 if (res)
1345 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n");
1346
1347 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1348 if (!nhi)
1349 return -ENOMEM;
1350
1351 nhi->pdev = pdev;
1352 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1353 /* cannot fail - table is allocated in pcim_iomap_regions */
1354 nhi->iobase = pcim_iomap_table(pdev)[0];
1355 nhi->hop_count = ioread32(nhi->iobase + REG_CAPS) & 0x3ff;
1356 dev_dbg(dev, "total paths: %d\n", nhi->hop_count);
1357
1358 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1359 sizeof(*nhi->tx_rings), GFP_KERNEL);
1360 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1361 sizeof(*nhi->rx_rings), GFP_KERNEL);
1362 if (!nhi->tx_rings || !nhi->rx_rings)
1363 return -ENOMEM;
1364
1365 nhi_check_quirks(nhi);
1366 nhi_check_iommu(nhi);
1367
1368 nhi_reset(nhi);
1369
1370 res = nhi_init_msi(nhi);
1371 if (res)
1372 return dev_err_probe(dev, res, "cannot enable MSI, aborting\n");
1373
1374 spin_lock_init(&nhi->lock);
1375
1376 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1377 if (res)
1378 return dev_err_probe(dev, res, "failed to set DMA mask\n");
1379
1380 pci_set_master(pdev);
1381
1382 if (nhi->ops && nhi->ops->init) {
1383 res = nhi->ops->init(nhi);
1384 if (res)
1385 return res;
1386 }
1387
1388 tb = nhi_select_cm(nhi);
1389 if (!tb)
1390 return dev_err_probe(dev, -ENODEV,
1391 "failed to determine connection manager, aborting\n");
1392
1393 dev_dbg(dev, "NHI initialized, starting thunderbolt\n");
1394
1395 res = tb_domain_add(tb);
1396 if (res) {
1397 /*
1398 * At this point the RX/TX rings might already have been
1399 * activated. Do a proper shutdown.
1400 */
1401 tb_domain_put(tb);
1402 nhi_shutdown(nhi);
1403 return res;
1404 }
1405 pci_set_drvdata(pdev, tb);
1406
1407 device_wakeup_enable(&pdev->dev);
1408
1409 pm_runtime_allow(&pdev->dev);
1410 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1411 pm_runtime_use_autosuspend(&pdev->dev);
1412 pm_runtime_put_autosuspend(&pdev->dev);
1413
1414 return 0;
1415}
1416
1417static void nhi_remove(struct pci_dev *pdev)
1418{
1419 struct tb *tb = pci_get_drvdata(pdev);
1420 struct tb_nhi *nhi = tb->nhi;
1421
1422 pm_runtime_get_sync(&pdev->dev);
1423 pm_runtime_dont_use_autosuspend(&pdev->dev);
1424 pm_runtime_forbid(&pdev->dev);
1425
1426 tb_domain_remove(tb);
1427 nhi_shutdown(nhi);
1428}
1429
1430/*
1431 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1432 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1433 * resume_noirq until we are done.
1434 */
1435static const struct dev_pm_ops nhi_pm_ops = {
1436 .suspend_noirq = nhi_suspend_noirq,
1437 .resume_noirq = nhi_resume_noirq,
1438 .freeze_noirq = nhi_freeze_noirq, /*
1439 * we just disable hotplug, the
1440 * pci-tunnels stay alive.
1441 */
1442 .thaw_noirq = nhi_thaw_noirq,
1443 .restore_noirq = nhi_resume_noirq,
1444 .suspend = nhi_suspend,
1445 .poweroff_noirq = nhi_poweroff_noirq,
1446 .poweroff = nhi_suspend,
1447 .complete = nhi_complete,
1448 .runtime_suspend = nhi_runtime_suspend,
1449 .runtime_resume = nhi_runtime_resume,
1450};
1451
1452static struct pci_device_id nhi_ids[] = {
1453 /*
1454 * We have to specify class, the TB bridges use the same device and
1455 * vendor (sub)id on gen 1 and gen 2 controllers.
1456 */
1457 {
1458 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1459 .vendor = PCI_VENDOR_ID_INTEL,
1460 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1461 .subvendor = 0x2222, .subdevice = 0x1111,
1462 },
1463 {
1464 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1465 .vendor = PCI_VENDOR_ID_INTEL,
1466 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1467 .subvendor = 0x2222, .subdevice = 0x1111,
1468 },
1469 {
1470 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1471 .vendor = PCI_VENDOR_ID_INTEL,
1472 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1473 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1474 },
1475 {
1476 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1477 .vendor = PCI_VENDOR_ID_INTEL,
1478 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1479 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1480 },
1481
1482 /* Thunderbolt 3 */
1483 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1484 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1485 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1486 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1487 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1488 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1489 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1490 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1491 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1492 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1493 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1494 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1495 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1496 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1497 /* Thunderbolt 4 */
1498 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1499 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1500 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1501 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1502 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1503 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1504 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1505 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1506 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
1507 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1508 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
1509 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1510 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0),
1511 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1512 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1),
1513 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1514 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0),
1515 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1516 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0),
1517 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1518 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1),
1519 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1520 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI0),
1521 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1522 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI1),
1523 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1524 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) },
1525 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) },
1526
1527 /* Any USB4 compliant host */
1528 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1529
1530 { 0,}
1531};
1532
1533MODULE_DEVICE_TABLE(pci, nhi_ids);
1534MODULE_DESCRIPTION("Thunderbolt/USB4 core driver");
1535MODULE_LICENSE("GPL");
1536
1537static struct pci_driver nhi_driver = {
1538 .name = "thunderbolt",
1539 .id_table = nhi_ids,
1540 .probe = nhi_probe,
1541 .remove = nhi_remove,
1542 .shutdown = nhi_remove,
1543 .driver.pm = &nhi_pm_ops,
1544};
1545
1546static int __init nhi_init(void)
1547{
1548 int ret;
1549
1550 ret = tb_domain_init();
1551 if (ret)
1552 return ret;
1553 ret = pci_register_driver(&nhi_driver);
1554 if (ret)
1555 tb_domain_exit();
1556 return ret;
1557}
1558
1559static void __exit nhi_unload(void)
1560{
1561 pci_unregister_driver(&nhi_driver);
1562 tb_domain_exit();
1563}
1564
1565rootfs_initcall(nhi_init);
1566module_exit(nhi_unload);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Thunderbolt driver - NHI driver
4 *
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
7 *
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
10 */
11
12#include <linux/pm_runtime.h>
13#include <linux/slab.h>
14#include <linux/errno.h>
15#include <linux/pci.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/delay.h>
19#include <linux/property.h>
20
21#include "nhi.h"
22#include "nhi_regs.h"
23#include "tb.h"
24
25#define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
26
27#define RING_FIRST_USABLE_HOPID 1
28
29/*
30 * Minimal number of vectors when we use MSI-X. Two for control channel
31 * Rx/Tx and the rest four are for cross domain DMA paths.
32 */
33#define MSIX_MIN_VECS 6
34#define MSIX_MAX_VECS 16
35
36#define NHI_MAILBOX_TIMEOUT 500 /* ms */
37
38static int ring_interrupt_index(struct tb_ring *ring)
39{
40 int bit = ring->hop;
41 if (!ring->is_tx)
42 bit += ring->nhi->hop_count;
43 return bit;
44}
45
46/**
47 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
48 *
49 * ring->nhi->lock must be held.
50 */
51static void ring_interrupt_active(struct tb_ring *ring, bool active)
52{
53 int reg = REG_RING_INTERRUPT_BASE +
54 ring_interrupt_index(ring) / 32 * 4;
55 int bit = ring_interrupt_index(ring) & 31;
56 int mask = 1 << bit;
57 u32 old, new;
58
59 if (ring->irq > 0) {
60 u32 step, shift, ivr, misc;
61 void __iomem *ivr_base;
62 int index;
63
64 if (ring->is_tx)
65 index = ring->hop;
66 else
67 index = ring->hop + ring->nhi->hop_count;
68
69 /*
70 * Ask the hardware to clear interrupt status bits automatically
71 * since we already know which interrupt was triggered.
72 */
73 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
74 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
75 misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
76 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
77 }
78
79 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
80 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
81 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
82 ivr = ioread32(ivr_base + step);
83 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
84 if (active)
85 ivr |= ring->vector << shift;
86 iowrite32(ivr, ivr_base + step);
87 }
88
89 old = ioread32(ring->nhi->iobase + reg);
90 if (active)
91 new = old | mask;
92 else
93 new = old & ~mask;
94
95 dev_dbg(&ring->nhi->pdev->dev,
96 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
97 active ? "enabling" : "disabling", reg, bit, old, new);
98
99 if (new == old)
100 dev_WARN(&ring->nhi->pdev->dev,
101 "interrupt for %s %d is already %s\n",
102 RING_TYPE(ring), ring->hop,
103 active ? "enabled" : "disabled");
104 iowrite32(new, ring->nhi->iobase + reg);
105}
106
107/**
108 * nhi_disable_interrupts() - disable interrupts for all rings
109 *
110 * Use only during init and shutdown.
111 */
112static void nhi_disable_interrupts(struct tb_nhi *nhi)
113{
114 int i = 0;
115 /* disable interrupts */
116 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
117 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
118
119 /* clear interrupt status bits */
120 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
121 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
122}
123
124/* ring helper methods */
125
126static void __iomem *ring_desc_base(struct tb_ring *ring)
127{
128 void __iomem *io = ring->nhi->iobase;
129 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
130 io += ring->hop * 16;
131 return io;
132}
133
134static void __iomem *ring_options_base(struct tb_ring *ring)
135{
136 void __iomem *io = ring->nhi->iobase;
137 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
138 io += ring->hop * 32;
139 return io;
140}
141
142static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
143{
144 /*
145 * The other 16-bits in the register is read-only and writes to it
146 * are ignored by the hardware so we can save one ioread32() by
147 * filling the read-only bits with zeroes.
148 */
149 iowrite32(cons, ring_desc_base(ring) + 8);
150}
151
152static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
153{
154 /* See ring_iowrite_cons() above for explanation */
155 iowrite32(prod << 16, ring_desc_base(ring) + 8);
156}
157
158static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
159{
160 iowrite32(value, ring_desc_base(ring) + offset);
161}
162
163static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
164{
165 iowrite32(value, ring_desc_base(ring) + offset);
166 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
167}
168
169static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
170{
171 iowrite32(value, ring_options_base(ring) + offset);
172}
173
174static bool ring_full(struct tb_ring *ring)
175{
176 return ((ring->head + 1) % ring->size) == ring->tail;
177}
178
179static bool ring_empty(struct tb_ring *ring)
180{
181 return ring->head == ring->tail;
182}
183
184/**
185 * ring_write_descriptors() - post frames from ring->queue to the controller
186 *
187 * ring->lock is held.
188 */
189static void ring_write_descriptors(struct tb_ring *ring)
190{
191 struct ring_frame *frame, *n;
192 struct ring_desc *descriptor;
193 list_for_each_entry_safe(frame, n, &ring->queue, list) {
194 if (ring_full(ring))
195 break;
196 list_move_tail(&frame->list, &ring->in_flight);
197 descriptor = &ring->descriptors[ring->head];
198 descriptor->phys = frame->buffer_phy;
199 descriptor->time = 0;
200 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
201 if (ring->is_tx) {
202 descriptor->length = frame->size;
203 descriptor->eof = frame->eof;
204 descriptor->sof = frame->sof;
205 }
206 ring->head = (ring->head + 1) % ring->size;
207 if (ring->is_tx)
208 ring_iowrite_prod(ring, ring->head);
209 else
210 ring_iowrite_cons(ring, ring->head);
211 }
212}
213
214/**
215 * ring_work() - progress completed frames
216 *
217 * If the ring is shutting down then all frames are marked as canceled and
218 * their callbacks are invoked.
219 *
220 * Otherwise we collect all completed frame from the ring buffer, write new
221 * frame to the ring buffer and invoke the callbacks for the completed frames.
222 */
223static void ring_work(struct work_struct *work)
224{
225 struct tb_ring *ring = container_of(work, typeof(*ring), work);
226 struct ring_frame *frame;
227 bool canceled = false;
228 unsigned long flags;
229 LIST_HEAD(done);
230
231 spin_lock_irqsave(&ring->lock, flags);
232
233 if (!ring->running) {
234 /* Move all frames to done and mark them as canceled. */
235 list_splice_tail_init(&ring->in_flight, &done);
236 list_splice_tail_init(&ring->queue, &done);
237 canceled = true;
238 goto invoke_callback;
239 }
240
241 while (!ring_empty(ring)) {
242 if (!(ring->descriptors[ring->tail].flags
243 & RING_DESC_COMPLETED))
244 break;
245 frame = list_first_entry(&ring->in_flight, typeof(*frame),
246 list);
247 list_move_tail(&frame->list, &done);
248 if (!ring->is_tx) {
249 frame->size = ring->descriptors[ring->tail].length;
250 frame->eof = ring->descriptors[ring->tail].eof;
251 frame->sof = ring->descriptors[ring->tail].sof;
252 frame->flags = ring->descriptors[ring->tail].flags;
253 }
254 ring->tail = (ring->tail + 1) % ring->size;
255 }
256 ring_write_descriptors(ring);
257
258invoke_callback:
259 /* allow callbacks to schedule new work */
260 spin_unlock_irqrestore(&ring->lock, flags);
261 while (!list_empty(&done)) {
262 frame = list_first_entry(&done, typeof(*frame), list);
263 /*
264 * The callback may reenqueue or delete frame.
265 * Do not hold on to it.
266 */
267 list_del_init(&frame->list);
268 if (frame->callback)
269 frame->callback(ring, frame, canceled);
270 }
271}
272
273int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
274{
275 unsigned long flags;
276 int ret = 0;
277
278 spin_lock_irqsave(&ring->lock, flags);
279 if (ring->running) {
280 list_add_tail(&frame->list, &ring->queue);
281 ring_write_descriptors(ring);
282 } else {
283 ret = -ESHUTDOWN;
284 }
285 spin_unlock_irqrestore(&ring->lock, flags);
286 return ret;
287}
288EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
289
290/**
291 * tb_ring_poll() - Poll one completed frame from the ring
292 * @ring: Ring to poll
293 *
294 * This function can be called when @start_poll callback of the @ring
295 * has been called. It will read one completed frame from the ring and
296 * return it to the caller. Returns %NULL if there is no more completed
297 * frames.
298 */
299struct ring_frame *tb_ring_poll(struct tb_ring *ring)
300{
301 struct ring_frame *frame = NULL;
302 unsigned long flags;
303
304 spin_lock_irqsave(&ring->lock, flags);
305 if (!ring->running)
306 goto unlock;
307 if (ring_empty(ring))
308 goto unlock;
309
310 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
311 frame = list_first_entry(&ring->in_flight, typeof(*frame),
312 list);
313 list_del_init(&frame->list);
314
315 if (!ring->is_tx) {
316 frame->size = ring->descriptors[ring->tail].length;
317 frame->eof = ring->descriptors[ring->tail].eof;
318 frame->sof = ring->descriptors[ring->tail].sof;
319 frame->flags = ring->descriptors[ring->tail].flags;
320 }
321
322 ring->tail = (ring->tail + 1) % ring->size;
323 }
324
325unlock:
326 spin_unlock_irqrestore(&ring->lock, flags);
327 return frame;
328}
329EXPORT_SYMBOL_GPL(tb_ring_poll);
330
331static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
332{
333 int idx = ring_interrupt_index(ring);
334 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
335 int bit = idx % 32;
336 u32 val;
337
338 val = ioread32(ring->nhi->iobase + reg);
339 if (mask)
340 val &= ~BIT(bit);
341 else
342 val |= BIT(bit);
343 iowrite32(val, ring->nhi->iobase + reg);
344}
345
346/* Both @nhi->lock and @ring->lock should be held */
347static void __ring_interrupt(struct tb_ring *ring)
348{
349 if (!ring->running)
350 return;
351
352 if (ring->start_poll) {
353 __ring_interrupt_mask(ring, true);
354 ring->start_poll(ring->poll_data);
355 } else {
356 schedule_work(&ring->work);
357 }
358}
359
360/**
361 * tb_ring_poll_complete() - Re-start interrupt for the ring
362 * @ring: Ring to re-start the interrupt
363 *
364 * This will re-start (unmask) the ring interrupt once the user is done
365 * with polling.
366 */
367void tb_ring_poll_complete(struct tb_ring *ring)
368{
369 unsigned long flags;
370
371 spin_lock_irqsave(&ring->nhi->lock, flags);
372 spin_lock(&ring->lock);
373 if (ring->start_poll)
374 __ring_interrupt_mask(ring, false);
375 spin_unlock(&ring->lock);
376 spin_unlock_irqrestore(&ring->nhi->lock, flags);
377}
378EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
379
380static irqreturn_t ring_msix(int irq, void *data)
381{
382 struct tb_ring *ring = data;
383
384 spin_lock(&ring->nhi->lock);
385 spin_lock(&ring->lock);
386 __ring_interrupt(ring);
387 spin_unlock(&ring->lock);
388 spin_unlock(&ring->nhi->lock);
389
390 return IRQ_HANDLED;
391}
392
393static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
394{
395 struct tb_nhi *nhi = ring->nhi;
396 unsigned long irqflags;
397 int ret;
398
399 if (!nhi->pdev->msix_enabled)
400 return 0;
401
402 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
403 if (ret < 0)
404 return ret;
405
406 ring->vector = ret;
407
408 ring->irq = pci_irq_vector(ring->nhi->pdev, ring->vector);
409 if (ring->irq < 0)
410 return ring->irq;
411
412 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
413 return request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
414}
415
416static void ring_release_msix(struct tb_ring *ring)
417{
418 if (ring->irq <= 0)
419 return;
420
421 free_irq(ring->irq, ring);
422 ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
423 ring->vector = 0;
424 ring->irq = 0;
425}
426
427static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
428{
429 int ret = 0;
430
431 spin_lock_irq(&nhi->lock);
432
433 if (ring->hop < 0) {
434 unsigned int i;
435
436 /*
437 * Automatically allocate HopID from the non-reserved
438 * range 1 .. hop_count - 1.
439 */
440 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
441 if (ring->is_tx) {
442 if (!nhi->tx_rings[i]) {
443 ring->hop = i;
444 break;
445 }
446 } else {
447 if (!nhi->rx_rings[i]) {
448 ring->hop = i;
449 break;
450 }
451 }
452 }
453 }
454
455 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
456 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
457 ret = -EINVAL;
458 goto err_unlock;
459 }
460 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
461 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
462 ring->hop);
463 ret = -EBUSY;
464 goto err_unlock;
465 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
466 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
467 ring->hop);
468 ret = -EBUSY;
469 goto err_unlock;
470 }
471
472 if (ring->is_tx)
473 nhi->tx_rings[ring->hop] = ring;
474 else
475 nhi->rx_rings[ring->hop] = ring;
476
477err_unlock:
478 spin_unlock_irq(&nhi->lock);
479
480 return ret;
481}
482
483static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
484 bool transmit, unsigned int flags,
485 u16 sof_mask, u16 eof_mask,
486 void (*start_poll)(void *),
487 void *poll_data)
488{
489 struct tb_ring *ring = NULL;
490
491 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
492 transmit ? "TX" : "RX", hop, size);
493
494 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
495 if (!ring)
496 return NULL;
497
498 spin_lock_init(&ring->lock);
499 INIT_LIST_HEAD(&ring->queue);
500 INIT_LIST_HEAD(&ring->in_flight);
501 INIT_WORK(&ring->work, ring_work);
502
503 ring->nhi = nhi;
504 ring->hop = hop;
505 ring->is_tx = transmit;
506 ring->size = size;
507 ring->flags = flags;
508 ring->sof_mask = sof_mask;
509 ring->eof_mask = eof_mask;
510 ring->head = 0;
511 ring->tail = 0;
512 ring->running = false;
513 ring->start_poll = start_poll;
514 ring->poll_data = poll_data;
515
516 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
517 size * sizeof(*ring->descriptors),
518 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
519 if (!ring->descriptors)
520 goto err_free_ring;
521
522 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
523 goto err_free_descs;
524
525 if (nhi_alloc_hop(nhi, ring))
526 goto err_release_msix;
527
528 return ring;
529
530err_release_msix:
531 ring_release_msix(ring);
532err_free_descs:
533 dma_free_coherent(&ring->nhi->pdev->dev,
534 ring->size * sizeof(*ring->descriptors),
535 ring->descriptors, ring->descriptors_dma);
536err_free_ring:
537 kfree(ring);
538
539 return NULL;
540}
541
542/**
543 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
544 * @nhi: Pointer to the NHI the ring is to be allocated
545 * @hop: HopID (ring) to allocate
546 * @size: Number of entries in the ring
547 * @flags: Flags for the ring
548 */
549struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
550 unsigned int flags)
551{
552 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, NULL, NULL);
553}
554EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
555
556/**
557 * tb_ring_alloc_rx() - Allocate DMA ring for receive
558 * @nhi: Pointer to the NHI the ring is to be allocated
559 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
560 * @size: Number of entries in the ring
561 * @flags: Flags for the ring
562 * @sof_mask: Mask of PDF values that start a frame
563 * @eof_mask: Mask of PDF values that end a frame
564 * @start_poll: If not %NULL the ring will call this function when an
565 * interrupt is triggered and masked, instead of callback
566 * in each Rx frame.
567 * @poll_data: Optional data passed to @start_poll
568 */
569struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
570 unsigned int flags, u16 sof_mask, u16 eof_mask,
571 void (*start_poll)(void *), void *poll_data)
572{
573 return tb_ring_alloc(nhi, hop, size, false, flags, sof_mask, eof_mask,
574 start_poll, poll_data);
575}
576EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
577
578/**
579 * tb_ring_start() - enable a ring
580 *
581 * Must not be invoked in parallel with tb_ring_stop().
582 */
583void tb_ring_start(struct tb_ring *ring)
584{
585 u16 frame_size;
586 u32 flags;
587
588 spin_lock_irq(&ring->nhi->lock);
589 spin_lock(&ring->lock);
590 if (ring->nhi->going_away)
591 goto err;
592 if (ring->running) {
593 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
594 goto err;
595 }
596 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
597 RING_TYPE(ring), ring->hop);
598
599 if (ring->flags & RING_FLAG_FRAME) {
600 /* Means 4096 */
601 frame_size = 0;
602 flags = RING_FLAG_ENABLE;
603 } else {
604 frame_size = TB_FRAME_SIZE;
605 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
606 }
607
608 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
609 if (ring->is_tx) {
610 ring_iowrite32desc(ring, ring->size, 12);
611 ring_iowrite32options(ring, 0, 4); /* time releated ? */
612 ring_iowrite32options(ring, flags, 0);
613 } else {
614 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
615
616 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
617 ring_iowrite32options(ring, sof_eof_mask, 4);
618 ring_iowrite32options(ring, flags, 0);
619 }
620 ring_interrupt_active(ring, true);
621 ring->running = true;
622err:
623 spin_unlock(&ring->lock);
624 spin_unlock_irq(&ring->nhi->lock);
625}
626EXPORT_SYMBOL_GPL(tb_ring_start);
627
628/**
629 * tb_ring_stop() - shutdown a ring
630 *
631 * Must not be invoked from a callback.
632 *
633 * This method will disable the ring. Further calls to
634 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
635 * called.
636 *
637 * All enqueued frames will be canceled and their callbacks will be executed
638 * with frame->canceled set to true (on the callback thread). This method
639 * returns only after all callback invocations have finished.
640 */
641void tb_ring_stop(struct tb_ring *ring)
642{
643 spin_lock_irq(&ring->nhi->lock);
644 spin_lock(&ring->lock);
645 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
646 RING_TYPE(ring), ring->hop);
647 if (ring->nhi->going_away)
648 goto err;
649 if (!ring->running) {
650 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
651 RING_TYPE(ring), ring->hop);
652 goto err;
653 }
654 ring_interrupt_active(ring, false);
655
656 ring_iowrite32options(ring, 0, 0);
657 ring_iowrite64desc(ring, 0, 0);
658 ring_iowrite32desc(ring, 0, 8);
659 ring_iowrite32desc(ring, 0, 12);
660 ring->head = 0;
661 ring->tail = 0;
662 ring->running = false;
663
664err:
665 spin_unlock(&ring->lock);
666 spin_unlock_irq(&ring->nhi->lock);
667
668 /*
669 * schedule ring->work to invoke callbacks on all remaining frames.
670 */
671 schedule_work(&ring->work);
672 flush_work(&ring->work);
673}
674EXPORT_SYMBOL_GPL(tb_ring_stop);
675
676/*
677 * tb_ring_free() - free ring
678 *
679 * When this method returns all invocations of ring->callback will have
680 * finished.
681 *
682 * Ring must be stopped.
683 *
684 * Must NOT be called from ring_frame->callback!
685 */
686void tb_ring_free(struct tb_ring *ring)
687{
688 spin_lock_irq(&ring->nhi->lock);
689 /*
690 * Dissociate the ring from the NHI. This also ensures that
691 * nhi_interrupt_work cannot reschedule ring->work.
692 */
693 if (ring->is_tx)
694 ring->nhi->tx_rings[ring->hop] = NULL;
695 else
696 ring->nhi->rx_rings[ring->hop] = NULL;
697
698 if (ring->running) {
699 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
700 RING_TYPE(ring), ring->hop);
701 }
702 spin_unlock_irq(&ring->nhi->lock);
703
704 ring_release_msix(ring);
705
706 dma_free_coherent(&ring->nhi->pdev->dev,
707 ring->size * sizeof(*ring->descriptors),
708 ring->descriptors, ring->descriptors_dma);
709
710 ring->descriptors = NULL;
711 ring->descriptors_dma = 0;
712
713
714 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
715 ring->hop);
716
717 /**
718 * ring->work can no longer be scheduled (it is scheduled only
719 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
720 * to finish before freeing the ring.
721 */
722 flush_work(&ring->work);
723 kfree(ring);
724}
725EXPORT_SYMBOL_GPL(tb_ring_free);
726
727/**
728 * nhi_mailbox_cmd() - Send a command through NHI mailbox
729 * @nhi: Pointer to the NHI structure
730 * @cmd: Command to send
731 * @data: Data to be send with the command
732 *
733 * Sends mailbox command to the firmware running on NHI. Returns %0 in
734 * case of success and negative errno in case of failure.
735 */
736int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
737{
738 ktime_t timeout;
739 u32 val;
740
741 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
742
743 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
744 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
745 val |= REG_INMAIL_OP_REQUEST | cmd;
746 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
747
748 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
749 do {
750 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
751 if (!(val & REG_INMAIL_OP_REQUEST))
752 break;
753 usleep_range(10, 20);
754 } while (ktime_before(ktime_get(), timeout));
755
756 if (val & REG_INMAIL_OP_REQUEST)
757 return -ETIMEDOUT;
758 if (val & REG_INMAIL_ERROR)
759 return -EIO;
760
761 return 0;
762}
763
764/**
765 * nhi_mailbox_mode() - Return current firmware operation mode
766 * @nhi: Pointer to the NHI structure
767 *
768 * The function reads current firmware operation mode using NHI mailbox
769 * registers and returns it to the caller.
770 */
771enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
772{
773 u32 val;
774
775 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
776 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
777 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
778
779 return (enum nhi_fw_mode)val;
780}
781
782static void nhi_interrupt_work(struct work_struct *work)
783{
784 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
785 int value = 0; /* Suppress uninitialized usage warning. */
786 int bit;
787 int hop = -1;
788 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
789 struct tb_ring *ring;
790
791 spin_lock_irq(&nhi->lock);
792
793 /*
794 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
795 * (TX, RX, RX overflow). We iterate over the bits and read a new
796 * dwords as required. The registers are cleared on read.
797 */
798 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
799 if (bit % 32 == 0)
800 value = ioread32(nhi->iobase
801 + REG_RING_NOTIFY_BASE
802 + 4 * (bit / 32));
803 if (++hop == nhi->hop_count) {
804 hop = 0;
805 type++;
806 }
807 if ((value & (1 << (bit % 32))) == 0)
808 continue;
809 if (type == 2) {
810 dev_warn(&nhi->pdev->dev,
811 "RX overflow for ring %d\n",
812 hop);
813 continue;
814 }
815 if (type == 0)
816 ring = nhi->tx_rings[hop];
817 else
818 ring = nhi->rx_rings[hop];
819 if (ring == NULL) {
820 dev_warn(&nhi->pdev->dev,
821 "got interrupt for inactive %s ring %d\n",
822 type ? "RX" : "TX",
823 hop);
824 continue;
825 }
826
827 spin_lock(&ring->lock);
828 __ring_interrupt(ring);
829 spin_unlock(&ring->lock);
830 }
831 spin_unlock_irq(&nhi->lock);
832}
833
834static irqreturn_t nhi_msi(int irq, void *data)
835{
836 struct tb_nhi *nhi = data;
837 schedule_work(&nhi->interrupt_work);
838 return IRQ_HANDLED;
839}
840
841static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
842{
843 struct pci_dev *pdev = to_pci_dev(dev);
844 struct tb *tb = pci_get_drvdata(pdev);
845 struct tb_nhi *nhi = tb->nhi;
846 int ret;
847
848 ret = tb_domain_suspend_noirq(tb);
849 if (ret)
850 return ret;
851
852 if (nhi->ops && nhi->ops->suspend_noirq) {
853 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
854 if (ret)
855 return ret;
856 }
857
858 return 0;
859}
860
861static int nhi_suspend_noirq(struct device *dev)
862{
863 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
864}
865
866static bool nhi_wake_supported(struct pci_dev *pdev)
867{
868 u8 val;
869
870 /*
871 * If power rails are sustainable for wakeup from S4 this
872 * property is set by the BIOS.
873 */
874 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
875 return !!val;
876
877 return true;
878}
879
880static int nhi_poweroff_noirq(struct device *dev)
881{
882 struct pci_dev *pdev = to_pci_dev(dev);
883 bool wakeup;
884
885 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
886 return __nhi_suspend_noirq(dev, wakeup);
887}
888
889static void nhi_enable_int_throttling(struct tb_nhi *nhi)
890{
891 /* Throttling is specified in 256ns increments */
892 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
893 unsigned int i;
894
895 /*
896 * Configure interrupt throttling for all vectors even if we
897 * only use few.
898 */
899 for (i = 0; i < MSIX_MAX_VECS; i++) {
900 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
901 iowrite32(throttle, nhi->iobase + reg);
902 }
903}
904
905static int nhi_resume_noirq(struct device *dev)
906{
907 struct pci_dev *pdev = to_pci_dev(dev);
908 struct tb *tb = pci_get_drvdata(pdev);
909 struct tb_nhi *nhi = tb->nhi;
910 int ret;
911
912 /*
913 * Check that the device is still there. It may be that the user
914 * unplugged last device which causes the host controller to go
915 * away on PCs.
916 */
917 if (!pci_device_is_present(pdev)) {
918 nhi->going_away = true;
919 } else {
920 if (nhi->ops && nhi->ops->resume_noirq) {
921 ret = nhi->ops->resume_noirq(nhi);
922 if (ret)
923 return ret;
924 }
925 nhi_enable_int_throttling(tb->nhi);
926 }
927
928 return tb_domain_resume_noirq(tb);
929}
930
931static int nhi_suspend(struct device *dev)
932{
933 struct pci_dev *pdev = to_pci_dev(dev);
934 struct tb *tb = pci_get_drvdata(pdev);
935
936 return tb_domain_suspend(tb);
937}
938
939static void nhi_complete(struct device *dev)
940{
941 struct pci_dev *pdev = to_pci_dev(dev);
942 struct tb *tb = pci_get_drvdata(pdev);
943
944 /*
945 * If we were runtime suspended when system suspend started,
946 * schedule runtime resume now. It should bring the domain back
947 * to functional state.
948 */
949 if (pm_runtime_suspended(&pdev->dev))
950 pm_runtime_resume(&pdev->dev);
951 else
952 tb_domain_complete(tb);
953}
954
955static int nhi_runtime_suspend(struct device *dev)
956{
957 struct pci_dev *pdev = to_pci_dev(dev);
958 struct tb *tb = pci_get_drvdata(pdev);
959 struct tb_nhi *nhi = tb->nhi;
960 int ret;
961
962 ret = tb_domain_runtime_suspend(tb);
963 if (ret)
964 return ret;
965
966 if (nhi->ops && nhi->ops->runtime_suspend) {
967 ret = nhi->ops->runtime_suspend(tb->nhi);
968 if (ret)
969 return ret;
970 }
971 return 0;
972}
973
974static int nhi_runtime_resume(struct device *dev)
975{
976 struct pci_dev *pdev = to_pci_dev(dev);
977 struct tb *tb = pci_get_drvdata(pdev);
978 struct tb_nhi *nhi = tb->nhi;
979 int ret;
980
981 if (nhi->ops && nhi->ops->runtime_resume) {
982 ret = nhi->ops->runtime_resume(nhi);
983 if (ret)
984 return ret;
985 }
986
987 nhi_enable_int_throttling(nhi);
988 return tb_domain_runtime_resume(tb);
989}
990
991static void nhi_shutdown(struct tb_nhi *nhi)
992{
993 int i;
994
995 dev_dbg(&nhi->pdev->dev, "shutdown\n");
996
997 for (i = 0; i < nhi->hop_count; i++) {
998 if (nhi->tx_rings[i])
999 dev_WARN(&nhi->pdev->dev,
1000 "TX ring %d is still active\n", i);
1001 if (nhi->rx_rings[i])
1002 dev_WARN(&nhi->pdev->dev,
1003 "RX ring %d is still active\n", i);
1004 }
1005 nhi_disable_interrupts(nhi);
1006 /*
1007 * We have to release the irq before calling flush_work. Otherwise an
1008 * already executing IRQ handler could call schedule_work again.
1009 */
1010 if (!nhi->pdev->msix_enabled) {
1011 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1012 flush_work(&nhi->interrupt_work);
1013 }
1014 ida_destroy(&nhi->msix_ida);
1015
1016 if (nhi->ops && nhi->ops->shutdown)
1017 nhi->ops->shutdown(nhi);
1018}
1019
1020static int nhi_init_msi(struct tb_nhi *nhi)
1021{
1022 struct pci_dev *pdev = nhi->pdev;
1023 int res, irq, nvec;
1024
1025 /* In case someone left them on. */
1026 nhi_disable_interrupts(nhi);
1027
1028 nhi_enable_int_throttling(nhi);
1029
1030 ida_init(&nhi->msix_ida);
1031
1032 /*
1033 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1034 * get all MSI-X vectors and if we succeed, each ring will have
1035 * one MSI-X. If for some reason that does not work out, we
1036 * fallback to a single MSI.
1037 */
1038 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1039 PCI_IRQ_MSIX);
1040 if (nvec < 0) {
1041 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1042 if (nvec < 0)
1043 return nvec;
1044
1045 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1046
1047 irq = pci_irq_vector(nhi->pdev, 0);
1048 if (irq < 0)
1049 return irq;
1050
1051 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1052 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1053 if (res) {
1054 dev_err(&pdev->dev, "request_irq failed, aborting\n");
1055 return res;
1056 }
1057 }
1058
1059 return 0;
1060}
1061
1062static bool nhi_imr_valid(struct pci_dev *pdev)
1063{
1064 u8 val;
1065
1066 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1067 return !!val;
1068
1069 return true;
1070}
1071
1072static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1073{
1074 struct tb_nhi *nhi;
1075 struct tb *tb;
1076 int res;
1077
1078 if (!nhi_imr_valid(pdev)) {
1079 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1080 return -ENODEV;
1081 }
1082
1083 res = pcim_enable_device(pdev);
1084 if (res) {
1085 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1086 return res;
1087 }
1088
1089 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1090 if (res) {
1091 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1092 return res;
1093 }
1094
1095 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1096 if (!nhi)
1097 return -ENOMEM;
1098
1099 nhi->pdev = pdev;
1100 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1101 /* cannot fail - table is allocated bin pcim_iomap_regions */
1102 nhi->iobase = pcim_iomap_table(pdev)[0];
1103 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1104 dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count);
1105
1106 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1107 sizeof(*nhi->tx_rings), GFP_KERNEL);
1108 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1109 sizeof(*nhi->rx_rings), GFP_KERNEL);
1110 if (!nhi->tx_rings || !nhi->rx_rings)
1111 return -ENOMEM;
1112
1113 res = nhi_init_msi(nhi);
1114 if (res) {
1115 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1116 return res;
1117 }
1118
1119 spin_lock_init(&nhi->lock);
1120
1121 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1122 if (res)
1123 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1124 if (res) {
1125 dev_err(&pdev->dev, "failed to set DMA mask\n");
1126 return res;
1127 }
1128
1129 pci_set_master(pdev);
1130
1131 if (nhi->ops && nhi->ops->init) {
1132 res = nhi->ops->init(nhi);
1133 if (res)
1134 return res;
1135 }
1136
1137 tb = icm_probe(nhi);
1138 if (!tb)
1139 tb = tb_probe(nhi);
1140 if (!tb) {
1141 dev_err(&nhi->pdev->dev,
1142 "failed to determine connection manager, aborting\n");
1143 return -ENODEV;
1144 }
1145
1146 dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1147
1148 res = tb_domain_add(tb);
1149 if (res) {
1150 /*
1151 * At this point the RX/TX rings might already have been
1152 * activated. Do a proper shutdown.
1153 */
1154 tb_domain_put(tb);
1155 nhi_shutdown(nhi);
1156 return res;
1157 }
1158 pci_set_drvdata(pdev, tb);
1159
1160 pm_runtime_allow(&pdev->dev);
1161 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1162 pm_runtime_use_autosuspend(&pdev->dev);
1163 pm_runtime_put_autosuspend(&pdev->dev);
1164
1165 return 0;
1166}
1167
1168static void nhi_remove(struct pci_dev *pdev)
1169{
1170 struct tb *tb = pci_get_drvdata(pdev);
1171 struct tb_nhi *nhi = tb->nhi;
1172
1173 pm_runtime_get_sync(&pdev->dev);
1174 pm_runtime_dont_use_autosuspend(&pdev->dev);
1175 pm_runtime_forbid(&pdev->dev);
1176
1177 tb_domain_remove(tb);
1178 nhi_shutdown(nhi);
1179}
1180
1181/*
1182 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1183 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1184 * resume_noirq until we are done.
1185 */
1186static const struct dev_pm_ops nhi_pm_ops = {
1187 .suspend_noirq = nhi_suspend_noirq,
1188 .resume_noirq = nhi_resume_noirq,
1189 .freeze_noirq = nhi_suspend_noirq, /*
1190 * we just disable hotplug, the
1191 * pci-tunnels stay alive.
1192 */
1193 .thaw_noirq = nhi_resume_noirq,
1194 .restore_noirq = nhi_resume_noirq,
1195 .suspend = nhi_suspend,
1196 .freeze = nhi_suspend,
1197 .poweroff_noirq = nhi_poweroff_noirq,
1198 .poweroff = nhi_suspend,
1199 .complete = nhi_complete,
1200 .runtime_suspend = nhi_runtime_suspend,
1201 .runtime_resume = nhi_runtime_resume,
1202};
1203
1204static struct pci_device_id nhi_ids[] = {
1205 /*
1206 * We have to specify class, the TB bridges use the same device and
1207 * vendor (sub)id on gen 1 and gen 2 controllers.
1208 */
1209 {
1210 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1211 .vendor = PCI_VENDOR_ID_INTEL,
1212 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1213 .subvendor = 0x2222, .subdevice = 0x1111,
1214 },
1215 {
1216 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1217 .vendor = PCI_VENDOR_ID_INTEL,
1218 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1219 .subvendor = 0x2222, .subdevice = 0x1111,
1220 },
1221 {
1222 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1223 .vendor = PCI_VENDOR_ID_INTEL,
1224 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1225 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1226 },
1227 {
1228 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1229 .vendor = PCI_VENDOR_ID_INTEL,
1230 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1231 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1232 },
1233
1234 /* Thunderbolt 3 */
1235 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1236 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1237 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1238 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1239 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1240 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1241 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1242 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1243 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1244 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1245 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1246 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1247 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1248 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1249 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1250 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1251 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1252 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1253
1254 /* Any USB4 compliant host */
1255 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1256
1257 { 0,}
1258};
1259
1260MODULE_DEVICE_TABLE(pci, nhi_ids);
1261MODULE_LICENSE("GPL");
1262
1263static struct pci_driver nhi_driver = {
1264 .name = "thunderbolt",
1265 .id_table = nhi_ids,
1266 .probe = nhi_probe,
1267 .remove = nhi_remove,
1268 .shutdown = nhi_remove,
1269 .driver.pm = &nhi_pm_ops,
1270};
1271
1272static int __init nhi_init(void)
1273{
1274 int ret;
1275
1276 ret = tb_domain_init();
1277 if (ret)
1278 return ret;
1279 ret = pci_register_driver(&nhi_driver);
1280 if (ret)
1281 tb_domain_exit();
1282 return ret;
1283}
1284
1285static void __exit nhi_unload(void)
1286{
1287 pci_unregister_driver(&nhi_driver);
1288 tb_domain_exit();
1289}
1290
1291rootfs_initcall(nhi_init);
1292module_exit(nhi_unload);