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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
7 *
8 * Driver for Semtech SX150X I2C GPIO Expanders
9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
10 *
11 * Author: Gregory Bean <gbean@codeaurora.org>
12 */
13
14#include <linux/regmap.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/mutex.h>
20#include <linux/slab.h>
21#include <linux/of.h>
22#include <linux/gpio/driver.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26#include <linux/pinctrl/pinconf-generic.h>
27
28#include "core.h"
29#include "pinconf.h"
30#include "pinctrl-utils.h"
31
32/* The chip models of sx150x */
33enum {
34 SX150X_123 = 0,
35 SX150X_456,
36 SX150X_789,
37};
38enum {
39 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
40 SX150X_MAX_REGISTER = 0xad,
41 SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
42 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
43 SX150X_789_RESET_KEY1 = 0x12,
44 SX150X_789_RESET_KEY2 = 0x34,
45};
46
47struct sx150x_123_pri {
48 u8 reg_pld_mode;
49 u8 reg_pld_table0;
50 u8 reg_pld_table1;
51 u8 reg_pld_table2;
52 u8 reg_pld_table3;
53 u8 reg_pld_table4;
54 u8 reg_advanced;
55};
56
57struct sx150x_456_pri {
58 u8 reg_pld_mode;
59 u8 reg_pld_table0;
60 u8 reg_pld_table1;
61 u8 reg_pld_table2;
62 u8 reg_pld_table3;
63 u8 reg_pld_table4;
64 u8 reg_advanced;
65};
66
67struct sx150x_789_pri {
68 u8 reg_drain;
69 u8 reg_polarity;
70 u8 reg_clock;
71 u8 reg_misc;
72 u8 reg_reset;
73 u8 ngpios;
74};
75
76struct sx150x_device_data {
77 u8 model;
78 u8 reg_pullup;
79 u8 reg_pulldn;
80 u8 reg_dir;
81 u8 reg_data;
82 u8 reg_irq_mask;
83 u8 reg_irq_src;
84 u8 reg_sense;
85 u8 ngpios;
86 union {
87 struct sx150x_123_pri x123;
88 struct sx150x_456_pri x456;
89 struct sx150x_789_pri x789;
90 } pri;
91 const struct pinctrl_pin_desc *pins;
92 unsigned int npins;
93};
94
95struct sx150x_pinctrl {
96 struct device *dev;
97 struct i2c_client *client;
98 struct pinctrl_dev *pctldev;
99 struct pinctrl_desc pinctrl_desc;
100 struct gpio_chip gpio;
101 struct regmap *regmap;
102 struct {
103 u32 sense;
104 u32 masked;
105 } irq;
106 struct mutex lock;
107 const struct sx150x_device_data *data;
108};
109
110static const struct pinctrl_pin_desc sx150x_4_pins[] = {
111 PINCTRL_PIN(0, "gpio0"),
112 PINCTRL_PIN(1, "gpio1"),
113 PINCTRL_PIN(2, "gpio2"),
114 PINCTRL_PIN(3, "gpio3"),
115 PINCTRL_PIN(4, "oscio"),
116};
117
118static const struct pinctrl_pin_desc sx150x_8_pins[] = {
119 PINCTRL_PIN(0, "gpio0"),
120 PINCTRL_PIN(1, "gpio1"),
121 PINCTRL_PIN(2, "gpio2"),
122 PINCTRL_PIN(3, "gpio3"),
123 PINCTRL_PIN(4, "gpio4"),
124 PINCTRL_PIN(5, "gpio5"),
125 PINCTRL_PIN(6, "gpio6"),
126 PINCTRL_PIN(7, "gpio7"),
127 PINCTRL_PIN(8, "oscio"),
128};
129
130static const struct pinctrl_pin_desc sx150x_16_pins[] = {
131 PINCTRL_PIN(0, "gpio0"),
132 PINCTRL_PIN(1, "gpio1"),
133 PINCTRL_PIN(2, "gpio2"),
134 PINCTRL_PIN(3, "gpio3"),
135 PINCTRL_PIN(4, "gpio4"),
136 PINCTRL_PIN(5, "gpio5"),
137 PINCTRL_PIN(6, "gpio6"),
138 PINCTRL_PIN(7, "gpio7"),
139 PINCTRL_PIN(8, "gpio8"),
140 PINCTRL_PIN(9, "gpio9"),
141 PINCTRL_PIN(10, "gpio10"),
142 PINCTRL_PIN(11, "gpio11"),
143 PINCTRL_PIN(12, "gpio12"),
144 PINCTRL_PIN(13, "gpio13"),
145 PINCTRL_PIN(14, "gpio14"),
146 PINCTRL_PIN(15, "gpio15"),
147 PINCTRL_PIN(16, "oscio"),
148};
149
150static const struct sx150x_device_data sx1501q_device_data = {
151 .model = SX150X_123,
152 .reg_pullup = 0x02,
153 .reg_pulldn = 0x03,
154 .reg_dir = 0x01,
155 .reg_data = 0x00,
156 .reg_irq_mask = 0x05,
157 .reg_irq_src = 0x08,
158 .reg_sense = 0x07,
159 .pri.x123 = {
160 .reg_pld_mode = 0x10,
161 .reg_pld_table0 = 0x11,
162 .reg_pld_table2 = 0x13,
163 .reg_advanced = 0xad,
164 },
165 .ngpios = 4,
166 .pins = sx150x_4_pins,
167 .npins = 4, /* oscio not available */
168};
169
170static const struct sx150x_device_data sx1502q_device_data = {
171 .model = SX150X_123,
172 .reg_pullup = 0x02,
173 .reg_pulldn = 0x03,
174 .reg_dir = 0x01,
175 .reg_data = 0x00,
176 .reg_irq_mask = 0x05,
177 .reg_irq_src = 0x08,
178 .reg_sense = 0x06,
179 .pri.x123 = {
180 .reg_pld_mode = 0x10,
181 .reg_pld_table0 = 0x11,
182 .reg_pld_table1 = 0x12,
183 .reg_pld_table2 = 0x13,
184 .reg_pld_table3 = 0x14,
185 .reg_pld_table4 = 0x15,
186 .reg_advanced = 0xad,
187 },
188 .ngpios = 8,
189 .pins = sx150x_8_pins,
190 .npins = 8, /* oscio not available */
191};
192
193static const struct sx150x_device_data sx1503q_device_data = {
194 .model = SX150X_123,
195 .reg_pullup = 0x04,
196 .reg_pulldn = 0x06,
197 .reg_dir = 0x02,
198 .reg_data = 0x00,
199 .reg_irq_mask = 0x08,
200 .reg_irq_src = 0x0e,
201 .reg_sense = 0x0a,
202 .pri.x123 = {
203 .reg_pld_mode = 0x20,
204 .reg_pld_table0 = 0x22,
205 .reg_pld_table1 = 0x24,
206 .reg_pld_table2 = 0x26,
207 .reg_pld_table3 = 0x28,
208 .reg_pld_table4 = 0x2a,
209 .reg_advanced = 0xad,
210 },
211 .ngpios = 16,
212 .pins = sx150x_16_pins,
213 .npins = 16, /* oscio not available */
214};
215
216static const struct sx150x_device_data sx1504q_device_data = {
217 .model = SX150X_456,
218 .reg_pullup = 0x02,
219 .reg_pulldn = 0x03,
220 .reg_dir = 0x01,
221 .reg_data = 0x00,
222 .reg_irq_mask = 0x05,
223 .reg_irq_src = 0x08,
224 .reg_sense = 0x07,
225 .pri.x456 = {
226 .reg_pld_mode = 0x10,
227 .reg_pld_table0 = 0x11,
228 .reg_pld_table2 = 0x13,
229 },
230 .ngpios = 4,
231 .pins = sx150x_4_pins,
232 .npins = 4, /* oscio not available */
233};
234
235static const struct sx150x_device_data sx1505q_device_data = {
236 .model = SX150X_456,
237 .reg_pullup = 0x02,
238 .reg_pulldn = 0x03,
239 .reg_dir = 0x01,
240 .reg_data = 0x00,
241 .reg_irq_mask = 0x05,
242 .reg_irq_src = 0x08,
243 .reg_sense = 0x06,
244 .pri.x456 = {
245 .reg_pld_mode = 0x10,
246 .reg_pld_table0 = 0x11,
247 .reg_pld_table1 = 0x12,
248 .reg_pld_table2 = 0x13,
249 .reg_pld_table3 = 0x14,
250 .reg_pld_table4 = 0x15,
251 },
252 .ngpios = 8,
253 .pins = sx150x_8_pins,
254 .npins = 8, /* oscio not available */
255};
256
257static const struct sx150x_device_data sx1506q_device_data = {
258 .model = SX150X_456,
259 .reg_pullup = 0x04,
260 .reg_pulldn = 0x06,
261 .reg_dir = 0x02,
262 .reg_data = 0x00,
263 .reg_irq_mask = 0x08,
264 .reg_irq_src = 0x0e,
265 .reg_sense = 0x0a,
266 .pri.x456 = {
267 .reg_pld_mode = 0x20,
268 .reg_pld_table0 = 0x22,
269 .reg_pld_table1 = 0x24,
270 .reg_pld_table2 = 0x26,
271 .reg_pld_table3 = 0x28,
272 .reg_pld_table4 = 0x2a,
273 .reg_advanced = 0xad,
274 },
275 .ngpios = 16,
276 .pins = sx150x_16_pins,
277 .npins = 16, /* oscio not available */
278};
279
280static const struct sx150x_device_data sx1507q_device_data = {
281 .model = SX150X_789,
282 .reg_pullup = 0x03,
283 .reg_pulldn = 0x04,
284 .reg_dir = 0x07,
285 .reg_data = 0x08,
286 .reg_irq_mask = 0x09,
287 .reg_irq_src = 0x0b,
288 .reg_sense = 0x0a,
289 .pri.x789 = {
290 .reg_drain = 0x05,
291 .reg_polarity = 0x06,
292 .reg_clock = 0x0d,
293 .reg_misc = 0x0e,
294 .reg_reset = 0x7d,
295 },
296 .ngpios = 4,
297 .pins = sx150x_4_pins,
298 .npins = ARRAY_SIZE(sx150x_4_pins),
299};
300
301static const struct sx150x_device_data sx1508q_device_data = {
302 .model = SX150X_789,
303 .reg_pullup = 0x03,
304 .reg_pulldn = 0x04,
305 .reg_dir = 0x07,
306 .reg_data = 0x08,
307 .reg_irq_mask = 0x09,
308 .reg_irq_src = 0x0c,
309 .reg_sense = 0x0a,
310 .pri.x789 = {
311 .reg_drain = 0x05,
312 .reg_polarity = 0x06,
313 .reg_clock = 0x0f,
314 .reg_misc = 0x10,
315 .reg_reset = 0x7d,
316 },
317 .ngpios = 8,
318 .pins = sx150x_8_pins,
319 .npins = ARRAY_SIZE(sx150x_8_pins),
320};
321
322static const struct sx150x_device_data sx1509q_device_data = {
323 .model = SX150X_789,
324 .reg_pullup = 0x06,
325 .reg_pulldn = 0x08,
326 .reg_dir = 0x0e,
327 .reg_data = 0x10,
328 .reg_irq_mask = 0x12,
329 .reg_irq_src = 0x18,
330 .reg_sense = 0x14,
331 .pri.x789 = {
332 .reg_drain = 0x0a,
333 .reg_polarity = 0x0c,
334 .reg_clock = 0x1e,
335 .reg_misc = 0x1f,
336 .reg_reset = 0x7d,
337 },
338 .ngpios = 16,
339 .pins = sx150x_16_pins,
340 .npins = ARRAY_SIZE(sx150x_16_pins),
341};
342
343static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
344{
345 return 0;
346}
347
348static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
349 unsigned int group)
350{
351 return NULL;
352}
353
354static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
355 unsigned int group,
356 const unsigned int **pins,
357 unsigned int *num_pins)
358{
359 return -ENOTSUPP;
360}
361
362static const struct pinctrl_ops sx150x_pinctrl_ops = {
363 .get_groups_count = sx150x_pinctrl_get_groups_count,
364 .get_group_name = sx150x_pinctrl_get_group_name,
365 .get_group_pins = sx150x_pinctrl_get_group_pins,
366#ifdef CONFIG_OF
367 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
368 .dt_free_map = pinctrl_utils_free_map,
369#endif
370};
371
372static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
373{
374 if (pin >= pctl->data->npins)
375 return false;
376
377 /* OSCIO pin is only present in 789 devices */
378 if (pctl->data->model != SX150X_789)
379 return false;
380
381 return !strcmp(pctl->data->pins[pin].name, "oscio");
382}
383
384static int sx150x_gpio_get_direction(struct gpio_chip *chip,
385 unsigned int offset)
386{
387 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
388 unsigned int value;
389 int ret;
390
391 if (sx150x_pin_is_oscio(pctl, offset))
392 return GPIO_LINE_DIRECTION_OUT;
393
394 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
395 if (ret < 0)
396 return ret;
397
398 if (value & BIT(offset))
399 return GPIO_LINE_DIRECTION_IN;
400
401 return GPIO_LINE_DIRECTION_OUT;
402}
403
404static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
405{
406 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
407 unsigned int value;
408 int ret;
409
410 if (sx150x_pin_is_oscio(pctl, offset))
411 return -EINVAL;
412
413 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
414 if (ret < 0)
415 return ret;
416
417 return !!(value & BIT(offset));
418}
419
420static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
421 int value)
422{
423 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
424 BIT(offset), value ? BIT(offset) : 0);
425}
426
427static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
428 int value)
429{
430 return regmap_write(pctl->regmap,
431 pctl->data->pri.x789.reg_clock,
432 (value ? 0x1f : 0x10));
433}
434
435static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
436 int value)
437{
438 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
439
440 if (sx150x_pin_is_oscio(pctl, offset))
441 sx150x_gpio_oscio_set(pctl, value);
442 else
443 __sx150x_gpio_set(pctl, offset, value);
444}
445
446static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
447 unsigned long *mask,
448 unsigned long *bits)
449{
450 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
451
452 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
453}
454
455static int sx150x_gpio_direction_input(struct gpio_chip *chip,
456 unsigned int offset)
457{
458 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
459
460 if (sx150x_pin_is_oscio(pctl, offset))
461 return -EINVAL;
462
463 return regmap_write_bits(pctl->regmap,
464 pctl->data->reg_dir,
465 BIT(offset), BIT(offset));
466}
467
468static int sx150x_gpio_direction_output(struct gpio_chip *chip,
469 unsigned int offset, int value)
470{
471 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
472 int ret;
473
474 if (sx150x_pin_is_oscio(pctl, offset))
475 return sx150x_gpio_oscio_set(pctl, value);
476
477 ret = __sx150x_gpio_set(pctl, offset, value);
478 if (ret < 0)
479 return ret;
480
481 return regmap_write_bits(pctl->regmap,
482 pctl->data->reg_dir,
483 BIT(offset), 0);
484}
485
486static void sx150x_irq_mask(struct irq_data *d)
487{
488 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
489 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
490 unsigned int n = irqd_to_hwirq(d);
491
492 pctl->irq.masked |= BIT(n);
493 gpiochip_disable_irq(gc, n);
494}
495
496static void sx150x_irq_unmask(struct irq_data *d)
497{
498 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
499 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
500 unsigned int n = irqd_to_hwirq(d);
501
502 gpiochip_enable_irq(gc, n);
503 pctl->irq.masked &= ~BIT(n);
504}
505
506static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
507 unsigned int line, unsigned int sense)
508{
509 /*
510 * Every interrupt line is represented by two bits shifted
511 * proportionally to the line number
512 */
513 const unsigned int n = line * 2;
514 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
515 SX150X_IRQ_TYPE_EDGE_FALLING) << n);
516
517 pctl->irq.sense &= mask;
518 pctl->irq.sense |= sense << n;
519}
520
521static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
522{
523 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
524 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
525 unsigned int n, val = 0;
526
527 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
528 return -EINVAL;
529
530 n = irqd_to_hwirq(d);
531
532 if (flow_type & IRQ_TYPE_EDGE_RISING)
533 val |= SX150X_IRQ_TYPE_EDGE_RISING;
534 if (flow_type & IRQ_TYPE_EDGE_FALLING)
535 val |= SX150X_IRQ_TYPE_EDGE_FALLING;
536
537 sx150x_irq_set_sense(pctl, n, val);
538 return 0;
539}
540
541static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
542{
543 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
544 unsigned long n, status;
545 unsigned int val;
546 int err;
547
548 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
549 if (err < 0)
550 return IRQ_NONE;
551
552 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
553 if (err < 0)
554 return IRQ_NONE;
555
556 status = val;
557 for_each_set_bit(n, &status, pctl->data->ngpios)
558 handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
559
560 return IRQ_HANDLED;
561}
562
563static void sx150x_irq_bus_lock(struct irq_data *d)
564{
565 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
566 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
567
568 mutex_lock(&pctl->lock);
569}
570
571static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
572{
573 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
574 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
575
576 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
577 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
578 mutex_unlock(&pctl->lock);
579}
580
581
582static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p)
583{
584 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
585 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
586
587 seq_printf(p, pctl->client->name);
588}
589
590static const struct irq_chip sx150x_irq_chip = {
591 .irq_mask = sx150x_irq_mask,
592 .irq_unmask = sx150x_irq_unmask,
593 .irq_set_type = sx150x_irq_set_type,
594 .irq_bus_lock = sx150x_irq_bus_lock,
595 .irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock,
596 .irq_print_chip = sx150x_irq_print_chip,
597 .flags = IRQCHIP_IMMUTABLE,
598 GPIOCHIP_IRQ_RESOURCE_HELPERS,
599};
600
601static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
602 unsigned long *config)
603{
604 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
605 unsigned int param = pinconf_to_config_param(*config);
606 int ret;
607 u32 arg;
608 unsigned int data;
609
610 if (sx150x_pin_is_oscio(pctl, pin)) {
611 switch (param) {
612 case PIN_CONFIG_DRIVE_PUSH_PULL:
613 case PIN_CONFIG_OUTPUT:
614 ret = regmap_read(pctl->regmap,
615 pctl->data->pri.x789.reg_clock,
616 &data);
617 if (ret < 0)
618 return ret;
619
620 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
621 arg = (data & 0x1f) ? 1 : 0;
622 else {
623 if ((data & 0x1f) == 0x1f)
624 arg = 1;
625 else if ((data & 0x1f) == 0x10)
626 arg = 0;
627 else
628 return -EINVAL;
629 }
630
631 break;
632 default:
633 return -ENOTSUPP;
634 }
635
636 goto out;
637 }
638
639 switch (param) {
640 case PIN_CONFIG_BIAS_PULL_DOWN:
641 ret = regmap_read(pctl->regmap,
642 pctl->data->reg_pulldn,
643 &data);
644 data &= BIT(pin);
645
646 if (ret < 0)
647 return ret;
648
649 if (!ret)
650 return -EINVAL;
651
652 arg = 1;
653 break;
654
655 case PIN_CONFIG_BIAS_PULL_UP:
656 ret = regmap_read(pctl->regmap,
657 pctl->data->reg_pullup,
658 &data);
659 data &= BIT(pin);
660
661 if (ret < 0)
662 return ret;
663
664 if (!ret)
665 return -EINVAL;
666
667 arg = 1;
668 break;
669
670 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
671 if (pctl->data->model != SX150X_789)
672 return -ENOTSUPP;
673
674 ret = regmap_read(pctl->regmap,
675 pctl->data->pri.x789.reg_drain,
676 &data);
677 data &= BIT(pin);
678
679 if (ret < 0)
680 return ret;
681
682 if (!data)
683 return -EINVAL;
684
685 arg = 1;
686 break;
687
688 case PIN_CONFIG_DRIVE_PUSH_PULL:
689 if (pctl->data->model != SX150X_789)
690 arg = true;
691 else {
692 ret = regmap_read(pctl->regmap,
693 pctl->data->pri.x789.reg_drain,
694 &data);
695 data &= BIT(pin);
696
697 if (ret < 0)
698 return ret;
699
700 if (data)
701 return -EINVAL;
702
703 arg = 1;
704 }
705 break;
706
707 case PIN_CONFIG_OUTPUT:
708 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
709 if (ret < 0)
710 return ret;
711
712 if (ret == GPIO_LINE_DIRECTION_IN)
713 return -EINVAL;
714
715 ret = sx150x_gpio_get(&pctl->gpio, pin);
716 if (ret < 0)
717 return ret;
718
719 arg = ret;
720 break;
721
722 default:
723 return -ENOTSUPP;
724 }
725
726out:
727 *config = pinconf_to_config_packed(param, arg);
728
729 return 0;
730}
731
732static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
733 unsigned long *configs, unsigned int num_configs)
734{
735 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
736 enum pin_config_param param;
737 u32 arg;
738 int i;
739 int ret;
740
741 for (i = 0; i < num_configs; i++) {
742 param = pinconf_to_config_param(configs[i]);
743 arg = pinconf_to_config_argument(configs[i]);
744
745 if (sx150x_pin_is_oscio(pctl, pin)) {
746 if (param == PIN_CONFIG_OUTPUT) {
747 ret = sx150x_gpio_direction_output(&pctl->gpio,
748 pin, arg);
749 if (ret < 0)
750 return ret;
751
752 continue;
753 } else
754 return -ENOTSUPP;
755 }
756
757 switch (param) {
758 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
759 case PIN_CONFIG_BIAS_DISABLE:
760 ret = regmap_write_bits(pctl->regmap,
761 pctl->data->reg_pulldn,
762 BIT(pin), 0);
763 if (ret < 0)
764 return ret;
765
766 ret = regmap_write_bits(pctl->regmap,
767 pctl->data->reg_pullup,
768 BIT(pin), 0);
769 if (ret < 0)
770 return ret;
771
772 break;
773
774 case PIN_CONFIG_BIAS_PULL_UP:
775 ret = regmap_write_bits(pctl->regmap,
776 pctl->data->reg_pullup,
777 BIT(pin), BIT(pin));
778 if (ret < 0)
779 return ret;
780
781 break;
782
783 case PIN_CONFIG_BIAS_PULL_DOWN:
784 ret = regmap_write_bits(pctl->regmap,
785 pctl->data->reg_pulldn,
786 BIT(pin), BIT(pin));
787 if (ret < 0)
788 return ret;
789
790 break;
791
792 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
793 if (pctl->data->model != SX150X_789 ||
794 sx150x_pin_is_oscio(pctl, pin))
795 return -ENOTSUPP;
796
797 ret = regmap_write_bits(pctl->regmap,
798 pctl->data->pri.x789.reg_drain,
799 BIT(pin), BIT(pin));
800 if (ret < 0)
801 return ret;
802
803 break;
804
805 case PIN_CONFIG_DRIVE_PUSH_PULL:
806 if (pctl->data->model != SX150X_789 ||
807 sx150x_pin_is_oscio(pctl, pin))
808 return 0;
809
810 ret = regmap_write_bits(pctl->regmap,
811 pctl->data->pri.x789.reg_drain,
812 BIT(pin), 0);
813 if (ret < 0)
814 return ret;
815
816 break;
817
818 case PIN_CONFIG_OUTPUT:
819 ret = sx150x_gpio_direction_output(&pctl->gpio,
820 pin, arg);
821 if (ret < 0)
822 return ret;
823
824 break;
825
826 default:
827 return -ENOTSUPP;
828 }
829 } /* for each config */
830
831 return 0;
832}
833
834static const struct pinconf_ops sx150x_pinconf_ops = {
835 .pin_config_get = sx150x_pinconf_get,
836 .pin_config_set = sx150x_pinconf_set,
837 .is_generic = true,
838};
839
840static const struct i2c_device_id sx150x_id[] = {
841 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
842 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
843 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
844 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
845 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
846 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
847 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
848 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
849 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
850 {}
851};
852
853static const struct of_device_id sx150x_of_match[] = {
854 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
855 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
856 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
857 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
858 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
859 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
860 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
861 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
862 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
863 {},
864};
865
866static int sx150x_reset(struct sx150x_pinctrl *pctl)
867{
868 int err;
869
870 err = i2c_smbus_write_byte_data(pctl->client,
871 pctl->data->pri.x789.reg_reset,
872 SX150X_789_RESET_KEY1);
873 if (err < 0)
874 return err;
875
876 err = i2c_smbus_write_byte_data(pctl->client,
877 pctl->data->pri.x789.reg_reset,
878 SX150X_789_RESET_KEY2);
879 return err;
880}
881
882static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
883{
884 u8 reg, value;
885
886 switch (pctl->data->model) {
887 case SX150X_789:
888 reg = pctl->data->pri.x789.reg_misc;
889 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
890 break;
891 case SX150X_456:
892 reg = pctl->data->pri.x456.reg_advanced;
893 value = 0x00;
894
895 /*
896 * Only SX1506 has RegAdvanced, SX1504/5 are expected
897 * to initialize this offset to zero
898 */
899 if (!reg)
900 return 0;
901 break;
902 case SX150X_123:
903 reg = pctl->data->pri.x123.reg_advanced;
904 value = 0x00;
905 break;
906 default:
907 WARN(1, "Unknown chip model %d\n", pctl->data->model);
908 return -EINVAL;
909 }
910
911 return regmap_write(pctl->regmap, reg, value);
912}
913
914static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
915{
916 const u8 reg[] = {
917 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
918 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
919 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
920 };
921 int err;
922
923 if (pctl->data->model == SX150X_789 &&
924 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
925 err = sx150x_reset(pctl);
926 if (err < 0)
927 return err;
928 }
929
930 err = sx150x_init_misc(pctl);
931 if (err < 0)
932 return err;
933
934 /* Set all pins to work in normal mode */
935 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
936}
937
938static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
939 unsigned int reg)
940{
941 const struct sx150x_device_data *data = pctl->data;
942
943 if (reg == data->reg_sense) {
944 /*
945 * RegSense packs two bits of configuration per GPIO,
946 * so we'd need to read twice as many bits as there
947 * are GPIO in our chip
948 */
949 return 2 * data->ngpios;
950 } else if ((data->model == SX150X_789 &&
951 (reg == data->pri.x789.reg_misc ||
952 reg == data->pri.x789.reg_clock ||
953 reg == data->pri.x789.reg_reset))
954 ||
955 (data->model == SX150X_123 &&
956 reg == data->pri.x123.reg_advanced)
957 ||
958 (data->model == SX150X_456 &&
959 data->pri.x456.reg_advanced &&
960 reg == data->pri.x456.reg_advanced)) {
961 return 8;
962 } else {
963 return data->ngpios;
964 }
965}
966
967static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
968 unsigned int reg, unsigned int val)
969{
970 unsigned int a, b;
971 const struct sx150x_device_data *data = pctl->data;
972
973 /*
974 * Whereas SX1509 presents RegSense in a simple layout as such:
975 * reg [ f f e e d d c c ]
976 * reg + 1 [ b b a a 9 9 8 8 ]
977 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
978 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
979 *
980 * SX1503 and SX1506 deviate from that data layout, instead storing
981 * their contents as follows:
982 *
983 * reg [ f f e e d d c c ]
984 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
985 * reg + 2 [ b b a a 9 9 8 8 ]
986 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
987 *
988 * so, taking that into account, we swap two
989 * inner bytes of a 4-byte result
990 */
991
992 if (reg == data->reg_sense &&
993 data->ngpios == 16 &&
994 (data->model == SX150X_123 ||
995 data->model == SX150X_456)) {
996 a = val & 0x00ff0000;
997 b = val & 0x0000ff00;
998
999 val &= 0xff0000ff;
1000 val |= b << 8;
1001 val |= a >> 8;
1002 }
1003
1004 return val;
1005}
1006
1007/*
1008 * In order to mask the differences between 16 and 8 bit expander
1009 * devices we set up a sligthly ficticious regmap that pretends to be
1010 * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
1011 * pair/quartet) registers and transparently reconstructs those
1012 * registers via multiple I2C/SMBus reads
1013 *
1014 * This way the rest of the driver code, interfacing with the chip via
1015 * regmap API, can work assuming that each GPIO pin is represented by
1016 * a group of bits at an offset proportional to GPIO number within a
1017 * given register.
1018 */
1019static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1020 unsigned int *result)
1021{
1022 int ret, n;
1023 struct sx150x_pinctrl *pctl = context;
1024 struct i2c_client *i2c = pctl->client;
1025 const int width = sx150x_regmap_reg_width(pctl, reg);
1026 unsigned int idx, val;
1027
1028 /*
1029 * There are four potential cases covered by this function:
1030 *
1031 * 1) 8-pin chip, single configuration bit register
1032 *
1033 * This is trivial the code below just needs to read:
1034 * reg [ 7 6 5 4 3 2 1 0 ]
1035 *
1036 * 2) 8-pin chip, double configuration bit register (RegSense)
1037 *
1038 * The read will be done as follows:
1039 * reg [ 7 7 6 6 5 5 4 4 ]
1040 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
1041 *
1042 * 3) 16-pin chip, single configuration bit register
1043 *
1044 * The read will be done as follows:
1045 * reg [ f e d c b a 9 8 ]
1046 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
1047 *
1048 * 4) 16-pin chip, double configuration bit register (RegSense)
1049 *
1050 * The read will be done as follows:
1051 * reg [ f f e e d d c c ]
1052 * reg + 1 [ b b a a 9 9 8 8 ]
1053 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
1054 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
1055 */
1056
1057 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1058 val <<= 8;
1059
1060 ret = i2c_smbus_read_byte_data(i2c, idx);
1061 if (ret < 0)
1062 return ret;
1063
1064 val |= ret;
1065 }
1066
1067 *result = sx150x_maybe_swizzle(pctl, reg, val);
1068
1069 return 0;
1070}
1071
1072static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1073 unsigned int val)
1074{
1075 int ret, n;
1076 struct sx150x_pinctrl *pctl = context;
1077 struct i2c_client *i2c = pctl->client;
1078 const int width = sx150x_regmap_reg_width(pctl, reg);
1079
1080 val = sx150x_maybe_swizzle(pctl, reg, val);
1081
1082 n = (width - 1) & ~7;
1083 do {
1084 const u8 byte = (val >> n) & 0xff;
1085
1086 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1087 if (ret < 0)
1088 return ret;
1089
1090 reg++;
1091 n -= 8;
1092 } while (n >= 0);
1093
1094 return 0;
1095}
1096
1097static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1098{
1099 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1100
1101 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1102}
1103
1104static const struct regmap_config sx150x_regmap_config = {
1105 .reg_bits = 8,
1106 .val_bits = 32,
1107
1108 .cache_type = REGCACHE_RBTREE,
1109
1110 .reg_read = sx150x_regmap_reg_read,
1111 .reg_write = sx150x_regmap_reg_write,
1112
1113 .max_register = SX150X_MAX_REGISTER,
1114 .volatile_reg = sx150x_reg_volatile,
1115};
1116
1117static int sx150x_probe(struct i2c_client *client)
1118{
1119 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1120 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1121 struct device *dev = &client->dev;
1122 struct sx150x_pinctrl *pctl;
1123 int ret;
1124
1125 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1126 return -ENOSYS;
1127
1128 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1129 if (!pctl)
1130 return -ENOMEM;
1131
1132 i2c_set_clientdata(client, pctl);
1133
1134 pctl->dev = dev;
1135 pctl->client = client;
1136
1137 pctl->data = i2c_get_match_data(client);
1138 if (!pctl->data)
1139 return -EINVAL;
1140
1141 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1142 &sx150x_regmap_config);
1143 if (IS_ERR(pctl->regmap)) {
1144 ret = PTR_ERR(pctl->regmap);
1145 dev_err(dev, "Failed to allocate register map: %d\n",
1146 ret);
1147 return ret;
1148 }
1149
1150 mutex_init(&pctl->lock);
1151
1152 ret = sx150x_init_hw(pctl);
1153 if (ret)
1154 return ret;
1155
1156 /* Pinctrl_desc */
1157 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1158 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1159 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1160 pctl->pinctrl_desc.pins = pctl->data->pins;
1161 pctl->pinctrl_desc.npins = pctl->data->npins;
1162 pctl->pinctrl_desc.owner = THIS_MODULE;
1163
1164 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1165 pctl, &pctl->pctldev);
1166 if (ret) {
1167 dev_err(dev, "Failed to register pinctrl device\n");
1168 return ret;
1169 }
1170
1171 /* Register GPIO controller */
1172 pctl->gpio.base = -1;
1173 pctl->gpio.ngpio = pctl->data->npins;
1174 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1175 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1176 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1177 pctl->gpio.get = sx150x_gpio_get;
1178 pctl->gpio.set = sx150x_gpio_set;
1179 pctl->gpio.set_config = gpiochip_generic_config;
1180 pctl->gpio.parent = dev;
1181 pctl->gpio.can_sleep = true;
1182 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1183 if (!pctl->gpio.label)
1184 return -ENOMEM;
1185
1186 /*
1187 * Setting multiple pins is not safe when all pins are not
1188 * handled by the same regmap register. The oscio pin (present
1189 * on the SX150X_789 chips) lives in its own register, so
1190 * would require locking that is not in place at this time.
1191 */
1192 if (pctl->data->model != SX150X_789)
1193 pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1194
1195 /* Add Interrupt support if an irq is specified */
1196 if (client->irq > 0) {
1197 struct gpio_irq_chip *girq;
1198
1199 pctl->irq.masked = ~0;
1200 pctl->irq.sense = 0;
1201 /*
1202 * Because sx150x_irq_threaded_fn invokes all of the
1203 * nested interrupt handlers via handle_nested_irq,
1204 * any "handler" assigned to struct gpio_irq_chip
1205 * below is going to be ignored, so the choice of the
1206 * function does not matter that much.
1207 *
1208 * We set it to handle_bad_irq to avoid confusion,
1209 * plus it will be instantly noticeable if it is ever
1210 * called (should not happen)
1211 */
1212 girq = &pctl->gpio.irq;
1213 gpio_irq_chip_set_chip(girq, &sx150x_irq_chip);
1214 /* This will let us handle the parent IRQ in the driver */
1215 girq->parent_handler = NULL;
1216 girq->num_parents = 0;
1217 girq->parents = NULL;
1218 girq->default_type = IRQ_TYPE_NONE;
1219 girq->handler = handle_bad_irq;
1220 girq->threaded = true;
1221
1222 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1223 sx150x_irq_thread_fn,
1224 IRQF_ONESHOT | IRQF_SHARED |
1225 IRQF_TRIGGER_FALLING,
1226 client->name, pctl);
1227 if (ret < 0)
1228 return ret;
1229 }
1230
1231 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1232 if (ret)
1233 return ret;
1234
1235 /*
1236 * Pin control functions need to be enabled AFTER registering the
1237 * GPIO chip because sx150x_pinconf_set() calls
1238 * sx150x_gpio_direction_output().
1239 */
1240 ret = pinctrl_enable(pctl->pctldev);
1241 if (ret) {
1242 dev_err(dev, "Failed to enable pinctrl device\n");
1243 return ret;
1244 }
1245
1246 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1247 0, 0, pctl->data->npins);
1248 if (ret)
1249 return ret;
1250
1251 return 0;
1252}
1253
1254static struct i2c_driver sx150x_driver = {
1255 .driver = {
1256 .name = "sx150x-pinctrl",
1257 .of_match_table = sx150x_of_match,
1258 },
1259 .probe = sx150x_probe,
1260 .id_table = sx150x_id,
1261};
1262
1263static int __init sx150x_init(void)
1264{
1265 return i2c_add_driver(&sx150x_driver);
1266}
1267subsys_initcall(sx150x_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
7 *
8 * Driver for Semtech SX150X I2C GPIO Expanders
9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
10 *
11 * Author: Gregory Bean <gbean@codeaurora.org>
12 */
13
14#include <linux/regmap.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/mutex.h>
20#include <linux/slab.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/gpio/driver.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/pinctrl/pinconf-generic.h>
28
29#include "core.h"
30#include "pinconf.h"
31#include "pinctrl-utils.h"
32
33/* The chip models of sx150x */
34enum {
35 SX150X_123 = 0,
36 SX150X_456,
37 SX150X_789,
38};
39enum {
40 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
41 SX150X_MAX_REGISTER = 0xad,
42 SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
43 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
44 SX150X_789_RESET_KEY1 = 0x12,
45 SX150X_789_RESET_KEY2 = 0x34,
46};
47
48struct sx150x_123_pri {
49 u8 reg_pld_mode;
50 u8 reg_pld_table0;
51 u8 reg_pld_table1;
52 u8 reg_pld_table2;
53 u8 reg_pld_table3;
54 u8 reg_pld_table4;
55 u8 reg_advanced;
56};
57
58struct sx150x_456_pri {
59 u8 reg_pld_mode;
60 u8 reg_pld_table0;
61 u8 reg_pld_table1;
62 u8 reg_pld_table2;
63 u8 reg_pld_table3;
64 u8 reg_pld_table4;
65 u8 reg_advanced;
66};
67
68struct sx150x_789_pri {
69 u8 reg_drain;
70 u8 reg_polarity;
71 u8 reg_clock;
72 u8 reg_misc;
73 u8 reg_reset;
74 u8 ngpios;
75};
76
77struct sx150x_device_data {
78 u8 model;
79 u8 reg_pullup;
80 u8 reg_pulldn;
81 u8 reg_dir;
82 u8 reg_data;
83 u8 reg_irq_mask;
84 u8 reg_irq_src;
85 u8 reg_sense;
86 u8 ngpios;
87 union {
88 struct sx150x_123_pri x123;
89 struct sx150x_456_pri x456;
90 struct sx150x_789_pri x789;
91 } pri;
92 const struct pinctrl_pin_desc *pins;
93 unsigned int npins;
94};
95
96struct sx150x_pinctrl {
97 struct device *dev;
98 struct i2c_client *client;
99 struct pinctrl_dev *pctldev;
100 struct pinctrl_desc pinctrl_desc;
101 struct gpio_chip gpio;
102 struct irq_chip irq_chip;
103 struct regmap *regmap;
104 struct {
105 u32 sense;
106 u32 masked;
107 } irq;
108 struct mutex lock;
109 const struct sx150x_device_data *data;
110};
111
112static const struct pinctrl_pin_desc sx150x_4_pins[] = {
113 PINCTRL_PIN(0, "gpio0"),
114 PINCTRL_PIN(1, "gpio1"),
115 PINCTRL_PIN(2, "gpio2"),
116 PINCTRL_PIN(3, "gpio3"),
117 PINCTRL_PIN(4, "oscio"),
118};
119
120static const struct pinctrl_pin_desc sx150x_8_pins[] = {
121 PINCTRL_PIN(0, "gpio0"),
122 PINCTRL_PIN(1, "gpio1"),
123 PINCTRL_PIN(2, "gpio2"),
124 PINCTRL_PIN(3, "gpio3"),
125 PINCTRL_PIN(4, "gpio4"),
126 PINCTRL_PIN(5, "gpio5"),
127 PINCTRL_PIN(6, "gpio6"),
128 PINCTRL_PIN(7, "gpio7"),
129 PINCTRL_PIN(8, "oscio"),
130};
131
132static const struct pinctrl_pin_desc sx150x_16_pins[] = {
133 PINCTRL_PIN(0, "gpio0"),
134 PINCTRL_PIN(1, "gpio1"),
135 PINCTRL_PIN(2, "gpio2"),
136 PINCTRL_PIN(3, "gpio3"),
137 PINCTRL_PIN(4, "gpio4"),
138 PINCTRL_PIN(5, "gpio5"),
139 PINCTRL_PIN(6, "gpio6"),
140 PINCTRL_PIN(7, "gpio7"),
141 PINCTRL_PIN(8, "gpio8"),
142 PINCTRL_PIN(9, "gpio9"),
143 PINCTRL_PIN(10, "gpio10"),
144 PINCTRL_PIN(11, "gpio11"),
145 PINCTRL_PIN(12, "gpio12"),
146 PINCTRL_PIN(13, "gpio13"),
147 PINCTRL_PIN(14, "gpio14"),
148 PINCTRL_PIN(15, "gpio15"),
149 PINCTRL_PIN(16, "oscio"),
150};
151
152static const struct sx150x_device_data sx1501q_device_data = {
153 .model = SX150X_123,
154 .reg_pullup = 0x02,
155 .reg_pulldn = 0x03,
156 .reg_dir = 0x01,
157 .reg_data = 0x00,
158 .reg_irq_mask = 0x05,
159 .reg_irq_src = 0x08,
160 .reg_sense = 0x07,
161 .pri.x123 = {
162 .reg_pld_mode = 0x10,
163 .reg_pld_table0 = 0x11,
164 .reg_pld_table2 = 0x13,
165 .reg_advanced = 0xad,
166 },
167 .ngpios = 4,
168 .pins = sx150x_4_pins,
169 .npins = 4, /* oscio not available */
170};
171
172static const struct sx150x_device_data sx1502q_device_data = {
173 .model = SX150X_123,
174 .reg_pullup = 0x02,
175 .reg_pulldn = 0x03,
176 .reg_dir = 0x01,
177 .reg_data = 0x00,
178 .reg_irq_mask = 0x05,
179 .reg_irq_src = 0x08,
180 .reg_sense = 0x06,
181 .pri.x123 = {
182 .reg_pld_mode = 0x10,
183 .reg_pld_table0 = 0x11,
184 .reg_pld_table1 = 0x12,
185 .reg_pld_table2 = 0x13,
186 .reg_pld_table3 = 0x14,
187 .reg_pld_table4 = 0x15,
188 .reg_advanced = 0xad,
189 },
190 .ngpios = 8,
191 .pins = sx150x_8_pins,
192 .npins = 8, /* oscio not available */
193};
194
195static const struct sx150x_device_data sx1503q_device_data = {
196 .model = SX150X_123,
197 .reg_pullup = 0x04,
198 .reg_pulldn = 0x06,
199 .reg_dir = 0x02,
200 .reg_data = 0x00,
201 .reg_irq_mask = 0x08,
202 .reg_irq_src = 0x0e,
203 .reg_sense = 0x0a,
204 .pri.x123 = {
205 .reg_pld_mode = 0x20,
206 .reg_pld_table0 = 0x22,
207 .reg_pld_table1 = 0x24,
208 .reg_pld_table2 = 0x26,
209 .reg_pld_table3 = 0x28,
210 .reg_pld_table4 = 0x2a,
211 .reg_advanced = 0xad,
212 },
213 .ngpios = 16,
214 .pins = sx150x_16_pins,
215 .npins = 16, /* oscio not available */
216};
217
218static const struct sx150x_device_data sx1504q_device_data = {
219 .model = SX150X_456,
220 .reg_pullup = 0x02,
221 .reg_pulldn = 0x03,
222 .reg_dir = 0x01,
223 .reg_data = 0x00,
224 .reg_irq_mask = 0x05,
225 .reg_irq_src = 0x08,
226 .reg_sense = 0x07,
227 .pri.x456 = {
228 .reg_pld_mode = 0x10,
229 .reg_pld_table0 = 0x11,
230 .reg_pld_table2 = 0x13,
231 },
232 .ngpios = 4,
233 .pins = sx150x_4_pins,
234 .npins = 4, /* oscio not available */
235};
236
237static const struct sx150x_device_data sx1505q_device_data = {
238 .model = SX150X_456,
239 .reg_pullup = 0x02,
240 .reg_pulldn = 0x03,
241 .reg_dir = 0x01,
242 .reg_data = 0x00,
243 .reg_irq_mask = 0x05,
244 .reg_irq_src = 0x08,
245 .reg_sense = 0x06,
246 .pri.x456 = {
247 .reg_pld_mode = 0x10,
248 .reg_pld_table0 = 0x11,
249 .reg_pld_table1 = 0x12,
250 .reg_pld_table2 = 0x13,
251 .reg_pld_table3 = 0x14,
252 .reg_pld_table4 = 0x15,
253 },
254 .ngpios = 8,
255 .pins = sx150x_8_pins,
256 .npins = 8, /* oscio not available */
257};
258
259static const struct sx150x_device_data sx1506q_device_data = {
260 .model = SX150X_456,
261 .reg_pullup = 0x04,
262 .reg_pulldn = 0x06,
263 .reg_dir = 0x02,
264 .reg_data = 0x00,
265 .reg_irq_mask = 0x08,
266 .reg_irq_src = 0x0e,
267 .reg_sense = 0x0a,
268 .pri.x456 = {
269 .reg_pld_mode = 0x20,
270 .reg_pld_table0 = 0x22,
271 .reg_pld_table1 = 0x24,
272 .reg_pld_table2 = 0x26,
273 .reg_pld_table3 = 0x28,
274 .reg_pld_table4 = 0x2a,
275 .reg_advanced = 0xad,
276 },
277 .ngpios = 16,
278 .pins = sx150x_16_pins,
279 .npins = 16, /* oscio not available */
280};
281
282static const struct sx150x_device_data sx1507q_device_data = {
283 .model = SX150X_789,
284 .reg_pullup = 0x03,
285 .reg_pulldn = 0x04,
286 .reg_dir = 0x07,
287 .reg_data = 0x08,
288 .reg_irq_mask = 0x09,
289 .reg_irq_src = 0x0b,
290 .reg_sense = 0x0a,
291 .pri.x789 = {
292 .reg_drain = 0x05,
293 .reg_polarity = 0x06,
294 .reg_clock = 0x0d,
295 .reg_misc = 0x0e,
296 .reg_reset = 0x7d,
297 },
298 .ngpios = 4,
299 .pins = sx150x_4_pins,
300 .npins = ARRAY_SIZE(sx150x_4_pins),
301};
302
303static const struct sx150x_device_data sx1508q_device_data = {
304 .model = SX150X_789,
305 .reg_pullup = 0x03,
306 .reg_pulldn = 0x04,
307 .reg_dir = 0x07,
308 .reg_data = 0x08,
309 .reg_irq_mask = 0x09,
310 .reg_irq_src = 0x0c,
311 .reg_sense = 0x0a,
312 .pri.x789 = {
313 .reg_drain = 0x05,
314 .reg_polarity = 0x06,
315 .reg_clock = 0x0f,
316 .reg_misc = 0x10,
317 .reg_reset = 0x7d,
318 },
319 .ngpios = 8,
320 .pins = sx150x_8_pins,
321 .npins = ARRAY_SIZE(sx150x_8_pins),
322};
323
324static const struct sx150x_device_data sx1509q_device_data = {
325 .model = SX150X_789,
326 .reg_pullup = 0x06,
327 .reg_pulldn = 0x08,
328 .reg_dir = 0x0e,
329 .reg_data = 0x10,
330 .reg_irq_mask = 0x12,
331 .reg_irq_src = 0x18,
332 .reg_sense = 0x14,
333 .pri.x789 = {
334 .reg_drain = 0x0a,
335 .reg_polarity = 0x0c,
336 .reg_clock = 0x1e,
337 .reg_misc = 0x1f,
338 .reg_reset = 0x7d,
339 },
340 .ngpios = 16,
341 .pins = sx150x_16_pins,
342 .npins = ARRAY_SIZE(sx150x_16_pins),
343};
344
345static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
346{
347 return 0;
348}
349
350static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
351 unsigned int group)
352{
353 return NULL;
354}
355
356static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
357 unsigned int group,
358 const unsigned int **pins,
359 unsigned int *num_pins)
360{
361 return -ENOTSUPP;
362}
363
364static const struct pinctrl_ops sx150x_pinctrl_ops = {
365 .get_groups_count = sx150x_pinctrl_get_groups_count,
366 .get_group_name = sx150x_pinctrl_get_group_name,
367 .get_group_pins = sx150x_pinctrl_get_group_pins,
368#ifdef CONFIG_OF
369 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
370 .dt_free_map = pinctrl_utils_free_map,
371#endif
372};
373
374static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
375{
376 if (pin >= pctl->data->npins)
377 return false;
378
379 /* OSCIO pin is only present in 789 devices */
380 if (pctl->data->model != SX150X_789)
381 return false;
382
383 return !strcmp(pctl->data->pins[pin].name, "oscio");
384}
385
386static int sx150x_gpio_get_direction(struct gpio_chip *chip,
387 unsigned int offset)
388{
389 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
390 unsigned int value;
391 int ret;
392
393 if (sx150x_pin_is_oscio(pctl, offset))
394 return GPIO_LINE_DIRECTION_OUT;
395
396 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
397 if (ret < 0)
398 return ret;
399
400 if (value & BIT(offset))
401 return GPIO_LINE_DIRECTION_IN;
402
403 return GPIO_LINE_DIRECTION_OUT;
404}
405
406static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
407{
408 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
409 unsigned int value;
410 int ret;
411
412 if (sx150x_pin_is_oscio(pctl, offset))
413 return -EINVAL;
414
415 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
416 if (ret < 0)
417 return ret;
418
419 return !!(value & BIT(offset));
420}
421
422static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
423 int value)
424{
425 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
426 BIT(offset), value ? BIT(offset) : 0);
427}
428
429static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
430 int value)
431{
432 return regmap_write(pctl->regmap,
433 pctl->data->pri.x789.reg_clock,
434 (value ? 0x1f : 0x10));
435}
436
437static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
438 int value)
439{
440 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
441
442 if (sx150x_pin_is_oscio(pctl, offset))
443 sx150x_gpio_oscio_set(pctl, value);
444 else
445 __sx150x_gpio_set(pctl, offset, value);
446
447}
448
449static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
450 unsigned long *mask,
451 unsigned long *bits)
452{
453 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
454
455 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
456}
457
458static int sx150x_gpio_direction_input(struct gpio_chip *chip,
459 unsigned int offset)
460{
461 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
462
463 if (sx150x_pin_is_oscio(pctl, offset))
464 return -EINVAL;
465
466 return regmap_write_bits(pctl->regmap,
467 pctl->data->reg_dir,
468 BIT(offset), BIT(offset));
469}
470
471static int sx150x_gpio_direction_output(struct gpio_chip *chip,
472 unsigned int offset, int value)
473{
474 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
475 int ret;
476
477 if (sx150x_pin_is_oscio(pctl, offset))
478 return sx150x_gpio_oscio_set(pctl, value);
479
480 ret = __sx150x_gpio_set(pctl, offset, value);
481 if (ret < 0)
482 return ret;
483
484 return regmap_write_bits(pctl->regmap,
485 pctl->data->reg_dir,
486 BIT(offset), 0);
487}
488
489static void sx150x_irq_mask(struct irq_data *d)
490{
491 struct sx150x_pinctrl *pctl =
492 gpiochip_get_data(irq_data_get_irq_chip_data(d));
493 unsigned int n = d->hwirq;
494
495 pctl->irq.masked |= BIT(n);
496}
497
498static void sx150x_irq_unmask(struct irq_data *d)
499{
500 struct sx150x_pinctrl *pctl =
501 gpiochip_get_data(irq_data_get_irq_chip_data(d));
502 unsigned int n = d->hwirq;
503
504 pctl->irq.masked &= ~BIT(n);
505}
506
507static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
508 unsigned int line, unsigned int sense)
509{
510 /*
511 * Every interrupt line is represented by two bits shifted
512 * proportionally to the line number
513 */
514 const unsigned int n = line * 2;
515 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
516 SX150X_IRQ_TYPE_EDGE_FALLING) << n);
517
518 pctl->irq.sense &= mask;
519 pctl->irq.sense |= sense << n;
520}
521
522static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
523{
524 struct sx150x_pinctrl *pctl =
525 gpiochip_get_data(irq_data_get_irq_chip_data(d));
526 unsigned int n, val = 0;
527
528 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
529 return -EINVAL;
530
531 n = d->hwirq;
532
533 if (flow_type & IRQ_TYPE_EDGE_RISING)
534 val |= SX150X_IRQ_TYPE_EDGE_RISING;
535 if (flow_type & IRQ_TYPE_EDGE_FALLING)
536 val |= SX150X_IRQ_TYPE_EDGE_FALLING;
537
538 sx150x_irq_set_sense(pctl, n, val);
539 return 0;
540}
541
542static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
543{
544 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
545 unsigned long n, status;
546 unsigned int val;
547 int err;
548
549 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
550 if (err < 0)
551 return IRQ_NONE;
552
553 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
554 if (err < 0)
555 return IRQ_NONE;
556
557 status = val;
558 for_each_set_bit(n, &status, pctl->data->ngpios)
559 handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
560
561 return IRQ_HANDLED;
562}
563
564static void sx150x_irq_bus_lock(struct irq_data *d)
565{
566 struct sx150x_pinctrl *pctl =
567 gpiochip_get_data(irq_data_get_irq_chip_data(d));
568
569 mutex_lock(&pctl->lock);
570}
571
572static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
573{
574 struct sx150x_pinctrl *pctl =
575 gpiochip_get_data(irq_data_get_irq_chip_data(d));
576
577 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
578 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
579 mutex_unlock(&pctl->lock);
580}
581
582static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
583 unsigned long *config)
584{
585 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
586 unsigned int param = pinconf_to_config_param(*config);
587 int ret;
588 u32 arg;
589 unsigned int data;
590
591 if (sx150x_pin_is_oscio(pctl, pin)) {
592 switch (param) {
593 case PIN_CONFIG_DRIVE_PUSH_PULL:
594 case PIN_CONFIG_OUTPUT:
595 ret = regmap_read(pctl->regmap,
596 pctl->data->pri.x789.reg_clock,
597 &data);
598 if (ret < 0)
599 return ret;
600
601 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
602 arg = (data & 0x1f) ? 1 : 0;
603 else {
604 if ((data & 0x1f) == 0x1f)
605 arg = 1;
606 else if ((data & 0x1f) == 0x10)
607 arg = 0;
608 else
609 return -EINVAL;
610 }
611
612 break;
613 default:
614 return -ENOTSUPP;
615 }
616
617 goto out;
618 }
619
620 switch (param) {
621 case PIN_CONFIG_BIAS_PULL_DOWN:
622 ret = regmap_read(pctl->regmap,
623 pctl->data->reg_pulldn,
624 &data);
625 data &= BIT(pin);
626
627 if (ret < 0)
628 return ret;
629
630 if (!ret)
631 return -EINVAL;
632
633 arg = 1;
634 break;
635
636 case PIN_CONFIG_BIAS_PULL_UP:
637 ret = regmap_read(pctl->regmap,
638 pctl->data->reg_pullup,
639 &data);
640 data &= BIT(pin);
641
642 if (ret < 0)
643 return ret;
644
645 if (!ret)
646 return -EINVAL;
647
648 arg = 1;
649 break;
650
651 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
652 if (pctl->data->model != SX150X_789)
653 return -ENOTSUPP;
654
655 ret = regmap_read(pctl->regmap,
656 pctl->data->pri.x789.reg_drain,
657 &data);
658 data &= BIT(pin);
659
660 if (ret < 0)
661 return ret;
662
663 if (!data)
664 return -EINVAL;
665
666 arg = 1;
667 break;
668
669 case PIN_CONFIG_DRIVE_PUSH_PULL:
670 if (pctl->data->model != SX150X_789)
671 arg = true;
672 else {
673 ret = regmap_read(pctl->regmap,
674 pctl->data->pri.x789.reg_drain,
675 &data);
676 data &= BIT(pin);
677
678 if (ret < 0)
679 return ret;
680
681 if (data)
682 return -EINVAL;
683
684 arg = 1;
685 }
686 break;
687
688 case PIN_CONFIG_OUTPUT:
689 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
690 if (ret < 0)
691 return ret;
692
693 if (ret == GPIO_LINE_DIRECTION_IN)
694 return -EINVAL;
695
696 ret = sx150x_gpio_get(&pctl->gpio, pin);
697 if (ret < 0)
698 return ret;
699
700 arg = ret;
701 break;
702
703 default:
704 return -ENOTSUPP;
705 }
706
707out:
708 *config = pinconf_to_config_packed(param, arg);
709
710 return 0;
711}
712
713static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
714 unsigned long *configs, unsigned int num_configs)
715{
716 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
717 enum pin_config_param param;
718 u32 arg;
719 int i;
720 int ret;
721
722 for (i = 0; i < num_configs; i++) {
723 param = pinconf_to_config_param(configs[i]);
724 arg = pinconf_to_config_argument(configs[i]);
725
726 if (sx150x_pin_is_oscio(pctl, pin)) {
727 if (param == PIN_CONFIG_OUTPUT) {
728 ret = sx150x_gpio_direction_output(&pctl->gpio,
729 pin, arg);
730 if (ret < 0)
731 return ret;
732
733 continue;
734 } else
735 return -ENOTSUPP;
736 }
737
738 switch (param) {
739 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
740 case PIN_CONFIG_BIAS_DISABLE:
741 ret = regmap_write_bits(pctl->regmap,
742 pctl->data->reg_pulldn,
743 BIT(pin), 0);
744 if (ret < 0)
745 return ret;
746
747 ret = regmap_write_bits(pctl->regmap,
748 pctl->data->reg_pullup,
749 BIT(pin), 0);
750 if (ret < 0)
751 return ret;
752
753 break;
754
755 case PIN_CONFIG_BIAS_PULL_UP:
756 ret = regmap_write_bits(pctl->regmap,
757 pctl->data->reg_pullup,
758 BIT(pin), BIT(pin));
759 if (ret < 0)
760 return ret;
761
762 break;
763
764 case PIN_CONFIG_BIAS_PULL_DOWN:
765 ret = regmap_write_bits(pctl->regmap,
766 pctl->data->reg_pulldn,
767 BIT(pin), BIT(pin));
768 if (ret < 0)
769 return ret;
770
771 break;
772
773 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
774 if (pctl->data->model != SX150X_789 ||
775 sx150x_pin_is_oscio(pctl, pin))
776 return -ENOTSUPP;
777
778 ret = regmap_write_bits(pctl->regmap,
779 pctl->data->pri.x789.reg_drain,
780 BIT(pin), BIT(pin));
781 if (ret < 0)
782 return ret;
783
784 break;
785
786 case PIN_CONFIG_DRIVE_PUSH_PULL:
787 if (pctl->data->model != SX150X_789 ||
788 sx150x_pin_is_oscio(pctl, pin))
789 return 0;
790
791 ret = regmap_write_bits(pctl->regmap,
792 pctl->data->pri.x789.reg_drain,
793 BIT(pin), 0);
794 if (ret < 0)
795 return ret;
796
797 break;
798
799 case PIN_CONFIG_OUTPUT:
800 ret = sx150x_gpio_direction_output(&pctl->gpio,
801 pin, arg);
802 if (ret < 0)
803 return ret;
804
805 break;
806
807 default:
808 return -ENOTSUPP;
809 }
810 } /* for each config */
811
812 return 0;
813}
814
815static const struct pinconf_ops sx150x_pinconf_ops = {
816 .pin_config_get = sx150x_pinconf_get,
817 .pin_config_set = sx150x_pinconf_set,
818 .is_generic = true,
819};
820
821static const struct i2c_device_id sx150x_id[] = {
822 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
823 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
824 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
825 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
826 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
827 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
828 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
829 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
830 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
831 {}
832};
833
834static const struct of_device_id sx150x_of_match[] = {
835 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
836 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
837 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
838 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
839 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
840 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
841 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
842 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
843 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
844 {},
845};
846
847static int sx150x_reset(struct sx150x_pinctrl *pctl)
848{
849 int err;
850
851 err = i2c_smbus_write_byte_data(pctl->client,
852 pctl->data->pri.x789.reg_reset,
853 SX150X_789_RESET_KEY1);
854 if (err < 0)
855 return err;
856
857 err = i2c_smbus_write_byte_data(pctl->client,
858 pctl->data->pri.x789.reg_reset,
859 SX150X_789_RESET_KEY2);
860 return err;
861}
862
863static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
864{
865 u8 reg, value;
866
867 switch (pctl->data->model) {
868 case SX150X_789:
869 reg = pctl->data->pri.x789.reg_misc;
870 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
871 break;
872 case SX150X_456:
873 reg = pctl->data->pri.x456.reg_advanced;
874 value = 0x00;
875
876 /*
877 * Only SX1506 has RegAdvanced, SX1504/5 are expected
878 * to initialize this offset to zero
879 */
880 if (!reg)
881 return 0;
882 break;
883 case SX150X_123:
884 reg = pctl->data->pri.x123.reg_advanced;
885 value = 0x00;
886 break;
887 default:
888 WARN(1, "Unknown chip model %d\n", pctl->data->model);
889 return -EINVAL;
890 }
891
892 return regmap_write(pctl->regmap, reg, value);
893}
894
895static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
896{
897 const u8 reg[] = {
898 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
899 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
900 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
901 };
902 int err;
903
904 if (pctl->data->model == SX150X_789 &&
905 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
906 err = sx150x_reset(pctl);
907 if (err < 0)
908 return err;
909 }
910
911 err = sx150x_init_misc(pctl);
912 if (err < 0)
913 return err;
914
915 /* Set all pins to work in normal mode */
916 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
917}
918
919static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
920 unsigned int reg)
921{
922 const struct sx150x_device_data *data = pctl->data;
923
924 if (reg == data->reg_sense) {
925 /*
926 * RegSense packs two bits of configuration per GPIO,
927 * so we'd need to read twice as many bits as there
928 * are GPIO in our chip
929 */
930 return 2 * data->ngpios;
931 } else if ((data->model == SX150X_789 &&
932 (reg == data->pri.x789.reg_misc ||
933 reg == data->pri.x789.reg_clock ||
934 reg == data->pri.x789.reg_reset))
935 ||
936 (data->model == SX150X_123 &&
937 reg == data->pri.x123.reg_advanced)
938 ||
939 (data->model == SX150X_456 &&
940 data->pri.x456.reg_advanced &&
941 reg == data->pri.x456.reg_advanced)) {
942 return 8;
943 } else {
944 return data->ngpios;
945 }
946}
947
948static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
949 unsigned int reg, unsigned int val)
950{
951 unsigned int a, b;
952 const struct sx150x_device_data *data = pctl->data;
953
954 /*
955 * Whereas SX1509 presents RegSense in a simple layout as such:
956 * reg [ f f e e d d c c ]
957 * reg + 1 [ b b a a 9 9 8 8 ]
958 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
959 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
960 *
961 * SX1503 and SX1506 deviate from that data layout, instead storing
962 * their contents as follows:
963 *
964 * reg [ f f e e d d c c ]
965 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
966 * reg + 2 [ b b a a 9 9 8 8 ]
967 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
968 *
969 * so, taking that into account, we swap two
970 * inner bytes of a 4-byte result
971 */
972
973 if (reg == data->reg_sense &&
974 data->ngpios == 16 &&
975 (data->model == SX150X_123 ||
976 data->model == SX150X_456)) {
977 a = val & 0x00ff0000;
978 b = val & 0x0000ff00;
979
980 val &= 0xff0000ff;
981 val |= b << 8;
982 val |= a >> 8;
983 }
984
985 return val;
986}
987
988/*
989 * In order to mask the differences between 16 and 8 bit expander
990 * devices we set up a sligthly ficticious regmap that pretends to be
991 * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
992 * pair/quartet) registers and transparently reconstructs those
993 * registers via multiple I2C/SMBus reads
994 *
995 * This way the rest of the driver code, interfacing with the chip via
996 * regmap API, can work assuming that each GPIO pin is represented by
997 * a group of bits at an offset proportional to GPIO number within a
998 * given register.
999 */
1000static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1001 unsigned int *result)
1002{
1003 int ret, n;
1004 struct sx150x_pinctrl *pctl = context;
1005 struct i2c_client *i2c = pctl->client;
1006 const int width = sx150x_regmap_reg_width(pctl, reg);
1007 unsigned int idx, val;
1008
1009 /*
1010 * There are four potential cases covered by this function:
1011 *
1012 * 1) 8-pin chip, single configuration bit register
1013 *
1014 * This is trivial the code below just needs to read:
1015 * reg [ 7 6 5 4 3 2 1 0 ]
1016 *
1017 * 2) 8-pin chip, double configuration bit register (RegSense)
1018 *
1019 * The read will be done as follows:
1020 * reg [ 7 7 6 6 5 5 4 4 ]
1021 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
1022 *
1023 * 3) 16-pin chip, single configuration bit register
1024 *
1025 * The read will be done as follows:
1026 * reg [ f e d c b a 9 8 ]
1027 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
1028 *
1029 * 4) 16-pin chip, double configuration bit register (RegSense)
1030 *
1031 * The read will be done as follows:
1032 * reg [ f f e e d d c c ]
1033 * reg + 1 [ b b a a 9 9 8 8 ]
1034 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
1035 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
1036 */
1037
1038 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1039 val <<= 8;
1040
1041 ret = i2c_smbus_read_byte_data(i2c, idx);
1042 if (ret < 0)
1043 return ret;
1044
1045 val |= ret;
1046 }
1047
1048 *result = sx150x_maybe_swizzle(pctl, reg, val);
1049
1050 return 0;
1051}
1052
1053static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1054 unsigned int val)
1055{
1056 int ret, n;
1057 struct sx150x_pinctrl *pctl = context;
1058 struct i2c_client *i2c = pctl->client;
1059 const int width = sx150x_regmap_reg_width(pctl, reg);
1060
1061 val = sx150x_maybe_swizzle(pctl, reg, val);
1062
1063 n = (width - 1) & ~7;
1064 do {
1065 const u8 byte = (val >> n) & 0xff;
1066
1067 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1068 if (ret < 0)
1069 return ret;
1070
1071 reg++;
1072 n -= 8;
1073 } while (n >= 0);
1074
1075 return 0;
1076}
1077
1078static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1079{
1080 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1081
1082 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1083}
1084
1085static const struct regmap_config sx150x_regmap_config = {
1086 .reg_bits = 8,
1087 .val_bits = 32,
1088
1089 .cache_type = REGCACHE_RBTREE,
1090
1091 .reg_read = sx150x_regmap_reg_read,
1092 .reg_write = sx150x_regmap_reg_write,
1093
1094 .max_register = SX150X_MAX_REGISTER,
1095 .volatile_reg = sx150x_reg_volatile,
1096};
1097
1098static int sx150x_probe(struct i2c_client *client,
1099 const struct i2c_device_id *id)
1100{
1101 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1102 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1103 struct device *dev = &client->dev;
1104 struct sx150x_pinctrl *pctl;
1105 int ret;
1106
1107 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1108 return -ENOSYS;
1109
1110 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1111 if (!pctl)
1112 return -ENOMEM;
1113
1114 i2c_set_clientdata(client, pctl);
1115
1116 pctl->dev = dev;
1117 pctl->client = client;
1118
1119 if (dev->of_node)
1120 pctl->data = of_device_get_match_data(dev);
1121 else
1122 pctl->data = (struct sx150x_device_data *)id->driver_data;
1123
1124 if (!pctl->data)
1125 return -EINVAL;
1126
1127 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1128 &sx150x_regmap_config);
1129 if (IS_ERR(pctl->regmap)) {
1130 ret = PTR_ERR(pctl->regmap);
1131 dev_err(dev, "Failed to allocate register map: %d\n",
1132 ret);
1133 return ret;
1134 }
1135
1136 mutex_init(&pctl->lock);
1137
1138 ret = sx150x_init_hw(pctl);
1139 if (ret)
1140 return ret;
1141
1142 /* Pinctrl_desc */
1143 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1144 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1145 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1146 pctl->pinctrl_desc.pins = pctl->data->pins;
1147 pctl->pinctrl_desc.npins = pctl->data->npins;
1148 pctl->pinctrl_desc.owner = THIS_MODULE;
1149
1150 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1151 pctl, &pctl->pctldev);
1152 if (ret) {
1153 dev_err(dev, "Failed to register pinctrl device\n");
1154 return ret;
1155 }
1156
1157 ret = pinctrl_enable(pctl->pctldev);
1158 if (ret) {
1159 dev_err(dev, "Failed to enable pinctrl device\n");
1160 return ret;
1161 }
1162
1163 /* Register GPIO controller */
1164 pctl->gpio.base = -1;
1165 pctl->gpio.ngpio = pctl->data->npins;
1166 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1167 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1168 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1169 pctl->gpio.get = sx150x_gpio_get;
1170 pctl->gpio.set = sx150x_gpio_set;
1171 pctl->gpio.set_config = gpiochip_generic_config;
1172 pctl->gpio.parent = dev;
1173#ifdef CONFIG_OF_GPIO
1174 pctl->gpio.of_node = dev->of_node;
1175#endif
1176 pctl->gpio.can_sleep = true;
1177 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1178 if (!pctl->gpio.label)
1179 return -ENOMEM;
1180
1181 /*
1182 * Setting multiple pins is not safe when all pins are not
1183 * handled by the same regmap register. The oscio pin (present
1184 * on the SX150X_789 chips) lives in its own register, so
1185 * would require locking that is not in place at this time.
1186 */
1187 if (pctl->data->model != SX150X_789)
1188 pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1189
1190 /* Add Interrupt support if an irq is specified */
1191 if (client->irq > 0) {
1192 struct gpio_irq_chip *girq;
1193
1194 pctl->irq_chip.irq_mask = sx150x_irq_mask;
1195 pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1196 pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1197 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1198 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1199 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1200 GFP_KERNEL);
1201 if (!pctl->irq_chip.name)
1202 return -ENOMEM;
1203
1204 pctl->irq.masked = ~0;
1205 pctl->irq.sense = 0;
1206
1207 /*
1208 * Because sx150x_irq_threaded_fn invokes all of the
1209 * nested interrupt handlers via handle_nested_irq,
1210 * any "handler" assigned to struct gpio_irq_chip
1211 * below is going to be ignored, so the choice of the
1212 * function does not matter that much.
1213 *
1214 * We set it to handle_bad_irq to avoid confusion,
1215 * plus it will be instantly noticeable if it is ever
1216 * called (should not happen)
1217 */
1218 girq = &pctl->gpio.irq;
1219 girq->chip = &pctl->irq_chip;
1220 /* This will let us handle the parent IRQ in the driver */
1221 girq->parent_handler = NULL;
1222 girq->num_parents = 0;
1223 girq->parents = NULL;
1224 girq->default_type = IRQ_TYPE_NONE;
1225 girq->handler = handle_bad_irq;
1226 girq->threaded = true;
1227
1228 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1229 sx150x_irq_thread_fn,
1230 IRQF_ONESHOT | IRQF_SHARED |
1231 IRQF_TRIGGER_FALLING,
1232 pctl->irq_chip.name, pctl);
1233 if (ret < 0)
1234 return ret;
1235 }
1236
1237 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1238 if (ret)
1239 return ret;
1240
1241 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1242 0, 0, pctl->data->npins);
1243 if (ret)
1244 return ret;
1245
1246 return 0;
1247}
1248
1249static struct i2c_driver sx150x_driver = {
1250 .driver = {
1251 .name = "sx150x-pinctrl",
1252 .of_match_table = of_match_ptr(sx150x_of_match),
1253 },
1254 .probe = sx150x_probe,
1255 .id_table = sx150x_id,
1256};
1257
1258static int __init sx150x_init(void)
1259{
1260 return i2c_add_driver(&sx150x_driver);
1261}
1262subsys_initcall(sx150x_init);