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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence Torrent SD0801 PHY driver.
4 *
5 * Copyright 2018 Cadence Design Systems, Inc.
6 *
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/phy/phy-cadence.h>
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/phy/phy.h>
21#include <linux/platform_device.h>
22#include <linux/reset.h>
23#include <linux/regmap.h>
24
25#define REF_CLK_19_2MHZ 19200000
26#define REF_CLK_25MHZ 25000000
27#define REF_CLK_100MHZ 100000000
28#define REF_CLK_156_25MHZ 156250000
29
30#define MAX_NUM_LANES 4
31#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
32
33#define POLL_TIMEOUT_US 5000
34#define PLL_LOCK_TIMEOUT 100000
35
36#define DP_PLL0 BIT(0)
37#define DP_PLL1 BIT(1)
38
39#define TORRENT_COMMON_CDB_OFFSET 0x0
40
41#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
42 ((0x4000 << (block_offset)) + \
43 (((ln) << 9) << (reg_offset)))
44
45#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
46 ((0x8000 << (block_offset)) + \
47 (((ln) << 9) << (reg_offset)))
48
49#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
50 (0xC000 << (block_offset))
51
52#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
53 ((0xD000 << (block_offset)) + \
54 (((ln) << 8) << (reg_offset)))
55
56#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
57 (0xE000 << (block_offset))
58
59#define TORRENT_DPTX_PHY_OFFSET 0x0
60
61/*
62 * register offsets from DPTX PHY register block base (i.e MHDP
63 * register base + 0x30a00)
64 */
65#define PHY_AUX_CTRL 0x04
66#define PHY_RESET 0x20
67#define PMA_TX_ELEC_IDLE_SHIFT 4
68#define PHY_PMA_XCVR_PLLCLK_EN 0x24
69#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
70#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
71#define PHY_POWER_STATE_LN(ln) ((ln) * 8)
72#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
73#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
74#define PHY_PMA_CMN_READY 0x34
75
76/*
77 * register offsets from SD0801 PHY register block base (i.e MHDP
78 * register base + 0x500000)
79 */
80#define CMN_SSM_BANDGAP_TMR 0x0021U
81#define CMN_SSM_BIAS_TMR 0x0022U
82#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
83#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
84#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
85#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
86#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
87#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
88#define CMN_CDIAG_REFCLK_OVRD 0x004CU
89#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
90#define CMN_BGCAL_INIT_TMR 0x0064U
91#define CMN_BGCAL_ITER_TMR 0x0065U
92#define CMN_IBCAL_INIT_TMR 0x0074U
93#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
94#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
95#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
96#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
97#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
98#define CMN_PLL0_INTDIV_M0 0x0090U
99#define CMN_PLL0_FRACDIVL_M0 0x0091U
100#define CMN_PLL0_FRACDIVH_M0 0x0092U
101#define CMN_PLL0_HIGH_THR_M0 0x0093U
102#define CMN_PLL0_DSM_DIAG_M0 0x0094U
103#define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
104#define CMN_PLL0_DSM_FBL_OVRD_M0 0x0096U
105#define CMN_PLL0_SS_CTRL1_M0 0x0098U
106#define CMN_PLL0_SS_CTRL2_M0 0x0099U
107#define CMN_PLL0_SS_CTRL3_M0 0x009AU
108#define CMN_PLL0_SS_CTRL4_M0 0x009BU
109#define CMN_PLL0_LOCK_REFCNT_START 0x009CU
110#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
111#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
112#define CMN_PLL0_INTDIV_M1 0x00A0U
113#define CMN_PLL0_FRACDIVH_M1 0x00A2U
114#define CMN_PLL0_HIGH_THR_M1 0x00A3U
115#define CMN_PLL0_DSM_DIAG_M1 0x00A4U
116#define CMN_PLL0_SS_CTRL1_M1 0x00A8U
117#define CMN_PLL0_SS_CTRL2_M1 0x00A9U
118#define CMN_PLL0_SS_CTRL3_M1 0x00AAU
119#define CMN_PLL0_SS_CTRL4_M1 0x00ABU
120#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
121#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
122#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
123#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
124#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
125#define CMN_PLL1_INTDIV_M0 0x00D0U
126#define CMN_PLL1_FRACDIVL_M0 0x00D1U
127#define CMN_PLL1_FRACDIVH_M0 0x00D2U
128#define CMN_PLL1_HIGH_THR_M0 0x00D3U
129#define CMN_PLL1_DSM_DIAG_M0 0x00D4U
130#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
131#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
132#define CMN_PLL1_SS_CTRL1_M0 0x00D8U
133#define CMN_PLL1_SS_CTRL2_M0 0x00D9U
134#define CMN_PLL1_SS_CTRL3_M0 0x00DAU
135#define CMN_PLL1_SS_CTRL4_M0 0x00DBU
136#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
137#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
138#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
139#define CMN_TXPUCAL_TUNE 0x0103U
140#define CMN_TXPUCAL_INIT_TMR 0x0104U
141#define CMN_TXPUCAL_ITER_TMR 0x0105U
142#define CMN_TXPDCAL_TUNE 0x010BU
143#define CMN_TXPDCAL_INIT_TMR 0x010CU
144#define CMN_TXPDCAL_ITER_TMR 0x010DU
145#define CMN_RXCAL_INIT_TMR 0x0114U
146#define CMN_RXCAL_ITER_TMR 0x0115U
147#define CMN_SD_CAL_INIT_TMR 0x0124U
148#define CMN_SD_CAL_ITER_TMR 0x0125U
149#define CMN_SD_CAL_REFTIM_START 0x0126U
150#define CMN_SD_CAL_PLLCNT_START 0x0128U
151#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
152#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
153#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
154#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
155#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
156#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
157#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
158#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
159#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
160#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
161#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
162#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
163#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
164#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
165#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
166#define CMN_DIAG_BIAS_OVRD1 0x01E1U
167
168/* PMA TX Lane registers */
169#define TX_TXCC_CTRL 0x0040U
170#define TX_TXCC_CPOST_MULT_00 0x004CU
171#define TX_TXCC_CPOST_MULT_01 0x004DU
172#define TX_TXCC_MGNFS_MULT_000 0x0050U
173#define TX_TXCC_MGNFS_MULT_100 0x0054U
174#define DRV_DIAG_TX_DRV 0x00C6U
175#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
176#define XCVR_DIAG_HSCLK_SEL 0x00E6U
177#define XCVR_DIAG_HSCLK_DIV 0x00E7U
178#define XCVR_DIAG_RXCLK_CTRL 0x00E9U
179#define XCVR_DIAG_BIDI_CTRL 0x00EAU
180#define XCVR_DIAG_PSC_OVRD 0x00EBU
181#define TX_PSC_A0 0x0100U
182#define TX_PSC_A1 0x0101U
183#define TX_PSC_A2 0x0102U
184#define TX_PSC_A3 0x0103U
185#define TX_RCVDET_ST_TMR 0x0123U
186#define TX_DIAG_ACYA 0x01E7U
187#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
188
189/* PMA RX Lane registers */
190#define RX_PSC_A0 0x0000U
191#define RX_PSC_A1 0x0001U
192#define RX_PSC_A2 0x0002U
193#define RX_PSC_A3 0x0003U
194#define RX_PSC_CAL 0x0006U
195#define RX_SDCAL0_INIT_TMR 0x0044U
196#define RX_SDCAL0_ITER_TMR 0x0045U
197#define RX_SDCAL1_INIT_TMR 0x004CU
198#define RX_SDCAL1_ITER_TMR 0x004DU
199#define RX_CDRLF_CNFG 0x0080U
200#define RX_CDRLF_CNFG3 0x0082U
201#define RX_SIGDET_HL_FILT_TMR 0x0090U
202#define RX_REE_GCSM1_CTRL 0x0108U
203#define RX_REE_GCSM1_EQENM_PH1 0x0109U
204#define RX_REE_GCSM1_EQENM_PH2 0x010AU
205#define RX_REE_GCSM2_CTRL 0x0110U
206#define RX_REE_PERGCSM_CTRL 0x0118U
207#define RX_REE_ATTEN_THR 0x0149U
208#define RX_REE_TAP1_CLIP 0x0171U
209#define RX_REE_TAP2TON_CLIP 0x0172U
210#define RX_REE_SMGM_CTRL1 0x0177U
211#define RX_REE_SMGM_CTRL2 0x0178U
212#define RX_DIAG_DFE_CTRL 0x01E0U
213#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
214#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
215#define RX_DIAG_NQST_CTRL 0x01E5U
216#define RX_DIAG_SIGDET_TUNE 0x01E8U
217#define RX_DIAG_PI_RATE 0x01F4U
218#define RX_DIAG_PI_CAP 0x01F5U
219#define RX_DIAG_ACYA 0x01FFU
220
221/* PHY PCS common registers */
222#define PHY_PIPE_CMN_CTRL1 0x0000U
223#define PHY_PLL_CFG 0x000EU
224#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
225#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
226#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
227
228/* PHY PCS lane registers */
229#define PHY_PCS_ISO_LINK_CTRL 0x000BU
230
231/* PHY PMA common registers */
232#define PHY_PMA_CMN_CTRL1 0x0000U
233#define PHY_PMA_CMN_CTRL2 0x0001U
234#define PHY_PMA_PLL_RAW_CTRL 0x0003U
235
236#define CDNS_TORRENT_OUTPUT_CLOCKS 3
237
238static const char * const clk_names[] = {
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
242};
243
244static const struct reg_field phy_pll_cfg =
245 REG_FIELD(PHY_PLL_CFG, 0, 1);
246
247static const struct reg_field phy_pma_cmn_ctrl_1 =
248 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
249
250static const struct reg_field phy_pma_cmn_ctrl_2 =
251 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
252
253static const struct reg_field phy_pma_pll_raw_ctrl =
254 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
255
256static const struct reg_field phy_reset_ctrl =
257 REG_FIELD(PHY_RESET, 8, 8);
258
259static const struct reg_field phy_pcs_iso_link_ctrl_1 =
260 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
261
262static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
263
264static const struct reg_field cmn_cdiag_refclk_ovrd_4 =
265 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);
266
267#define REFCLK_OUT_NUM_CMN_CONFIG 4
268
269enum cdns_torrent_refclk_out_cmn {
270 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
271 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
272 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
273 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
274};
275
276static const struct reg_field refclk_out_cmn_cfg[] = {
277 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
278 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
279 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
280 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
281};
282
283static const int refclk_driver_parent_index[] = {
284 CDNS_TORRENT_DERIVED_REFCLK,
285 CDNS_TORRENT_RECEIVED_REFCLK
286};
287
288static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };
289
290enum cdns_torrent_phy_type {
291 TYPE_NONE,
292 TYPE_DP,
293 TYPE_PCIE,
294 TYPE_SGMII,
295 TYPE_QSGMII,
296 TYPE_USB,
297 TYPE_USXGMII,
298};
299
300enum cdns_torrent_ref_clk {
301 CLK_19_2_MHZ,
302 CLK_25_MHZ,
303 CLK_100_MHZ,
304 CLK_156_25_MHZ,
305 CLK_ANY,
306};
307
308enum cdns_torrent_ssc_mode {
309 NO_SSC,
310 EXTERNAL_SSC,
311 INTERNAL_SSC,
312 ANY_SSC,
313};
314
315/* Unique key id for vals table entry
316 * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
317 */
318#define REFCLK0_SHIFT 12
319#define REFCLK0_MASK GENMASK(14, 12)
320#define REFCLK1_SHIFT 9
321#define REFCLK1_MASK GENMASK(11, 9)
322#define LINK0_SHIFT 6
323#define LINK0_MASK GENMASK(8, 6)
324#define LINK1_SHIFT 3
325#define LINK1_MASK GENMASK(5, 3)
326#define SSC_SHIFT 0
327#define SSC_MASK GENMASK(2, 0)
328
329#define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \
330 ((((refclk0) << REFCLK0_SHIFT) & REFCLK0_MASK) | \
331 (((refclk1) << REFCLK1_SHIFT) & REFCLK1_MASK) | \
332 (((link0) << LINK0_SHIFT) & LINK0_MASK) | \
333 (((link1) << LINK1_SHIFT) & LINK1_MASK) | \
334 (((ssc) << SSC_SHIFT) & SSC_MASK))
335
336#define CDNS_TORRENT_KEY_ANYCLK(link0, link1) \
337 CDNS_TORRENT_KEY(CLK_ANY, CLK_ANY, \
338 (link0), (link1), ANY_SSC)
339
340struct cdns_torrent_inst {
341 struct phy *phy;
342 u32 mlane;
343 enum cdns_torrent_phy_type phy_type;
344 u32 num_lanes;
345 struct reset_control *lnk_rst;
346 enum cdns_torrent_ssc_mode ssc_mode;
347};
348
349struct cdns_torrent_phy {
350 void __iomem *base; /* DPTX registers base */
351 void __iomem *sd_base; /* SD0801 registers base */
352 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
353 u32 dp_pll;
354 struct reset_control *phy_rst;
355 struct reset_control *apb_rst;
356 struct device *dev;
357 struct clk *clk;
358 enum cdns_torrent_ref_clk ref_clk_rate;
359 struct cdns_torrent_inst phys[MAX_NUM_LANES];
360 int nsubnodes;
361 const struct cdns_torrent_data *init_data;
362 struct regmap *regmap_common_cdb;
363 struct regmap *regmap_phy_pcs_common_cdb;
364 struct regmap *regmap_phy_pma_common_cdb;
365 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
366 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
367 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
368 struct regmap *regmap_dptx_phy_reg;
369 struct regmap_field *phy_pll_cfg;
370 struct regmap_field *phy_pipe_cmn_ctrl1_0;
371 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
372 struct regmap_field *phy_pma_cmn_ctrl_1;
373 struct regmap_field *phy_pma_cmn_ctrl_2;
374 struct regmap_field *phy_pma_pll_raw_ctrl;
375 struct regmap_field *phy_reset_ctrl;
376 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
377 struct clk_hw_onecell_data *clk_hw_data;
378};
379
380enum phy_powerstate {
381 POWERSTATE_A0 = 0,
382 /* Powerstate A1 is unused */
383 POWERSTATE_A2 = 2,
384 POWERSTATE_A3 = 3,
385};
386
387struct cdns_torrent_refclk_driver {
388 struct clk_hw hw;
389 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
390 struct clk_init_data clk_data;
391};
392
393#define to_cdns_torrent_refclk_driver(_hw) \
394 container_of(_hw, struct cdns_torrent_refclk_driver, hw)
395
396struct cdns_torrent_derived_refclk {
397 struct clk_hw hw;
398 struct regmap_field *phy_pipe_cmn_ctrl1_0;
399 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
400 struct clk_init_data clk_data;
401};
402
403#define to_cdns_torrent_derived_refclk(_hw) \
404 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
405
406struct cdns_torrent_received_refclk {
407 struct clk_hw hw;
408 struct regmap_field *phy_pipe_cmn_ctrl1_0;
409 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
410 struct clk_init_data clk_data;
411};
412
413#define to_cdns_torrent_received_refclk(_hw) \
414 container_of(_hw, struct cdns_torrent_received_refclk, hw)
415
416struct cdns_reg_pairs {
417 u32 val;
418 u32 off;
419};
420
421struct cdns_torrent_vals {
422 struct cdns_reg_pairs *reg_pairs;
423 u32 num_regs;
424};
425
426struct cdns_torrent_vals_entry {
427 u32 key;
428 struct cdns_torrent_vals *vals;
429};
430
431struct cdns_torrent_vals_table {
432 struct cdns_torrent_vals_entry *entries;
433 u32 num_entries;
434};
435
436struct cdns_torrent_data {
437 u8 block_offset_shift;
438 u8 reg_offset_shift;
439 struct cdns_torrent_vals_table link_cmn_vals_tbl;
440 struct cdns_torrent_vals_table xcvr_diag_vals_tbl;
441 struct cdns_torrent_vals_table pcs_cmn_vals_tbl;
442 struct cdns_torrent_vals_table phy_pma_cmn_vals_tbl;
443 struct cdns_torrent_vals_table cmn_vals_tbl;
444 struct cdns_torrent_vals_table tx_ln_vals_tbl;
445 struct cdns_torrent_vals_table rx_ln_vals_tbl;
446};
447
448struct cdns_regmap_cdb_context {
449 struct device *dev;
450 void __iomem *base;
451 u8 reg_offset_shift;
452};
453
454static struct cdns_torrent_vals *cdns_torrent_get_tbl_vals(const struct cdns_torrent_vals_table *tbl,
455 enum cdns_torrent_ref_clk refclk0,
456 enum cdns_torrent_ref_clk refclk1,
457 enum cdns_torrent_phy_type link0,
458 enum cdns_torrent_phy_type link1,
459 enum cdns_torrent_ssc_mode ssc)
460{
461 int i;
462 u32 key = CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc);
463
464 for (i = 0; i < tbl->num_entries; i++) {
465 if (tbl->entries[i].key == key)
466 return tbl->entries[i].vals;
467 }
468
469 return NULL;
470}
471
472static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
473{
474 struct cdns_regmap_cdb_context *ctx = context;
475 u32 offset = reg << ctx->reg_offset_shift;
476
477 writew(val, ctx->base + offset);
478
479 return 0;
480}
481
482static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
483{
484 struct cdns_regmap_cdb_context *ctx = context;
485 u32 offset = reg << ctx->reg_offset_shift;
486
487 *val = readw(ctx->base + offset);
488 return 0;
489}
490
491static int cdns_regmap_dptx_write(void *context, unsigned int reg,
492 unsigned int val)
493{
494 struct cdns_regmap_cdb_context *ctx = context;
495 u32 offset = reg;
496
497 writel(val, ctx->base + offset);
498
499 return 0;
500}
501
502static int cdns_regmap_dptx_read(void *context, unsigned int reg,
503 unsigned int *val)
504{
505 struct cdns_regmap_cdb_context *ctx = context;
506 u32 offset = reg;
507
508 *val = readl(ctx->base + offset);
509 return 0;
510}
511
512#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
513{ \
514 .name = "torrent_tx_lane" n "_cdb", \
515 .reg_stride = 1, \
516 .fast_io = true, \
517 .reg_write = cdns_regmap_write, \
518 .reg_read = cdns_regmap_read, \
519}
520
521#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
522{ \
523 .name = "torrent_rx_lane" n "_cdb", \
524 .reg_stride = 1, \
525 .fast_io = true, \
526 .reg_write = cdns_regmap_write, \
527 .reg_read = cdns_regmap_read, \
528}
529
530static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
531 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
532 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
533 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
534 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
535};
536
537static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
538 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
539 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
540 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
541 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
542};
543
544static const struct regmap_config cdns_torrent_common_cdb_config = {
545 .name = "torrent_common_cdb",
546 .reg_stride = 1,
547 .fast_io = true,
548 .reg_write = cdns_regmap_write,
549 .reg_read = cdns_regmap_read,
550};
551
552#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
553{ \
554 .name = "torrent_phy_pcs_lane" n "_cdb", \
555 .reg_stride = 1, \
556 .fast_io = true, \
557 .reg_write = cdns_regmap_write, \
558 .reg_read = cdns_regmap_read, \
559}
560
561static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
562 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
563 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
564 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
565 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
566};
567
568static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
569 .name = "torrent_phy_pcs_cmn_cdb",
570 .reg_stride = 1,
571 .fast_io = true,
572 .reg_write = cdns_regmap_write,
573 .reg_read = cdns_regmap_read,
574};
575
576static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
577 .name = "torrent_phy_pma_cmn_cdb",
578 .reg_stride = 1,
579 .fast_io = true,
580 .reg_write = cdns_regmap_write,
581 .reg_read = cdns_regmap_read,
582};
583
584static const struct regmap_config cdns_torrent_dptx_phy_config = {
585 .name = "torrent_dptx_phy",
586 .reg_stride = 1,
587 .fast_io = true,
588 .reg_write = cdns_regmap_dptx_write,
589 .reg_read = cdns_regmap_dptx_read,
590};
591
592/* PHY mmr access functions */
593
594static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
595{
596 regmap_write(regmap, offset, val);
597}
598
599static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
600{
601 unsigned int val;
602
603 regmap_read(regmap, offset, &val);
604 return val;
605}
606
607/* DPTX mmr access functions */
608
609static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
610{
611 regmap_write(regmap, offset, val);
612}
613
614static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
615{
616 u32 val;
617
618 regmap_read(regmap, offset, &val);
619 return val;
620}
621
622/*
623 * Structure used to store values of PHY registers for voltage-related
624 * coefficients, for particular voltage swing and pre-emphasis level. Values
625 * are shared across all physical lanes.
626 */
627struct coefficients {
628 /* Value of DRV_DIAG_TX_DRV register to use */
629 u16 diag_tx_drv;
630 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
631 u16 mgnfs_mult;
632 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
633 u16 cpost_mult;
634};
635
636/*
637 * Array consists of values of voltage-related registers for sd0801 PHY. A value
638 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
639 */
640static const struct coefficients vltg_coeff[4][4] = {
641 /* voltage swing 0, pre-emphasis 0->3 */
642 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
643 .cpost_mult = 0x0000},
644 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
645 .cpost_mult = 0x0014},
646 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
647 .cpost_mult = 0x0020},
648 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
649 .cpost_mult = 0x002A}
650 },
651
652 /* voltage swing 1, pre-emphasis 0->3 */
653 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
654 .cpost_mult = 0x0000},
655 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
656 .cpost_mult = 0x0012},
657 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
658 .cpost_mult = 0x001F},
659 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
660 .cpost_mult = 0xFFFF}
661 },
662
663 /* voltage swing 2, pre-emphasis 0->3 */
664 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
665 .cpost_mult = 0x0000},
666 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
667 .cpost_mult = 0x0013},
668 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
669 .cpost_mult = 0xFFFF},
670 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
671 .cpost_mult = 0xFFFF}
672 },
673
674 /* voltage swing 3, pre-emphasis 0->3 */
675 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
676 .cpost_mult = 0x0000},
677 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
678 .cpost_mult = 0xFFFF},
679 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
680 .cpost_mult = 0xFFFF},
681 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
682 .cpost_mult = 0xFFFF}
683 }
684};
685
686static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
687{
688 switch (phy_type) {
689 case TYPE_DP:
690 return "DisplayPort";
691 case TYPE_PCIE:
692 return "PCIe";
693 case TYPE_SGMII:
694 return "SGMII";
695 case TYPE_QSGMII:
696 return "QSGMII";
697 case TYPE_USB:
698 return "USB";
699 case TYPE_USXGMII:
700 return "USXGMII";
701 default:
702 return "None";
703 }
704}
705
706/*
707 * Set registers responsible for enabling and configuring SSC, with second and
708 * third register values provided by parameters.
709 */
710static
711void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
712 u32 ctrl2_val, u32 ctrl3_val)
713{
714 struct regmap *regmap = cdns_phy->regmap_common_cdb;
715
716 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
717 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
718 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
719 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
720 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
721 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
722 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
723 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
724}
725
726static
727void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
728 u32 rate, bool ssc)
729{
730 struct regmap *regmap = cdns_phy->regmap_common_cdb;
731
732 /* Assumes 19.2 MHz refclock */
733 switch (rate) {
734 /* Setting VCO for 10.8GHz */
735 case 2700:
736 case 5400:
737 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
738 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
739 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
740 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
741 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
742 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
743 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
744 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
745 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
746 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
747 if (ssc)
748 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
749 break;
750 /* Setting VCO for 9.72GHz */
751 case 1620:
752 case 2430:
753 case 3240:
754 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
755 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
756 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
757 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
758 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
759 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
760 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
761 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
762 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
763 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
764 if (ssc)
765 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
766 break;
767 /* Setting VCO for 8.64GHz */
768 case 2160:
769 case 4320:
770 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
771 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
772 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
773 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
774 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
775 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
776 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
777 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
778 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
779 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
780 if (ssc)
781 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
782 break;
783 /* Setting VCO for 8.1GHz */
784 case 8100:
785 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
786 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
787 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
788 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
789 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
790 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
791 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
792 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
793 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
794 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
795 if (ssc)
796 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
797 break;
798 }
799
800 if (ssc) {
801 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
802 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
803 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
804 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
805 } else {
806 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
807 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
808 /* Set reset register values to disable SSC */
809 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
810 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
811 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
812 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
813 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
814 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
815 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
816 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
817 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
818 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
819 }
820
821 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
822 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
823 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
824 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
825}
826
827/*
828 * Set registers responsible for enabling and configuring SSC, with second
829 * register value provided by a parameter.
830 */
831static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
832 u32 ctrl2_val)
833{
834 struct regmap *regmap = cdns_phy->regmap_common_cdb;
835
836 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
837 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
838 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
839 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
840 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
841 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
842 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
843 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
844}
845
846static
847void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
848 u32 rate, bool ssc)
849{
850 struct regmap *regmap = cdns_phy->regmap_common_cdb;
851
852 /* Assumes 25 MHz refclock */
853 switch (rate) {
854 /* Setting VCO for 10.8GHz */
855 case 2700:
856 case 5400:
857 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
858 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
859 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
860 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
861 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
862 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
863 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
864 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
865 if (ssc)
866 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
867 break;
868 /* Setting VCO for 9.72GHz */
869 case 1620:
870 case 2430:
871 case 3240:
872 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
873 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
874 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
875 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
876 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
877 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
878 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
879 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
880 if (ssc)
881 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
882 break;
883 /* Setting VCO for 8.64GHz */
884 case 2160:
885 case 4320:
886 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
887 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
888 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
889 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
890 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
891 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
892 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
893 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
894 if (ssc)
895 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
896 break;
897 /* Setting VCO for 8.1GHz */
898 case 8100:
899 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
900 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
901 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
902 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
903 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
904 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
905 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
906 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
907 if (ssc)
908 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
909 break;
910 }
911
912 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
913 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
914
915 if (ssc) {
916 cdns_torrent_phy_write(regmap,
917 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
918 cdns_torrent_phy_write(regmap,
919 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
920 cdns_torrent_phy_write(regmap,
921 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
922 cdns_torrent_phy_write(regmap,
923 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
924 } else {
925 cdns_torrent_phy_write(regmap,
926 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
927 cdns_torrent_phy_write(regmap,
928 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
929 /* Set reset register values to disable SSC */
930 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
931 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
932 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
933 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
934 cdns_torrent_phy_write(regmap,
935 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
936 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
937 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
938 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
939 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
940 cdns_torrent_phy_write(regmap,
941 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
942 }
943
944 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
945 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
946 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
947 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
948}
949
950static
951void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
952 u32 rate, bool ssc)
953{
954 struct regmap *regmap = cdns_phy->regmap_common_cdb;
955
956 /* Assumes 100 MHz refclock */
957 switch (rate) {
958 /* Setting VCO for 10.8GHz */
959 case 2700:
960 case 5400:
961 if (cdns_phy->dp_pll & DP_PLL0)
962 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
963
964 if (cdns_phy->dp_pll & DP_PLL1) {
965 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
966 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
967 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
968 }
969 break;
970 /* Setting VCO for 9.72GHz */
971 case 1620:
972 case 2430:
973 case 3240:
974 if (cdns_phy->dp_pll & DP_PLL0) {
975 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
976 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
977 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
978 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
979 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
980 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
981 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
982 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
983 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
984 }
985 if (cdns_phy->dp_pll & DP_PLL1) {
986 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
987 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
988 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
989 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
990 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
991 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
992 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
993 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
994 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
995 }
996 break;
997 /* Setting VCO for 8.64GHz */
998 case 2160:
999 case 4320:
1000 if (cdns_phy->dp_pll & DP_PLL0) {
1001 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1002 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1003 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1004 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1005 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
1006 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
1007 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1008 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
1009 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1010 }
1011 if (cdns_phy->dp_pll & DP_PLL1) {
1012 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1013 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1014 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1015 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1016 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
1017 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
1018 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1019 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
1020 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1021 }
1022 break;
1023 /* Setting VCO for 8.1GHz */
1024 case 8100:
1025 if (cdns_phy->dp_pll & DP_PLL0) {
1026 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1027 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1028 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1029 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1030 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
1031 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1032 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
1033 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1034 }
1035 if (cdns_phy->dp_pll & DP_PLL1) {
1036 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1037 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1038 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1039 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1040 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
1041 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1042 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
1043 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1044 }
1045 break;
1046 }
1047}
1048
1049/* Set PLL used for DP configuration */
1050static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
1051 enum cdns_torrent_phy_type phy_t2)
1052{
1053 switch (phy_t2) {
1054 case TYPE_PCIE:
1055 case TYPE_USB:
1056 cdns_phy->dp_pll = DP_PLL1;
1057 break;
1058 case TYPE_SGMII:
1059 case TYPE_QSGMII:
1060 cdns_phy->dp_pll = DP_PLL0;
1061 break;
1062 case TYPE_NONE:
1063 cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;
1064 break;
1065 default:
1066 dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");
1067 return -EINVAL;
1068 }
1069
1070 return 0;
1071}
1072
1073/*
1074 * Enable or disable PLL for selected lanes.
1075 */
1076static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
1077 struct cdns_torrent_inst *inst,
1078 struct phy_configure_opts_dp *dp,
1079 bool enable)
1080{
1081 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1082 u32 rd_val, pll_ack_val;
1083 int ret;
1084
1085 /*
1086 * Used to determine, which bits to check for or enable in
1087 * PHY_PMA_XCVR_PLLCLK_EN register.
1088 */
1089 u32 pll_bits;
1090 /* Used to enable or disable lanes. */
1091 u32 pll_val;
1092
1093 /* Select values of registers and mask, depending on enabled lane count. */
1094 pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1095
1096 if (enable) {
1097 pll_bits = ((1 << dp->lanes) - 1);
1098 pll_val |= pll_bits;
1099 pll_ack_val = pll_bits;
1100 } else {
1101 pll_bits = ((1 << inst->num_lanes) - 1);
1102 pll_val &= (~pll_bits);
1103 pll_ack_val = 0;
1104 }
1105
1106 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
1107
1108 /* Wait for acknowledgment from PHY. */
1109 ret = regmap_read_poll_timeout(regmap,
1110 PHY_PMA_XCVR_PLLCLK_EN_ACK,
1111 rd_val,
1112 (rd_val & pll_bits) == pll_ack_val,
1113 0, POLL_TIMEOUT_US);
1114 ndelay(100);
1115 return ret;
1116}
1117
1118static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1119 struct cdns_torrent_inst *inst,
1120 u32 num_lanes,
1121 enum phy_powerstate powerstate)
1122{
1123 /* Register value for power state for a single byte. */
1124 u32 value_part, i;
1125 u32 value = 0;
1126 u32 mask = 0;
1127 u32 read_val;
1128 int ret;
1129 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1130
1131 switch (powerstate) {
1132 case (POWERSTATE_A0):
1133 value_part = 0x01U;
1134 break;
1135 case (POWERSTATE_A2):
1136 value_part = 0x04U;
1137 break;
1138 default:
1139 /* Powerstate A3 */
1140 value_part = 0x08U;
1141 break;
1142 }
1143
1144 /* Select values of registers and mask, depending on enabled lane count. */
1145
1146 for (i = 0; i < num_lanes; i++) {
1147 value |= (value_part << PHY_POWER_STATE_LN(i));
1148 mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(i));
1149 }
1150
1151 /* Set power state A<n>. */
1152 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1153 /* Wait, until PHY acknowledges power state completion. */
1154 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1155 read_val, (read_val & mask) == value, 0,
1156 POLL_TIMEOUT_US);
1157 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1158 ndelay(100);
1159
1160 return ret;
1161}
1162
1163static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
1164 struct cdns_torrent_inst *inst, u32 num_lanes)
1165{
1166 unsigned int read_val;
1167 int ret;
1168 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1169
1170 /*
1171 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1172 * master lane
1173 */
1174 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1175 read_val, read_val & 1,
1176 0, POLL_TIMEOUT_US);
1177 if (ret == -ETIMEDOUT) {
1178 dev_err(cdns_phy->dev,
1179 "timeout waiting for link PLL clock enable ack\n");
1180 return ret;
1181 }
1182
1183 ndelay(100);
1184
1185 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
1186 POWERSTATE_A2);
1187 if (ret)
1188 return ret;
1189
1190 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
1191 POWERSTATE_A0);
1192
1193 return ret;
1194}
1195
1196static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1197{
1198 unsigned int reg;
1199 int ret;
1200 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1201
1202 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1203 reg & 1, 0, POLL_TIMEOUT_US);
1204 if (ret == -ETIMEDOUT) {
1205 dev_err(cdns_phy->dev,
1206 "timeout waiting for PMA common ready\n");
1207 return -ETIMEDOUT;
1208 }
1209
1210 return 0;
1211}
1212
1213static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1214 struct cdns_torrent_inst *inst,
1215 u32 rate, u32 num_lanes)
1216{
1217 unsigned int clk_sel_val = 0;
1218 unsigned int hsclk_div_val = 0;
1219 unsigned int i;
1220
1221 switch (rate) {
1222 case 1620:
1223 clk_sel_val = 0x0f01;
1224 hsclk_div_val = 2;
1225 break;
1226 case 2160:
1227 case 2430:
1228 case 2700:
1229 clk_sel_val = 0x0701;
1230 hsclk_div_val = 1;
1231 break;
1232 case 3240:
1233 clk_sel_val = 0x0b00;
1234 hsclk_div_val = 2;
1235 break;
1236 case 4320:
1237 case 5400:
1238 clk_sel_val = 0x0301;
1239 hsclk_div_val = 0;
1240 break;
1241 case 8100:
1242 clk_sel_val = 0x0200;
1243 hsclk_div_val = 0;
1244 break;
1245 }
1246
1247 if (cdns_phy->dp_pll & DP_PLL0)
1248 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1249 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1250
1251 if (cdns_phy->dp_pll & DP_PLL1)
1252 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1253 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1254
1255 /* PMA lane configuration to deal with multi-link operation */
1256 for (i = 0; i < num_lanes; i++)
1257 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],
1258 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1259}
1260
1261/*
1262 * Perform register operations related to setting link rate, once powerstate is
1263 * set and PLL disable request was processed.
1264 */
1265static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
1266 struct cdns_torrent_inst *inst,
1267 struct phy_configure_opts_dp *dp)
1268{
1269 u32 read_val, field_val;
1270 int ret;
1271
1272 /*
1273 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before
1274 * re-programming the new data rate.
1275 */
1276 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
1277 if (ret)
1278 return ret;
1279 field_val &= ~(cdns_phy->dp_pll);
1280 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
1281
1282 /*
1283 * Wait for PLL ready de-assertion.
1284 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
1285 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1
1286 */
1287 if (cdns_phy->dp_pll & DP_PLL0) {
1288 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1289 read_val,
1290 ((read_val >> 2) & 0x01) != 0,
1291 0, POLL_TIMEOUT_US);
1292 if (ret)
1293 return ret;
1294 }
1295
1296 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) {
1297 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1298 read_val,
1299 ((read_val >> 3) & 0x01) != 0,
1300 0, POLL_TIMEOUT_US);
1301 if (ret)
1302 return ret;
1303 }
1304 ndelay(200);
1305
1306 /* DP Rate Change - VCO Output settings. */
1307 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1308 /* PMA common configuration 19.2MHz */
1309 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
1310 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1311 /* PMA common configuration 25MHz */
1312 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
1313 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1314 /* PMA common configuration 100MHz */
1315 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
1316
1317 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);
1318
1319 /* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */
1320 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
1321 if (ret)
1322 return ret;
1323 field_val |= cdns_phy->dp_pll;
1324 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
1325
1326 /*
1327 * Wait for PLL ready assertion.
1328 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
1329 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1
1330 */
1331 if (cdns_phy->dp_pll & DP_PLL0) {
1332 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1333 read_val,
1334 (read_val & 0x01) != 0,
1335 0, POLL_TIMEOUT_US);
1336 if (ret)
1337 return ret;
1338 }
1339
1340 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1)
1341 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1342 read_val,
1343 ((read_val >> 1) & 0x01) != 0,
1344 0, POLL_TIMEOUT_US);
1345
1346 return ret;
1347}
1348
1349/*
1350 * Verify, that parameters to configure PHY with are correct.
1351 */
1352static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
1353 struct phy_configure_opts_dp *dp)
1354{
1355 u8 i;
1356
1357 /* If changing link rate was required, verify it's supported. */
1358 if (dp->set_rate) {
1359 switch (dp->link_rate) {
1360 case 1620:
1361 case 2160:
1362 case 2430:
1363 case 2700:
1364 case 3240:
1365 case 4320:
1366 case 5400:
1367 case 8100:
1368 /* valid bit rate */
1369 break;
1370 default:
1371 return -EINVAL;
1372 }
1373 }
1374
1375 /* Verify lane count. */
1376 switch (dp->lanes) {
1377 case 1:
1378 case 2:
1379 case 4:
1380 /* valid lane count. */
1381 break;
1382 default:
1383 return -EINVAL;
1384 }
1385
1386 /* Check against actual number of PHY's lanes. */
1387 if (dp->lanes > inst->num_lanes)
1388 return -EINVAL;
1389
1390 /*
1391 * If changing voltages is required, check swing and pre-emphasis
1392 * levels, per-lane.
1393 */
1394 if (dp->set_voltages) {
1395 /* Lane count verified previously. */
1396 for (i = 0; i < dp->lanes; i++) {
1397 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1398 return -EINVAL;
1399
1400 /* Sum of voltage swing and pre-emphasis levels cannot
1401 * exceed 3.
1402 */
1403 if (dp->voltage[i] + dp->pre[i] > 3)
1404 return -EINVAL;
1405 }
1406 }
1407
1408 return 0;
1409}
1410
1411/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
1412static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
1413 struct cdns_torrent_inst *inst,
1414 u32 num_lanes)
1415{
1416 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1417 u32 pwr_state = cdns_torrent_dp_read(regmap,
1418 PHY_PMA_XCVR_POWER_STATE_REQ);
1419 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
1420 PHY_PMA_XCVR_PLLCLK_EN);
1421 u32 i;
1422
1423 for (i = 0; i < num_lanes; i++) {
1424 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK
1425 << PHY_POWER_STATE_LN(inst->mlane + i));
1426
1427 pll_clk_en &= ~(0x01U << (inst->mlane + i));
1428 }
1429
1430 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
1431 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
1432}
1433
1434/* Configure lane count as required. */
1435static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
1436 struct cdns_torrent_inst *inst,
1437 struct phy_configure_opts_dp *dp)
1438{
1439 u32 value, i;
1440 int ret;
1441 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1442 u8 lane_mask = (1 << dp->lanes) - 1;
1443 u8 pma_tx_elec_idle_mask = 0;
1444 u32 clane = inst->mlane;
1445
1446 lane_mask <<= clane;
1447
1448 value = cdns_torrent_dp_read(regmap, PHY_RESET);
1449 /* clear pma_tx_elec_idle_ln_* bits. */
1450 pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane;
1451
1452 pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT;
1453
1454 value &= ~pma_tx_elec_idle_mask;
1455
1456 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
1457 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
1458 pma_tx_elec_idle_mask;
1459
1460 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1461
1462 /* reset the link by asserting master lane phy_l0*_reset_n low */
1463 cdns_torrent_dp_write(regmap, PHY_RESET,
1464 value & (~(1 << clane)));
1465
1466 /*
1467 * Assert lane reset on unused lanes and master lane so they remain in reset
1468 * and powered down when re-enabling the link
1469 */
1470 for (i = 0; i < inst->num_lanes; i++)
1471 value &= (~(1 << (clane + i)));
1472
1473 for (i = 1; i < inst->num_lanes; i++)
1474 value |= ((1 << (clane + i)) & lane_mask);
1475
1476 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1477
1478 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes);
1479
1480 /* release phy_l0*_reset_n based on used laneCount */
1481 for (i = 0; i < inst->num_lanes; i++)
1482 value &= (~(1 << (clane + i)));
1483
1484 for (i = 0; i < inst->num_lanes; i++)
1485 value |= ((1 << (clane + i)) & lane_mask);
1486
1487 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1488
1489 /* Wait, until PHY gets ready after releasing PHY reset signal. */
1490 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1491 if (ret)
1492 return ret;
1493
1494 ndelay(100);
1495
1496 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1497 value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1498 value |= (1 << clane);
1499 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value);
1500
1501 ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);
1502
1503 return ret;
1504}
1505
1506/* Configure link rate as required. */
1507static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
1508 struct cdns_torrent_inst *inst,
1509 struct phy_configure_opts_dp *dp)
1510{
1511 int ret;
1512
1513 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1514 POWERSTATE_A3);
1515 if (ret)
1516 return ret;
1517 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);
1518 if (ret)
1519 return ret;
1520 ndelay(200);
1521
1522 ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);
1523 if (ret)
1524 return ret;
1525 ndelay(200);
1526
1527 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);
1528 if (ret)
1529 return ret;
1530 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1531 POWERSTATE_A2);
1532 if (ret)
1533 return ret;
1534 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1535 POWERSTATE_A0);
1536 if (ret)
1537 return ret;
1538 ndelay(900);
1539
1540 return ret;
1541}
1542
1543/* Configure voltage swing and pre-emphasis for all enabled lanes. */
1544static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
1545 struct cdns_torrent_inst *inst,
1546 struct phy_configure_opts_dp *dp)
1547{
1548 u8 lane;
1549 u16 val;
1550
1551 for (lane = 0; lane < dp->lanes; lane++) {
1552 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1553 TX_DIAG_ACYA);
1554 /*
1555 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
1556 * current state of the analog TX driver.
1557 */
1558 val |= TX_DIAG_ACYA_HBDC_MASK;
1559 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1560 TX_DIAG_ACYA, val);
1561
1562 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1563 TX_TXCC_CTRL, 0x08A4);
1564 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
1565 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1566 DRV_DIAG_TX_DRV, val);
1567 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
1568 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1569 TX_TXCC_MGNFS_MULT_000,
1570 val);
1571 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
1572 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1573 TX_TXCC_CPOST_MULT_00,
1574 val);
1575
1576 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1577 TX_DIAG_ACYA);
1578 /*
1579 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
1580 * analog TX driver to reflect the new programmed one.
1581 */
1582 val &= ~TX_DIAG_ACYA_HBDC_MASK;
1583 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1584 TX_DIAG_ACYA, val);
1585 }
1586};
1587
1588static int cdns_torrent_dp_configure(struct phy *phy,
1589 union phy_configure_opts *opts)
1590{
1591 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1592 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1593 int ret;
1594
1595 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
1596 if (ret) {
1597 dev_err(&phy->dev, "invalid params for phy configure\n");
1598 return ret;
1599 }
1600
1601 if (opts->dp.set_lanes) {
1602 ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);
1603 if (ret) {
1604 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
1605 return ret;
1606 }
1607 }
1608
1609 if (opts->dp.set_rate) {
1610 ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);
1611 if (ret) {
1612 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
1613 return ret;
1614 }
1615 }
1616
1617 if (opts->dp.set_voltages)
1618 cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);
1619
1620 return ret;
1621}
1622
1623static int cdns_torrent_phy_on(struct phy *phy)
1624{
1625 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1626 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1627 u32 read_val;
1628 int ret;
1629
1630 if (cdns_phy->nsubnodes == 1) {
1631 /* Take the PHY lane group out of reset */
1632 reset_control_deassert(inst->lnk_rst);
1633
1634 /* Take the PHY out of reset */
1635 ret = reset_control_deassert(cdns_phy->phy_rst);
1636 if (ret)
1637 return ret;
1638 }
1639
1640 /*
1641 * Wait for cmn_ready assertion
1642 * PHY_PMA_CMN_CTRL1[0] == 1
1643 */
1644 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1645 read_val, read_val, 1000,
1646 PLL_LOCK_TIMEOUT);
1647 if (ret) {
1648 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1649 return ret;
1650 }
1651
1652 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
1653 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
1654 read_val, !read_val, 1000,
1655 PLL_LOCK_TIMEOUT);
1656 if (ret == -ETIMEDOUT) {
1657 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
1658 return ret;
1659 }
1660 }
1661
1662 return 0;
1663}
1664
1665static int cdns_torrent_phy_off(struct phy *phy)
1666{
1667 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1668 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1669 int ret;
1670
1671 if (cdns_phy->nsubnodes != 1)
1672 return 0;
1673
1674 ret = reset_control_assert(cdns_phy->phy_rst);
1675 if (ret)
1676 return ret;
1677
1678 return reset_control_assert(inst->lnk_rst);
1679}
1680
1681static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
1682 struct cdns_torrent_inst *inst)
1683{
1684 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1685 unsigned char lane_bits;
1686 u32 val;
1687
1688 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1689
1690 /*
1691 * Set lines power state to A0
1692 * Set lines pll clk enable to 0
1693 */
1694 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
1695
1696 /*
1697 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1698 * used lanes
1699 */
1700 lane_bits = (1 << inst->num_lanes) - 1;
1701
1702 val = cdns_torrent_dp_read(regmap, PHY_RESET);
1703 val |= (0xF & lane_bits);
1704 val &= ~(lane_bits << 4);
1705 cdns_torrent_dp_write(regmap, PHY_RESET, val);
1706
1707 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1708 val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1709 val |= 1;
1710 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val);
1711
1712 /*
1713 * PHY PMA registers configuration functions
1714 * Initialize PHY with max supported link rate, without SSC.
1715 */
1716 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1717 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1718 cdns_phy->max_bit_rate,
1719 false);
1720 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1721 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1722 cdns_phy->max_bit_rate,
1723 false);
1724 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1725 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
1726 cdns_phy->max_bit_rate,
1727 false);
1728
1729 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,
1730 inst->num_lanes);
1731
1732 /* take out of reset */
1733 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1734}
1735
1736static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
1737 struct cdns_torrent_inst *inst,
1738 struct phy *phy)
1739{
1740 int ret;
1741
1742 ret = cdns_torrent_phy_on(phy);
1743 if (ret)
1744 return ret;
1745
1746 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1747 if (ret)
1748 return ret;
1749
1750 ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);
1751
1752 return ret;
1753}
1754
1755static int cdns_torrent_dp_init(struct phy *phy)
1756{
1757 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1758 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1759 int ret;
1760
1761 switch (cdns_phy->ref_clk_rate) {
1762 case CLK_19_2_MHZ:
1763 case CLK_25_MHZ:
1764 case CLK_100_MHZ:
1765 /* Valid Ref Clock Rate */
1766 break;
1767 default:
1768 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1769 return -EINVAL;
1770 }
1771
1772 ret = cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);
1773 if (ret)
1774 return ret;
1775
1776 cdns_torrent_dp_common_init(cdns_phy, inst);
1777
1778 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1779}
1780
1781static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy,
1782 struct cdns_torrent_inst *inst,
1783 struct phy *phy)
1784{
1785 if (cdns_phy->ref_clk_rate != CLK_100_MHZ) {
1786 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1787 return -EINVAL;
1788 }
1789
1790 cdns_torrent_dp_common_init(cdns_phy, inst);
1791
1792 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1793}
1794
1795static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1796{
1797 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1798
1799 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);
1800 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1801
1802 return 0;
1803}
1804
1805static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1806{
1807 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1808
1809 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1810 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);
1811}
1812
1813static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1814{
1815 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1816 int val;
1817
1818 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);
1819
1820 return !!val;
1821}
1822
1823static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1824 .enable = cdns_torrent_derived_refclk_enable,
1825 .disable = cdns_torrent_derived_refclk_disable,
1826 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1827};
1828
1829static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1830{
1831 struct cdns_torrent_derived_refclk *derived_refclk;
1832 struct device *dev = cdns_phy->dev;
1833 struct clk_init_data *init;
1834 const char *parent_name;
1835 char clk_name[100];
1836 struct clk_hw *hw;
1837 struct clk *clk;
1838 int ret;
1839
1840 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1841 if (!derived_refclk)
1842 return -ENOMEM;
1843
1844 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1845 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);
1846
1847 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1848 if (IS_ERR(clk)) {
1849 dev_err(dev, "No parent clock for derived_refclk\n");
1850 return PTR_ERR(clk);
1851 }
1852
1853 init = &derived_refclk->clk_data;
1854
1855 if (clk) {
1856 parent_name = __clk_get_name(clk);
1857 init->parent_names = &parent_name;
1858 init->num_parents = 1;
1859 }
1860 init->ops = &cdns_torrent_derived_refclk_ops;
1861 init->flags = 0;
1862 init->name = clk_name;
1863
1864 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1865 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1866
1867 derived_refclk->hw.init = init;
1868
1869 hw = &derived_refclk->hw;
1870 ret = devm_clk_hw_register(dev, hw);
1871 if (ret)
1872 return ret;
1873
1874 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;
1875
1876 return 0;
1877}
1878
1879static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)
1880{
1881 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1882
1883 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);
1884
1885 return 0;
1886}
1887
1888static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)
1889{
1890 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1891
1892 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);
1893}
1894
1895static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)
1896{
1897 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1898 int val, cmn_val;
1899
1900 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);
1901 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);
1902
1903 return val && !cmn_val;
1904}
1905
1906static const struct clk_ops cdns_torrent_received_refclk_ops = {
1907 .enable = cdns_torrent_received_refclk_enable,
1908 .disable = cdns_torrent_received_refclk_disable,
1909 .is_enabled = cdns_torrent_received_refclk_is_enabled,
1910};
1911
1912static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)
1913{
1914 struct cdns_torrent_received_refclk *received_refclk;
1915 struct device *dev = cdns_phy->dev;
1916 struct clk_init_data *init;
1917 const char *parent_name;
1918 char clk_name[100];
1919 struct clk_hw *hw;
1920 struct clk *clk;
1921 int ret;
1922
1923 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);
1924 if (!received_refclk)
1925 return -ENOMEM;
1926
1927 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1928 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);
1929
1930 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1931 if (IS_ERR(clk)) {
1932 dev_err(dev, "No parent clock for received_refclk\n");
1933 return PTR_ERR(clk);
1934 }
1935
1936 init = &received_refclk->clk_data;
1937
1938 if (clk) {
1939 parent_name = __clk_get_name(clk);
1940 init->parent_names = &parent_name;
1941 init->num_parents = 1;
1942 }
1943 init->ops = &cdns_torrent_received_refclk_ops;
1944 init->flags = 0;
1945 init->name = clk_name;
1946
1947 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1948 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1949
1950 received_refclk->hw.init = init;
1951
1952 hw = &received_refclk->hw;
1953 ret = devm_clk_hw_register(dev, hw);
1954 if (ret)
1955 return ret;
1956
1957 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;
1958
1959 return 0;
1960}
1961
1962static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)
1963{
1964 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1965
1966 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1967 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1968 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1969
1970 return 0;
1971}
1972
1973static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)
1974{
1975 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1976
1977 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);
1978}
1979
1980static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)
1981{
1982 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1983 int val;
1984
1985 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);
1986
1987 return !val;
1988}
1989
1990static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)
1991{
1992 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1993 unsigned int val;
1994
1995 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);
1996 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);
1997}
1998
1999static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)
2000{
2001 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
2002 unsigned int val;
2003
2004 val = cdns_torrent_refclk_driver_mux_table[index];
2005 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);
2006}
2007
2008static const struct clk_ops cdns_torrent_refclk_driver_ops = {
2009 .enable = cdns_torrent_refclk_driver_enable,
2010 .disable = cdns_torrent_refclk_driver_disable,
2011 .is_enabled = cdns_torrent_refclk_driver_is_enabled,
2012 .determine_rate = __clk_mux_determine_rate,
2013 .set_parent = cdns_torrent_refclk_driver_set_parent,
2014 .get_parent = cdns_torrent_refclk_driver_get_parent,
2015};
2016
2017static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)
2018{
2019 struct cdns_torrent_refclk_driver *refclk_driver;
2020 struct device *dev = cdns_phy->dev;
2021 struct regmap_field *field;
2022 struct clk_init_data *init;
2023 const char **parent_names;
2024 unsigned int num_parents;
2025 struct regmap *regmap;
2026 char clk_name[100];
2027 struct clk_hw *hw;
2028 int i, ret;
2029
2030 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);
2031 if (!refclk_driver)
2032 return -ENOMEM;
2033
2034 num_parents = ARRAY_SIZE(refclk_driver_parent_index);
2035 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
2036 if (!parent_names)
2037 return -ENOMEM;
2038
2039 for (i = 0; i < num_parents; i++) {
2040 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];
2041 if (IS_ERR_OR_NULL(hw)) {
2042 dev_err(dev, "No parent clock for refclk driver clock\n");
2043 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;
2044 }
2045 parent_names[i] = clk_hw_get_name(hw);
2046 }
2047
2048 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
2049 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
2050
2051 init = &refclk_driver->clk_data;
2052
2053 init->ops = &cdns_torrent_refclk_driver_ops;
2054 init->flags = CLK_SET_RATE_NO_REPARENT;
2055 init->parent_names = parent_names;
2056 init->num_parents = num_parents;
2057 init->name = clk_name;
2058
2059 regmap = cdns_phy->regmap_common_cdb;
2060
2061 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
2062 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
2063 if (IS_ERR(field)) {
2064 dev_err(dev, "Refclk driver CMN reg field init failed\n");
2065 return PTR_ERR(field);
2066 }
2067 refclk_driver->cmn_fields[i] = field;
2068 }
2069
2070 /* Enable Derived reference clock as default */
2071 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
2072
2073 refclk_driver->hw.init = init;
2074
2075 hw = &refclk_driver->hw;
2076 ret = devm_clk_hw_register(dev, hw);
2077 if (ret)
2078 return ret;
2079
2080 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;
2081
2082 return 0;
2083}
2084
2085static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
2086 u32 block_offset,
2087 u8 reg_offset_shift,
2088 const struct regmap_config *config)
2089{
2090 struct cdns_regmap_cdb_context *ctx;
2091
2092 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2093 if (!ctx)
2094 return ERR_PTR(-ENOMEM);
2095
2096 ctx->dev = dev;
2097 ctx->base = base + block_offset;
2098 ctx->reg_offset_shift = reg_offset_shift;
2099
2100 return devm_regmap_init(dev, NULL, ctx, config);
2101}
2102
2103static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
2104{
2105 struct device *dev = cdns_phy->dev;
2106 struct regmap_field *field;
2107 struct regmap *regmap;
2108
2109 regmap = cdns_phy->regmap_dptx_phy_reg;
2110 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
2111 if (IS_ERR(field)) {
2112 dev_err(dev, "PHY_RESET reg field init failed\n");
2113 return PTR_ERR(field);
2114 }
2115 cdns_phy->phy_reset_ctrl = field;
2116
2117 return 0;
2118}
2119
2120static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
2121{
2122 struct device *dev = cdns_phy->dev;
2123 struct regmap_field *field;
2124 struct regmap *regmap;
2125 int i;
2126
2127 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2128 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
2129 if (IS_ERR(field)) {
2130 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
2131 return PTR_ERR(field);
2132 }
2133 cdns_phy->phy_pll_cfg = field;
2134
2135 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2136 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
2137 if (IS_ERR(field)) {
2138 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
2139 return PTR_ERR(field);
2140 }
2141 cdns_phy->phy_pipe_cmn_ctrl1_0 = field;
2142
2143 regmap = cdns_phy->regmap_common_cdb;
2144 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);
2145 if (IS_ERR(field)) {
2146 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");
2147 return PTR_ERR(field);
2148 }
2149 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;
2150
2151 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2152 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
2153 if (IS_ERR(field)) {
2154 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
2155 return PTR_ERR(field);
2156 }
2157 cdns_phy->phy_pma_cmn_ctrl_1 = field;
2158
2159 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2160 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
2161 if (IS_ERR(field)) {
2162 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
2163 return PTR_ERR(field);
2164 }
2165 cdns_phy->phy_pma_cmn_ctrl_2 = field;
2166
2167 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2168 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
2169 if (IS_ERR(field)) {
2170 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
2171 return PTR_ERR(field);
2172 }
2173 cdns_phy->phy_pma_pll_raw_ctrl = field;
2174
2175 for (i = 0; i < MAX_NUM_LANES; i++) {
2176 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
2177 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
2178 if (IS_ERR(field)) {
2179 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
2180 return PTR_ERR(field);
2181 }
2182 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
2183 }
2184
2185 return 0;
2186}
2187
2188static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
2189{
2190 void __iomem *base = cdns_phy->base;
2191 struct device *dev = cdns_phy->dev;
2192 struct regmap *regmap;
2193 u8 reg_offset_shift;
2194 u32 block_offset;
2195
2196 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2197
2198 block_offset = TORRENT_DPTX_PHY_OFFSET;
2199 regmap = cdns_regmap_init(dev, base, block_offset,
2200 reg_offset_shift,
2201 &cdns_torrent_dptx_phy_config);
2202 if (IS_ERR(regmap)) {
2203 dev_err(dev, "Failed to init DPTX PHY regmap\n");
2204 return PTR_ERR(regmap);
2205 }
2206 cdns_phy->regmap_dptx_phy_reg = regmap;
2207
2208 return 0;
2209}
2210
2211static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
2212{
2213 void __iomem *sd_base = cdns_phy->sd_base;
2214 u8 block_offset_shift, reg_offset_shift;
2215 struct device *dev = cdns_phy->dev;
2216 struct regmap *regmap;
2217 u32 block_offset;
2218 int i;
2219
2220 block_offset_shift = cdns_phy->init_data->block_offset_shift;
2221 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2222
2223 for (i = 0; i < MAX_NUM_LANES; i++) {
2224 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
2225 reg_offset_shift);
2226 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2227 reg_offset_shift,
2228 &cdns_torrent_tx_lane_cdb_config[i]);
2229 if (IS_ERR(regmap)) {
2230 dev_err(dev, "Failed to init tx lane CDB regmap\n");
2231 return PTR_ERR(regmap);
2232 }
2233 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
2234
2235 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
2236 reg_offset_shift);
2237 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2238 reg_offset_shift,
2239 &cdns_torrent_rx_lane_cdb_config[i]);
2240 if (IS_ERR(regmap)) {
2241 dev_err(dev, "Failed to init rx lane CDB regmap\n");
2242 return PTR_ERR(regmap);
2243 }
2244 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
2245
2246 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
2247 reg_offset_shift);
2248 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2249 reg_offset_shift,
2250 &cdns_torrent_phy_pcs_lane_cdb_config[i]);
2251 if (IS_ERR(regmap)) {
2252 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
2253 return PTR_ERR(regmap);
2254 }
2255 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
2256 }
2257
2258 block_offset = TORRENT_COMMON_CDB_OFFSET;
2259 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2260 reg_offset_shift,
2261 &cdns_torrent_common_cdb_config);
2262 if (IS_ERR(regmap)) {
2263 dev_err(dev, "Failed to init common CDB regmap\n");
2264 return PTR_ERR(regmap);
2265 }
2266 cdns_phy->regmap_common_cdb = regmap;
2267
2268 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
2269 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2270 reg_offset_shift,
2271 &cdns_torrent_phy_pcs_cmn_cdb_config);
2272 if (IS_ERR(regmap)) {
2273 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
2274 return PTR_ERR(regmap);
2275 }
2276 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
2277
2278 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
2279 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2280 reg_offset_shift,
2281 &cdns_torrent_phy_pma_cmn_cdb_config);
2282 if (IS_ERR(regmap)) {
2283 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
2284 return PTR_ERR(regmap);
2285 }
2286 cdns_phy->regmap_phy_pma_common_cdb = regmap;
2287
2288 return 0;
2289}
2290
2291static int cdns_torrent_phy_init(struct phy *phy)
2292{
2293 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
2294 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2295 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2296 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2297 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2298 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
2299 enum cdns_torrent_phy_type phy_type = inst->phy_type;
2300 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
2301 struct cdns_torrent_vals *phy_pma_cmn_vals;
2302 struct cdns_torrent_vals *pcs_cmn_vals;
2303 struct cdns_reg_pairs *reg_pairs;
2304 struct regmap *regmap;
2305 u32 num_regs;
2306 int i, j;
2307
2308 if (cdns_phy->nsubnodes > 1) {
2309 if (phy_type == TYPE_DP)
2310 return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
2311 return 0;
2312 }
2313
2314 /**
2315 * Spread spectrum generation is not required or supported
2316 * for SGMII/QSGMII/USXGMII
2317 */
2318 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII || phy_type == TYPE_USXGMII)
2319 ssc = NO_SSC;
2320
2321 /* PHY configuration specific registers for single link */
2322 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl,
2323 CLK_ANY, CLK_ANY,
2324 phy_type, TYPE_NONE,
2325 ANY_SSC);
2326 if (link_cmn_vals) {
2327 reg_pairs = link_cmn_vals->reg_pairs;
2328 num_regs = link_cmn_vals->num_regs;
2329 regmap = cdns_phy->regmap_common_cdb;
2330
2331 /**
2332 * First array value in link_cmn_vals must be of
2333 * PHY_PLL_CFG register
2334 */
2335 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2336
2337 for (i = 1; i < num_regs; i++)
2338 regmap_write(regmap, reg_pairs[i].off,
2339 reg_pairs[i].val);
2340 }
2341
2342 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl,
2343 CLK_ANY, CLK_ANY,
2344 phy_type, TYPE_NONE,
2345 ANY_SSC);
2346 if (xcvr_diag_vals) {
2347 reg_pairs = xcvr_diag_vals->reg_pairs;
2348 num_regs = xcvr_diag_vals->num_regs;
2349 for (i = 0; i < inst->num_lanes; i++) {
2350 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2351 for (j = 0; j < num_regs; j++)
2352 regmap_write(regmap, reg_pairs[j].off,
2353 reg_pairs[j].val);
2354 }
2355 }
2356
2357 /* PHY PCS common registers configurations */
2358 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl,
2359 CLK_ANY, CLK_ANY,
2360 phy_type, TYPE_NONE,
2361 ANY_SSC);
2362 if (pcs_cmn_vals) {
2363 reg_pairs = pcs_cmn_vals->reg_pairs;
2364 num_regs = pcs_cmn_vals->num_regs;
2365 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2366 for (i = 0; i < num_regs; i++)
2367 regmap_write(regmap, reg_pairs[i].off,
2368 reg_pairs[i].val);
2369 }
2370
2371 /* PHY PMA common registers configurations */
2372 phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,
2373 CLK_ANY, CLK_ANY,
2374 phy_type, TYPE_NONE,
2375 ANY_SSC);
2376 if (phy_pma_cmn_vals) {
2377 reg_pairs = phy_pma_cmn_vals->reg_pairs;
2378 num_regs = phy_pma_cmn_vals->num_regs;
2379 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2380 for (i = 0; i < num_regs; i++)
2381 regmap_write(regmap, reg_pairs[i].off,
2382 reg_pairs[i].val);
2383 }
2384
2385 /* PMA common registers configurations */
2386 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,
2387 ref_clk, ref_clk,
2388 phy_type, TYPE_NONE,
2389 ssc);
2390 if (cmn_vals) {
2391 reg_pairs = cmn_vals->reg_pairs;
2392 num_regs = cmn_vals->num_regs;
2393 regmap = cdns_phy->regmap_common_cdb;
2394 for (i = 0; i < num_regs; i++)
2395 regmap_write(regmap, reg_pairs[i].off,
2396 reg_pairs[i].val);
2397 }
2398
2399 /* PMA TX lane registers configurations */
2400 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,
2401 ref_clk, ref_clk,
2402 phy_type, TYPE_NONE,
2403 ssc);
2404 if (tx_ln_vals) {
2405 reg_pairs = tx_ln_vals->reg_pairs;
2406 num_regs = tx_ln_vals->num_regs;
2407 for (i = 0; i < inst->num_lanes; i++) {
2408 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2409 for (j = 0; j < num_regs; j++)
2410 regmap_write(regmap, reg_pairs[j].off,
2411 reg_pairs[j].val);
2412 }
2413 }
2414
2415 /* PMA RX lane registers configurations */
2416 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,
2417 ref_clk, ref_clk,
2418 phy_type, TYPE_NONE,
2419 ssc);
2420 if (rx_ln_vals) {
2421 reg_pairs = rx_ln_vals->reg_pairs;
2422 num_regs = rx_ln_vals->num_regs;
2423 for (i = 0; i < inst->num_lanes; i++) {
2424 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2425 for (j = 0; j < num_regs; j++)
2426 regmap_write(regmap, reg_pairs[j].off,
2427 reg_pairs[j].val);
2428 }
2429 }
2430
2431 if (phy_type == TYPE_DP)
2432 return cdns_torrent_dp_init(phy);
2433
2434 return 0;
2435}
2436
2437static const struct phy_ops cdns_torrent_phy_ops = {
2438 .init = cdns_torrent_phy_init,
2439 .configure = cdns_torrent_dp_configure,
2440 .power_on = cdns_torrent_phy_on,
2441 .power_off = cdns_torrent_phy_off,
2442 .owner = THIS_MODULE,
2443};
2444
2445static int cdns_torrent_noop_phy_on(struct phy *phy)
2446{
2447 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
2448 usleep_range(5000, 10000);
2449
2450 return 0;
2451}
2452
2453static const struct phy_ops noop_ops = {
2454 .power_on = cdns_torrent_noop_phy_on,
2455 .owner = THIS_MODULE,
2456};
2457
2458static
2459int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2460{
2461 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2462 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2463 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2464 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2465 enum cdns_torrent_phy_type phy_t1, phy_t2;
2466 struct cdns_torrent_vals *pcs_cmn_vals;
2467 int i, j, node, mlane, num_lanes, ret;
2468 struct cdns_reg_pairs *reg_pairs;
2469 enum cdns_torrent_ssc_mode ssc;
2470 struct regmap *regmap;
2471 u32 num_regs;
2472
2473 /* Maximum 2 links (subnodes) are supported */
2474 if (cdns_phy->nsubnodes != 2)
2475 return -EINVAL;
2476
2477 phy_t1 = cdns_phy->phys[0].phy_type;
2478 phy_t2 = cdns_phy->phys[1].phy_type;
2479
2480 /**
2481 * First configure the PHY for first link with phy_t1. Get the array
2482 * values as [phy_t1][phy_t2][ssc].
2483 */
2484 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2485 if (node == 1) {
2486 /**
2487 * If first link with phy_t1 is configured, then
2488 * configure the PHY for second link with phy_t2.
2489 * Get the array values as [phy_t2][phy_t1][ssc].
2490 */
2491 swap(phy_t1, phy_t2);
2492 }
2493
2494 mlane = cdns_phy->phys[node].mlane;
2495 ssc = cdns_phy->phys[node].ssc_mode;
2496 num_lanes = cdns_phy->phys[node].num_lanes;
2497
2498 /**
2499 * PHY configuration specific registers:
2500 * link_cmn_vals depend on combination of PHY types being
2501 * configured and are common for both PHY types, so array
2502 * values should be same for [phy_t1][phy_t2][ssc] and
2503 * [phy_t2][phy_t1][ssc].
2504 * xcvr_diag_vals also depend on combination of PHY types
2505 * being configured, but these can be different for particular
2506 * PHY type and are per lane.
2507 */
2508 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl,
2509 CLK_ANY, CLK_ANY,
2510 phy_t1, phy_t2, ANY_SSC);
2511 if (link_cmn_vals) {
2512 reg_pairs = link_cmn_vals->reg_pairs;
2513 num_regs = link_cmn_vals->num_regs;
2514 regmap = cdns_phy->regmap_common_cdb;
2515
2516 /**
2517 * First array value in link_cmn_vals must be of
2518 * PHY_PLL_CFG register
2519 */
2520 regmap_field_write(cdns_phy->phy_pll_cfg,
2521 reg_pairs[0].val);
2522
2523 for (i = 1; i < num_regs; i++)
2524 regmap_write(regmap, reg_pairs[i].off,
2525 reg_pairs[i].val);
2526 }
2527
2528 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl,
2529 CLK_ANY, CLK_ANY,
2530 phy_t1, phy_t2, ANY_SSC);
2531 if (xcvr_diag_vals) {
2532 reg_pairs = xcvr_diag_vals->reg_pairs;
2533 num_regs = xcvr_diag_vals->num_regs;
2534 for (i = 0; i < num_lanes; i++) {
2535 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2536 for (j = 0; j < num_regs; j++)
2537 regmap_write(regmap, reg_pairs[j].off,
2538 reg_pairs[j].val);
2539 }
2540 }
2541
2542 /* PHY PCS common registers configurations */
2543 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl,
2544 CLK_ANY, CLK_ANY,
2545 phy_t1, phy_t2, ANY_SSC);
2546 if (pcs_cmn_vals) {
2547 reg_pairs = pcs_cmn_vals->reg_pairs;
2548 num_regs = pcs_cmn_vals->num_regs;
2549 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2550 for (i = 0; i < num_regs; i++)
2551 regmap_write(regmap, reg_pairs[i].off,
2552 reg_pairs[i].val);
2553 }
2554
2555 /* PMA common registers configurations */
2556 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,
2557 ref_clk, ref_clk,
2558 phy_t1, phy_t2, ssc);
2559 if (cmn_vals) {
2560 reg_pairs = cmn_vals->reg_pairs;
2561 num_regs = cmn_vals->num_regs;
2562 regmap = cdns_phy->regmap_common_cdb;
2563 for (i = 0; i < num_regs; i++)
2564 regmap_write(regmap, reg_pairs[i].off,
2565 reg_pairs[i].val);
2566 }
2567
2568 /* PMA TX lane registers configurations */
2569 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,
2570 ref_clk, ref_clk,
2571 phy_t1, phy_t2, ssc);
2572 if (tx_ln_vals) {
2573 reg_pairs = tx_ln_vals->reg_pairs;
2574 num_regs = tx_ln_vals->num_regs;
2575 for (i = 0; i < num_lanes; i++) {
2576 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2577 for (j = 0; j < num_regs; j++)
2578 regmap_write(regmap, reg_pairs[j].off,
2579 reg_pairs[j].val);
2580 }
2581 }
2582
2583 /* PMA RX lane registers configurations */
2584 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,
2585 ref_clk, ref_clk,
2586 phy_t1, phy_t2, ssc);
2587 if (rx_ln_vals) {
2588 reg_pairs = rx_ln_vals->reg_pairs;
2589 num_regs = rx_ln_vals->num_regs;
2590 for (i = 0; i < num_lanes; i++) {
2591 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2592 for (j = 0; j < num_regs; j++)
2593 regmap_write(regmap, reg_pairs[j].off,
2594 reg_pairs[j].val);
2595 }
2596 }
2597
2598 if (phy_t1 == TYPE_DP) {
2599 ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2);
2600 if (ret)
2601 return ret;
2602 }
2603
2604 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2605 }
2606
2607 /* Take the PHY out of reset */
2608 ret = reset_control_deassert(cdns_phy->phy_rst);
2609 if (ret)
2610 return ret;
2611
2612 return 0;
2613}
2614
2615static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2616{
2617 struct device *dev = cdns_phy->dev;
2618
2619 of_clk_del_provider(dev->of_node);
2620}
2621
2622static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2623{
2624 struct device *dev = cdns_phy->dev;
2625 struct device_node *node = dev->of_node;
2626 struct clk_hw_onecell_data *data;
2627 int ret;
2628
2629 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);
2630 if (!data)
2631 return -ENOMEM;
2632
2633 data->num = CDNS_TORRENT_OUTPUT_CLOCKS;
2634 cdns_phy->clk_hw_data = data;
2635
2636 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2637 if (ret) {
2638 dev_err(dev, "failed to register derived refclk\n");
2639 return ret;
2640 }
2641
2642 ret = cdns_torrent_received_refclk_register(cdns_phy);
2643 if (ret) {
2644 dev_err(dev, "failed to register received refclk\n");
2645 return ret;
2646 }
2647
2648 ret = cdns_torrent_refclk_driver_register(cdns_phy);
2649 if (ret) {
2650 dev_err(dev, "failed to register refclk driver\n");
2651 return ret;
2652 }
2653
2654 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
2655 if (ret) {
2656 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2657 return ret;
2658 }
2659
2660 return 0;
2661}
2662
2663static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2664{
2665 struct device *dev = cdns_phy->dev;
2666
2667 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2668 if (IS_ERR(cdns_phy->phy_rst)) {
2669 dev_err(dev, "%s: failed to get reset\n",
2670 dev->of_node->full_name);
2671 return PTR_ERR(cdns_phy->phy_rst);
2672 }
2673
2674 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2675 if (IS_ERR(cdns_phy->apb_rst)) {
2676 dev_err(dev, "%s: failed to get apb reset\n",
2677 dev->of_node->full_name);
2678 return PTR_ERR(cdns_phy->apb_rst);
2679 }
2680
2681 return 0;
2682}
2683
2684static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2685{
2686 struct device *dev = cdns_phy->dev;
2687 unsigned long ref_clk_rate;
2688 int ret;
2689
2690 cdns_phy->clk = devm_clk_get(dev, "refclk");
2691 if (IS_ERR(cdns_phy->clk)) {
2692 dev_err(dev, "phy ref clock not found\n");
2693 return PTR_ERR(cdns_phy->clk);
2694 }
2695
2696 ret = clk_prepare_enable(cdns_phy->clk);
2697 if (ret) {
2698 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2699 return ret;
2700 }
2701
2702 ref_clk_rate = clk_get_rate(cdns_phy->clk);
2703 if (!ref_clk_rate) {
2704 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2705 clk_disable_unprepare(cdns_phy->clk);
2706 return -EINVAL;
2707 }
2708
2709 switch (ref_clk_rate) {
2710 case REF_CLK_19_2MHZ:
2711 cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
2712 break;
2713 case REF_CLK_25MHZ:
2714 cdns_phy->ref_clk_rate = CLK_25_MHZ;
2715 break;
2716 case REF_CLK_100MHZ:
2717 cdns_phy->ref_clk_rate = CLK_100_MHZ;
2718 break;
2719 case REF_CLK_156_25MHZ:
2720 cdns_phy->ref_clk_rate = CLK_156_25_MHZ;
2721 break;
2722 default:
2723 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2724 clk_disable_unprepare(cdns_phy->clk);
2725 return -EINVAL;
2726 }
2727
2728 return 0;
2729}
2730
2731static int cdns_torrent_phy_probe(struct platform_device *pdev)
2732{
2733 struct cdns_torrent_phy *cdns_phy;
2734 struct device *dev = &pdev->dev;
2735 struct phy_provider *phy_provider;
2736 const struct cdns_torrent_data *data;
2737 struct device_node *child;
2738 int ret, subnodes, node = 0, i;
2739 u32 total_num_lanes = 0;
2740 int already_configured;
2741 u8 init_dp_regmap = 0;
2742 u32 phy_type;
2743
2744 /* Get init data for this PHY */
2745 data = of_device_get_match_data(dev);
2746 if (!data)
2747 return -EINVAL;
2748
2749 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2750 if (!cdns_phy)
2751 return -ENOMEM;
2752
2753 dev_set_drvdata(dev, cdns_phy);
2754 cdns_phy->dev = dev;
2755 cdns_phy->init_data = data;
2756
2757 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2758 if (IS_ERR(cdns_phy->sd_base))
2759 return PTR_ERR(cdns_phy->sd_base);
2760
2761 subnodes = of_get_available_child_count(dev->of_node);
2762 if (subnodes == 0) {
2763 dev_err(dev, "No available link subnodes found\n");
2764 return -EINVAL;
2765 }
2766
2767 ret = cdns_torrent_regmap_init(cdns_phy);
2768 if (ret)
2769 return ret;
2770
2771 ret = cdns_torrent_regfield_init(cdns_phy);
2772 if (ret)
2773 return ret;
2774
2775 ret = cdns_torrent_clk_register(cdns_phy);
2776 if (ret)
2777 return ret;
2778
2779 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2780
2781 if (!already_configured) {
2782 ret = cdns_torrent_reset(cdns_phy);
2783 if (ret)
2784 goto clk_cleanup;
2785
2786 ret = cdns_torrent_clk(cdns_phy);
2787 if (ret)
2788 goto clk_cleanup;
2789
2790 /* Enable APB */
2791 reset_control_deassert(cdns_phy->apb_rst);
2792 }
2793
2794 for_each_available_child_of_node(dev->of_node, child) {
2795 struct phy *gphy;
2796
2797 /* PHY subnode name must be 'phy'. */
2798 if (!(of_node_name_eq(child, "phy")))
2799 continue;
2800
2801 cdns_phy->phys[node].lnk_rst =
2802 of_reset_control_array_get_exclusive(child);
2803 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2804 dev_err(dev, "%s: failed to get reset\n",
2805 child->full_name);
2806 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2807 goto put_lnk_rst;
2808 }
2809
2810 if (of_property_read_u32(child, "reg",
2811 &cdns_phy->phys[node].mlane)) {
2812 dev_err(dev, "%s: No \"reg\"-property.\n",
2813 child->full_name);
2814 ret = -EINVAL;
2815 goto put_child;
2816 }
2817
2818 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2819 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2820 child->full_name);
2821 ret = -EINVAL;
2822 goto put_child;
2823 }
2824
2825 switch (phy_type) {
2826 case PHY_TYPE_PCIE:
2827 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2828 break;
2829 case PHY_TYPE_DP:
2830 cdns_phy->phys[node].phy_type = TYPE_DP;
2831 break;
2832 case PHY_TYPE_SGMII:
2833 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2834 break;
2835 case PHY_TYPE_QSGMII:
2836 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2837 break;
2838 case PHY_TYPE_USB3:
2839 cdns_phy->phys[node].phy_type = TYPE_USB;
2840 break;
2841 case PHY_TYPE_USXGMII:
2842 cdns_phy->phys[node].phy_type = TYPE_USXGMII;
2843 break;
2844 default:
2845 dev_err(dev, "Unsupported protocol\n");
2846 ret = -EINVAL;
2847 goto put_child;
2848 }
2849
2850 if (of_property_read_u32(child, "cdns,num-lanes",
2851 &cdns_phy->phys[node].num_lanes)) {
2852 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2853 child->full_name);
2854 ret = -EINVAL;
2855 goto put_child;
2856 }
2857
2858 total_num_lanes += cdns_phy->phys[node].num_lanes;
2859
2860 /* Get SSC mode */
2861 cdns_phy->phys[node].ssc_mode = NO_SSC;
2862 of_property_read_u32(child, "cdns,ssc-mode",
2863 &cdns_phy->phys[node].ssc_mode);
2864
2865 if (!already_configured)
2866 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2867 else
2868 gphy = devm_phy_create(dev, child, &noop_ops);
2869 if (IS_ERR(gphy)) {
2870 ret = PTR_ERR(gphy);
2871 goto put_child;
2872 }
2873
2874 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2875 switch (cdns_phy->phys[node].num_lanes) {
2876 case 1:
2877 case 2:
2878 case 4:
2879 /* valid number of lanes */
2880 break;
2881 default:
2882 dev_err(dev, "unsupported number of lanes: %d\n",
2883 cdns_phy->phys[node].num_lanes);
2884 ret = -EINVAL;
2885 goto put_child;
2886 }
2887
2888 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2889 of_property_read_u32(child, "cdns,max-bit-rate",
2890 &cdns_phy->max_bit_rate);
2891
2892 switch (cdns_phy->max_bit_rate) {
2893 case 1620:
2894 case 2160:
2895 case 2430:
2896 case 2700:
2897 case 3240:
2898 case 4320:
2899 case 5400:
2900 case 8100:
2901 /* valid bit rate */
2902 break;
2903 default:
2904 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2905 cdns_phy->max_bit_rate);
2906 ret = -EINVAL;
2907 goto put_child;
2908 }
2909
2910 /* DPTX registers */
2911 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2912 if (IS_ERR(cdns_phy->base)) {
2913 ret = PTR_ERR(cdns_phy->base);
2914 goto put_child;
2915 }
2916
2917 if (!init_dp_regmap) {
2918 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2919 if (ret)
2920 goto put_child;
2921
2922 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2923 if (ret)
2924 goto put_child;
2925
2926 init_dp_regmap++;
2927 }
2928
2929 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
2930 cdns_phy->max_bit_rate / 1000,
2931 cdns_phy->max_bit_rate % 1000);
2932
2933 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2934 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2935 gphy->attrs.mode = PHY_MODE_DP;
2936 }
2937
2938 cdns_phy->phys[node].phy = gphy;
2939 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2940
2941 node++;
2942 }
2943 cdns_phy->nsubnodes = node;
2944
2945 if (total_num_lanes > MAX_NUM_LANES) {
2946 dev_err(dev, "Invalid lane configuration\n");
2947 ret = -EINVAL;
2948 goto put_lnk_rst;
2949 }
2950
2951 if (cdns_phy->nsubnodes > 1 && !already_configured) {
2952 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2953 if (ret)
2954 goto put_lnk_rst;
2955 }
2956
2957 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2958 if (IS_ERR(phy_provider)) {
2959 ret = PTR_ERR(phy_provider);
2960 goto put_lnk_rst;
2961 }
2962
2963 if (cdns_phy->nsubnodes > 1)
2964 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
2965 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2966 cdns_phy->phys[0].num_lanes,
2967 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
2968 cdns_phy->phys[1].num_lanes);
2969 else
2970 dev_dbg(dev, "Single link: %s (%d lanes)",
2971 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2972 cdns_phy->phys[0].num_lanes);
2973
2974 return 0;
2975
2976put_child:
2977 node++;
2978put_lnk_rst:
2979 for (i = 0; i < node; i++)
2980 reset_control_put(cdns_phy->phys[i].lnk_rst);
2981 of_node_put(child);
2982 reset_control_assert(cdns_phy->apb_rst);
2983 clk_disable_unprepare(cdns_phy->clk);
2984clk_cleanup:
2985 cdns_torrent_clk_cleanup(cdns_phy);
2986 return ret;
2987}
2988
2989static void cdns_torrent_phy_remove(struct platform_device *pdev)
2990{
2991 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2992 int i;
2993
2994 reset_control_assert(cdns_phy->phy_rst);
2995 reset_control_assert(cdns_phy->apb_rst);
2996 for (i = 0; i < cdns_phy->nsubnodes; i++) {
2997 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2998 reset_control_put(cdns_phy->phys[i].lnk_rst);
2999 }
3000
3001 clk_disable_unprepare(cdns_phy->clk);
3002 cdns_torrent_clk_cleanup(cdns_phy);
3003}
3004
3005/* USB and DP link configuration */
3006static struct cdns_reg_pairs usb_dp_link_cmn_regs[] = {
3007 {0x0002, PHY_PLL_CFG},
3008 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3009};
3010
3011static struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = {
3012 {0x0000, XCVR_DIAG_HSCLK_SEL},
3013 {0x0001, XCVR_DIAG_HSCLK_DIV},
3014 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3015};
3016
3017static struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = {
3018 {0x0001, XCVR_DIAG_HSCLK_SEL},
3019 {0x0009, XCVR_DIAG_PLLDRC_CTRL}
3020};
3021
3022static struct cdns_torrent_vals usb_dp_link_cmn_vals = {
3023 .reg_pairs = usb_dp_link_cmn_regs,
3024 .num_regs = ARRAY_SIZE(usb_dp_link_cmn_regs),
3025};
3026
3027static struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = {
3028 .reg_pairs = usb_dp_xcvr_diag_ln_regs,
3029 .num_regs = ARRAY_SIZE(usb_dp_xcvr_diag_ln_regs),
3030};
3031
3032static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = {
3033 .reg_pairs = dp_usb_xcvr_diag_ln_regs,
3034 .num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs),
3035};
3036
3037/* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */
3038static struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = {
3039 {0x0040, PHY_PMA_CMN_CTRL1},
3040};
3041
3042static struct cdns_torrent_vals ti_usxgmii_phy_pma_cmn_vals = {
3043 .reg_pairs = ti_usxgmii_phy_pma_cmn_regs,
3044 .num_regs = ARRAY_SIZE(ti_usxgmii_phy_pma_cmn_regs),
3045};
3046
3047/* Single USXGMII link configuration */
3048static struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = {
3049 {0x0000, PHY_PLL_CFG},
3050 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0}
3051};
3052
3053static struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = {
3054 {0x0000, XCVR_DIAG_HSCLK_SEL},
3055 {0x0001, XCVR_DIAG_HSCLK_DIV},
3056 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
3057};
3058
3059static struct cdns_torrent_vals sl_usxgmii_link_cmn_vals = {
3060 .reg_pairs = sl_usxgmii_link_cmn_regs,
3061 .num_regs = ARRAY_SIZE(sl_usxgmii_link_cmn_regs),
3062};
3063
3064static struct cdns_torrent_vals sl_usxgmii_xcvr_diag_ln_vals = {
3065 .reg_pairs = sl_usxgmii_xcvr_diag_ln_regs,
3066 .num_regs = ARRAY_SIZE(sl_usxgmii_xcvr_diag_ln_regs),
3067};
3068
3069/* Single link USXGMII, 156.25 MHz Ref clk, no SSC */
3070static struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = {
3071 {0x0014, CMN_SSM_BIAS_TMR},
3072 {0x0028, CMN_PLLSM0_PLLPRE_TMR},
3073 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR},
3074 {0x0028, CMN_PLLSM1_PLLPRE_TMR},
3075 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR},
3076 {0x0062, CMN_BGCAL_INIT_TMR},
3077 {0x0062, CMN_BGCAL_ITER_TMR},
3078 {0x0014, CMN_IBCAL_INIT_TMR},
3079 {0x0018, CMN_TXPUCAL_INIT_TMR},
3080 {0x0005, CMN_TXPUCAL_ITER_TMR},
3081 {0x0018, CMN_TXPDCAL_INIT_TMR},
3082 {0x0005, CMN_TXPDCAL_ITER_TMR},
3083 {0x024A, CMN_RXCAL_INIT_TMR},
3084 {0x0005, CMN_RXCAL_ITER_TMR},
3085 {0x000B, CMN_SD_CAL_REFTIM_START},
3086 {0x0132, CMN_SD_CAL_PLLCNT_START},
3087 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3088 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},
3089 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},
3090 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},
3091 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},
3092 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR},
3093 {0x061B, CMN_PLL1_VCOCAL_INIT_TMR},
3094 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR},
3095 {0x0019, CMN_PLL1_VCOCAL_ITER_TMR},
3096 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START},
3097 {0x1354, CMN_PLL1_VCOCAL_REFTIM_START},
3098 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},
3099 {0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},
3100 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3101 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3102 {0x0138, CMN_PLL0_LOCK_REFCNT_START},
3103 {0x0138, CMN_PLL1_LOCK_REFCNT_START},
3104 {0x0138, CMN_PLL0_LOCK_PLLCNT_START},
3105 {0x0138, CMN_PLL1_LOCK_PLLCNT_START}
3106};
3107
3108static struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = {
3109 {0x07A2, TX_RCVDET_ST_TMR},
3110 {0x00F3, TX_PSC_A0},
3111 {0x04A2, TX_PSC_A2},
3112 {0x04A2, TX_PSC_A3},
3113 {0x0000, TX_TXCC_CPOST_MULT_00},
3114 {0x0000, XCVR_DIAG_PSC_OVRD}
3115};
3116
3117static struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = {
3118 {0x0014, RX_SDCAL0_INIT_TMR},
3119 {0x0062, RX_SDCAL0_ITER_TMR},
3120 {0x0014, RX_SDCAL1_INIT_TMR},
3121 {0x0062, RX_SDCAL1_ITER_TMR},
3122 {0x091D, RX_PSC_A0},
3123 {0x0900, RX_PSC_A2},
3124 {0x0100, RX_PSC_A3},
3125 {0x0030, RX_REE_SMGM_CTRL1},
3126 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3127 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3128 {0x0000, RX_DIAG_DFE_CTRL},
3129 {0x0019, RX_REE_TAP1_CLIP},
3130 {0x0019, RX_REE_TAP2TON_CLIP},
3131 {0x00B9, RX_DIAG_NQST_CTRL},
3132 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3133 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3134 {0x0033, RX_DIAG_PI_RATE},
3135 {0x0001, RX_DIAG_ACYA},
3136 {0x018C, RX_CDRLF_CNFG}
3137};
3138
3139static struct cdns_torrent_vals sl_usxgmii_156_25_no_ssc_cmn_vals = {
3140 .reg_pairs = sl_usxgmii_156_25_no_ssc_cmn_regs,
3141 .num_regs = ARRAY_SIZE(sl_usxgmii_156_25_no_ssc_cmn_regs),
3142};
3143
3144static struct cdns_torrent_vals usxgmii_156_25_no_ssc_tx_ln_vals = {
3145 .reg_pairs = usxgmii_156_25_no_ssc_tx_ln_regs,
3146 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_tx_ln_regs),
3147};
3148
3149static struct cdns_torrent_vals usxgmii_156_25_no_ssc_rx_ln_vals = {
3150 .reg_pairs = usxgmii_156_25_no_ssc_rx_ln_regs,
3151 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_rx_ln_regs),
3152};
3153
3154/* PCIe and DP link configuration */
3155static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = {
3156 {0x0003, PHY_PLL_CFG},
3157 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3158 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}
3159};
3160
3161static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = {
3162 {0x0000, XCVR_DIAG_HSCLK_SEL},
3163 {0x0001, XCVR_DIAG_HSCLK_DIV},
3164 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3165};
3166
3167static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = {
3168 {0x0001, XCVR_DIAG_HSCLK_SEL},
3169 {0x0009, XCVR_DIAG_PLLDRC_CTRL}
3170};
3171
3172static struct cdns_torrent_vals pcie_dp_link_cmn_vals = {
3173 .reg_pairs = pcie_dp_link_cmn_regs,
3174 .num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs),
3175};
3176
3177static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = {
3178 .reg_pairs = pcie_dp_xcvr_diag_ln_regs,
3179 .num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs),
3180};
3181
3182static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = {
3183 .reg_pairs = dp_pcie_xcvr_diag_ln_regs,
3184 .num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs),
3185};
3186
3187/* DP Multilink, 100 MHz Ref clk, no SSC */
3188static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = {
3189 {0x007F, CMN_TXPUCAL_TUNE},
3190 {0x007F, CMN_TXPDCAL_TUNE}
3191};
3192
3193static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = {
3194 {0x00FB, TX_PSC_A0},
3195 {0x04AA, TX_PSC_A2},
3196 {0x04AA, TX_PSC_A3},
3197 {0x000F, XCVR_DIAG_BIDI_CTRL}
3198};
3199
3200static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = {
3201 {0x0000, RX_PSC_A0},
3202 {0x0000, RX_PSC_A2},
3203 {0x0000, RX_PSC_A3},
3204 {0x0000, RX_PSC_CAL},
3205 {0x0000, RX_REE_GCSM1_CTRL},
3206 {0x0000, RX_REE_GCSM2_CTRL},
3207 {0x0000, RX_REE_PERGCSM_CTRL}
3208};
3209
3210static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = {
3211 .reg_pairs = dp_100_no_ssc_cmn_regs,
3212 .num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs),
3213};
3214
3215static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = {
3216 .reg_pairs = dp_100_no_ssc_tx_ln_regs,
3217 .num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs),
3218};
3219
3220static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = {
3221 .reg_pairs = dp_100_no_ssc_rx_ln_regs,
3222 .num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs),
3223};
3224
3225/* Single DisplayPort(DP) link configuration */
3226static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
3227 {0x0000, PHY_PLL_CFG},
3228};
3229
3230static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
3231 {0x0000, XCVR_DIAG_HSCLK_SEL},
3232 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
3233};
3234
3235static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
3236 .reg_pairs = sl_dp_link_cmn_regs,
3237 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
3238};
3239
3240static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
3241 .reg_pairs = sl_dp_xcvr_diag_ln_regs,
3242 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
3243};
3244
3245/* Single DP, 19.2 MHz Ref clk, no SSC */
3246static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
3247 {0x0014, CMN_SSM_BIAS_TMR},
3248 {0x0027, CMN_PLLSM0_PLLPRE_TMR},
3249 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
3250 {0x0027, CMN_PLLSM1_PLLPRE_TMR},
3251 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
3252 {0x0060, CMN_BGCAL_INIT_TMR},
3253 {0x0060, CMN_BGCAL_ITER_TMR},
3254 {0x0014, CMN_IBCAL_INIT_TMR},
3255 {0x0018, CMN_TXPUCAL_INIT_TMR},
3256 {0x0005, CMN_TXPUCAL_ITER_TMR},
3257 {0x0018, CMN_TXPDCAL_INIT_TMR},
3258 {0x0005, CMN_TXPDCAL_ITER_TMR},
3259 {0x0240, CMN_RXCAL_INIT_TMR},
3260 {0x0005, CMN_RXCAL_ITER_TMR},
3261 {0x0002, CMN_SD_CAL_INIT_TMR},
3262 {0x0002, CMN_SD_CAL_ITER_TMR},
3263 {0x000B, CMN_SD_CAL_REFTIM_START},
3264 {0x0137, CMN_SD_CAL_PLLCNT_START},
3265 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3266 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3267 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3268 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3269 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3270 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3271 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3272 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3273 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
3274 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
3275 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
3276 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
3277 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
3278 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3279 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
3280 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3281};
3282
3283static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
3284 {0x0780, TX_RCVDET_ST_TMR},
3285 {0x00FB, TX_PSC_A0},
3286 {0x04AA, TX_PSC_A2},
3287 {0x04AA, TX_PSC_A3},
3288 {0x000F, XCVR_DIAG_BIDI_CTRL}
3289};
3290
3291static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
3292 {0x0000, RX_PSC_A0},
3293 {0x0000, RX_PSC_A2},
3294 {0x0000, RX_PSC_A3},
3295 {0x0000, RX_PSC_CAL},
3296 {0x0000, RX_REE_GCSM1_CTRL},
3297 {0x0000, RX_REE_GCSM2_CTRL},
3298 {0x0000, RX_REE_PERGCSM_CTRL}
3299};
3300
3301static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
3302 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
3303 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
3304};
3305
3306static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
3307 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
3308 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
3309};
3310
3311static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
3312 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
3313 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
3314};
3315
3316/* Single DP, 25 MHz Ref clk, no SSC */
3317static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
3318 {0x0019, CMN_SSM_BIAS_TMR},
3319 {0x0032, CMN_PLLSM0_PLLPRE_TMR},
3320 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
3321 {0x0032, CMN_PLLSM1_PLLPRE_TMR},
3322 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
3323 {0x007D, CMN_BGCAL_INIT_TMR},
3324 {0x007D, CMN_BGCAL_ITER_TMR},
3325 {0x0019, CMN_IBCAL_INIT_TMR},
3326 {0x001E, CMN_TXPUCAL_INIT_TMR},
3327 {0x0006, CMN_TXPUCAL_ITER_TMR},
3328 {0x001E, CMN_TXPDCAL_INIT_TMR},
3329 {0x0006, CMN_TXPDCAL_ITER_TMR},
3330 {0x02EE, CMN_RXCAL_INIT_TMR},
3331 {0x0006, CMN_RXCAL_ITER_TMR},
3332 {0x0002, CMN_SD_CAL_INIT_TMR},
3333 {0x0002, CMN_SD_CAL_ITER_TMR},
3334 {0x000E, CMN_SD_CAL_REFTIM_START},
3335 {0x012B, CMN_SD_CAL_PLLCNT_START},
3336 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3337 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3338 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3339 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3340 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3341 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3342 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3343 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3344 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
3345 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
3346 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
3347 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
3348 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
3349 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3350 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
3351 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3352};
3353
3354static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
3355 {0x09C4, TX_RCVDET_ST_TMR},
3356 {0x00FB, TX_PSC_A0},
3357 {0x04AA, TX_PSC_A2},
3358 {0x04AA, TX_PSC_A3},
3359 {0x000F, XCVR_DIAG_BIDI_CTRL}
3360};
3361
3362static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
3363 {0x0000, RX_PSC_A0},
3364 {0x0000, RX_PSC_A2},
3365 {0x0000, RX_PSC_A3},
3366 {0x0000, RX_PSC_CAL},
3367 {0x0000, RX_REE_GCSM1_CTRL},
3368 {0x0000, RX_REE_GCSM2_CTRL},
3369 {0x0000, RX_REE_PERGCSM_CTRL}
3370};
3371
3372static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
3373 .reg_pairs = sl_dp_25_no_ssc_cmn_regs,
3374 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
3375};
3376
3377static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
3378 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
3379 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
3380};
3381
3382static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
3383 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
3384 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
3385};
3386
3387/* Single DP, 100 MHz Ref clk, no SSC */
3388static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
3389 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3390 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3391};
3392
3393static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
3394 {0x00FB, TX_PSC_A0},
3395 {0x04AA, TX_PSC_A2},
3396 {0x04AA, TX_PSC_A3},
3397 {0x000F, XCVR_DIAG_BIDI_CTRL}
3398};
3399
3400static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
3401 {0x0000, RX_PSC_A0},
3402 {0x0000, RX_PSC_A2},
3403 {0x0000, RX_PSC_A3},
3404 {0x0000, RX_PSC_CAL},
3405 {0x0000, RX_REE_GCSM1_CTRL},
3406 {0x0000, RX_REE_GCSM2_CTRL},
3407 {0x0000, RX_REE_PERGCSM_CTRL}
3408};
3409
3410static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
3411 .reg_pairs = sl_dp_100_no_ssc_cmn_regs,
3412 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
3413};
3414
3415static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
3416 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
3417 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
3418};
3419
3420static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
3421 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
3422 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
3423};
3424
3425/* USB and SGMII/QSGMII link configuration */
3426static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
3427 {0x0002, PHY_PLL_CFG},
3428 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
3429 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3430};
3431
3432static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
3433 {0x0000, XCVR_DIAG_HSCLK_SEL},
3434 {0x0001, XCVR_DIAG_HSCLK_DIV},
3435 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3436};
3437
3438static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
3439 {0x0011, XCVR_DIAG_HSCLK_SEL},
3440 {0x0003, XCVR_DIAG_HSCLK_DIV},
3441 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3442};
3443
3444static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
3445 .reg_pairs = usb_sgmii_link_cmn_regs,
3446 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
3447};
3448
3449static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
3450 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
3451 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
3452};
3453
3454static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
3455 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
3456 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
3457};
3458
3459/* PCIe and USB Unique SSC link configuration */
3460static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
3461 {0x0003, PHY_PLL_CFG},
3462 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3463 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3464 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
3465};
3466
3467static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
3468 {0x0000, XCVR_DIAG_HSCLK_SEL},
3469 {0x0001, XCVR_DIAG_HSCLK_DIV},
3470 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3471};
3472
3473static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
3474 {0x0011, XCVR_DIAG_HSCLK_SEL},
3475 {0x0001, XCVR_DIAG_HSCLK_DIV},
3476 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
3477};
3478
3479static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
3480 .reg_pairs = pcie_usb_link_cmn_regs,
3481 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
3482};
3483
3484static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
3485 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
3486 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
3487};
3488
3489static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
3490 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
3491 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
3492};
3493
3494/* USB 100 MHz Ref clk, internal SSC */
3495static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
3496 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3497 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3498 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3499 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3500 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3501 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3502 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3503 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3504 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3505 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3506 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3507 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3508 {0x0064, CMN_PLL0_INTDIV_M0},
3509 {0x0050, CMN_PLL0_INTDIV_M1},
3510 {0x0064, CMN_PLL1_INTDIV_M0},
3511 {0x0002, CMN_PLL0_FRACDIVH_M0},
3512 {0x0002, CMN_PLL0_FRACDIVH_M1},
3513 {0x0002, CMN_PLL1_FRACDIVH_M0},
3514 {0x0044, CMN_PLL0_HIGH_THR_M0},
3515 {0x0036, CMN_PLL0_HIGH_THR_M1},
3516 {0x0044, CMN_PLL1_HIGH_THR_M0},
3517 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3518 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3519 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3520 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3521 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3522 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3523 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3524 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3525 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3526 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3527 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3528 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3529 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3530 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3531 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3532 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3533 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3534 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3535 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3536 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3537 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3538 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3539 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3540 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3541 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3542 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3543 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3544 {0x007F, CMN_TXPUCAL_TUNE},
3545 {0x007F, CMN_TXPDCAL_TUNE}
3546};
3547
3548static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
3549 .reg_pairs = usb_100_int_ssc_cmn_regs,
3550 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
3551};
3552
3553/* Single USB link configuration */
3554static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
3555 {0x0000, PHY_PLL_CFG},
3556 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3557};
3558
3559static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
3560 {0x0000, XCVR_DIAG_HSCLK_SEL},
3561 {0x0001, XCVR_DIAG_HSCLK_DIV},
3562 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3563};
3564
3565static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
3566 .reg_pairs = sl_usb_link_cmn_regs,
3567 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
3568};
3569
3570static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
3571 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
3572 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
3573};
3574
3575/* USB PHY PCS common configuration */
3576static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
3577 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
3578 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
3579 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
3580};
3581
3582static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
3583 .reg_pairs = usb_phy_pcs_cmn_regs,
3584 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
3585};
3586
3587/* USB 100 MHz Ref clk, no SSC */
3588static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
3589 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3590 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3591 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3592 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3593 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3594 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3595 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3596};
3597
3598static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
3599 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
3600 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
3601};
3602
3603static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
3604 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3605 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3606 {0x007F, CMN_TXPUCAL_TUNE},
3607 {0x007F, CMN_TXPDCAL_TUNE}
3608};
3609
3610static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
3611 {0x02FF, TX_PSC_A0},
3612 {0x06AF, TX_PSC_A1},
3613 {0x06AE, TX_PSC_A2},
3614 {0x06AE, TX_PSC_A3},
3615 {0x2A82, TX_TXCC_CTRL},
3616 {0x0014, TX_TXCC_CPOST_MULT_01},
3617 {0x0003, XCVR_DIAG_PSC_OVRD}
3618};
3619
3620static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
3621 {0x0D1D, RX_PSC_A0},
3622 {0x0D1D, RX_PSC_A1},
3623 {0x0D00, RX_PSC_A2},
3624 {0x0500, RX_PSC_A3},
3625 {0x0013, RX_SIGDET_HL_FILT_TMR},
3626 {0x0000, RX_REE_GCSM1_CTRL},
3627 {0x0C02, RX_REE_ATTEN_THR},
3628 {0x0330, RX_REE_SMGM_CTRL1},
3629 {0x0300, RX_REE_SMGM_CTRL2},
3630 {0x0019, RX_REE_TAP1_CLIP},
3631 {0x0019, RX_REE_TAP2TON_CLIP},
3632 {0x1004, RX_DIAG_SIGDET_TUNE},
3633 {0x00F9, RX_DIAG_NQST_CTRL},
3634 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3635 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3636 {0x0000, RX_DIAG_PI_CAP},
3637 {0x0031, RX_DIAG_PI_RATE},
3638 {0x0001, RX_DIAG_ACYA},
3639 {0x018C, RX_CDRLF_CNFG},
3640 {0x0003, RX_CDRLF_CNFG3}
3641};
3642
3643static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
3644 .reg_pairs = usb_100_no_ssc_cmn_regs,
3645 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
3646};
3647
3648static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
3649 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
3650 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
3651};
3652
3653static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
3654 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
3655 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
3656};
3657
3658/* Single link USB, 100 MHz Ref clk, internal SSC */
3659static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
3660 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3661 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3662 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3663 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3664 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3665 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3666 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3667 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3668 {0x0064, CMN_PLL0_INTDIV_M0},
3669 {0x0064, CMN_PLL1_INTDIV_M0},
3670 {0x0002, CMN_PLL0_FRACDIVH_M0},
3671 {0x0002, CMN_PLL1_FRACDIVH_M0},
3672 {0x0044, CMN_PLL0_HIGH_THR_M0},
3673 {0x0044, CMN_PLL1_HIGH_THR_M0},
3674 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3675 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3676 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3677 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3678 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3679 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3680 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3681 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3682 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3683 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3684 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3685 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3686 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3687 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3688 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3689 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3690 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3691 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3692 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3693 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3694 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3695 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3696 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3697 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3698};
3699
3700static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
3701 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
3702 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
3703};
3704
3705/* PCIe and SGMII/QSGMII Unique SSC link configuration */
3706static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
3707 {0x0003, PHY_PLL_CFG},
3708 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3709 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3710 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3711};
3712
3713static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
3714 {0x0000, XCVR_DIAG_HSCLK_SEL},
3715 {0x0001, XCVR_DIAG_HSCLK_DIV},
3716 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3717};
3718
3719static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
3720 {0x0011, XCVR_DIAG_HSCLK_SEL},
3721 {0x0003, XCVR_DIAG_HSCLK_DIV},
3722 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3723};
3724
3725static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
3726 .reg_pairs = pcie_sgmii_link_cmn_regs,
3727 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
3728};
3729
3730static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
3731 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
3732 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
3733};
3734
3735static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
3736 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
3737 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
3738};
3739
3740/* SGMII 100 MHz Ref clk, no SSC */
3741static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
3742 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3743 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3744 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3745 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3746 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3747};
3748
3749static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
3750 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
3751 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
3752};
3753
3754static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
3755 {0x007F, CMN_TXPUCAL_TUNE},
3756 {0x007F, CMN_TXPDCAL_TUNE}
3757};
3758
3759static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
3760 {0x00F3, TX_PSC_A0},
3761 {0x04A2, TX_PSC_A2},
3762 {0x04A2, TX_PSC_A3},
3763 {0x0000, TX_TXCC_CPOST_MULT_00},
3764 {0x00B3, DRV_DIAG_TX_DRV}
3765};
3766
3767static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
3768 {0x00F3, TX_PSC_A0},
3769 {0x04A2, TX_PSC_A2},
3770 {0x04A2, TX_PSC_A3},
3771 {0x0000, TX_TXCC_CPOST_MULT_00},
3772 {0x00B3, DRV_DIAG_TX_DRV},
3773 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3774};
3775
3776static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
3777 {0x091D, RX_PSC_A0},
3778 {0x0900, RX_PSC_A2},
3779 {0x0100, RX_PSC_A3},
3780 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3781 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3782 {0x0000, RX_DIAG_DFE_CTRL},
3783 {0x0019, RX_REE_TAP1_CLIP},
3784 {0x0019, RX_REE_TAP2TON_CLIP},
3785 {0x0098, RX_DIAG_NQST_CTRL},
3786 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3787 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3788 {0x0000, RX_DIAG_PI_CAP},
3789 {0x0010, RX_DIAG_PI_RATE},
3790 {0x0001, RX_DIAG_ACYA},
3791 {0x018C, RX_CDRLF_CNFG},
3792};
3793
3794static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
3795 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
3796 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
3797};
3798
3799static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
3800 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
3801 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
3802};
3803
3804static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
3805 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
3806 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
3807};
3808
3809static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
3810 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
3811 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
3812};
3813
3814/* SGMII 100 MHz Ref clk, internal SSC */
3815static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
3816 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3817 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3818 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3819 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3820 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3821 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3822 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3823 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3824 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3825 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3826 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3827 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3828 {0x0064, CMN_PLL0_INTDIV_M0},
3829 {0x0050, CMN_PLL0_INTDIV_M1},
3830 {0x0064, CMN_PLL1_INTDIV_M0},
3831 {0x0002, CMN_PLL0_FRACDIVH_M0},
3832 {0x0002, CMN_PLL0_FRACDIVH_M1},
3833 {0x0002, CMN_PLL1_FRACDIVH_M0},
3834 {0x0044, CMN_PLL0_HIGH_THR_M0},
3835 {0x0036, CMN_PLL0_HIGH_THR_M1},
3836 {0x0044, CMN_PLL1_HIGH_THR_M0},
3837 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3838 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3839 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3840 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3841 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3842 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3843 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3844 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3845 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3846 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3847 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3848 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3849 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3850 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3851 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3852 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3853 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3854 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3855 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3856 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3857 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3858 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3859 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3860 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3861 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3862 {0x007F, CMN_TXPUCAL_TUNE},
3863 {0x007F, CMN_TXPDCAL_TUNE}
3864};
3865
3866static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
3867 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
3868 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
3869};
3870
3871/* QSGMII 100 MHz Ref clk, no SSC */
3872static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
3873 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3874 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3875 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3876 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3877 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3878};
3879
3880static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
3881 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
3882 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
3883};
3884
3885static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
3886 {0x007F, CMN_TXPUCAL_TUNE},
3887 {0x007F, CMN_TXPDCAL_TUNE}
3888};
3889
3890static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
3891 {0x00F3, TX_PSC_A0},
3892 {0x04A2, TX_PSC_A2},
3893 {0x04A2, TX_PSC_A3},
3894 {0x0000, TX_TXCC_CPOST_MULT_00},
3895 {0x0011, TX_TXCC_MGNFS_MULT_100},
3896 {0x0003, DRV_DIAG_TX_DRV}
3897};
3898
3899static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
3900 {0x00F3, TX_PSC_A0},
3901 {0x04A2, TX_PSC_A2},
3902 {0x04A2, TX_PSC_A3},
3903 {0x0000, TX_TXCC_CPOST_MULT_00},
3904 {0x0011, TX_TXCC_MGNFS_MULT_100},
3905 {0x0003, DRV_DIAG_TX_DRV},
3906 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3907};
3908
3909static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
3910 {0x091D, RX_PSC_A0},
3911 {0x0900, RX_PSC_A2},
3912 {0x0100, RX_PSC_A3},
3913 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3914 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3915 {0x0000, RX_DIAG_DFE_CTRL},
3916 {0x0019, RX_REE_TAP1_CLIP},
3917 {0x0019, RX_REE_TAP2TON_CLIP},
3918 {0x0098, RX_DIAG_NQST_CTRL},
3919 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3920 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3921 {0x0000, RX_DIAG_PI_CAP},
3922 {0x0010, RX_DIAG_PI_RATE},
3923 {0x0001, RX_DIAG_ACYA},
3924 {0x018C, RX_CDRLF_CNFG},
3925};
3926
3927static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
3928 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
3929 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
3930};
3931
3932static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
3933 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
3934 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
3935};
3936
3937static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
3938 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
3939 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
3940};
3941
3942static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
3943 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
3944 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3945};
3946
3947/* QSGMII 100 MHz Ref clk, internal SSC */
3948static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
3949 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3950 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3951 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3952 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3953 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3954 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3955 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3956 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3957 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3958 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3959 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3960 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3961 {0x0064, CMN_PLL0_INTDIV_M0},
3962 {0x0050, CMN_PLL0_INTDIV_M1},
3963 {0x0064, CMN_PLL1_INTDIV_M0},
3964 {0x0002, CMN_PLL0_FRACDIVH_M0},
3965 {0x0002, CMN_PLL0_FRACDIVH_M1},
3966 {0x0002, CMN_PLL1_FRACDIVH_M0},
3967 {0x0044, CMN_PLL0_HIGH_THR_M0},
3968 {0x0036, CMN_PLL0_HIGH_THR_M1},
3969 {0x0044, CMN_PLL1_HIGH_THR_M0},
3970 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3971 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3972 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3973 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3974 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3975 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3976 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3977 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3978 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3979 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3980 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3981 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3982 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3983 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3984 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3985 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3986 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3987 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3988 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3989 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3990 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3991 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3992 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3993 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3994 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3995 {0x007F, CMN_TXPUCAL_TUNE},
3996 {0x007F, CMN_TXPDCAL_TUNE}
3997};
3998
3999static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
4000 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
4001 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
4002};
4003
4004/* Single SGMII/QSGMII link configuration */
4005static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
4006 {0x0000, PHY_PLL_CFG},
4007 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
4008};
4009
4010static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
4011 {0x0000, XCVR_DIAG_HSCLK_SEL},
4012 {0x0003, XCVR_DIAG_HSCLK_DIV},
4013 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
4014};
4015
4016static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
4017 .reg_pairs = sl_sgmii_link_cmn_regs,
4018 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
4019};
4020
4021static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
4022 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
4023 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
4024};
4025
4026/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
4027static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
4028 {0x0004, CMN_PLL0_DSM_DIAG_M0},
4029 {0x0004, CMN_PLL0_DSM_DIAG_M1},
4030 {0x0004, CMN_PLL1_DSM_DIAG_M0},
4031 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
4032 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
4033 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
4034 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
4035 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
4036 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
4037 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
4038 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
4039 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
4040 {0x0064, CMN_PLL0_INTDIV_M0},
4041 {0x0050, CMN_PLL0_INTDIV_M1},
4042 {0x0064, CMN_PLL1_INTDIV_M0},
4043 {0x0002, CMN_PLL0_FRACDIVH_M0},
4044 {0x0002, CMN_PLL0_FRACDIVH_M1},
4045 {0x0002, CMN_PLL1_FRACDIVH_M0},
4046 {0x0044, CMN_PLL0_HIGH_THR_M0},
4047 {0x0036, CMN_PLL0_HIGH_THR_M1},
4048 {0x0044, CMN_PLL1_HIGH_THR_M0},
4049 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
4050 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
4051 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
4052 {0x0001, CMN_PLL0_SS_CTRL1_M0},
4053 {0x0001, CMN_PLL0_SS_CTRL1_M1},
4054 {0x0001, CMN_PLL1_SS_CTRL1_M0},
4055 {0x011B, CMN_PLL0_SS_CTRL2_M0},
4056 {0x011B, CMN_PLL0_SS_CTRL2_M1},
4057 {0x011B, CMN_PLL1_SS_CTRL2_M0},
4058 {0x006E, CMN_PLL0_SS_CTRL3_M0},
4059 {0x0058, CMN_PLL0_SS_CTRL3_M1},
4060 {0x006E, CMN_PLL1_SS_CTRL3_M0},
4061 {0x000E, CMN_PLL0_SS_CTRL4_M0},
4062 {0x0012, CMN_PLL0_SS_CTRL4_M1},
4063 {0x000E, CMN_PLL1_SS_CTRL4_M0},
4064 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
4065 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
4066 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
4067 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
4068 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
4069 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
4070 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
4071 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
4072 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
4073 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
4074};
4075
4076static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
4077 .reg_pairs = pcie_100_int_ssc_cmn_regs,
4078 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
4079};
4080
4081/* Single link PCIe, 100 MHz Ref clk, internal SSC */
4082static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
4083 {0x0004, CMN_PLL0_DSM_DIAG_M0},
4084 {0x0004, CMN_PLL0_DSM_DIAG_M1},
4085 {0x0004, CMN_PLL1_DSM_DIAG_M0},
4086 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
4087 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
4088 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
4089 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
4090 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
4091 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
4092 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
4093 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
4094 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
4095 {0x0064, CMN_PLL0_INTDIV_M0},
4096 {0x0050, CMN_PLL0_INTDIV_M1},
4097 {0x0050, CMN_PLL1_INTDIV_M0},
4098 {0x0002, CMN_PLL0_FRACDIVH_M0},
4099 {0x0002, CMN_PLL0_FRACDIVH_M1},
4100 {0x0002, CMN_PLL1_FRACDIVH_M0},
4101 {0x0044, CMN_PLL0_HIGH_THR_M0},
4102 {0x0036, CMN_PLL0_HIGH_THR_M1},
4103 {0x0036, CMN_PLL1_HIGH_THR_M0},
4104 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
4105 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
4106 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
4107 {0x0001, CMN_PLL0_SS_CTRL1_M0},
4108 {0x0001, CMN_PLL0_SS_CTRL1_M1},
4109 {0x0001, CMN_PLL1_SS_CTRL1_M0},
4110 {0x011B, CMN_PLL0_SS_CTRL2_M0},
4111 {0x011B, CMN_PLL0_SS_CTRL2_M1},
4112 {0x011B, CMN_PLL1_SS_CTRL2_M0},
4113 {0x006E, CMN_PLL0_SS_CTRL3_M0},
4114 {0x0058, CMN_PLL0_SS_CTRL3_M1},
4115 {0x0058, CMN_PLL1_SS_CTRL3_M0},
4116 {0x000E, CMN_PLL0_SS_CTRL4_M0},
4117 {0x0012, CMN_PLL0_SS_CTRL4_M1},
4118 {0x0012, CMN_PLL1_SS_CTRL4_M0},
4119 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
4120 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
4121 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
4122 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
4123 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
4124 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
4125 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
4126 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
4127 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
4128 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
4129};
4130
4131static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
4132 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
4133 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
4134};
4135
4136/* PCIe, 100 MHz Ref clk, no SSC & external SSC */
4137static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
4138 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
4139 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
4140 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
4141};
4142
4143static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
4144 {0x0019, RX_REE_TAP1_CLIP},
4145 {0x0019, RX_REE_TAP2TON_CLIP},
4146 {0x0001, RX_DIAG_ACYA}
4147};
4148
4149static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
4150 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
4151 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
4152};
4153
4154static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
4155 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
4156 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
4157};
4158
4159static struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
4160 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_link_cmn_vals},
4161 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &pcie_dp_link_cmn_vals},
4162 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
4163
4164 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4165 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
4166 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
4167 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
4168 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
4169
4170 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4171 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
4172 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},
4173
4174 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4175 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
4176 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},
4177
4178 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals},
4179 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals},
4180 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals},
4181 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals},
4182 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},
4183
4184 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals},
4185};
4186
4187static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
4188 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_xcvr_diag_ln_vals},
4189 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &dp_pcie_xcvr_diag_ln_vals},
4190 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
4191
4192 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4193 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4194 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4195 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
4196 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
4197
4198 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4199 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
4200 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},
4201
4202 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4203 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
4204 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},
4205
4206 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals},
4207 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals},
4208 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals},
4209 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals},
4210 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},
4211
4212 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals},
4213};
4214
4215static struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
4216 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals},
4217 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals},
4218 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals},
4219 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals},
4220 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals},
4221};
4222
4223static struct cdns_torrent_vals_entry cmn_vals_entries[] = {
4224 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals},
4225 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals},
4226
4227 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4228 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals},
4229 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4230
4231 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4232 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4233 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
4234
4235 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4236 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4237 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4238
4239 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4240 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4241 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4242
4243 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4244 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4245 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4246
4247 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4248
4249 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
4250
4251 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
4252 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4253 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals},
4254
4255 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
4256 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4257 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4258
4259 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},
4260
4261 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
4262 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4263 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals},
4264
4265 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
4266 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4267 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4268
4269 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4270 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4271 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4272
4273 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},
4274 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
4275 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
4276
4277 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4278 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4279 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4280
4281 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4282 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4283 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4284
4285 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
4286
4287 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
4288};
4289
4290static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
4291 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},
4292 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},
4293
4294 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},
4295 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4296 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4297
4298 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4299 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4300 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
4301
4302 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
4303 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
4304 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
4305
4306 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},
4307 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},
4308 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},
4309
4310 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},
4311 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},
4312 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
4313
4314 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4315
4316 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4317
4318 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4319 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4320 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4321
4322 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4323 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4324 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4325
4326 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4327
4328 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4329 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4330 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4331
4332 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4333 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4334 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4335
4336 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4337 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4338 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4339
4340 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4341 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4342 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4343
4344 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4345 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4346 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4347
4348 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4349 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4350 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4351
4352 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4353
4354 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4355};
4356
4357static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
4358 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals},
4359 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals},
4360
4361 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals},
4362 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
4363 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
4364
4365 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4366 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4367 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4368
4369 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4370 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4371 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4372
4373 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4374 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4375 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4376
4377 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4378 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4379 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4380
4381 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4382
4383 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4384
4385 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4386 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4387 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4388
4389 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4390 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4391 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4392
4393 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4394
4395 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4396 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4397 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4398
4399 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4400 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4401 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4402
4403 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4404 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4405 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4406
4407 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4408 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4409 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4410
4411 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4412 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4413 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4414
4415 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4416 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4417 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4418
4419 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4420
4421 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4422};
4423
4424static const struct cdns_torrent_data cdns_map_torrent = {
4425 .block_offset_shift = 0x2,
4426 .reg_offset_shift = 0x2,
4427 .link_cmn_vals_tbl = {
4428 .entries = link_cmn_vals_entries,
4429 .num_entries = ARRAY_SIZE(link_cmn_vals_entries),
4430 },
4431 .xcvr_diag_vals_tbl = {
4432 .entries = xcvr_diag_vals_entries,
4433 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),
4434 },
4435 .pcs_cmn_vals_tbl = {
4436 .entries = pcs_cmn_vals_entries,
4437 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),
4438 },
4439 .cmn_vals_tbl = {
4440 .entries = cmn_vals_entries,
4441 .num_entries = ARRAY_SIZE(cmn_vals_entries),
4442 },
4443 .tx_ln_vals_tbl = {
4444 .entries = cdns_tx_ln_vals_entries,
4445 .num_entries = ARRAY_SIZE(cdns_tx_ln_vals_entries),
4446 },
4447 .rx_ln_vals_tbl = {
4448 .entries = cdns_rx_ln_vals_entries,
4449 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries),
4450 },
4451};
4452
4453static struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = {
4454 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals},
4455};
4456
4457static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
4458 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},
4459 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},
4460
4461 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},
4462 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4463 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4464
4465 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4466 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4467 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
4468
4469 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
4470 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
4471 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
4472
4473 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},
4474 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},
4475 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},
4476
4477 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},
4478 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},
4479 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
4480
4481 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4482
4483 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4484
4485 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4486 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4487 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4488
4489 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4490 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4491 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4492
4493 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4494
4495 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4496 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4497 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4498
4499 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4500 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4501 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4502
4503 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4504 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4505 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4506
4507 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4508 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4509 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4510
4511 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4512 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4513 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4514
4515 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4516 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4517 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4518
4519 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4520
4521 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4522};
4523
4524static const struct cdns_torrent_data ti_j721e_map_torrent = {
4525 .block_offset_shift = 0x0,
4526 .reg_offset_shift = 0x1,
4527 .link_cmn_vals_tbl = {
4528 .entries = link_cmn_vals_entries,
4529 .num_entries = ARRAY_SIZE(link_cmn_vals_entries),
4530 },
4531 .xcvr_diag_vals_tbl = {
4532 .entries = xcvr_diag_vals_entries,
4533 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),
4534 },
4535 .pcs_cmn_vals_tbl = {
4536 .entries = pcs_cmn_vals_entries,
4537 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),
4538 },
4539 .phy_pma_cmn_vals_tbl = {
4540 .entries = j721e_phy_pma_cmn_vals_entries,
4541 .num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries),
4542 },
4543 .cmn_vals_tbl = {
4544 .entries = cmn_vals_entries,
4545 .num_entries = ARRAY_SIZE(cmn_vals_entries),
4546 },
4547 .tx_ln_vals_tbl = {
4548 .entries = ti_tx_ln_vals_entries,
4549 .num_entries = ARRAY_SIZE(ti_tx_ln_vals_entries),
4550 },
4551 .rx_ln_vals_tbl = {
4552 .entries = cdns_rx_ln_vals_entries,
4553 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries),
4554 },
4555};
4556
4557static const struct of_device_id cdns_torrent_phy_of_match[] = {
4558 {
4559 .compatible = "cdns,torrent-phy",
4560 .data = &cdns_map_torrent,
4561 },
4562 {
4563 .compatible = "ti,j721e-serdes-10g",
4564 .data = &ti_j721e_map_torrent,
4565 },
4566 {}
4567};
4568MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
4569
4570static struct platform_driver cdns_torrent_phy_driver = {
4571 .probe = cdns_torrent_phy_probe,
4572 .remove_new = cdns_torrent_phy_remove,
4573 .driver = {
4574 .name = "cdns-torrent-phy",
4575 .of_match_table = cdns_torrent_phy_of_match,
4576 }
4577};
4578module_platform_driver(cdns_torrent_phy_driver);
4579
4580MODULE_AUTHOR("Cadence Design Systems, Inc.");
4581MODULE_DESCRIPTION("Cadence Torrent PHY driver");
4582MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence Torrent SD0801 PHY driver.
4 *
5 * Copyright 2018 Cadence Design Systems, Inc.
6 *
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/phy/phy.h>
21#include <linux/platform_device.h>
22#include <linux/reset.h>
23#include <linux/regmap.h>
24
25#define REF_CLK_19_2MHz 19200000
26#define REF_CLK_25MHz 25000000
27
28#define DEFAULT_NUM_LANES 4
29#define MAX_NUM_LANES 4
30#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
31
32#define POLL_TIMEOUT_US 5000
33
34#define TORRENT_COMMON_CDB_OFFSET 0x0
35
36#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
37 ((0x4000 << (block_offset)) + \
38 (((ln) << 9) << (reg_offset)))
39
40#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
41 ((0x8000 << (block_offset)) + \
42 (((ln) << 9) << (reg_offset)))
43
44#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
45 (0xC000 << (block_offset))
46
47#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
48 (0xE000 << (block_offset))
49
50#define TORRENT_DPTX_PHY_OFFSET 0x0
51
52/*
53 * register offsets from DPTX PHY register block base (i.e MHDP
54 * register base + 0x30a00)
55 */
56#define PHY_AUX_CTRL 0x04
57#define PHY_RESET 0x20
58#define PMA_TX_ELEC_IDLE_MASK 0xF0U
59#define PMA_TX_ELEC_IDLE_SHIFT 4
60#define PHY_L00_RESET_N_MASK 0x01U
61#define PHY_PMA_XCVR_PLLCLK_EN 0x24
62#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
63#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
64#define PHY_POWER_STATE_LN_0 0x0000
65#define PHY_POWER_STATE_LN_1 0x0008
66#define PHY_POWER_STATE_LN_2 0x0010
67#define PHY_POWER_STATE_LN_3 0x0018
68#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
69#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
70#define PHY_PMA_CMN_READY 0x34
71
72/*
73 * register offsets from SD0801 PHY register block base (i.e MHDP
74 * register base + 0x500000)
75 */
76#define CMN_SSM_BANDGAP_TMR 0x0021U
77#define CMN_SSM_BIAS_TMR 0x0022U
78#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
79#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
80#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
81#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
82#define CMN_BGCAL_INIT_TMR 0x0064U
83#define CMN_BGCAL_ITER_TMR 0x0065U
84#define CMN_IBCAL_INIT_TMR 0x0074U
85#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
86#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
87#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
88#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
89#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
90#define CMN_PLL0_INTDIV_M0 0x0090U
91#define CMN_PLL0_FRACDIVL_M0 0x0091U
92#define CMN_PLL0_FRACDIVH_M0 0x0092U
93#define CMN_PLL0_HIGH_THR_M0 0x0093U
94#define CMN_PLL0_DSM_DIAG_M0 0x0094U
95#define CMN_PLL0_SS_CTRL1_M0 0x0098U
96#define CMN_PLL0_SS_CTRL2_M0 0x0099U
97#define CMN_PLL0_SS_CTRL3_M0 0x009AU
98#define CMN_PLL0_SS_CTRL4_M0 0x009BU
99#define CMN_PLL0_LOCK_REFCNT_START 0x009CU
100#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
101#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
102#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
103#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
104#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
105#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
106#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
107#define CMN_PLL1_INTDIV_M0 0x00D0U
108#define CMN_PLL1_FRACDIVL_M0 0x00D1U
109#define CMN_PLL1_FRACDIVH_M0 0x00D2U
110#define CMN_PLL1_HIGH_THR_M0 0x00D3U
111#define CMN_PLL1_DSM_DIAG_M0 0x00D4U
112#define CMN_PLL1_SS_CTRL1_M0 0x00D8U
113#define CMN_PLL1_SS_CTRL2_M0 0x00D9U
114#define CMN_PLL1_SS_CTRL3_M0 0x00DAU
115#define CMN_PLL1_SS_CTRL4_M0 0x00DBU
116#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
117#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
118#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
119#define CMN_TXPUCAL_INIT_TMR 0x0104U
120#define CMN_TXPUCAL_ITER_TMR 0x0105U
121#define CMN_TXPDCAL_INIT_TMR 0x010CU
122#define CMN_TXPDCAL_ITER_TMR 0x010DU
123#define CMN_RXCAL_INIT_TMR 0x0114U
124#define CMN_RXCAL_ITER_TMR 0x0115U
125#define CMN_SD_CAL_INIT_TMR 0x0124U
126#define CMN_SD_CAL_ITER_TMR 0x0125U
127#define CMN_SD_CAL_REFTIM_START 0x0126U
128#define CMN_SD_CAL_PLLCNT_START 0x0128U
129#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
130#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
131#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
132#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
133#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
134#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
135#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
136#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
137#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
138#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
139#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
140#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
141
142/* PMA TX Lane registers */
143#define TX_TXCC_CTRL 0x0040U
144#define TX_TXCC_CPOST_MULT_00 0x004CU
145#define TX_TXCC_MGNFS_MULT_000 0x0050U
146#define DRV_DIAG_TX_DRV 0x00C6U
147#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
148#define XCVR_DIAG_HSCLK_SEL 0x00E6U
149#define XCVR_DIAG_HSCLK_DIV 0x00E7U
150#define XCVR_DIAG_BIDI_CTRL 0x00EAU
151#define TX_PSC_A0 0x0100U
152#define TX_PSC_A2 0x0102U
153#define TX_PSC_A3 0x0103U
154#define TX_RCVDET_ST_TMR 0x0123U
155#define TX_DIAG_ACYA 0x01E7U
156#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
157
158/* PMA RX Lane registers */
159#define RX_PSC_A0 0x0000U
160#define RX_PSC_A2 0x0002U
161#define RX_PSC_A3 0x0003U
162#define RX_PSC_CAL 0x0006U
163#define RX_REE_GCSM1_CTRL 0x0108U
164#define RX_REE_GCSM2_CTRL 0x0110U
165#define RX_REE_PERGCSM_CTRL 0x0118U
166
167/* PHY PCS common registers */
168#define PHY_PLL_CFG 0x000EU
169
170/* PHY PMA common registers */
171#define PHY_PMA_CMN_CTRL2 0x0001U
172#define PHY_PMA_PLL_RAW_CTRL 0x0003U
173
174static const struct reg_field phy_pll_cfg =
175 REG_FIELD(PHY_PLL_CFG, 0, 1);
176
177static const struct reg_field phy_pma_cmn_ctrl_2 =
178 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
179
180static const struct reg_field phy_pma_pll_raw_ctrl =
181 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
182
183static const struct reg_field phy_reset_ctrl =
184 REG_FIELD(PHY_RESET, 8, 8);
185
186static const struct of_device_id cdns_torrent_phy_of_match[];
187
188struct cdns_torrent_inst {
189 struct phy *phy;
190 u32 mlane;
191 u32 phy_type;
192 u32 num_lanes;
193 struct reset_control *lnk_rst;
194};
195
196struct cdns_torrent_phy {
197 void __iomem *base; /* DPTX registers base */
198 void __iomem *sd_base; /* SD0801 registers base */
199 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
200 struct reset_control *phy_rst;
201 struct device *dev;
202 struct clk *clk;
203 unsigned long ref_clk_rate;
204 struct cdns_torrent_inst phys[MAX_NUM_LANES];
205 int nsubnodes;
206 struct regmap *regmap;
207 struct regmap *regmap_common_cdb;
208 struct regmap *regmap_phy_pcs_common_cdb;
209 struct regmap *regmap_phy_pma_common_cdb;
210 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
211 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
212 struct regmap *regmap_dptx_phy_reg;
213 struct regmap_field *phy_pll_cfg;
214 struct regmap_field *phy_pma_cmn_ctrl_2;
215 struct regmap_field *phy_pma_pll_raw_ctrl;
216 struct regmap_field *phy_reset_ctrl;
217};
218
219enum phy_powerstate {
220 POWERSTATE_A0 = 0,
221 /* Powerstate A1 is unused */
222 POWERSTATE_A2 = 2,
223 POWERSTATE_A3 = 3,
224};
225
226static int cdns_torrent_dp_init(struct phy *phy);
227static int cdns_torrent_dp_exit(struct phy *phy);
228static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
229 u32 num_lanes);
230static
231int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
232static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
233 struct cdns_torrent_inst *inst);
234static
235void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
236static
237void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
238 u32 rate, bool ssc);
239static
240void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
241static
242void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
243 u32 rate, bool ssc);
244static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
245 unsigned int lane);
246static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
247 u32 rate, u32 num_lanes);
248static int cdns_torrent_dp_configure(struct phy *phy,
249 union phy_configure_opts *opts);
250static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
251 u32 num_lanes,
252 enum phy_powerstate powerstate);
253static int cdns_torrent_phy_on(struct phy *phy);
254static int cdns_torrent_phy_off(struct phy *phy);
255
256static const struct phy_ops cdns_torrent_phy_ops = {
257 .init = cdns_torrent_dp_init,
258 .exit = cdns_torrent_dp_exit,
259 .configure = cdns_torrent_dp_configure,
260 .power_on = cdns_torrent_phy_on,
261 .power_off = cdns_torrent_phy_off,
262 .owner = THIS_MODULE,
263};
264
265struct cdns_torrent_data {
266 u8 block_offset_shift;
267 u8 reg_offset_shift;
268};
269
270struct cdns_regmap_cdb_context {
271 struct device *dev;
272 void __iomem *base;
273 u8 reg_offset_shift;
274};
275
276static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
277{
278 struct cdns_regmap_cdb_context *ctx = context;
279 u32 offset = reg << ctx->reg_offset_shift;
280
281 writew(val, ctx->base + offset);
282
283 return 0;
284}
285
286static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
287{
288 struct cdns_regmap_cdb_context *ctx = context;
289 u32 offset = reg << ctx->reg_offset_shift;
290
291 *val = readw(ctx->base + offset);
292 return 0;
293}
294
295static int cdns_regmap_dptx_write(void *context, unsigned int reg,
296 unsigned int val)
297{
298 struct cdns_regmap_cdb_context *ctx = context;
299 u32 offset = reg;
300
301 writel(val, ctx->base + offset);
302
303 return 0;
304}
305
306static int cdns_regmap_dptx_read(void *context, unsigned int reg,
307 unsigned int *val)
308{
309 struct cdns_regmap_cdb_context *ctx = context;
310 u32 offset = reg;
311
312 *val = readl(ctx->base + offset);
313 return 0;
314}
315
316#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
317{ \
318 .name = "torrent_tx_lane" n "_cdb", \
319 .reg_stride = 1, \
320 .fast_io = true, \
321 .reg_write = cdns_regmap_write, \
322 .reg_read = cdns_regmap_read, \
323}
324
325#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
326{ \
327 .name = "torrent_rx_lane" n "_cdb", \
328 .reg_stride = 1, \
329 .fast_io = true, \
330 .reg_write = cdns_regmap_write, \
331 .reg_read = cdns_regmap_read, \
332}
333
334static struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
335 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
336 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
337 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
338 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
339};
340
341static struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
342 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
343 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
344 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
345 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
346};
347
348static struct regmap_config cdns_torrent_common_cdb_config = {
349 .name = "torrent_common_cdb",
350 .reg_stride = 1,
351 .fast_io = true,
352 .reg_write = cdns_regmap_write,
353 .reg_read = cdns_regmap_read,
354};
355
356static struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
357 .name = "torrent_phy_pcs_cmn_cdb",
358 .reg_stride = 1,
359 .fast_io = true,
360 .reg_write = cdns_regmap_write,
361 .reg_read = cdns_regmap_read,
362};
363
364static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
365 .name = "torrent_phy_pma_cmn_cdb",
366 .reg_stride = 1,
367 .fast_io = true,
368 .reg_write = cdns_regmap_write,
369 .reg_read = cdns_regmap_read,
370};
371
372static struct regmap_config cdns_torrent_dptx_phy_config = {
373 .name = "torrent_dptx_phy",
374 .reg_stride = 1,
375 .fast_io = true,
376 .reg_write = cdns_regmap_dptx_write,
377 .reg_read = cdns_regmap_dptx_read,
378};
379
380/* PHY mmr access functions */
381
382static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
383{
384 regmap_write(regmap, offset, val);
385}
386
387static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
388{
389 unsigned int val;
390
391 regmap_read(regmap, offset, &val);
392 return val;
393}
394
395/* DPTX mmr access functions */
396
397static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
398{
399 regmap_write(regmap, offset, val);
400}
401
402static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
403{
404 u32 val;
405
406 regmap_read(regmap, offset, &val);
407 return val;
408}
409
410/*
411 * Structure used to store values of PHY registers for voltage-related
412 * coefficients, for particular voltage swing and pre-emphasis level. Values
413 * are shared across all physical lanes.
414 */
415struct coefficients {
416 /* Value of DRV_DIAG_TX_DRV register to use */
417 u16 diag_tx_drv;
418 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
419 u16 mgnfs_mult;
420 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
421 u16 cpost_mult;
422};
423
424/*
425 * Array consists of values of voltage-related registers for sd0801 PHY. A value
426 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
427 */
428static const struct coefficients vltg_coeff[4][4] = {
429 /* voltage swing 0, pre-emphasis 0->3 */
430 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
431 .cpost_mult = 0x0000},
432 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
433 .cpost_mult = 0x0014},
434 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
435 .cpost_mult = 0x0020},
436 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
437 .cpost_mult = 0x002A}
438 },
439
440 /* voltage swing 1, pre-emphasis 0->3 */
441 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
442 .cpost_mult = 0x0000},
443 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
444 .cpost_mult = 0x0012},
445 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
446 .cpost_mult = 0x001F},
447 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
448 .cpost_mult = 0xFFFF}
449 },
450
451 /* voltage swing 2, pre-emphasis 0->3 */
452 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
453 .cpost_mult = 0x0000},
454 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
455 .cpost_mult = 0x0013},
456 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
457 .cpost_mult = 0xFFFF},
458 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
459 .cpost_mult = 0xFFFF}
460 },
461
462 /* voltage swing 3, pre-emphasis 0->3 */
463 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
464 .cpost_mult = 0x0000},
465 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
466 .cpost_mult = 0xFFFF},
467 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
468 .cpost_mult = 0xFFFF},
469 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
470 .cpost_mult = 0xFFFF}
471 }
472};
473
474/*
475 * Enable or disable PLL for selected lanes.
476 */
477static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
478 struct phy_configure_opts_dp *dp,
479 bool enable)
480{
481 u32 rd_val;
482 u32 ret;
483 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
484
485 /*
486 * Used to determine, which bits to check for or enable in
487 * PHY_PMA_XCVR_PLLCLK_EN register.
488 */
489 u32 pll_bits;
490 /* Used to enable or disable lanes. */
491 u32 pll_val;
492
493 /* Select values of registers and mask, depending on enabled lane
494 * count.
495 */
496 switch (dp->lanes) {
497 /* lane 0 */
498 case (1):
499 pll_bits = 0x00000001;
500 break;
501 /* lanes 0-1 */
502 case (2):
503 pll_bits = 0x00000003;
504 break;
505 /* lanes 0-3, all */
506 default:
507 pll_bits = 0x0000000F;
508 break;
509 }
510
511 if (enable)
512 pll_val = pll_bits;
513 else
514 pll_val = 0x00000000;
515
516 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
517
518 /* Wait for acknowledgment from PHY. */
519 ret = regmap_read_poll_timeout(regmap,
520 PHY_PMA_XCVR_PLLCLK_EN_ACK,
521 rd_val,
522 (rd_val & pll_bits) == pll_val,
523 0, POLL_TIMEOUT_US);
524 ndelay(100);
525 return ret;
526}
527
528/*
529 * Perform register operations related to setting link rate, once powerstate is
530 * set and PLL disable request was processed.
531 */
532static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
533 struct phy_configure_opts_dp *dp)
534{
535 u32 ret;
536 u32 read_val;
537
538 /* Disable the cmn_pll0_en before re-programming the new data rate. */
539 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
540
541 /*
542 * Wait for PLL ready de-assertion.
543 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
544 */
545 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
546 read_val,
547 ((read_val >> 2) & 0x01) != 0,
548 0, POLL_TIMEOUT_US);
549 if (ret)
550 return ret;
551 ndelay(200);
552
553 /* DP Rate Change - VCO Output settings. */
554 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
555 /* PMA common configuration 19.2MHz */
556 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
557 dp->ssc);
558 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
559 } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
560 /* PMA common configuration 25MHz */
561 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
562 dp->ssc);
563 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
564 }
565 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
566
567 /* Enable the cmn_pll0_en. */
568 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
569
570 /*
571 * Wait for PLL ready assertion.
572 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
573 */
574 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
575 read_val,
576 (read_val & 0x01) != 0,
577 0, POLL_TIMEOUT_US);
578 return ret;
579}
580
581/*
582 * Verify, that parameters to configure PHY with are correct.
583 */
584static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
585 struct phy_configure_opts_dp *dp)
586{
587 u8 i;
588
589 /* If changing link rate was required, verify it's supported. */
590 if (dp->set_rate) {
591 switch (dp->link_rate) {
592 case 1620:
593 case 2160:
594 case 2430:
595 case 2700:
596 case 3240:
597 case 4320:
598 case 5400:
599 case 8100:
600 /* valid bit rate */
601 break;
602 default:
603 return -EINVAL;
604 }
605 }
606
607 /* Verify lane count. */
608 switch (dp->lanes) {
609 case 1:
610 case 2:
611 case 4:
612 /* valid lane count. */
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 /* Check against actual number of PHY's lanes. */
619 if (dp->lanes > inst->num_lanes)
620 return -EINVAL;
621
622 /*
623 * If changing voltages is required, check swing and pre-emphasis
624 * levels, per-lane.
625 */
626 if (dp->set_voltages) {
627 /* Lane count verified previously. */
628 for (i = 0; i < dp->lanes; i++) {
629 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
630 return -EINVAL;
631
632 /* Sum of voltage swing and pre-emphasis levels cannot
633 * exceed 3.
634 */
635 if (dp->voltage[i] + dp->pre[i] > 3)
636 return -EINVAL;
637 }
638 }
639
640 return 0;
641}
642
643/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
644static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
645 u32 num_lanes)
646{
647 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
648 u32 pwr_state = cdns_torrent_dp_read(regmap,
649 PHY_PMA_XCVR_POWER_STATE_REQ);
650 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
651 PHY_PMA_XCVR_PLLCLK_EN);
652
653 /* Lane 0 is always enabled. */
654 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
655 PHY_POWER_STATE_LN_0);
656 pll_clk_en &= ~0x01U;
657
658 if (num_lanes > 1) {
659 /* lane 1 */
660 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
661 PHY_POWER_STATE_LN_1);
662 pll_clk_en &= ~(0x01U << 1);
663 }
664
665 if (num_lanes > 2) {
666 /* lanes 2 and 3 */
667 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
668 PHY_POWER_STATE_LN_2);
669 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
670 PHY_POWER_STATE_LN_3);
671 pll_clk_en &= ~(0x01U << 2);
672 pll_clk_en &= ~(0x01U << 3);
673 }
674
675 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
676 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
677}
678
679/* Configure lane count as required. */
680static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
681 struct phy_configure_opts_dp *dp)
682{
683 u32 value;
684 u32 ret;
685 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
686 u8 lane_mask = (1 << dp->lanes) - 1;
687
688 value = cdns_torrent_dp_read(regmap, PHY_RESET);
689 /* clear pma_tx_elec_idle_ln_* bits. */
690 value &= ~PMA_TX_ELEC_IDLE_MASK;
691 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
692 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
693 PMA_TX_ELEC_IDLE_MASK;
694 cdns_torrent_dp_write(regmap, PHY_RESET, value);
695
696 /* reset the link by asserting phy_l00_reset_n low */
697 cdns_torrent_dp_write(regmap, PHY_RESET,
698 value & (~PHY_L00_RESET_N_MASK));
699
700 /*
701 * Assert lane reset on unused lanes and lane 0 so they remain in reset
702 * and powered down when re-enabling the link
703 */
704 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
705 cdns_torrent_dp_write(regmap, PHY_RESET, value);
706
707 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
708
709 /* release phy_l0*_reset_n based on used laneCount */
710 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
711 cdns_torrent_dp_write(regmap, PHY_RESET, value);
712
713 /* Wait, until PHY gets ready after releasing PHY reset signal. */
714 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
715 if (ret)
716 return ret;
717
718 ndelay(100);
719
720 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
721 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
722
723 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
724
725 return ret;
726}
727
728/* Configure link rate as required. */
729static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
730 struct phy_configure_opts_dp *dp)
731{
732 u32 ret;
733
734 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
735 POWERSTATE_A3);
736 if (ret)
737 return ret;
738 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
739 if (ret)
740 return ret;
741 ndelay(200);
742
743 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
744 if (ret)
745 return ret;
746 ndelay(200);
747
748 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
749 if (ret)
750 return ret;
751 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
752 POWERSTATE_A2);
753 if (ret)
754 return ret;
755 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
756 POWERSTATE_A0);
757 if (ret)
758 return ret;
759 ndelay(900);
760
761 return ret;
762}
763
764/* Configure voltage swing and pre-emphasis for all enabled lanes. */
765static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
766 struct phy_configure_opts_dp *dp)
767{
768 u8 lane;
769 u16 val;
770
771 for (lane = 0; lane < dp->lanes; lane++) {
772 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
773 TX_DIAG_ACYA);
774 /*
775 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
776 * current state of the analog TX driver.
777 */
778 val |= TX_DIAG_ACYA_HBDC_MASK;
779 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
780 TX_DIAG_ACYA, val);
781
782 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
783 TX_TXCC_CTRL, 0x08A4);
784 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
785 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
786 DRV_DIAG_TX_DRV, val);
787 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
788 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
789 TX_TXCC_MGNFS_MULT_000,
790 val);
791 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
792 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
793 TX_TXCC_CPOST_MULT_00,
794 val);
795
796 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
797 TX_DIAG_ACYA);
798 /*
799 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
800 * analog TX driver to reflect the new programmed one.
801 */
802 val &= ~TX_DIAG_ACYA_HBDC_MASK;
803 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
804 TX_DIAG_ACYA, val);
805 }
806};
807
808static int cdns_torrent_dp_configure(struct phy *phy,
809 union phy_configure_opts *opts)
810{
811 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
812 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
813 int ret;
814
815 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
816 if (ret) {
817 dev_err(&phy->dev, "invalid params for phy configure\n");
818 return ret;
819 }
820
821 if (opts->dp.set_lanes) {
822 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
823 if (ret) {
824 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
825 return ret;
826 }
827 }
828
829 if (opts->dp.set_rate) {
830 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
831 if (ret) {
832 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
833 return ret;
834 }
835 }
836
837 if (opts->dp.set_voltages)
838 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
839
840 return ret;
841}
842
843static int cdns_torrent_dp_init(struct phy *phy)
844{
845 unsigned char lane_bits;
846 int ret;
847 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
848 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
849 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
850
851 ret = clk_prepare_enable(cdns_phy->clk);
852 if (ret) {
853 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
854 return ret;
855 }
856
857 cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
858 if (!(cdns_phy->ref_clk_rate)) {
859 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
860 clk_disable_unprepare(cdns_phy->clk);
861 return -EINVAL;
862 }
863
864 switch (cdns_phy->ref_clk_rate) {
865 case REF_CLK_19_2MHz:
866 case REF_CLK_25MHz:
867 /* Valid Ref Clock Rate */
868 break;
869 default:
870 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
871 return -EINVAL;
872 }
873
874 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
875
876 /* PHY PMA registers configuration function */
877 cdns_torrent_dp_pma_cfg(cdns_phy, inst);
878
879 /*
880 * Set lines power state to A0
881 * Set lines pll clk enable to 0
882 */
883 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
884
885 /*
886 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
887 * used lanes
888 */
889 lane_bits = (1 << inst->num_lanes) - 1;
890 cdns_torrent_dp_write(regmap, PHY_RESET,
891 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
892
893 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
894 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
895
896 /* PHY PMA registers configuration functions */
897 /* Initialize PHY with max supported link rate, without SSC. */
898 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
899 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
900 cdns_phy->max_bit_rate,
901 false);
902 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
903 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
904 cdns_phy->max_bit_rate,
905 false);
906 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
907 inst->num_lanes);
908
909 /* take out of reset */
910 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
911
912 cdns_torrent_phy_on(phy);
913
914 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
915 if (ret)
916 return ret;
917
918 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
919
920 return ret;
921}
922
923static int cdns_torrent_dp_exit(struct phy *phy)
924{
925 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
926
927 clk_disable_unprepare(cdns_phy->clk);
928 return 0;
929}
930
931static
932int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
933{
934 unsigned int reg;
935 int ret;
936 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
937
938 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
939 reg & 1, 0, POLL_TIMEOUT_US);
940 if (ret == -ETIMEDOUT) {
941 dev_err(cdns_phy->dev,
942 "timeout waiting for PMA common ready\n");
943 return -ETIMEDOUT;
944 }
945
946 return 0;
947}
948
949static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
950 struct cdns_torrent_inst *inst)
951{
952 unsigned int i;
953
954 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
955 /* PMA common configuration 19.2MHz */
956 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
957 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
958 /* PMA common configuration 25MHz */
959 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
960
961 /* PMA lane configuration to deal with multi-link operation */
962 for (i = 0; i < inst->num_lanes; i++)
963 cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
964}
965
966static
967void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
968{
969 struct regmap *regmap = cdns_phy->regmap_common_cdb;
970
971 /* refclock registers - assumes 19.2 MHz refclock */
972 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
973 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
974 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
975 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
976 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
977 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
978 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
979 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
980 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
981 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
982 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
983 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
984 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
985 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
986 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
987 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
988 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
989 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
990
991 /* PLL registers */
992 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
993 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
994 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
995 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
996 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
997 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
998 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
999 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1000 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
1001 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1002 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
1003 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1004 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
1005 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1006 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
1007 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1008}
1009
1010/*
1011 * Set registers responsible for enabling and configuring SSC, with second and
1012 * third register values provided by parameters.
1013 */
1014static
1015void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1016 u32 ctrl2_val, u32 ctrl3_val)
1017{
1018 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1019
1020 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1021 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1022 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
1023 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1024 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1025 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1026 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
1027 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1028}
1029
1030static
1031void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1032 u32 rate, bool ssc)
1033{
1034 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1035
1036 /* Assumes 19.2 MHz refclock */
1037 switch (rate) {
1038 /* Setting VCO for 10.8GHz */
1039 case 2700:
1040 case 5400:
1041 cdns_torrent_phy_write(regmap,
1042 CMN_PLL0_INTDIV_M0, 0x0119);
1043 cdns_torrent_phy_write(regmap,
1044 CMN_PLL0_FRACDIVL_M0, 0x4000);
1045 cdns_torrent_phy_write(regmap,
1046 CMN_PLL0_FRACDIVH_M0, 0x0002);
1047 cdns_torrent_phy_write(regmap,
1048 CMN_PLL0_HIGH_THR_M0, 0x00BC);
1049 cdns_torrent_phy_write(regmap,
1050 CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
1051 cdns_torrent_phy_write(regmap,
1052 CMN_PLL1_INTDIV_M0, 0x0119);
1053 cdns_torrent_phy_write(regmap,
1054 CMN_PLL1_FRACDIVL_M0, 0x4000);
1055 cdns_torrent_phy_write(regmap,
1056 CMN_PLL1_FRACDIVH_M0, 0x0002);
1057 cdns_torrent_phy_write(regmap,
1058 CMN_PLL1_HIGH_THR_M0, 0x00BC);
1059 cdns_torrent_phy_write(regmap,
1060 CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
1061 if (ssc)
1062 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
1063 0x006A);
1064 break;
1065 /* Setting VCO for 9.72GHz */
1066 case 1620:
1067 case 2430:
1068 case 3240:
1069 cdns_torrent_phy_write(regmap,
1070 CMN_PLL0_INTDIV_M0, 0x01FA);
1071 cdns_torrent_phy_write(regmap,
1072 CMN_PLL0_FRACDIVL_M0, 0x4000);
1073 cdns_torrent_phy_write(regmap,
1074 CMN_PLL0_FRACDIVH_M0, 0x0002);
1075 cdns_torrent_phy_write(regmap,
1076 CMN_PLL0_HIGH_THR_M0, 0x0152);
1077 cdns_torrent_phy_write(regmap,
1078 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1079 cdns_torrent_phy_write(regmap,
1080 CMN_PLL1_INTDIV_M0, 0x01FA);
1081 cdns_torrent_phy_write(regmap,
1082 CMN_PLL1_FRACDIVL_M0, 0x4000);
1083 cdns_torrent_phy_write(regmap,
1084 CMN_PLL1_FRACDIVH_M0, 0x0002);
1085 cdns_torrent_phy_write(regmap,
1086 CMN_PLL1_HIGH_THR_M0, 0x0152);
1087 cdns_torrent_phy_write(regmap,
1088 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1089 if (ssc)
1090 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
1091 0x0069);
1092 break;
1093 /* Setting VCO for 8.64GHz */
1094 case 2160:
1095 case 4320:
1096 cdns_torrent_phy_write(regmap,
1097 CMN_PLL0_INTDIV_M0, 0x01C2);
1098 cdns_torrent_phy_write(regmap,
1099 CMN_PLL0_FRACDIVL_M0, 0x0000);
1100 cdns_torrent_phy_write(regmap,
1101 CMN_PLL0_FRACDIVH_M0, 0x0002);
1102 cdns_torrent_phy_write(regmap,
1103 CMN_PLL0_HIGH_THR_M0, 0x012C);
1104 cdns_torrent_phy_write(regmap,
1105 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1106 cdns_torrent_phy_write(regmap,
1107 CMN_PLL1_INTDIV_M0, 0x01C2);
1108 cdns_torrent_phy_write(regmap,
1109 CMN_PLL1_FRACDIVL_M0, 0x0000);
1110 cdns_torrent_phy_write(regmap,
1111 CMN_PLL1_FRACDIVH_M0, 0x0002);
1112 cdns_torrent_phy_write(regmap,
1113 CMN_PLL1_HIGH_THR_M0, 0x012C);
1114 cdns_torrent_phy_write(regmap,
1115 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1116 if (ssc)
1117 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
1118 0x0069);
1119 break;
1120 /* Setting VCO for 8.1GHz */
1121 case 8100:
1122 cdns_torrent_phy_write(regmap,
1123 CMN_PLL0_INTDIV_M0, 0x01A5);
1124 cdns_torrent_phy_write(regmap,
1125 CMN_PLL0_FRACDIVL_M0, 0xE000);
1126 cdns_torrent_phy_write(regmap,
1127 CMN_PLL0_FRACDIVH_M0, 0x0002);
1128 cdns_torrent_phy_write(regmap,
1129 CMN_PLL0_HIGH_THR_M0, 0x011A);
1130 cdns_torrent_phy_write(regmap,
1131 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1132 cdns_torrent_phy_write(regmap,
1133 CMN_PLL1_INTDIV_M0, 0x01A5);
1134 cdns_torrent_phy_write(regmap,
1135 CMN_PLL1_FRACDIVL_M0, 0xE000);
1136 cdns_torrent_phy_write(regmap,
1137 CMN_PLL1_FRACDIVH_M0, 0x0002);
1138 cdns_torrent_phy_write(regmap,
1139 CMN_PLL1_HIGH_THR_M0, 0x011A);
1140 cdns_torrent_phy_write(regmap,
1141 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1142 if (ssc)
1143 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
1144 0x006A);
1145 break;
1146 }
1147
1148 if (ssc) {
1149 cdns_torrent_phy_write(regmap,
1150 CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
1151 cdns_torrent_phy_write(regmap,
1152 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1153 cdns_torrent_phy_write(regmap,
1154 CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
1155 cdns_torrent_phy_write(regmap,
1156 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1157 } else {
1158 cdns_torrent_phy_write(regmap,
1159 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
1160 cdns_torrent_phy_write(regmap,
1161 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
1162 /* Set reset register values to disable SSC */
1163 cdns_torrent_phy_write(regmap,
1164 CMN_PLL0_SS_CTRL1_M0, 0x0002);
1165 cdns_torrent_phy_write(regmap,
1166 CMN_PLL0_SS_CTRL2_M0, 0x0000);
1167 cdns_torrent_phy_write(regmap,
1168 CMN_PLL0_SS_CTRL3_M0, 0x0000);
1169 cdns_torrent_phy_write(regmap,
1170 CMN_PLL0_SS_CTRL4_M0, 0x0000);
1171 cdns_torrent_phy_write(regmap,
1172 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1173 cdns_torrent_phy_write(regmap,
1174 CMN_PLL1_SS_CTRL1_M0, 0x0002);
1175 cdns_torrent_phy_write(regmap,
1176 CMN_PLL1_SS_CTRL2_M0, 0x0000);
1177 cdns_torrent_phy_write(regmap,
1178 CMN_PLL1_SS_CTRL3_M0, 0x0000);
1179 cdns_torrent_phy_write(regmap,
1180 CMN_PLL1_SS_CTRL4_M0, 0x0000);
1181 cdns_torrent_phy_write(regmap,
1182 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1183 }
1184
1185 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
1186 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
1187 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
1188 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
1189}
1190
1191static
1192void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
1193{
1194 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1195
1196 /* refclock registers - assumes 25 MHz refclock */
1197 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
1198 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
1199 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
1200 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
1201 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
1202 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
1203 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
1204 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
1205 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
1206 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
1207 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
1208 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
1209 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
1210 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
1211 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
1212 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
1213 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
1214 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
1215
1216 /* PLL registers */
1217 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1218 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1219 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1220 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1221 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1222 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1223 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1224 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1225 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
1226 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1227 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
1228 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1229 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
1230 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1231 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
1232 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1233}
1234
1235/*
1236 * Set registers responsible for enabling and configuring SSC, with second
1237 * register value provided by a parameter.
1238 */
1239static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
1240 u32 ctrl2_val)
1241{
1242 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1243
1244 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1245 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1246 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
1247 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1248 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1249 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1250 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
1251 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1252}
1253
1254static
1255void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
1256 u32 rate, bool ssc)
1257{
1258 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1259
1260 /* Assumes 25 MHz refclock */
1261 switch (rate) {
1262 /* Setting VCO for 10.8GHz */
1263 case 2700:
1264 case 5400:
1265 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
1266 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1267 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1268 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
1269 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
1270 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1271 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1272 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
1273 if (ssc)
1274 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
1275 break;
1276 /* Setting VCO for 9.72GHz */
1277 case 1620:
1278 case 2430:
1279 case 3240:
1280 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
1281 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
1282 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1283 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
1284 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
1285 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
1286 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1287 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
1288 if (ssc)
1289 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
1290 break;
1291 /* Setting VCO for 8.64GHz */
1292 case 2160:
1293 case 4320:
1294 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
1295 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
1296 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1297 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
1298 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
1299 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
1300 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1301 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
1302 if (ssc)
1303 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
1304 break;
1305 /* Setting VCO for 8.1GHz */
1306 case 8100:
1307 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
1308 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1309 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1310 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
1311 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
1312 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1313 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1314 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
1315 if (ssc)
1316 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
1317 break;
1318 }
1319
1320 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1321 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1322
1323 if (ssc) {
1324 cdns_torrent_phy_write(regmap,
1325 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
1326 cdns_torrent_phy_write(regmap,
1327 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1328 cdns_torrent_phy_write(regmap,
1329 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
1330 cdns_torrent_phy_write(regmap,
1331 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1332 } else {
1333 cdns_torrent_phy_write(regmap,
1334 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
1335 cdns_torrent_phy_write(regmap,
1336 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
1337 /* Set reset register values to disable SSC */
1338 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
1339 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
1340 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
1341 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
1342 cdns_torrent_phy_write(regmap,
1343 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1344 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
1345 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
1346 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
1347 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
1348 cdns_torrent_phy_write(regmap,
1349 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1350 }
1351
1352 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
1353 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
1354 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
1355 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
1356}
1357
1358static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1359 u32 rate, u32 num_lanes)
1360{
1361 unsigned int clk_sel_val = 0;
1362 unsigned int hsclk_div_val = 0;
1363 unsigned int i;
1364
1365 /* 16'h0000 for single DP link configuration */
1366 regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
1367
1368 switch (rate) {
1369 case 1620:
1370 clk_sel_val = 0x0f01;
1371 hsclk_div_val = 2;
1372 break;
1373 case 2160:
1374 case 2430:
1375 case 2700:
1376 clk_sel_val = 0x0701;
1377 hsclk_div_val = 1;
1378 break;
1379 case 3240:
1380 clk_sel_val = 0x0b00;
1381 hsclk_div_val = 2;
1382 break;
1383 case 4320:
1384 case 5400:
1385 clk_sel_val = 0x0301;
1386 hsclk_div_val = 0;
1387 break;
1388 case 8100:
1389 clk_sel_val = 0x0200;
1390 hsclk_div_val = 0;
1391 break;
1392 }
1393
1394 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1395 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1396 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1397 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1398
1399 /* PMA lane configuration to deal with multi-link operation */
1400 for (i = 0; i < num_lanes; i++)
1401 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1402 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1403}
1404
1405static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
1406 unsigned int lane)
1407{
1408 /* Per lane, refclock-dependent receiver detection setting */
1409 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1410 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1411 TX_RCVDET_ST_TMR, 0x0780);
1412 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1413 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1414 TX_RCVDET_ST_TMR, 0x09C4);
1415
1416 /* Writing Tx/Rx Power State Controllers registers */
1417 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1418 TX_PSC_A0, 0x00FB);
1419 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1420 TX_PSC_A2, 0x04AA);
1421 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1422 TX_PSC_A3, 0x04AA);
1423 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1424 RX_PSC_A0, 0x0000);
1425 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1426 RX_PSC_A2, 0x0000);
1427 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1428 RX_PSC_A3, 0x0000);
1429
1430 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1431 RX_PSC_CAL, 0x0000);
1432
1433 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1434 RX_REE_GCSM1_CTRL, 0x0000);
1435 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1436 RX_REE_GCSM2_CTRL, 0x0000);
1437 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1438 RX_REE_PERGCSM_CTRL, 0x0000);
1439
1440 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1441 XCVR_DIAG_BIDI_CTRL, 0x000F);
1442 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1443 XCVR_DIAG_PLLDRC_CTRL, 0x0001);
1444 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1445 XCVR_DIAG_HSCLK_SEL, 0x0000);
1446}
1447
1448static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1449 u32 num_lanes,
1450 enum phy_powerstate powerstate)
1451{
1452 /* Register value for power state for a single byte. */
1453 u32 value_part;
1454 u32 value;
1455 u32 mask;
1456 u32 read_val;
1457 u32 ret;
1458 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1459
1460 switch (powerstate) {
1461 case (POWERSTATE_A0):
1462 value_part = 0x01U;
1463 break;
1464 case (POWERSTATE_A2):
1465 value_part = 0x04U;
1466 break;
1467 default:
1468 /* Powerstate A3 */
1469 value_part = 0x08U;
1470 break;
1471 }
1472
1473 /* Select values of registers and mask, depending on enabled
1474 * lane count.
1475 */
1476 switch (num_lanes) {
1477 /* lane 0 */
1478 case (1):
1479 value = value_part;
1480 mask = 0x0000003FU;
1481 break;
1482 /* lanes 0-1 */
1483 case (2):
1484 value = (value_part
1485 | (value_part << 8));
1486 mask = 0x00003F3FU;
1487 break;
1488 /* lanes 0-3, all */
1489 default:
1490 value = (value_part
1491 | (value_part << 8)
1492 | (value_part << 16)
1493 | (value_part << 24));
1494 mask = 0x3F3F3F3FU;
1495 break;
1496 }
1497
1498 /* Set power state A<n>. */
1499 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1500 /* Wait, until PHY acknowledges power state completion. */
1501 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1502 read_val, (read_val & mask) == value, 0,
1503 POLL_TIMEOUT_US);
1504 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1505 ndelay(100);
1506
1507 return ret;
1508}
1509
1510static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1511{
1512 unsigned int read_val;
1513 int ret;
1514 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1515
1516 /*
1517 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1518 * master lane
1519 */
1520 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1521 read_val, read_val & 1,
1522 0, POLL_TIMEOUT_US);
1523 if (ret == -ETIMEDOUT) {
1524 dev_err(cdns_phy->dev,
1525 "timeout waiting for link PLL clock enable ack\n");
1526 return ret;
1527 }
1528
1529 ndelay(100);
1530
1531 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1532 POWERSTATE_A2);
1533 if (ret)
1534 return ret;
1535
1536 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1537 POWERSTATE_A0);
1538
1539 return ret;
1540}
1541
1542static int cdns_torrent_phy_on(struct phy *phy)
1543{
1544 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1545 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1546 int ret;
1547
1548 /* Take the PHY out of reset */
1549 ret = reset_control_deassert(cdns_phy->phy_rst);
1550 if (ret)
1551 return ret;
1552
1553 /* Take the PHY lane group out of reset */
1554 return reset_control_deassert(inst->lnk_rst);
1555}
1556
1557static int cdns_torrent_phy_off(struct phy *phy)
1558{
1559 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1560 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1561 int ret;
1562
1563 ret = reset_control_assert(cdns_phy->phy_rst);
1564 if (ret)
1565 return ret;
1566
1567 return reset_control_assert(inst->lnk_rst);
1568}
1569
1570static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1571 u32 block_offset,
1572 u8 reg_offset_shift,
1573 const struct regmap_config *config)
1574{
1575 struct cdns_regmap_cdb_context *ctx;
1576
1577 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1578 if (!ctx)
1579 return ERR_PTR(-ENOMEM);
1580
1581 ctx->dev = dev;
1582 ctx->base = base + block_offset;
1583 ctx->reg_offset_shift = reg_offset_shift;
1584
1585 return devm_regmap_init(dev, NULL, ctx, config);
1586}
1587
1588static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy)
1589{
1590 struct device *dev = cdns_phy->dev;
1591 struct regmap_field *field;
1592 struct regmap *regmap;
1593
1594 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1595 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1596 if (IS_ERR(field)) {
1597 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1598 return PTR_ERR(field);
1599 }
1600 cdns_phy->phy_pll_cfg = field;
1601
1602 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1603 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
1604 if (IS_ERR(field)) {
1605 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
1606 return PTR_ERR(field);
1607 }
1608 cdns_phy->phy_pma_cmn_ctrl_2 = field;
1609
1610 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1611 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
1612 if (IS_ERR(field)) {
1613 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
1614 return PTR_ERR(field);
1615 }
1616 cdns_phy->phy_pma_pll_raw_ctrl = field;
1617
1618 regmap = cdns_phy->regmap_dptx_phy_reg;
1619 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1620 if (IS_ERR(field)) {
1621 dev_err(dev, "PHY_RESET reg field init failed\n");
1622 return PTR_ERR(field);
1623 }
1624 cdns_phy->phy_reset_ctrl = field;
1625
1626 return 0;
1627}
1628
1629static int cdns_regmap_init_torrent_dp(struct cdns_torrent_phy *cdns_phy,
1630 void __iomem *sd_base,
1631 void __iomem *base,
1632 u8 block_offset_shift,
1633 u8 reg_offset_shift)
1634{
1635 struct device *dev = cdns_phy->dev;
1636 struct regmap *regmap;
1637 u32 block_offset;
1638 int i;
1639
1640 for (i = 0; i < MAX_NUM_LANES; i++) {
1641 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
1642 reg_offset_shift);
1643 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1644 reg_offset_shift,
1645 &cdns_torrent_tx_lane_cdb_config[i]);
1646 if (IS_ERR(regmap)) {
1647 dev_err(dev, "Failed to init tx lane CDB regmap\n");
1648 return PTR_ERR(regmap);
1649 }
1650 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
1651
1652 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
1653 reg_offset_shift);
1654 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1655 reg_offset_shift,
1656 &cdns_torrent_rx_lane_cdb_config[i]);
1657 if (IS_ERR(regmap)) {
1658 dev_err(dev, "Failed to init rx lane CDB regmap\n");
1659 return PTR_ERR(regmap);
1660 }
1661 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
1662 }
1663
1664 block_offset = TORRENT_COMMON_CDB_OFFSET;
1665 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1666 reg_offset_shift,
1667 &cdns_torrent_common_cdb_config);
1668 if (IS_ERR(regmap)) {
1669 dev_err(dev, "Failed to init common CDB regmap\n");
1670 return PTR_ERR(regmap);
1671 }
1672 cdns_phy->regmap_common_cdb = regmap;
1673
1674 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
1675 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1676 reg_offset_shift,
1677 &cdns_torrent_phy_pcs_cmn_cdb_config);
1678 if (IS_ERR(regmap)) {
1679 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1680 return PTR_ERR(regmap);
1681 }
1682 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
1683
1684 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
1685 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1686 reg_offset_shift,
1687 &cdns_torrent_phy_pma_cmn_cdb_config);
1688 if (IS_ERR(regmap)) {
1689 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1690 return PTR_ERR(regmap);
1691 }
1692 cdns_phy->regmap_phy_pma_common_cdb = regmap;
1693
1694 block_offset = TORRENT_DPTX_PHY_OFFSET;
1695 regmap = cdns_regmap_init(dev, base, block_offset,
1696 reg_offset_shift,
1697 &cdns_torrent_dptx_phy_config);
1698 if (IS_ERR(regmap)) {
1699 dev_err(dev, "Failed to init DPTX PHY regmap\n");
1700 return PTR_ERR(regmap);
1701 }
1702 cdns_phy->regmap_dptx_phy_reg = regmap;
1703
1704 return 0;
1705}
1706
1707static int cdns_torrent_phy_probe(struct platform_device *pdev)
1708{
1709 struct resource *regs;
1710 struct cdns_torrent_phy *cdns_phy;
1711 struct device *dev = &pdev->dev;
1712 struct phy_provider *phy_provider;
1713 const struct of_device_id *match;
1714 struct cdns_torrent_data *data;
1715 struct device_node *child;
1716 int ret, subnodes, node = 0, i;
1717
1718 /* Get init data for this PHY */
1719 match = of_match_device(cdns_torrent_phy_of_match, dev);
1720 if (!match)
1721 return -EINVAL;
1722
1723 data = (struct cdns_torrent_data *)match->data;
1724
1725 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
1726 if (!cdns_phy)
1727 return -ENOMEM;
1728
1729 dev_set_drvdata(dev, cdns_phy);
1730 cdns_phy->dev = dev;
1731
1732 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
1733 if (IS_ERR(cdns_phy->phy_rst)) {
1734 dev_err(dev, "%s: failed to get reset\n",
1735 dev->of_node->full_name);
1736 return PTR_ERR(cdns_phy->phy_rst);
1737 }
1738
1739 cdns_phy->clk = devm_clk_get(dev, "refclk");
1740 if (IS_ERR(cdns_phy->clk)) {
1741 dev_err(dev, "phy ref clock not found\n");
1742 return PTR_ERR(cdns_phy->clk);
1743 }
1744
1745 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1746 cdns_phy->sd_base = devm_ioremap_resource(&pdev->dev, regs);
1747 if (IS_ERR(cdns_phy->sd_base))
1748 return PTR_ERR(cdns_phy->sd_base);
1749
1750 subnodes = of_get_available_child_count(dev->of_node);
1751 if (subnodes == 0) {
1752 dev_err(dev, "No available link subnodes found\n");
1753 return -EINVAL;
1754 } else if (subnodes != 1) {
1755 dev_err(dev, "Driver supports only one link subnode.\n");
1756 return -EINVAL;
1757 }
1758
1759 for_each_available_child_of_node(dev->of_node, child) {
1760 struct phy *gphy;
1761
1762 cdns_phy->phys[node].lnk_rst =
1763 of_reset_control_array_get_exclusive(child);
1764 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
1765 dev_err(dev, "%s: failed to get reset\n",
1766 child->full_name);
1767 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
1768 goto put_lnk_rst;
1769 }
1770
1771 if (of_property_read_u32(child, "reg",
1772 &cdns_phy->phys[node].mlane)) {
1773 dev_err(dev, "%s: No \"reg\"-property.\n",
1774 child->full_name);
1775 ret = -EINVAL;
1776 goto put_child;
1777 }
1778
1779 if (cdns_phy->phys[node].mlane != 0) {
1780 dev_err(dev,
1781 "%s: Driver supports only lane-0 as master lane.\n",
1782 child->full_name);
1783 ret = -EINVAL;
1784 goto put_child;
1785 }
1786
1787 if (of_property_read_u32(child, "cdns,phy-type",
1788 &cdns_phy->phys[node].phy_type)) {
1789 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
1790 child->full_name);
1791 ret = -EINVAL;
1792 goto put_child;
1793 }
1794
1795 cdns_phy->phys[node].num_lanes = DEFAULT_NUM_LANES;
1796 of_property_read_u32(child, "cdns,num-lanes",
1797 &cdns_phy->phys[node].num_lanes);
1798
1799 if (cdns_phy->phys[node].phy_type == PHY_TYPE_DP) {
1800 switch (cdns_phy->phys[node].num_lanes) {
1801 case 1:
1802 case 2:
1803 case 4:
1804 /* valid number of lanes */
1805 break;
1806 default:
1807 dev_err(dev, "unsupported number of lanes: %d\n",
1808 cdns_phy->phys[node].num_lanes);
1809 ret = -EINVAL;
1810 goto put_child;
1811 }
1812
1813 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
1814 of_property_read_u32(child, "cdns,max-bit-rate",
1815 &cdns_phy->max_bit_rate);
1816
1817 switch (cdns_phy->max_bit_rate) {
1818 case 1620:
1819 case 2160:
1820 case 2430:
1821 case 2700:
1822 case 3240:
1823 case 4320:
1824 case 5400:
1825 case 8100:
1826 /* valid bit rate */
1827 break;
1828 default:
1829 dev_err(dev, "unsupported max bit rate: %dMbps\n",
1830 cdns_phy->max_bit_rate);
1831 ret = -EINVAL;
1832 goto put_child;
1833 }
1834
1835 /* DPTX registers */
1836 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1837 cdns_phy->base = devm_ioremap_resource(&pdev->dev,
1838 regs);
1839 if (IS_ERR(cdns_phy->base)) {
1840 ret = PTR_ERR(cdns_phy->base);
1841 goto put_child;
1842 }
1843
1844 gphy = devm_phy_create(dev, child,
1845 &cdns_torrent_phy_ops);
1846 if (IS_ERR(gphy)) {
1847 ret = PTR_ERR(gphy);
1848 goto put_child;
1849 }
1850
1851 dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
1852 cdns_phy->phys[node].num_lanes,
1853 cdns_phy->max_bit_rate / 1000,
1854 cdns_phy->max_bit_rate % 1000);
1855 } else {
1856 dev_err(dev, "Driver supports only PHY_TYPE_DP\n");
1857 ret = -ENOTSUPP;
1858 goto put_child;
1859 }
1860 cdns_phy->phys[node].phy = gphy;
1861 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
1862
1863 node++;
1864 }
1865 cdns_phy->nsubnodes = node;
1866
1867 ret = cdns_regmap_init_torrent_dp(cdns_phy, cdns_phy->sd_base,
1868 cdns_phy->base,
1869 data->block_offset_shift,
1870 data->reg_offset_shift);
1871 if (ret)
1872 goto put_lnk_rst;
1873
1874 ret = cdns_regfield_init(cdns_phy);
1875 if (ret)
1876 goto put_lnk_rst;
1877
1878 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1879 if (IS_ERR(phy_provider)) {
1880 ret = PTR_ERR(phy_provider);
1881 goto put_lnk_rst;
1882 }
1883
1884 return 0;
1885
1886put_child:
1887 node++;
1888put_lnk_rst:
1889 for (i = 0; i < node; i++)
1890 reset_control_put(cdns_phy->phys[i].lnk_rst);
1891 of_node_put(child);
1892 return ret;
1893}
1894
1895static int cdns_torrent_phy_remove(struct platform_device *pdev)
1896{
1897 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
1898 int i;
1899
1900 reset_control_assert(cdns_phy->phy_rst);
1901 for (i = 0; i < cdns_phy->nsubnodes; i++) {
1902 reset_control_assert(cdns_phy->phys[i].lnk_rst);
1903 reset_control_put(cdns_phy->phys[i].lnk_rst);
1904 }
1905
1906 return 0;
1907}
1908
1909static const struct cdns_torrent_data cdns_map_torrent = {
1910 .block_offset_shift = 0x2,
1911 .reg_offset_shift = 0x2,
1912};
1913
1914static const struct cdns_torrent_data ti_j721e_map_torrent = {
1915 .block_offset_shift = 0x0,
1916 .reg_offset_shift = 0x1,
1917};
1918
1919static const struct of_device_id cdns_torrent_phy_of_match[] = {
1920 {
1921 .compatible = "cdns,torrent-phy",
1922 .data = &cdns_map_torrent,
1923 },
1924 {
1925 .compatible = "ti,j721e-serdes-10g",
1926 .data = &ti_j721e_map_torrent,
1927 },
1928 {}
1929};
1930MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
1931
1932static struct platform_driver cdns_torrent_phy_driver = {
1933 .probe = cdns_torrent_phy_probe,
1934 .remove = cdns_torrent_phy_remove,
1935 .driver = {
1936 .name = "cdns-torrent-phy",
1937 .of_match_table = cdns_torrent_phy_of_match,
1938 }
1939};
1940module_platform_driver(cdns_torrent_phy_driver);
1941
1942MODULE_AUTHOR("Cadence Design Systems, Inc.");
1943MODULE_DESCRIPTION("Cadence Torrent PHY driver");
1944MODULE_LICENSE("GPL v2");