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1// SPDX-License-Identifier: GPL-2.0-only
2/*======================================================================
3
4 Device driver for the PCMCIA control functionality of PXA2xx
5 microprocessors.
6
7
8 (c) Ian Molton (spyro@f2s.com) 2003
9 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
10
11 derived from sa11xx_base.c
12
13 Portions created by John G. Dorsey are
14 Copyright (C) 1999 John G. Dorsey.
15
16 ======================================================================*/
17
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/ioport.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/platform_device.h>
26#include <linux/soc/pxa/cpu.h>
27#include <linux/soc/pxa/smemc.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32
33#include <pcmcia/ss.h>
34#include <pcmcia/cistpl.h>
35
36#include "soc_common.h"
37#include "pxa2xx_base.h"
38
39/*
40 * Personal Computer Memory Card International Association (PCMCIA) sockets
41 */
42
43#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
44#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
45#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
46#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
47#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
48
49#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
50#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
51#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
52#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
53
54#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
55#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
56#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
57#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
58
59#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
60 (0x20000000 + (Nb) * PCMCIASp)
61#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
62#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
63 (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
64#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
65 (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
66
67#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
68#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
69#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
70#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
71
72#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
73#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
74#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
75#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
76
77
78#define MCXX_SETUP_MASK (0x7f)
79#define MCXX_ASST_MASK (0x1f)
80#define MCXX_HOLD_MASK (0x3f)
81#define MCXX_SETUP_SHIFT (0)
82#define MCXX_ASST_SHIFT (7)
83#define MCXX_HOLD_SHIFT (14)
84
85static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
86 u_int mem_clk_10khz)
87{
88 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
89 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
90}
91
92static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
93 u_int mem_clk_10khz)
94{
95 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
96 return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
97}
98
99static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
100 u_int mem_clk_10khz)
101{
102 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
103 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
104}
105
106/* This function returns the (approximate) command assertion period, in
107 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
108 */
109static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
110 u_int pcmcia_mcxx_asst)
111{
112 return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
113}
114
115static uint32_t pxa2xx_pcmcia_mcmem(int sock, int speed, int clock)
116{
117 uint32_t val;
118
119 val = ((pxa2xx_mcxx_setup(speed, clock)
120 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
121 | ((pxa2xx_mcxx_asst(speed, clock)
122 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
123 | ((pxa2xx_mcxx_hold(speed, clock)
124 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
125
126 return val;
127}
128
129static int pxa2xx_pcmcia_mcio(int sock, int speed, int clock)
130{
131 uint32_t val;
132
133 val = ((pxa2xx_mcxx_setup(speed, clock)
134 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
135 | ((pxa2xx_mcxx_asst(speed, clock)
136 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
137 | ((pxa2xx_mcxx_hold(speed, clock)
138 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
139
140
141 return val;
142}
143
144static int pxa2xx_pcmcia_mcatt(int sock, int speed, int clock)
145{
146 uint32_t val;
147
148 val = ((pxa2xx_mcxx_setup(speed, clock)
149 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
150 | ((pxa2xx_mcxx_asst(speed, clock)
151 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
152 | ((pxa2xx_mcxx_hold(speed, clock)
153 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
154
155
156 return val;
157}
158
159static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
160{
161 unsigned long clk = clk_get_rate(skt->clk) / 10000;
162 struct soc_pcmcia_timing timing;
163 int sock = skt->nr;
164
165 soc_common_pcmcia_get_timing(skt, &timing);
166
167 pxa_smemc_set_pcmcia_timing(sock,
168 pxa2xx_pcmcia_mcmem(sock, timing.mem, clk),
169 pxa2xx_pcmcia_mcatt(sock, timing.attr, clk),
170 pxa2xx_pcmcia_mcio(sock, timing.io, clk));
171
172 return 0;
173}
174
175#ifdef CONFIG_CPU_FREQ
176
177static int
178pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
179 unsigned long val,
180 struct cpufreq_freqs *freqs)
181{
182 switch (val) {
183 case CPUFREQ_PRECHANGE:
184 if (freqs->new > freqs->old) {
185 debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
186 "pre-updating\n",
187 freqs->new / 1000, (freqs->new / 100) % 10,
188 freqs->old / 1000, (freqs->old / 100) % 10);
189 pxa2xx_pcmcia_set_timing(skt);
190 }
191 break;
192
193 case CPUFREQ_POSTCHANGE:
194 if (freqs->new < freqs->old) {
195 debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
196 "post-updating\n",
197 freqs->new / 1000, (freqs->new / 100) % 10,
198 freqs->old / 1000, (freqs->old / 100) % 10);
199 pxa2xx_pcmcia_set_timing(skt);
200 }
201 break;
202 }
203 return 0;
204}
205#endif
206
207void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
208{
209 pxa_smemc_set_pcmcia_socket(1);
210}
211EXPORT_SYMBOL(pxa2xx_configure_sockets);
212
213static const char *skt_names[] = {
214 "PCMCIA socket 0",
215 "PCMCIA socket 1",
216};
217
218#define SKT_DEV_INFO_SIZE(n) \
219 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
220
221int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
222{
223 skt->res_skt.start = _PCMCIA(skt->nr);
224 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
225 skt->res_skt.name = skt_names[skt->nr];
226 skt->res_skt.flags = IORESOURCE_MEM;
227
228 skt->res_io.start = _PCMCIAIO(skt->nr);
229 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
230 skt->res_io.name = "io";
231 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
232
233 skt->res_mem.start = _PCMCIAMem(skt->nr);
234 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
235 skt->res_mem.name = "memory";
236 skt->res_mem.flags = IORESOURCE_MEM;
237
238 skt->res_attr.start = _PCMCIAAttr(skt->nr);
239 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
240 skt->res_attr.name = "attribute";
241 skt->res_attr.flags = IORESOURCE_MEM;
242
243 return soc_pcmcia_add_one(skt);
244}
245EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
246
247void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
248{
249 /* Provide our PXA2xx specific timing routines. */
250 ops->set_timing = pxa2xx_pcmcia_set_timing;
251#ifdef CONFIG_CPU_FREQ
252 ops->frequency_change = pxa2xx_pcmcia_frequency_change;
253#endif
254}
255EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
256
257static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
258{
259 int i, ret = 0;
260 struct pcmcia_low_level *ops;
261 struct skt_dev_info *sinfo;
262 struct soc_pcmcia_socket *skt;
263 struct clk *clk;
264
265 ops = (struct pcmcia_low_level *)dev->dev.platform_data;
266 if (!ops) {
267 ret = -ENODEV;
268 goto err0;
269 }
270
271 if (cpu_is_pxa320() && ops->nr > 1) {
272 dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
273 ret = -EINVAL;
274 goto err0;
275 }
276
277 clk = devm_clk_get(&dev->dev, NULL);
278 if (IS_ERR(clk))
279 return -ENODEV;
280
281 pxa2xx_drv_pcmcia_ops(ops);
282
283 sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
284 GFP_KERNEL);
285 if (!sinfo)
286 return -ENOMEM;
287
288 sinfo->nskt = ops->nr;
289
290 /* Initialize processor specific parameters */
291 for (i = 0; i < ops->nr; i++) {
292 skt = &sinfo->skt[i];
293
294 skt->nr = ops->first + i;
295 skt->clk = clk;
296 soc_pcmcia_init_one(skt, ops, &dev->dev);
297
298 ret = pxa2xx_drv_pcmcia_add_one(skt);
299 if (ret)
300 goto err1;
301 }
302
303 pxa2xx_configure_sockets(&dev->dev, ops);
304 dev_set_drvdata(&dev->dev, sinfo);
305
306 return 0;
307
308err1:
309 while (--i >= 0)
310 soc_pcmcia_remove_one(&sinfo->skt[i]);
311
312err0:
313 return ret;
314}
315
316static void pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
317{
318 struct skt_dev_info *sinfo = platform_get_drvdata(dev);
319 int i;
320
321 for (i = 0; i < sinfo->nskt; i++)
322 soc_pcmcia_remove_one(&sinfo->skt[i]);
323}
324
325static int pxa2xx_drv_pcmcia_resume(struct device *dev)
326{
327 struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
328
329 pxa2xx_configure_sockets(dev, ops);
330 return 0;
331}
332
333static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
334 .resume = pxa2xx_drv_pcmcia_resume,
335};
336
337static struct platform_driver pxa2xx_pcmcia_driver = {
338 .probe = pxa2xx_drv_pcmcia_probe,
339 .remove_new = pxa2xx_drv_pcmcia_remove,
340 .driver = {
341 .name = "pxa2xx-pcmcia",
342 .pm = &pxa2xx_drv_pcmcia_pm_ops,
343 },
344};
345
346static int __init pxa2xx_pcmcia_init(void)
347{
348 return platform_driver_register(&pxa2xx_pcmcia_driver);
349}
350
351static void __exit pxa2xx_pcmcia_exit(void)
352{
353 platform_driver_unregister(&pxa2xx_pcmcia_driver);
354}
355
356fs_initcall(pxa2xx_pcmcia_init);
357module_exit(pxa2xx_pcmcia_exit);
358
359MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
360MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
361MODULE_LICENSE("GPL");
362MODULE_ALIAS("platform:pxa2xx-pcmcia");
1// SPDX-License-Identifier: GPL-2.0-only
2/*======================================================================
3
4 Device driver for the PCMCIA control functionality of PXA2xx
5 microprocessors.
6
7
8 (c) Ian Molton (spyro@f2s.com) 2003
9 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
10
11 derived from sa11xx_base.c
12
13 Portions created by John G. Dorsey are
14 Copyright (C) 1999 John G. Dorsey.
15
16 ======================================================================*/
17
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/ioport.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/platform_device.h>
26
27#include <mach/hardware.h>
28#include <mach/smemc.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <mach/pxa2xx-regs.h>
32#include <asm/mach-types.h>
33
34#include <pcmcia/ss.h>
35#include <pcmcia/cistpl.h>
36
37#include "soc_common.h"
38#include "pxa2xx_base.h"
39
40/*
41 * Personal Computer Memory Card International Association (PCMCIA) sockets
42 */
43
44#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
45#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
46#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
47#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
48#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
49
50#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
51#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
52#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
53#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
54
55#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
56#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
57#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
58#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
59
60#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
61 (0x20000000 + (Nb) * PCMCIASp)
62#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
63#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
64 (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
65#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
66 (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
67
68#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
69#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
70#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
71#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
72
73#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
74#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
75#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
76#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
77
78
79#define MCXX_SETUP_MASK (0x7f)
80#define MCXX_ASST_MASK (0x1f)
81#define MCXX_HOLD_MASK (0x3f)
82#define MCXX_SETUP_SHIFT (0)
83#define MCXX_ASST_SHIFT (7)
84#define MCXX_HOLD_SHIFT (14)
85
86static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
87 u_int mem_clk_10khz)
88{
89 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
90 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
91}
92
93static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
94 u_int mem_clk_10khz)
95{
96 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
97 return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
98}
99
100static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
101 u_int mem_clk_10khz)
102{
103 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
104 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
105}
106
107/* This function returns the (approximate) command assertion period, in
108 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
109 */
110static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
111 u_int pcmcia_mcxx_asst)
112{
113 return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
114}
115
116static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
117{
118 uint32_t val;
119
120 val = ((pxa2xx_mcxx_setup(speed, clock)
121 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
122 | ((pxa2xx_mcxx_asst(speed, clock)
123 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
124 | ((pxa2xx_mcxx_hold(speed, clock)
125 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
126
127 __raw_writel(val, MCMEM(sock));
128
129 return 0;
130}
131
132static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
133{
134 uint32_t val;
135
136 val = ((pxa2xx_mcxx_setup(speed, clock)
137 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
138 | ((pxa2xx_mcxx_asst(speed, clock)
139 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
140 | ((pxa2xx_mcxx_hold(speed, clock)
141 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
142
143 __raw_writel(val, MCIO(sock));
144
145 return 0;
146}
147
148static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
149{
150 uint32_t val;
151
152 val = ((pxa2xx_mcxx_setup(speed, clock)
153 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
154 | ((pxa2xx_mcxx_asst(speed, clock)
155 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
156 | ((pxa2xx_mcxx_hold(speed, clock)
157 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
158
159 __raw_writel(val, MCATT(sock));
160
161 return 0;
162}
163
164static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
165{
166 struct soc_pcmcia_timing timing;
167 int sock = skt->nr;
168
169 soc_common_pcmcia_get_timing(skt, &timing);
170
171 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
172 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
173 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
174
175 return 0;
176}
177
178static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
179{
180 unsigned long clk = clk_get_rate(skt->clk);
181 return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
182}
183
184#ifdef CONFIG_CPU_FREQ
185
186static int
187pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
188 unsigned long val,
189 struct cpufreq_freqs *freqs)
190{
191 switch (val) {
192 case CPUFREQ_PRECHANGE:
193 if (freqs->new > freqs->old) {
194 debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
195 "pre-updating\n",
196 freqs->new / 1000, (freqs->new / 100) % 10,
197 freqs->old / 1000, (freqs->old / 100) % 10);
198 pxa2xx_pcmcia_set_timing(skt);
199 }
200 break;
201
202 case CPUFREQ_POSTCHANGE:
203 if (freqs->new < freqs->old) {
204 debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
205 "post-updating\n",
206 freqs->new / 1000, (freqs->new / 100) % 10,
207 freqs->old / 1000, (freqs->old / 100) % 10);
208 pxa2xx_pcmcia_set_timing(skt);
209 }
210 break;
211 }
212 return 0;
213}
214#endif
215
216void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
217{
218 /*
219 * We have at least one socket, so set MECR:CIT
220 * (Card Is There)
221 */
222 uint32_t mecr = MECR_CIT;
223
224 /* Set MECR:NOS (Number Of Sockets) */
225 if ((ops->first + ops->nr) > 1 ||
226 machine_is_viper() || machine_is_arcom_zeus())
227 mecr |= MECR_NOS;
228
229 __raw_writel(mecr, MECR);
230}
231EXPORT_SYMBOL(pxa2xx_configure_sockets);
232
233static const char *skt_names[] = {
234 "PCMCIA socket 0",
235 "PCMCIA socket 1",
236};
237
238#define SKT_DEV_INFO_SIZE(n) \
239 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
240
241int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
242{
243 skt->res_skt.start = _PCMCIA(skt->nr);
244 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
245 skt->res_skt.name = skt_names[skt->nr];
246 skt->res_skt.flags = IORESOURCE_MEM;
247
248 skt->res_io.start = _PCMCIAIO(skt->nr);
249 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
250 skt->res_io.name = "io";
251 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
252
253 skt->res_mem.start = _PCMCIAMem(skt->nr);
254 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
255 skt->res_mem.name = "memory";
256 skt->res_mem.flags = IORESOURCE_MEM;
257
258 skt->res_attr.start = _PCMCIAAttr(skt->nr);
259 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
260 skt->res_attr.name = "attribute";
261 skt->res_attr.flags = IORESOURCE_MEM;
262
263 return soc_pcmcia_add_one(skt);
264}
265EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
266
267void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
268{
269 /* Provide our PXA2xx specific timing routines. */
270 ops->set_timing = pxa2xx_pcmcia_set_timing;
271#ifdef CONFIG_CPU_FREQ
272 ops->frequency_change = pxa2xx_pcmcia_frequency_change;
273#endif
274}
275EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
276
277static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
278{
279 int i, ret = 0;
280 struct pcmcia_low_level *ops;
281 struct skt_dev_info *sinfo;
282 struct soc_pcmcia_socket *skt;
283 struct clk *clk;
284
285 ops = (struct pcmcia_low_level *)dev->dev.platform_data;
286 if (!ops) {
287 ret = -ENODEV;
288 goto err0;
289 }
290
291 if (cpu_is_pxa320() && ops->nr > 1) {
292 dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
293 ret = -EINVAL;
294 goto err0;
295 }
296
297 clk = devm_clk_get(&dev->dev, NULL);
298 if (IS_ERR(clk))
299 return -ENODEV;
300
301 pxa2xx_drv_pcmcia_ops(ops);
302
303 sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
304 GFP_KERNEL);
305 if (!sinfo)
306 return -ENOMEM;
307
308 sinfo->nskt = ops->nr;
309
310 /* Initialize processor specific parameters */
311 for (i = 0; i < ops->nr; i++) {
312 skt = &sinfo->skt[i];
313
314 skt->nr = ops->first + i;
315 skt->clk = clk;
316 soc_pcmcia_init_one(skt, ops, &dev->dev);
317
318 ret = pxa2xx_drv_pcmcia_add_one(skt);
319 if (ret)
320 goto err1;
321 }
322
323 pxa2xx_configure_sockets(&dev->dev, ops);
324 dev_set_drvdata(&dev->dev, sinfo);
325
326 return 0;
327
328err1:
329 while (--i >= 0)
330 soc_pcmcia_remove_one(&sinfo->skt[i]);
331
332err0:
333 return ret;
334}
335
336static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
337{
338 struct skt_dev_info *sinfo = platform_get_drvdata(dev);
339 int i;
340
341 for (i = 0; i < sinfo->nskt; i++)
342 soc_pcmcia_remove_one(&sinfo->skt[i]);
343
344 return 0;
345}
346
347static int pxa2xx_drv_pcmcia_resume(struct device *dev)
348{
349 struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
350
351 pxa2xx_configure_sockets(dev, ops);
352 return 0;
353}
354
355static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
356 .resume = pxa2xx_drv_pcmcia_resume,
357};
358
359static struct platform_driver pxa2xx_pcmcia_driver = {
360 .probe = pxa2xx_drv_pcmcia_probe,
361 .remove = pxa2xx_drv_pcmcia_remove,
362 .driver = {
363 .name = "pxa2xx-pcmcia",
364 .pm = &pxa2xx_drv_pcmcia_pm_ops,
365 },
366};
367
368static int __init pxa2xx_pcmcia_init(void)
369{
370 return platform_driver_register(&pxa2xx_pcmcia_driver);
371}
372
373static void __exit pxa2xx_pcmcia_exit(void)
374{
375 platform_driver_unregister(&pxa2xx_pcmcia_driver);
376}
377
378fs_initcall(pxa2xx_pcmcia_init);
379module_exit(pxa2xx_pcmcia_exit);
380
381MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
382MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
383MODULE_LICENSE("GPL");
384MODULE_ALIAS("platform:pxa2xx-pcmcia");