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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/mmc/sdio_func.h>
9#include <linux/mmc/sdio_ids.h>
10#include <linux/mmc/host.h>
11#include <linux/mmc/sdio.h>
12#include <linux/of_irq.h>
13
14#include "netdev.h"
15#include "cfg80211.h"
16
17#define SDIO_MODALIAS "wilc1000_sdio"
18
19static const struct sdio_device_id wilc_sdio_ids[] = {
20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) },
21 { },
22};
23MODULE_DEVICE_TABLE(sdio, wilc_sdio_ids);
24
25#define WILC_SDIO_BLOCK_SIZE 512
26
27struct wilc_sdio {
28 bool irq_gpio;
29 u32 block_size;
30 bool isinit;
31 u8 *cmd53_buf;
32};
33
34struct sdio_cmd52 {
35 u32 read_write: 1;
36 u32 function: 3;
37 u32 raw: 1;
38 u32 address: 17;
39 u32 data: 8;
40};
41
42struct sdio_cmd53 {
43 u32 read_write: 1;
44 u32 function: 3;
45 u32 block_mode: 1;
46 u32 increment: 1;
47 u32 address: 17;
48 u32 count: 9;
49 u8 *buffer;
50 u32 block_size;
51 bool use_global_buf;
52};
53
54static const struct wilc_hif_func wilc_hif_sdio;
55
56static void wilc_sdio_interrupt(struct sdio_func *func)
57{
58 sdio_release_host(func);
59 wilc_handle_isr(sdio_get_drvdata(func));
60 sdio_claim_host(func);
61}
62
63static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd)
64{
65 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
66 int ret;
67 u8 data;
68
69 sdio_claim_host(func);
70
71 func->num = cmd->function;
72 if (cmd->read_write) { /* write */
73 if (cmd->raw) {
74 sdio_writeb(func, cmd->data, cmd->address, &ret);
75 data = sdio_readb(func, cmd->address, &ret);
76 cmd->data = data;
77 } else {
78 sdio_writeb(func, cmd->data, cmd->address, &ret);
79 }
80 } else { /* read */
81 data = sdio_readb(func, cmd->address, &ret);
82 cmd->data = data;
83 }
84
85 sdio_release_host(func);
86
87 if (ret)
88 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
89 return ret;
90}
91
92static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd)
93{
94 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
95 int size, ret;
96 struct wilc_sdio *sdio_priv = wilc->bus_data;
97 u8 *buf = cmd->buffer;
98
99 sdio_claim_host(func);
100
101 func->num = cmd->function;
102 func->cur_blksize = cmd->block_size;
103 if (cmd->block_mode)
104 size = cmd->count * cmd->block_size;
105 else
106 size = cmd->count;
107
108 if (cmd->use_global_buf) {
109 if (size > sizeof(u32)) {
110 ret = -EINVAL;
111 goto out;
112 }
113 buf = sdio_priv->cmd53_buf;
114 }
115
116 if (cmd->read_write) { /* write */
117 if (cmd->use_global_buf)
118 memcpy(buf, cmd->buffer, size);
119
120 ret = sdio_memcpy_toio(func, cmd->address, buf, size);
121 } else { /* read */
122 ret = sdio_memcpy_fromio(func, buf, cmd->address, size);
123
124 if (cmd->use_global_buf)
125 memcpy(cmd->buffer, buf, size);
126 }
127out:
128 sdio_release_host(func);
129
130 if (ret)
131 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
132
133 return ret;
134}
135
136static int wilc_sdio_probe(struct sdio_func *func,
137 const struct sdio_device_id *id)
138{
139 struct wilc *wilc;
140 int ret;
141 struct wilc_sdio *sdio_priv;
142
143 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL);
144 if (!sdio_priv)
145 return -ENOMEM;
146
147 sdio_priv->cmd53_buf = kzalloc(sizeof(u32), GFP_KERNEL);
148 if (!sdio_priv->cmd53_buf) {
149 ret = -ENOMEM;
150 goto free;
151 }
152
153 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO,
154 &wilc_hif_sdio);
155 if (ret)
156 goto free;
157
158 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) {
159 struct device_node *np = func->card->dev.of_node;
160 int irq_num = of_irq_get(np, 0);
161
162 if (irq_num > 0) {
163 wilc->dev_irq_num = irq_num;
164 sdio_priv->irq_gpio = true;
165 }
166 }
167
168 sdio_set_drvdata(func, wilc);
169 wilc->bus_data = sdio_priv;
170 wilc->dev = &func->dev;
171
172 wilc->rtc_clk = devm_clk_get_optional(&func->card->dev, "rtc");
173 if (IS_ERR(wilc->rtc_clk)) {
174 ret = PTR_ERR(wilc->rtc_clk);
175 goto dispose_irq;
176 }
177 clk_prepare_enable(wilc->rtc_clk);
178
179 dev_info(&func->dev, "Driver Initializing success\n");
180 return 0;
181
182dispose_irq:
183 irq_dispose_mapping(wilc->dev_irq_num);
184 wilc_netdev_cleanup(wilc);
185free:
186 kfree(sdio_priv->cmd53_buf);
187 kfree(sdio_priv);
188 return ret;
189}
190
191static void wilc_sdio_remove(struct sdio_func *func)
192{
193 struct wilc *wilc = sdio_get_drvdata(func);
194 struct wilc_sdio *sdio_priv = wilc->bus_data;
195
196 clk_disable_unprepare(wilc->rtc_clk);
197 wilc_netdev_cleanup(wilc);
198 kfree(sdio_priv->cmd53_buf);
199 kfree(sdio_priv);
200}
201
202static int wilc_sdio_reset(struct wilc *wilc)
203{
204 struct sdio_cmd52 cmd;
205 int ret;
206 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
207
208 cmd.read_write = 1;
209 cmd.function = 0;
210 cmd.raw = 0;
211 cmd.address = SDIO_CCCR_ABORT;
212 cmd.data = WILC_SDIO_CCCR_ABORT_RESET;
213 ret = wilc_sdio_cmd52(wilc, &cmd);
214 if (ret) {
215 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
216 return ret;
217 }
218 return 0;
219}
220
221static bool wilc_sdio_is_init(struct wilc *wilc)
222{
223 struct wilc_sdio *sdio_priv = wilc->bus_data;
224
225 return sdio_priv->isinit;
226}
227
228static int wilc_sdio_suspend(struct device *dev)
229{
230 struct sdio_func *func = dev_to_sdio_func(dev);
231 struct wilc *wilc = sdio_get_drvdata(func);
232 int ret;
233
234 dev_info(dev, "sdio suspend\n");
235 chip_wakeup(wilc);
236
237 if (!IS_ERR(wilc->rtc_clk))
238 clk_disable_unprepare(wilc->rtc_clk);
239
240 if (wilc->suspend_event) {
241 host_sleep_notify(wilc);
242 chip_allow_sleep(wilc);
243 }
244
245 ret = wilc_sdio_reset(wilc);
246 if (ret) {
247 dev_err(&func->dev, "Fail reset sdio\n");
248 return ret;
249 }
250 sdio_claim_host(func);
251
252 return 0;
253}
254
255static int wilc_sdio_enable_interrupt(struct wilc *dev)
256{
257 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
258 int ret = 0;
259
260 sdio_claim_host(func);
261 ret = sdio_claim_irq(func, wilc_sdio_interrupt);
262 sdio_release_host(func);
263
264 if (ret < 0) {
265 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret);
266 ret = -EIO;
267 }
268 return ret;
269}
270
271static void wilc_sdio_disable_interrupt(struct wilc *dev)
272{
273 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
274 int ret;
275
276 sdio_claim_host(func);
277 ret = sdio_release_irq(func);
278 if (ret < 0)
279 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret);
280 sdio_release_host(func);
281}
282
283/********************************************
284 *
285 * Function 0
286 *
287 ********************************************/
288
289static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
290{
291 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
292 struct sdio_cmd52 cmd;
293 int ret;
294
295 /**
296 * Review: BIG ENDIAN
297 **/
298 cmd.read_write = 1;
299 cmd.function = 0;
300 cmd.raw = 0;
301 cmd.address = WILC_SDIO_FBR_CSA_REG;
302 cmd.data = (u8)adr;
303 ret = wilc_sdio_cmd52(wilc, &cmd);
304 if (ret) {
305 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
306 cmd.address);
307 return ret;
308 }
309
310 cmd.address = WILC_SDIO_FBR_CSA_REG + 1;
311 cmd.data = (u8)(adr >> 8);
312 ret = wilc_sdio_cmd52(wilc, &cmd);
313 if (ret) {
314 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
315 cmd.address);
316 return ret;
317 }
318
319 cmd.address = WILC_SDIO_FBR_CSA_REG + 2;
320 cmd.data = (u8)(adr >> 16);
321 ret = wilc_sdio_cmd52(wilc, &cmd);
322 if (ret) {
323 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
324 cmd.address);
325 return ret;
326 }
327
328 return 0;
329}
330
331static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num,
332 u32 block_size)
333{
334 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
335 struct sdio_cmd52 cmd;
336 int ret;
337
338 cmd.read_write = 1;
339 cmd.function = 0;
340 cmd.raw = 0;
341 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE;
342 cmd.data = (u8)block_size;
343 ret = wilc_sdio_cmd52(wilc, &cmd);
344 if (ret) {
345 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
346 cmd.address);
347 return ret;
348 }
349
350 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1;
351 cmd.data = (u8)(block_size >> 8);
352 ret = wilc_sdio_cmd52(wilc, &cmd);
353 if (ret) {
354 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
355 cmd.address);
356 return ret;
357 }
358
359 return 0;
360}
361
362/********************************************
363 *
364 * Sdio interfaces
365 *
366 ********************************************/
367static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
368{
369 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
370 struct wilc_sdio *sdio_priv = wilc->bus_data;
371 int ret;
372
373 cpu_to_le32s(&data);
374
375 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
376 struct sdio_cmd52 cmd;
377
378 cmd.read_write = 1;
379 cmd.function = 0;
380 cmd.raw = 0;
381 cmd.address = addr;
382 cmd.data = data;
383 ret = wilc_sdio_cmd52(wilc, &cmd);
384 if (ret)
385 dev_err(&func->dev,
386 "Failed cmd 52, read reg (%08x) ...\n", addr);
387 } else {
388 struct sdio_cmd53 cmd;
389
390 /**
391 * set the AHB address
392 **/
393 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
394 if (ret)
395 return ret;
396
397 cmd.read_write = 1;
398 cmd.function = 0;
399 cmd.address = WILC_SDIO_FBR_DATA_REG;
400 cmd.block_mode = 0;
401 cmd.increment = 1;
402 cmd.count = sizeof(u32);
403 cmd.buffer = (u8 *)&data;
404 cmd.use_global_buf = true;
405 cmd.block_size = sdio_priv->block_size;
406 ret = wilc_sdio_cmd53(wilc, &cmd);
407 if (ret)
408 dev_err(&func->dev,
409 "Failed cmd53, write reg (%08x)...\n", addr);
410 }
411
412 return ret;
413}
414
415static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
416{
417 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
418 struct wilc_sdio *sdio_priv = wilc->bus_data;
419 u32 block_size = sdio_priv->block_size;
420 struct sdio_cmd53 cmd;
421 int nblk, nleft, ret;
422
423 cmd.read_write = 1;
424 if (addr > 0) {
425 /**
426 * func 0 access
427 **/
428 cmd.function = 0;
429 cmd.address = WILC_SDIO_FBR_DATA_REG;
430 } else {
431 /**
432 * func 1 access
433 **/
434 cmd.function = 1;
435 cmd.address = WILC_SDIO_F1_DATA_REG;
436 }
437
438 size = ALIGN(size, 4);
439 nblk = size / block_size;
440 nleft = size % block_size;
441
442 cmd.use_global_buf = false;
443 if (nblk > 0) {
444 cmd.block_mode = 1;
445 cmd.increment = 1;
446 cmd.count = nblk;
447 cmd.buffer = buf;
448 cmd.block_size = block_size;
449 if (addr > 0) {
450 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
451 if (ret)
452 return ret;
453 }
454 ret = wilc_sdio_cmd53(wilc, &cmd);
455 if (ret) {
456 dev_err(&func->dev,
457 "Failed cmd53 [%x], block send...\n", addr);
458 return ret;
459 }
460 if (addr > 0)
461 addr += nblk * block_size;
462 buf += nblk * block_size;
463 }
464
465 if (nleft > 0) {
466 cmd.block_mode = 0;
467 cmd.increment = 1;
468 cmd.count = nleft;
469 cmd.buffer = buf;
470
471 cmd.block_size = block_size;
472
473 if (addr > 0) {
474 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
475 if (ret)
476 return ret;
477 }
478 ret = wilc_sdio_cmd53(wilc, &cmd);
479 if (ret) {
480 dev_err(&func->dev,
481 "Failed cmd53 [%x], bytes send...\n", addr);
482 return ret;
483 }
484 }
485
486 return 0;
487}
488
489static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
490{
491 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
492 struct wilc_sdio *sdio_priv = wilc->bus_data;
493 int ret;
494
495 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
496 struct sdio_cmd52 cmd;
497
498 cmd.read_write = 0;
499 cmd.function = 0;
500 cmd.raw = 0;
501 cmd.address = addr;
502 ret = wilc_sdio_cmd52(wilc, &cmd);
503 if (ret) {
504 dev_err(&func->dev,
505 "Failed cmd 52, read reg (%08x) ...\n", addr);
506 return ret;
507 }
508 *data = cmd.data;
509 } else {
510 struct sdio_cmd53 cmd;
511
512 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
513 if (ret)
514 return ret;
515
516 cmd.read_write = 0;
517 cmd.function = 0;
518 cmd.address = WILC_SDIO_FBR_DATA_REG;
519 cmd.block_mode = 0;
520 cmd.increment = 1;
521 cmd.count = sizeof(u32);
522 cmd.buffer = (u8 *)data;
523 cmd.use_global_buf = true;
524
525 cmd.block_size = sdio_priv->block_size;
526 ret = wilc_sdio_cmd53(wilc, &cmd);
527 if (ret) {
528 dev_err(&func->dev,
529 "Failed cmd53, read reg (%08x)...\n", addr);
530 return ret;
531 }
532 }
533
534 le32_to_cpus(data);
535 return 0;
536}
537
538static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
539{
540 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
541 struct wilc_sdio *sdio_priv = wilc->bus_data;
542 u32 block_size = sdio_priv->block_size;
543 struct sdio_cmd53 cmd;
544 int nblk, nleft, ret;
545
546 cmd.read_write = 0;
547 if (addr > 0) {
548 /**
549 * func 0 access
550 **/
551 cmd.function = 0;
552 cmd.address = WILC_SDIO_FBR_DATA_REG;
553 } else {
554 /**
555 * func 1 access
556 **/
557 cmd.function = 1;
558 cmd.address = WILC_SDIO_F1_DATA_REG;
559 }
560
561 size = ALIGN(size, 4);
562 nblk = size / block_size;
563 nleft = size % block_size;
564
565 cmd.use_global_buf = false;
566 if (nblk > 0) {
567 cmd.block_mode = 1;
568 cmd.increment = 1;
569 cmd.count = nblk;
570 cmd.buffer = buf;
571 cmd.block_size = block_size;
572 if (addr > 0) {
573 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
574 if (ret)
575 return ret;
576 }
577 ret = wilc_sdio_cmd53(wilc, &cmd);
578 if (ret) {
579 dev_err(&func->dev,
580 "Failed cmd53 [%x], block read...\n", addr);
581 return ret;
582 }
583 if (addr > 0)
584 addr += nblk * block_size;
585 buf += nblk * block_size;
586 } /* if (nblk > 0) */
587
588 if (nleft > 0) {
589 cmd.block_mode = 0;
590 cmd.increment = 1;
591 cmd.count = nleft;
592 cmd.buffer = buf;
593
594 cmd.block_size = block_size;
595
596 if (addr > 0) {
597 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
598 if (ret)
599 return ret;
600 }
601 ret = wilc_sdio_cmd53(wilc, &cmd);
602 if (ret) {
603 dev_err(&func->dev,
604 "Failed cmd53 [%x], bytes read...\n", addr);
605 return ret;
606 }
607 }
608
609 return 0;
610}
611
612/********************************************
613 *
614 * Bus interfaces
615 *
616 ********************************************/
617
618static int wilc_sdio_deinit(struct wilc *wilc)
619{
620 struct wilc_sdio *sdio_priv = wilc->bus_data;
621
622 sdio_priv->isinit = false;
623 return 0;
624}
625
626static int wilc_sdio_init(struct wilc *wilc, bool resume)
627{
628 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
629 struct wilc_sdio *sdio_priv = wilc->bus_data;
630 struct sdio_cmd52 cmd;
631 int loop, ret;
632 u32 chipid;
633
634 /**
635 * function 0 csa enable
636 **/
637 cmd.read_write = 1;
638 cmd.function = 0;
639 cmd.raw = 1;
640 cmd.address = SDIO_FBR_BASE(1);
641 cmd.data = SDIO_FBR_ENABLE_CSA;
642 ret = wilc_sdio_cmd52(wilc, &cmd);
643 if (ret) {
644 dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
645 return ret;
646 }
647
648 /**
649 * function 0 block size
650 **/
651 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE);
652 if (ret) {
653 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n");
654 return ret;
655 }
656 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE;
657
658 /**
659 * enable func1 IO
660 **/
661 cmd.read_write = 1;
662 cmd.function = 0;
663 cmd.raw = 1;
664 cmd.address = SDIO_CCCR_IOEx;
665 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1;
666 ret = wilc_sdio_cmd52(wilc, &cmd);
667 if (ret) {
668 dev_err(&func->dev,
669 "Fail cmd 52, set IOE register...\n");
670 return ret;
671 }
672
673 /**
674 * make sure func 1 is up
675 **/
676 cmd.read_write = 0;
677 cmd.function = 0;
678 cmd.raw = 0;
679 cmd.address = SDIO_CCCR_IORx;
680 loop = 3;
681 do {
682 cmd.data = 0;
683 ret = wilc_sdio_cmd52(wilc, &cmd);
684 if (ret) {
685 dev_err(&func->dev,
686 "Fail cmd 52, get IOR register...\n");
687 return ret;
688 }
689 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1)
690 break;
691 } while (loop--);
692
693 if (loop <= 0) {
694 dev_err(&func->dev, "Fail func 1 is not ready...\n");
695 return -EINVAL;
696 }
697
698 /**
699 * func 1 is ready, set func 1 block size
700 **/
701 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE);
702 if (ret) {
703 dev_err(&func->dev, "Fail set func 1 block size...\n");
704 return ret;
705 }
706
707 /**
708 * func 1 interrupt enable
709 **/
710 cmd.read_write = 1;
711 cmd.function = 0;
712 cmd.raw = 1;
713 cmd.address = SDIO_CCCR_IENx;
714 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1;
715 ret = wilc_sdio_cmd52(wilc, &cmd);
716 if (ret) {
717 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
718 return ret;
719 }
720
721 /**
722 * make sure can read back chip id correctly
723 **/
724 if (!resume) {
725 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid);
726 if (ret) {
727 dev_err(&func->dev, "Fail cmd read chip id...\n");
728 return ret;
729 }
730 dev_err(&func->dev, "chipid (%08x)\n", chipid);
731 }
732
733 sdio_priv->isinit = true;
734 return 0;
735}
736
737static int wilc_sdio_read_size(struct wilc *wilc, u32 *size)
738{
739 u32 tmp;
740 struct sdio_cmd52 cmd;
741
742 /**
743 * Read DMA count in words
744 **/
745 cmd.read_write = 0;
746 cmd.function = 0;
747 cmd.raw = 0;
748 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG;
749 cmd.data = 0;
750 wilc_sdio_cmd52(wilc, &cmd);
751 tmp = cmd.data;
752
753 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1;
754 cmd.data = 0;
755 wilc_sdio_cmd52(wilc, &cmd);
756 tmp |= (cmd.data << 8);
757
758 *size = tmp;
759 return 0;
760}
761
762static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
763{
764 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
765 struct wilc_sdio *sdio_priv = wilc->bus_data;
766 u32 tmp;
767 u8 irq_flags;
768 struct sdio_cmd52 cmd;
769
770 wilc_sdio_read_size(wilc, &tmp);
771
772 /**
773 * Read IRQ flags
774 **/
775 if (!sdio_priv->irq_gpio) {
776 cmd.function = 1;
777 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG;
778 } else {
779 cmd.function = 0;
780 cmd.address = WILC_SDIO_IRQ_FLAG_REG;
781 }
782 cmd.raw = 0;
783 cmd.read_write = 0;
784 cmd.data = 0;
785 wilc_sdio_cmd52(wilc, &cmd);
786 irq_flags = cmd.data;
787 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data);
788
789 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags))
790 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n",
791 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags));
792
793 *int_status = tmp;
794
795 return 0;
796}
797
798static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
799{
800 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
801 struct wilc_sdio *sdio_priv = wilc->bus_data;
802 int ret;
803 u32 reg = 0;
804
805 if (sdio_priv->irq_gpio)
806 reg = val & (BIT(MAX_NUM_INT) - 1);
807
808 /* select VMM table 0 */
809 if (val & SEL_VMM_TBL0)
810 reg |= BIT(5);
811 /* select VMM table 1 */
812 if (val & SEL_VMM_TBL1)
813 reg |= BIT(6);
814 /* enable VMM */
815 if (val & EN_VMM)
816 reg |= BIT(7);
817 if (reg) {
818 struct sdio_cmd52 cmd;
819
820 cmd.read_write = 1;
821 cmd.function = 0;
822 cmd.raw = 0;
823 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
824 cmd.data = reg;
825
826 ret = wilc_sdio_cmd52(wilc, &cmd);
827 if (ret) {
828 dev_err(&func->dev,
829 "Failed cmd52, set (%02x) data (%d) ...\n",
830 cmd.address, __LINE__);
831 return ret;
832 }
833 }
834 return 0;
835}
836
837static int wilc_sdio_sync_ext(struct wilc *wilc, int nint)
838{
839 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
840 struct wilc_sdio *sdio_priv = wilc->bus_data;
841 u32 reg;
842
843 if (nint > MAX_NUM_INT) {
844 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint);
845 return -EINVAL;
846 }
847
848 /**
849 * Disable power sequencer
850 **/
851 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) {
852 dev_err(&func->dev, "Failed read misc reg...\n");
853 return -EINVAL;
854 }
855
856 reg &= ~BIT(8);
857 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) {
858 dev_err(&func->dev, "Failed write misc reg...\n");
859 return -EINVAL;
860 }
861
862 if (sdio_priv->irq_gpio) {
863 u32 reg;
864 int ret, i;
865
866 /**
867 * interrupt pin mux select
868 **/
869 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®);
870 if (ret) {
871 dev_err(&func->dev, "Failed read reg (%08x)...\n",
872 WILC_PIN_MUX_0);
873 return ret;
874 }
875 reg |= BIT(8);
876 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg);
877 if (ret) {
878 dev_err(&func->dev, "Failed write reg (%08x)...\n",
879 WILC_PIN_MUX_0);
880 return ret;
881 }
882
883 /**
884 * interrupt enable
885 **/
886 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®);
887 if (ret) {
888 dev_err(&func->dev, "Failed read reg (%08x)...\n",
889 WILC_INTR_ENABLE);
890 return ret;
891 }
892
893 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
894 reg |= BIT((27 + i));
895 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg);
896 if (ret) {
897 dev_err(&func->dev, "Failed write reg (%08x)...\n",
898 WILC_INTR_ENABLE);
899 return ret;
900 }
901 if (nint) {
902 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®);
903 if (ret) {
904 dev_err(&func->dev,
905 "Failed read reg (%08x)...\n",
906 WILC_INTR2_ENABLE);
907 return ret;
908 }
909
910 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
911 reg |= BIT(i);
912
913 ret = wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg);
914 if (ret) {
915 dev_err(&func->dev,
916 "Failed write reg (%08x)...\n",
917 WILC_INTR2_ENABLE);
918 return ret;
919 }
920 }
921 }
922 return 0;
923}
924
925/* Global sdio HIF function table */
926static const struct wilc_hif_func wilc_hif_sdio = {
927 .hif_init = wilc_sdio_init,
928 .hif_deinit = wilc_sdio_deinit,
929 .hif_read_reg = wilc_sdio_read_reg,
930 .hif_write_reg = wilc_sdio_write_reg,
931 .hif_block_rx = wilc_sdio_read,
932 .hif_block_tx = wilc_sdio_write,
933 .hif_read_int = wilc_sdio_read_int,
934 .hif_clear_int_ext = wilc_sdio_clear_int_ext,
935 .hif_read_size = wilc_sdio_read_size,
936 .hif_block_tx_ext = wilc_sdio_write,
937 .hif_block_rx_ext = wilc_sdio_read,
938 .hif_sync_ext = wilc_sdio_sync_ext,
939 .enable_interrupt = wilc_sdio_enable_interrupt,
940 .disable_interrupt = wilc_sdio_disable_interrupt,
941 .hif_reset = wilc_sdio_reset,
942 .hif_is_init = wilc_sdio_is_init,
943};
944
945static int wilc_sdio_resume(struct device *dev)
946{
947 struct sdio_func *func = dev_to_sdio_func(dev);
948 struct wilc *wilc = sdio_get_drvdata(func);
949
950 dev_info(dev, "sdio resume\n");
951 sdio_release_host(func);
952 chip_wakeup(wilc);
953 wilc_sdio_init(wilc, true);
954
955 if (wilc->suspend_event)
956 host_wakeup_notify(wilc);
957
958 chip_allow_sleep(wilc);
959
960 return 0;
961}
962
963static const struct of_device_id wilc_of_match[] = {
964 { .compatible = "microchip,wilc1000", },
965 { /* sentinel */ }
966};
967MODULE_DEVICE_TABLE(of, wilc_of_match);
968
969static const struct dev_pm_ops wilc_sdio_pm_ops = {
970 .suspend = wilc_sdio_suspend,
971 .resume = wilc_sdio_resume,
972};
973
974static struct sdio_driver wilc_sdio_driver = {
975 .name = SDIO_MODALIAS,
976 .id_table = wilc_sdio_ids,
977 .probe = wilc_sdio_probe,
978 .remove = wilc_sdio_remove,
979 .drv = {
980 .pm = &wilc_sdio_pm_ops,
981 .of_match_table = wilc_of_match,
982 }
983};
984module_driver(wilc_sdio_driver,
985 sdio_register_driver,
986 sdio_unregister_driver);
987MODULE_DESCRIPTION("Atmel WILC1000 SDIO wireless driver");
988MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/mmc/sdio_func.h>
9#include <linux/mmc/sdio_ids.h>
10#include <linux/mmc/host.h>
11#include <linux/mmc/sdio.h>
12#include <linux/of_irq.h>
13
14#include "netdev.h"
15#include "cfg80211.h"
16
17#define SDIO_MODALIAS "wilc1000_sdio"
18
19static const struct sdio_device_id wilc_sdio_ids[] = {
20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) },
21 { },
22};
23
24#define WILC_SDIO_BLOCK_SIZE 512
25
26struct wilc_sdio {
27 bool irq_gpio;
28 u32 block_size;
29 int has_thrpt_enh3;
30};
31
32struct sdio_cmd52 {
33 u32 read_write: 1;
34 u32 function: 3;
35 u32 raw: 1;
36 u32 address: 17;
37 u32 data: 8;
38};
39
40struct sdio_cmd53 {
41 u32 read_write: 1;
42 u32 function: 3;
43 u32 block_mode: 1;
44 u32 increment: 1;
45 u32 address: 17;
46 u32 count: 9;
47 u8 *buffer;
48 u32 block_size;
49};
50
51static const struct wilc_hif_func wilc_hif_sdio;
52
53static void wilc_sdio_interrupt(struct sdio_func *func)
54{
55 sdio_release_host(func);
56 wilc_handle_isr(sdio_get_drvdata(func));
57 sdio_claim_host(func);
58}
59
60static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd)
61{
62 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
63 int ret;
64 u8 data;
65
66 sdio_claim_host(func);
67
68 func->num = cmd->function;
69 if (cmd->read_write) { /* write */
70 if (cmd->raw) {
71 sdio_writeb(func, cmd->data, cmd->address, &ret);
72 data = sdio_readb(func, cmd->address, &ret);
73 cmd->data = data;
74 } else {
75 sdio_writeb(func, cmd->data, cmd->address, &ret);
76 }
77 } else { /* read */
78 data = sdio_readb(func, cmd->address, &ret);
79 cmd->data = data;
80 }
81
82 sdio_release_host(func);
83
84 if (ret)
85 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
86 return ret;
87}
88
89static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd)
90{
91 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
92 int size, ret;
93
94 sdio_claim_host(func);
95
96 func->num = cmd->function;
97 func->cur_blksize = cmd->block_size;
98 if (cmd->block_mode)
99 size = cmd->count * cmd->block_size;
100 else
101 size = cmd->count;
102
103 if (cmd->read_write) { /* write */
104 ret = sdio_memcpy_toio(func, cmd->address,
105 (void *)cmd->buffer, size);
106 } else { /* read */
107 ret = sdio_memcpy_fromio(func, (void *)cmd->buffer,
108 cmd->address, size);
109 }
110
111 sdio_release_host(func);
112
113 if (ret)
114 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
115
116 return ret;
117}
118
119static int wilc_sdio_probe(struct sdio_func *func,
120 const struct sdio_device_id *id)
121{
122 struct wilc *wilc;
123 int ret;
124 struct wilc_sdio *sdio_priv;
125
126 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL);
127 if (!sdio_priv)
128 return -ENOMEM;
129
130 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO,
131 &wilc_hif_sdio);
132 if (ret) {
133 kfree(sdio_priv);
134 return ret;
135 }
136
137 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) {
138 struct device_node *np = func->card->dev.of_node;
139 int irq_num = of_irq_get(np, 0);
140
141 if (irq_num > 0) {
142 wilc->dev_irq_num = irq_num;
143 sdio_priv->irq_gpio = true;
144 }
145 }
146
147 sdio_set_drvdata(func, wilc);
148 wilc->bus_data = sdio_priv;
149 wilc->dev = &func->dev;
150
151 wilc->rtc_clk = devm_clk_get(&func->card->dev, "rtc");
152 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
153 return -EPROBE_DEFER;
154 else if (!IS_ERR(wilc->rtc_clk))
155 clk_prepare_enable(wilc->rtc_clk);
156
157 dev_info(&func->dev, "Driver Initializing success\n");
158 return 0;
159}
160
161static void wilc_sdio_remove(struct sdio_func *func)
162{
163 struct wilc *wilc = sdio_get_drvdata(func);
164
165 if (!IS_ERR(wilc->rtc_clk))
166 clk_disable_unprepare(wilc->rtc_clk);
167
168 wilc_netdev_cleanup(wilc);
169}
170
171static int wilc_sdio_reset(struct wilc *wilc)
172{
173 struct sdio_cmd52 cmd;
174 int ret;
175 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
176
177 cmd.read_write = 1;
178 cmd.function = 0;
179 cmd.raw = 0;
180 cmd.address = SDIO_CCCR_ABORT;
181 cmd.data = WILC_SDIO_CCCR_ABORT_RESET;
182 ret = wilc_sdio_cmd52(wilc, &cmd);
183 if (ret) {
184 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
185 return ret;
186 }
187 return 0;
188}
189
190static int wilc_sdio_suspend(struct device *dev)
191{
192 struct sdio_func *func = dev_to_sdio_func(dev);
193 struct wilc *wilc = sdio_get_drvdata(func);
194 int ret;
195
196 dev_info(dev, "sdio suspend\n");
197 chip_wakeup(wilc);
198
199 if (!IS_ERR(wilc->rtc_clk))
200 clk_disable_unprepare(wilc->rtc_clk);
201
202 if (wilc->suspend_event) {
203 host_sleep_notify(wilc);
204 chip_allow_sleep(wilc);
205 }
206
207 ret = wilc_sdio_reset(wilc);
208 if (ret) {
209 dev_err(&func->dev, "Fail reset sdio\n");
210 return ret;
211 }
212 sdio_claim_host(func);
213
214 return 0;
215}
216
217static int wilc_sdio_enable_interrupt(struct wilc *dev)
218{
219 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
220 int ret = 0;
221
222 sdio_claim_host(func);
223 ret = sdio_claim_irq(func, wilc_sdio_interrupt);
224 sdio_release_host(func);
225
226 if (ret < 0) {
227 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret);
228 ret = -EIO;
229 }
230 return ret;
231}
232
233static void wilc_sdio_disable_interrupt(struct wilc *dev)
234{
235 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
236 int ret;
237
238 sdio_claim_host(func);
239 ret = sdio_release_irq(func);
240 if (ret < 0)
241 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret);
242 sdio_release_host(func);
243}
244
245/********************************************
246 *
247 * Function 0
248 *
249 ********************************************/
250
251static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
252{
253 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
254 struct sdio_cmd52 cmd;
255 int ret;
256
257 /**
258 * Review: BIG ENDIAN
259 **/
260 cmd.read_write = 1;
261 cmd.function = 0;
262 cmd.raw = 0;
263 cmd.address = WILC_SDIO_FBR_CSA_REG;
264 cmd.data = (u8)adr;
265 ret = wilc_sdio_cmd52(wilc, &cmd);
266 if (ret) {
267 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
268 cmd.address);
269 return ret;
270 }
271
272 cmd.address = WILC_SDIO_FBR_CSA_REG + 1;
273 cmd.data = (u8)(adr >> 8);
274 ret = wilc_sdio_cmd52(wilc, &cmd);
275 if (ret) {
276 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
277 cmd.address);
278 return ret;
279 }
280
281 cmd.address = WILC_SDIO_FBR_CSA_REG + 2;
282 cmd.data = (u8)(adr >> 16);
283 ret = wilc_sdio_cmd52(wilc, &cmd);
284 if (ret) {
285 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
286 cmd.address);
287 return ret;
288 }
289
290 return 0;
291}
292
293static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num,
294 u32 block_size)
295{
296 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
297 struct sdio_cmd52 cmd;
298 int ret;
299
300 cmd.read_write = 1;
301 cmd.function = 0;
302 cmd.raw = 0;
303 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE;
304 cmd.data = (u8)block_size;
305 ret = wilc_sdio_cmd52(wilc, &cmd);
306 if (ret) {
307 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
308 cmd.address);
309 return ret;
310 }
311
312 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1;
313 cmd.data = (u8)(block_size >> 8);
314 ret = wilc_sdio_cmd52(wilc, &cmd);
315 if (ret) {
316 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
317 cmd.address);
318 return ret;
319 }
320
321 return 0;
322}
323
324/********************************************
325 *
326 * Sdio interfaces
327 *
328 ********************************************/
329static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
330{
331 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
332 struct wilc_sdio *sdio_priv = wilc->bus_data;
333 int ret;
334
335 cpu_to_le32s(&data);
336
337 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
338 struct sdio_cmd52 cmd;
339
340 cmd.read_write = 1;
341 cmd.function = 0;
342 cmd.raw = 0;
343 cmd.address = addr;
344 cmd.data = data;
345 ret = wilc_sdio_cmd52(wilc, &cmd);
346 if (ret)
347 dev_err(&func->dev,
348 "Failed cmd 52, read reg (%08x) ...\n", addr);
349 } else {
350 struct sdio_cmd53 cmd;
351
352 /**
353 * set the AHB address
354 **/
355 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
356 if (ret)
357 return ret;
358
359 cmd.read_write = 1;
360 cmd.function = 0;
361 cmd.address = WILC_SDIO_FBR_DATA_REG;
362 cmd.block_mode = 0;
363 cmd.increment = 1;
364 cmd.count = 4;
365 cmd.buffer = (u8 *)&data;
366 cmd.block_size = sdio_priv->block_size;
367 ret = wilc_sdio_cmd53(wilc, &cmd);
368 if (ret)
369 dev_err(&func->dev,
370 "Failed cmd53, write reg (%08x)...\n", addr);
371 }
372
373 return ret;
374}
375
376static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
377{
378 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
379 struct wilc_sdio *sdio_priv = wilc->bus_data;
380 u32 block_size = sdio_priv->block_size;
381 struct sdio_cmd53 cmd;
382 int nblk, nleft, ret;
383
384 cmd.read_write = 1;
385 if (addr > 0) {
386 /**
387 * func 0 access
388 **/
389 cmd.function = 0;
390 cmd.address = WILC_SDIO_FBR_DATA_REG;
391 } else {
392 /**
393 * func 1 access
394 **/
395 cmd.function = 1;
396 cmd.address = WILC_SDIO_F1_DATA_REG;
397 }
398
399 size = ALIGN(size, 4);
400 nblk = size / block_size;
401 nleft = size % block_size;
402
403 if (nblk > 0) {
404 cmd.block_mode = 1;
405 cmd.increment = 1;
406 cmd.count = nblk;
407 cmd.buffer = buf;
408 cmd.block_size = block_size;
409 if (addr > 0) {
410 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
411 if (ret)
412 return ret;
413 }
414 ret = wilc_sdio_cmd53(wilc, &cmd);
415 if (ret) {
416 dev_err(&func->dev,
417 "Failed cmd53 [%x], block send...\n", addr);
418 return ret;
419 }
420 if (addr > 0)
421 addr += nblk * block_size;
422 buf += nblk * block_size;
423 }
424
425 if (nleft > 0) {
426 cmd.block_mode = 0;
427 cmd.increment = 1;
428 cmd.count = nleft;
429 cmd.buffer = buf;
430
431 cmd.block_size = block_size;
432
433 if (addr > 0) {
434 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
435 if (ret)
436 return ret;
437 }
438 ret = wilc_sdio_cmd53(wilc, &cmd);
439 if (ret) {
440 dev_err(&func->dev,
441 "Failed cmd53 [%x], bytes send...\n", addr);
442 return ret;
443 }
444 }
445
446 return 0;
447}
448
449static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
450{
451 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
452 struct wilc_sdio *sdio_priv = wilc->bus_data;
453 int ret;
454
455 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
456 struct sdio_cmd52 cmd;
457
458 cmd.read_write = 0;
459 cmd.function = 0;
460 cmd.raw = 0;
461 cmd.address = addr;
462 ret = wilc_sdio_cmd52(wilc, &cmd);
463 if (ret) {
464 dev_err(&func->dev,
465 "Failed cmd 52, read reg (%08x) ...\n", addr);
466 return ret;
467 }
468 *data = cmd.data;
469 } else {
470 struct sdio_cmd53 cmd;
471
472 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
473 if (ret)
474 return ret;
475
476 cmd.read_write = 0;
477 cmd.function = 0;
478 cmd.address = WILC_SDIO_FBR_DATA_REG;
479 cmd.block_mode = 0;
480 cmd.increment = 1;
481 cmd.count = 4;
482 cmd.buffer = (u8 *)data;
483
484 cmd.block_size = sdio_priv->block_size;
485 ret = wilc_sdio_cmd53(wilc, &cmd);
486 if (ret) {
487 dev_err(&func->dev,
488 "Failed cmd53, read reg (%08x)...\n", addr);
489 return ret;
490 }
491 }
492
493 le32_to_cpus(data);
494 return 0;
495}
496
497static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
498{
499 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
500 struct wilc_sdio *sdio_priv = wilc->bus_data;
501 u32 block_size = sdio_priv->block_size;
502 struct sdio_cmd53 cmd;
503 int nblk, nleft, ret;
504
505 cmd.read_write = 0;
506 if (addr > 0) {
507 /**
508 * func 0 access
509 **/
510 cmd.function = 0;
511 cmd.address = WILC_SDIO_FBR_DATA_REG;
512 } else {
513 /**
514 * func 1 access
515 **/
516 cmd.function = 1;
517 cmd.address = WILC_SDIO_F1_DATA_REG;
518 }
519
520 size = ALIGN(size, 4);
521 nblk = size / block_size;
522 nleft = size % block_size;
523
524 if (nblk > 0) {
525 cmd.block_mode = 1;
526 cmd.increment = 1;
527 cmd.count = nblk;
528 cmd.buffer = buf;
529 cmd.block_size = block_size;
530 if (addr > 0) {
531 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
532 if (ret)
533 return ret;
534 }
535 ret = wilc_sdio_cmd53(wilc, &cmd);
536 if (ret) {
537 dev_err(&func->dev,
538 "Failed cmd53 [%x], block read...\n", addr);
539 return ret;
540 }
541 if (addr > 0)
542 addr += nblk * block_size;
543 buf += nblk * block_size;
544 } /* if (nblk > 0) */
545
546 if (nleft > 0) {
547 cmd.block_mode = 0;
548 cmd.increment = 1;
549 cmd.count = nleft;
550 cmd.buffer = buf;
551
552 cmd.block_size = block_size;
553
554 if (addr > 0) {
555 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
556 if (ret)
557 return ret;
558 }
559 ret = wilc_sdio_cmd53(wilc, &cmd);
560 if (ret) {
561 dev_err(&func->dev,
562 "Failed cmd53 [%x], bytes read...\n", addr);
563 return ret;
564 }
565 }
566
567 return 0;
568}
569
570/********************************************
571 *
572 * Bus interfaces
573 *
574 ********************************************/
575
576static int wilc_sdio_deinit(struct wilc *wilc)
577{
578 return 0;
579}
580
581static int wilc_sdio_init(struct wilc *wilc, bool resume)
582{
583 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
584 struct wilc_sdio *sdio_priv = wilc->bus_data;
585 struct sdio_cmd52 cmd;
586 int loop, ret;
587 u32 chipid;
588
589 /**
590 * function 0 csa enable
591 **/
592 cmd.read_write = 1;
593 cmd.function = 0;
594 cmd.raw = 1;
595 cmd.address = SDIO_FBR_BASE(func->num);
596 cmd.data = SDIO_FBR_ENABLE_CSA;
597 ret = wilc_sdio_cmd52(wilc, &cmd);
598 if (ret) {
599 dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
600 return ret;
601 }
602
603 /**
604 * function 0 block size
605 **/
606 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE);
607 if (ret) {
608 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n");
609 return ret;
610 }
611 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE;
612
613 /**
614 * enable func1 IO
615 **/
616 cmd.read_write = 1;
617 cmd.function = 0;
618 cmd.raw = 1;
619 cmd.address = SDIO_CCCR_IOEx;
620 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1;
621 ret = wilc_sdio_cmd52(wilc, &cmd);
622 if (ret) {
623 dev_err(&func->dev,
624 "Fail cmd 52, set IOE register...\n");
625 return ret;
626 }
627
628 /**
629 * make sure func 1 is up
630 **/
631 cmd.read_write = 0;
632 cmd.function = 0;
633 cmd.raw = 0;
634 cmd.address = SDIO_CCCR_IORx;
635 loop = 3;
636 do {
637 cmd.data = 0;
638 ret = wilc_sdio_cmd52(wilc, &cmd);
639 if (ret) {
640 dev_err(&func->dev,
641 "Fail cmd 52, get IOR register...\n");
642 return ret;
643 }
644 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1)
645 break;
646 } while (loop--);
647
648 if (loop <= 0) {
649 dev_err(&func->dev, "Fail func 1 is not ready...\n");
650 return -EINVAL;
651 }
652
653 /**
654 * func 1 is ready, set func 1 block size
655 **/
656 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE);
657 if (ret) {
658 dev_err(&func->dev, "Fail set func 1 block size...\n");
659 return ret;
660 }
661
662 /**
663 * func 1 interrupt enable
664 **/
665 cmd.read_write = 1;
666 cmd.function = 0;
667 cmd.raw = 1;
668 cmd.address = SDIO_CCCR_IENx;
669 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1;
670 ret = wilc_sdio_cmd52(wilc, &cmd);
671 if (ret) {
672 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
673 return ret;
674 }
675
676 /**
677 * make sure can read back chip id correctly
678 **/
679 if (!resume) {
680 int rev;
681
682 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid);
683 if (ret) {
684 dev_err(&func->dev, "Fail cmd read chip id...\n");
685 return ret;
686 }
687 dev_err(&func->dev, "chipid (%08x)\n", chipid);
688 rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid);
689 if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A))
690 sdio_priv->has_thrpt_enh3 = 1;
691 else
692 sdio_priv->has_thrpt_enh3 = 0;
693 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n",
694 sdio_priv->has_thrpt_enh3);
695 }
696
697 return 0;
698}
699
700static int wilc_sdio_read_size(struct wilc *wilc, u32 *size)
701{
702 u32 tmp;
703 struct sdio_cmd52 cmd;
704
705 /**
706 * Read DMA count in words
707 **/
708 cmd.read_write = 0;
709 cmd.function = 0;
710 cmd.raw = 0;
711 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG;
712 cmd.data = 0;
713 wilc_sdio_cmd52(wilc, &cmd);
714 tmp = cmd.data;
715
716 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1;
717 cmd.data = 0;
718 wilc_sdio_cmd52(wilc, &cmd);
719 tmp |= (cmd.data << 8);
720
721 *size = tmp;
722 return 0;
723}
724
725static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
726{
727 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
728 struct wilc_sdio *sdio_priv = wilc->bus_data;
729 u32 tmp;
730 u8 irq_flags;
731 struct sdio_cmd52 cmd;
732
733 wilc_sdio_read_size(wilc, &tmp);
734
735 /**
736 * Read IRQ flags
737 **/
738 if (!sdio_priv->irq_gpio) {
739 cmd.function = 1;
740 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG;
741 } else {
742 cmd.function = 0;
743 cmd.address = WILC_SDIO_IRQ_FLAG_REG;
744 }
745 cmd.raw = 0;
746 cmd.read_write = 0;
747 cmd.data = 0;
748 wilc_sdio_cmd52(wilc, &cmd);
749 irq_flags = cmd.data;
750 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data);
751
752 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags))
753 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n",
754 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags));
755
756 *int_status = tmp;
757
758 return 0;
759}
760
761static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
762{
763 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
764 struct wilc_sdio *sdio_priv = wilc->bus_data;
765 int ret;
766 int vmm_ctl;
767
768 if (sdio_priv->has_thrpt_enh3) {
769 u32 reg = 0;
770
771 if (sdio_priv->irq_gpio)
772 reg = val & (BIT(MAX_NUM_INT) - 1);
773
774 /* select VMM table 0 */
775 if (val & SEL_VMM_TBL0)
776 reg |= BIT(5);
777 /* select VMM table 1 */
778 if (val & SEL_VMM_TBL1)
779 reg |= BIT(6);
780 /* enable VMM */
781 if (val & EN_VMM)
782 reg |= BIT(7);
783 if (reg) {
784 struct sdio_cmd52 cmd;
785
786 cmd.read_write = 1;
787 cmd.function = 0;
788 cmd.raw = 0;
789 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
790 cmd.data = reg;
791
792 ret = wilc_sdio_cmd52(wilc, &cmd);
793 if (ret) {
794 dev_err(&func->dev,
795 "Failed cmd52, set (%02x) data (%d) ...\n",
796 cmd.address, __LINE__);
797 return ret;
798 }
799 }
800 return 0;
801 }
802 if (sdio_priv->irq_gpio) {
803 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */
804 /*
805 * Cannot clear multiple interrupts.
806 * Must clear each interrupt individually.
807 */
808 u32 flags;
809 int i;
810
811 flags = val & (BIT(MAX_NUM_INT) - 1);
812 for (i = 0; i < NUM_INT_EXT && flags; i++) {
813 if (flags & BIT(i)) {
814 struct sdio_cmd52 cmd;
815
816 cmd.read_write = 1;
817 cmd.function = 0;
818 cmd.raw = 0;
819 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
820 cmd.data = BIT(i);
821
822 ret = wilc_sdio_cmd52(wilc, &cmd);
823 if (ret) {
824 dev_err(&func->dev,
825 "Failed cmd52, set (%02x) data (%d) ...\n",
826 cmd.address, __LINE__);
827 return ret;
828 }
829 flags &= ~BIT(i);
830 }
831 }
832
833 for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) {
834 if (flags & BIT(i)) {
835 dev_err(&func->dev,
836 "Unexpected interrupt cleared %d...\n",
837 i);
838 flags &= ~BIT(i);
839 }
840 }
841 }
842
843 vmm_ctl = 0;
844 /* select VMM table 0 */
845 if (val & SEL_VMM_TBL0)
846 vmm_ctl |= BIT(0);
847 /* select VMM table 1 */
848 if (val & SEL_VMM_TBL1)
849 vmm_ctl |= BIT(1);
850 /* enable VMM */
851 if (val & EN_VMM)
852 vmm_ctl |= BIT(2);
853
854 if (vmm_ctl) {
855 struct sdio_cmd52 cmd;
856
857 cmd.read_write = 1;
858 cmd.function = 0;
859 cmd.raw = 0;
860 cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG;
861 cmd.data = vmm_ctl;
862 ret = wilc_sdio_cmd52(wilc, &cmd);
863 if (ret) {
864 dev_err(&func->dev,
865 "Failed cmd52, set (%02x) data (%d) ...\n",
866 cmd.address, __LINE__);
867 return ret;
868 }
869 }
870 return 0;
871}
872
873static int wilc_sdio_sync_ext(struct wilc *wilc, int nint)
874{
875 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
876 struct wilc_sdio *sdio_priv = wilc->bus_data;
877 u32 reg;
878
879 if (nint > MAX_NUM_INT) {
880 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint);
881 return -EINVAL;
882 }
883
884 /**
885 * Disable power sequencer
886 **/
887 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) {
888 dev_err(&func->dev, "Failed read misc reg...\n");
889 return -EINVAL;
890 }
891
892 reg &= ~BIT(8);
893 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) {
894 dev_err(&func->dev, "Failed write misc reg...\n");
895 return -EINVAL;
896 }
897
898 if (sdio_priv->irq_gpio) {
899 u32 reg;
900 int ret, i;
901
902 /**
903 * interrupt pin mux select
904 **/
905 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®);
906 if (ret) {
907 dev_err(&func->dev, "Failed read reg (%08x)...\n",
908 WILC_PIN_MUX_0);
909 return ret;
910 }
911 reg |= BIT(8);
912 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg);
913 if (ret) {
914 dev_err(&func->dev, "Failed write reg (%08x)...\n",
915 WILC_PIN_MUX_0);
916 return ret;
917 }
918
919 /**
920 * interrupt enable
921 **/
922 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®);
923 if (ret) {
924 dev_err(&func->dev, "Failed read reg (%08x)...\n",
925 WILC_INTR_ENABLE);
926 return ret;
927 }
928
929 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
930 reg |= BIT((27 + i));
931 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg);
932 if (ret) {
933 dev_err(&func->dev, "Failed write reg (%08x)...\n",
934 WILC_INTR_ENABLE);
935 return ret;
936 }
937 if (nint) {
938 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®);
939 if (ret) {
940 dev_err(&func->dev,
941 "Failed read reg (%08x)...\n",
942 WILC_INTR2_ENABLE);
943 return ret;
944 }
945
946 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
947 reg |= BIT(i);
948
949 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®);
950 if (ret) {
951 dev_err(&func->dev,
952 "Failed write reg (%08x)...\n",
953 WILC_INTR2_ENABLE);
954 return ret;
955 }
956 }
957 }
958 return 0;
959}
960
961/* Global sdio HIF function table */
962static const struct wilc_hif_func wilc_hif_sdio = {
963 .hif_init = wilc_sdio_init,
964 .hif_deinit = wilc_sdio_deinit,
965 .hif_read_reg = wilc_sdio_read_reg,
966 .hif_write_reg = wilc_sdio_write_reg,
967 .hif_block_rx = wilc_sdio_read,
968 .hif_block_tx = wilc_sdio_write,
969 .hif_read_int = wilc_sdio_read_int,
970 .hif_clear_int_ext = wilc_sdio_clear_int_ext,
971 .hif_read_size = wilc_sdio_read_size,
972 .hif_block_tx_ext = wilc_sdio_write,
973 .hif_block_rx_ext = wilc_sdio_read,
974 .hif_sync_ext = wilc_sdio_sync_ext,
975 .enable_interrupt = wilc_sdio_enable_interrupt,
976 .disable_interrupt = wilc_sdio_disable_interrupt,
977};
978
979static int wilc_sdio_resume(struct device *dev)
980{
981 struct sdio_func *func = dev_to_sdio_func(dev);
982 struct wilc *wilc = sdio_get_drvdata(func);
983
984 dev_info(dev, "sdio resume\n");
985 sdio_release_host(func);
986 chip_wakeup(wilc);
987 wilc_sdio_init(wilc, true);
988
989 if (wilc->suspend_event)
990 host_wakeup_notify(wilc);
991
992 chip_allow_sleep(wilc);
993
994 return 0;
995}
996
997static const struct of_device_id wilc_of_match[] = {
998 { .compatible = "microchip,wilc1000", },
999 { /* sentinel */ }
1000};
1001MODULE_DEVICE_TABLE(of, wilc_of_match);
1002
1003static const struct dev_pm_ops wilc_sdio_pm_ops = {
1004 .suspend = wilc_sdio_suspend,
1005 .resume = wilc_sdio_resume,
1006};
1007
1008static struct sdio_driver wilc_sdio_driver = {
1009 .name = SDIO_MODALIAS,
1010 .id_table = wilc_sdio_ids,
1011 .probe = wilc_sdio_probe,
1012 .remove = wilc_sdio_remove,
1013 .drv = {
1014 .pm = &wilc_sdio_pm_ops,
1015 .of_match_table = wilc_of_match,
1016 }
1017};
1018module_driver(wilc_sdio_driver,
1019 sdio_register_driver,
1020 sdio_unregister_driver);
1021MODULE_LICENSE("GPL");