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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016 Intel Deutschland GmbH
6 */
7#ifndef __iwl_prph_h__
8#define __iwl_prph_h__
9#include <linux/bitfield.h>
10
11/*
12 * Registers in this file are internal, not PCI bus memory mapped.
13 * Driver accesses these via HBUS_TARG_PRPH_* registers.
14 */
15#define PRPH_BASE (0x00000)
16#define PRPH_END (0xFFFFF)
17
18/* APMG (power management) constants */
19#define APMG_BASE (PRPH_BASE + 0x3000)
20#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
21#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
22#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
23#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
24#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
25#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
26#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
27#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
28#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
29#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
30
31#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
32#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
33#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
34
35#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
36#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
37#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
38#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
39#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
40#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
41#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
42
43#define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
44#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
45#define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000)
46
47#define APMG_RTC_INT_STT_RFKILL (0x10000000)
48
49/* Device system time */
50#define DEVICE_SYSTEM_TIME_REG 0xA0206C
51
52/* Device NMI register and value for 8000 family and lower hw's */
53#define DEVICE_SET_NMI_REG 0x00a01c30
54#define DEVICE_SET_NMI_VAL_DRV BIT(7)
55/* Device NMI register and value for 9000 family and above hw's */
56#define UREG_NIC_SET_NMI_DRIVER 0x00a05c10
57#define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER BIT(24)
58#define UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE (BIT(24) | BIT(25))
59
60/* Shared registers (0x0..0x3ff, via target indirect or periphery */
61#define SHR_BASE 0x00a10000
62
63/* Shared GP1 register */
64#define SHR_APMG_GP1_REG 0x01dc
65#define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)
66#define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
67#define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
68
69/* Shared DL_CFG register */
70#define SHR_APMG_DL_CFG_REG 0x01c4
71#define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)
72#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
73#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
74#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
75
76/* Shared APMG_XTAL_CFG register */
77#define SHR_APMG_XTAL_CFG_REG 0x1c0
78#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
79
80/*
81 * Device reset for family 8000
82 * write to bit 24 in order to reset the CPU
83*/
84#define RELEASE_CPU_RESET (0x300C)
85#define RELEASE_CPU_RESET_BIT BIT(24)
86
87/*****************************************************************************
88 * 7000/3000 series SHR DTS addresses *
89 *****************************************************************************/
90
91#define SHR_MISC_WFM_DTS_EN (0x00a10024)
92#define DTSC_CFG_MODE (0x00a10604)
93#define DTSC_VREF_AVG (0x00a10648)
94#define DTSC_VREF5_AVG (0x00a1064c)
95#define DTSC_CFG_MODE_PERIODIC (0x2)
96#define DTSC_PTAT_AVG (0x00a10650)
97
98
99/**
100 * Tx Scheduler
101 *
102 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
103 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
104 * host DRAM. It steers each frame's Tx command (which contains the frame
105 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
106 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
107 * but one DMA channel may take input from several queues.
108 *
109 * Tx DMA FIFOs have dedicated purposes.
110 *
111 * For 5000 series and up, they are used differently
112 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
113 *
114 * 0 -- EDCA BK (background) frames, lowest priority
115 * 1 -- EDCA BE (best effort) frames, normal priority
116 * 2 -- EDCA VI (video) frames, higher priority
117 * 3 -- EDCA VO (voice) and management frames, highest priority
118 * 4 -- unused
119 * 5 -- unused
120 * 6 -- unused
121 * 7 -- Commands
122 *
123 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
124 * In addition, driver can map the remaining queues to Tx DMA/FIFO
125 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
126 *
127 * The driver sets up each queue to work in one of two modes:
128 *
129 * 1) Scheduler-Ack, in which the scheduler automatically supports a
130 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
131 * contains TFDs for a unique combination of Recipient Address (RA)
132 * and Traffic Identifier (TID), that is, traffic of a given
133 * Quality-Of-Service (QOS) priority, destined for a single station.
134 *
135 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
136 * each frame within the BA window, including whether it's been transmitted,
137 * and whether it's been acknowledged by the receiving station. The device
138 * automatically processes block-acks received from the receiving STA,
139 * and reschedules un-acked frames to be retransmitted (successful
140 * Tx completion may end up being out-of-order).
141 *
142 * The driver must maintain the queue's Byte Count table in host DRAM
143 * for this mode.
144 * This mode does not support fragmentation.
145 *
146 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
147 * The device may automatically retry Tx, but will retry only one frame
148 * at a time, until receiving ACK from receiving station, or reaching
149 * retry limit and giving up.
150 *
151 * The command queue (#4/#9) must use this mode!
152 * This mode does not require use of the Byte Count table in host DRAM.
153 *
154 * Driver controls scheduler operation via 3 means:
155 * 1) Scheduler registers
156 * 2) Shared scheduler data base in internal SRAM
157 * 3) Shared data in host DRAM
158 *
159 * Initialization:
160 *
161 * When loading, driver should allocate memory for:
162 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
163 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
164 * (1024 bytes for each queue).
165 *
166 * After receiving "Alive" response from uCode, driver must initialize
167 * the scheduler (especially for queue #4/#9, the command queue, otherwise
168 * the driver can't issue commands!):
169 */
170#define SCD_MEM_LOWER_BOUND (0x0000)
171
172/**
173 * Max Tx window size is the max number of contiguous TFDs that the scheduler
174 * can keep track of at one time when creating block-ack chains of frames.
175 * Note that "64" matches the number of ack bits in a block-ack packet.
176 */
177#define SCD_WIN_SIZE 64
178#define SCD_FRAME_LIMIT 64
179
180#define SCD_TXFIFO_POS_TID (0)
181#define SCD_TXFIFO_POS_RA (4)
182#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
183
184/* agn SCD */
185#define SCD_QUEUE_STTS_REG_POS_TXF (0)
186#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
187#define SCD_QUEUE_STTS_REG_POS_WSL (4)
188#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
189#define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
190
191#define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00)
192#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000)
193#define SCD_QUEUE_CTX_REG1_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG1_ ## _n, _v)
194
195#define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F)
196#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000)
197#define SCD_QUEUE_CTX_REG2_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG2_ ## _n, _v)
198
199#define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0)
200#define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18)
201
202/* Context Data */
203#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
204#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
205
206/* Tx status */
207#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
208#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
209
210/* Translation Data */
211#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
212#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
213
214#define SCD_CONTEXT_QUEUE_OFFSET(x)\
215 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
216
217#define SCD_TX_STTS_QUEUE_OFFSET(x)\
218 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
219
220#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
221 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
222
223#define SCD_BASE (PRPH_BASE + 0xa02c00)
224
225#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
226#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
227#define SCD_AIT (SCD_BASE + 0x0c)
228#define SCD_TXFACT (SCD_BASE + 0x10)
229#define SCD_ACTIVE (SCD_BASE + 0x14)
230#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
231#define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
232#define SCD_AGGR_SEL (SCD_BASE + 0x248)
233#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
234#define SCD_GP_CTRL (SCD_BASE + 0x1a8)
235#define SCD_EN_CTRL (SCD_BASE + 0x254)
236
237/*********************** END TX SCHEDULER *************************************/
238
239/* Oscillator clock */
240#define OSC_CLK (0xa04068)
241#define OSC_CLK_FORCE_CONTROL (0x8)
242
243#define FH_UCODE_LOAD_STATUS (0x1AF0)
244
245/*
246 * Replacing FH_UCODE_LOAD_STATUS
247 * This register is writen by driver and is read by uCode during boot flow.
248 * Note this address is cleared after MAC reset.
249 */
250#define UREG_UCODE_LOAD_STATUS (0xa05c40)
251#define UREG_CPU_INIT_RUN (0xa05c44)
252
253#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
254#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
255
256#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
257#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
258
259#define LMAC2_PRPH_OFFSET (0x100000)
260
261/* Rx FIFO */
262#define RXF_SIZE_ADDR (0xa00c88)
263#define RXF_RD_D_SPACE (0xa00c40)
264#define RXF_RD_WR_PTR (0xa00c50)
265#define RXF_RD_RD_PTR (0xa00c54)
266#define RXF_RD_FENCE_PTR (0xa00c4c)
267#define RXF_SET_FENCE_MODE (0xa00c14)
268#define RXF_LD_WR2FENCE (0xa00c1c)
269#define RXF_FIFO_RD_FENCE_INC (0xa00c68)
270#define RXF_SIZE_BYTE_CND_POS (7)
271#define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
272#define RXF_DIFF_FROM_PREV (0x200)
273#define RXF2C_DIFF_FROM_PREV (0x4e00)
274
275#define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
276#define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
277
278/* Tx FIFO */
279#define TXF_FIFO_ITEM_CNT (0xa00438)
280#define TXF_WR_PTR (0xa00414)
281#define TXF_RD_PTR (0xa00410)
282#define TXF_FENCE_PTR (0xa00418)
283#define TXF_LOCK_FENCE (0xa00424)
284#define TXF_LARC_NUM (0xa0043c)
285#define TXF_READ_MODIFY_DATA (0xa00448)
286#define TXF_READ_MODIFY_ADDR (0xa0044c)
287
288/* UMAC Internal Tx Fifo */
289#define TXF_CPU2_FIFO_ITEM_CNT (0xA00538)
290#define TXF_CPU2_WR_PTR (0xA00514)
291#define TXF_CPU2_RD_PTR (0xA00510)
292#define TXF_CPU2_FENCE_PTR (0xA00518)
293#define TXF_CPU2_LOCK_FENCE (0xA00524)
294#define TXF_CPU2_NUM (0xA0053C)
295#define TXF_CPU2_READ_MODIFY_DATA (0xA00548)
296#define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C)
297
298/* Radio registers access */
299#define RSP_RADIO_CMD (0xa02804)
300#define RSP_RADIO_RDDAT (0xa02814)
301#define RADIO_RSP_ADDR_POS (6)
302#define RADIO_RSP_RD_CMD (3)
303
304/* LTR control (Qu only) */
305#define HPM_MAC_LTR_CSR 0xa0348c
306#define HPM_MAC_LRT_ENABLE_ALL 0xf
307/* also uses CSR_LTR_* for values */
308#define HPM_UMAC_LTR 0xa03480
309
310/* FW monitor */
311#define MON_BUFF_SAMPLE_CTL (0xa03c00)
312#define MON_BUFF_BASE_ADDR (0xa03c1c)
313#define MON_BUFF_END_ADDR (0xa03c40)
314#define MON_BUFF_WRPTR (0xa03c44)
315#define MON_BUFF_CYCLE_CNT (0xa03c48)
316/* FW monitor family 8000 and on */
317#define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c)
318#define MON_BUFF_END_ADDR_VER2 (0xa03c20)
319#define MON_BUFF_WRPTR_VER2 (0xa03c24)
320#define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28)
321#define MON_BUFF_SHIFT_VER2 (0x8)
322/* FW monitor familiy AX210 and on */
323#define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20)
324#define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24)
325#define DBGC_CUR_DBGBUF_STATUS (0xd03c1c)
326#define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c)
327#define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff)
328#define DBGC_CUR_DBGBUF_STATUS_IDX_MSK (0x0f000000)
329
330#define MON_DMARB_RD_CTL_ADDR (0xa03c60)
331#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
332
333#define DBGC_IN_SAMPLE (0xa03c00)
334#define DBGC_OUT_CTRL (0xa03c0c)
335
336/* M2S registers */
337#define LDBG_M2S_BUF_WPTR (0xa0476c)
338#define LDBG_M2S_BUF_WRAP_CNT (0xa04774)
339#define LDBG_M2S_BUF_WPTR_VAL_MSK (0x000fffff)
340#define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK (0x000fffff)
341
342/* enable the ID buf for read */
343#define WFPM_PS_CTL_CLR 0xA0300C
344#define WFMP_MAC_ADDR_0 0xA03080
345#define WFMP_MAC_ADDR_1 0xA03084
346#define LMPM_PMG_EN 0xA01CEC
347#define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078
348#define RFIC_REG_RD 0xAD0470
349#define WFPM_CTRL_REG 0xA03030
350#define WFPM_OTP_CFG1_ADDR 0x00a03098
351#define WFPM_OTP_CFG1_IS_JACKET_BIT BIT(5)
352#define WFPM_OTP_CFG1_IS_CDB_BIT BIT(4)
353#define WFPM_OTP_BZ_BNJ_JACKET_BIT 5
354#define WFPM_OTP_BZ_BNJ_CDB_BIT 4
355#define WFPM_OTP_CFG1_IS_JACKET(_val) (((_val) & 0x00000020) >> WFPM_OTP_BZ_BNJ_JACKET_BIT)
356#define WFPM_OTP_CFG1_IS_CDB(_val) (((_val) & 0x00000010) >> WFPM_OTP_BZ_BNJ_CDB_BIT)
357
358
359#define WFPM_GP2 0xA030B4
360
361/* DBGI SRAM Register details */
362#define DBGI_SRAM_TARGET_ACCESS_RDATA_LSB 0x00A2E154
363#define DBGI_SRAM_TARGET_ACCESS_RDATA_MSB 0x00A2E158
364#define DBGI_SRAM_FIFO_POINTERS 0x00A2E148
365#define DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK 0x00000FFF
366
367enum {
368 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,
369};
370
371#define CNVI_AUX_MISC_CHIP 0xA200B0
372#define CNVR_AUX_MISC_CHIP 0xA2B800
373#define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890
374#define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938
375#define CNVI_SCU_SEQ_DATA_DW9 0xA27488
376
377#define PREG_AUX_BUS_WPROT_0 0xA04CC0
378
379/* device family 9000 WPROT register */
380#define PREG_PRPH_WPROT_9000 0xA04CE0
381/* device family 22000 WPROT register */
382#define PREG_PRPH_WPROT_22000 0xA04D00
383
384#define SB_MODIFY_CFG_FLAG 0xA03088
385#define SB_CFG_RESIDES_IN_ROM 0x80
386#define SB_CPU_1_STATUS 0xA01E30
387#define SB_CPU_2_STATUS 0xA01E34
388#define UMAG_SB_CPU_1_STATUS 0xA038C0
389#define UMAG_SB_CPU_2_STATUS 0xA038C4
390#define UMAG_GEN_HW_STATUS 0xA038C8
391#define UREG_UMAC_CURRENT_PC 0xa05c18
392#define UREG_LMAC1_CURRENT_PC 0xa05c1c
393#define UREG_LMAC2_CURRENT_PC 0xa05c20
394
395#define WFPM_LMAC1_PD_NOTIFICATION 0xa0338c
396#define WFPM_ARC1_PD_NOTIFICATION 0xa03044
397#define HPM_SECONDARY_DEVICE_STATE 0xa03404
398#define WFPM_MAC_OTP_CFG7_ADDR 0xa03338
399#define WFPM_MAC_OTP_CFG7_DATA 0xa0333c
400
401
402/* For UMAG_GEN_HW_STATUS reg check */
403enum {
404 UMAG_GEN_HW_IS_FPGA = BIT(1),
405};
406
407/* FW chicken bits */
408#define LMPM_CHICK 0xA01FF8
409enum {
410 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),
411};
412
413/* FW chicken bits */
414#define LMPM_PAGE_PASS_NOTIF 0xA03824
415enum {
416 LMPM_PAGE_PASS_NOTIF_POS = BIT(20),
417};
418
419/*
420 * CRF ID register
421 *
422 * type: bits 0-11
423 * reserved: bits 12-18
424 * slave_exist: bit 19
425 * dash: bits 20-23
426 * step: bits 24-27
427 * flavor: bits 28-31
428 */
429#define REG_CRF_ID_TYPE(val) (((val) & 0x00000FFF) >> 0)
430#define REG_CRF_ID_SLAVE(val) (((val) & 0x00080000) >> 19)
431#define REG_CRF_ID_DASH(val) (((val) & 0x00F00000) >> 20)
432#define REG_CRF_ID_STEP(val) (((val) & 0x0F000000) >> 24)
433#define REG_CRF_ID_FLAVOR(val) (((val) & 0xF0000000) >> 28)
434
435#define UREG_CHICK (0xA05C00)
436#define UREG_CHICK_MSI_ENABLE BIT(24)
437#define UREG_CHICK_MSIX_ENABLE BIT(25)
438
439#define SD_REG_VER 0xa29600
440#define SD_REG_VER_GEN2 0x00a2b800
441
442#define REG_CRF_ID_TYPE_JF_1 0x201
443#define REG_CRF_ID_TYPE_JF_2 0x202
444#define REG_CRF_ID_TYPE_HR_CDB 0x503
445#define REG_CRF_ID_TYPE_HR_NONE_CDB 0x504
446#define REG_CRF_ID_TYPE_HR_NONE_CDB_1X1 0x501
447#define REG_CRF_ID_TYPE_HR_NONE_CDB_CCP 0x532
448#define REG_CRF_ID_TYPE_GF 0x410
449#define REG_CRF_ID_TYPE_GF_TC 0xF08
450#define REG_CRF_ID_TYPE_MR 0x810
451#define REG_CRF_ID_TYPE_FM 0x910
452#define REG_CRF_ID_TYPE_FMI 0x930
453#define REG_CRF_ID_TYPE_FMR 0x900
454#define REG_CRF_ID_TYPE_WHP 0xA10
455
456#define HPM_DEBUG 0xA03440
457#define PERSISTENCE_BIT BIT(12)
458#define PREG_WFPM_ACCESS BIT(12)
459
460#define HPM_HIPM_GEN_CFG 0xA03458
461#define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0)
462#define HPM_HIPM_GEN_CFG_CR_SLP_EN BIT(1)
463#define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE BIT(10)
464
465#define UREG_DOORBELL_TO_ISR6 0xA05C04
466#define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0)
467#define UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE (BIT(0) | BIT(1))
468#define UREG_DOORBELL_TO_ISR6_SUSPEND BIT(18)
469#define UREG_DOORBELL_TO_ISR6_RESUME BIT(19)
470#define UREG_DOORBELL_TO_ISR6_PNVM BIT(20)
471
472/*
473 * From BZ family driver triggers this bit for suspend and resume
474 * The driver should update CSR_IPC_SLEEP_CONTROL before triggering
475 * this interrupt with suspend/resume value
476 */
477#define UREG_DOORBELL_TO_ISR6_SLEEP_CTRL BIT(31)
478
479#define CNVI_MBOX_C 0xA3400C
480
481#define FSEQ_ERROR_CODE 0xA340C8
482#define FSEQ_TOP_INIT_VERSION 0xA34038
483#define FSEQ_CNVIO_INIT_VERSION 0xA3403C
484#define FSEQ_OTP_VERSION 0xA340FC
485#define FSEQ_TOP_CONTENT_VERSION 0xA340F4
486#define FSEQ_ALIVE_TOKEN 0xA340F0
487#define FSEQ_CNVI_ID 0xA3408C
488#define FSEQ_CNVR_ID 0xA34090
489#define FSEQ_PREV_CNVIO_INIT_VERSION 0xA34084
490#define FSEQ_WIFI_FSEQ_VERSION 0xA34040
491#define FSEQ_BT_FSEQ_VERSION 0xA34044
492#define FSEQ_CLASS_TP_VERSION 0xA34078
493
494#define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3
495#define IWL_D3_SLEEP_STATUS_RESUME 0xD0
496
497#define WMAL_INDRCT_RD_CMD1_OPMOD_POS 28
498#define WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK 0xFFFFF
499#define WMAL_CMD_READ_BURST_ACCESS 2
500#define WMAL_MRSPF_1 0xADFC20
501#define WMAL_INDRCT_RD_CMD1 0xADFD44
502#define WMAL_INDRCT_CMD1 0xADFC14
503#define WMAL_INDRCT_CMD(addr) \
504 ((WMAL_CMD_READ_BURST_ACCESS << WMAL_INDRCT_RD_CMD1_OPMOD_POS) | \
505 ((addr) & WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK))
506
507#define WFPM_LMAC1_PS_CTL_RW 0xA03380
508#define WFPM_LMAC2_PS_CTL_RW 0xA033C0
509#define WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK 0x0000000F
510#define WFPM_PHYRF_STATE_ON 5
511#define HBUS_TIMEOUT 0xA5A5A5A1
512#define WFPM_DPHY_OFF 0xDF10FF
513
514#define REG_OTP_MINOR 0xA0333C
515
516#define WFPM_LMAC2_PD_NOTIFICATION 0xA033CC
517#define WFPM_LMAC2_PD_RE_READ BIT(31)
518
519#define DPHYIP_INDIRECT 0xA2D800
520#define DPHYIP_INDIRECT_RD_MSK 0xFF000000
521#define DPHYIP_INDIRECT_RD_SHIFT 24
522
523#endif /* __iwl_prph_h__ */
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9 * Copyright(c) 2016 Intel Deutschland GmbH
10 * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <linuxwifi@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 * BSD LICENSE
29 *
30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31 * Copyright(c) 2016 Intel Deutschland GmbH
32 * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 *
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
44 * distribution.
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 *****************************************************************************/
61
62#ifndef __iwl_prph_h__
63#define __iwl_prph_h__
64#include <linux/bitfield.h>
65
66/*
67 * Registers in this file are internal, not PCI bus memory mapped.
68 * Driver accesses these via HBUS_TARG_PRPH_* registers.
69 */
70#define PRPH_BASE (0x00000)
71#define PRPH_END (0xFFFFF)
72
73/* APMG (power management) constants */
74#define APMG_BASE (PRPH_BASE + 0x3000)
75#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
76#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
77#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
78#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
79#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
80#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
81#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
82#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
83#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
84#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
85
86#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
87#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
88#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
89
90#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
91#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
92#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
93#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
94#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
95#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
96#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
97
98#define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
99#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
100#define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000)
101
102#define APMG_RTC_INT_STT_RFKILL (0x10000000)
103
104/* Device system time */
105#define DEVICE_SYSTEM_TIME_REG 0xA0206C
106
107/* Device NMI register and value for 8000 family and lower hw's */
108#define DEVICE_SET_NMI_REG 0x00a01c30
109#define DEVICE_SET_NMI_VAL_DRV BIT(7)
110/* Device NMI register and value for 9000 family and above hw's */
111#define UREG_NIC_SET_NMI_DRIVER 0x00a05c10
112#define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK 0xff000000
113
114/* Shared registers (0x0..0x3ff, via target indirect or periphery */
115#define SHR_BASE 0x00a10000
116
117/* Shared GP1 register */
118#define SHR_APMG_GP1_REG 0x01dc
119#define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)
120#define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
121#define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
122
123/* Shared DL_CFG register */
124#define SHR_APMG_DL_CFG_REG 0x01c4
125#define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)
126#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
127#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
128#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
129
130/* Shared APMG_XTAL_CFG register */
131#define SHR_APMG_XTAL_CFG_REG 0x1c0
132#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
133
134/*
135 * Device reset for family 8000
136 * write to bit 24 in order to reset the CPU
137*/
138#define RELEASE_CPU_RESET (0x300C)
139#define RELEASE_CPU_RESET_BIT BIT(24)
140
141/*****************************************************************************
142 * 7000/3000 series SHR DTS addresses *
143 *****************************************************************************/
144
145#define SHR_MISC_WFM_DTS_EN (0x00a10024)
146#define DTSC_CFG_MODE (0x00a10604)
147#define DTSC_VREF_AVG (0x00a10648)
148#define DTSC_VREF5_AVG (0x00a1064c)
149#define DTSC_CFG_MODE_PERIODIC (0x2)
150#define DTSC_PTAT_AVG (0x00a10650)
151
152
153/**
154 * Tx Scheduler
155 *
156 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
157 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
158 * host DRAM. It steers each frame's Tx command (which contains the frame
159 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
160 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
161 * but one DMA channel may take input from several queues.
162 *
163 * Tx DMA FIFOs have dedicated purposes.
164 *
165 * For 5000 series and up, they are used differently
166 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
167 *
168 * 0 -- EDCA BK (background) frames, lowest priority
169 * 1 -- EDCA BE (best effort) frames, normal priority
170 * 2 -- EDCA VI (video) frames, higher priority
171 * 3 -- EDCA VO (voice) and management frames, highest priority
172 * 4 -- unused
173 * 5 -- unused
174 * 6 -- unused
175 * 7 -- Commands
176 *
177 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
178 * In addition, driver can map the remaining queues to Tx DMA/FIFO
179 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
180 *
181 * The driver sets up each queue to work in one of two modes:
182 *
183 * 1) Scheduler-Ack, in which the scheduler automatically supports a
184 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
185 * contains TFDs for a unique combination of Recipient Address (RA)
186 * and Traffic Identifier (TID), that is, traffic of a given
187 * Quality-Of-Service (QOS) priority, destined for a single station.
188 *
189 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
190 * each frame within the BA window, including whether it's been transmitted,
191 * and whether it's been acknowledged by the receiving station. The device
192 * automatically processes block-acks received from the receiving STA,
193 * and reschedules un-acked frames to be retransmitted (successful
194 * Tx completion may end up being out-of-order).
195 *
196 * The driver must maintain the queue's Byte Count table in host DRAM
197 * for this mode.
198 * This mode does not support fragmentation.
199 *
200 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
201 * The device may automatically retry Tx, but will retry only one frame
202 * at a time, until receiving ACK from receiving station, or reaching
203 * retry limit and giving up.
204 *
205 * The command queue (#4/#9) must use this mode!
206 * This mode does not require use of the Byte Count table in host DRAM.
207 *
208 * Driver controls scheduler operation via 3 means:
209 * 1) Scheduler registers
210 * 2) Shared scheduler data base in internal SRAM
211 * 3) Shared data in host DRAM
212 *
213 * Initialization:
214 *
215 * When loading, driver should allocate memory for:
216 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
217 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
218 * (1024 bytes for each queue).
219 *
220 * After receiving "Alive" response from uCode, driver must initialize
221 * the scheduler (especially for queue #4/#9, the command queue, otherwise
222 * the driver can't issue commands!):
223 */
224#define SCD_MEM_LOWER_BOUND (0x0000)
225
226/**
227 * Max Tx window size is the max number of contiguous TFDs that the scheduler
228 * can keep track of at one time when creating block-ack chains of frames.
229 * Note that "64" matches the number of ack bits in a block-ack packet.
230 */
231#define SCD_WIN_SIZE 64
232#define SCD_FRAME_LIMIT 64
233
234#define SCD_TXFIFO_POS_TID (0)
235#define SCD_TXFIFO_POS_RA (4)
236#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
237
238/* agn SCD */
239#define SCD_QUEUE_STTS_REG_POS_TXF (0)
240#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
241#define SCD_QUEUE_STTS_REG_POS_WSL (4)
242#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
243#define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
244
245#define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00)
246#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000)
247#define SCD_QUEUE_CTX_REG1_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG1_ ## _n, _v)
248
249#define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F)
250#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000)
251#define SCD_QUEUE_CTX_REG2_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG2_ ## _n, _v)
252
253#define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0)
254#define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18)
255
256/* Context Data */
257#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
258#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
259
260/* Tx status */
261#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
262#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
263
264/* Translation Data */
265#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
266#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
267
268#define SCD_CONTEXT_QUEUE_OFFSET(x)\
269 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
270
271#define SCD_TX_STTS_QUEUE_OFFSET(x)\
272 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
273
274#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
275 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
276
277#define SCD_BASE (PRPH_BASE + 0xa02c00)
278
279#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
280#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
281#define SCD_AIT (SCD_BASE + 0x0c)
282#define SCD_TXFACT (SCD_BASE + 0x10)
283#define SCD_ACTIVE (SCD_BASE + 0x14)
284#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
285#define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
286#define SCD_AGGR_SEL (SCD_BASE + 0x248)
287#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
288#define SCD_GP_CTRL (SCD_BASE + 0x1a8)
289#define SCD_EN_CTRL (SCD_BASE + 0x254)
290
291/*********************** END TX SCHEDULER *************************************/
292
293/* Oscillator clock */
294#define OSC_CLK (0xa04068)
295#define OSC_CLK_FORCE_CONTROL (0x8)
296
297#define FH_UCODE_LOAD_STATUS (0x1AF0)
298
299/*
300 * Replacing FH_UCODE_LOAD_STATUS
301 * This register is writen by driver and is read by uCode during boot flow.
302 * Note this address is cleared after MAC reset.
303 */
304#define UREG_UCODE_LOAD_STATUS (0xa05c40)
305#define UREG_CPU_INIT_RUN (0xa05c44)
306
307#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
308#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
309
310#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
311#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
312
313#define LMAC2_PRPH_OFFSET (0x100000)
314
315/* Rx FIFO */
316#define RXF_SIZE_ADDR (0xa00c88)
317#define RXF_RD_D_SPACE (0xa00c40)
318#define RXF_RD_WR_PTR (0xa00c50)
319#define RXF_RD_RD_PTR (0xa00c54)
320#define RXF_RD_FENCE_PTR (0xa00c4c)
321#define RXF_SET_FENCE_MODE (0xa00c14)
322#define RXF_LD_WR2FENCE (0xa00c1c)
323#define RXF_FIFO_RD_FENCE_INC (0xa00c68)
324#define RXF_SIZE_BYTE_CND_POS (7)
325#define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
326#define RXF_DIFF_FROM_PREV (0x200)
327#define RXF2C_DIFF_FROM_PREV (0x4e00)
328
329#define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
330#define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
331
332/* Tx FIFO */
333#define TXF_FIFO_ITEM_CNT (0xa00438)
334#define TXF_WR_PTR (0xa00414)
335#define TXF_RD_PTR (0xa00410)
336#define TXF_FENCE_PTR (0xa00418)
337#define TXF_LOCK_FENCE (0xa00424)
338#define TXF_LARC_NUM (0xa0043c)
339#define TXF_READ_MODIFY_DATA (0xa00448)
340#define TXF_READ_MODIFY_ADDR (0xa0044c)
341
342/* UMAC Internal Tx Fifo */
343#define TXF_CPU2_FIFO_ITEM_CNT (0xA00538)
344#define TXF_CPU2_WR_PTR (0xA00514)
345#define TXF_CPU2_RD_PTR (0xA00510)
346#define TXF_CPU2_FENCE_PTR (0xA00518)
347#define TXF_CPU2_LOCK_FENCE (0xA00524)
348#define TXF_CPU2_NUM (0xA0053C)
349#define TXF_CPU2_READ_MODIFY_DATA (0xA00548)
350#define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C)
351
352/* Radio registers access */
353#define RSP_RADIO_CMD (0xa02804)
354#define RSP_RADIO_RDDAT (0xa02814)
355#define RADIO_RSP_ADDR_POS (6)
356#define RADIO_RSP_RD_CMD (3)
357
358/* FW monitor */
359#define MON_BUFF_SAMPLE_CTL (0xa03c00)
360#define MON_BUFF_BASE_ADDR (0xa03c1c)
361#define MON_BUFF_END_ADDR (0xa03c40)
362#define MON_BUFF_WRPTR (0xa03c44)
363#define MON_BUFF_CYCLE_CNT (0xa03c48)
364/* FW monitor family 8000 and on */
365#define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c)
366#define MON_BUFF_END_ADDR_VER2 (0xa03c20)
367#define MON_BUFF_WRPTR_VER2 (0xa03c24)
368#define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28)
369#define MON_BUFF_SHIFT_VER2 (0x8)
370/* FW monitor familiy AX210 and on */
371#define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20)
372#define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24)
373#define DBGC_CUR_DBGBUF_STATUS (0xd03c1c)
374#define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c)
375#define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff)
376#define DBGC_CUR_DBGBUF_STATUS_IDX_MSK (0x0f000000)
377
378#define MON_DMARB_RD_CTL_ADDR (0xa03c60)
379#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
380
381#define DBGC_IN_SAMPLE (0xa03c00)
382#define DBGC_OUT_CTRL (0xa03c0c)
383
384/* M2S registers */
385#define LDBG_M2S_BUF_WPTR (0xa0476c)
386#define LDBG_M2S_BUF_WRAP_CNT (0xa04774)
387#define LDBG_M2S_BUF_WPTR_VAL_MSK (0x000fffff)
388#define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK (0x000fffff)
389
390/* enable the ID buf for read */
391#define WFPM_PS_CTL_CLR 0xA0300C
392#define WFMP_MAC_ADDR_0 0xA03080
393#define WFMP_MAC_ADDR_1 0xA03084
394#define LMPM_PMG_EN 0xA01CEC
395#define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078
396#define RFIC_REG_RD 0xAD0470
397#define WFPM_CTRL_REG 0xA03030
398#define WFPM_GP2 0xA030B4
399enum {
400 ENABLE_WFPM = BIT(31),
401 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,
402};
403
404#define CNVI_AUX_MISC_CHIP 0xA200B0
405#define CNVR_AUX_MISC_CHIP 0xA2B800
406#define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890
407#define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938
408
409enum {
410 HW_STEP_LOCATION_BITS = 24,
411};
412
413#define PREG_AUX_BUS_WPROT_0 0xA04CC0
414
415/* device family 9000 WPROT register */
416#define PREG_PRPH_WPROT_9000 0xA04CE0
417/* device family 22000 WPROT register */
418#define PREG_PRPH_WPROT_22000 0xA04D00
419
420#define SB_CPU_1_STATUS 0xA01E30
421#define SB_CPU_2_STATUS 0xA01E34
422#define UMAG_SB_CPU_1_STATUS 0xA038C0
423#define UMAG_SB_CPU_2_STATUS 0xA038C4
424#define UMAG_GEN_HW_STATUS 0xA038C8
425#define UREG_UMAC_CURRENT_PC 0xa05c18
426#define UREG_LMAC1_CURRENT_PC 0xa05c1c
427#define UREG_LMAC2_CURRENT_PC 0xa05c20
428
429/* For UMAG_GEN_HW_STATUS reg check */
430enum {
431 UMAG_GEN_HW_IS_FPGA = BIT(1),
432};
433
434/* FW chicken bits */
435#define LMPM_CHICK 0xA01FF8
436enum {
437 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),
438};
439
440/* FW chicken bits */
441#define LMPM_PAGE_PASS_NOTIF 0xA03824
442enum {
443 LMPM_PAGE_PASS_NOTIF_POS = BIT(20),
444};
445
446#define UREG_CHICK (0xA05C00)
447#define UREG_CHICK_MSI_ENABLE BIT(24)
448#define UREG_CHICK_MSIX_ENABLE BIT(25)
449
450#define HPM_DEBUG 0xA03440
451#define PERSISTENCE_BIT BIT(12)
452#define PREG_WFPM_ACCESS BIT(12)
453
454#define HPM_HIPM_GEN_CFG 0xA03458
455#define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0)
456#define HPM_HIPM_GEN_CFG_CR_SLP_EN BIT(1)
457#define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE BIT(10)
458
459#define UREG_DOORBELL_TO_ISR6 0xA05C04
460#define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0)
461#define UREG_DOORBELL_TO_ISR6_SUSPEND BIT(18)
462#define UREG_DOORBELL_TO_ISR6_RESUME BIT(19)
463
464#define FSEQ_ERROR_CODE 0xA340C8
465#define FSEQ_TOP_INIT_VERSION 0xA34038
466#define FSEQ_CNVIO_INIT_VERSION 0xA3403C
467#define FSEQ_OTP_VERSION 0xA340FC
468#define FSEQ_TOP_CONTENT_VERSION 0xA340F4
469#define FSEQ_ALIVE_TOKEN 0xA340F0
470#define FSEQ_CNVI_ID 0xA3408C
471#define FSEQ_CNVR_ID 0xA34090
472
473#define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3
474#define IWL_D3_SLEEP_STATUS_RESUME 0xD0
475#endif /* __iwl_prph_h__ */