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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2018-2024 Intel Corporation
4 */
5#include <linux/firmware.h>
6#include "iwl-drv.h"
7#include "iwl-trans.h"
8#include "iwl-dbg-tlv.h"
9#include "fw/dbg.h"
10#include "fw/runtime.h"
11
12/**
13 * enum iwl_dbg_tlv_type - debug TLV types
14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
17 * @IWL_DBG_TLV_TYPE_REGION: region TLV
18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV
20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
21 */
22enum iwl_dbg_tlv_type {
23 IWL_DBG_TLV_TYPE_DEBUG_INFO =
24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
25 IWL_DBG_TLV_TYPE_BUF_ALLOC,
26 IWL_DBG_TLV_TYPE_HCMD,
27 IWL_DBG_TLV_TYPE_REGION,
28 IWL_DBG_TLV_TYPE_TRIGGER,
29 IWL_DBG_TLV_TYPE_CONF_SET,
30 IWL_DBG_TLV_TYPE_NUM,
31};
32
33/**
34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct
35 * @min_ver: min version supported
36 * @max_ver: max version supported
37 */
38struct iwl_dbg_tlv_ver_data {
39 int min_ver;
40 int max_ver;
41};
42
43/**
44 * struct iwl_dbg_tlv_timer_node - timer node struct
45 * @list: list of &struct iwl_dbg_tlv_timer_node
46 * @timer: timer
47 * @fwrt: &struct iwl_fw_runtime
48 * @tlv: TLV attach to the timer node
49 */
50struct iwl_dbg_tlv_timer_node {
51 struct list_head list;
52 struct timer_list timer;
53 struct iwl_fw_runtime *fwrt;
54 struct iwl_ucode_tlv *tlv;
55};
56
57static const struct iwl_dbg_tlv_ver_data
58dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,},
60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,},
61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,},
62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,},
63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,},
65};
66
67static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv,
68 struct list_head *list)
69{
70 u32 len = le32_to_cpu(tlv->length);
71 struct iwl_dbg_tlv_node *node;
72
73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
74 if (!node)
75 return -ENOMEM;
76
77 memcpy(&node->tlv, tlv, sizeof(node->tlv));
78 memcpy(node->tlv.data, tlv->data, len);
79 list_add_tail(&node->list, list);
80
81 return 0;
82}
83
84static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv)
85{
86 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
87 u32 type = le32_to_cpu(tlv->type);
88 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
89 u32 ver = le32_to_cpu(hdr->version);
90
91 if (ver < dbg_ver_table[tlv_idx].min_ver ||
92 ver > dbg_ver_table[tlv_idx].max_ver)
93 return false;
94
95 return true;
96}
97
98static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
99 const struct iwl_ucode_tlv *tlv)
100{
101 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data;
102
103 if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
104 return -EINVAL;
105
106 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
107 debug_info->debug_cfg_name);
108
109 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
110}
111
112static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
113 const struct iwl_ucode_tlv *tlv)
114{
115 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data;
116 u32 buf_location;
117 u32 alloc_id;
118
119 if (le32_to_cpu(tlv->length) != sizeof(*alloc))
120 return -EINVAL;
121
122 buf_location = le32_to_cpu(alloc->buf_location);
123 alloc_id = le32_to_cpu(alloc->alloc_id);
124
125 if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
126 buf_location >= IWL_FW_INI_LOCATION_NUM)
127 goto err;
128
129 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
130 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
131 goto err;
132
133 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH &&
134 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
135 goto err;
136
137 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH &&
138 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
139 goto err;
140
141 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH &&
142 alloc->req_size == 0) {
143 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n");
144 return -EINVAL;
145 }
146
147 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
148
149 return 0;
150err:
151 IWL_ERR(trans,
152 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
153 alloc_id, buf_location);
154 return -EINVAL;
155}
156
157static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
158 const struct iwl_ucode_tlv *tlv)
159{
160 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data;
161 u32 tp = le32_to_cpu(hcmd->time_point);
162
163 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
164 return -EINVAL;
165
166 /* Host commands can not be sent in early time point since the FW
167 * is not ready
168 */
169 if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
170 tp >= IWL_FW_INI_TIME_POINT_NUM ||
171 tp == IWL_FW_INI_TIME_POINT_EARLY) {
172 IWL_ERR(trans,
173 "WRT: Invalid time point %u for host command TLV\n",
174 tp);
175 return -EINVAL;
176 }
177
178 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
179}
180
181static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
182 const struct iwl_ucode_tlv *tlv)
183{
184 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data;
185 struct iwl_ucode_tlv **active_reg;
186 u32 id = le32_to_cpu(reg->id);
187 u8 type = reg->type;
188 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
189
190 /*
191 * The higher part of the ID from version 2 is debug policy.
192 * The id will be only lsb 16 bits, so mask it out.
193 */
194 if (le32_to_cpu(reg->hdr.version) >= 2)
195 id &= IWL_FW_INI_REGION_ID_MASK;
196
197 if (le32_to_cpu(tlv->length) < sizeof(*reg))
198 return -EINVAL;
199
200 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */
201 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
202 IWL_FW_INI_MAX_NAME, reg->name);
203
204 if (id >= IWL_FW_INI_MAX_REGION_ID) {
205 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
206 return -EINVAL;
207 }
208
209 if (type <= IWL_FW_INI_REGION_INVALID ||
210 type >= IWL_FW_INI_REGION_NUM) {
211 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
212 return -EINVAL;
213 }
214
215 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
216 !trans->ops->read_config32) {
217 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
218 return -EOPNOTSUPP;
219 }
220
221 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) {
222 trans->dbg.imr_data.sram_addr =
223 le32_to_cpu(reg->internal_buffer.base_addr);
224 trans->dbg.imr_data.sram_size =
225 le32_to_cpu(reg->internal_buffer.size);
226 }
227
228
229 active_reg = &trans->dbg.active_regions[id];
230 if (*active_reg) {
231 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
232
233 kfree(*active_reg);
234 }
235
236 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
237 if (!*active_reg)
238 return -ENOMEM;
239
240 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
241
242 return 0;
243}
244
245static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
246 const struct iwl_ucode_tlv *tlv)
247{
248 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data;
249 struct iwl_fw_ini_trigger_tlv *dup_trig;
250 u32 tp = le32_to_cpu(trig->time_point);
251 u32 rf = le32_to_cpu(trig->reset_fw);
252 struct iwl_ucode_tlv *dup = NULL;
253 int ret;
254
255 if (le32_to_cpu(tlv->length) < sizeof(*trig))
256 return -EINVAL;
257
258 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
259 tp >= IWL_FW_INI_TIME_POINT_NUM) {
260 IWL_ERR(trans,
261 "WRT: Invalid time point %u for trigger TLV\n",
262 tp);
263 return -EINVAL;
264 }
265
266 IWL_DEBUG_FW(trans,
267 "WRT: time point %u for trigger TLV with reset_fw %u\n",
268 tp, rf);
269 trans->dbg.last_tp_resetfw = 0xFF;
270 if (!le32_to_cpu(trig->occurrences)) {
271 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
272 GFP_KERNEL);
273 if (!dup)
274 return -ENOMEM;
275 dup_trig = (void *)dup->data;
276 dup_trig->occurrences = cpu_to_le32(-1);
277 tlv = dup;
278 }
279
280 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
281 kfree(dup);
282
283 return ret;
284}
285
286static int iwl_dbg_tlv_config_set(struct iwl_trans *trans,
287 const struct iwl_ucode_tlv *tlv)
288{
289 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data;
290 u32 tp = le32_to_cpu(conf_set->time_point);
291 u32 type = le32_to_cpu(conf_set->set_type);
292
293 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
294 tp >= IWL_FW_INI_TIME_POINT_NUM) {
295 IWL_DEBUG_FW(trans,
296 "WRT: Invalid time point %u for config set TLV\n", tp);
297 return -EINVAL;
298 }
299
300 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID ||
301 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) {
302 IWL_DEBUG_FW(trans,
303 "WRT: Invalid config set type %u for config set TLV\n", type);
304 return -EINVAL;
305 }
306
307 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list);
308}
309
310static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
311 const struct iwl_ucode_tlv *tlv) = {
312 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
313 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
314 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
315 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region,
316 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
317 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set,
318};
319
320void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
321 bool ext)
322{
323 enum iwl_ini_cfg_state *cfg_state = ext ?
324 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
325 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
326 u32 type;
327 u32 tlv_idx;
328 u32 domain;
329 int ret;
330
331 if (le32_to_cpu(tlv->length) < sizeof(*hdr))
332 return;
333
334 type = le32_to_cpu(tlv->type);
335 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
336 domain = le32_to_cpu(hdr->domain);
337
338 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
339 !(domain & trans->dbg.domains_bitmap)) {
340 IWL_DEBUG_FW(trans,
341 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
342 domain, trans->dbg.domains_bitmap);
343 return;
344 }
345
346 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
347 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
348 goto out_err;
349 }
350
351 if (!iwl_dbg_tlv_ver_support(tlv)) {
352 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
353 le32_to_cpu(hdr->version));
354 goto out_err;
355 }
356
357 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
358 if (ret) {
359 IWL_WARN(trans,
360 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
361 type, ret, ext);
362 goto out_err;
363 }
364
365 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
366 *cfg_state = IWL_INI_CFG_STATE_LOADED;
367
368 return;
369
370out_err:
371 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
372}
373
374void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
375{
376 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
377 struct iwl_dbg_tlv_timer_node *node, *tmp;
378
379 list_for_each_entry_safe(node, tmp, timer_list, list) {
380 timer_shutdown_sync(&node->timer);
381 list_del(&node->list);
382 kfree(node);
383 }
384}
385IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
386
387static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
388 enum iwl_fw_ini_allocation_id alloc_id)
389{
390 struct iwl_fw_mon *fw_mon;
391 int i;
392
393 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
394 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
395 return;
396
397 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
398
399 for (i = 0; i < fw_mon->num_frags; i++) {
400 struct iwl_dram_data *frag = &fw_mon->frags[i];
401
402 dma_free_coherent(trans->dev, frag->size, frag->block,
403 frag->physical);
404
405 frag->physical = 0;
406 frag->block = NULL;
407 frag->size = 0;
408 }
409
410 kfree(fw_mon->frags);
411 fw_mon->frags = NULL;
412 fw_mon->num_frags = 0;
413}
414
415void iwl_dbg_tlv_free(struct iwl_trans *trans)
416{
417 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
418 int i;
419
420 iwl_dbg_tlv_del_timers(trans);
421
422 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
423 struct iwl_ucode_tlv **active_reg =
424 &trans->dbg.active_regions[i];
425
426 kfree(*active_reg);
427 *active_reg = NULL;
428 }
429
430 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
431 &trans->dbg.debug_info_tlv_list, list) {
432 list_del(&tlv_node->list);
433 kfree(tlv_node);
434 }
435
436 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
437 struct iwl_dbg_tlv_time_point_data *tp =
438 &trans->dbg.time_point[i];
439
440 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
441 list) {
442 list_del(&tlv_node->list);
443 kfree(tlv_node);
444 }
445
446 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
447 list) {
448 list_del(&tlv_node->list);
449 kfree(tlv_node);
450 }
451
452 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
453 &tp->active_trig_list, list) {
454 list_del(&tlv_node->list);
455 kfree(tlv_node);
456 }
457
458 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
459 &tp->config_list, list) {
460 list_del(&tlv_node->list);
461 kfree(tlv_node);
462 }
463
464 }
465
466 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
467 iwl_dbg_tlv_fragments_free(trans, i);
468}
469
470static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
471 size_t len)
472{
473 const struct iwl_ucode_tlv *tlv;
474 u32 tlv_len;
475
476 while (len >= sizeof(*tlv)) {
477 len -= sizeof(*tlv);
478 tlv = (const void *)data;
479
480 tlv_len = le32_to_cpu(tlv->length);
481
482 if (len < tlv_len) {
483 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
484 len, tlv_len);
485 return -EINVAL;
486 }
487 len -= ALIGN(tlv_len, 4);
488 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
489
490 iwl_dbg_tlv_alloc(trans, tlv, true);
491 }
492
493 return 0;
494}
495
496void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
497{
498 const struct firmware *fw;
499 const char *yoyo_bin = "iwl-debug-yoyo.bin";
500 int res;
501
502 if (!iwlwifi_mod_params.enable_ini ||
503 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000)
504 return;
505
506 res = firmware_request_nowarn(&fw, yoyo_bin, dev);
507 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
508
509 if (res)
510 return;
511
512 trans->dbg.yoyo_bin_loaded = true;
513
514 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
515
516 release_firmware(fw);
517}
518
519void iwl_dbg_tlv_init(struct iwl_trans *trans)
520{
521 int i;
522
523 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
524 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
525
526 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
527 struct iwl_dbg_tlv_time_point_data *tp =
528 &trans->dbg.time_point[i];
529
530 INIT_LIST_HEAD(&tp->trig_list);
531 INIT_LIST_HEAD(&tp->hcmd_list);
532 INIT_LIST_HEAD(&tp->active_trig_list);
533 INIT_LIST_HEAD(&tp->config_list);
534 }
535}
536
537static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
538 struct iwl_dram_data *frag, u32 pages)
539{
540 void *block = NULL;
541 dma_addr_t physical;
542
543 if (!frag || frag->size || !pages)
544 return -EIO;
545
546 /*
547 * We try to allocate as many pages as we can, starting with
548 * the requested amount and going down until we can allocate
549 * something. Because of DIV_ROUND_UP(), pages will never go
550 * down to 0 and stop the loop, so stop when pages reaches 1,
551 * which is too small anyway.
552 */
553 while (pages > 1) {
554 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
555 &physical,
556 GFP_KERNEL | __GFP_NOWARN);
557 if (block)
558 break;
559
560 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
561 pages * PAGE_SIZE);
562
563 pages = DIV_ROUND_UP(pages, 2);
564 }
565
566 if (!block)
567 return -ENOMEM;
568
569 frag->physical = physical;
570 frag->block = block;
571 frag->size = pages * PAGE_SIZE;
572
573 return pages;
574}
575
576static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
577 enum iwl_fw_ini_allocation_id alloc_id)
578{
579 struct iwl_fw_mon *fw_mon;
580 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
581 u32 num_frags, remain_pages, frag_pages;
582 int i;
583
584 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
585 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
586 return -EIO;
587
588 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
589 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
590
591 if (fw_mon->num_frags) {
592 for (i = 0; i < fw_mon->num_frags; i++)
593 memset(fw_mon->frags[i].block, 0,
594 fw_mon->frags[i].size);
595 return 0;
596 }
597
598 if (fw_mon_cfg->buf_location !=
599 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
600 return 0;
601
602 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
603 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
604 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
605 return -EIO;
606 num_frags = 1;
607 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
608 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) {
609 return -EIO;
610 }
611
612 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
613 PAGE_SIZE);
614 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
615 num_frags = min_t(u32, num_frags, remain_pages);
616 frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
617
618 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
619 if (!fw_mon->frags)
620 return -ENOMEM;
621
622 for (i = 0; i < num_frags; i++) {
623 int pages = min_t(u32, frag_pages, remain_pages);
624
625 IWL_DEBUG_FW(fwrt,
626 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
627 alloc_id, i, pages * PAGE_SIZE);
628
629 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
630 pages);
631 if (pages < 0) {
632 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
633 (remain_pages * PAGE_SIZE);
634
635 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
636 iwl_dbg_tlv_fragments_free(fwrt->trans,
637 alloc_id);
638 return pages;
639 }
640 break;
641 }
642
643 remain_pages -= pages;
644 fw_mon->num_frags++;
645 }
646
647 return 0;
648}
649
650static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
651 enum iwl_fw_ini_allocation_id alloc_id)
652{
653 struct iwl_fw_mon *fw_mon;
654 u32 remain_frags, num_commands;
655 int i, fw_mon_idx = 0;
656
657 if (!fw_has_capa(&fwrt->fw->ucode_capa,
658 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
659 return 0;
660
661 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
662 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
663 return -EIO;
664
665 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
666 IWL_FW_INI_LOCATION_DRAM_PATH)
667 return 0;
668
669 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
670
671 /* the first fragment of DBGC1 is given to the FW via register
672 * or context info
673 */
674 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
675 fw_mon_idx++;
676
677 remain_frags = fw_mon->num_frags - fw_mon_idx;
678 if (!remain_frags)
679 return 0;
680
681 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
682
683 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
684 alloc_id);
685
686 for (i = 0; i < num_commands; i++) {
687 u32 num_frags = min_t(u32, remain_frags,
688 BUF_ALLOC_MAX_NUM_FRAGS);
689 struct iwl_buf_alloc_cmd data = {
690 .alloc_id = cpu_to_le32(alloc_id),
691 .num_frags = cpu_to_le32(num_frags),
692 .buf_location =
693 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
694 };
695 struct iwl_host_cmd hcmd = {
696 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
697 .data[0] = &data,
698 .len[0] = sizeof(data),
699 .flags = CMD_SEND_IN_RFKILL,
700 };
701 int ret, j;
702
703 for (j = 0; j < num_frags; j++) {
704 struct iwl_buf_alloc_frag *frag = &data.frags[j];
705 struct iwl_dram_data *fw_mon_frag =
706 &fw_mon->frags[fw_mon_idx++];
707
708 frag->addr = cpu_to_le64(fw_mon_frag->physical);
709 frag->size = cpu_to_le32(fw_mon_frag->size);
710 }
711 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
712 if (ret)
713 return ret;
714
715 remain_frags -= num_frags;
716 }
717
718 return 0;
719}
720
721static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
722{
723 int ret, i;
724
725 if (fw_has_capa(&fwrt->fw->ucode_capa,
726 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
727 return;
728
729 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
730 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
731 if (ret)
732 IWL_WARN(fwrt,
733 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
734 i, ret);
735 }
736}
737
738static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
739 enum iwl_fw_ini_allocation_id alloc_id,
740 struct iwl_dram_info *dram_info)
741{
742 struct iwl_fw_mon *fw_mon;
743 u32 remain_frags, num_frags;
744 int j, fw_mon_idx = 0;
745 struct iwl_buf_alloc_cmd *data;
746
747 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
748 IWL_FW_INI_LOCATION_DRAM_PATH) {
749 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n",
750 alloc_id);
751 return -1;
752 }
753
754 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
755
756 /* the first fragment of DBGC1 is given to the FW via register
757 * or context info
758 */
759 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
760 fw_mon_idx++;
761
762 remain_frags = fw_mon->num_frags - fw_mon_idx;
763 if (!remain_frags)
764 return -1;
765
766 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
767 data = &dram_info->dram_frags[alloc_id - 1];
768 data->alloc_id = cpu_to_le32(alloc_id);
769 data->num_frags = cpu_to_le32(num_frags);
770 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH);
771
772 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n",
773 cpu_to_le32(alloc_id), cpu_to_le32(num_frags));
774
775 for (j = 0; j < num_frags; j++) {
776 struct iwl_buf_alloc_frag *frag = &data->frags[j];
777 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++];
778
779 frag->addr = cpu_to_le64(fw_mon_frag->physical);
780 frag->size = cpu_to_le32(fw_mon_frag->size);
781 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n");
782 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n",
783 j, cpu_to_le64(fw_mon_frag->physical),
784 cpu_to_le32(fw_mon_frag->size));
785 }
786 return 0;
787}
788
789static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
790{
791 int ret, i;
792 bool dram_alloc = false;
793 struct iwl_dram_data *frags =
794 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
795 struct iwl_dram_info *dram_info;
796
797 if (!frags || !frags->block)
798 return;
799
800 dram_info = frags->block;
801
802 if (!fw_has_capa(&fwrt->fw->ucode_capa,
803 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
804 return;
805
806 memset(dram_info, 0, sizeof(*dram_info));
807
808 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1;
809 i < IWL_FW_INI_ALLOCATION_NUM; i++) {
810 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
811 IWL_FW_INI_LOCATION_INVALID)
812 continue;
813
814 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
815 if (!ret)
816 dram_alloc = true;
817 else
818 IWL_INFO(fwrt,
819 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n",
820 i, ret);
821 }
822
823 if (dram_alloc) {
824 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD);
825 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD);
826 }
827}
828
829static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
830 struct list_head *hcmd_list)
831{
832 struct iwl_dbg_tlv_node *node;
833
834 list_for_each_entry(node, hcmd_list, list) {
835 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
836 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
837 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
838 struct iwl_host_cmd cmd = {
839 .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
840 .len = { hcmd_len, },
841 .data = { hcmd_data->data, },
842 };
843
844 iwl_trans_send_cmd(fwrt->trans, &cmd);
845 }
846}
847
848static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
849 struct list_head *conf_list)
850{
851 struct iwl_dbg_tlv_node *node;
852
853 list_for_each_entry(node, conf_list, list) {
854 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data;
855 u32 count, address, value;
856 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8;
857 u32 type = le32_to_cpu(config_list->set_type);
858 u32 offset = le32_to_cpu(config_list->addr_offset);
859
860 switch (type) {
861 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: {
862 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
863 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n");
864 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n");
865 continue;
866 }
867 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len);
868 for (count = 0; count < len; count++) {
869 address = le32_to_cpu(config_list->addr_val[count].address);
870 value = le32_to_cpu(config_list->addr_val[count].value);
871 iwl_trans_write_prph(fwrt->trans, address + offset, value);
872 }
873 iwl_trans_release_nic_access(fwrt->trans);
874 break;
875 }
876 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: {
877 for (count = 0; count < len; count++) {
878 address = le32_to_cpu(config_list->addr_val[count].address);
879 value = le32_to_cpu(config_list->addr_val[count].value);
880 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
881 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n",
882 count, address, value);
883 }
884 break;
885 }
886 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: {
887 for (count = 0; count < len; count++) {
888 address = le32_to_cpu(config_list->addr_val[count].address);
889 value = le32_to_cpu(config_list->addr_val[count].value);
890 iwl_write32(fwrt->trans, address + offset, value);
891 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
892 count, address, value);
893 }
894 break;
895 }
896 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: {
897 struct iwl_dbgc1_info dram_info = {};
898 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
899 __le64 dram_base_addr;
900 __le32 dram_size;
901 u64 dram_addr;
902 u32 ret;
903
904 if (!frags)
905 break;
906
907 dram_base_addr = cpu_to_le64(frags->physical);
908 dram_size = cpu_to_le32(frags->size);
909 dram_addr = le64_to_cpu(dram_base_addr);
910
911 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n",
912 dram_base_addr, dram_size);
913 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n",
914 le32_to_cpu(config_list->addr_offset));
915 for (count = 0; count < len; count++) {
916 address = le32_to_cpu(config_list->addr_val[count].address);
917 dram_info.dbgc1_add_lsb =
918 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400);
919 dram_info.dbgc1_add_msb =
920 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32);
921 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400);
922 ret = iwl_trans_write_mem(fwrt->trans,
923 address + offset, &dram_info, 4);
924 if (ret) {
925 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n");
926 break;
927 }
928 }
929 break;
930 }
931 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: {
932 u32 debug_token_config =
933 le32_to_cpu(config_list->addr_val[0].value);
934
935 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n",
936 debug_token_config);
937 fwrt->trans->dbg.ucode_preset = debug_token_config;
938 break;
939 }
940 default:
941 break;
942 }
943 }
944}
945
946static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
947{
948 struct iwl_dbg_tlv_timer_node *timer_node =
949 from_timer(timer_node, t, timer);
950 struct iwl_fwrt_dump_data dump_data = {
951 .trig = (void *)timer_node->tlv->data,
952 };
953 int ret;
954
955 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
956 if (!ret || ret == -EBUSY) {
957 u32 occur = le32_to_cpu(dump_data.trig->occurrences);
958 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
959
960 if (!occur)
961 return;
962
963 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
964 }
965}
966
967static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
968{
969 struct iwl_dbg_tlv_node *node;
970 struct list_head *trig_list =
971 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
972
973 list_for_each_entry(node, trig_list, list) {
974 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
975 struct iwl_dbg_tlv_timer_node *timer_node;
976 u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
977 u32 min_interval = 100;
978
979 if (!occur)
980 continue;
981
982 /* make sure there is at least one dword of data for the
983 * interval value
984 */
985 if (le32_to_cpu(node->tlv.length) <
986 sizeof(*trig) + sizeof(__le32)) {
987 IWL_ERR(fwrt,
988 "WRT: Invalid periodic trigger data was not given\n");
989 continue;
990 }
991
992 if (le32_to_cpu(trig->data[0]) < min_interval) {
993 IWL_WARN(fwrt,
994 "WRT: Override min interval from %u to %u msec\n",
995 le32_to_cpu(trig->data[0]), min_interval);
996 trig->data[0] = cpu_to_le32(min_interval);
997 }
998
999 collect_interval = le32_to_cpu(trig->data[0]);
1000
1001 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
1002 if (!timer_node) {
1003 IWL_ERR(fwrt,
1004 "WRT: Failed to allocate periodic trigger\n");
1005 continue;
1006 }
1007
1008 timer_node->fwrt = fwrt;
1009 timer_node->tlv = &node->tlv;
1010 timer_setup(&timer_node->timer,
1011 iwl_dbg_tlv_periodic_trig_handler, 0);
1012
1013 list_add_tail(&timer_node->list,
1014 &fwrt->trans->dbg.periodic_trig_list);
1015
1016 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
1017
1018 mod_timer(&timer_node->timer,
1019 jiffies + msecs_to_jiffies(collect_interval));
1020 }
1021}
1022
1023static bool is_trig_data_contained(const struct iwl_ucode_tlv *new,
1024 const struct iwl_ucode_tlv *old)
1025{
1026 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data;
1027 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data;
1028 const __le32 *new_data = new_trig->data, *old_data = old_trig->data;
1029 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
1030 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data);
1031 int i, j;
1032
1033 for (i = 0; i < new_dwords_num; i++) {
1034 bool match = false;
1035
1036 for (j = 0; j < old_dwords_num; j++) {
1037 if (new_data[i] == old_data[j]) {
1038 match = true;
1039 break;
1040 }
1041 }
1042 if (!match)
1043 return false;
1044 }
1045
1046 return true;
1047}
1048
1049static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
1050 struct iwl_ucode_tlv *trig_tlv,
1051 struct iwl_dbg_tlv_node *node)
1052{
1053 struct iwl_ucode_tlv *node_tlv = &node->tlv;
1054 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
1055 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1056 u32 policy = le32_to_cpu(trig->apply_policy);
1057 u32 size = le32_to_cpu(trig_tlv->length);
1058 u32 trig_data_len = size - sizeof(*trig);
1059 u32 offset = 0;
1060
1061 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
1062 u32 data_len = le32_to_cpu(node_tlv->length) -
1063 sizeof(*node_trig);
1064
1065 IWL_DEBUG_FW(fwrt,
1066 "WRT: Appending trigger data (time point %u)\n",
1067 le32_to_cpu(trig->time_point));
1068
1069 offset += data_len;
1070 size += data_len;
1071 } else {
1072 IWL_DEBUG_FW(fwrt,
1073 "WRT: Overriding trigger data (time point %u)\n",
1074 le32_to_cpu(trig->time_point));
1075 }
1076
1077 if (size != le32_to_cpu(node_tlv->length)) {
1078 struct list_head *prev = node->list.prev;
1079 struct iwl_dbg_tlv_node *tmp;
1080
1081 list_del(&node->list);
1082
1083 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
1084 if (!tmp) {
1085 IWL_WARN(fwrt,
1086 "WRT: No memory to override trigger (time point %u)\n",
1087 le32_to_cpu(trig->time_point));
1088
1089 list_add(&node->list, prev);
1090
1091 return -ENOMEM;
1092 }
1093
1094 list_add(&tmp->list, prev);
1095 node_tlv = &tmp->tlv;
1096 node_trig = (void *)node_tlv->data;
1097 }
1098
1099 memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len);
1100 node_tlv->length = cpu_to_le32(size);
1101
1102 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
1103 IWL_DEBUG_FW(fwrt,
1104 "WRT: Overriding trigger configuration (time point %u)\n",
1105 le32_to_cpu(trig->time_point));
1106
1107 /* the first 11 dwords are configuration related */
1108 memcpy(node_trig, trig, sizeof(__le32) * 11);
1109 }
1110
1111 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
1112 IWL_DEBUG_FW(fwrt,
1113 "WRT: Overriding trigger regions (time point %u)\n",
1114 le32_to_cpu(trig->time_point));
1115
1116 node_trig->regions_mask = trig->regions_mask;
1117 } else {
1118 IWL_DEBUG_FW(fwrt,
1119 "WRT: Appending trigger regions (time point %u)\n",
1120 le32_to_cpu(trig->time_point));
1121
1122 node_trig->regions_mask |= trig->regions_mask;
1123 }
1124
1125 return 0;
1126}
1127
1128static int
1129iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
1130 struct list_head *trig_list,
1131 struct iwl_ucode_tlv *trig_tlv)
1132{
1133 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1134 struct iwl_dbg_tlv_node *node, *match = NULL;
1135 u32 policy = le32_to_cpu(trig->apply_policy);
1136
1137 list_for_each_entry(node, trig_list, list) {
1138 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
1139 break;
1140
1141 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
1142 is_trig_data_contained(trig_tlv, &node->tlv)) {
1143 match = node;
1144 break;
1145 }
1146 }
1147
1148 if (!match) {
1149 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
1150 le32_to_cpu(trig->time_point));
1151 return iwl_dbg_tlv_add(trig_tlv, trig_list);
1152 }
1153
1154 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
1155}
1156
1157static void
1158iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
1159 struct iwl_dbg_tlv_time_point_data *tp)
1160{
1161 struct iwl_dbg_tlv_node *node;
1162 struct list_head *trig_list = &tp->trig_list;
1163 struct list_head *active_trig_list = &tp->active_trig_list;
1164
1165 list_for_each_entry(node, trig_list, list) {
1166 struct iwl_ucode_tlv *tlv = &node->tlv;
1167
1168 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
1169 }
1170}
1171
1172static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
1173 struct iwl_fwrt_dump_data *dump_data,
1174 union iwl_dbg_tlv_tp_data *tp_data,
1175 u32 trig_data)
1176{
1177 struct iwl_rx_packet *pkt = tp_data->fw_pkt;
1178 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
1179
1180 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd &&
1181 pkt->hdr.group_id == wanted_hdr->group_id)) {
1182 struct iwl_rx_packet *fw_pkt =
1183 kmemdup(pkt,
1184 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
1185 GFP_ATOMIC);
1186
1187 if (!fw_pkt)
1188 return false;
1189
1190 dump_data->fw_pkt = fw_pkt;
1191
1192 return true;
1193 }
1194
1195 return false;
1196}
1197
1198static int
1199iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
1200 struct list_head *active_trig_list,
1201 union iwl_dbg_tlv_tp_data *tp_data,
1202 bool (*data_check)(struct iwl_fw_runtime *fwrt,
1203 struct iwl_fwrt_dump_data *dump_data,
1204 union iwl_dbg_tlv_tp_data *tp_data,
1205 u32 trig_data))
1206{
1207 struct iwl_dbg_tlv_node *node;
1208
1209 list_for_each_entry(node, active_trig_list, list) {
1210 struct iwl_fwrt_dump_data dump_data = {
1211 .trig = (void *)node->tlv.data,
1212 };
1213 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
1214 data);
1215 int ret, i;
1216 u32 tp = le32_to_cpu(dump_data.trig->time_point);
1217
1218
1219 if (!num_data) {
1220 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1221 if (ret)
1222 return ret;
1223 }
1224
1225 for (i = 0; i < num_data; i++) {
1226 if (!data_check ||
1227 data_check(fwrt, &dump_data, tp_data,
1228 le32_to_cpu(dump_data.trig->data[i]))) {
1229 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1230 if (ret)
1231 return ret;
1232
1233 break;
1234 }
1235 }
1236
1237 fwrt->trans->dbg.restart_required = FALSE;
1238 IWL_DEBUG_FW(fwrt, "WRT: tp %d, reset_fw %d\n",
1239 tp, dump_data.trig->reset_fw);
1240 IWL_DEBUG_FW(fwrt,
1241 "WRT: restart_required %d, last_tp_resetfw %d\n",
1242 fwrt->trans->dbg.restart_required,
1243 fwrt->trans->dbg.last_tp_resetfw);
1244
1245 if (fwrt->trans->trans_cfg->device_family ==
1246 IWL_DEVICE_FAMILY_9000) {
1247 fwrt->trans->dbg.restart_required = TRUE;
1248 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT &&
1249 fwrt->trans->dbg.last_tp_resetfw ==
1250 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1251 fwrt->trans->dbg.restart_required = FALSE;
1252 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1253 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n");
1254 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1255 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) {
1256 IWL_DEBUG_FW(fwrt, "WRT: stop and reload firmware\n");
1257 fwrt->trans->dbg.restart_required = TRUE;
1258 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1259 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1260 IWL_DEBUG_FW(fwrt,
1261 "WRT: stop only and no reload firmware\n");
1262 fwrt->trans->dbg.restart_required = FALSE;
1263 fwrt->trans->dbg.last_tp_resetfw =
1264 le32_to_cpu(dump_data.trig->reset_fw);
1265 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1266 IWL_FW_INI_RESET_FW_MODE_NOTHING) {
1267 IWL_DEBUG_FW(fwrt,
1268 "WRT: nothing need to be done after debug collection\n");
1269 } else {
1270 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n",
1271 le32_to_cpu(dump_data.trig->reset_fw));
1272 }
1273 }
1274 return 0;
1275}
1276
1277void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1278{
1279 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1280 int ret, i;
1281 u32 failed_alloc = 0;
1282
1283 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) {
1284 IWL_DEBUG_FW(fwrt,
1285 "WRT: Generating active triggers list, domain 0x%x\n",
1286 fwrt->trans->dbg.domains_bitmap);
1287
1288 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1289 struct iwl_dbg_tlv_time_point_data *tp =
1290 &fwrt->trans->dbg.time_point[i];
1291
1292 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1293 }
1294 } else if (*ini_dest != IWL_FW_INI_LOCATION_DRAM_PATH) {
1295 /* For DRAM, go through the loop below to clear all the buffers
1296 * properly on restart, otherwise garbage may be left there and
1297 * leak into new debug dumps.
1298 */
1299 return;
1300 }
1301
1302 *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1303 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1304 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1305 &fwrt->trans->dbg.fw_mon_cfg[i];
1306 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1307
1308 if (dest == IWL_FW_INI_LOCATION_INVALID) {
1309 failed_alloc |= BIT(i);
1310 continue;
1311 }
1312
1313 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1314 *ini_dest = dest;
1315
1316 if (dest != *ini_dest)
1317 continue;
1318
1319 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1320
1321 if (ret) {
1322 IWL_WARN(fwrt,
1323 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1324 i, ret);
1325 failed_alloc |= BIT(i);
1326 }
1327 }
1328
1329 if (!failed_alloc)
1330 return;
1331
1332 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1333 struct iwl_fw_ini_region_tlv *reg;
1334 struct iwl_ucode_tlv **active_reg =
1335 &fwrt->trans->dbg.active_regions[i];
1336 u32 reg_type;
1337
1338 if (!*active_reg) {
1339 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1340 continue;
1341 }
1342
1343 reg = (void *)(*active_reg)->data;
1344 reg_type = reg->type;
1345
1346 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER ||
1347 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc))
1348 continue;
1349
1350 IWL_DEBUG_FW(fwrt,
1351 "WRT: removing allocation id %d from region id %d\n",
1352 le32_to_cpu(reg->dram_alloc_id), i);
1353
1354 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id));
1355 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1356
1357 kfree(*active_reg);
1358 *active_reg = NULL;
1359 }
1360}
1361
1362void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1363 enum iwl_fw_ini_time_point tp_id,
1364 union iwl_dbg_tlv_tp_data *tp_data,
1365 bool sync)
1366{
1367 struct list_head *hcmd_list, *trig_list, *conf_list;
1368
1369 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1370 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1371 tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1372 return;
1373
1374 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1375 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1376 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;
1377
1378 switch (tp_id) {
1379 case IWL_FW_INI_TIME_POINT_EARLY:
1380 iwl_dbg_tlv_init_cfg(fwrt);
1381 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1382 iwl_dbg_tlv_update_drams(fwrt);
1383 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1384 break;
1385 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1386 iwl_dbg_tlv_apply_buffers(fwrt);
1387 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1388 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1389 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1390 break;
1391 case IWL_FW_INI_TIME_POINT_PERIODIC:
1392 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1393 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1394 break;
1395 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1396 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1397 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION:
1398 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1399 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1400 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1401 iwl_dbg_tlv_check_fw_pkt);
1402 break;
1403 default:
1404 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1405 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1406 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1407 break;
1408 }
1409}
1410IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point);
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright (C) 2018 - 2020 Intel Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright (C) 2018 - 2020 Intel Corporation
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 *
38 * * Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * * Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in
42 * the documentation and/or other materials provided with the
43 * distribution.
44 * * Neither the name Intel Corporation nor the names of its
45 * contributors may be used to endorse or promote products derived
46 * from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
49 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
50 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
51 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
52 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
53 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
54 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
58 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 *
60 *****************************************************************************/
61
62#include <linux/firmware.h>
63#include "iwl-drv.h"
64#include "iwl-trans.h"
65#include "iwl-dbg-tlv.h"
66#include "fw/dbg.h"
67#include "fw/runtime.h"
68
69/**
70 * enum iwl_dbg_tlv_type - debug TLV types
71 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
72 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
73 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
74 * @IWL_DBG_TLV_TYPE_REGION: region TLV
75 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
76 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
77 */
78enum iwl_dbg_tlv_type {
79 IWL_DBG_TLV_TYPE_DEBUG_INFO =
80 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
81 IWL_DBG_TLV_TYPE_BUF_ALLOC,
82 IWL_DBG_TLV_TYPE_HCMD,
83 IWL_DBG_TLV_TYPE_REGION,
84 IWL_DBG_TLV_TYPE_TRIGGER,
85 IWL_DBG_TLV_TYPE_NUM,
86};
87
88/**
89 * struct iwl_dbg_tlv_ver_data - debug TLV version struct
90 * @min_ver: min version supported
91 * @max_ver: max version supported
92 */
93struct iwl_dbg_tlv_ver_data {
94 int min_ver;
95 int max_ver;
96};
97
98/**
99 * struct iwl_dbg_tlv_timer_node - timer node struct
100 * @list: list of &struct iwl_dbg_tlv_timer_node
101 * @timer: timer
102 * @fwrt: &struct iwl_fw_runtime
103 * @tlv: TLV attach to the timer node
104 */
105struct iwl_dbg_tlv_timer_node {
106 struct list_head list;
107 struct timer_list timer;
108 struct iwl_fw_runtime *fwrt;
109 struct iwl_ucode_tlv *tlv;
110};
111
112static const struct iwl_dbg_tlv_ver_data
113dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
114 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,},
115 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,},
116 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,},
117 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,},
118 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
119};
120
121static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list)
122{
123 u32 len = le32_to_cpu(tlv->length);
124 struct iwl_dbg_tlv_node *node;
125
126 node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
127 if (!node)
128 return -ENOMEM;
129
130 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len);
131 list_add_tail(&node->list, list);
132
133 return 0;
134}
135
136static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv)
137{
138 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
139 u32 type = le32_to_cpu(tlv->type);
140 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
141 u32 ver = le32_to_cpu(hdr->version);
142
143 if (ver < dbg_ver_table[tlv_idx].min_ver ||
144 ver > dbg_ver_table[tlv_idx].max_ver)
145 return false;
146
147 return true;
148}
149
150static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
151 struct iwl_ucode_tlv *tlv)
152{
153 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data;
154
155 if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
156 return -EINVAL;
157
158 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
159 debug_info->debug_cfg_name);
160
161 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
162}
163
164static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
165 struct iwl_ucode_tlv *tlv)
166{
167 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data;
168 u32 buf_location;
169 u32 alloc_id;
170
171 if (le32_to_cpu(tlv->length) != sizeof(*alloc))
172 return -EINVAL;
173
174 buf_location = le32_to_cpu(alloc->buf_location);
175 alloc_id = le32_to_cpu(alloc->alloc_id);
176
177 if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
178 buf_location >= IWL_FW_INI_LOCATION_NUM)
179 goto err;
180
181 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
182 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
183 goto err;
184
185 if ((buf_location == IWL_FW_INI_LOCATION_SRAM_PATH ||
186 buf_location == IWL_FW_INI_LOCATION_NPK_PATH) &&
187 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
188 goto err;
189
190 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
191
192 return 0;
193err:
194 IWL_ERR(trans,
195 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
196 alloc_id, buf_location);
197 return -EINVAL;
198}
199
200static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
201 struct iwl_ucode_tlv *tlv)
202{
203 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data;
204 u32 tp = le32_to_cpu(hcmd->time_point);
205
206 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
207 return -EINVAL;
208
209 /* Host commands can not be sent in early time point since the FW
210 * is not ready
211 */
212 if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
213 tp >= IWL_FW_INI_TIME_POINT_NUM ||
214 tp == IWL_FW_INI_TIME_POINT_EARLY) {
215 IWL_ERR(trans,
216 "WRT: Invalid time point %u for host command TLV\n",
217 tp);
218 return -EINVAL;
219 }
220
221 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
222}
223
224static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
225 struct iwl_ucode_tlv *tlv)
226{
227 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data;
228 struct iwl_ucode_tlv **active_reg;
229 u32 id = le32_to_cpu(reg->id);
230 u32 type = le32_to_cpu(reg->type);
231 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
232
233 if (le32_to_cpu(tlv->length) < sizeof(*reg))
234 return -EINVAL;
235
236 if (id >= IWL_FW_INI_MAX_REGION_ID) {
237 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
238 return -EINVAL;
239 }
240
241 if (type <= IWL_FW_INI_REGION_INVALID ||
242 type >= IWL_FW_INI_REGION_NUM) {
243 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
244 return -EINVAL;
245 }
246
247 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
248 !trans->ops->read_config32) {
249 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
250 return -EOPNOTSUPP;
251 }
252
253 active_reg = &trans->dbg.active_regions[id];
254 if (*active_reg) {
255 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
256
257 kfree(*active_reg);
258 }
259
260 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
261 if (!*active_reg)
262 return -ENOMEM;
263
264 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
265
266 return 0;
267}
268
269static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
270 struct iwl_ucode_tlv *tlv)
271{
272 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data;
273 u32 tp = le32_to_cpu(trig->time_point);
274 struct iwl_ucode_tlv *dup = NULL;
275 int ret;
276
277 if (le32_to_cpu(tlv->length) < sizeof(*trig))
278 return -EINVAL;
279
280 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
281 tp >= IWL_FW_INI_TIME_POINT_NUM) {
282 IWL_ERR(trans,
283 "WRT: Invalid time point %u for trigger TLV\n",
284 tp);
285 return -EINVAL;
286 }
287
288 if (!le32_to_cpu(trig->occurrences)) {
289 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
290 GFP_KERNEL);
291 if (!dup)
292 return -ENOMEM;
293 trig = (void *)dup->data;
294 trig->occurrences = cpu_to_le32(-1);
295 tlv = dup;
296 }
297
298 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
299 kfree(dup);
300
301 return ret;
302}
303
304static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
305 struct iwl_ucode_tlv *tlv) = {
306 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
307 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
308 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
309 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region,
310 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
311};
312
313void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv,
314 bool ext)
315{
316 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
317 u32 type = le32_to_cpu(tlv->type);
318 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
319 u32 domain = le32_to_cpu(hdr->domain);
320 enum iwl_ini_cfg_state *cfg_state = ext ?
321 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
322 int ret;
323
324 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
325 !(domain & trans->dbg.domains_bitmap)) {
326 IWL_DEBUG_FW(trans,
327 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
328 domain, trans->dbg.domains_bitmap);
329 return;
330 }
331
332 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
333 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
334 goto out_err;
335 }
336
337 if (!iwl_dbg_tlv_ver_support(tlv)) {
338 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
339 le32_to_cpu(hdr->version));
340 goto out_err;
341 }
342
343 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
344 if (ret) {
345 IWL_ERR(trans,
346 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
347 type, ret, ext);
348 goto out_err;
349 }
350
351 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
352 *cfg_state = IWL_INI_CFG_STATE_LOADED;
353
354 return;
355
356out_err:
357 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
358}
359
360void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
361{
362 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
363 struct iwl_dbg_tlv_timer_node *node, *tmp;
364
365 list_for_each_entry_safe(node, tmp, timer_list, list) {
366 del_timer(&node->timer);
367 list_del(&node->list);
368 kfree(node);
369 }
370}
371IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
372
373static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
374 enum iwl_fw_ini_allocation_id alloc_id)
375{
376 struct iwl_fw_mon *fw_mon;
377 int i;
378
379 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
380 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
381 return;
382
383 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
384
385 for (i = 0; i < fw_mon->num_frags; i++) {
386 struct iwl_dram_data *frag = &fw_mon->frags[i];
387
388 dma_free_coherent(trans->dev, frag->size, frag->block,
389 frag->physical);
390
391 frag->physical = 0;
392 frag->block = NULL;
393 frag->size = 0;
394 }
395
396 kfree(fw_mon->frags);
397 fw_mon->frags = NULL;
398 fw_mon->num_frags = 0;
399}
400
401void iwl_dbg_tlv_free(struct iwl_trans *trans)
402{
403 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
404 int i;
405
406 iwl_dbg_tlv_del_timers(trans);
407
408 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
409 struct iwl_ucode_tlv **active_reg =
410 &trans->dbg.active_regions[i];
411
412 kfree(*active_reg);
413 *active_reg = NULL;
414 }
415
416 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
417 &trans->dbg.debug_info_tlv_list, list) {
418 list_del(&tlv_node->list);
419 kfree(tlv_node);
420 }
421
422 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
423 struct iwl_dbg_tlv_time_point_data *tp =
424 &trans->dbg.time_point[i];
425
426 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
427 list) {
428 list_del(&tlv_node->list);
429 kfree(tlv_node);
430 }
431
432 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
433 list) {
434 list_del(&tlv_node->list);
435 kfree(tlv_node);
436 }
437
438 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
439 &tp->active_trig_list, list) {
440 list_del(&tlv_node->list);
441 kfree(tlv_node);
442 }
443 }
444
445 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
446 iwl_dbg_tlv_fragments_free(trans, i);
447}
448
449static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
450 size_t len)
451{
452 struct iwl_ucode_tlv *tlv;
453 u32 tlv_len;
454
455 while (len >= sizeof(*tlv)) {
456 len -= sizeof(*tlv);
457 tlv = (void *)data;
458
459 tlv_len = le32_to_cpu(tlv->length);
460
461 if (len < tlv_len) {
462 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
463 len, tlv_len);
464 return -EINVAL;
465 }
466 len -= ALIGN(tlv_len, 4);
467 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
468
469 iwl_dbg_tlv_alloc(trans, tlv, true);
470 }
471
472 return 0;
473}
474
475void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
476{
477 const struct firmware *fw;
478 int res;
479
480 if (!iwlwifi_mod_params.enable_ini)
481 return;
482
483 res = firmware_request_nowarn(&fw, "iwl-debug-yoyo.bin", dev);
484 if (res)
485 return;
486
487 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
488
489 release_firmware(fw);
490}
491
492void iwl_dbg_tlv_init(struct iwl_trans *trans)
493{
494 int i;
495
496 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
497 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
498
499 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
500 struct iwl_dbg_tlv_time_point_data *tp =
501 &trans->dbg.time_point[i];
502
503 INIT_LIST_HEAD(&tp->trig_list);
504 INIT_LIST_HEAD(&tp->hcmd_list);
505 INIT_LIST_HEAD(&tp->active_trig_list);
506 }
507}
508
509static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
510 struct iwl_dram_data *frag, u32 pages)
511{
512 void *block = NULL;
513 dma_addr_t physical;
514
515 if (!frag || frag->size || !pages)
516 return -EIO;
517
518 /*
519 * We try to allocate as many pages as we can, starting with
520 * the requested amount and going down until we can allocate
521 * something. Because of DIV_ROUND_UP(), pages will never go
522 * down to 0 and stop the loop, so stop when pages reaches 1,
523 * which is too small anyway.
524 */
525 while (pages > 1) {
526 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
527 &physical,
528 GFP_KERNEL | __GFP_NOWARN);
529 if (block)
530 break;
531
532 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
533 pages * PAGE_SIZE);
534
535 pages = DIV_ROUND_UP(pages, 2);
536 }
537
538 if (!block)
539 return -ENOMEM;
540
541 frag->physical = physical;
542 frag->block = block;
543 frag->size = pages * PAGE_SIZE;
544
545 return pages;
546}
547
548static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
549 enum iwl_fw_ini_allocation_id alloc_id)
550{
551 struct iwl_fw_mon *fw_mon;
552 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
553 u32 num_frags, remain_pages, frag_pages;
554 int i;
555
556 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
557 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
558 return -EIO;
559
560 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
561 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
562
563 if (fw_mon->num_frags ||
564 fw_mon_cfg->buf_location !=
565 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
566 return 0;
567
568 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
569 if (!fw_has_capa(&fwrt->fw->ucode_capa,
570 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) {
571 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
572 return -EIO;
573 num_frags = 1;
574 }
575
576 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
577 PAGE_SIZE);
578 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
579 num_frags = min_t(u32, num_frags, remain_pages);
580 frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
581
582 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
583 if (!fw_mon->frags)
584 return -ENOMEM;
585
586 for (i = 0; i < num_frags; i++) {
587 int pages = min_t(u32, frag_pages, remain_pages);
588
589 IWL_DEBUG_FW(fwrt,
590 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
591 alloc_id, i, pages * PAGE_SIZE);
592
593 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
594 pages);
595 if (pages < 0) {
596 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
597 (remain_pages * PAGE_SIZE);
598
599 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
600 iwl_dbg_tlv_fragments_free(fwrt->trans,
601 alloc_id);
602 return pages;
603 }
604 break;
605 }
606
607 remain_pages -= pages;
608 fw_mon->num_frags++;
609 }
610
611 return 0;
612}
613
614static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
615 enum iwl_fw_ini_allocation_id alloc_id)
616{
617 struct iwl_fw_mon *fw_mon;
618 u32 remain_frags, num_commands;
619 int i, fw_mon_idx = 0;
620
621 if (!fw_has_capa(&fwrt->fw->ucode_capa,
622 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
623 return 0;
624
625 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
626 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
627 return -EIO;
628
629 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
630 IWL_FW_INI_LOCATION_DRAM_PATH)
631 return 0;
632
633 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
634
635 /* the first fragment of DBGC1 is given to the FW via register
636 * or context info
637 */
638 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
639 fw_mon_idx++;
640
641 remain_frags = fw_mon->num_frags - fw_mon_idx;
642 if (!remain_frags)
643 return 0;
644
645 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
646
647 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
648 alloc_id);
649
650 for (i = 0; i < num_commands; i++) {
651 u32 num_frags = min_t(u32, remain_frags,
652 BUF_ALLOC_MAX_NUM_FRAGS);
653 struct iwl_buf_alloc_cmd data = {
654 .alloc_id = cpu_to_le32(alloc_id),
655 .num_frags = cpu_to_le32(num_frags),
656 .buf_location =
657 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
658 };
659 struct iwl_host_cmd hcmd = {
660 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
661 .data[0] = &data,
662 .len[0] = sizeof(data),
663 };
664 int ret, j;
665
666 for (j = 0; j < num_frags; j++) {
667 struct iwl_buf_alloc_frag *frag = &data.frags[j];
668 struct iwl_dram_data *fw_mon_frag =
669 &fw_mon->frags[fw_mon_idx++];
670
671 frag->addr = cpu_to_le64(fw_mon_frag->physical);
672 frag->size = cpu_to_le32(fw_mon_frag->size);
673 }
674 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
675 if (ret)
676 return ret;
677
678 remain_frags -= num_frags;
679 }
680
681 return 0;
682}
683
684static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
685{
686 int ret, i;
687
688 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
689 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
690 if (ret)
691 IWL_WARN(fwrt,
692 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
693 i, ret);
694 }
695}
696
697static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
698 struct list_head *hcmd_list)
699{
700 struct iwl_dbg_tlv_node *node;
701
702 list_for_each_entry(node, hcmd_list, list) {
703 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
704 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
705 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
706 struct iwl_host_cmd cmd = {
707 .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
708 .len = { hcmd_len, },
709 .data = { hcmd_data->data, },
710 };
711
712 iwl_trans_send_cmd(fwrt->trans, &cmd);
713 }
714}
715
716static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
717{
718 struct iwl_dbg_tlv_timer_node *timer_node =
719 from_timer(timer_node, t, timer);
720 struct iwl_fwrt_dump_data dump_data = {
721 .trig = (void *)timer_node->tlv->data,
722 };
723 int ret;
724
725 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data);
726 if (!ret || ret == -EBUSY) {
727 u32 occur = le32_to_cpu(dump_data.trig->occurrences);
728 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
729
730 if (!occur)
731 return;
732
733 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
734 }
735}
736
737static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
738{
739 struct iwl_dbg_tlv_node *node;
740 struct list_head *trig_list =
741 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
742
743 list_for_each_entry(node, trig_list, list) {
744 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
745 struct iwl_dbg_tlv_timer_node *timer_node;
746 u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
747 u32 min_interval = 100;
748
749 if (!occur)
750 continue;
751
752 /* make sure there is at least one dword of data for the
753 * interval value
754 */
755 if (le32_to_cpu(node->tlv.length) <
756 sizeof(*trig) + sizeof(__le32)) {
757 IWL_ERR(fwrt,
758 "WRT: Invalid periodic trigger data was not given\n");
759 continue;
760 }
761
762 if (le32_to_cpu(trig->data[0]) < min_interval) {
763 IWL_WARN(fwrt,
764 "WRT: Override min interval from %u to %u msec\n",
765 le32_to_cpu(trig->data[0]), min_interval);
766 trig->data[0] = cpu_to_le32(min_interval);
767 }
768
769 collect_interval = le32_to_cpu(trig->data[0]);
770
771 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
772 if (!timer_node) {
773 IWL_ERR(fwrt,
774 "WRT: Failed to allocate periodic trigger\n");
775 continue;
776 }
777
778 timer_node->fwrt = fwrt;
779 timer_node->tlv = &node->tlv;
780 timer_setup(&timer_node->timer,
781 iwl_dbg_tlv_periodic_trig_handler, 0);
782
783 list_add_tail(&timer_node->list,
784 &fwrt->trans->dbg.periodic_trig_list);
785
786 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
787
788 mod_timer(&timer_node->timer,
789 jiffies + msecs_to_jiffies(collect_interval));
790 }
791}
792
793static bool is_trig_data_contained(struct iwl_ucode_tlv *new,
794 struct iwl_ucode_tlv *old)
795{
796 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data;
797 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data;
798 __le32 *new_data = new_trig->data, *old_data = old_trig->data;
799 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
800 u32 old_dwords_num = iwl_tlv_array_len(new, new_trig, data);
801 int i, j;
802
803 for (i = 0; i < new_dwords_num; i++) {
804 bool match = false;
805
806 for (j = 0; j < old_dwords_num; j++) {
807 if (new_data[i] == old_data[j]) {
808 match = true;
809 break;
810 }
811 }
812 if (!match)
813 return false;
814 }
815
816 return true;
817}
818
819static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
820 struct iwl_ucode_tlv *trig_tlv,
821 struct iwl_dbg_tlv_node *node)
822{
823 struct iwl_ucode_tlv *node_tlv = &node->tlv;
824 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
825 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
826 u32 policy = le32_to_cpu(trig->apply_policy);
827 u32 size = le32_to_cpu(trig_tlv->length);
828 u32 trig_data_len = size - sizeof(*trig);
829 u32 offset = 0;
830
831 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
832 u32 data_len = le32_to_cpu(node_tlv->length) -
833 sizeof(*node_trig);
834
835 IWL_DEBUG_FW(fwrt,
836 "WRT: Appending trigger data (time point %u)\n",
837 le32_to_cpu(trig->time_point));
838
839 offset += data_len;
840 size += data_len;
841 } else {
842 IWL_DEBUG_FW(fwrt,
843 "WRT: Overriding trigger data (time point %u)\n",
844 le32_to_cpu(trig->time_point));
845 }
846
847 if (size != le32_to_cpu(node_tlv->length)) {
848 struct list_head *prev = node->list.prev;
849 struct iwl_dbg_tlv_node *tmp;
850
851 list_del(&node->list);
852
853 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
854 if (!tmp) {
855 IWL_WARN(fwrt,
856 "WRT: No memory to override trigger (time point %u)\n",
857 le32_to_cpu(trig->time_point));
858
859 list_add(&node->list, prev);
860
861 return -ENOMEM;
862 }
863
864 list_add(&tmp->list, prev);
865 node_tlv = &tmp->tlv;
866 node_trig = (void *)node_tlv->data;
867 }
868
869 memcpy(node_trig->data + offset, trig->data, trig_data_len);
870 node_tlv->length = cpu_to_le32(size);
871
872 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
873 IWL_DEBUG_FW(fwrt,
874 "WRT: Overriding trigger configuration (time point %u)\n",
875 le32_to_cpu(trig->time_point));
876
877 /* the first 11 dwords are configuration related */
878 memcpy(node_trig, trig, sizeof(__le32) * 11);
879 }
880
881 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
882 IWL_DEBUG_FW(fwrt,
883 "WRT: Overriding trigger regions (time point %u)\n",
884 le32_to_cpu(trig->time_point));
885
886 node_trig->regions_mask = trig->regions_mask;
887 } else {
888 IWL_DEBUG_FW(fwrt,
889 "WRT: Appending trigger regions (time point %u)\n",
890 le32_to_cpu(trig->time_point));
891
892 node_trig->regions_mask |= trig->regions_mask;
893 }
894
895 return 0;
896}
897
898static int
899iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
900 struct list_head *trig_list,
901 struct iwl_ucode_tlv *trig_tlv)
902{
903 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
904 struct iwl_dbg_tlv_node *node, *match = NULL;
905 u32 policy = le32_to_cpu(trig->apply_policy);
906
907 list_for_each_entry(node, trig_list, list) {
908 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
909 break;
910
911 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
912 is_trig_data_contained(trig_tlv, &node->tlv)) {
913 match = node;
914 break;
915 }
916 }
917
918 if (!match) {
919 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
920 le32_to_cpu(trig->time_point));
921 return iwl_dbg_tlv_add(trig_tlv, trig_list);
922 }
923
924 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
925}
926
927static void
928iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
929 struct iwl_dbg_tlv_time_point_data *tp)
930{
931 struct iwl_dbg_tlv_node *node;
932 struct list_head *trig_list = &tp->trig_list;
933 struct list_head *active_trig_list = &tp->active_trig_list;
934
935 list_for_each_entry(node, trig_list, list) {
936 struct iwl_ucode_tlv *tlv = &node->tlv;
937
938 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
939 }
940}
941
942static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
943 struct iwl_fwrt_dump_data *dump_data,
944 union iwl_dbg_tlv_tp_data *tp_data,
945 u32 trig_data)
946{
947 struct iwl_rx_packet *pkt = tp_data->fw_pkt;
948 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
949
950 if (pkt && ((wanted_hdr->cmd == 0 && wanted_hdr->group_id == 0) ||
951 (pkt->hdr.cmd == wanted_hdr->cmd &&
952 pkt->hdr.group_id == wanted_hdr->group_id))) {
953 struct iwl_rx_packet *fw_pkt =
954 kmemdup(pkt,
955 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
956 GFP_ATOMIC);
957
958 if (!fw_pkt)
959 return false;
960
961 dump_data->fw_pkt = fw_pkt;
962
963 return true;
964 }
965
966 return false;
967}
968
969static int
970iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt,
971 struct list_head *active_trig_list,
972 union iwl_dbg_tlv_tp_data *tp_data,
973 bool (*data_check)(struct iwl_fw_runtime *fwrt,
974 struct iwl_fwrt_dump_data *dump_data,
975 union iwl_dbg_tlv_tp_data *tp_data,
976 u32 trig_data))
977{
978 struct iwl_dbg_tlv_node *node;
979
980 list_for_each_entry(node, active_trig_list, list) {
981 struct iwl_fwrt_dump_data dump_data = {
982 .trig = (void *)node->tlv.data,
983 };
984 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
985 data);
986 int ret, i;
987
988 if (!num_data) {
989 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
990 if (ret)
991 return ret;
992 }
993
994 for (i = 0; i < num_data; i++) {
995 if (!data_check ||
996 data_check(fwrt, &dump_data, tp_data,
997 le32_to_cpu(dump_data.trig->data[i]))) {
998 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
999 if (ret)
1000 return ret;
1001
1002 break;
1003 }
1004 }
1005 }
1006
1007 return 0;
1008}
1009
1010static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1011{
1012 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1013 int ret, i;
1014
1015 IWL_DEBUG_FW(fwrt,
1016 "WRT: Generating active triggers list, domain 0x%x\n",
1017 fwrt->trans->dbg.domains_bitmap);
1018
1019 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1020 struct iwl_dbg_tlv_time_point_data *tp =
1021 &fwrt->trans->dbg.time_point[i];
1022
1023 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1024 }
1025
1026 *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1027 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1028 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1029 &fwrt->trans->dbg.fw_mon_cfg[i];
1030 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1031
1032 if (dest == IWL_FW_INI_LOCATION_INVALID)
1033 continue;
1034
1035 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1036 *ini_dest = dest;
1037
1038 if (dest != *ini_dest)
1039 continue;
1040
1041 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1042 if (ret)
1043 IWL_WARN(fwrt,
1044 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1045 i, ret);
1046 }
1047}
1048
1049void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1050 enum iwl_fw_ini_time_point tp_id,
1051 union iwl_dbg_tlv_tp_data *tp_data)
1052{
1053 struct list_head *hcmd_list, *trig_list;
1054
1055 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1056 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1057 tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1058 return;
1059
1060 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1061 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1062
1063 switch (tp_id) {
1064 case IWL_FW_INI_TIME_POINT_EARLY:
1065 iwl_dbg_tlv_init_cfg(fwrt);
1066 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1067 break;
1068 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1069 iwl_dbg_tlv_apply_buffers(fwrt);
1070 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1071 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1072 break;
1073 case IWL_FW_INI_TIME_POINT_PERIODIC:
1074 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1075 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1076 break;
1077 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1078 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1079 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1080 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data,
1081 iwl_dbg_tlv_check_fw_pkt);
1082 break;
1083 default:
1084 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1085 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1086 break;
1087 }
1088}
1089IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point);