Loading...
1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2022, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: pv-drivers@vmware.com
24 *
25 */
26
27#ifndef _VMXNET3_DEFS_H_
28#define _VMXNET3_DEFS_H_
29
30#include "upt1_defs.h"
31
32/* all registers are 32 bit wide */
33/* BAR 1 */
34enum {
35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
39 VMXNET3_REG_CMD = 0x20, /* Command */
40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
43 VMXNET3_REG_ECR = 0x40, /* Event Cause Register */
44 VMXNET3_REG_DCR = 0x48, /* Device capability register,
45 * from 0x48 to 0x80
46 */
47 VMXNET3_REG_PTCR = 0x88, /* Passthru capbility register
48 * from 0x88 to 0xb0
49 */
50};
51
52/* BAR 0 */
53enum {
54 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
55 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
56 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
57 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
58};
59
60/* For Large PT BAR, the following offset to DB register */
61enum {
62 VMXNET3_REG_LB_TXPROD = 0x1000, /* Tx Producer Index */
63 VMXNET3_REG_LB_RXPROD = 0x1400, /* Rx Producer Index for ring 1 */
64 VMXNET3_REG_LB_RXPROD2 = 0x1800, /* Rx Producer Index for ring 2 */
65};
66
67#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
68#define VMXNET3_LARGE_PT_REG_SIZE 8192 /* large PT pages */
69#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
70#define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */
71#define VMXNET3_OOB_REG_SIZE (4094 * 4096) /* OOB pages */
72
73#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
74#define VMXNET3_REG_ALIGN_MASK 0x7
75
76/* I/O Mapped access to registers */
77#define VMXNET3_IO_TYPE_PT 0
78#define VMXNET3_IO_TYPE_VD 1
79#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
80#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
81#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
82
83enum {
84 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
85 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
86 VMXNET3_CMD_QUIESCE_DEV,
87 VMXNET3_CMD_RESET_DEV,
88 VMXNET3_CMD_UPDATE_RX_MODE,
89 VMXNET3_CMD_UPDATE_MAC_FILTERS,
90 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
91 VMXNET3_CMD_UPDATE_RSSIDT,
92 VMXNET3_CMD_UPDATE_IML,
93 VMXNET3_CMD_UPDATE_PMCFG,
94 VMXNET3_CMD_UPDATE_FEATURE,
95 VMXNET3_CMD_RESERVED1,
96 VMXNET3_CMD_LOAD_PLUGIN,
97 VMXNET3_CMD_RESERVED2,
98 VMXNET3_CMD_RESERVED3,
99 VMXNET3_CMD_SET_COALESCE,
100 VMXNET3_CMD_REGISTER_MEMREGS,
101 VMXNET3_CMD_SET_RSS_FIELDS,
102 VMXNET3_CMD_RESERVED4,
103 VMXNET3_CMD_RESERVED5,
104 VMXNET3_CMD_SET_RING_BUFFER_SIZE,
105
106 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
107 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
108 VMXNET3_CMD_GET_STATS,
109 VMXNET3_CMD_GET_LINK,
110 VMXNET3_CMD_GET_PERM_MAC_LO,
111 VMXNET3_CMD_GET_PERM_MAC_HI,
112 VMXNET3_CMD_GET_DID_LO,
113 VMXNET3_CMD_GET_DID_HI,
114 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
115 VMXNET3_CMD_GET_CONF_INTR,
116 VMXNET3_CMD_GET_RESERVED1,
117 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
118 VMXNET3_CMD_GET_COALESCE,
119 VMXNET3_CMD_GET_RSS_FIELDS,
120 VMXNET3_CMD_GET_RESERVED2,
121 VMXNET3_CMD_GET_RESERVED3,
122 VMXNET3_CMD_GET_MAX_QUEUES_CONF,
123 VMXNET3_CMD_GET_RESERVED4,
124 VMXNET3_CMD_GET_MAX_CAPABILITIES,
125 VMXNET3_CMD_GET_DCR0_REG,
126};
127
128/*
129 * Little Endian layout of bitfields -
130 * Byte 0 : 7.....len.....0
131 * Byte 1 : oco gen 13.len.8
132 * Byte 2 : 5.msscof.0 ext1 dtype
133 * Byte 3 : 13...msscof...6
134 *
135 * Big Endian layout of bitfields -
136 * Byte 0: 13...msscof...6
137 * Byte 1 : 5.msscof.0 ext1 dtype
138 * Byte 2 : oco gen 13.len.8
139 * Byte 3 : 7.....len.....0
140 *
141 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
142 * the bit fields correctly. And cpu_to_le32 will convert bitfields
143 * bit fields written by big endian driver to format required by device.
144 */
145
146struct Vmxnet3_TxDesc {
147 __le64 addr;
148
149#ifdef __BIG_ENDIAN_BITFIELD
150 u32 msscof:14; /* MSS, checksum offset, flags */
151 u32 ext1:1; /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */
152 u32 dtype:1; /* descriptor type */
153 u32 oco:1; /* Outer csum offload */
154 u32 gen:1; /* generation bit */
155 u32 len:14;
156#else
157 u32 len:14;
158 u32 gen:1; /* generation bit */
159 u32 oco:1; /* Outer csum offload */
160 u32 dtype:1; /* descriptor type */
161 u32 ext1:1; /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */
162 u32 msscof:14; /* MSS, checksum offset, flags */
163#endif /* __BIG_ENDIAN_BITFIELD */
164
165#ifdef __BIG_ENDIAN_BITFIELD
166 u32 tci:16; /* Tag to Insert */
167 u32 ti:1; /* VLAN Tag Insertion */
168 u32 ext2:1;
169 u32 cq:1; /* completion request */
170 u32 eop:1; /* End Of Packet */
171 u32 om:2; /* offload mode */
172 u32 hlen:10; /* header len */
173#else
174 u32 hlen:10; /* header len */
175 u32 om:2; /* offload mode */
176 u32 eop:1; /* End Of Packet */
177 u32 cq:1; /* completion request */
178 u32 ext2:1;
179 u32 ti:1; /* VLAN Tag Insertion */
180 u32 tci:16; /* Tag to Insert */
181#endif /* __BIG_ENDIAN_BITFIELD */
182};
183
184/* TxDesc.OM values */
185#define VMXNET3_OM_NONE 0
186#define VMXNET3_OM_ENCAP 1
187#define VMXNET3_OM_CSUM 2
188#define VMXNET3_OM_TSO 3
189
190/* fields in TxDesc we access w/o using bit fields */
191#define VMXNET3_TXD_EOP_SHIFT 12
192#define VMXNET3_TXD_CQ_SHIFT 13
193#define VMXNET3_TXD_GEN_SHIFT 14
194#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
195#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
196
197#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
198#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
199#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
200
201#define VMXNET3_HDR_COPY_SIZE 128
202
203
204struct Vmxnet3_TxDataDesc {
205 u8 data[VMXNET3_HDR_COPY_SIZE];
206};
207
208typedef u8 Vmxnet3_RxDataDesc;
209
210#define VMXNET3_TCD_GEN_SHIFT 31
211#define VMXNET3_TCD_GEN_SIZE 1
212#define VMXNET3_TCD_TXIDX_SHIFT 0
213#define VMXNET3_TCD_TXIDX_SIZE 12
214#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
215
216struct Vmxnet3_TxCompDesc {
217 u32 txdIdx:12; /* Index of the EOP TxDesc */
218 u32 ext1:20;
219
220 __le32 ext2;
221 __le32 ext3;
222
223 u32 rsvd:24;
224 u32 type:7; /* completion type */
225 u32 gen:1; /* generation bit */
226};
227
228struct Vmxnet3_RxDesc {
229 __le64 addr;
230
231#ifdef __BIG_ENDIAN_BITFIELD
232 u32 gen:1; /* Generation bit */
233 u32 rsvd:15;
234 u32 dtype:1; /* Descriptor type */
235 u32 btype:1; /* Buffer Type */
236 u32 len:14;
237#else
238 u32 len:14;
239 u32 btype:1; /* Buffer Type */
240 u32 dtype:1; /* Descriptor type */
241 u32 rsvd:15;
242 u32 gen:1; /* Generation bit */
243#endif
244 u32 ext1;
245};
246
247/* values of RXD.BTYPE */
248#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
249#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
250
251/* fields in RxDesc we access w/o using bit fields */
252#define VMXNET3_RXD_BTYPE_SHIFT 14
253#define VMXNET3_RXD_GEN_SHIFT 31
254
255#define VMXNET3_RCD_HDR_INNER_SHIFT 13
256
257struct Vmxnet3_RxCompDesc {
258#ifdef __BIG_ENDIAN_BITFIELD
259 u32 ext2:1;
260 u32 cnc:1; /* Checksum Not Calculated */
261 u32 rssType:4; /* RSS hash type used */
262 u32 rqID:10; /* rx queue/ring ID */
263 u32 sop:1; /* Start of Packet */
264 u32 eop:1; /* End of Packet */
265 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
266 /* bit 1: indicating rssType is based on inner header */
267 u32 rxdIdx:12; /* Index of the RxDesc */
268#else
269 u32 rxdIdx:12; /* Index of the RxDesc */
270 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
271 /* bit 1: indicating rssType is based on inner header */
272 u32 eop:1; /* End of Packet */
273 u32 sop:1; /* Start of Packet */
274 u32 rqID:10; /* rx queue/ring ID */
275 u32 rssType:4; /* RSS hash type used */
276 u32 cnc:1; /* Checksum Not Calculated */
277 u32 ext2:1;
278#endif /* __BIG_ENDIAN_BITFIELD */
279
280 __le32 rssHash; /* RSS hash value */
281
282#ifdef __BIG_ENDIAN_BITFIELD
283 u32 tci:16; /* Tag stripped */
284 u32 ts:1; /* Tag is stripped */
285 u32 err:1; /* Error */
286 u32 len:14; /* data length */
287#else
288 u32 len:14; /* data length */
289 u32 err:1; /* Error */
290 u32 ts:1; /* Tag is stripped */
291 u32 tci:16; /* Tag stripped */
292#endif /* __BIG_ENDIAN_BITFIELD */
293
294
295#ifdef __BIG_ENDIAN_BITFIELD
296 u32 gen:1; /* generation bit */
297 u32 type:7; /* completion type */
298 u32 fcs:1; /* Frame CRC correct */
299 u32 frg:1; /* IP Fragment */
300 u32 v4:1; /* IPv4 */
301 u32 v6:1; /* IPv6 */
302 u32 ipc:1; /* IP Checksum Correct */
303 u32 tcp:1; /* TCP packet */
304 u32 udp:1; /* UDP packet */
305 u32 tuc:1; /* TCP/UDP Checksum Correct */
306 u32 csum:16;
307#else
308 u32 csum:16;
309 u32 tuc:1; /* TCP/UDP Checksum Correct */
310 u32 udp:1; /* UDP packet */
311 u32 tcp:1; /* TCP packet */
312 u32 ipc:1; /* IP Checksum Correct */
313 u32 v6:1; /* IPv6 */
314 u32 v4:1; /* IPv4 */
315 u32 frg:1; /* IP Fragment */
316 u32 fcs:1; /* Frame CRC correct */
317 u32 type:7; /* completion type */
318 u32 gen:1; /* generation bit */
319#endif /* __BIG_ENDIAN_BITFIELD */
320};
321
322struct Vmxnet3_RxCompDescExt {
323 __le32 dword1;
324 u8 segCnt; /* Number of aggregated packets */
325 u8 dupAckCnt; /* Number of duplicate Acks */
326 __le16 tsDelta; /* TCP timestamp difference */
327 __le32 dword2;
328#ifdef __BIG_ENDIAN_BITFIELD
329 u32 gen:1; /* generation bit */
330 u32 type:7; /* completion type */
331 u32 fcs:1; /* Frame CRC correct */
332 u32 frg:1; /* IP Fragment */
333 u32 v4:1; /* IPv4 */
334 u32 v6:1; /* IPv6 */
335 u32 ipc:1; /* IP Checksum Correct */
336 u32 tcp:1; /* TCP packet */
337 u32 udp:1; /* UDP packet */
338 u32 tuc:1; /* TCP/UDP Checksum Correct */
339 u32 mss:16;
340#else
341 u32 mss:16;
342 u32 tuc:1; /* TCP/UDP Checksum Correct */
343 u32 udp:1; /* UDP packet */
344 u32 tcp:1; /* TCP packet */
345 u32 ipc:1; /* IP Checksum Correct */
346 u32 v6:1; /* IPv6 */
347 u32 v4:1; /* IPv4 */
348 u32 frg:1; /* IP Fragment */
349 u32 fcs:1; /* Frame CRC correct */
350 u32 type:7; /* completion type */
351 u32 gen:1; /* generation bit */
352#endif /* __BIG_ENDIAN_BITFIELD */
353};
354
355
356/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
357#define VMXNET3_RCD_TUC_SHIFT 16
358#define VMXNET3_RCD_IPC_SHIFT 19
359
360/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
361#define VMXNET3_RCD_TYPE_SHIFT 56
362#define VMXNET3_RCD_GEN_SHIFT 63
363
364/* csum OK for TCP/UDP pkts over IP */
365#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
366 1 << VMXNET3_RCD_IPC_SHIFT)
367#define VMXNET3_TXD_GEN_SIZE 1
368#define VMXNET3_TXD_EOP_SIZE 1
369
370/* value of RxCompDesc.rssType */
371#define VMXNET3_RCD_RSS_TYPE_NONE 0
372#define VMXNET3_RCD_RSS_TYPE_IPV4 1
373#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
374#define VMXNET3_RCD_RSS_TYPE_IPV6 3
375#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
376#define VMXNET3_RCD_RSS_TYPE_UDPIPV4 5
377#define VMXNET3_RCD_RSS_TYPE_UDPIPV6 6
378#define VMXNET3_RCD_RSS_TYPE_ESPIPV4 7
379#define VMXNET3_RCD_RSS_TYPE_ESPIPV6 8
380
381
382/* a union for accessing all cmd/completion descriptors */
383union Vmxnet3_GenericDesc {
384 __le64 qword[2];
385 __le32 dword[4];
386 __le16 word[8];
387 struct Vmxnet3_TxDesc txd;
388 struct Vmxnet3_RxDesc rxd;
389 struct Vmxnet3_TxCompDesc tcd;
390 struct Vmxnet3_RxCompDesc rcd;
391 struct Vmxnet3_RxCompDescExt rcdExt;
392};
393
394#define VMXNET3_INIT_GEN 1
395
396/* Max size of a single tx buffer */
397#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
398
399/* # of tx desc needed for a tx buffer size */
400#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
401 VMXNET3_MAX_TX_BUF_SIZE)
402
403/* max # of tx descs for a non-tso pkt */
404#define VMXNET3_MAX_TXD_PER_PKT 16
405/* max # of tx descs for a tso pkt */
406#define VMXNET3_MAX_TSO_TXD_PER_PKT 24
407
408/* Max size of a single rx buffer */
409#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
410/* Minimum size of a type 0 buffer */
411#define VMXNET3_MIN_T0_BUF_SIZE 128
412#define VMXNET3_MAX_CSUM_OFFSET 1024
413
414/* Ring base address alignment */
415#define VMXNET3_RING_BA_ALIGN 512
416#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
417
418/* Ring size must be a multiple of 32 */
419#define VMXNET3_RING_SIZE_ALIGN 32
420#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
421
422/* Tx Data Ring buffer size must be a multiple of 64 */
423#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
424#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
425
426/* Rx Data Ring buffer size must be a multiple of 64 */
427#define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
428#define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
429
430/* Max ring size */
431#define VMXNET3_TX_RING_MAX_SIZE 4096
432#define VMXNET3_TC_RING_MAX_SIZE 4096
433#define VMXNET3_RX_RING_MAX_SIZE 4096
434#define VMXNET3_RX_RING2_MAX_SIZE 4096
435#define VMXNET3_RC_RING_MAX_SIZE 8192
436
437#define VMXNET3_TXDATA_DESC_MIN_SIZE 128
438#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
439
440#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
441
442/* a list of reasons for queue stop */
443
444enum {
445 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
446 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
447 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
448 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
449 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
450 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
451 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
452 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
453};
454
455/* completion descriptor types */
456#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
457#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
458#define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
459
460enum {
461 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
462 VMXNET3_GOS_BITS_32 = 1,
463 VMXNET3_GOS_BITS_64 = 2,
464};
465
466#define VMXNET3_GOS_TYPE_LINUX 1
467
468
469struct Vmxnet3_GOSInfo {
470#ifdef __BIG_ENDIAN_BITFIELD
471 u32 gosMisc:10; /* other info about gos */
472 u32 gosVer:16; /* gos version */
473 u32 gosType:4; /* which guest */
474 u32 gosBits:2; /* 32-bit or 64-bit? */
475#else
476 u32 gosBits:2; /* 32-bit or 64-bit? */
477 u32 gosType:4; /* which guest */
478 u32 gosVer:16; /* gos version */
479 u32 gosMisc:10; /* other info about gos */
480#endif /* __BIG_ENDIAN_BITFIELD */
481};
482
483struct Vmxnet3_DriverInfo {
484 __le32 version;
485 struct Vmxnet3_GOSInfo gos;
486 __le32 vmxnet3RevSpt;
487 __le32 uptVerSpt;
488};
489
490
491#define VMXNET3_REV1_MAGIC 3133079265u
492
493/*
494 * QueueDescPA must be 128 bytes aligned. It points to an array of
495 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
496 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
497 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
498 */
499#define VMXNET3_QUEUE_DESC_ALIGN 128
500
501
502struct Vmxnet3_MiscConf {
503 struct Vmxnet3_DriverInfo driverInfo;
504 __le64 uptFeatures;
505 __le64 ddPA; /* driver data PA */
506 __le64 queueDescPA; /* queue descriptor table PA */
507 __le32 ddLen; /* driver data len */
508 __le32 queueDescLen; /* queue desc. table len in bytes */
509 __le32 mtu;
510 __le16 maxNumRxSG;
511 u8 numTxQueues;
512 u8 numRxQueues;
513 __le32 reserved[4];
514};
515
516
517struct Vmxnet3_TxQueueConf {
518 __le64 txRingBasePA;
519 __le64 dataRingBasePA;
520 __le64 compRingBasePA;
521 __le64 ddPA; /* driver data */
522 __le64 reserved;
523 __le32 txRingSize; /* # of tx desc */
524 __le32 dataRingSize; /* # of data desc */
525 __le32 compRingSize; /* # of comp desc */
526 __le32 ddLen; /* size of driver data */
527 u8 intrIdx;
528 u8 _pad1[1];
529 __le16 txDataRingDescSize;
530 u8 _pad2[4];
531};
532
533
534struct Vmxnet3_RxQueueConf {
535 __le64 rxRingBasePA[2];
536 __le64 compRingBasePA;
537 __le64 ddPA; /* driver data */
538 __le64 rxDataRingBasePA;
539 __le32 rxRingSize[2]; /* # of rx desc */
540 __le32 compRingSize; /* # of rx comp desc */
541 __le32 ddLen; /* size of driver data */
542 u8 intrIdx;
543 u8 _pad1[1];
544 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
545 u8 _pad2[4];
546};
547
548
549enum vmxnet3_intr_mask_mode {
550 VMXNET3_IMM_AUTO = 0,
551 VMXNET3_IMM_ACTIVE = 1,
552 VMXNET3_IMM_LAZY = 2
553};
554
555enum vmxnet3_intr_type {
556 VMXNET3_IT_AUTO = 0,
557 VMXNET3_IT_INTX = 1,
558 VMXNET3_IT_MSI = 2,
559 VMXNET3_IT_MSIX = 3
560};
561
562#define VMXNET3_MAX_TX_QUEUES 8
563#define VMXNET3_MAX_RX_QUEUES 16
564/* addition 1 for events */
565#define VMXNET3_MAX_INTRS 25
566
567/* Version 6 and later will use below macros */
568#define VMXNET3_EXT_MAX_TX_QUEUES 32
569#define VMXNET3_EXT_MAX_RX_QUEUES 32
570/* addition 1 for events */
571#define VMXNET3_EXT_MAX_INTRS 65
572#define VMXNET3_FIRST_SET_INTRS 64
573
574/* value of intrCtrl */
575#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
576
577
578struct Vmxnet3_IntrConf {
579 bool autoMask;
580 u8 numIntrs; /* # of interrupts */
581 u8 eventIntrIdx;
582 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
583 * each intr */
584 __le32 intrCtrl;
585 __le32 reserved[2];
586};
587
588struct Vmxnet3_IntrConfExt {
589 u8 autoMask;
590 u8 numIntrs; /* # of interrupts */
591 u8 eventIntrIdx;
592 u8 reserved;
593 __le32 intrCtrl;
594 __le32 reserved1;
595 u8 modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for
596 * each intr
597 */
598 u8 reserved2[3];
599};
600
601/* one bit per VLAN ID, the size is in the units of u32 */
602#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
603
604
605struct Vmxnet3_QueueStatus {
606 bool stopped;
607 u8 _pad[3];
608 __le32 error;
609};
610
611
612struct Vmxnet3_TxQueueCtrl {
613 __le32 txNumDeferred;
614 __le32 txThreshold;
615 __le64 reserved;
616};
617
618
619struct Vmxnet3_RxQueueCtrl {
620 bool updateRxProd;
621 u8 _pad[7];
622 __le64 reserved;
623};
624
625enum {
626 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
627 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
628 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
629 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
630 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
631};
632
633struct Vmxnet3_RxFilterConf {
634 __le32 rxMode; /* VMXNET3_RXM_xxx */
635 __le16 mfTableLen; /* size of the multicast filter table */
636 __le16 _pad1;
637 __le64 mfTablePA; /* PA of the multicast filters table */
638 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
639};
640
641
642#define VMXNET3_PM_MAX_FILTERS 6
643#define VMXNET3_PM_MAX_PATTERN_SIZE 128
644#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
645
646#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
647#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
648 * filters */
649
650
651struct Vmxnet3_PM_PktFilter {
652 u8 maskSize;
653 u8 patternSize;
654 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
655 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
656 u8 pad[6];
657};
658
659
660struct Vmxnet3_PMConf {
661 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
662 u8 numFilters;
663 u8 pad[5];
664 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
665};
666
667
668struct Vmxnet3_VariableLenConfDesc {
669 __le32 confVer;
670 __le32 confLen;
671 __le64 confPA;
672};
673
674
675struct Vmxnet3_TxQueueDesc {
676 struct Vmxnet3_TxQueueCtrl ctrl;
677 struct Vmxnet3_TxQueueConf conf;
678
679 /* Driver read after a GET command */
680 struct Vmxnet3_QueueStatus status;
681 struct UPT1_TxStats stats;
682 u8 _pad[88]; /* 128 aligned */
683};
684
685
686struct Vmxnet3_RxQueueDesc {
687 struct Vmxnet3_RxQueueCtrl ctrl;
688 struct Vmxnet3_RxQueueConf conf;
689 /* Driver read after a GET commad */
690 struct Vmxnet3_QueueStatus status;
691 struct UPT1_RxStats stats;
692 u8 __pad[88]; /* 128 aligned */
693};
694
695struct Vmxnet3_SetPolling {
696 u8 enablePolling;
697};
698
699#define VMXNET3_COAL_STATIC_MAX_DEPTH 128
700#define VMXNET3_COAL_RBC_MIN_RATE 100
701#define VMXNET3_COAL_RBC_MAX_RATE 100000
702
703enum Vmxnet3_CoalesceMode {
704 VMXNET3_COALESCE_DISABLED = 0,
705 VMXNET3_COALESCE_ADAPT = 1,
706 VMXNET3_COALESCE_STATIC = 2,
707 VMXNET3_COALESCE_RBC = 3
708};
709
710struct Vmxnet3_CoalesceRbc {
711 u32 rbc_rate;
712};
713
714struct Vmxnet3_CoalesceStatic {
715 u32 tx_depth;
716 u32 tx_comp_depth;
717 u32 rx_depth;
718};
719
720struct Vmxnet3_CoalesceScheme {
721 enum Vmxnet3_CoalesceMode coalMode;
722 union {
723 struct Vmxnet3_CoalesceRbc coalRbc;
724 struct Vmxnet3_CoalesceStatic coalStatic;
725 } coalPara;
726};
727
728struct Vmxnet3_MemoryRegion {
729 __le64 startPA;
730 __le32 length;
731 __le16 txQueueBits;
732 __le16 rxQueueBits;
733};
734
735#define MAX_MEMORY_REGION_PER_QUEUE 16
736#define MAX_MEMORY_REGION_PER_DEVICE 256
737
738struct Vmxnet3_MemRegs {
739 __le16 numRegs;
740 __le16 pad[3];
741 struct Vmxnet3_MemoryRegion memRegs[1];
742};
743
744enum Vmxnet3_RSSField {
745 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
746 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
747 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
748 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
749 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
750 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
751};
752
753struct Vmxnet3_RingBufferSize {
754 __le16 ring1BufSizeType0;
755 __le16 ring1BufSizeType1;
756 __le16 ring2BufSizeType1;
757 __le16 pad;
758};
759
760/* If the command data <= 16 bytes, use the shared memory directly.
761 * otherwise, use variable length configuration descriptor.
762 */
763union Vmxnet3_CmdInfo {
764 struct Vmxnet3_VariableLenConfDesc varConf;
765 struct Vmxnet3_SetPolling setPolling;
766 enum Vmxnet3_RSSField setRssFields;
767 struct Vmxnet3_RingBufferSize ringBufSize;
768 __le64 data[2];
769};
770
771struct Vmxnet3_DSDevRead {
772 /* read-only region for device, read by dev in response to a SET cmd */
773 struct Vmxnet3_MiscConf misc;
774 struct Vmxnet3_IntrConf intrConf;
775 struct Vmxnet3_RxFilterConf rxFilterConf;
776 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
777 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
778 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
779};
780
781struct Vmxnet3_DSDevReadExt {
782 /* read-only region for device, read by dev in response to a SET cmd */
783 struct Vmxnet3_IntrConfExt intrConfExt;
784};
785
786/* All structures in DriverShared are padded to multiples of 8 bytes */
787struct Vmxnet3_DriverShared {
788 __le32 magic;
789 /* make devRead start at 64bit boundaries */
790 __le32 size; /* size of DriverShared */
791 struct Vmxnet3_DSDevRead devRead;
792 __le32 ecr;
793 __le32 reserved;
794 union {
795 __le32 reserved1[4];
796 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of
797 * executing the relevant
798 * command
799 */
800 } cu;
801 struct Vmxnet3_DSDevReadExt devReadExt;
802};
803
804
805#define VMXNET3_ECR_RQERR (1 << 0)
806#define VMXNET3_ECR_TQERR (1 << 1)
807#define VMXNET3_ECR_LINK (1 << 2)
808#define VMXNET3_ECR_DIC (1 << 3)
809#define VMXNET3_ECR_DEBUG (1 << 4)
810
811/* flip the gen bit of a ring */
812#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
813
814/* only use this if moving the idx won't affect the gen bit */
815#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
816 do {\
817 (idx)++;\
818 if (unlikely((idx) == (ring_size))) {\
819 (idx) = 0;\
820 } \
821 } while (0)
822
823#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
824 (vfTable[vid >> 5] |= (1 << (vid & 31)))
825#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
826 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
827
828#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
829 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
830
831#define VMXNET3_MAX_MTU 9000
832#define VMXNET3_V6_MAX_MTU 9190
833#define VMXNET3_MIN_MTU 60
834
835#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
836#define VMXNET3_LINK_DOWN 0
837
838#define VMXNET3_DCR_ERROR 31 /* error when bit 31 of DCR is set */
839#define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */
840#define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */
841#define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */
842#define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */
843#define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */
844#define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */
845#define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */
846#define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */
847#define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */
848#define VMXNET3_CAP_VERSION_4_MAX VMXNET3_CAP_PKT_STEERING_IPV4
849#define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */
850#define VMXNET3_CAP_VERSION_5_MAX VMXNET3_CAP_ESP_RSS_IPV6
851#define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */
852#define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */
853#define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */
854#define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */
855#define VMXNET3_CAP_VERSION_6_MAX VMXNET3_CAP_CRC32_HASH_FUNC
856#define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */
857#define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */
858#define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */
859#define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */
860#define VMXNET3_CAP_VERSION_7_MAX 18
861/* when new capability is introduced, update VMXNET3_CAP_MAX */
862#define VMXNET3_CAP_MAX VMXNET3_CAP_VERSION_7_MAX
863
864#endif /* _VMXNET3_DEFS_H_ */
1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: pv-drivers@vmware.com
24 *
25 */
26
27#ifndef _VMXNET3_DEFS_H_
28#define _VMXNET3_DEFS_H_
29
30#include "upt1_defs.h"
31
32/* all registers are 32 bit wide */
33/* BAR 1 */
34enum {
35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
39 VMXNET3_REG_CMD = 0x20, /* Command */
40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
43 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
44};
45
46/* BAR 0 */
47enum {
48 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
49 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
50 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
52};
53
54#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
55#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
56
57#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
58#define VMXNET3_REG_ALIGN_MASK 0x7
59
60/* I/O Mapped access to registers */
61#define VMXNET3_IO_TYPE_PT 0
62#define VMXNET3_IO_TYPE_VD 1
63#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
64#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
65#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
66
67enum {
68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
70 VMXNET3_CMD_QUIESCE_DEV,
71 VMXNET3_CMD_RESET_DEV,
72 VMXNET3_CMD_UPDATE_RX_MODE,
73 VMXNET3_CMD_UPDATE_MAC_FILTERS,
74 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
75 VMXNET3_CMD_UPDATE_RSSIDT,
76 VMXNET3_CMD_UPDATE_IML,
77 VMXNET3_CMD_UPDATE_PMCFG,
78 VMXNET3_CMD_UPDATE_FEATURE,
79 VMXNET3_CMD_RESERVED1,
80 VMXNET3_CMD_LOAD_PLUGIN,
81 VMXNET3_CMD_RESERVED2,
82 VMXNET3_CMD_RESERVED3,
83 VMXNET3_CMD_SET_COALESCE,
84 VMXNET3_CMD_REGISTER_MEMREGS,
85 VMXNET3_CMD_SET_RSS_FIELDS,
86
87 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
88 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
89 VMXNET3_CMD_GET_STATS,
90 VMXNET3_CMD_GET_LINK,
91 VMXNET3_CMD_GET_PERM_MAC_LO,
92 VMXNET3_CMD_GET_PERM_MAC_HI,
93 VMXNET3_CMD_GET_DID_LO,
94 VMXNET3_CMD_GET_DID_HI,
95 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
96 VMXNET3_CMD_GET_CONF_INTR,
97 VMXNET3_CMD_GET_RESERVED1,
98 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
99 VMXNET3_CMD_GET_COALESCE,
100 VMXNET3_CMD_GET_RSS_FIELDS,
101};
102
103/*
104 * Little Endian layout of bitfields -
105 * Byte 0 : 7.....len.....0
106 * Byte 1 : oco gen 13.len.8
107 * Byte 2 : 5.msscof.0 ext1 dtype
108 * Byte 3 : 13...msscof...6
109 *
110 * Big Endian layout of bitfields -
111 * Byte 0: 13...msscof...6
112 * Byte 1 : 5.msscof.0 ext1 dtype
113 * Byte 2 : oco gen 13.len.8
114 * Byte 3 : 7.....len.....0
115 *
116 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
117 * the bit fields correctly. And cpu_to_le32 will convert bitfields
118 * bit fields written by big endian driver to format required by device.
119 */
120
121struct Vmxnet3_TxDesc {
122 __le64 addr;
123
124#ifdef __BIG_ENDIAN_BITFIELD
125 u32 msscof:14; /* MSS, checksum offset, flags */
126 u32 ext1:1;
127 u32 dtype:1; /* descriptor type */
128 u32 oco:1;
129 u32 gen:1; /* generation bit */
130 u32 len:14;
131#else
132 u32 len:14;
133 u32 gen:1; /* generation bit */
134 u32 oco:1;
135 u32 dtype:1; /* descriptor type */
136 u32 ext1:1;
137 u32 msscof:14; /* MSS, checksum offset, flags */
138#endif /* __BIG_ENDIAN_BITFIELD */
139
140#ifdef __BIG_ENDIAN_BITFIELD
141 u32 tci:16; /* Tag to Insert */
142 u32 ti:1; /* VLAN Tag Insertion */
143 u32 ext2:1;
144 u32 cq:1; /* completion request */
145 u32 eop:1; /* End Of Packet */
146 u32 om:2; /* offload mode */
147 u32 hlen:10; /* header len */
148#else
149 u32 hlen:10; /* header len */
150 u32 om:2; /* offload mode */
151 u32 eop:1; /* End Of Packet */
152 u32 cq:1; /* completion request */
153 u32 ext2:1;
154 u32 ti:1; /* VLAN Tag Insertion */
155 u32 tci:16; /* Tag to Insert */
156#endif /* __BIG_ENDIAN_BITFIELD */
157};
158
159/* TxDesc.OM values */
160#define VMXNET3_OM_NONE 0
161#define VMXNET3_OM_ENCAP 1
162#define VMXNET3_OM_CSUM 2
163#define VMXNET3_OM_TSO 3
164
165/* fields in TxDesc we access w/o using bit fields */
166#define VMXNET3_TXD_EOP_SHIFT 12
167#define VMXNET3_TXD_CQ_SHIFT 13
168#define VMXNET3_TXD_GEN_SHIFT 14
169#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
170#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
171
172#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
173#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
174#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
175
176#define VMXNET3_HDR_COPY_SIZE 128
177
178
179struct Vmxnet3_TxDataDesc {
180 u8 data[VMXNET3_HDR_COPY_SIZE];
181};
182
183typedef u8 Vmxnet3_RxDataDesc;
184
185#define VMXNET3_TCD_GEN_SHIFT 31
186#define VMXNET3_TCD_GEN_SIZE 1
187#define VMXNET3_TCD_TXIDX_SHIFT 0
188#define VMXNET3_TCD_TXIDX_SIZE 12
189#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
190
191struct Vmxnet3_TxCompDesc {
192 u32 txdIdx:12; /* Index of the EOP TxDesc */
193 u32 ext1:20;
194
195 __le32 ext2;
196 __le32 ext3;
197
198 u32 rsvd:24;
199 u32 type:7; /* completion type */
200 u32 gen:1; /* generation bit */
201};
202
203struct Vmxnet3_RxDesc {
204 __le64 addr;
205
206#ifdef __BIG_ENDIAN_BITFIELD
207 u32 gen:1; /* Generation bit */
208 u32 rsvd:15;
209 u32 dtype:1; /* Descriptor type */
210 u32 btype:1; /* Buffer Type */
211 u32 len:14;
212#else
213 u32 len:14;
214 u32 btype:1; /* Buffer Type */
215 u32 dtype:1; /* Descriptor type */
216 u32 rsvd:15;
217 u32 gen:1; /* Generation bit */
218#endif
219 u32 ext1;
220};
221
222/* values of RXD.BTYPE */
223#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
224#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
225
226/* fields in RxDesc we access w/o using bit fields */
227#define VMXNET3_RXD_BTYPE_SHIFT 14
228#define VMXNET3_RXD_GEN_SHIFT 31
229
230#define VMXNET3_RCD_HDR_INNER_SHIFT 13
231
232struct Vmxnet3_RxCompDesc {
233#ifdef __BIG_ENDIAN_BITFIELD
234 u32 ext2:1;
235 u32 cnc:1; /* Checksum Not Calculated */
236 u32 rssType:4; /* RSS hash type used */
237 u32 rqID:10; /* rx queue/ring ID */
238 u32 sop:1; /* Start of Packet */
239 u32 eop:1; /* End of Packet */
240 u32 ext1:2;
241 u32 rxdIdx:12; /* Index of the RxDesc */
242#else
243 u32 rxdIdx:12; /* Index of the RxDesc */
244 u32 ext1:2;
245 u32 eop:1; /* End of Packet */
246 u32 sop:1; /* Start of Packet */
247 u32 rqID:10; /* rx queue/ring ID */
248 u32 rssType:4; /* RSS hash type used */
249 u32 cnc:1; /* Checksum Not Calculated */
250 u32 ext2:1;
251#endif /* __BIG_ENDIAN_BITFIELD */
252
253 __le32 rssHash; /* RSS hash value */
254
255#ifdef __BIG_ENDIAN_BITFIELD
256 u32 tci:16; /* Tag stripped */
257 u32 ts:1; /* Tag is stripped */
258 u32 err:1; /* Error */
259 u32 len:14; /* data length */
260#else
261 u32 len:14; /* data length */
262 u32 err:1; /* Error */
263 u32 ts:1; /* Tag is stripped */
264 u32 tci:16; /* Tag stripped */
265#endif /* __BIG_ENDIAN_BITFIELD */
266
267
268#ifdef __BIG_ENDIAN_BITFIELD
269 u32 gen:1; /* generation bit */
270 u32 type:7; /* completion type */
271 u32 fcs:1; /* Frame CRC correct */
272 u32 frg:1; /* IP Fragment */
273 u32 v4:1; /* IPv4 */
274 u32 v6:1; /* IPv6 */
275 u32 ipc:1; /* IP Checksum Correct */
276 u32 tcp:1; /* TCP packet */
277 u32 udp:1; /* UDP packet */
278 u32 tuc:1; /* TCP/UDP Checksum Correct */
279 u32 csum:16;
280#else
281 u32 csum:16;
282 u32 tuc:1; /* TCP/UDP Checksum Correct */
283 u32 udp:1; /* UDP packet */
284 u32 tcp:1; /* TCP packet */
285 u32 ipc:1; /* IP Checksum Correct */
286 u32 v6:1; /* IPv6 */
287 u32 v4:1; /* IPv4 */
288 u32 frg:1; /* IP Fragment */
289 u32 fcs:1; /* Frame CRC correct */
290 u32 type:7; /* completion type */
291 u32 gen:1; /* generation bit */
292#endif /* __BIG_ENDIAN_BITFIELD */
293};
294
295struct Vmxnet3_RxCompDescExt {
296 __le32 dword1;
297 u8 segCnt; /* Number of aggregated packets */
298 u8 dupAckCnt; /* Number of duplicate Acks */
299 __le16 tsDelta; /* TCP timestamp difference */
300 __le32 dword2;
301#ifdef __BIG_ENDIAN_BITFIELD
302 u32 gen:1; /* generation bit */
303 u32 type:7; /* completion type */
304 u32 fcs:1; /* Frame CRC correct */
305 u32 frg:1; /* IP Fragment */
306 u32 v4:1; /* IPv4 */
307 u32 v6:1; /* IPv6 */
308 u32 ipc:1; /* IP Checksum Correct */
309 u32 tcp:1; /* TCP packet */
310 u32 udp:1; /* UDP packet */
311 u32 tuc:1; /* TCP/UDP Checksum Correct */
312 u32 mss:16;
313#else
314 u32 mss:16;
315 u32 tuc:1; /* TCP/UDP Checksum Correct */
316 u32 udp:1; /* UDP packet */
317 u32 tcp:1; /* TCP packet */
318 u32 ipc:1; /* IP Checksum Correct */
319 u32 v6:1; /* IPv6 */
320 u32 v4:1; /* IPv4 */
321 u32 frg:1; /* IP Fragment */
322 u32 fcs:1; /* Frame CRC correct */
323 u32 type:7; /* completion type */
324 u32 gen:1; /* generation bit */
325#endif /* __BIG_ENDIAN_BITFIELD */
326};
327
328
329/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
330#define VMXNET3_RCD_TUC_SHIFT 16
331#define VMXNET3_RCD_IPC_SHIFT 19
332
333/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
334#define VMXNET3_RCD_TYPE_SHIFT 56
335#define VMXNET3_RCD_GEN_SHIFT 63
336
337/* csum OK for TCP/UDP pkts over IP */
338#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
339 1 << VMXNET3_RCD_IPC_SHIFT)
340#define VMXNET3_TXD_GEN_SIZE 1
341#define VMXNET3_TXD_EOP_SIZE 1
342
343/* value of RxCompDesc.rssType */
344enum {
345 VMXNET3_RCD_RSS_TYPE_NONE = 0,
346 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
347 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
348 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
349 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
350};
351
352
353/* a union for accessing all cmd/completion descriptors */
354union Vmxnet3_GenericDesc {
355 __le64 qword[2];
356 __le32 dword[4];
357 __le16 word[8];
358 struct Vmxnet3_TxDesc txd;
359 struct Vmxnet3_RxDesc rxd;
360 struct Vmxnet3_TxCompDesc tcd;
361 struct Vmxnet3_RxCompDesc rcd;
362 struct Vmxnet3_RxCompDescExt rcdExt;
363};
364
365#define VMXNET3_INIT_GEN 1
366
367/* Max size of a single tx buffer */
368#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
369
370/* # of tx desc needed for a tx buffer size */
371#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
372 VMXNET3_MAX_TX_BUF_SIZE)
373
374/* max # of tx descs for a non-tso pkt */
375#define VMXNET3_MAX_TXD_PER_PKT 16
376
377/* Max size of a single rx buffer */
378#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
379/* Minimum size of a type 0 buffer */
380#define VMXNET3_MIN_T0_BUF_SIZE 128
381#define VMXNET3_MAX_CSUM_OFFSET 1024
382
383/* Ring base address alignment */
384#define VMXNET3_RING_BA_ALIGN 512
385#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
386
387/* Ring size must be a multiple of 32 */
388#define VMXNET3_RING_SIZE_ALIGN 32
389#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
390
391/* Tx Data Ring buffer size must be a multiple of 64 */
392#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
393#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
394
395/* Rx Data Ring buffer size must be a multiple of 64 */
396#define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
397#define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
398
399/* Max ring size */
400#define VMXNET3_TX_RING_MAX_SIZE 4096
401#define VMXNET3_TC_RING_MAX_SIZE 4096
402#define VMXNET3_RX_RING_MAX_SIZE 4096
403#define VMXNET3_RX_RING2_MAX_SIZE 4096
404#define VMXNET3_RC_RING_MAX_SIZE 8192
405
406#define VMXNET3_TXDATA_DESC_MIN_SIZE 128
407#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
408
409#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
410
411/* a list of reasons for queue stop */
412
413enum {
414 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
415 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
416 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
417 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
418 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
419 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
420 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
421 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
422};
423
424/* completion descriptor types */
425#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
426#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
427#define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
428
429enum {
430 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
431 VMXNET3_GOS_BITS_32 = 1,
432 VMXNET3_GOS_BITS_64 = 2,
433};
434
435#define VMXNET3_GOS_TYPE_LINUX 1
436
437
438struct Vmxnet3_GOSInfo {
439#ifdef __BIG_ENDIAN_BITFIELD
440 u32 gosMisc:10; /* other info about gos */
441 u32 gosVer:16; /* gos version */
442 u32 gosType:4; /* which guest */
443 u32 gosBits:2; /* 32-bit or 64-bit? */
444#else
445 u32 gosBits:2; /* 32-bit or 64-bit? */
446 u32 gosType:4; /* which guest */
447 u32 gosVer:16; /* gos version */
448 u32 gosMisc:10; /* other info about gos */
449#endif /* __BIG_ENDIAN_BITFIELD */
450};
451
452struct Vmxnet3_DriverInfo {
453 __le32 version;
454 struct Vmxnet3_GOSInfo gos;
455 __le32 vmxnet3RevSpt;
456 __le32 uptVerSpt;
457};
458
459
460#define VMXNET3_REV1_MAGIC 3133079265u
461
462/*
463 * QueueDescPA must be 128 bytes aligned. It points to an array of
464 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
465 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
466 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
467 */
468#define VMXNET3_QUEUE_DESC_ALIGN 128
469
470
471struct Vmxnet3_MiscConf {
472 struct Vmxnet3_DriverInfo driverInfo;
473 __le64 uptFeatures;
474 __le64 ddPA; /* driver data PA */
475 __le64 queueDescPA; /* queue descriptor table PA */
476 __le32 ddLen; /* driver data len */
477 __le32 queueDescLen; /* queue desc. table len in bytes */
478 __le32 mtu;
479 __le16 maxNumRxSG;
480 u8 numTxQueues;
481 u8 numRxQueues;
482 __le32 reserved[4];
483};
484
485
486struct Vmxnet3_TxQueueConf {
487 __le64 txRingBasePA;
488 __le64 dataRingBasePA;
489 __le64 compRingBasePA;
490 __le64 ddPA; /* driver data */
491 __le64 reserved;
492 __le32 txRingSize; /* # of tx desc */
493 __le32 dataRingSize; /* # of data desc */
494 __le32 compRingSize; /* # of comp desc */
495 __le32 ddLen; /* size of driver data */
496 u8 intrIdx;
497 u8 _pad1[1];
498 __le16 txDataRingDescSize;
499 u8 _pad2[4];
500};
501
502
503struct Vmxnet3_RxQueueConf {
504 __le64 rxRingBasePA[2];
505 __le64 compRingBasePA;
506 __le64 ddPA; /* driver data */
507 __le64 rxDataRingBasePA;
508 __le32 rxRingSize[2]; /* # of rx desc */
509 __le32 compRingSize; /* # of rx comp desc */
510 __le32 ddLen; /* size of driver data */
511 u8 intrIdx;
512 u8 _pad1[1];
513 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
514 u8 _pad2[4];
515};
516
517
518enum vmxnet3_intr_mask_mode {
519 VMXNET3_IMM_AUTO = 0,
520 VMXNET3_IMM_ACTIVE = 1,
521 VMXNET3_IMM_LAZY = 2
522};
523
524enum vmxnet3_intr_type {
525 VMXNET3_IT_AUTO = 0,
526 VMXNET3_IT_INTX = 1,
527 VMXNET3_IT_MSI = 2,
528 VMXNET3_IT_MSIX = 3
529};
530
531#define VMXNET3_MAX_TX_QUEUES 8
532#define VMXNET3_MAX_RX_QUEUES 16
533/* addition 1 for events */
534#define VMXNET3_MAX_INTRS 25
535
536/* value of intrCtrl */
537#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
538
539
540struct Vmxnet3_IntrConf {
541 bool autoMask;
542 u8 numIntrs; /* # of interrupts */
543 u8 eventIntrIdx;
544 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
545 * each intr */
546 __le32 intrCtrl;
547 __le32 reserved[2];
548};
549
550/* one bit per VLAN ID, the size is in the units of u32 */
551#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
552
553
554struct Vmxnet3_QueueStatus {
555 bool stopped;
556 u8 _pad[3];
557 __le32 error;
558};
559
560
561struct Vmxnet3_TxQueueCtrl {
562 __le32 txNumDeferred;
563 __le32 txThreshold;
564 __le64 reserved;
565};
566
567
568struct Vmxnet3_RxQueueCtrl {
569 bool updateRxProd;
570 u8 _pad[7];
571 __le64 reserved;
572};
573
574enum {
575 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
576 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
577 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
578 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
579 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
580};
581
582struct Vmxnet3_RxFilterConf {
583 __le32 rxMode; /* VMXNET3_RXM_xxx */
584 __le16 mfTableLen; /* size of the multicast filter table */
585 __le16 _pad1;
586 __le64 mfTablePA; /* PA of the multicast filters table */
587 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
588};
589
590
591#define VMXNET3_PM_MAX_FILTERS 6
592#define VMXNET3_PM_MAX_PATTERN_SIZE 128
593#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
594
595#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
596#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
597 * filters */
598
599
600struct Vmxnet3_PM_PktFilter {
601 u8 maskSize;
602 u8 patternSize;
603 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
604 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
605 u8 pad[6];
606};
607
608
609struct Vmxnet3_PMConf {
610 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
611 u8 numFilters;
612 u8 pad[5];
613 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
614};
615
616
617struct Vmxnet3_VariableLenConfDesc {
618 __le32 confVer;
619 __le32 confLen;
620 __le64 confPA;
621};
622
623
624struct Vmxnet3_TxQueueDesc {
625 struct Vmxnet3_TxQueueCtrl ctrl;
626 struct Vmxnet3_TxQueueConf conf;
627
628 /* Driver read after a GET command */
629 struct Vmxnet3_QueueStatus status;
630 struct UPT1_TxStats stats;
631 u8 _pad[88]; /* 128 aligned */
632};
633
634
635struct Vmxnet3_RxQueueDesc {
636 struct Vmxnet3_RxQueueCtrl ctrl;
637 struct Vmxnet3_RxQueueConf conf;
638 /* Driver read after a GET commad */
639 struct Vmxnet3_QueueStatus status;
640 struct UPT1_RxStats stats;
641 u8 __pad[88]; /* 128 aligned */
642};
643
644struct Vmxnet3_SetPolling {
645 u8 enablePolling;
646};
647
648#define VMXNET3_COAL_STATIC_MAX_DEPTH 128
649#define VMXNET3_COAL_RBC_MIN_RATE 100
650#define VMXNET3_COAL_RBC_MAX_RATE 100000
651
652enum Vmxnet3_CoalesceMode {
653 VMXNET3_COALESCE_DISABLED = 0,
654 VMXNET3_COALESCE_ADAPT = 1,
655 VMXNET3_COALESCE_STATIC = 2,
656 VMXNET3_COALESCE_RBC = 3
657};
658
659struct Vmxnet3_CoalesceRbc {
660 u32 rbc_rate;
661};
662
663struct Vmxnet3_CoalesceStatic {
664 u32 tx_depth;
665 u32 tx_comp_depth;
666 u32 rx_depth;
667};
668
669struct Vmxnet3_CoalesceScheme {
670 enum Vmxnet3_CoalesceMode coalMode;
671 union {
672 struct Vmxnet3_CoalesceRbc coalRbc;
673 struct Vmxnet3_CoalesceStatic coalStatic;
674 } coalPara;
675};
676
677struct Vmxnet3_MemoryRegion {
678 __le64 startPA;
679 __le32 length;
680 __le16 txQueueBits;
681 __le16 rxQueueBits;
682};
683
684#define MAX_MEMORY_REGION_PER_QUEUE 16
685#define MAX_MEMORY_REGION_PER_DEVICE 256
686
687struct Vmxnet3_MemRegs {
688 __le16 numRegs;
689 __le16 pad[3];
690 struct Vmxnet3_MemoryRegion memRegs[1];
691};
692
693enum Vmxnet3_RSSField {
694 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
695 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
696 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
697 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
698 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
699 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
700};
701
702/* If the command data <= 16 bytes, use the shared memory directly.
703 * otherwise, use variable length configuration descriptor.
704 */
705union Vmxnet3_CmdInfo {
706 struct Vmxnet3_VariableLenConfDesc varConf;
707 struct Vmxnet3_SetPolling setPolling;
708 enum Vmxnet3_RSSField setRssFields;
709 __le64 data[2];
710};
711
712struct Vmxnet3_DSDevRead {
713 /* read-only region for device, read by dev in response to a SET cmd */
714 struct Vmxnet3_MiscConf misc;
715 struct Vmxnet3_IntrConf intrConf;
716 struct Vmxnet3_RxFilterConf rxFilterConf;
717 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
718 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
719 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
720};
721
722/* All structures in DriverShared are padded to multiples of 8 bytes */
723struct Vmxnet3_DriverShared {
724 __le32 magic;
725 /* make devRead start at 64bit boundaries */
726 __le32 pad;
727 struct Vmxnet3_DSDevRead devRead;
728 __le32 ecr;
729 __le32 reserved;
730 union {
731 __le32 reserved1[4];
732 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of
733 * executing the relevant
734 * command
735 */
736 } cu;
737};
738
739
740#define VMXNET3_ECR_RQERR (1 << 0)
741#define VMXNET3_ECR_TQERR (1 << 1)
742#define VMXNET3_ECR_LINK (1 << 2)
743#define VMXNET3_ECR_DIC (1 << 3)
744#define VMXNET3_ECR_DEBUG (1 << 4)
745
746/* flip the gen bit of a ring */
747#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
748
749/* only use this if moving the idx won't affect the gen bit */
750#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
751 do {\
752 (idx)++;\
753 if (unlikely((idx) == (ring_size))) {\
754 (idx) = 0;\
755 } \
756 } while (0)
757
758#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
759 (vfTable[vid >> 5] |= (1 << (vid & 31)))
760#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
761 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
762
763#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
764 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
765
766#define VMXNET3_MAX_MTU 9000
767#define VMXNET3_MIN_MTU 60
768
769#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
770#define VMXNET3_LINK_DOWN 0
771
772#endif /* _VMXNET3_DEFS_H_ */