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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13#include "bcm-phy-lib.h"
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/phy.h>
17#include <linux/pm_wakeup.h>
18#include <linux/brcmphy.h>
19#include <linux/of.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/gpio/consumer.h>
23
24#define BRCM_PHY_MODEL(phydev) \
25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
26
27#define BRCM_PHY_REV(phydev) \
28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
29
30MODULE_DESCRIPTION("Broadcom PHY driver");
31MODULE_AUTHOR("Maciej W. Rozycki");
32MODULE_LICENSE("GPL");
33
34struct bcm54xx_phy_priv {
35 u64 *stats;
36 struct bcm_ptp_private *ptp;
37 int wake_irq;
38 bool wake_irq_enabled;
39};
40
41static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev)
42{
43 struct bcm54xx_phy_priv *priv = phydev->priv;
44
45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0;
46}
47
48static int bcm54xx_config_clock_delay(struct phy_device *phydev)
49{
50 int rc, val;
51
52 /* handling PHY's internal RX clock delay */
53 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
54 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
55 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
56 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
57 /* Disable RGMII RXC-RXD skew */
58 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
59 }
60 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
61 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
62 /* Enable RGMII RXC-RXD skew */
63 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
64 }
65 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
66 val);
67 if (rc < 0)
68 return rc;
69
70 /* handling PHY's internal TX clock delay */
71 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
72 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
73 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
74 /* Disable internal TX clock delay */
75 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
76 }
77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
79 /* Enable internal TX clock delay */
80 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
81 }
82 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
83 if (rc < 0)
84 return rc;
85
86 return 0;
87}
88
89static int bcm54210e_config_init(struct phy_device *phydev)
90{
91 int val;
92
93 bcm54xx_config_clock_delay(phydev);
94
95 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
96 val = phy_read(phydev, MII_CTRL1000);
97 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
98 phy_write(phydev, MII_CTRL1000, val);
99 }
100
101 return 0;
102}
103
104static int bcm54612e_config_init(struct phy_device *phydev)
105{
106 int reg;
107
108 bcm54xx_config_clock_delay(phydev);
109
110 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
111 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
112 int err;
113
114 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
115 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
116 BCM54612E_LED4_CLK125OUT_EN | reg);
117
118 if (err < 0)
119 return err;
120 }
121
122 return 0;
123}
124
125static int bcm54616s_config_init(struct phy_device *phydev)
126{
127 int rc, val;
128
129 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
130 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
131 return 0;
132
133 /* Ensure proper interface mode is selected. */
134 /* Disable RGMII mode */
135 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
136 if (val < 0)
137 return val;
138 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
139 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
140 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
141 val);
142 if (rc < 0)
143 return rc;
144
145 /* Select 1000BASE-X register set (primary SerDes) */
146 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
147 if (val < 0)
148 return val;
149 val |= BCM54XX_SHD_MODE_1000BX;
150 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
151 if (rc < 0)
152 return rc;
153
154 /* Power down SerDes interface */
155 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
156 if (rc < 0)
157 return rc;
158
159 /* Select proper interface mode */
160 val &= ~BCM54XX_SHD_INTF_SEL_MASK;
161 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
162 BCM54XX_SHD_INTF_SEL_SGMII :
163 BCM54XX_SHD_INTF_SEL_GBIC;
164 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
165 if (rc < 0)
166 return rc;
167
168 /* Power up SerDes interface */
169 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
170 if (rc < 0)
171 return rc;
172
173 /* Select copper register set */
174 val &= ~BCM54XX_SHD_MODE_1000BX;
175 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
176 if (rc < 0)
177 return rc;
178
179 /* Power up copper interface */
180 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
181}
182
183/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
184static int bcm50610_a0_workaround(struct phy_device *phydev)
185{
186 int err;
187
188 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
189 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
190 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
191 if (err < 0)
192 return err;
193
194 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
195 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
196 if (err < 0)
197 return err;
198
199 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
200 MII_BCM54XX_EXP_EXP75_VDACCTRL);
201 if (err < 0)
202 return err;
203
204 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
205 MII_BCM54XX_EXP_EXP96_MYST);
206 if (err < 0)
207 return err;
208
209 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
210 MII_BCM54XX_EXP_EXP97_MYST);
211
212 return err;
213}
214
215static int bcm54xx_phydsp_config(struct phy_device *phydev)
216{
217 int err, err2;
218
219 /* Enable the SMDSP clock */
220 err = bcm54xx_auxctl_write(phydev,
221 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
222 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
223 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
224 if (err < 0)
225 return err;
226
227 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
228 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
229 /* Clear bit 9 to fix a phy interop issue. */
230 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
231 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
232 if (err < 0)
233 goto error;
234
235 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
236 err = bcm50610_a0_workaround(phydev);
237 if (err < 0)
238 goto error;
239 }
240 }
241
242 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
243 int val;
244
245 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
246 if (val < 0)
247 goto error;
248
249 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
250 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
251 }
252
253error:
254 /* Disable the SMDSP clock */
255 err2 = bcm54xx_auxctl_write(phydev,
256 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
257 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
258
259 /* Return the first error reported. */
260 return err ? err : err2;
261}
262
263static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
264{
265 u32 orig;
266 int val;
267 bool clk125en = true;
268
269 /* Abort if we are using an untested phy. */
270 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
271 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
272 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
273 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
274 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
275 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
276 return;
277
278 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
279 if (val < 0)
280 return;
281
282 orig = val;
283
284 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
285 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
286 BRCM_PHY_REV(phydev) >= 0x3) {
287 /*
288 * Here, bit 0 _disables_ CLK125 when set.
289 * This bit is set by default.
290 */
291 clk125en = false;
292 } else {
293 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
294 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
295 /* Here, bit 0 _enables_ CLK125 when set */
296 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
297 }
298 clk125en = false;
299 }
300 }
301
302 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
303 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
304 else
305 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
306
307 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
308 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
309 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
310 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
311 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
312 else
313 val |= BCM54XX_SHD_SCR3_TRDDAPD;
314 }
315
316 if (orig != val)
317 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
318
319 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
320 if (val < 0)
321 return;
322
323 orig = val;
324
325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
326 val |= BCM54XX_SHD_APD_EN;
327 else
328 val &= ~BCM54XX_SHD_APD_EN;
329
330 if (orig != val)
331 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
332}
333
334static void bcm54xx_ptp_stop(struct phy_device *phydev)
335{
336 struct bcm54xx_phy_priv *priv = phydev->priv;
337
338 if (priv->ptp)
339 bcm_ptp_stop(priv->ptp);
340}
341
342static void bcm54xx_ptp_config_init(struct phy_device *phydev)
343{
344 struct bcm54xx_phy_priv *priv = phydev->priv;
345
346 if (priv->ptp)
347 bcm_ptp_config_init(phydev);
348}
349
350static int bcm54xx_config_init(struct phy_device *phydev)
351{
352 int reg, err, val;
353
354 reg = phy_read(phydev, MII_BCM54XX_ECR);
355 if (reg < 0)
356 return reg;
357
358 /* Mask interrupts globally. */
359 reg |= MII_BCM54XX_ECR_IM;
360 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
361 if (err < 0)
362 return err;
363
364 /* Unmask events we are interested in. */
365 reg = ~(MII_BCM54XX_INT_DUPLEX |
366 MII_BCM54XX_INT_SPEED |
367 MII_BCM54XX_INT_LINK);
368 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
369 if (err < 0)
370 return err;
371
372 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
373 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
374 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
375 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
376
377 bcm54xx_adjust_rxrefclk(phydev);
378
379 switch (BRCM_PHY_MODEL(phydev)) {
380 case PHY_ID_BCM50610:
381 case PHY_ID_BCM50610M:
382 err = bcm54xx_config_clock_delay(phydev);
383 break;
384 case PHY_ID_BCM54210E:
385 err = bcm54210e_config_init(phydev);
386 break;
387 case PHY_ID_BCM54612E:
388 err = bcm54612e_config_init(phydev);
389 break;
390 case PHY_ID_BCM54616S:
391 err = bcm54616s_config_init(phydev);
392 break;
393 case PHY_ID_BCM54810:
394 /* For BCM54810, we need to disable BroadR-Reach function */
395 val = bcm_phy_read_exp(phydev,
396 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
397 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
398 err = bcm_phy_write_exp(phydev,
399 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
400 val);
401 break;
402 }
403 if (err)
404 return err;
405
406 bcm54xx_phydsp_config(phydev);
407
408 /* For non-SFP setups, encode link speed into LED1 and LED3 pair
409 * (green/amber).
410 * Also flash these two LEDs on activity. This means configuring
411 * them for MULTICOLOR and encoding link/activity into them.
412 * Don't do this for devices on an SFP module, since some of these
413 * use the LED outputs to control the SFP LOS signal, and changing
414 * these settings will cause LOS to malfunction.
415 */
416 if (!phy_on_sfp(phydev)) {
417 val = BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
418 BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
419 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val);
420
421 val = BCM_LED_MULTICOLOR_IN_PHASE |
422 BCM54XX_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
423 BCM54XX_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
424 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
425 }
426
427 bcm54xx_ptp_config_init(phydev);
428
429 /* Acknowledge any left over interrupt and charge the device for
430 * wake-up.
431 */
432 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
433 if (err < 0)
434 return err;
435
436 if (err)
437 pm_wakeup_event(&phydev->mdio.dev, 0);
438
439 return 0;
440}
441
442static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable)
443{
444 int ret = 0;
445
446 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND))
447 return ret;
448
449 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL);
450 if (ret < 0)
451 goto out;
452
453 if (enable)
454 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP;
455 else
456 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP);
457
458 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret);
459out:
460 return ret;
461}
462
463static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state)
464{
465 struct bcm54xx_phy_priv *priv = phydev->priv;
466 int ret = 0;
467
468 if (!bcm54xx_phy_can_wakeup(phydev))
469 return ret;
470
471 if (priv->wake_irq_enabled != state) {
472 if (state)
473 ret = enable_irq_wake(priv->wake_irq);
474 else
475 ret = disable_irq_wake(priv->wake_irq);
476 priv->wake_irq_enabled = state;
477 }
478
479 return ret;
480}
481
482static int bcm54xx_suspend(struct phy_device *phydev)
483{
484 int ret = 0;
485
486 bcm54xx_ptp_stop(phydev);
487
488 /* Acknowledge any Wake-on-LAN interrupt prior to suspend */
489 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
490 if (ret < 0)
491 return ret;
492
493 if (phydev->wol_enabled)
494 return bcm54xx_set_wakeup_irq(phydev, true);
495
496 /* We cannot use a read/modify/write here otherwise the PHY gets into
497 * a bad state where its LEDs keep flashing, thus defeating the purpose
498 * of low power mode.
499 */
500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
501 if (ret < 0)
502 return ret;
503
504 return bcm54xx_iddq_set(phydev, true);
505}
506
507static int bcm54xx_resume(struct phy_device *phydev)
508{
509 int ret = 0;
510
511 if (phydev->wol_enabled) {
512 ret = bcm54xx_set_wakeup_irq(phydev, false);
513 if (ret)
514 return ret;
515 }
516
517 ret = bcm54xx_iddq_set(phydev, false);
518 if (ret < 0)
519 return ret;
520
521 /* Writes to register other than BMCR would be ignored
522 * unless we clear the PDOWN bit first
523 */
524 ret = genphy_resume(phydev);
525 if (ret < 0)
526 return ret;
527
528 /* Upon exiting power down, the PHY remains in an internal reset state
529 * for 40us
530 */
531 fsleep(40);
532
533 /* Issue a soft reset after clearing the power down bit
534 * and before doing any other configuration.
535 */
536 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) {
537 ret = genphy_soft_reset(phydev);
538 if (ret < 0)
539 return ret;
540 }
541
542 return bcm54xx_config_init(phydev);
543}
544
545static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
546{
547 return -EOPNOTSUPP;
548}
549
550static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
551 u16 val)
552{
553 return -EOPNOTSUPP;
554}
555
556static int bcm54811_config_init(struct phy_device *phydev)
557{
558 int err, reg;
559
560 /* Disable BroadR-Reach function. */
561 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
562 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
563 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
564 reg);
565 if (err < 0)
566 return err;
567
568 err = bcm54xx_config_init(phydev);
569
570 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
571 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
572 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
573 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
574 BCM54612E_LED4_CLK125OUT_EN | reg);
575 if (err < 0)
576 return err;
577 }
578
579 return err;
580}
581
582static int bcm5481_config_aneg(struct phy_device *phydev)
583{
584 struct device_node *np = phydev->mdio.dev.of_node;
585 int ret;
586
587 /* Aneg firstly. */
588 ret = genphy_config_aneg(phydev);
589
590 /* Then we can set up the delay. */
591 bcm54xx_config_clock_delay(phydev);
592
593 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
594 /* Lane Swap - Undocumented register...magic! */
595 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
596 0x11B);
597 if (ret < 0)
598 return ret;
599 }
600
601 return ret;
602}
603
604struct bcm54616s_phy_priv {
605 bool mode_1000bx_en;
606};
607
608static int bcm54616s_probe(struct phy_device *phydev)
609{
610 struct bcm54616s_phy_priv *priv;
611 int val;
612
613 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
614 if (!priv)
615 return -ENOMEM;
616
617 phydev->priv = priv;
618
619 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
620 if (val < 0)
621 return val;
622
623 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
624 * is 01b, and the link between PHY and its link partner can be
625 * either 1000Base-X or 100Base-FX.
626 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
627 * support is still missing as of now.
628 */
629 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
630 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
631 if (val < 0)
632 return val;
633
634 /* Bit 0 of the SerDes 100-FX Control register, when set
635 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
636 * When this bit is set to 0, it sets the GMII/RGMII ->
637 * 1000BASE-X configuration.
638 */
639 if (!(val & BCM54616S_100FX_MODE))
640 priv->mode_1000bx_en = true;
641
642 phydev->port = PORT_FIBRE;
643 }
644
645 return 0;
646}
647
648static int bcm54616s_config_aneg(struct phy_device *phydev)
649{
650 struct bcm54616s_phy_priv *priv = phydev->priv;
651 int ret;
652
653 /* Aneg firstly. */
654 if (priv->mode_1000bx_en)
655 ret = genphy_c37_config_aneg(phydev);
656 else
657 ret = genphy_config_aneg(phydev);
658
659 /* Then we can set up the delay. */
660 bcm54xx_config_clock_delay(phydev);
661
662 return ret;
663}
664
665static int bcm54616s_read_status(struct phy_device *phydev)
666{
667 struct bcm54616s_phy_priv *priv = phydev->priv;
668 int err;
669
670 if (priv->mode_1000bx_en)
671 err = genphy_c37_read_status(phydev);
672 else
673 err = genphy_read_status(phydev);
674
675 return err;
676}
677
678static int brcm_fet_config_init(struct phy_device *phydev)
679{
680 int reg, err, err2, brcmtest;
681
682 /* Reset the PHY to bring it to a known state. */
683 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
684 if (err < 0)
685 return err;
686
687 /* The datasheet indicates the PHY needs up to 1us to complete a reset,
688 * build some slack here.
689 */
690 usleep_range(1000, 2000);
691
692 /* The PHY requires 65 MDC clock cycles to complete a write operation
693 * and turnaround the line properly.
694 *
695 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
696 * may flag the lack of turn-around as a read failure. This is
697 * particularly true with this combination since the MDIO controller
698 * only used 64 MDC cycles. This is not a critical failure in this
699 * specific case and it has no functional impact otherwise, so we let
700 * that one go through. If there is a genuine bus error, the next read
701 * of MII_BRCM_FET_INTREG will error out.
702 */
703 err = phy_read(phydev, MII_BMCR);
704 if (err < 0 && err != -EIO)
705 return err;
706
707 /* Read to clear status bits */
708 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
709 if (reg < 0)
710 return reg;
711
712 /* Unmask events we are interested in and mask interrupts globally. */
713 if (phydev->phy_id == PHY_ID_BCM5221)
714 reg = MII_BRCM_FET_IR_ENABLE |
715 MII_BRCM_FET_IR_MASK;
716 else
717 reg = MII_BRCM_FET_IR_DUPLEX_EN |
718 MII_BRCM_FET_IR_SPEED_EN |
719 MII_BRCM_FET_IR_LINK_EN |
720 MII_BRCM_FET_IR_ENABLE |
721 MII_BRCM_FET_IR_MASK;
722
723 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
724 if (err < 0)
725 return err;
726
727 /* Enable shadow register access */
728 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
729 if (brcmtest < 0)
730 return brcmtest;
731
732 reg = brcmtest | MII_BRCM_FET_BT_SRE;
733
734 phy_lock_mdio_bus(phydev);
735
736 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
737 if (err < 0) {
738 phy_unlock_mdio_bus(phydev);
739 return err;
740 }
741
742 if (phydev->phy_id != PHY_ID_BCM5221) {
743 /* Set the LED mode */
744 reg = __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
745 if (reg < 0) {
746 err = reg;
747 goto done;
748 }
749
750 err = __phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
751 MII_BRCM_FET_SHDW_AM4_LED_MASK,
752 MII_BRCM_FET_SHDW_AM4_LED_MODE1);
753 if (err < 0)
754 goto done;
755
756 /* Enable auto MDIX */
757 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
758 MII_BRCM_FET_SHDW_MC_FAME);
759 if (err < 0)
760 goto done;
761 }
762
763 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
764 /* Enable auto power down */
765 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
766 MII_BRCM_FET_SHDW_AS2_APDE);
767 }
768
769done:
770 /* Disable shadow register access */
771 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
772 if (!err)
773 err = err2;
774
775 phy_unlock_mdio_bus(phydev);
776
777 return err;
778}
779
780static int brcm_fet_ack_interrupt(struct phy_device *phydev)
781{
782 int reg;
783
784 /* Clear pending interrupts. */
785 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
786 if (reg < 0)
787 return reg;
788
789 return 0;
790}
791
792static int brcm_fet_config_intr(struct phy_device *phydev)
793{
794 int reg, err;
795
796 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
797 if (reg < 0)
798 return reg;
799
800 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
801 err = brcm_fet_ack_interrupt(phydev);
802 if (err)
803 return err;
804
805 reg &= ~MII_BRCM_FET_IR_MASK;
806 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
807 } else {
808 reg |= MII_BRCM_FET_IR_MASK;
809 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
810 if (err)
811 return err;
812
813 err = brcm_fet_ack_interrupt(phydev);
814 }
815
816 return err;
817}
818
819static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
820{
821 int irq_status;
822
823 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
824 if (irq_status < 0) {
825 phy_error(phydev);
826 return IRQ_NONE;
827 }
828
829 if (irq_status == 0)
830 return IRQ_NONE;
831
832 phy_trigger_machine(phydev);
833
834 return IRQ_HANDLED;
835}
836
837static int brcm_fet_suspend(struct phy_device *phydev)
838{
839 int reg, err, err2, brcmtest;
840
841 /* We cannot use a read/modify/write here otherwise the PHY continues
842 * to drive LEDs which defeats the purpose of low power mode.
843 */
844 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
845 if (err < 0)
846 return err;
847
848 /* Enable shadow register access */
849 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
850 if (brcmtest < 0)
851 return brcmtest;
852
853 reg = brcmtest | MII_BRCM_FET_BT_SRE;
854
855 phy_lock_mdio_bus(phydev);
856
857 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
858 if (err < 0) {
859 phy_unlock_mdio_bus(phydev);
860 return err;
861 }
862
863 if (phydev->phy_id == PHY_ID_BCM5221)
864 /* Force Low Power Mode with clock enabled */
865 reg = BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM;
866 else
867 /* Set standby mode */
868 reg = MII_BRCM_FET_SHDW_AM4_STANDBY;
869
870 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
871
872 /* Disable shadow register access */
873 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
874 if (!err)
875 err = err2;
876
877 phy_unlock_mdio_bus(phydev);
878
879 return err;
880}
881
882static int bcm5221_config_aneg(struct phy_device *phydev)
883{
884 int ret, val;
885
886 ret = genphy_config_aneg(phydev);
887 if (ret)
888 return ret;
889
890 switch (phydev->mdix_ctrl) {
891 case ETH_TP_MDI:
892 val = BCM5221_AEGSR_MDIX_DIS;
893 break;
894 case ETH_TP_MDI_X:
895 val = BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP;
896 break;
897 case ETH_TP_MDI_AUTO:
898 val = 0;
899 break;
900 default:
901 return 0;
902 }
903
904 return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP |
905 BCM5221_AEGSR_MDIX_DIS,
906 val);
907}
908
909static int bcm5221_read_status(struct phy_device *phydev)
910{
911 int ret;
912
913 /* Read MDIX status */
914 ret = phy_read(phydev, BCM5221_AEGSR);
915 if (ret < 0)
916 return ret;
917
918 if (ret & BCM5221_AEGSR_MDIX_DIS) {
919 if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP)
920 phydev->mdix_ctrl = ETH_TP_MDI_X;
921 else
922 phydev->mdix_ctrl = ETH_TP_MDI;
923 } else {
924 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
925 }
926
927 if (ret & BCM5221_AEGSR_MDIX_STATUS)
928 phydev->mdix = ETH_TP_MDI_X;
929 else
930 phydev->mdix = ETH_TP_MDI;
931
932 return genphy_read_status(phydev);
933}
934
935static void bcm54xx_phy_get_wol(struct phy_device *phydev,
936 struct ethtool_wolinfo *wol)
937{
938 /* We cannot wake-up if we do not have a dedicated PHY interrupt line
939 * or an out of band GPIO descriptor for wake-up. Zeroing
940 * wol->supported allows the caller (MAC driver) to play through and
941 * offer its own Wake-on-LAN scheme if available.
942 */
943 if (!bcm54xx_phy_can_wakeup(phydev)) {
944 wol->supported = 0;
945 return;
946 }
947
948 bcm_phy_get_wol(phydev, wol);
949}
950
951static int bcm54xx_phy_set_wol(struct phy_device *phydev,
952 struct ethtool_wolinfo *wol)
953{
954 int ret;
955
956 /* We cannot wake-up if we do not have a dedicated PHY interrupt line
957 * or an out of band GPIO descriptor for wake-up. Returning -EOPNOTSUPP
958 * allows the caller (MAC driver) to play through and offer its own
959 * Wake-on-LAN scheme if available.
960 */
961 if (!bcm54xx_phy_can_wakeup(phydev))
962 return -EOPNOTSUPP;
963
964 ret = bcm_phy_set_wol(phydev, wol);
965 if (ret < 0)
966 return ret;
967
968 return 0;
969}
970
971static int bcm54xx_phy_probe(struct phy_device *phydev)
972{
973 struct bcm54xx_phy_priv *priv;
974 struct gpio_desc *wakeup_gpio;
975 int ret = 0;
976
977 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
978 if (!priv)
979 return -ENOMEM;
980
981 priv->wake_irq = -ENXIO;
982
983 phydev->priv = priv;
984
985 priv->stats = devm_kcalloc(&phydev->mdio.dev,
986 bcm_phy_get_sset_count(phydev), sizeof(u64),
987 GFP_KERNEL);
988 if (!priv->stats)
989 return -ENOMEM;
990
991 priv->ptp = bcm_ptp_probe(phydev);
992 if (IS_ERR(priv->ptp))
993 return PTR_ERR(priv->ptp);
994
995 /* We cannot utilize the _optional variant here since we want to know
996 * whether the GPIO descriptor exists or not to advertise Wake-on-LAN
997 * support or not.
998 */
999 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN);
1000 if (PTR_ERR(wakeup_gpio) == -EPROBE_DEFER)
1001 return PTR_ERR(wakeup_gpio);
1002
1003 if (!IS_ERR(wakeup_gpio)) {
1004 priv->wake_irq = gpiod_to_irq(wakeup_gpio);
1005
1006 /* Dummy interrupt handler which is not enabled but is provided
1007 * in order for the interrupt descriptor to be fully set-up.
1008 */
1009 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq,
1010 bcm_phy_wol_isr,
1011 IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN,
1012 dev_name(&phydev->mdio.dev), phydev);
1013 if (ret)
1014 return ret;
1015 }
1016
1017 /* If we do not have a main interrupt or a side-band wake-up interrupt,
1018 * then the device cannot be marked as wake-up capable.
1019 */
1020 if (!bcm54xx_phy_can_wakeup(phydev))
1021 return 0;
1022
1023 return device_init_wakeup(&phydev->mdio.dev, true);
1024}
1025
1026static void bcm54xx_get_stats(struct phy_device *phydev,
1027 struct ethtool_stats *stats, u64 *data)
1028{
1029 struct bcm54xx_phy_priv *priv = phydev->priv;
1030
1031 bcm_phy_get_stats(phydev, priv->stats, stats, data);
1032}
1033
1034static void bcm54xx_link_change_notify(struct phy_device *phydev)
1035{
1036 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE |
1037 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE;
1038 int ret;
1039
1040 if (phydev->state != PHY_RUNNING)
1041 return;
1042
1043 /* Don't change the DAC wake settings if auto power down
1044 * is not requested.
1045 */
1046 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
1047 return;
1048
1049 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08);
1050 if (ret < 0)
1051 return;
1052
1053 /* Enable/disable 10BaseT auto and forced early DAC wake depending
1054 * on the negotiated speed, those settings should only be done
1055 * for 10Mbits/sec.
1056 */
1057 if (phydev->speed == SPEED_10)
1058 ret |= mask;
1059 else
1060 ret &= ~mask;
1061 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret);
1062}
1063
1064static struct phy_driver broadcom_drivers[] = {
1065{
1066 .phy_id = PHY_ID_BCM5411,
1067 .phy_id_mask = 0xfffffff0,
1068 .name = "Broadcom BCM5411",
1069 /* PHY_GBIT_FEATURES */
1070 .get_sset_count = bcm_phy_get_sset_count,
1071 .get_strings = bcm_phy_get_strings,
1072 .get_stats = bcm54xx_get_stats,
1073 .probe = bcm54xx_phy_probe,
1074 .config_init = bcm54xx_config_init,
1075 .config_intr = bcm_phy_config_intr,
1076 .handle_interrupt = bcm_phy_handle_interrupt,
1077 .link_change_notify = bcm54xx_link_change_notify,
1078}, {
1079 .phy_id = PHY_ID_BCM5421,
1080 .phy_id_mask = 0xfffffff0,
1081 .name = "Broadcom BCM5421",
1082 /* PHY_GBIT_FEATURES */
1083 .get_sset_count = bcm_phy_get_sset_count,
1084 .get_strings = bcm_phy_get_strings,
1085 .get_stats = bcm54xx_get_stats,
1086 .probe = bcm54xx_phy_probe,
1087 .config_init = bcm54xx_config_init,
1088 .config_intr = bcm_phy_config_intr,
1089 .handle_interrupt = bcm_phy_handle_interrupt,
1090 .link_change_notify = bcm54xx_link_change_notify,
1091}, {
1092 .phy_id = PHY_ID_BCM54210E,
1093 .phy_id_mask = 0xfffffff0,
1094 .name = "Broadcom BCM54210E",
1095 /* PHY_GBIT_FEATURES */
1096 .flags = PHY_ALWAYS_CALL_SUSPEND,
1097 .get_sset_count = bcm_phy_get_sset_count,
1098 .get_strings = bcm_phy_get_strings,
1099 .get_stats = bcm54xx_get_stats,
1100 .probe = bcm54xx_phy_probe,
1101 .config_init = bcm54xx_config_init,
1102 .config_intr = bcm_phy_config_intr,
1103 .handle_interrupt = bcm_phy_handle_interrupt,
1104 .link_change_notify = bcm54xx_link_change_notify,
1105 .suspend = bcm54xx_suspend,
1106 .resume = bcm54xx_resume,
1107 .get_wol = bcm54xx_phy_get_wol,
1108 .set_wol = bcm54xx_phy_set_wol,
1109 .led_brightness_set = bcm_phy_led_brightness_set,
1110}, {
1111 .phy_id = PHY_ID_BCM5461,
1112 .phy_id_mask = 0xfffffff0,
1113 .name = "Broadcom BCM5461",
1114 /* PHY_GBIT_FEATURES */
1115 .get_sset_count = bcm_phy_get_sset_count,
1116 .get_strings = bcm_phy_get_strings,
1117 .get_stats = bcm54xx_get_stats,
1118 .probe = bcm54xx_phy_probe,
1119 .config_init = bcm54xx_config_init,
1120 .config_intr = bcm_phy_config_intr,
1121 .handle_interrupt = bcm_phy_handle_interrupt,
1122 .link_change_notify = bcm54xx_link_change_notify,
1123 .led_brightness_set = bcm_phy_led_brightness_set,
1124}, {
1125 .phy_id = PHY_ID_BCM54612E,
1126 .phy_id_mask = 0xfffffff0,
1127 .name = "Broadcom BCM54612E",
1128 /* PHY_GBIT_FEATURES */
1129 .get_sset_count = bcm_phy_get_sset_count,
1130 .get_strings = bcm_phy_get_strings,
1131 .get_stats = bcm54xx_get_stats,
1132 .probe = bcm54xx_phy_probe,
1133 .config_init = bcm54xx_config_init,
1134 .config_intr = bcm_phy_config_intr,
1135 .handle_interrupt = bcm_phy_handle_interrupt,
1136 .link_change_notify = bcm54xx_link_change_notify,
1137 .led_brightness_set = bcm_phy_led_brightness_set,
1138 .suspend = bcm54xx_suspend,
1139 .resume = bcm54xx_resume,
1140}, {
1141 .phy_id = PHY_ID_BCM54616S,
1142 .phy_id_mask = 0xfffffff0,
1143 .name = "Broadcom BCM54616S",
1144 /* PHY_GBIT_FEATURES */
1145 .soft_reset = genphy_soft_reset,
1146 .config_init = bcm54xx_config_init,
1147 .config_aneg = bcm54616s_config_aneg,
1148 .config_intr = bcm_phy_config_intr,
1149 .handle_interrupt = bcm_phy_handle_interrupt,
1150 .read_status = bcm54616s_read_status,
1151 .probe = bcm54616s_probe,
1152 .link_change_notify = bcm54xx_link_change_notify,
1153 .led_brightness_set = bcm_phy_led_brightness_set,
1154}, {
1155 .phy_id = PHY_ID_BCM5464,
1156 .phy_id_mask = 0xfffffff0,
1157 .name = "Broadcom BCM5464",
1158 /* PHY_GBIT_FEATURES */
1159 .get_sset_count = bcm_phy_get_sset_count,
1160 .get_strings = bcm_phy_get_strings,
1161 .get_stats = bcm54xx_get_stats,
1162 .probe = bcm54xx_phy_probe,
1163 .config_init = bcm54xx_config_init,
1164 .config_intr = bcm_phy_config_intr,
1165 .handle_interrupt = bcm_phy_handle_interrupt,
1166 .suspend = genphy_suspend,
1167 .resume = genphy_resume,
1168 .link_change_notify = bcm54xx_link_change_notify,
1169 .led_brightness_set = bcm_phy_led_brightness_set,
1170}, {
1171 .phy_id = PHY_ID_BCM5481,
1172 .phy_id_mask = 0xfffffff0,
1173 .name = "Broadcom BCM5481",
1174 /* PHY_GBIT_FEATURES */
1175 .get_sset_count = bcm_phy_get_sset_count,
1176 .get_strings = bcm_phy_get_strings,
1177 .get_stats = bcm54xx_get_stats,
1178 .probe = bcm54xx_phy_probe,
1179 .config_init = bcm54xx_config_init,
1180 .config_aneg = bcm5481_config_aneg,
1181 .config_intr = bcm_phy_config_intr,
1182 .handle_interrupt = bcm_phy_handle_interrupt,
1183 .link_change_notify = bcm54xx_link_change_notify,
1184 .led_brightness_set = bcm_phy_led_brightness_set,
1185}, {
1186 .phy_id = PHY_ID_BCM54810,
1187 .phy_id_mask = 0xfffffff0,
1188 .name = "Broadcom BCM54810",
1189 /* PHY_GBIT_FEATURES */
1190 .get_sset_count = bcm_phy_get_sset_count,
1191 .get_strings = bcm_phy_get_strings,
1192 .get_stats = bcm54xx_get_stats,
1193 .probe = bcm54xx_phy_probe,
1194 .read_mmd = bcm54810_read_mmd,
1195 .write_mmd = bcm54810_write_mmd,
1196 .config_init = bcm54xx_config_init,
1197 .config_aneg = bcm5481_config_aneg,
1198 .config_intr = bcm_phy_config_intr,
1199 .handle_interrupt = bcm_phy_handle_interrupt,
1200 .suspend = bcm54xx_suspend,
1201 .resume = bcm54xx_resume,
1202 .link_change_notify = bcm54xx_link_change_notify,
1203 .led_brightness_set = bcm_phy_led_brightness_set,
1204}, {
1205 .phy_id = PHY_ID_BCM54811,
1206 .phy_id_mask = 0xfffffff0,
1207 .name = "Broadcom BCM54811",
1208 /* PHY_GBIT_FEATURES */
1209 .get_sset_count = bcm_phy_get_sset_count,
1210 .get_strings = bcm_phy_get_strings,
1211 .get_stats = bcm54xx_get_stats,
1212 .probe = bcm54xx_phy_probe,
1213 .config_init = bcm54811_config_init,
1214 .config_aneg = bcm5481_config_aneg,
1215 .config_intr = bcm_phy_config_intr,
1216 .handle_interrupt = bcm_phy_handle_interrupt,
1217 .suspend = bcm54xx_suspend,
1218 .resume = bcm54xx_resume,
1219 .link_change_notify = bcm54xx_link_change_notify,
1220 .led_brightness_set = bcm_phy_led_brightness_set,
1221}, {
1222 .phy_id = PHY_ID_BCM5482,
1223 .phy_id_mask = 0xfffffff0,
1224 .name = "Broadcom BCM5482",
1225 /* PHY_GBIT_FEATURES */
1226 .get_sset_count = bcm_phy_get_sset_count,
1227 .get_strings = bcm_phy_get_strings,
1228 .get_stats = bcm54xx_get_stats,
1229 .probe = bcm54xx_phy_probe,
1230 .config_init = bcm54xx_config_init,
1231 .config_intr = bcm_phy_config_intr,
1232 .handle_interrupt = bcm_phy_handle_interrupt,
1233 .link_change_notify = bcm54xx_link_change_notify,
1234 .led_brightness_set = bcm_phy_led_brightness_set,
1235}, {
1236 .phy_id = PHY_ID_BCM50610,
1237 .phy_id_mask = 0xfffffff0,
1238 .name = "Broadcom BCM50610",
1239 /* PHY_GBIT_FEATURES */
1240 .get_sset_count = bcm_phy_get_sset_count,
1241 .get_strings = bcm_phy_get_strings,
1242 .get_stats = bcm54xx_get_stats,
1243 .probe = bcm54xx_phy_probe,
1244 .config_init = bcm54xx_config_init,
1245 .config_intr = bcm_phy_config_intr,
1246 .handle_interrupt = bcm_phy_handle_interrupt,
1247 .link_change_notify = bcm54xx_link_change_notify,
1248 .suspend = bcm54xx_suspend,
1249 .resume = bcm54xx_resume,
1250 .led_brightness_set = bcm_phy_led_brightness_set,
1251}, {
1252 .phy_id = PHY_ID_BCM50610M,
1253 .phy_id_mask = 0xfffffff0,
1254 .name = "Broadcom BCM50610M",
1255 /* PHY_GBIT_FEATURES */
1256 .get_sset_count = bcm_phy_get_sset_count,
1257 .get_strings = bcm_phy_get_strings,
1258 .get_stats = bcm54xx_get_stats,
1259 .probe = bcm54xx_phy_probe,
1260 .config_init = bcm54xx_config_init,
1261 .config_intr = bcm_phy_config_intr,
1262 .handle_interrupt = bcm_phy_handle_interrupt,
1263 .link_change_notify = bcm54xx_link_change_notify,
1264 .suspend = bcm54xx_suspend,
1265 .resume = bcm54xx_resume,
1266 .led_brightness_set = bcm_phy_led_brightness_set,
1267}, {
1268 .phy_id = PHY_ID_BCM57780,
1269 .phy_id_mask = 0xfffffff0,
1270 .name = "Broadcom BCM57780",
1271 /* PHY_GBIT_FEATURES */
1272 .get_sset_count = bcm_phy_get_sset_count,
1273 .get_strings = bcm_phy_get_strings,
1274 .get_stats = bcm54xx_get_stats,
1275 .probe = bcm54xx_phy_probe,
1276 .config_init = bcm54xx_config_init,
1277 .config_intr = bcm_phy_config_intr,
1278 .handle_interrupt = bcm_phy_handle_interrupt,
1279 .link_change_notify = bcm54xx_link_change_notify,
1280 .led_brightness_set = bcm_phy_led_brightness_set,
1281}, {
1282 .phy_id = PHY_ID_BCMAC131,
1283 .phy_id_mask = 0xfffffff0,
1284 .name = "Broadcom BCMAC131",
1285 /* PHY_BASIC_FEATURES */
1286 .config_init = brcm_fet_config_init,
1287 .config_intr = brcm_fet_config_intr,
1288 .handle_interrupt = brcm_fet_handle_interrupt,
1289 .suspend = brcm_fet_suspend,
1290 .resume = brcm_fet_config_init,
1291}, {
1292 .phy_id = PHY_ID_BCM5241,
1293 .phy_id_mask = 0xfffffff0,
1294 .name = "Broadcom BCM5241",
1295 /* PHY_BASIC_FEATURES */
1296 .config_init = brcm_fet_config_init,
1297 .config_intr = brcm_fet_config_intr,
1298 .handle_interrupt = brcm_fet_handle_interrupt,
1299 .suspend = brcm_fet_suspend,
1300 .resume = brcm_fet_config_init,
1301}, {
1302 .phy_id = PHY_ID_BCM5221,
1303 .phy_id_mask = 0xfffffff0,
1304 .name = "Broadcom BCM5221",
1305 /* PHY_BASIC_FEATURES */
1306 .config_init = brcm_fet_config_init,
1307 .config_intr = brcm_fet_config_intr,
1308 .handle_interrupt = brcm_fet_handle_interrupt,
1309 .suspend = brcm_fet_suspend,
1310 .resume = brcm_fet_config_init,
1311 .config_aneg = bcm5221_config_aneg,
1312 .read_status = bcm5221_read_status,
1313}, {
1314 .phy_id = PHY_ID_BCM5395,
1315 .phy_id_mask = 0xfffffff0,
1316 .name = "Broadcom BCM5395",
1317 .flags = PHY_IS_INTERNAL,
1318 /* PHY_GBIT_FEATURES */
1319 .get_sset_count = bcm_phy_get_sset_count,
1320 .get_strings = bcm_phy_get_strings,
1321 .get_stats = bcm54xx_get_stats,
1322 .probe = bcm54xx_phy_probe,
1323 .link_change_notify = bcm54xx_link_change_notify,
1324 .led_brightness_set = bcm_phy_led_brightness_set,
1325}, {
1326 .phy_id = PHY_ID_BCM53125,
1327 .phy_id_mask = 0xfffffff0,
1328 .name = "Broadcom BCM53125",
1329 .flags = PHY_IS_INTERNAL,
1330 /* PHY_GBIT_FEATURES */
1331 .get_sset_count = bcm_phy_get_sset_count,
1332 .get_strings = bcm_phy_get_strings,
1333 .get_stats = bcm54xx_get_stats,
1334 .probe = bcm54xx_phy_probe,
1335 .config_init = bcm54xx_config_init,
1336 .config_intr = bcm_phy_config_intr,
1337 .handle_interrupt = bcm_phy_handle_interrupt,
1338 .link_change_notify = bcm54xx_link_change_notify,
1339 .led_brightness_set = bcm_phy_led_brightness_set,
1340}, {
1341 .phy_id = PHY_ID_BCM53128,
1342 .phy_id_mask = 0xfffffff0,
1343 .name = "Broadcom BCM53128",
1344 .flags = PHY_IS_INTERNAL,
1345 /* PHY_GBIT_FEATURES */
1346 .get_sset_count = bcm_phy_get_sset_count,
1347 .get_strings = bcm_phy_get_strings,
1348 .get_stats = bcm54xx_get_stats,
1349 .probe = bcm54xx_phy_probe,
1350 .config_init = bcm54xx_config_init,
1351 .config_intr = bcm_phy_config_intr,
1352 .handle_interrupt = bcm_phy_handle_interrupt,
1353 .link_change_notify = bcm54xx_link_change_notify,
1354 .led_brightness_set = bcm_phy_led_brightness_set,
1355}, {
1356 .phy_id = PHY_ID_BCM89610,
1357 .phy_id_mask = 0xfffffff0,
1358 .name = "Broadcom BCM89610",
1359 /* PHY_GBIT_FEATURES */
1360 .get_sset_count = bcm_phy_get_sset_count,
1361 .get_strings = bcm_phy_get_strings,
1362 .get_stats = bcm54xx_get_stats,
1363 .probe = bcm54xx_phy_probe,
1364 .config_init = bcm54xx_config_init,
1365 .config_intr = bcm_phy_config_intr,
1366 .handle_interrupt = bcm_phy_handle_interrupt,
1367 .link_change_notify = bcm54xx_link_change_notify,
1368} };
1369
1370module_phy_driver(broadcom_drivers);
1371
1372static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
1373 { PHY_ID_BCM5411, 0xfffffff0 },
1374 { PHY_ID_BCM5421, 0xfffffff0 },
1375 { PHY_ID_BCM54210E, 0xfffffff0 },
1376 { PHY_ID_BCM5461, 0xfffffff0 },
1377 { PHY_ID_BCM54612E, 0xfffffff0 },
1378 { PHY_ID_BCM54616S, 0xfffffff0 },
1379 { PHY_ID_BCM5464, 0xfffffff0 },
1380 { PHY_ID_BCM5481, 0xfffffff0 },
1381 { PHY_ID_BCM54810, 0xfffffff0 },
1382 { PHY_ID_BCM54811, 0xfffffff0 },
1383 { PHY_ID_BCM5482, 0xfffffff0 },
1384 { PHY_ID_BCM50610, 0xfffffff0 },
1385 { PHY_ID_BCM50610M, 0xfffffff0 },
1386 { PHY_ID_BCM57780, 0xfffffff0 },
1387 { PHY_ID_BCMAC131, 0xfffffff0 },
1388 { PHY_ID_BCM5221, 0xfffffff0 },
1389 { PHY_ID_BCM5241, 0xfffffff0 },
1390 { PHY_ID_BCM5395, 0xfffffff0 },
1391 { PHY_ID_BCM53125, 0xfffffff0 },
1392 { PHY_ID_BCM53128, 0xfffffff0 },
1393 { PHY_ID_BCM89610, 0xfffffff0 },
1394 { }
1395};
1396
1397MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13#include "bcm-phy-lib.h"
14#include <linux/module.h>
15#include <linux/phy.h>
16#include <linux/brcmphy.h>
17#include <linux/of.h>
18
19#define BRCM_PHY_MODEL(phydev) \
20 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
21
22#define BRCM_PHY_REV(phydev) \
23 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
24
25MODULE_DESCRIPTION("Broadcom PHY driver");
26MODULE_AUTHOR("Maciej W. Rozycki");
27MODULE_LICENSE("GPL");
28
29static int bcm54xx_config_clock_delay(struct phy_device *phydev);
30
31static int bcm54210e_config_init(struct phy_device *phydev)
32{
33 int val;
34
35 bcm54xx_config_clock_delay(phydev);
36
37 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
38 val = phy_read(phydev, MII_CTRL1000);
39 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
40 phy_write(phydev, MII_CTRL1000, val);
41 }
42
43 return 0;
44}
45
46static int bcm54612e_config_init(struct phy_device *phydev)
47{
48 int reg;
49
50 bcm54xx_config_clock_delay(phydev);
51
52 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
53 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
54 int err;
55
56 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
57 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
58 BCM54612E_LED4_CLK125OUT_EN | reg);
59
60 if (err < 0)
61 return err;
62 }
63
64 return 0;
65}
66
67static int bcm54xx_config_clock_delay(struct phy_device *phydev)
68{
69 int rc, val;
70
71 /* handling PHY's internal RX clock delay */
72 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
73 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
74 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
75 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
76 /* Disable RGMII RXC-RXD skew */
77 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
78 }
79 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
80 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
81 /* Enable RGMII RXC-RXD skew */
82 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
83 }
84 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
85 val);
86 if (rc < 0)
87 return rc;
88
89 /* handling PHY's internal TX clock delay */
90 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
91 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
92 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
93 /* Disable internal TX clock delay */
94 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
95 }
96 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
97 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
98 /* Enable internal TX clock delay */
99 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
100 }
101 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
102 if (rc < 0)
103 return rc;
104
105 return 0;
106}
107
108/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
109static int bcm50610_a0_workaround(struct phy_device *phydev)
110{
111 int err;
112
113 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
114 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
115 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
116 if (err < 0)
117 return err;
118
119 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
120 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
121 if (err < 0)
122 return err;
123
124 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
125 MII_BCM54XX_EXP_EXP75_VDACCTRL);
126 if (err < 0)
127 return err;
128
129 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
130 MII_BCM54XX_EXP_EXP96_MYST);
131 if (err < 0)
132 return err;
133
134 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
135 MII_BCM54XX_EXP_EXP97_MYST);
136
137 return err;
138}
139
140static int bcm54xx_phydsp_config(struct phy_device *phydev)
141{
142 int err, err2;
143
144 /* Enable the SMDSP clock */
145 err = bcm54xx_auxctl_write(phydev,
146 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
147 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
148 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
149 if (err < 0)
150 return err;
151
152 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
153 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
154 /* Clear bit 9 to fix a phy interop issue. */
155 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
156 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
157 if (err < 0)
158 goto error;
159
160 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
161 err = bcm50610_a0_workaround(phydev);
162 if (err < 0)
163 goto error;
164 }
165 }
166
167 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
168 int val;
169
170 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
171 if (val < 0)
172 goto error;
173
174 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
175 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
176 }
177
178error:
179 /* Disable the SMDSP clock */
180 err2 = bcm54xx_auxctl_write(phydev,
181 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
182 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
183
184 /* Return the first error reported. */
185 return err ? err : err2;
186}
187
188static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
189{
190 u32 orig;
191 int val;
192 bool clk125en = true;
193
194 /* Abort if we are using an untested phy. */
195 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
196 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
197 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
198 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
199 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
200 return;
201
202 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
203 if (val < 0)
204 return;
205
206 orig = val;
207
208 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
209 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
210 BRCM_PHY_REV(phydev) >= 0x3) {
211 /*
212 * Here, bit 0 _disables_ CLK125 when set.
213 * This bit is set by default.
214 */
215 clk125en = false;
216 } else {
217 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
218 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
219 /* Here, bit 0 _enables_ CLK125 when set */
220 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
221 }
222 clk125en = false;
223 }
224 }
225
226 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
227 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
228 else
229 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
230
231 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
232 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
233 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
234 val |= BCM54810_SHD_SCR3_TRDDAPD;
235 else
236 val |= BCM54XX_SHD_SCR3_TRDDAPD;
237 }
238
239 if (orig != val)
240 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
241
242 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
243 if (val < 0)
244 return;
245
246 orig = val;
247
248 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
249 val |= BCM54XX_SHD_APD_EN;
250 else
251 val &= ~BCM54XX_SHD_APD_EN;
252
253 if (orig != val)
254 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
255}
256
257static int bcm54xx_config_init(struct phy_device *phydev)
258{
259 int reg, err, val;
260
261 reg = phy_read(phydev, MII_BCM54XX_ECR);
262 if (reg < 0)
263 return reg;
264
265 /* Mask interrupts globally. */
266 reg |= MII_BCM54XX_ECR_IM;
267 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
268 if (err < 0)
269 return err;
270
271 /* Unmask events we are interested in. */
272 reg = ~(MII_BCM54XX_INT_DUPLEX |
273 MII_BCM54XX_INT_SPEED |
274 MII_BCM54XX_INT_LINK);
275 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
276 if (err < 0)
277 return err;
278
279 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
280 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
281 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
282 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
283
284 bcm54xx_adjust_rxrefclk(phydev);
285
286 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
287 err = bcm54210e_config_init(phydev);
288 if (err)
289 return err;
290 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
291 err = bcm54612e_config_init(phydev);
292 if (err)
293 return err;
294 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
295 /* For BCM54810, we need to disable BroadR-Reach function */
296 val = bcm_phy_read_exp(phydev,
297 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
298 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
299 err = bcm_phy_write_exp(phydev,
300 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
301 val);
302 if (err < 0)
303 return err;
304 }
305
306 bcm54xx_phydsp_config(phydev);
307
308 /* Encode link speed into LED1 and LED3 pair (green/amber).
309 * Also flash these two LEDs on activity. This means configuring
310 * them for MULTICOLOR and encoding link/activity into them.
311 */
312 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
313 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
314 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
315
316 val = BCM_LED_MULTICOLOR_IN_PHASE |
317 BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
318 BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
319 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
320
321 return 0;
322}
323
324static int bcm54xx_resume(struct phy_device *phydev)
325{
326 int ret;
327
328 /* Writes to register other than BMCR would be ignored
329 * unless we clear the PDOWN bit first
330 */
331 ret = genphy_resume(phydev);
332 if (ret < 0)
333 return ret;
334
335 return bcm54xx_config_init(phydev);
336}
337
338static int bcm54811_config_init(struct phy_device *phydev)
339{
340 int err, reg;
341
342 /* Disable BroadR-Reach function. */
343 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
344 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
345 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
346 reg);
347 if (err < 0)
348 return err;
349
350 err = bcm54xx_config_init(phydev);
351
352 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
353 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
354 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
355 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
356 BCM54612E_LED4_CLK125OUT_EN | reg);
357 if (err < 0)
358 return err;
359 }
360
361 return err;
362}
363
364static int bcm5482_config_init(struct phy_device *phydev)
365{
366 int err, reg;
367
368 err = bcm54xx_config_init(phydev);
369
370 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
371 /*
372 * Enable secondary SerDes and its use as an LED source
373 */
374 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
375 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
376 reg |
377 BCM5482_SHD_SSD_LEDM |
378 BCM5482_SHD_SSD_EN);
379
380 /*
381 * Enable SGMII slave mode and auto-detection
382 */
383 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
384 err = bcm_phy_read_exp(phydev, reg);
385 if (err < 0)
386 return err;
387 err = bcm_phy_write_exp(phydev, reg, err |
388 BCM5482_SSD_SGMII_SLAVE_EN |
389 BCM5482_SSD_SGMII_SLAVE_AD);
390 if (err < 0)
391 return err;
392
393 /*
394 * Disable secondary SerDes powerdown
395 */
396 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
397 err = bcm_phy_read_exp(phydev, reg);
398 if (err < 0)
399 return err;
400 err = bcm_phy_write_exp(phydev, reg,
401 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
402 if (err < 0)
403 return err;
404
405 /*
406 * Select 1000BASE-X register set (primary SerDes)
407 */
408 reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
409 bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
410 reg | BCM54XX_SHD_MODE_1000BX);
411
412 /*
413 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
414 * (Use LED1 as secondary SerDes ACTIVITY LED)
415 */
416 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
417 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
418 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
419
420 /*
421 * Auto-negotiation doesn't seem to work quite right
422 * in this mode, so we disable it and force it to the
423 * right speed/duplex setting. Only 'link status'
424 * is important.
425 */
426 phydev->autoneg = AUTONEG_DISABLE;
427 phydev->speed = SPEED_1000;
428 phydev->duplex = DUPLEX_FULL;
429 }
430
431 return err;
432}
433
434static int bcm5482_read_status(struct phy_device *phydev)
435{
436 int err;
437
438 err = genphy_read_status(phydev);
439
440 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
441 /*
442 * Only link status matters for 1000Base-X mode, so force
443 * 1000 Mbit/s full-duplex status
444 */
445 if (phydev->link) {
446 phydev->speed = SPEED_1000;
447 phydev->duplex = DUPLEX_FULL;
448 }
449 }
450
451 return err;
452}
453
454static int bcm5481_config_aneg(struct phy_device *phydev)
455{
456 struct device_node *np = phydev->mdio.dev.of_node;
457 int ret;
458
459 /* Aneg firstly. */
460 ret = genphy_config_aneg(phydev);
461
462 /* Then we can set up the delay. */
463 bcm54xx_config_clock_delay(phydev);
464
465 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
466 /* Lane Swap - Undocumented register...magic! */
467 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
468 0x11B);
469 if (ret < 0)
470 return ret;
471 }
472
473 return ret;
474}
475
476static int bcm54616s_probe(struct phy_device *phydev)
477{
478 int val, intf_sel;
479
480 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
481 if (val < 0)
482 return val;
483
484 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
485 * is 01b, and the link between PHY and its link partner can be
486 * either 1000Base-X or 100Base-FX.
487 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
488 * support is still missing as of now.
489 */
490 intf_sel = (val & BCM54XX_SHD_INTF_SEL_MASK) >> 1;
491 if (intf_sel == 1) {
492 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
493 if (val < 0)
494 return val;
495
496 /* Bit 0 of the SerDes 100-FX Control register, when set
497 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
498 * When this bit is set to 0, it sets the GMII/RGMII ->
499 * 1000BASE-X configuration.
500 */
501 if (!(val & BCM54616S_100FX_MODE))
502 phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
503 }
504
505 return 0;
506}
507
508static int bcm54616s_config_aneg(struct phy_device *phydev)
509{
510 int ret;
511
512 /* Aneg firstly. */
513 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
514 ret = genphy_c37_config_aneg(phydev);
515 else
516 ret = genphy_config_aneg(phydev);
517
518 /* Then we can set up the delay. */
519 bcm54xx_config_clock_delay(phydev);
520
521 return ret;
522}
523
524static int bcm54616s_read_status(struct phy_device *phydev)
525{
526 int err;
527
528 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
529 err = genphy_c37_read_status(phydev);
530 else
531 err = genphy_read_status(phydev);
532
533 return err;
534}
535
536static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
537{
538 int val;
539
540 val = phy_read(phydev, reg);
541 if (val < 0)
542 return val;
543
544 return phy_write(phydev, reg, val | set);
545}
546
547static int brcm_fet_config_init(struct phy_device *phydev)
548{
549 int reg, err, err2, brcmtest;
550
551 /* Reset the PHY to bring it to a known state. */
552 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
553 if (err < 0)
554 return err;
555
556 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
557 if (reg < 0)
558 return reg;
559
560 /* Unmask events we are interested in and mask interrupts globally. */
561 reg = MII_BRCM_FET_IR_DUPLEX_EN |
562 MII_BRCM_FET_IR_SPEED_EN |
563 MII_BRCM_FET_IR_LINK_EN |
564 MII_BRCM_FET_IR_ENABLE |
565 MII_BRCM_FET_IR_MASK;
566
567 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
568 if (err < 0)
569 return err;
570
571 /* Enable shadow register access */
572 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
573 if (brcmtest < 0)
574 return brcmtest;
575
576 reg = brcmtest | MII_BRCM_FET_BT_SRE;
577
578 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
579 if (err < 0)
580 return err;
581
582 /* Set the LED mode */
583 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
584 if (reg < 0) {
585 err = reg;
586 goto done;
587 }
588
589 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
590 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
591
592 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
593 if (err < 0)
594 goto done;
595
596 /* Enable auto MDIX */
597 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
598 MII_BRCM_FET_SHDW_MC_FAME);
599 if (err < 0)
600 goto done;
601
602 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
603 /* Enable auto power down */
604 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
605 MII_BRCM_FET_SHDW_AS2_APDE);
606 }
607
608done:
609 /* Disable shadow register access */
610 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
611 if (!err)
612 err = err2;
613
614 return err;
615}
616
617static int brcm_fet_ack_interrupt(struct phy_device *phydev)
618{
619 int reg;
620
621 /* Clear pending interrupts. */
622 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
623 if (reg < 0)
624 return reg;
625
626 return 0;
627}
628
629static int brcm_fet_config_intr(struct phy_device *phydev)
630{
631 int reg, err;
632
633 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
634 if (reg < 0)
635 return reg;
636
637 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
638 reg &= ~MII_BRCM_FET_IR_MASK;
639 else
640 reg |= MII_BRCM_FET_IR_MASK;
641
642 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
643 return err;
644}
645
646struct bcm53xx_phy_priv {
647 u64 *stats;
648};
649
650static int bcm53xx_phy_probe(struct phy_device *phydev)
651{
652 struct bcm53xx_phy_priv *priv;
653
654 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
655 if (!priv)
656 return -ENOMEM;
657
658 phydev->priv = priv;
659
660 priv->stats = devm_kcalloc(&phydev->mdio.dev,
661 bcm_phy_get_sset_count(phydev), sizeof(u64),
662 GFP_KERNEL);
663 if (!priv->stats)
664 return -ENOMEM;
665
666 return 0;
667}
668
669static void bcm53xx_phy_get_stats(struct phy_device *phydev,
670 struct ethtool_stats *stats, u64 *data)
671{
672 struct bcm53xx_phy_priv *priv = phydev->priv;
673
674 bcm_phy_get_stats(phydev, priv->stats, stats, data);
675}
676
677static struct phy_driver broadcom_drivers[] = {
678{
679 .phy_id = PHY_ID_BCM5411,
680 .phy_id_mask = 0xfffffff0,
681 .name = "Broadcom BCM5411",
682 /* PHY_GBIT_FEATURES */
683 .config_init = bcm54xx_config_init,
684 .ack_interrupt = bcm_phy_ack_intr,
685 .config_intr = bcm_phy_config_intr,
686}, {
687 .phy_id = PHY_ID_BCM5421,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM5421",
690 /* PHY_GBIT_FEATURES */
691 .config_init = bcm54xx_config_init,
692 .ack_interrupt = bcm_phy_ack_intr,
693 .config_intr = bcm_phy_config_intr,
694}, {
695 .phy_id = PHY_ID_BCM54210E,
696 .phy_id_mask = 0xfffffff0,
697 .name = "Broadcom BCM54210E",
698 /* PHY_GBIT_FEATURES */
699 .config_init = bcm54xx_config_init,
700 .ack_interrupt = bcm_phy_ack_intr,
701 .config_intr = bcm_phy_config_intr,
702}, {
703 .phy_id = PHY_ID_BCM5461,
704 .phy_id_mask = 0xfffffff0,
705 .name = "Broadcom BCM5461",
706 /* PHY_GBIT_FEATURES */
707 .config_init = bcm54xx_config_init,
708 .ack_interrupt = bcm_phy_ack_intr,
709 .config_intr = bcm_phy_config_intr,
710}, {
711 .phy_id = PHY_ID_BCM54612E,
712 .phy_id_mask = 0xfffffff0,
713 .name = "Broadcom BCM54612E",
714 /* PHY_GBIT_FEATURES */
715 .config_init = bcm54xx_config_init,
716 .ack_interrupt = bcm_phy_ack_intr,
717 .config_intr = bcm_phy_config_intr,
718}, {
719 .phy_id = PHY_ID_BCM54616S,
720 .phy_id_mask = 0xfffffff0,
721 .name = "Broadcom BCM54616S",
722 /* PHY_GBIT_FEATURES */
723 .config_init = bcm54xx_config_init,
724 .config_aneg = bcm54616s_config_aneg,
725 .ack_interrupt = bcm_phy_ack_intr,
726 .config_intr = bcm_phy_config_intr,
727 .read_status = bcm54616s_read_status,
728 .probe = bcm54616s_probe,
729}, {
730 .phy_id = PHY_ID_BCM5464,
731 .phy_id_mask = 0xfffffff0,
732 .name = "Broadcom BCM5464",
733 /* PHY_GBIT_FEATURES */
734 .config_init = bcm54xx_config_init,
735 .ack_interrupt = bcm_phy_ack_intr,
736 .config_intr = bcm_phy_config_intr,
737 .suspend = genphy_suspend,
738 .resume = genphy_resume,
739}, {
740 .phy_id = PHY_ID_BCM5481,
741 .phy_id_mask = 0xfffffff0,
742 .name = "Broadcom BCM5481",
743 /* PHY_GBIT_FEATURES */
744 .config_init = bcm54xx_config_init,
745 .config_aneg = bcm5481_config_aneg,
746 .ack_interrupt = bcm_phy_ack_intr,
747 .config_intr = bcm_phy_config_intr,
748}, {
749 .phy_id = PHY_ID_BCM54810,
750 .phy_id_mask = 0xfffffff0,
751 .name = "Broadcom BCM54810",
752 /* PHY_GBIT_FEATURES */
753 .config_init = bcm54xx_config_init,
754 .config_aneg = bcm5481_config_aneg,
755 .ack_interrupt = bcm_phy_ack_intr,
756 .config_intr = bcm_phy_config_intr,
757 .suspend = genphy_suspend,
758 .resume = bcm54xx_resume,
759}, {
760 .phy_id = PHY_ID_BCM54811,
761 .phy_id_mask = 0xfffffff0,
762 .name = "Broadcom BCM54811",
763 /* PHY_GBIT_FEATURES */
764 .config_init = bcm54811_config_init,
765 .config_aneg = bcm5481_config_aneg,
766 .ack_interrupt = bcm_phy_ack_intr,
767 .config_intr = bcm_phy_config_intr,
768 .suspend = genphy_suspend,
769 .resume = bcm54xx_resume,
770}, {
771 .phy_id = PHY_ID_BCM5482,
772 .phy_id_mask = 0xfffffff0,
773 .name = "Broadcom BCM5482",
774 /* PHY_GBIT_FEATURES */
775 .config_init = bcm5482_config_init,
776 .read_status = bcm5482_read_status,
777 .ack_interrupt = bcm_phy_ack_intr,
778 .config_intr = bcm_phy_config_intr,
779}, {
780 .phy_id = PHY_ID_BCM50610,
781 .phy_id_mask = 0xfffffff0,
782 .name = "Broadcom BCM50610",
783 /* PHY_GBIT_FEATURES */
784 .config_init = bcm54xx_config_init,
785 .ack_interrupt = bcm_phy_ack_intr,
786 .config_intr = bcm_phy_config_intr,
787}, {
788 .phy_id = PHY_ID_BCM50610M,
789 .phy_id_mask = 0xfffffff0,
790 .name = "Broadcom BCM50610M",
791 /* PHY_GBIT_FEATURES */
792 .config_init = bcm54xx_config_init,
793 .ack_interrupt = bcm_phy_ack_intr,
794 .config_intr = bcm_phy_config_intr,
795}, {
796 .phy_id = PHY_ID_BCM57780,
797 .phy_id_mask = 0xfffffff0,
798 .name = "Broadcom BCM57780",
799 /* PHY_GBIT_FEATURES */
800 .config_init = bcm54xx_config_init,
801 .ack_interrupt = bcm_phy_ack_intr,
802 .config_intr = bcm_phy_config_intr,
803}, {
804 .phy_id = PHY_ID_BCMAC131,
805 .phy_id_mask = 0xfffffff0,
806 .name = "Broadcom BCMAC131",
807 /* PHY_BASIC_FEATURES */
808 .config_init = brcm_fet_config_init,
809 .ack_interrupt = brcm_fet_ack_interrupt,
810 .config_intr = brcm_fet_config_intr,
811}, {
812 .phy_id = PHY_ID_BCM5241,
813 .phy_id_mask = 0xfffffff0,
814 .name = "Broadcom BCM5241",
815 /* PHY_BASIC_FEATURES */
816 .config_init = brcm_fet_config_init,
817 .ack_interrupt = brcm_fet_ack_interrupt,
818 .config_intr = brcm_fet_config_intr,
819}, {
820 .phy_id = PHY_ID_BCM5395,
821 .phy_id_mask = 0xfffffff0,
822 .name = "Broadcom BCM5395",
823 .flags = PHY_IS_INTERNAL,
824 /* PHY_GBIT_FEATURES */
825 .get_sset_count = bcm_phy_get_sset_count,
826 .get_strings = bcm_phy_get_strings,
827 .get_stats = bcm53xx_phy_get_stats,
828 .probe = bcm53xx_phy_probe,
829}, {
830 .phy_id = PHY_ID_BCM53125,
831 .phy_id_mask = 0xfffffff0,
832 .name = "Broadcom BCM53125",
833 .flags = PHY_IS_INTERNAL,
834 /* PHY_GBIT_FEATURES */
835 .get_sset_count = bcm_phy_get_sset_count,
836 .get_strings = bcm_phy_get_strings,
837 .get_stats = bcm53xx_phy_get_stats,
838 .probe = bcm53xx_phy_probe,
839 .config_init = bcm54xx_config_init,
840 .ack_interrupt = bcm_phy_ack_intr,
841 .config_intr = bcm_phy_config_intr,
842}, {
843 .phy_id = PHY_ID_BCM89610,
844 .phy_id_mask = 0xfffffff0,
845 .name = "Broadcom BCM89610",
846 /* PHY_GBIT_FEATURES */
847 .config_init = bcm54xx_config_init,
848 .ack_interrupt = bcm_phy_ack_intr,
849 .config_intr = bcm_phy_config_intr,
850} };
851
852module_phy_driver(broadcom_drivers);
853
854static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
855 { PHY_ID_BCM5411, 0xfffffff0 },
856 { PHY_ID_BCM5421, 0xfffffff0 },
857 { PHY_ID_BCM54210E, 0xfffffff0 },
858 { PHY_ID_BCM5461, 0xfffffff0 },
859 { PHY_ID_BCM54612E, 0xfffffff0 },
860 { PHY_ID_BCM54616S, 0xfffffff0 },
861 { PHY_ID_BCM5464, 0xfffffff0 },
862 { PHY_ID_BCM5481, 0xfffffff0 },
863 { PHY_ID_BCM54810, 0xfffffff0 },
864 { PHY_ID_BCM54811, 0xfffffff0 },
865 { PHY_ID_BCM5482, 0xfffffff0 },
866 { PHY_ID_BCM50610, 0xfffffff0 },
867 { PHY_ID_BCM50610M, 0xfffffff0 },
868 { PHY_ID_BCM57780, 0xfffffff0 },
869 { PHY_ID_BCMAC131, 0xfffffff0 },
870 { PHY_ID_BCM5241, 0xfffffff0 },
871 { PHY_ID_BCM5395, 0xfffffff0 },
872 { PHY_ID_BCM53125, 0xfffffff0 },
873 { PHY_ID_BCM89610, 0xfffffff0 },
874 { }
875};
876
877MODULE_DEVICE_TABLE(mdio, broadcom_tbl);