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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4/* ethtool support for ixgbe */
5
6#include <linux/interrupt.h>
7#include <linux/types.h>
8#include <linux/module.h>
9#include <linux/slab.h>
10#include <linux/pci.h>
11#include <linux/netdevice.h>
12#include <linux/ethtool.h>
13#include <linux/vmalloc.h>
14#include <linux/highmem.h>
15#include <linux/uaccess.h>
16
17#include "ixgbe.h"
18#include "ixgbe_phy.h"
19
20
21enum {NETDEV_STATS, IXGBE_STATS};
22
23struct ixgbe_stats {
24 char stat_string[ETH_GSTRING_LEN];
25 int type;
26 int sizeof_stat;
27 int stat_offset;
28};
29
30#define IXGBE_STAT(m) IXGBE_STATS, \
31 sizeof(((struct ixgbe_adapter *)0)->m), \
32 offsetof(struct ixgbe_adapter, m)
33#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
34 sizeof(((struct rtnl_link_stats64 *)0)->m), \
35 offsetof(struct rtnl_link_stats64, m)
36
37static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
38 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
39 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
40 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
41 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
42 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
43 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
44 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
45 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
46 {"lsc_int", IXGBE_STAT(lsc_int)},
47 {"tx_busy", IXGBE_STAT(tx_busy)},
48 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
49 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
50 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
51 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
52 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
53 {"multicast", IXGBE_NETDEV_STAT(multicast)},
54 {"broadcast", IXGBE_STAT(stats.bprc)},
55 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
56 {"collisions", IXGBE_NETDEV_STAT(collisions)},
57 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
58 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
59 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
60 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
61 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
62 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
63 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
64 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
65 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
66 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
67 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
68 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
69 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
70 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
71 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
72 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
73 {"rx_length_errors", IXGBE_STAT(stats.rlec)},
74 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
75 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
76 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
77 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
78 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
79 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
80 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
81 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)},
82 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
83 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
84 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
85 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
86 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
87 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
88 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
89 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)},
90 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)},
91 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)},
92 {"tx_ipsec", IXGBE_STAT(tx_ipsec)},
93 {"rx_ipsec", IXGBE_STAT(rx_ipsec)},
94#ifdef IXGBE_FCOE
95 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
96 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
97 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
98 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
99 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
100 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
101 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
102 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
103#endif /* IXGBE_FCOE */
104};
105
106/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
107 * we set the num_rx_queues to evaluate to num_tx_queues. This is
108 * used because we do not have a good way to get the max number of
109 * rx queues with CONFIG_RPS disabled.
110 */
111#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
112
113#define IXGBE_QUEUE_STATS_LEN ( \
114 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
115 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
116#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
117#define IXGBE_PB_STATS_LEN ( \
118 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
119 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
120 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
121 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
122 / sizeof(u64))
123#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
124 IXGBE_PB_STATS_LEN + \
125 IXGBE_QUEUE_STATS_LEN)
126
127static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
128 "Register test (offline)", "Eeprom test (offline)",
129 "Interrupt test (offline)", "Loopback test (offline)",
130 "Link test (on/offline)"
131};
132#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
133
134static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = {
135#define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0)
136 "legacy-rx",
137#define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1)
138 "vf-ipsec",
139#define IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF BIT(2)
140 "mdd-disable-vf",
141};
142
143#define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings)
144
145#define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
146
147static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw,
148 struct ethtool_link_ksettings *cmd)
149{
150 if (!ixgbe_isbackplane(hw->phy.media_type)) {
151 ethtool_link_ksettings_add_link_mode(cmd, supported,
152 10000baseT_Full);
153 return;
154 }
155
156 switch (hw->device_id) {
157 case IXGBE_DEV_ID_82598:
158 case IXGBE_DEV_ID_82599_KX4:
159 case IXGBE_DEV_ID_82599_KX4_MEZZ:
160 case IXGBE_DEV_ID_X550EM_X_KX4:
161 ethtool_link_ksettings_add_link_mode
162 (cmd, supported, 10000baseKX4_Full);
163 break;
164 case IXGBE_DEV_ID_82598_BX:
165 case IXGBE_DEV_ID_82599_KR:
166 case IXGBE_DEV_ID_X550EM_X_KR:
167 case IXGBE_DEV_ID_X550EM_X_XFI:
168 ethtool_link_ksettings_add_link_mode
169 (cmd, supported, 10000baseKR_Full);
170 break;
171 default:
172 ethtool_link_ksettings_add_link_mode
173 (cmd, supported, 10000baseKX4_Full);
174 ethtool_link_ksettings_add_link_mode
175 (cmd, supported, 10000baseKR_Full);
176 break;
177 }
178}
179
180static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw,
181 struct ethtool_link_ksettings *cmd)
182{
183 if (!ixgbe_isbackplane(hw->phy.media_type)) {
184 ethtool_link_ksettings_add_link_mode(cmd, advertising,
185 10000baseT_Full);
186 return;
187 }
188
189 switch (hw->device_id) {
190 case IXGBE_DEV_ID_82598:
191 case IXGBE_DEV_ID_82599_KX4:
192 case IXGBE_DEV_ID_82599_KX4_MEZZ:
193 case IXGBE_DEV_ID_X550EM_X_KX4:
194 ethtool_link_ksettings_add_link_mode
195 (cmd, advertising, 10000baseKX4_Full);
196 break;
197 case IXGBE_DEV_ID_82598_BX:
198 case IXGBE_DEV_ID_82599_KR:
199 case IXGBE_DEV_ID_X550EM_X_KR:
200 case IXGBE_DEV_ID_X550EM_X_XFI:
201 ethtool_link_ksettings_add_link_mode
202 (cmd, advertising, 10000baseKR_Full);
203 break;
204 default:
205 ethtool_link_ksettings_add_link_mode
206 (cmd, advertising, 10000baseKX4_Full);
207 ethtool_link_ksettings_add_link_mode
208 (cmd, advertising, 10000baseKR_Full);
209 break;
210 }
211}
212
213static int ixgbe_get_link_ksettings(struct net_device *netdev,
214 struct ethtool_link_ksettings *cmd)
215{
216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
217 struct ixgbe_hw *hw = &adapter->hw;
218 ixgbe_link_speed supported_link;
219 bool autoneg = false;
220
221 ethtool_link_ksettings_zero_link_mode(cmd, supported);
222 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
223
224 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
225
226 /* set the supported link speeds */
227 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) {
228 ixgbe_set_supported_10gtypes(hw, cmd);
229 ixgbe_set_advertising_10gtypes(hw, cmd);
230 }
231 if (supported_link & IXGBE_LINK_SPEED_5GB_FULL)
232 ethtool_link_ksettings_add_link_mode(cmd, supported,
233 5000baseT_Full);
234
235 if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL)
236 ethtool_link_ksettings_add_link_mode(cmd, supported,
237 2500baseT_Full);
238
239 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) {
240 if (ixgbe_isbackplane(hw->phy.media_type)) {
241 ethtool_link_ksettings_add_link_mode(cmd, supported,
242 1000baseKX_Full);
243 ethtool_link_ksettings_add_link_mode(cmd, advertising,
244 1000baseKX_Full);
245 } else {
246 ethtool_link_ksettings_add_link_mode(cmd, supported,
247 1000baseT_Full);
248 ethtool_link_ksettings_add_link_mode(cmd, advertising,
249 1000baseT_Full);
250 }
251 }
252 if (supported_link & IXGBE_LINK_SPEED_100_FULL) {
253 ethtool_link_ksettings_add_link_mode(cmd, supported,
254 100baseT_Full);
255 ethtool_link_ksettings_add_link_mode(cmd, advertising,
256 100baseT_Full);
257 }
258 if (supported_link & IXGBE_LINK_SPEED_10_FULL) {
259 ethtool_link_ksettings_add_link_mode(cmd, supported,
260 10baseT_Full);
261 ethtool_link_ksettings_add_link_mode(cmd, advertising,
262 10baseT_Full);
263 }
264
265 /* set the advertised speeds */
266 if (hw->phy.autoneg_advertised) {
267 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
268 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
269 ethtool_link_ksettings_add_link_mode(cmd, advertising,
270 10baseT_Full);
271 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
272 ethtool_link_ksettings_add_link_mode(cmd, advertising,
273 100baseT_Full);
274 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
275 ixgbe_set_advertising_10gtypes(hw, cmd);
276 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
277 if (ethtool_link_ksettings_test_link_mode
278 (cmd, supported, 1000baseKX_Full))
279 ethtool_link_ksettings_add_link_mode
280 (cmd, advertising, 1000baseKX_Full);
281 else
282 ethtool_link_ksettings_add_link_mode
283 (cmd, advertising, 1000baseT_Full);
284 }
285 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL)
286 ethtool_link_ksettings_add_link_mode(cmd, advertising,
287 5000baseT_Full);
288 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
289 ethtool_link_ksettings_add_link_mode(cmd, advertising,
290 2500baseT_Full);
291 } else {
292 if (hw->phy.multispeed_fiber && !autoneg) {
293 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
294 ethtool_link_ksettings_add_link_mode
295 (cmd, advertising, 10000baseT_Full);
296 }
297 }
298
299 if (autoneg) {
300 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
301 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
302 cmd->base.autoneg = AUTONEG_ENABLE;
303 } else
304 cmd->base.autoneg = AUTONEG_DISABLE;
305
306 /* Determine the remaining settings based on the PHY type. */
307 switch (adapter->hw.phy.type) {
308 case ixgbe_phy_tn:
309 case ixgbe_phy_aq:
310 case ixgbe_phy_x550em_ext_t:
311 case ixgbe_phy_fw:
312 case ixgbe_phy_cu_unknown:
313 ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
314 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
315 cmd->base.port = PORT_TP;
316 break;
317 case ixgbe_phy_qt:
318 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
319 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
320 cmd->base.port = PORT_FIBRE;
321 break;
322 case ixgbe_phy_nl:
323 case ixgbe_phy_sfp_passive_tyco:
324 case ixgbe_phy_sfp_passive_unknown:
325 case ixgbe_phy_sfp_ftl:
326 case ixgbe_phy_sfp_avago:
327 case ixgbe_phy_sfp_intel:
328 case ixgbe_phy_sfp_unknown:
329 case ixgbe_phy_qsfp_passive_unknown:
330 case ixgbe_phy_qsfp_active_unknown:
331 case ixgbe_phy_qsfp_intel:
332 case ixgbe_phy_qsfp_unknown:
333 /* SFP+ devices, further checking needed */
334 switch (adapter->hw.phy.sfp_type) {
335 case ixgbe_sfp_type_da_cu:
336 case ixgbe_sfp_type_da_cu_core0:
337 case ixgbe_sfp_type_da_cu_core1:
338 ethtool_link_ksettings_add_link_mode(cmd, supported,
339 FIBRE);
340 ethtool_link_ksettings_add_link_mode(cmd, advertising,
341 FIBRE);
342 cmd->base.port = PORT_DA;
343 break;
344 case ixgbe_sfp_type_sr:
345 case ixgbe_sfp_type_lr:
346 case ixgbe_sfp_type_srlr_core0:
347 case ixgbe_sfp_type_srlr_core1:
348 case ixgbe_sfp_type_1g_sx_core0:
349 case ixgbe_sfp_type_1g_sx_core1:
350 case ixgbe_sfp_type_1g_lx_core0:
351 case ixgbe_sfp_type_1g_lx_core1:
352 ethtool_link_ksettings_add_link_mode(cmd, supported,
353 FIBRE);
354 ethtool_link_ksettings_add_link_mode(cmd, advertising,
355 FIBRE);
356 cmd->base.port = PORT_FIBRE;
357 break;
358 case ixgbe_sfp_type_not_present:
359 ethtool_link_ksettings_add_link_mode(cmd, supported,
360 FIBRE);
361 ethtool_link_ksettings_add_link_mode(cmd, advertising,
362 FIBRE);
363 cmd->base.port = PORT_NONE;
364 break;
365 case ixgbe_sfp_type_1g_cu_core0:
366 case ixgbe_sfp_type_1g_cu_core1:
367 ethtool_link_ksettings_add_link_mode(cmd, supported,
368 TP);
369 ethtool_link_ksettings_add_link_mode(cmd, advertising,
370 TP);
371 cmd->base.port = PORT_TP;
372 break;
373 case ixgbe_sfp_type_unknown:
374 default:
375 ethtool_link_ksettings_add_link_mode(cmd, supported,
376 FIBRE);
377 ethtool_link_ksettings_add_link_mode(cmd, advertising,
378 FIBRE);
379 cmd->base.port = PORT_OTHER;
380 break;
381 }
382 break;
383 case ixgbe_phy_xaui:
384 ethtool_link_ksettings_add_link_mode(cmd, supported,
385 FIBRE);
386 ethtool_link_ksettings_add_link_mode(cmd, advertising,
387 FIBRE);
388 cmd->base.port = PORT_NONE;
389 break;
390 case ixgbe_phy_unknown:
391 case ixgbe_phy_generic:
392 case ixgbe_phy_sfp_unsupported:
393 default:
394 ethtool_link_ksettings_add_link_mode(cmd, supported,
395 FIBRE);
396 ethtool_link_ksettings_add_link_mode(cmd, advertising,
397 FIBRE);
398 cmd->base.port = PORT_OTHER;
399 break;
400 }
401
402 /* Indicate pause support */
403 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
404
405 switch (hw->fc.requested_mode) {
406 case ixgbe_fc_full:
407 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
408 break;
409 case ixgbe_fc_rx_pause:
410 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
411 ethtool_link_ksettings_add_link_mode(cmd, advertising,
412 Asym_Pause);
413 break;
414 case ixgbe_fc_tx_pause:
415 ethtool_link_ksettings_add_link_mode(cmd, advertising,
416 Asym_Pause);
417 break;
418 default:
419 ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause);
420 ethtool_link_ksettings_del_link_mode(cmd, advertising,
421 Asym_Pause);
422 }
423
424 if (netif_carrier_ok(netdev)) {
425 switch (adapter->link_speed) {
426 case IXGBE_LINK_SPEED_10GB_FULL:
427 cmd->base.speed = SPEED_10000;
428 break;
429 case IXGBE_LINK_SPEED_5GB_FULL:
430 cmd->base.speed = SPEED_5000;
431 break;
432 case IXGBE_LINK_SPEED_2_5GB_FULL:
433 cmd->base.speed = SPEED_2500;
434 break;
435 case IXGBE_LINK_SPEED_1GB_FULL:
436 cmd->base.speed = SPEED_1000;
437 break;
438 case IXGBE_LINK_SPEED_100_FULL:
439 cmd->base.speed = SPEED_100;
440 break;
441 case IXGBE_LINK_SPEED_10_FULL:
442 cmd->base.speed = SPEED_10;
443 break;
444 default:
445 break;
446 }
447 cmd->base.duplex = DUPLEX_FULL;
448 } else {
449 cmd->base.speed = SPEED_UNKNOWN;
450 cmd->base.duplex = DUPLEX_UNKNOWN;
451 }
452
453 return 0;
454}
455
456static int ixgbe_set_link_ksettings(struct net_device *netdev,
457 const struct ethtool_link_ksettings *cmd)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 struct ixgbe_hw *hw = &adapter->hw;
461 u32 advertised, old;
462 s32 err = 0;
463
464 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
465 (hw->phy.multispeed_fiber)) {
466 /*
467 * this function does not support duplex forcing, but can
468 * limit the advertising of the adapter to the specified speed
469 */
470 if (!linkmode_subset(cmd->link_modes.advertising,
471 cmd->link_modes.supported))
472 return -EINVAL;
473
474 /* only allow one speed at a time if no autoneg */
475 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) {
476 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
477 10000baseT_Full) &&
478 ethtool_link_ksettings_test_link_mode(cmd, advertising,
479 1000baseT_Full))
480 return -EINVAL;
481 }
482
483 old = hw->phy.autoneg_advertised;
484 advertised = 0;
485 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
486 10000baseT_Full))
487 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
488 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
489 5000baseT_Full))
490 advertised |= IXGBE_LINK_SPEED_5GB_FULL;
491 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
492 2500baseT_Full))
493 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
494 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
495 1000baseT_Full))
496 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
497
498 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
499 100baseT_Full))
500 advertised |= IXGBE_LINK_SPEED_100_FULL;
501
502 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
503 10baseT_Full))
504 advertised |= IXGBE_LINK_SPEED_10_FULL;
505
506 if (old == advertised)
507 return err;
508 /* this sets the link speed and restarts auto-neg */
509 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
510 usleep_range(1000, 2000);
511
512 hw->mac.autotry_restart = true;
513 err = hw->mac.ops.setup_link(hw, advertised, true);
514 if (err) {
515 e_info(probe, "setup link failed with code %d\n", err);
516 hw->mac.ops.setup_link(hw, old, true);
517 }
518 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
519 } else {
520 /* in this case we currently only support 10Gb/FULL */
521 u32 speed = cmd->base.speed;
522
523 if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
524 (!ethtool_link_ksettings_test_link_mode(cmd, advertising,
525 10000baseT_Full)) ||
526 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL))
527 return -EINVAL;
528 }
529
530 return err;
531}
532
533static void ixgbe_get_pause_stats(struct net_device *netdev,
534 struct ethtool_pause_stats *stats)
535{
536 struct ixgbe_adapter *adapter = netdev_priv(netdev);
537 struct ixgbe_hw_stats *hwstats = &adapter->stats;
538
539 stats->tx_pause_frames = hwstats->lxontxc + hwstats->lxofftxc;
540 stats->rx_pause_frames = hwstats->lxonrxc + hwstats->lxoffrxc;
541}
542
543static void ixgbe_get_pauseparam(struct net_device *netdev,
544 struct ethtool_pauseparam *pause)
545{
546 struct ixgbe_adapter *adapter = netdev_priv(netdev);
547 struct ixgbe_hw *hw = &adapter->hw;
548
549 if (ixgbe_device_supports_autoneg_fc(hw) &&
550 !hw->fc.disable_fc_autoneg)
551 pause->autoneg = 1;
552 else
553 pause->autoneg = 0;
554
555 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
556 pause->rx_pause = 1;
557 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
558 pause->tx_pause = 1;
559 } else if (hw->fc.current_mode == ixgbe_fc_full) {
560 pause->rx_pause = 1;
561 pause->tx_pause = 1;
562 }
563}
564
565static int ixgbe_set_pauseparam(struct net_device *netdev,
566 struct ethtool_pauseparam *pause)
567{
568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
569 struct ixgbe_hw *hw = &adapter->hw;
570 struct ixgbe_fc_info fc = hw->fc;
571
572 /* 82598 does no support link flow control with DCB enabled */
573 if ((hw->mac.type == ixgbe_mac_82598EB) &&
574 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
575 return -EINVAL;
576
577 /* some devices do not support autoneg of link flow control */
578 if ((pause->autoneg == AUTONEG_ENABLE) &&
579 !ixgbe_device_supports_autoneg_fc(hw))
580 return -EINVAL;
581
582 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
583
584 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
585 fc.requested_mode = ixgbe_fc_full;
586 else if (pause->rx_pause && !pause->tx_pause)
587 fc.requested_mode = ixgbe_fc_rx_pause;
588 else if (!pause->rx_pause && pause->tx_pause)
589 fc.requested_mode = ixgbe_fc_tx_pause;
590 else
591 fc.requested_mode = ixgbe_fc_none;
592
593 /* if the thing changed then we'll update and use new autoneg */
594 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
595 hw->fc = fc;
596 if (netif_running(netdev))
597 ixgbe_reinit_locked(adapter);
598 else
599 ixgbe_reset(adapter);
600 }
601
602 return 0;
603}
604
605static u32 ixgbe_get_msglevel(struct net_device *netdev)
606{
607 struct ixgbe_adapter *adapter = netdev_priv(netdev);
608 return adapter->msg_enable;
609}
610
611static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
612{
613 struct ixgbe_adapter *adapter = netdev_priv(netdev);
614 adapter->msg_enable = data;
615}
616
617static int ixgbe_get_regs_len(struct net_device *netdev)
618{
619#define IXGBE_REGS_LEN 1145
620 return IXGBE_REGS_LEN * sizeof(u32);
621}
622
623#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
624
625static void ixgbe_get_regs(struct net_device *netdev,
626 struct ethtool_regs *regs, void *p)
627{
628 struct ixgbe_adapter *adapter = netdev_priv(netdev);
629 struct ixgbe_hw *hw = &adapter->hw;
630 u32 *regs_buff = p;
631 u8 i;
632
633 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
634
635 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
636 hw->device_id;
637
638 /* General Registers */
639 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
640 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
641 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
642 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
643 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
644 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
645 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
646 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
647
648 /* NVM Register */
649 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
650 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
651 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
652 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
653 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
654 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
655 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
656 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
657 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
658 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
659
660 /* Interrupt */
661 /* don't read EICR because it can clear interrupt causes, instead
662 * read EICS which is a shadow but doesn't clear EICR */
663 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
664 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
665 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
666 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
667 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
668 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
669 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
670 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
671 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
672 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
673 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
674 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
675
676 /* Flow Control */
677 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
678 for (i = 0; i < 4; i++)
679 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
680 for (i = 0; i < 8; i++) {
681 switch (hw->mac.type) {
682 case ixgbe_mac_82598EB:
683 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
684 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
685 break;
686 case ixgbe_mac_82599EB:
687 case ixgbe_mac_X540:
688 case ixgbe_mac_X550:
689 case ixgbe_mac_X550EM_x:
690 case ixgbe_mac_x550em_a:
691 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
692 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
693 break;
694 default:
695 break;
696 }
697 }
698 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
699 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
700
701 /* Receive DMA */
702 for (i = 0; i < 64; i++)
703 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
704 for (i = 0; i < 64; i++)
705 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
706 for (i = 0; i < 64; i++)
707 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
708 for (i = 0; i < 64; i++)
709 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
710 for (i = 0; i < 64; i++)
711 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
712 for (i = 0; i < 64; i++)
713 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
714 for (i = 0; i < 16; i++)
715 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
716 for (i = 0; i < 16; i++)
717 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
718 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
719 for (i = 0; i < 8; i++)
720 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
721 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
722 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
723
724 /* Receive */
725 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
726 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
727 for (i = 0; i < 16; i++)
728 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
729 for (i = 0; i < 16; i++)
730 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
731 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
732 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
733 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
734 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
735 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
736 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
737 for (i = 0; i < 8; i++)
738 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
739 for (i = 0; i < 8; i++)
740 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
741 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
742
743 /* Transmit */
744 for (i = 0; i < 32; i++)
745 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
746 for (i = 0; i < 32; i++)
747 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
748 for (i = 0; i < 32; i++)
749 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
750 for (i = 0; i < 32; i++)
751 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
752 for (i = 0; i < 32; i++)
753 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
754 for (i = 0; i < 32; i++)
755 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
756 for (i = 0; i < 32; i++)
757 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
758 for (i = 0; i < 32; i++)
759 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
760 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
761 for (i = 0; i < 16; i++)
762 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
763 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
764 for (i = 0; i < 8; i++)
765 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
766 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
767
768 /* Wake Up */
769 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
770 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
771 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
772 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
773 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
774 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
775 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
776 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
777 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
778
779 /* DCB */
780 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
781 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
782
783 switch (hw->mac.type) {
784 case ixgbe_mac_82598EB:
785 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
786 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
787 for (i = 0; i < 8; i++)
788 regs_buff[833 + i] =
789 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
790 for (i = 0; i < 8; i++)
791 regs_buff[841 + i] =
792 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
793 for (i = 0; i < 8; i++)
794 regs_buff[849 + i] =
795 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
796 for (i = 0; i < 8; i++)
797 regs_buff[857 + i] =
798 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
799 break;
800 case ixgbe_mac_82599EB:
801 case ixgbe_mac_X540:
802 case ixgbe_mac_X550:
803 case ixgbe_mac_X550EM_x:
804 case ixgbe_mac_x550em_a:
805 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
806 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
807 for (i = 0; i < 8; i++)
808 regs_buff[833 + i] =
809 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
810 for (i = 0; i < 8; i++)
811 regs_buff[841 + i] =
812 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
813 for (i = 0; i < 8; i++)
814 regs_buff[849 + i] =
815 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
816 for (i = 0; i < 8; i++)
817 regs_buff[857 + i] =
818 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
819 break;
820 default:
821 break;
822 }
823
824 for (i = 0; i < 8; i++)
825 regs_buff[865 + i] =
826 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
827 for (i = 0; i < 8; i++)
828 regs_buff[873 + i] =
829 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
830
831 /* Statistics */
832 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
833 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
834 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
835 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
836 for (i = 0; i < 8; i++)
837 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
838 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
839 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
840 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
841 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
842 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
843 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
844 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
845 for (i = 0; i < 8; i++)
846 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
847 for (i = 0; i < 8; i++)
848 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
849 for (i = 0; i < 8; i++)
850 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
851 for (i = 0; i < 8; i++)
852 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
853 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
854 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
855 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
856 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
857 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
858 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
859 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
860 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
861 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
862 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
863 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
864 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
865 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
866 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
867 for (i = 0; i < 8; i++)
868 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
869 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
870 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
871 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
872 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
873 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
874 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
875 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
876 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
877 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
878 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
879 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
880 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
881 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
882 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
883 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
884 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
885 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
886 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
887 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
888 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
889 for (i = 0; i < 16; i++)
890 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
891 for (i = 0; i < 16; i++)
892 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
893 for (i = 0; i < 16; i++)
894 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
895 for (i = 0; i < 16; i++)
896 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
897
898 /* MAC */
899 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
900 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
901 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
902 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
903 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
904 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
905 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
906 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
907 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
908 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
909 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
910 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
911 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
912 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
913 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
914 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
915 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
916 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
917 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
918 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
919 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
920 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
921 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
922 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
923 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
924 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
925 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
926 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
927 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
928 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
929 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
930 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
931 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
932
933 /* Diagnostic */
934 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
935 for (i = 0; i < 8; i++)
936 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
937 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
938 for (i = 0; i < 4; i++)
939 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
940 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
941 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
942 for (i = 0; i < 8; i++)
943 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
944 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
945 for (i = 0; i < 4; i++)
946 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
947 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
948 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
949 for (i = 0; i < 4; i++)
950 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
951 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
952 for (i = 0; i < 4; i++)
953 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
954 for (i = 0; i < 8; i++)
955 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
956 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
957 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
958 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
959 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
960 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
961 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
962 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
963 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
964 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
965
966 /* 82599 X540 specific registers */
967 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
968
969 /* 82599 X540 specific DCB registers */
970 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
971 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
972 for (i = 0; i < 4; i++)
973 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
974 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
975 /* same as RTTQCNRM */
976 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
977 /* same as RTTQCNRR */
978
979 /* X540 specific DCB registers */
980 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
981 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
982
983 /* Security config registers */
984 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
985 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
986 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF);
987 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
988 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
989 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
990}
991
992static int ixgbe_get_eeprom_len(struct net_device *netdev)
993{
994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
995 return adapter->hw.eeprom.word_size * 2;
996}
997
998static int ixgbe_get_eeprom(struct net_device *netdev,
999 struct ethtool_eeprom *eeprom, u8 *bytes)
1000{
1001 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1002 struct ixgbe_hw *hw = &adapter->hw;
1003 u16 *eeprom_buff;
1004 int first_word, last_word, eeprom_len;
1005 int ret_val = 0;
1006 u16 i;
1007
1008 if (eeprom->len == 0)
1009 return -EINVAL;
1010
1011 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1012
1013 first_word = eeprom->offset >> 1;
1014 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1015 eeprom_len = last_word - first_word + 1;
1016
1017 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL);
1018 if (!eeprom_buff)
1019 return -ENOMEM;
1020
1021 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
1022 eeprom_buff);
1023
1024 /* Device's eeprom is always little-endian, word addressable */
1025 for (i = 0; i < eeprom_len; i++)
1026 le16_to_cpus(&eeprom_buff[i]);
1027
1028 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
1029 kfree(eeprom_buff);
1030
1031 return ret_val;
1032}
1033
1034static int ixgbe_set_eeprom(struct net_device *netdev,
1035 struct ethtool_eeprom *eeprom, u8 *bytes)
1036{
1037 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1038 struct ixgbe_hw *hw = &adapter->hw;
1039 u16 *eeprom_buff;
1040 void *ptr;
1041 int max_len, first_word, last_word, ret_val = 0;
1042 u16 i;
1043
1044 if (eeprom->len == 0)
1045 return -EINVAL;
1046
1047 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1048 return -EINVAL;
1049
1050 max_len = hw->eeprom.word_size * 2;
1051
1052 first_word = eeprom->offset >> 1;
1053 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1054 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1055 if (!eeprom_buff)
1056 return -ENOMEM;
1057
1058 ptr = eeprom_buff;
1059
1060 if (eeprom->offset & 1) {
1061 /*
1062 * need read/modify/write of first changed EEPROM word
1063 * only the second byte of the word is being modified
1064 */
1065 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
1066 if (ret_val)
1067 goto err;
1068
1069 ptr++;
1070 }
1071 if ((eeprom->offset + eeprom->len) & 1) {
1072 /*
1073 * need read/modify/write of last changed EEPROM word
1074 * only the first byte of the word is being modified
1075 */
1076 ret_val = hw->eeprom.ops.read(hw, last_word,
1077 &eeprom_buff[last_word - first_word]);
1078 if (ret_val)
1079 goto err;
1080 }
1081
1082 /* Device's eeprom is always little-endian, word addressable */
1083 for (i = 0; i < last_word - first_word + 1; i++)
1084 le16_to_cpus(&eeprom_buff[i]);
1085
1086 memcpy(ptr, bytes, eeprom->len);
1087
1088 for (i = 0; i < last_word - first_word + 1; i++)
1089 cpu_to_le16s(&eeprom_buff[i]);
1090
1091 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
1092 last_word - first_word + 1,
1093 eeprom_buff);
1094
1095 /* Update the checksum */
1096 if (ret_val == 0)
1097 hw->eeprom.ops.update_checksum(hw);
1098
1099err:
1100 kfree(eeprom_buff);
1101 return ret_val;
1102}
1103
1104static void ixgbe_get_drvinfo(struct net_device *netdev,
1105 struct ethtool_drvinfo *drvinfo)
1106{
1107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1108
1109 strscpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
1110
1111 strscpy(drvinfo->fw_version, adapter->eeprom_id,
1112 sizeof(drvinfo->fw_version));
1113
1114 strscpy(drvinfo->bus_info, pci_name(adapter->pdev),
1115 sizeof(drvinfo->bus_info));
1116
1117 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN;
1118}
1119
1120static u32 ixgbe_get_max_rxd(struct ixgbe_adapter *adapter)
1121{
1122 switch (adapter->hw.mac.type) {
1123 case ixgbe_mac_82598EB:
1124 return IXGBE_MAX_RXD_82598;
1125 case ixgbe_mac_82599EB:
1126 return IXGBE_MAX_RXD_82599;
1127 case ixgbe_mac_X540:
1128 return IXGBE_MAX_RXD_X540;
1129 case ixgbe_mac_X550:
1130 case ixgbe_mac_X550EM_x:
1131 case ixgbe_mac_x550em_a:
1132 return IXGBE_MAX_RXD_X550;
1133 default:
1134 return IXGBE_MAX_RXD_82598;
1135 }
1136}
1137
1138static u32 ixgbe_get_max_txd(struct ixgbe_adapter *adapter)
1139{
1140 switch (adapter->hw.mac.type) {
1141 case ixgbe_mac_82598EB:
1142 return IXGBE_MAX_TXD_82598;
1143 case ixgbe_mac_82599EB:
1144 return IXGBE_MAX_TXD_82599;
1145 case ixgbe_mac_X540:
1146 return IXGBE_MAX_TXD_X540;
1147 case ixgbe_mac_X550:
1148 case ixgbe_mac_X550EM_x:
1149 case ixgbe_mac_x550em_a:
1150 return IXGBE_MAX_TXD_X550;
1151 default:
1152 return IXGBE_MAX_TXD_82598;
1153 }
1154}
1155
1156static void ixgbe_get_ringparam(struct net_device *netdev,
1157 struct ethtool_ringparam *ring,
1158 struct kernel_ethtool_ringparam *kernel_ring,
1159 struct netlink_ext_ack *extack)
1160{
1161 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1162 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1163 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1164
1165 ring->rx_max_pending = ixgbe_get_max_rxd(adapter);
1166 ring->tx_max_pending = ixgbe_get_max_txd(adapter);
1167 ring->rx_pending = rx_ring->count;
1168 ring->tx_pending = tx_ring->count;
1169}
1170
1171static int ixgbe_set_ringparam(struct net_device *netdev,
1172 struct ethtool_ringparam *ring,
1173 struct kernel_ethtool_ringparam *kernel_ring,
1174 struct netlink_ext_ack *extack)
1175{
1176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1177 struct ixgbe_ring *temp_ring;
1178 int i, j, err = 0;
1179 u32 new_rx_count, new_tx_count;
1180
1181 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1182 return -EINVAL;
1183
1184 new_tx_count = clamp_t(u32, ring->tx_pending,
1185 IXGBE_MIN_TXD, ixgbe_get_max_txd(adapter));
1186 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1187
1188 new_rx_count = clamp_t(u32, ring->rx_pending,
1189 IXGBE_MIN_RXD, ixgbe_get_max_rxd(adapter));
1190 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1191
1192 if ((new_tx_count == adapter->tx_ring_count) &&
1193 (new_rx_count == adapter->rx_ring_count)) {
1194 /* nothing to do */
1195 return 0;
1196 }
1197
1198 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1199 usleep_range(1000, 2000);
1200
1201 if (!netif_running(adapter->netdev)) {
1202 for (i = 0; i < adapter->num_tx_queues; i++)
1203 adapter->tx_ring[i]->count = new_tx_count;
1204 for (i = 0; i < adapter->num_xdp_queues; i++)
1205 adapter->xdp_ring[i]->count = new_tx_count;
1206 for (i = 0; i < adapter->num_rx_queues; i++)
1207 adapter->rx_ring[i]->count = new_rx_count;
1208 adapter->tx_ring_count = new_tx_count;
1209 adapter->xdp_ring_count = new_tx_count;
1210 adapter->rx_ring_count = new_rx_count;
1211 goto clear_reset;
1212 }
1213
1214 /* allocate temporary buffer to store rings in */
1215 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues,
1216 adapter->num_rx_queues);
1217 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring)));
1218
1219 if (!temp_ring) {
1220 err = -ENOMEM;
1221 goto clear_reset;
1222 }
1223
1224 ixgbe_down(adapter);
1225
1226 /*
1227 * Setup new Tx resources and free the old Tx resources in that order.
1228 * We can then assign the new resources to the rings via a memcpy.
1229 * The advantage to this approach is that we are guaranteed to still
1230 * have resources even in the case of an allocation failure.
1231 */
1232 if (new_tx_count != adapter->tx_ring_count) {
1233 for (i = 0; i < adapter->num_tx_queues; i++) {
1234 memcpy(&temp_ring[i], adapter->tx_ring[i],
1235 sizeof(struct ixgbe_ring));
1236
1237 temp_ring[i].count = new_tx_count;
1238 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1239 if (err) {
1240 while (i) {
1241 i--;
1242 ixgbe_free_tx_resources(&temp_ring[i]);
1243 }
1244 goto err_setup;
1245 }
1246 }
1247
1248 for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1249 memcpy(&temp_ring[i], adapter->xdp_ring[j],
1250 sizeof(struct ixgbe_ring));
1251
1252 temp_ring[i].count = new_tx_count;
1253 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1254 if (err) {
1255 while (i) {
1256 i--;
1257 ixgbe_free_tx_resources(&temp_ring[i]);
1258 }
1259 goto err_setup;
1260 }
1261 }
1262
1263 for (i = 0; i < adapter->num_tx_queues; i++) {
1264 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1265
1266 memcpy(adapter->tx_ring[i], &temp_ring[i],
1267 sizeof(struct ixgbe_ring));
1268 }
1269 for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1270 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
1271
1272 memcpy(adapter->xdp_ring[j], &temp_ring[i],
1273 sizeof(struct ixgbe_ring));
1274 }
1275
1276 adapter->tx_ring_count = new_tx_count;
1277 }
1278
1279 /* Repeat the process for the Rx rings if needed */
1280 if (new_rx_count != adapter->rx_ring_count) {
1281 for (i = 0; i < adapter->num_rx_queues; i++) {
1282 memcpy(&temp_ring[i], adapter->rx_ring[i],
1283 sizeof(struct ixgbe_ring));
1284
1285 /* Clear copied XDP RX-queue info */
1286 memset(&temp_ring[i].xdp_rxq, 0,
1287 sizeof(temp_ring[i].xdp_rxq));
1288
1289 temp_ring[i].count = new_rx_count;
1290 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]);
1291 if (err) {
1292 while (i) {
1293 i--;
1294 ixgbe_free_rx_resources(&temp_ring[i]);
1295 }
1296 goto err_setup;
1297 }
1298
1299 }
1300
1301 for (i = 0; i < adapter->num_rx_queues; i++) {
1302 ixgbe_free_rx_resources(adapter->rx_ring[i]);
1303
1304 memcpy(adapter->rx_ring[i], &temp_ring[i],
1305 sizeof(struct ixgbe_ring));
1306 }
1307
1308 adapter->rx_ring_count = new_rx_count;
1309 }
1310
1311err_setup:
1312 ixgbe_up(adapter);
1313 vfree(temp_ring);
1314clear_reset:
1315 clear_bit(__IXGBE_RESETTING, &adapter->state);
1316 return err;
1317}
1318
1319static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1320{
1321 switch (sset) {
1322 case ETH_SS_TEST:
1323 return IXGBE_TEST_LEN;
1324 case ETH_SS_STATS:
1325 return IXGBE_STATS_LEN;
1326 case ETH_SS_PRIV_FLAGS:
1327 return IXGBE_PRIV_FLAGS_STR_LEN;
1328 default:
1329 return -EOPNOTSUPP;
1330 }
1331}
1332
1333static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1334 struct ethtool_stats *stats, u64 *data)
1335{
1336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1337 struct rtnl_link_stats64 temp;
1338 const struct rtnl_link_stats64 *net_stats;
1339 unsigned int start;
1340 struct ixgbe_ring *ring;
1341 int i, j;
1342 char *p = NULL;
1343
1344 ixgbe_update_stats(adapter);
1345 net_stats = dev_get_stats(netdev, &temp);
1346 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1347 switch (ixgbe_gstrings_stats[i].type) {
1348 case NETDEV_STATS:
1349 p = (char *) net_stats +
1350 ixgbe_gstrings_stats[i].stat_offset;
1351 break;
1352 case IXGBE_STATS:
1353 p = (char *) adapter +
1354 ixgbe_gstrings_stats[i].stat_offset;
1355 break;
1356 default:
1357 data[i] = 0;
1358 continue;
1359 }
1360
1361 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1362 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1363 }
1364 for (j = 0; j < netdev->num_tx_queues; j++) {
1365 ring = adapter->tx_ring[j];
1366 if (!ring) {
1367 data[i] = 0;
1368 data[i+1] = 0;
1369 i += 2;
1370 continue;
1371 }
1372
1373 do {
1374 start = u64_stats_fetch_begin(&ring->syncp);
1375 data[i] = ring->stats.packets;
1376 data[i+1] = ring->stats.bytes;
1377 } while (u64_stats_fetch_retry(&ring->syncp, start));
1378 i += 2;
1379 }
1380 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1381 ring = adapter->rx_ring[j];
1382 if (!ring) {
1383 data[i] = 0;
1384 data[i+1] = 0;
1385 i += 2;
1386 continue;
1387 }
1388
1389 do {
1390 start = u64_stats_fetch_begin(&ring->syncp);
1391 data[i] = ring->stats.packets;
1392 data[i+1] = ring->stats.bytes;
1393 } while (u64_stats_fetch_retry(&ring->syncp, start));
1394 i += 2;
1395 }
1396
1397 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1398 data[i++] = adapter->stats.pxontxc[j];
1399 data[i++] = adapter->stats.pxofftxc[j];
1400 }
1401 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1402 data[i++] = adapter->stats.pxonrxc[j];
1403 data[i++] = adapter->stats.pxoffrxc[j];
1404 }
1405}
1406
1407static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1408 u8 *data)
1409{
1410 unsigned int i;
1411 u8 *p = data;
1412
1413 switch (stringset) {
1414 case ETH_SS_TEST:
1415 for (i = 0; i < IXGBE_TEST_LEN; i++)
1416 ethtool_puts(&p, ixgbe_gstrings_test[i]);
1417 break;
1418 case ETH_SS_STATS:
1419 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++)
1420 ethtool_puts(&p, ixgbe_gstrings_stats[i].stat_string);
1421 for (i = 0; i < netdev->num_tx_queues; i++) {
1422 ethtool_sprintf(&p, "tx_queue_%u_packets", i);
1423 ethtool_sprintf(&p, "tx_queue_%u_bytes", i);
1424 }
1425 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1426 ethtool_sprintf(&p, "rx_queue_%u_packets", i);
1427 ethtool_sprintf(&p, "rx_queue_%u_bytes", i);
1428 }
1429 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1430 ethtool_sprintf(&p, "tx_pb_%u_pxon", i);
1431 ethtool_sprintf(&p, "tx_pb_%u_pxoff", i);
1432 }
1433 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1434 ethtool_sprintf(&p, "rx_pb_%u_pxon", i);
1435 ethtool_sprintf(&p, "rx_pb_%u_pxoff", i);
1436 }
1437 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1438 break;
1439 case ETH_SS_PRIV_FLAGS:
1440 memcpy(data, ixgbe_priv_flags_strings,
1441 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
1442 }
1443}
1444
1445static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1446{
1447 struct ixgbe_hw *hw = &adapter->hw;
1448 bool link_up;
1449 u32 link_speed = 0;
1450
1451 if (ixgbe_removed(hw->hw_addr)) {
1452 *data = 1;
1453 return 1;
1454 }
1455 *data = 0;
1456
1457 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1458 if (link_up)
1459 return *data;
1460 else
1461 *data = 1;
1462 return *data;
1463}
1464
1465/* ethtool register test data */
1466struct ixgbe_reg_test {
1467 u16 reg;
1468 u8 array_len;
1469 u8 test_type;
1470 u32 mask;
1471 u32 write;
1472};
1473
1474/* In the hardware, registers are laid out either singly, in arrays
1475 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1476 * most tests take place on arrays or single registers (handled
1477 * as a single-element array) and special-case the tables.
1478 * Table tests are always pattern tests.
1479 *
1480 * We also make provision for some required setup steps by specifying
1481 * registers to be written without any read-back testing.
1482 */
1483
1484#define PATTERN_TEST 1
1485#define SET_READ_TEST 2
1486#define WRITE_NO_TEST 3
1487#define TABLE32_TEST 4
1488#define TABLE64_TEST_LO 5
1489#define TABLE64_TEST_HI 6
1490
1491/* default 82599 register test */
1492static const struct ixgbe_reg_test reg_test_82599[] = {
1493 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1494 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1495 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1496 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1497 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1498 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1499 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1500 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1501 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1502 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1503 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1504 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1505 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1506 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1507 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1508 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1509 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1510 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1511 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1512 { .reg = 0 }
1513};
1514
1515/* default 82598 register test */
1516static const struct ixgbe_reg_test reg_test_82598[] = {
1517 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1518 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1519 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1520 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1521 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1522 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1523 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1524 /* Enable all four RX queues before testing. */
1525 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1526 /* RDH is read-only for 82598, only test RDT. */
1527 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1528 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1529 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1530 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1531 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1532 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1533 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1534 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1535 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1536 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1537 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1538 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1539 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1540 { .reg = 0 }
1541};
1542
1543static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1544 u32 mask, u32 write)
1545{
1546 u32 pat, val, before;
1547 static const u32 test_pattern[] = {
1548 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1549
1550 if (ixgbe_removed(adapter->hw.hw_addr)) {
1551 *data = 1;
1552 return true;
1553 }
1554 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1555 before = ixgbe_read_reg(&adapter->hw, reg);
1556 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1557 val = ixgbe_read_reg(&adapter->hw, reg);
1558 if (val != (test_pattern[pat] & write & mask)) {
1559 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1560 reg, val, (test_pattern[pat] & write & mask));
1561 *data = reg;
1562 ixgbe_write_reg(&adapter->hw, reg, before);
1563 return true;
1564 }
1565 ixgbe_write_reg(&adapter->hw, reg, before);
1566 }
1567 return false;
1568}
1569
1570static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1571 u32 mask, u32 write)
1572{
1573 u32 val, before;
1574
1575 if (ixgbe_removed(adapter->hw.hw_addr)) {
1576 *data = 1;
1577 return true;
1578 }
1579 before = ixgbe_read_reg(&adapter->hw, reg);
1580 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1581 val = ixgbe_read_reg(&adapter->hw, reg);
1582 if ((write & mask) != (val & mask)) {
1583 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1584 reg, (val & mask), (write & mask));
1585 *data = reg;
1586 ixgbe_write_reg(&adapter->hw, reg, before);
1587 return true;
1588 }
1589 ixgbe_write_reg(&adapter->hw, reg, before);
1590 return false;
1591}
1592
1593static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1594{
1595 const struct ixgbe_reg_test *test;
1596 u32 value, before, after;
1597 u32 i, toggle;
1598
1599 if (ixgbe_removed(adapter->hw.hw_addr)) {
1600 e_err(drv, "Adapter removed - register test blocked\n");
1601 *data = 1;
1602 return 1;
1603 }
1604 switch (adapter->hw.mac.type) {
1605 case ixgbe_mac_82598EB:
1606 toggle = 0x7FFFF3FF;
1607 test = reg_test_82598;
1608 break;
1609 case ixgbe_mac_82599EB:
1610 case ixgbe_mac_X540:
1611 case ixgbe_mac_X550:
1612 case ixgbe_mac_X550EM_x:
1613 case ixgbe_mac_x550em_a:
1614 toggle = 0x7FFFF30F;
1615 test = reg_test_82599;
1616 break;
1617 default:
1618 *data = 1;
1619 return 1;
1620 }
1621
1622 /*
1623 * Because the status register is such a special case,
1624 * we handle it separately from the rest of the register
1625 * tests. Some bits are read-only, some toggle, and some
1626 * are writeable on newer MACs.
1627 */
1628 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1629 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1630 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1631 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1632 if (value != after) {
1633 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1634 after, value);
1635 *data = 1;
1636 return 1;
1637 }
1638 /* restore previous status */
1639 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1640
1641 /*
1642 * Perform the remainder of the register test, looping through
1643 * the test table until we either fail or reach the null entry.
1644 */
1645 while (test->reg) {
1646 for (i = 0; i < test->array_len; i++) {
1647 bool b = false;
1648
1649 switch (test->test_type) {
1650 case PATTERN_TEST:
1651 b = reg_pattern_test(adapter, data,
1652 test->reg + (i * 0x40),
1653 test->mask,
1654 test->write);
1655 break;
1656 case SET_READ_TEST:
1657 b = reg_set_and_check(adapter, data,
1658 test->reg + (i * 0x40),
1659 test->mask,
1660 test->write);
1661 break;
1662 case WRITE_NO_TEST:
1663 ixgbe_write_reg(&adapter->hw,
1664 test->reg + (i * 0x40),
1665 test->write);
1666 break;
1667 case TABLE32_TEST:
1668 b = reg_pattern_test(adapter, data,
1669 test->reg + (i * 4),
1670 test->mask,
1671 test->write);
1672 break;
1673 case TABLE64_TEST_LO:
1674 b = reg_pattern_test(adapter, data,
1675 test->reg + (i * 8),
1676 test->mask,
1677 test->write);
1678 break;
1679 case TABLE64_TEST_HI:
1680 b = reg_pattern_test(adapter, data,
1681 (test->reg + 4) + (i * 8),
1682 test->mask,
1683 test->write);
1684 break;
1685 }
1686 if (b)
1687 return 1;
1688 }
1689 test++;
1690 }
1691
1692 *data = 0;
1693 return 0;
1694}
1695
1696static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1697{
1698 struct ixgbe_hw *hw = &adapter->hw;
1699 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1700 *data = 1;
1701 else
1702 *data = 0;
1703 return *data;
1704}
1705
1706static irqreturn_t ixgbe_test_intr(int irq, void *data)
1707{
1708 struct net_device *netdev = (struct net_device *) data;
1709 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1710
1711 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1712
1713 return IRQ_HANDLED;
1714}
1715
1716static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1717{
1718 struct net_device *netdev = adapter->netdev;
1719 u32 mask, i = 0, shared_int = true;
1720 u32 irq = adapter->pdev->irq;
1721
1722 *data = 0;
1723
1724 /* Hook up test interrupt handler just for this test */
1725 if (adapter->msix_entries) {
1726 /* NOTE: we don't test MSI-X interrupts here, yet */
1727 return 0;
1728 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1729 shared_int = false;
1730 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1731 netdev)) {
1732 *data = 1;
1733 return -1;
1734 }
1735 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1736 netdev->name, netdev)) {
1737 shared_int = false;
1738 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1739 netdev->name, netdev)) {
1740 *data = 1;
1741 return -1;
1742 }
1743 e_info(hw, "testing %s interrupt\n", shared_int ?
1744 "shared" : "unshared");
1745
1746 /* Disable all the interrupts */
1747 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1748 IXGBE_WRITE_FLUSH(&adapter->hw);
1749 usleep_range(10000, 20000);
1750
1751 /* Test each interrupt */
1752 for (; i < 10; i++) {
1753 /* Interrupt to test */
1754 mask = BIT(i);
1755
1756 if (!shared_int) {
1757 /*
1758 * Disable the interrupts to be reported in
1759 * the cause register and then force the same
1760 * interrupt and see if one gets posted. If
1761 * an interrupt was posted to the bus, the
1762 * test failed.
1763 */
1764 adapter->test_icr = 0;
1765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1766 ~mask & 0x00007FFF);
1767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1768 ~mask & 0x00007FFF);
1769 IXGBE_WRITE_FLUSH(&adapter->hw);
1770 usleep_range(10000, 20000);
1771
1772 if (adapter->test_icr & mask) {
1773 *data = 3;
1774 break;
1775 }
1776 }
1777
1778 /*
1779 * Enable the interrupt to be reported in the cause
1780 * register and then force the same interrupt and see
1781 * if one gets posted. If an interrupt was not posted
1782 * to the bus, the test failed.
1783 */
1784 adapter->test_icr = 0;
1785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1787 IXGBE_WRITE_FLUSH(&adapter->hw);
1788 usleep_range(10000, 20000);
1789
1790 if (!(adapter->test_icr & mask)) {
1791 *data = 4;
1792 break;
1793 }
1794
1795 if (!shared_int) {
1796 /*
1797 * Disable the other interrupts to be reported in
1798 * the cause register and then force the other
1799 * interrupts and see if any get posted. If
1800 * an interrupt was posted to the bus, the
1801 * test failed.
1802 */
1803 adapter->test_icr = 0;
1804 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1805 ~mask & 0x00007FFF);
1806 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1807 ~mask & 0x00007FFF);
1808 IXGBE_WRITE_FLUSH(&adapter->hw);
1809 usleep_range(10000, 20000);
1810
1811 if (adapter->test_icr) {
1812 *data = 5;
1813 break;
1814 }
1815 }
1816 }
1817
1818 /* Disable all the interrupts */
1819 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1820 IXGBE_WRITE_FLUSH(&adapter->hw);
1821 usleep_range(10000, 20000);
1822
1823 /* Unhook test interrupt handler */
1824 free_irq(irq, netdev);
1825
1826 return *data;
1827}
1828
1829static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1830{
1831 /* Shut down the DMA engines now so they can be reinitialized later,
1832 * since the test rings and normally used rings should overlap on
1833 * queue 0 we can just use the standard disable Rx/Tx calls and they
1834 * will take care of disabling the test rings for us.
1835 */
1836
1837 /* first Rx */
1838 ixgbe_disable_rx(adapter);
1839
1840 /* now Tx */
1841 ixgbe_disable_tx(adapter);
1842
1843 ixgbe_reset(adapter);
1844
1845 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1846 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1847}
1848
1849static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1850{
1851 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1852 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1853 struct ixgbe_hw *hw = &adapter->hw;
1854 u32 rctl, reg_data;
1855 int ret_val;
1856 int err;
1857
1858 /* Setup Tx descriptor ring and Tx buffers */
1859 tx_ring->count = IXGBE_DEFAULT_TXD;
1860 tx_ring->queue_index = 0;
1861 tx_ring->dev = &adapter->pdev->dev;
1862 tx_ring->netdev = adapter->netdev;
1863 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1864
1865 err = ixgbe_setup_tx_resources(tx_ring);
1866 if (err)
1867 return 1;
1868
1869 switch (adapter->hw.mac.type) {
1870 case ixgbe_mac_82599EB:
1871 case ixgbe_mac_X540:
1872 case ixgbe_mac_X550:
1873 case ixgbe_mac_X550EM_x:
1874 case ixgbe_mac_x550em_a:
1875 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1876 reg_data |= IXGBE_DMATXCTL_TE;
1877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1878 break;
1879 default:
1880 break;
1881 }
1882
1883 ixgbe_configure_tx_ring(adapter, tx_ring);
1884
1885 /* Setup Rx Descriptor ring and Rx buffers */
1886 rx_ring->count = IXGBE_DEFAULT_RXD;
1887 rx_ring->queue_index = 0;
1888 rx_ring->dev = &adapter->pdev->dev;
1889 rx_ring->netdev = adapter->netdev;
1890 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1891
1892 err = ixgbe_setup_rx_resources(adapter, rx_ring);
1893 if (err) {
1894 ret_val = 4;
1895 goto err_nomem;
1896 }
1897
1898 hw->mac.ops.disable_rx(hw);
1899
1900 ixgbe_configure_rx_ring(adapter, rx_ring);
1901
1902 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1903 rctl |= IXGBE_RXCTRL_DMBYPS;
1904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1905
1906 hw->mac.ops.enable_rx(hw);
1907
1908 return 0;
1909
1910err_nomem:
1911 ixgbe_free_desc_rings(adapter);
1912 return ret_val;
1913}
1914
1915static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1916{
1917 struct ixgbe_hw *hw = &adapter->hw;
1918 u32 reg_data;
1919
1920
1921 /* Setup MAC loopback */
1922 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1923 reg_data |= IXGBE_HLREG0_LPBK;
1924 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1925
1926 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1927 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1928 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1929
1930 /* X540 and X550 needs to set the MACC.FLU bit to force link up */
1931 switch (adapter->hw.mac.type) {
1932 case ixgbe_mac_X540:
1933 case ixgbe_mac_X550:
1934 case ixgbe_mac_X550EM_x:
1935 case ixgbe_mac_x550em_a:
1936 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1937 reg_data |= IXGBE_MACC_FLU;
1938 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1939 break;
1940 default:
1941 if (hw->mac.orig_autoc) {
1942 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1943 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1944 } else {
1945 return 10;
1946 }
1947 }
1948 IXGBE_WRITE_FLUSH(hw);
1949 usleep_range(10000, 20000);
1950
1951 /* Disable Atlas Tx lanes; re-enabled in reset path */
1952 if (hw->mac.type == ixgbe_mac_82598EB) {
1953 u8 atlas;
1954
1955 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1956 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1957 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1958
1959 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1960 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1961 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1962
1963 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1964 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1965 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1966
1967 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1968 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1969 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1970 }
1971
1972 return 0;
1973}
1974
1975static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1976{
1977 u32 reg_data;
1978
1979 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1980 reg_data &= ~IXGBE_HLREG0_LPBK;
1981 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1982}
1983
1984static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1985 unsigned int frame_size)
1986{
1987 memset(skb->data, 0xFF, frame_size);
1988 frame_size >>= 1;
1989 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1990 skb->data[frame_size + 10] = 0xBE;
1991 skb->data[frame_size + 12] = 0xAF;
1992}
1993
1994static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1995 unsigned int frame_size)
1996{
1997 unsigned char *data;
1998
1999 frame_size >>= 1;
2000
2001 data = page_address(rx_buffer->page) + rx_buffer->page_offset;
2002
2003 return data[3] == 0xFF && data[frame_size + 10] == 0xBE &&
2004 data[frame_size + 12] == 0xAF;
2005}
2006
2007static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
2008 struct ixgbe_ring *tx_ring,
2009 unsigned int size)
2010{
2011 union ixgbe_adv_rx_desc *rx_desc;
2012 u16 rx_ntc, tx_ntc, count = 0;
2013
2014 /* initialize next to clean and descriptor values */
2015 rx_ntc = rx_ring->next_to_clean;
2016 tx_ntc = tx_ring->next_to_clean;
2017 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
2018
2019 while (tx_ntc != tx_ring->next_to_use) {
2020 union ixgbe_adv_tx_desc *tx_desc;
2021 struct ixgbe_tx_buffer *tx_buffer;
2022
2023 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc);
2024
2025 /* if DD is not set transmit has not completed */
2026 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
2027 return count;
2028
2029 /* unmap buffer on Tx side */
2030 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
2031
2032 /* Free all the Tx ring sk_buffs */
2033 dev_kfree_skb_any(tx_buffer->skb);
2034
2035 /* unmap skb header data */
2036 dma_unmap_single(tx_ring->dev,
2037 dma_unmap_addr(tx_buffer, dma),
2038 dma_unmap_len(tx_buffer, len),
2039 DMA_TO_DEVICE);
2040 dma_unmap_len_set(tx_buffer, len, 0);
2041
2042 /* increment Tx next to clean counter */
2043 tx_ntc++;
2044 if (tx_ntc == tx_ring->count)
2045 tx_ntc = 0;
2046 }
2047
2048 while (rx_desc->wb.upper.length) {
2049 struct ixgbe_rx_buffer *rx_buffer;
2050
2051 /* check Rx buffer */
2052 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
2053
2054 /* sync Rx buffer for CPU read */
2055 dma_sync_single_for_cpu(rx_ring->dev,
2056 rx_buffer->dma,
2057 ixgbe_rx_bufsz(rx_ring),
2058 DMA_FROM_DEVICE);
2059
2060 /* verify contents of skb */
2061 if (ixgbe_check_lbtest_frame(rx_buffer, size))
2062 count++;
2063 else
2064 break;
2065
2066 /* sync Rx buffer for device write */
2067 dma_sync_single_for_device(rx_ring->dev,
2068 rx_buffer->dma,
2069 ixgbe_rx_bufsz(rx_ring),
2070 DMA_FROM_DEVICE);
2071
2072 /* increment Rx next to clean counter */
2073 rx_ntc++;
2074 if (rx_ntc == rx_ring->count)
2075 rx_ntc = 0;
2076
2077 /* fetch next descriptor */
2078 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
2079 }
2080
2081 netdev_tx_reset_queue(txring_txq(tx_ring));
2082
2083 /* re-map buffers to ring, store next to clean values */
2084 ixgbe_alloc_rx_buffers(rx_ring, count);
2085 rx_ring->next_to_clean = rx_ntc;
2086 tx_ring->next_to_clean = tx_ntc;
2087
2088 return count;
2089}
2090
2091static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
2092{
2093 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
2094 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
2095 int i, j, lc, good_cnt, ret_val = 0;
2096 unsigned int size = 1024;
2097 netdev_tx_t tx_ret_val;
2098 struct sk_buff *skb;
2099 u32 flags_orig = adapter->flags;
2100
2101 /* DCB can modify the frames on Tx */
2102 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2103
2104 /* allocate test skb */
2105 skb = alloc_skb(size, GFP_KERNEL);
2106 if (!skb)
2107 return 11;
2108
2109 /* place data into test skb */
2110 ixgbe_create_lbtest_frame(skb, size);
2111 skb_put(skb, size);
2112
2113 /*
2114 * Calculate the loop count based on the largest descriptor ring
2115 * The idea is to wrap the largest ring a number of times using 64
2116 * send/receive pairs during each loop
2117 */
2118
2119 if (rx_ring->count <= tx_ring->count)
2120 lc = ((tx_ring->count / 64) * 2) + 1;
2121 else
2122 lc = ((rx_ring->count / 64) * 2) + 1;
2123
2124 for (j = 0; j <= lc; j++) {
2125 /* reset count of good packets */
2126 good_cnt = 0;
2127
2128 /* place 64 packets on the transmit queue*/
2129 for (i = 0; i < 64; i++) {
2130 skb_get(skb);
2131 tx_ret_val = ixgbe_xmit_frame_ring(skb,
2132 adapter,
2133 tx_ring);
2134 if (tx_ret_val == NETDEV_TX_OK)
2135 good_cnt++;
2136 }
2137
2138 if (good_cnt != 64) {
2139 ret_val = 12;
2140 break;
2141 }
2142
2143 /* allow 200 milliseconds for packets to go from Tx to Rx */
2144 msleep(200);
2145
2146 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
2147 if (good_cnt != 64) {
2148 ret_val = 13;
2149 break;
2150 }
2151 }
2152
2153 /* free the original skb */
2154 kfree_skb(skb);
2155 adapter->flags = flags_orig;
2156
2157 return ret_val;
2158}
2159
2160static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
2161{
2162 *data = ixgbe_setup_desc_rings(adapter);
2163 if (*data)
2164 goto out;
2165 *data = ixgbe_setup_loopback_test(adapter);
2166 if (*data)
2167 goto err_loopback;
2168 *data = ixgbe_run_loopback_test(adapter);
2169 ixgbe_loopback_cleanup(adapter);
2170
2171err_loopback:
2172 ixgbe_free_desc_rings(adapter);
2173out:
2174 return *data;
2175}
2176
2177static void ixgbe_diag_test(struct net_device *netdev,
2178 struct ethtool_test *eth_test, u64 *data)
2179{
2180 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2181 bool if_running = netif_running(netdev);
2182
2183 if (ixgbe_removed(adapter->hw.hw_addr)) {
2184 e_err(hw, "Adapter removed - test blocked\n");
2185 data[0] = 1;
2186 data[1] = 1;
2187 data[2] = 1;
2188 data[3] = 1;
2189 data[4] = 1;
2190 eth_test->flags |= ETH_TEST_FL_FAILED;
2191 return;
2192 }
2193 set_bit(__IXGBE_TESTING, &adapter->state);
2194 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2195 struct ixgbe_hw *hw = &adapter->hw;
2196
2197 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2198 int i;
2199 for (i = 0; i < adapter->num_vfs; i++) {
2200 if (adapter->vfinfo[i].clear_to_send) {
2201 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
2202 data[0] = 1;
2203 data[1] = 1;
2204 data[2] = 1;
2205 data[3] = 1;
2206 data[4] = 1;
2207 eth_test->flags |= ETH_TEST_FL_FAILED;
2208 clear_bit(__IXGBE_TESTING,
2209 &adapter->state);
2210 return;
2211 }
2212 }
2213 }
2214
2215 /* Offline tests */
2216 e_info(hw, "offline testing starting\n");
2217
2218 /* Link test performed before hardware reset so autoneg doesn't
2219 * interfere with test result
2220 */
2221 if (ixgbe_link_test(adapter, &data[4]))
2222 eth_test->flags |= ETH_TEST_FL_FAILED;
2223
2224 if (if_running)
2225 /* indicate we're in test mode */
2226 ixgbe_close(netdev);
2227 else
2228 ixgbe_reset(adapter);
2229
2230 e_info(hw, "register testing starting\n");
2231 if (ixgbe_reg_test(adapter, &data[0]))
2232 eth_test->flags |= ETH_TEST_FL_FAILED;
2233
2234 ixgbe_reset(adapter);
2235 e_info(hw, "eeprom testing starting\n");
2236 if (ixgbe_eeprom_test(adapter, &data[1]))
2237 eth_test->flags |= ETH_TEST_FL_FAILED;
2238
2239 ixgbe_reset(adapter);
2240 e_info(hw, "interrupt testing starting\n");
2241 if (ixgbe_intr_test(adapter, &data[2]))
2242 eth_test->flags |= ETH_TEST_FL_FAILED;
2243
2244 /* If SRIOV or VMDq is enabled then skip MAC
2245 * loopback diagnostic. */
2246 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2247 IXGBE_FLAG_VMDQ_ENABLED)) {
2248 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2249 data[3] = 0;
2250 goto skip_loopback;
2251 }
2252
2253 ixgbe_reset(adapter);
2254 e_info(hw, "loopback testing starting\n");
2255 if (ixgbe_loopback_test(adapter, &data[3]))
2256 eth_test->flags |= ETH_TEST_FL_FAILED;
2257
2258skip_loopback:
2259 ixgbe_reset(adapter);
2260
2261 /* clear testing bit and return adapter to previous state */
2262 clear_bit(__IXGBE_TESTING, &adapter->state);
2263 if (if_running)
2264 ixgbe_open(netdev);
2265 else if (hw->mac.ops.disable_tx_laser)
2266 hw->mac.ops.disable_tx_laser(hw);
2267 } else {
2268 e_info(hw, "online testing starting\n");
2269
2270 /* Online tests */
2271 if (ixgbe_link_test(adapter, &data[4]))
2272 eth_test->flags |= ETH_TEST_FL_FAILED;
2273
2274 /* Offline tests aren't run; pass by default */
2275 data[0] = 0;
2276 data[1] = 0;
2277 data[2] = 0;
2278 data[3] = 0;
2279
2280 clear_bit(__IXGBE_TESTING, &adapter->state);
2281 }
2282}
2283
2284static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2285 struct ethtool_wolinfo *wol)
2286{
2287 struct ixgbe_hw *hw = &adapter->hw;
2288 int retval = 0;
2289
2290 /* WOL not supported for all devices */
2291 if (!ixgbe_wol_supported(adapter, hw->device_id,
2292 hw->subsystem_device_id)) {
2293 retval = 1;
2294 wol->supported = 0;
2295 }
2296
2297 return retval;
2298}
2299
2300static void ixgbe_get_wol(struct net_device *netdev,
2301 struct ethtool_wolinfo *wol)
2302{
2303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2304
2305 wol->supported = WAKE_UCAST | WAKE_MCAST |
2306 WAKE_BCAST | WAKE_MAGIC;
2307 wol->wolopts = 0;
2308
2309 if (ixgbe_wol_exclusion(adapter, wol) ||
2310 !device_can_wakeup(&adapter->pdev->dev))
2311 return;
2312
2313 if (adapter->wol & IXGBE_WUFC_EX)
2314 wol->wolopts |= WAKE_UCAST;
2315 if (adapter->wol & IXGBE_WUFC_MC)
2316 wol->wolopts |= WAKE_MCAST;
2317 if (adapter->wol & IXGBE_WUFC_BC)
2318 wol->wolopts |= WAKE_BCAST;
2319 if (adapter->wol & IXGBE_WUFC_MAG)
2320 wol->wolopts |= WAKE_MAGIC;
2321}
2322
2323static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2324{
2325 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2326
2327 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE |
2328 WAKE_FILTER))
2329 return -EOPNOTSUPP;
2330
2331 if (ixgbe_wol_exclusion(adapter, wol))
2332 return wol->wolopts ? -EOPNOTSUPP : 0;
2333
2334 adapter->wol = 0;
2335
2336 if (wol->wolopts & WAKE_UCAST)
2337 adapter->wol |= IXGBE_WUFC_EX;
2338 if (wol->wolopts & WAKE_MCAST)
2339 adapter->wol |= IXGBE_WUFC_MC;
2340 if (wol->wolopts & WAKE_BCAST)
2341 adapter->wol |= IXGBE_WUFC_BC;
2342 if (wol->wolopts & WAKE_MAGIC)
2343 adapter->wol |= IXGBE_WUFC_MAG;
2344
2345 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2346
2347 return 0;
2348}
2349
2350static int ixgbe_nway_reset(struct net_device *netdev)
2351{
2352 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2353
2354 if (netif_running(netdev))
2355 ixgbe_reinit_locked(adapter);
2356
2357 return 0;
2358}
2359
2360static int ixgbe_set_phys_id(struct net_device *netdev,
2361 enum ethtool_phys_id_state state)
2362{
2363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2364 struct ixgbe_hw *hw = &adapter->hw;
2365
2366 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off)
2367 return -EOPNOTSUPP;
2368
2369 switch (state) {
2370 case ETHTOOL_ID_ACTIVE:
2371 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2372 return 2;
2373
2374 case ETHTOOL_ID_ON:
2375 hw->mac.ops.led_on(hw, hw->mac.led_link_act);
2376 break;
2377
2378 case ETHTOOL_ID_OFF:
2379 hw->mac.ops.led_off(hw, hw->mac.led_link_act);
2380 break;
2381
2382 case ETHTOOL_ID_INACTIVE:
2383 /* Restore LED settings */
2384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2385 break;
2386 }
2387
2388 return 0;
2389}
2390
2391static int ixgbe_get_coalesce(struct net_device *netdev,
2392 struct ethtool_coalesce *ec,
2393 struct kernel_ethtool_coalesce *kernel_coal,
2394 struct netlink_ext_ack *extack)
2395{
2396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2397
2398 /* only valid if in constant ITR mode */
2399 if (adapter->rx_itr_setting <= 1)
2400 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2401 else
2402 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2403
2404 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2405 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2406 return 0;
2407
2408 /* only valid if in constant ITR mode */
2409 if (adapter->tx_itr_setting <= 1)
2410 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2411 else
2412 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2413
2414 return 0;
2415}
2416
2417/*
2418 * this function must be called before setting the new value of
2419 * rx_itr_setting
2420 */
2421static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2422{
2423 struct net_device *netdev = adapter->netdev;
2424
2425 /* nothing to do if LRO or RSC are not enabled */
2426 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2427 !(netdev->features & NETIF_F_LRO))
2428 return false;
2429
2430 /* check the feature flag value and enable RSC if necessary */
2431 if (adapter->rx_itr_setting == 1 ||
2432 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2433 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2434 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2435 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2436 return true;
2437 }
2438 /* if interrupt rate is too high then disable RSC */
2439 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2440 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2441 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2442 return true;
2443 }
2444 return false;
2445}
2446
2447static int ixgbe_set_coalesce(struct net_device *netdev,
2448 struct ethtool_coalesce *ec,
2449 struct kernel_ethtool_coalesce *kernel_coal,
2450 struct netlink_ext_ack *extack)
2451{
2452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2453 struct ixgbe_q_vector *q_vector;
2454 int i;
2455 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2456 bool need_reset = false;
2457
2458 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2459 /* reject Tx specific changes in case of mixed RxTx vectors */
2460 if (ec->tx_coalesce_usecs)
2461 return -EINVAL;
2462 tx_itr_prev = adapter->rx_itr_setting;
2463 } else {
2464 tx_itr_prev = adapter->tx_itr_setting;
2465 }
2466
2467 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2468 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2469 return -EINVAL;
2470
2471 if (ec->rx_coalesce_usecs > 1)
2472 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2473 else
2474 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2475
2476 if (adapter->rx_itr_setting == 1)
2477 rx_itr_param = IXGBE_20K_ITR;
2478 else
2479 rx_itr_param = adapter->rx_itr_setting;
2480
2481 if (ec->tx_coalesce_usecs > 1)
2482 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2483 else
2484 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2485
2486 if (adapter->tx_itr_setting == 1)
2487 tx_itr_param = IXGBE_12K_ITR;
2488 else
2489 tx_itr_param = adapter->tx_itr_setting;
2490
2491 /* mixed Rx/Tx */
2492 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2493 adapter->tx_itr_setting = adapter->rx_itr_setting;
2494
2495 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2496 if ((adapter->tx_itr_setting != 1) &&
2497 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2498 if ((tx_itr_prev == 1) ||
2499 (tx_itr_prev >= IXGBE_100K_ITR))
2500 need_reset = true;
2501 } else {
2502 if ((tx_itr_prev != 1) &&
2503 (tx_itr_prev < IXGBE_100K_ITR))
2504 need_reset = true;
2505 }
2506
2507 /* check the old value and enable RSC if necessary */
2508 need_reset |= ixgbe_update_rsc(adapter);
2509
2510 for (i = 0; i < adapter->num_q_vectors; i++) {
2511 q_vector = adapter->q_vector[i];
2512 if (q_vector->tx.count && !q_vector->rx.count)
2513 /* tx only */
2514 q_vector->itr = tx_itr_param;
2515 else
2516 /* rx only or mixed */
2517 q_vector->itr = rx_itr_param;
2518 ixgbe_write_eitr(q_vector);
2519 }
2520
2521 /*
2522 * do reset here at the end to make sure EITR==0 case is handled
2523 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2524 * also locks in RSC enable/disable which requires reset
2525 */
2526 if (need_reset)
2527 ixgbe_do_reset(netdev);
2528
2529 return 0;
2530}
2531
2532static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2533 struct ethtool_rxnfc *cmd)
2534{
2535 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2536 struct ethtool_rx_flow_spec *fsp =
2537 (struct ethtool_rx_flow_spec *)&cmd->fs;
2538 struct hlist_node *node2;
2539 struct ixgbe_fdir_filter *rule = NULL;
2540
2541 /* report total rule count */
2542 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2543
2544 hlist_for_each_entry_safe(rule, node2,
2545 &adapter->fdir_filter_list, fdir_node) {
2546 if (fsp->location <= rule->sw_idx)
2547 break;
2548 }
2549
2550 if (!rule || fsp->location != rule->sw_idx)
2551 return -EINVAL;
2552
2553 /* fill out the flow spec entry */
2554
2555 /* set flow type field */
2556 switch (rule->filter.formatted.flow_type) {
2557 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2558 fsp->flow_type = TCP_V4_FLOW;
2559 break;
2560 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2561 fsp->flow_type = UDP_V4_FLOW;
2562 break;
2563 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2564 fsp->flow_type = SCTP_V4_FLOW;
2565 break;
2566 case IXGBE_ATR_FLOW_TYPE_IPV4:
2567 fsp->flow_type = IP_USER_FLOW;
2568 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2569 fsp->h_u.usr_ip4_spec.proto = 0;
2570 fsp->m_u.usr_ip4_spec.proto = 0;
2571 break;
2572 default:
2573 return -EINVAL;
2574 }
2575
2576 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2577 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2578 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2579 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2580 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2581 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2582 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2583 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2584 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2585 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2586 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2587 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2588 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2589 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2590 fsp->flow_type |= FLOW_EXT;
2591
2592 /* record action */
2593 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2594 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2595 else
2596 fsp->ring_cookie = rule->action;
2597
2598 return 0;
2599}
2600
2601static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2602 struct ethtool_rxnfc *cmd,
2603 u32 *rule_locs)
2604{
2605 struct hlist_node *node2;
2606 struct ixgbe_fdir_filter *rule;
2607 int cnt = 0;
2608
2609 /* report total rule count */
2610 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2611
2612 hlist_for_each_entry_safe(rule, node2,
2613 &adapter->fdir_filter_list, fdir_node) {
2614 if (cnt == cmd->rule_cnt)
2615 return -EMSGSIZE;
2616 rule_locs[cnt] = rule->sw_idx;
2617 cnt++;
2618 }
2619
2620 cmd->rule_cnt = cnt;
2621
2622 return 0;
2623}
2624
2625static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2626 struct ethtool_rxnfc *cmd)
2627{
2628 cmd->data = 0;
2629
2630 /* Report default options for RSS on ixgbe */
2631 switch (cmd->flow_type) {
2632 case TCP_V4_FLOW:
2633 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2634 fallthrough;
2635 case UDP_V4_FLOW:
2636 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2637 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2638 fallthrough;
2639 case SCTP_V4_FLOW:
2640 case AH_ESP_V4_FLOW:
2641 case AH_V4_FLOW:
2642 case ESP_V4_FLOW:
2643 case IPV4_FLOW:
2644 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2645 break;
2646 case TCP_V6_FLOW:
2647 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2648 fallthrough;
2649 case UDP_V6_FLOW:
2650 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2651 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2652 fallthrough;
2653 case SCTP_V6_FLOW:
2654 case AH_ESP_V6_FLOW:
2655 case AH_V6_FLOW:
2656 case ESP_V6_FLOW:
2657 case IPV6_FLOW:
2658 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2659 break;
2660 default:
2661 return -EINVAL;
2662 }
2663
2664 return 0;
2665}
2666
2667static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
2668{
2669 if (adapter->hw.mac.type < ixgbe_mac_X550)
2670 return 16;
2671 else
2672 return 64;
2673}
2674
2675static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2676 u32 *rule_locs)
2677{
2678 struct ixgbe_adapter *adapter = netdev_priv(dev);
2679 int ret = -EOPNOTSUPP;
2680
2681 switch (cmd->cmd) {
2682 case ETHTOOL_GRXRINGS:
2683 cmd->data = min_t(int, adapter->num_rx_queues,
2684 ixgbe_rss_indir_tbl_max(adapter));
2685 ret = 0;
2686 break;
2687 case ETHTOOL_GRXCLSRLCNT:
2688 cmd->rule_cnt = adapter->fdir_filter_count;
2689 ret = 0;
2690 break;
2691 case ETHTOOL_GRXCLSRULE:
2692 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2693 break;
2694 case ETHTOOL_GRXCLSRLALL:
2695 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2696 break;
2697 case ETHTOOL_GRXFH:
2698 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2699 break;
2700 default:
2701 break;
2702 }
2703
2704 return ret;
2705}
2706
2707int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2708 struct ixgbe_fdir_filter *input,
2709 u16 sw_idx)
2710{
2711 struct ixgbe_hw *hw = &adapter->hw;
2712 struct hlist_node *node2;
2713 struct ixgbe_fdir_filter *rule, *parent;
2714 int err = -EINVAL;
2715
2716 parent = NULL;
2717 rule = NULL;
2718
2719 hlist_for_each_entry_safe(rule, node2,
2720 &adapter->fdir_filter_list, fdir_node) {
2721 /* hash found, or no matching entry */
2722 if (rule->sw_idx >= sw_idx)
2723 break;
2724 parent = rule;
2725 }
2726
2727 /* if there is an old rule occupying our place remove it */
2728 if (rule && (rule->sw_idx == sw_idx)) {
2729 if (!input || (rule->filter.formatted.bkt_hash !=
2730 input->filter.formatted.bkt_hash)) {
2731 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2732 &rule->filter,
2733 sw_idx);
2734 }
2735
2736 hlist_del(&rule->fdir_node);
2737 kfree(rule);
2738 adapter->fdir_filter_count--;
2739 }
2740
2741 /*
2742 * If no input this was a delete, err should be 0 if a rule was
2743 * successfully found and removed from the list else -EINVAL
2744 */
2745 if (!input)
2746 return err;
2747
2748 /* initialize node and set software index */
2749 INIT_HLIST_NODE(&input->fdir_node);
2750
2751 /* add filter to the list */
2752 if (parent)
2753 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
2754 else
2755 hlist_add_head(&input->fdir_node,
2756 &adapter->fdir_filter_list);
2757
2758 /* update counts */
2759 adapter->fdir_filter_count++;
2760
2761 return 0;
2762}
2763
2764static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2765 u8 *flow_type)
2766{
2767 switch (fsp->flow_type & ~FLOW_EXT) {
2768 case TCP_V4_FLOW:
2769 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2770 break;
2771 case UDP_V4_FLOW:
2772 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2773 break;
2774 case SCTP_V4_FLOW:
2775 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2776 break;
2777 case IP_USER_FLOW:
2778 switch (fsp->h_u.usr_ip4_spec.proto) {
2779 case IPPROTO_TCP:
2780 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2781 break;
2782 case IPPROTO_UDP:
2783 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2784 break;
2785 case IPPROTO_SCTP:
2786 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2787 break;
2788 case 0:
2789 if (!fsp->m_u.usr_ip4_spec.proto) {
2790 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2791 break;
2792 }
2793 fallthrough;
2794 default:
2795 return 0;
2796 }
2797 break;
2798 default:
2799 return 0;
2800 }
2801
2802 return 1;
2803}
2804
2805static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2806 struct ethtool_rxnfc *cmd)
2807{
2808 struct ethtool_rx_flow_spec *fsp =
2809 (struct ethtool_rx_flow_spec *)&cmd->fs;
2810 struct ixgbe_hw *hw = &adapter->hw;
2811 struct ixgbe_fdir_filter *input;
2812 union ixgbe_atr_input mask;
2813 u8 queue;
2814 int err;
2815
2816 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2817 return -EOPNOTSUPP;
2818
2819 /* ring_cookie is a masked into a set of queues and ixgbe pools or
2820 * we use the drop index.
2821 */
2822 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2823 queue = IXGBE_FDIR_DROP_QUEUE;
2824 } else {
2825 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2826 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2827
2828 if (!vf && (ring >= adapter->num_rx_queues))
2829 return -EINVAL;
2830 else if (vf &&
2831 ((vf > adapter->num_vfs) ||
2832 ring >= adapter->num_rx_queues_per_pool))
2833 return -EINVAL;
2834
2835 /* Map the ring onto the absolute queue index */
2836 if (!vf)
2837 queue = adapter->rx_ring[ring]->reg_idx;
2838 else
2839 queue = ((vf - 1) *
2840 adapter->num_rx_queues_per_pool) + ring;
2841 }
2842
2843 /* Don't allow indexes to exist outside of available space */
2844 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2845 e_err(drv, "Location out of range\n");
2846 return -EINVAL;
2847 }
2848
2849 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2850 if (!input)
2851 return -ENOMEM;
2852
2853 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2854
2855 /* set SW index */
2856 input->sw_idx = fsp->location;
2857
2858 /* record flow type */
2859 if (!ixgbe_flowspec_to_flow_type(fsp,
2860 &input->filter.formatted.flow_type)) {
2861 e_err(drv, "Unrecognized flow type\n");
2862 goto err_out;
2863 }
2864
2865 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2866 IXGBE_ATR_L4TYPE_MASK;
2867
2868 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2869 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2870
2871 /* Copy input into formatted structures */
2872 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2873 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2874 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2875 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2876 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2877 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2878 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2879 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2880
2881 if (fsp->flow_type & FLOW_EXT) {
2882 input->filter.formatted.vm_pool =
2883 (unsigned char)ntohl(fsp->h_ext.data[1]);
2884 mask.formatted.vm_pool =
2885 (unsigned char)ntohl(fsp->m_ext.data[1]);
2886 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2887 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2888 input->filter.formatted.flex_bytes =
2889 fsp->h_ext.vlan_etype;
2890 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2891 }
2892
2893 /* determine if we need to drop or route the packet */
2894 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2895 input->action = IXGBE_FDIR_DROP_QUEUE;
2896 else
2897 input->action = fsp->ring_cookie;
2898
2899 spin_lock(&adapter->fdir_perfect_lock);
2900
2901 if (hlist_empty(&adapter->fdir_filter_list)) {
2902 /* save mask and program input mask into HW */
2903 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2904 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2905 if (err) {
2906 e_err(drv, "Error writing mask\n");
2907 goto err_out_w_lock;
2908 }
2909 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2910 e_err(drv, "Only one mask supported per port\n");
2911 goto err_out_w_lock;
2912 }
2913
2914 /* apply mask and compute/store hash */
2915 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2916
2917 /* program filters to filter memory */
2918 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2919 &input->filter, input->sw_idx, queue);
2920 if (err)
2921 goto err_out_w_lock;
2922
2923 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2924
2925 spin_unlock(&adapter->fdir_perfect_lock);
2926
2927 return err;
2928err_out_w_lock:
2929 spin_unlock(&adapter->fdir_perfect_lock);
2930err_out:
2931 kfree(input);
2932 return -EINVAL;
2933}
2934
2935static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2936 struct ethtool_rxnfc *cmd)
2937{
2938 struct ethtool_rx_flow_spec *fsp =
2939 (struct ethtool_rx_flow_spec *)&cmd->fs;
2940 int err;
2941
2942 spin_lock(&adapter->fdir_perfect_lock);
2943 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2944 spin_unlock(&adapter->fdir_perfect_lock);
2945
2946 return err;
2947}
2948
2949#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2950 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2951static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2952 struct ethtool_rxnfc *nfc)
2953{
2954 u32 flags2 = adapter->flags2;
2955
2956 /*
2957 * RSS does not support anything other than hashing
2958 * to queues on src and dst IPs and ports
2959 */
2960 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2961 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2962 return -EINVAL;
2963
2964 switch (nfc->flow_type) {
2965 case TCP_V4_FLOW:
2966 case TCP_V6_FLOW:
2967 if (!(nfc->data & RXH_IP_SRC) ||
2968 !(nfc->data & RXH_IP_DST) ||
2969 !(nfc->data & RXH_L4_B_0_1) ||
2970 !(nfc->data & RXH_L4_B_2_3))
2971 return -EINVAL;
2972 break;
2973 case UDP_V4_FLOW:
2974 if (!(nfc->data & RXH_IP_SRC) ||
2975 !(nfc->data & RXH_IP_DST))
2976 return -EINVAL;
2977 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2978 case 0:
2979 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2980 break;
2981 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2982 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2983 break;
2984 default:
2985 return -EINVAL;
2986 }
2987 break;
2988 case UDP_V6_FLOW:
2989 if (!(nfc->data & RXH_IP_SRC) ||
2990 !(nfc->data & RXH_IP_DST))
2991 return -EINVAL;
2992 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2993 case 0:
2994 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2995 break;
2996 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2997 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2998 break;
2999 default:
3000 return -EINVAL;
3001 }
3002 break;
3003 case AH_ESP_V4_FLOW:
3004 case AH_V4_FLOW:
3005 case ESP_V4_FLOW:
3006 case SCTP_V4_FLOW:
3007 case AH_ESP_V6_FLOW:
3008 case AH_V6_FLOW:
3009 case ESP_V6_FLOW:
3010 case SCTP_V6_FLOW:
3011 if (!(nfc->data & RXH_IP_SRC) ||
3012 !(nfc->data & RXH_IP_DST) ||
3013 (nfc->data & RXH_L4_B_0_1) ||
3014 (nfc->data & RXH_L4_B_2_3))
3015 return -EINVAL;
3016 break;
3017 default:
3018 return -EINVAL;
3019 }
3020
3021 /* if we changed something we need to update flags */
3022 if (flags2 != adapter->flags2) {
3023 struct ixgbe_hw *hw = &adapter->hw;
3024 u32 mrqc;
3025 unsigned int pf_pool = adapter->num_vfs;
3026
3027 if ((hw->mac.type >= ixgbe_mac_X550) &&
3028 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3029 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
3030 else
3031 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3032
3033 if ((flags2 & UDP_RSS_FLAGS) &&
3034 !(adapter->flags2 & UDP_RSS_FLAGS))
3035 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
3036
3037 adapter->flags2 = flags2;
3038
3039 /* Perform hash on these packet types */
3040 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
3041 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
3042 | IXGBE_MRQC_RSS_FIELD_IPV6
3043 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3044
3045 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
3046 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
3047
3048 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3049 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3050
3051 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3052 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3053
3054 if ((hw->mac.type >= ixgbe_mac_X550) &&
3055 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3056 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
3057 else
3058 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3059 }
3060
3061 return 0;
3062}
3063
3064static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3065{
3066 struct ixgbe_adapter *adapter = netdev_priv(dev);
3067 int ret = -EOPNOTSUPP;
3068
3069 switch (cmd->cmd) {
3070 case ETHTOOL_SRXCLSRLINS:
3071 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
3072 break;
3073 case ETHTOOL_SRXCLSRLDEL:
3074 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
3075 break;
3076 case ETHTOOL_SRXFH:
3077 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
3078 break;
3079 default:
3080 break;
3081 }
3082
3083 return ret;
3084}
3085
3086static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
3087{
3088 return IXGBE_RSS_KEY_SIZE;
3089}
3090
3091static u32 ixgbe_rss_indir_size(struct net_device *netdev)
3092{
3093 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3094
3095 return ixgbe_rss_indir_tbl_entries(adapter);
3096}
3097
3098static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
3099{
3100 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
3101 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask;
3102
3103 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3104 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1;
3105
3106 for (i = 0; i < reta_size; i++)
3107 indir[i] = adapter->rss_indir_tbl[i] & rss_m;
3108}
3109
3110static int ixgbe_get_rxfh(struct net_device *netdev,
3111 struct ethtool_rxfh_param *rxfh)
3112{
3113 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3114
3115 rxfh->hfunc = ETH_RSS_HASH_TOP;
3116
3117 if (rxfh->indir)
3118 ixgbe_get_reta(adapter, rxfh->indir);
3119
3120 if (rxfh->key)
3121 memcpy(rxfh->key, adapter->rss_key,
3122 ixgbe_get_rxfh_key_size(netdev));
3123
3124 return 0;
3125}
3126
3127static int ixgbe_set_rxfh(struct net_device *netdev,
3128 struct ethtool_rxfh_param *rxfh,
3129 struct netlink_ext_ack *extack)
3130{
3131 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3132 int i;
3133 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3134
3135 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
3136 rxfh->hfunc != ETH_RSS_HASH_TOP)
3137 return -EOPNOTSUPP;
3138
3139 /* Fill out the redirection table */
3140 if (rxfh->indir) {
3141 int max_queues = min_t(int, adapter->num_rx_queues,
3142 ixgbe_rss_indir_tbl_max(adapter));
3143
3144 /*Allow at least 2 queues w/ SR-IOV.*/
3145 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3146 (max_queues < 2))
3147 max_queues = 2;
3148
3149 /* Verify user input. */
3150 for (i = 0; i < reta_entries; i++)
3151 if (rxfh->indir[i] >= max_queues)
3152 return -EINVAL;
3153
3154 for (i = 0; i < reta_entries; i++)
3155 adapter->rss_indir_tbl[i] = rxfh->indir[i];
3156
3157 ixgbe_store_reta(adapter);
3158 }
3159
3160 /* Fill out the rss hash key */
3161 if (rxfh->key) {
3162 memcpy(adapter->rss_key, rxfh->key,
3163 ixgbe_get_rxfh_key_size(netdev));
3164 ixgbe_store_key(adapter);
3165 }
3166
3167 return 0;
3168}
3169
3170static int ixgbe_get_ts_info(struct net_device *dev,
3171 struct ethtool_ts_info *info)
3172{
3173 struct ixgbe_adapter *adapter = netdev_priv(dev);
3174
3175 /* we always support timestamping disabled */
3176 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
3177
3178 switch (adapter->hw.mac.type) {
3179 case ixgbe_mac_X550:
3180 case ixgbe_mac_X550EM_x:
3181 case ixgbe_mac_x550em_a:
3182 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3183 break;
3184 case ixgbe_mac_X540:
3185 case ixgbe_mac_82599EB:
3186 info->rx_filters |=
3187 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3188 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3189 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3190 break;
3191 default:
3192 return ethtool_op_get_ts_info(dev, info);
3193 }
3194
3195 info->so_timestamping =
3196 SOF_TIMESTAMPING_TX_SOFTWARE |
3197 SOF_TIMESTAMPING_RX_SOFTWARE |
3198 SOF_TIMESTAMPING_SOFTWARE |
3199 SOF_TIMESTAMPING_TX_HARDWARE |
3200 SOF_TIMESTAMPING_RX_HARDWARE |
3201 SOF_TIMESTAMPING_RAW_HARDWARE;
3202
3203 if (adapter->ptp_clock)
3204 info->phc_index = ptp_clock_index(adapter->ptp_clock);
3205 else
3206 info->phc_index = -1;
3207
3208 info->tx_types =
3209 BIT(HWTSTAMP_TX_OFF) |
3210 BIT(HWTSTAMP_TX_ON);
3211
3212 return 0;
3213}
3214
3215static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3216{
3217 unsigned int max_combined;
3218 u8 tcs = adapter->hw_tcs;
3219
3220 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3221 /* We only support one q_vector without MSI-X */
3222 max_combined = 1;
3223 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3224 /* Limit value based on the queue mask */
3225 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1;
3226 } else if (tcs > 1) {
3227 /* For DCB report channels per traffic class */
3228 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3229 /* 8 TC w/ 4 queues per TC */
3230 max_combined = 4;
3231 } else if (tcs > 4) {
3232 /* 8 TC w/ 8 queues per TC */
3233 max_combined = 8;
3234 } else {
3235 /* 4 TC w/ 16 queues per TC */
3236 max_combined = 16;
3237 }
3238 } else if (adapter->atr_sample_rate) {
3239 /* support up to 64 queues with ATR */
3240 max_combined = IXGBE_MAX_FDIR_INDICES;
3241 } else {
3242 /* support up to 16 queues with RSS */
3243 max_combined = ixgbe_max_rss_indices(adapter);
3244 }
3245
3246 return min_t(int, max_combined, num_online_cpus());
3247}
3248
3249static void ixgbe_get_channels(struct net_device *dev,
3250 struct ethtool_channels *ch)
3251{
3252 struct ixgbe_adapter *adapter = netdev_priv(dev);
3253
3254 /* report maximum channels */
3255 ch->max_combined = ixgbe_max_channels(adapter);
3256
3257 /* report info for other vector */
3258 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3259 ch->max_other = NON_Q_VECTORS;
3260 ch->other_count = NON_Q_VECTORS;
3261 }
3262
3263 /* record RSS queues */
3264 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3265
3266 /* nothing else to report if RSS is disabled */
3267 if (ch->combined_count == 1)
3268 return;
3269
3270 /* we do not support ATR queueing if SR-IOV is enabled */
3271 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3272 return;
3273
3274 /* same thing goes for being DCB enabled */
3275 if (adapter->hw_tcs > 1)
3276 return;
3277
3278 /* if ATR is disabled we can exit */
3279 if (!adapter->atr_sample_rate)
3280 return;
3281
3282 /* report flow director queues as maximum channels */
3283 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3284}
3285
3286static int ixgbe_set_channels(struct net_device *dev,
3287 struct ethtool_channels *ch)
3288{
3289 struct ixgbe_adapter *adapter = netdev_priv(dev);
3290 unsigned int count = ch->combined_count;
3291 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3292
3293 /* verify they are not requesting separate vectors */
3294 if (!count || ch->rx_count || ch->tx_count)
3295 return -EINVAL;
3296
3297 /* verify other_count has not changed */
3298 if (ch->other_count != NON_Q_VECTORS)
3299 return -EINVAL;
3300
3301 /* verify the number of channels does not exceed hardware limits */
3302 if (count > ixgbe_max_channels(adapter))
3303 return -EINVAL;
3304
3305 /* update feature limits from largest to smallest supported values */
3306 adapter->ring_feature[RING_F_FDIR].limit = count;
3307
3308 /* cap RSS limit */
3309 if (count > max_rss_indices)
3310 count = max_rss_indices;
3311 adapter->ring_feature[RING_F_RSS].limit = count;
3312
3313#ifdef IXGBE_FCOE
3314 /* cap FCoE limit at 8 */
3315 if (count > IXGBE_FCRETA_SIZE)
3316 count = IXGBE_FCRETA_SIZE;
3317 adapter->ring_feature[RING_F_FCOE].limit = count;
3318
3319#endif
3320 /* use setup TC to update any traffic class queue mapping */
3321 return ixgbe_setup_tc(dev, adapter->hw_tcs);
3322}
3323
3324static int ixgbe_get_module_info(struct net_device *dev,
3325 struct ethtool_modinfo *modinfo)
3326{
3327 struct ixgbe_adapter *adapter = netdev_priv(dev);
3328 struct ixgbe_hw *hw = &adapter->hw;
3329 s32 status;
3330 u8 sff8472_rev, addr_mode;
3331 bool page_swap = false;
3332
3333 if (hw->phy.type == ixgbe_phy_fw)
3334 return -ENXIO;
3335
3336 /* Check whether we support SFF-8472 or not */
3337 status = hw->phy.ops.read_i2c_eeprom(hw,
3338 IXGBE_SFF_SFF_8472_COMP,
3339 &sff8472_rev);
3340 if (status)
3341 return -EIO;
3342
3343 /* addressing mode is not supported */
3344 status = hw->phy.ops.read_i2c_eeprom(hw,
3345 IXGBE_SFF_SFF_8472_SWAP,
3346 &addr_mode);
3347 if (status)
3348 return -EIO;
3349
3350 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3351 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3352 page_swap = true;
3353 }
3354
3355 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap ||
3356 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) {
3357 /* We have a SFP, but it does not support SFF-8472 */
3358 modinfo->type = ETH_MODULE_SFF_8079;
3359 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3360 } else {
3361 /* We have a SFP which supports a revision of SFF-8472. */
3362 modinfo->type = ETH_MODULE_SFF_8472;
3363 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3364 }
3365
3366 return 0;
3367}
3368
3369static int ixgbe_get_module_eeprom(struct net_device *dev,
3370 struct ethtool_eeprom *ee,
3371 u8 *data)
3372{
3373 struct ixgbe_adapter *adapter = netdev_priv(dev);
3374 struct ixgbe_hw *hw = &adapter->hw;
3375 s32 status = -EFAULT;
3376 u8 databyte = 0xFF;
3377 int i = 0;
3378
3379 if (ee->len == 0)
3380 return -EINVAL;
3381
3382 if (hw->phy.type == ixgbe_phy_fw)
3383 return -ENXIO;
3384
3385 for (i = ee->offset; i < ee->offset + ee->len; i++) {
3386 /* I2C reads can take long time */
3387 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3388 return -EBUSY;
3389
3390 if (i < ETH_MODULE_SFF_8079_LEN)
3391 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3392 else
3393 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3394
3395 if (status)
3396 return -EIO;
3397
3398 data[i - ee->offset] = databyte;
3399 }
3400
3401 return 0;
3402}
3403
3404static const struct {
3405 ixgbe_link_speed mac_speed;
3406 u32 supported;
3407} ixgbe_ls_map[] = {
3408 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full },
3409 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full },
3410 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full },
3411 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full },
3412 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full },
3413};
3414
3415static const struct {
3416 u32 lp_advertised;
3417 u32 mac_speed;
3418} ixgbe_lp_map[] = {
3419 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full },
3420 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full },
3421 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full },
3422 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full },
3423 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full },
3424 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full},
3425};
3426
3427static int
3428ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata)
3429{
3430 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
3431 struct ixgbe_hw *hw = &adapter->hw;
3432 s32 rc;
3433 u16 i;
3434
3435 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info);
3436 if (rc)
3437 return rc;
3438
3439 edata->lp_advertised = 0;
3440 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) {
3441 if (info[0] & ixgbe_lp_map[i].lp_advertised)
3442 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed;
3443 }
3444
3445 edata->supported = 0;
3446 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3447 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed)
3448 edata->supported |= ixgbe_ls_map[i].supported;
3449 }
3450
3451 edata->advertised = 0;
3452 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3453 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed)
3454 edata->advertised |= ixgbe_ls_map[i].supported;
3455 }
3456
3457 edata->eee_enabled = !!edata->advertised;
3458 edata->tx_lpi_enabled = edata->eee_enabled;
3459 if (edata->advertised & edata->lp_advertised)
3460 edata->eee_active = true;
3461
3462 return 0;
3463}
3464
3465static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3466{
3467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3468 struct ixgbe_hw *hw = &adapter->hw;
3469
3470 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3471 return -EOPNOTSUPP;
3472
3473 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw)
3474 return ixgbe_get_eee_fw(adapter, edata);
3475
3476 return -EOPNOTSUPP;
3477}
3478
3479static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
3480{
3481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3482 struct ixgbe_hw *hw = &adapter->hw;
3483 struct ethtool_eee eee_data;
3484 s32 ret_val;
3485
3486 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3487 return -EOPNOTSUPP;
3488
3489 memset(&eee_data, 0, sizeof(struct ethtool_eee));
3490
3491 ret_val = ixgbe_get_eee(netdev, &eee_data);
3492 if (ret_val)
3493 return ret_val;
3494
3495 if (eee_data.eee_enabled && !edata->eee_enabled) {
3496 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) {
3497 e_err(drv, "Setting EEE tx-lpi is not supported\n");
3498 return -EINVAL;
3499 }
3500
3501 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) {
3502 e_err(drv,
3503 "Setting EEE Tx LPI timer is not supported\n");
3504 return -EINVAL;
3505 }
3506
3507 if (eee_data.advertised != edata->advertised) {
3508 e_err(drv,
3509 "Setting EEE advertised speeds is not supported\n");
3510 return -EINVAL;
3511 }
3512 }
3513
3514 if (eee_data.eee_enabled != edata->eee_enabled) {
3515 if (edata->eee_enabled) {
3516 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
3517 hw->phy.eee_speeds_advertised =
3518 hw->phy.eee_speeds_supported;
3519 } else {
3520 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
3521 hw->phy.eee_speeds_advertised = 0;
3522 }
3523
3524 /* reset link */
3525 if (netif_running(netdev))
3526 ixgbe_reinit_locked(adapter);
3527 else
3528 ixgbe_reset(adapter);
3529 }
3530
3531 return 0;
3532}
3533
3534static u32 ixgbe_get_priv_flags(struct net_device *netdev)
3535{
3536 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3537 u32 priv_flags = 0;
3538
3539 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
3540 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX;
3541
3542 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED)
3543 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN;
3544
3545 if (adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF)
3546 priv_flags |= IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF;
3547
3548 return priv_flags;
3549}
3550
3551static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3552{
3553 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3554 unsigned int flags2 = adapter->flags2;
3555 unsigned int i;
3556
3557 flags2 &= ~IXGBE_FLAG2_RX_LEGACY;
3558 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX)
3559 flags2 |= IXGBE_FLAG2_RX_LEGACY;
3560
3561 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED;
3562 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN)
3563 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED;
3564
3565 flags2 &= ~IXGBE_FLAG2_AUTO_DISABLE_VF;
3566 if (priv_flags & IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF) {
3567 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3568 /* Reset primary abort counter */
3569 for (i = 0; i < adapter->num_vfs; i++)
3570 adapter->vfinfo[i].primary_abort_count = 0;
3571
3572 flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF;
3573 } else {
3574 e_info(probe,
3575 "Cannot set private flags: Operation not supported\n");
3576 return -EOPNOTSUPP;
3577 }
3578 }
3579
3580 if (flags2 != adapter->flags2) {
3581 adapter->flags2 = flags2;
3582
3583 /* reset interface to repopulate queues */
3584 if (netif_running(netdev))
3585 ixgbe_reinit_locked(adapter);
3586 }
3587
3588 return 0;
3589}
3590
3591static const struct ethtool_ops ixgbe_ethtool_ops = {
3592 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3593 .get_drvinfo = ixgbe_get_drvinfo,
3594 .get_regs_len = ixgbe_get_regs_len,
3595 .get_regs = ixgbe_get_regs,
3596 .get_wol = ixgbe_get_wol,
3597 .set_wol = ixgbe_set_wol,
3598 .nway_reset = ixgbe_nway_reset,
3599 .get_link = ethtool_op_get_link,
3600 .get_eeprom_len = ixgbe_get_eeprom_len,
3601 .get_eeprom = ixgbe_get_eeprom,
3602 .set_eeprom = ixgbe_set_eeprom,
3603 .get_ringparam = ixgbe_get_ringparam,
3604 .set_ringparam = ixgbe_set_ringparam,
3605 .get_pause_stats = ixgbe_get_pause_stats,
3606 .get_pauseparam = ixgbe_get_pauseparam,
3607 .set_pauseparam = ixgbe_set_pauseparam,
3608 .get_msglevel = ixgbe_get_msglevel,
3609 .set_msglevel = ixgbe_set_msglevel,
3610 .self_test = ixgbe_diag_test,
3611 .get_strings = ixgbe_get_strings,
3612 .set_phys_id = ixgbe_set_phys_id,
3613 .get_sset_count = ixgbe_get_sset_count,
3614 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3615 .get_coalesce = ixgbe_get_coalesce,
3616 .set_coalesce = ixgbe_set_coalesce,
3617 .get_rxnfc = ixgbe_get_rxnfc,
3618 .set_rxnfc = ixgbe_set_rxnfc,
3619 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3620 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3621 .get_rxfh = ixgbe_get_rxfh,
3622 .set_rxfh = ixgbe_set_rxfh,
3623 .get_eee = ixgbe_get_eee,
3624 .set_eee = ixgbe_set_eee,
3625 .get_channels = ixgbe_get_channels,
3626 .set_channels = ixgbe_set_channels,
3627 .get_priv_flags = ixgbe_get_priv_flags,
3628 .set_priv_flags = ixgbe_set_priv_flags,
3629 .get_ts_info = ixgbe_get_ts_info,
3630 .get_module_info = ixgbe_get_module_info,
3631 .get_module_eeprom = ixgbe_get_module_eeprom,
3632 .get_link_ksettings = ixgbe_get_link_ksettings,
3633 .set_link_ksettings = ixgbe_set_link_ksettings,
3634};
3635
3636void ixgbe_set_ethtool_ops(struct net_device *netdev)
3637{
3638 netdev->ethtool_ops = &ixgbe_ethtool_ops;
3639}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4/* ethtool support for ixgbe */
5
6#include <linux/interrupt.h>
7#include <linux/types.h>
8#include <linux/module.h>
9#include <linux/slab.h>
10#include <linux/pci.h>
11#include <linux/netdevice.h>
12#include <linux/ethtool.h>
13#include <linux/vmalloc.h>
14#include <linux/highmem.h>
15#include <linux/uaccess.h>
16
17#include "ixgbe.h"
18#include "ixgbe_phy.h"
19
20
21#define IXGBE_ALL_RAR_ENTRIES 16
22
23enum {NETDEV_STATS, IXGBE_STATS};
24
25struct ixgbe_stats {
26 char stat_string[ETH_GSTRING_LEN];
27 int type;
28 int sizeof_stat;
29 int stat_offset;
30};
31
32#define IXGBE_STAT(m) IXGBE_STATS, \
33 sizeof(((struct ixgbe_adapter *)0)->m), \
34 offsetof(struct ixgbe_adapter, m)
35#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
36 sizeof(((struct rtnl_link_stats64 *)0)->m), \
37 offsetof(struct rtnl_link_stats64, m)
38
39static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
40 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
41 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
42 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
43 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
44 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
45 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
46 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
47 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
48 {"lsc_int", IXGBE_STAT(lsc_int)},
49 {"tx_busy", IXGBE_STAT(tx_busy)},
50 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
51 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
52 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
53 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
54 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
55 {"multicast", IXGBE_NETDEV_STAT(multicast)},
56 {"broadcast", IXGBE_STAT(stats.bprc)},
57 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
58 {"collisions", IXGBE_NETDEV_STAT(collisions)},
59 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
60 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
61 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
62 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
63 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
64 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
65 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
66 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
67 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
68 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
69 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
70 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
71 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
72 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
73 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
74 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
75 {"rx_length_errors", IXGBE_STAT(stats.rlec)},
76 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
77 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
78 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
79 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
80 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
81 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
82 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
83 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)},
84 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
85 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
86 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
87 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
88 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
89 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
90 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
91 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)},
92 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)},
93 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)},
94 {"tx_ipsec", IXGBE_STAT(tx_ipsec)},
95 {"rx_ipsec", IXGBE_STAT(rx_ipsec)},
96#ifdef IXGBE_FCOE
97 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
98 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
99 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
100 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
101 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
102 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
103 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
104 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
105#endif /* IXGBE_FCOE */
106};
107
108/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
109 * we set the num_rx_queues to evaluate to num_tx_queues. This is
110 * used because we do not have a good way to get the max number of
111 * rx queues with CONFIG_RPS disabled.
112 */
113#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
114
115#define IXGBE_QUEUE_STATS_LEN ( \
116 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
117 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
118#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
119#define IXGBE_PB_STATS_LEN ( \
120 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
121 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
122 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
123 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
124 / sizeof(u64))
125#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
126 IXGBE_PB_STATS_LEN + \
127 IXGBE_QUEUE_STATS_LEN)
128
129static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
130 "Register test (offline)", "Eeprom test (offline)",
131 "Interrupt test (offline)", "Loopback test (offline)",
132 "Link test (on/offline)"
133};
134#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
135
136static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = {
137#define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0)
138 "legacy-rx",
139#define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1)
140 "vf-ipsec",
141};
142
143#define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings)
144
145#define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
146
147static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw,
148 struct ethtool_link_ksettings *cmd)
149{
150 if (!ixgbe_isbackplane(hw->phy.media_type)) {
151 ethtool_link_ksettings_add_link_mode(cmd, supported,
152 10000baseT_Full);
153 return;
154 }
155
156 switch (hw->device_id) {
157 case IXGBE_DEV_ID_82598:
158 case IXGBE_DEV_ID_82599_KX4:
159 case IXGBE_DEV_ID_82599_KX4_MEZZ:
160 case IXGBE_DEV_ID_X550EM_X_KX4:
161 ethtool_link_ksettings_add_link_mode
162 (cmd, supported, 10000baseKX4_Full);
163 break;
164 case IXGBE_DEV_ID_82598_BX:
165 case IXGBE_DEV_ID_82599_KR:
166 case IXGBE_DEV_ID_X550EM_X_KR:
167 case IXGBE_DEV_ID_X550EM_X_XFI:
168 ethtool_link_ksettings_add_link_mode
169 (cmd, supported, 10000baseKR_Full);
170 break;
171 default:
172 ethtool_link_ksettings_add_link_mode
173 (cmd, supported, 10000baseKX4_Full);
174 ethtool_link_ksettings_add_link_mode
175 (cmd, supported, 10000baseKR_Full);
176 break;
177 }
178}
179
180static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw,
181 struct ethtool_link_ksettings *cmd)
182{
183 if (!ixgbe_isbackplane(hw->phy.media_type)) {
184 ethtool_link_ksettings_add_link_mode(cmd, advertising,
185 10000baseT_Full);
186 return;
187 }
188
189 switch (hw->device_id) {
190 case IXGBE_DEV_ID_82598:
191 case IXGBE_DEV_ID_82599_KX4:
192 case IXGBE_DEV_ID_82599_KX4_MEZZ:
193 case IXGBE_DEV_ID_X550EM_X_KX4:
194 ethtool_link_ksettings_add_link_mode
195 (cmd, advertising, 10000baseKX4_Full);
196 break;
197 case IXGBE_DEV_ID_82598_BX:
198 case IXGBE_DEV_ID_82599_KR:
199 case IXGBE_DEV_ID_X550EM_X_KR:
200 case IXGBE_DEV_ID_X550EM_X_XFI:
201 ethtool_link_ksettings_add_link_mode
202 (cmd, advertising, 10000baseKR_Full);
203 break;
204 default:
205 ethtool_link_ksettings_add_link_mode
206 (cmd, advertising, 10000baseKX4_Full);
207 ethtool_link_ksettings_add_link_mode
208 (cmd, advertising, 10000baseKR_Full);
209 break;
210 }
211}
212
213static int ixgbe_get_link_ksettings(struct net_device *netdev,
214 struct ethtool_link_ksettings *cmd)
215{
216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
217 struct ixgbe_hw *hw = &adapter->hw;
218 ixgbe_link_speed supported_link;
219 bool autoneg = false;
220
221 ethtool_link_ksettings_zero_link_mode(cmd, supported);
222 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
223
224 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
225
226 /* set the supported link speeds */
227 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) {
228 ixgbe_set_supported_10gtypes(hw, cmd);
229 ixgbe_set_advertising_10gtypes(hw, cmd);
230 }
231 if (supported_link & IXGBE_LINK_SPEED_5GB_FULL)
232 ethtool_link_ksettings_add_link_mode(cmd, supported,
233 5000baseT_Full);
234
235 if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL)
236 ethtool_link_ksettings_add_link_mode(cmd, supported,
237 2500baseT_Full);
238
239 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) {
240 if (ixgbe_isbackplane(hw->phy.media_type)) {
241 ethtool_link_ksettings_add_link_mode(cmd, supported,
242 1000baseKX_Full);
243 ethtool_link_ksettings_add_link_mode(cmd, advertising,
244 1000baseKX_Full);
245 } else {
246 ethtool_link_ksettings_add_link_mode(cmd, supported,
247 1000baseT_Full);
248 ethtool_link_ksettings_add_link_mode(cmd, advertising,
249 1000baseT_Full);
250 }
251 }
252 if (supported_link & IXGBE_LINK_SPEED_100_FULL) {
253 ethtool_link_ksettings_add_link_mode(cmd, supported,
254 100baseT_Full);
255 ethtool_link_ksettings_add_link_mode(cmd, advertising,
256 100baseT_Full);
257 }
258 if (supported_link & IXGBE_LINK_SPEED_10_FULL) {
259 ethtool_link_ksettings_add_link_mode(cmd, supported,
260 10baseT_Full);
261 ethtool_link_ksettings_add_link_mode(cmd, advertising,
262 10baseT_Full);
263 }
264
265 /* set the advertised speeds */
266 if (hw->phy.autoneg_advertised) {
267 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
268 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
269 ethtool_link_ksettings_add_link_mode(cmd, advertising,
270 10baseT_Full);
271 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
272 ethtool_link_ksettings_add_link_mode(cmd, advertising,
273 100baseT_Full);
274 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
275 ixgbe_set_advertising_10gtypes(hw, cmd);
276 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
277 if (ethtool_link_ksettings_test_link_mode
278 (cmd, supported, 1000baseKX_Full))
279 ethtool_link_ksettings_add_link_mode
280 (cmd, advertising, 1000baseKX_Full);
281 else
282 ethtool_link_ksettings_add_link_mode
283 (cmd, advertising, 1000baseT_Full);
284 }
285 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL)
286 ethtool_link_ksettings_add_link_mode(cmd, advertising,
287 5000baseT_Full);
288 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
289 ethtool_link_ksettings_add_link_mode(cmd, advertising,
290 2500baseT_Full);
291 } else {
292 if (hw->phy.multispeed_fiber && !autoneg) {
293 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
294 ethtool_link_ksettings_add_link_mode
295 (cmd, advertising, 10000baseT_Full);
296 }
297 }
298
299 if (autoneg) {
300 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
301 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
302 cmd->base.autoneg = AUTONEG_ENABLE;
303 } else
304 cmd->base.autoneg = AUTONEG_DISABLE;
305
306 /* Determine the remaining settings based on the PHY type. */
307 switch (adapter->hw.phy.type) {
308 case ixgbe_phy_tn:
309 case ixgbe_phy_aq:
310 case ixgbe_phy_x550em_ext_t:
311 case ixgbe_phy_fw:
312 case ixgbe_phy_cu_unknown:
313 ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
314 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
315 cmd->base.port = PORT_TP;
316 break;
317 case ixgbe_phy_qt:
318 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
319 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
320 cmd->base.port = PORT_FIBRE;
321 break;
322 case ixgbe_phy_nl:
323 case ixgbe_phy_sfp_passive_tyco:
324 case ixgbe_phy_sfp_passive_unknown:
325 case ixgbe_phy_sfp_ftl:
326 case ixgbe_phy_sfp_avago:
327 case ixgbe_phy_sfp_intel:
328 case ixgbe_phy_sfp_unknown:
329 case ixgbe_phy_qsfp_passive_unknown:
330 case ixgbe_phy_qsfp_active_unknown:
331 case ixgbe_phy_qsfp_intel:
332 case ixgbe_phy_qsfp_unknown:
333 /* SFP+ devices, further checking needed */
334 switch (adapter->hw.phy.sfp_type) {
335 case ixgbe_sfp_type_da_cu:
336 case ixgbe_sfp_type_da_cu_core0:
337 case ixgbe_sfp_type_da_cu_core1:
338 ethtool_link_ksettings_add_link_mode(cmd, supported,
339 FIBRE);
340 ethtool_link_ksettings_add_link_mode(cmd, advertising,
341 FIBRE);
342 cmd->base.port = PORT_DA;
343 break;
344 case ixgbe_sfp_type_sr:
345 case ixgbe_sfp_type_lr:
346 case ixgbe_sfp_type_srlr_core0:
347 case ixgbe_sfp_type_srlr_core1:
348 case ixgbe_sfp_type_1g_sx_core0:
349 case ixgbe_sfp_type_1g_sx_core1:
350 case ixgbe_sfp_type_1g_lx_core0:
351 case ixgbe_sfp_type_1g_lx_core1:
352 ethtool_link_ksettings_add_link_mode(cmd, supported,
353 FIBRE);
354 ethtool_link_ksettings_add_link_mode(cmd, advertising,
355 FIBRE);
356 cmd->base.port = PORT_FIBRE;
357 break;
358 case ixgbe_sfp_type_not_present:
359 ethtool_link_ksettings_add_link_mode(cmd, supported,
360 FIBRE);
361 ethtool_link_ksettings_add_link_mode(cmd, advertising,
362 FIBRE);
363 cmd->base.port = PORT_NONE;
364 break;
365 case ixgbe_sfp_type_1g_cu_core0:
366 case ixgbe_sfp_type_1g_cu_core1:
367 ethtool_link_ksettings_add_link_mode(cmd, supported,
368 TP);
369 ethtool_link_ksettings_add_link_mode(cmd, advertising,
370 TP);
371 cmd->base.port = PORT_TP;
372 break;
373 case ixgbe_sfp_type_unknown:
374 default:
375 ethtool_link_ksettings_add_link_mode(cmd, supported,
376 FIBRE);
377 ethtool_link_ksettings_add_link_mode(cmd, advertising,
378 FIBRE);
379 cmd->base.port = PORT_OTHER;
380 break;
381 }
382 break;
383 case ixgbe_phy_xaui:
384 ethtool_link_ksettings_add_link_mode(cmd, supported,
385 FIBRE);
386 ethtool_link_ksettings_add_link_mode(cmd, advertising,
387 FIBRE);
388 cmd->base.port = PORT_NONE;
389 break;
390 case ixgbe_phy_unknown:
391 case ixgbe_phy_generic:
392 case ixgbe_phy_sfp_unsupported:
393 default:
394 ethtool_link_ksettings_add_link_mode(cmd, supported,
395 FIBRE);
396 ethtool_link_ksettings_add_link_mode(cmd, advertising,
397 FIBRE);
398 cmd->base.port = PORT_OTHER;
399 break;
400 }
401
402 /* Indicate pause support */
403 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
404
405 switch (hw->fc.requested_mode) {
406 case ixgbe_fc_full:
407 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
408 break;
409 case ixgbe_fc_rx_pause:
410 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
411 ethtool_link_ksettings_add_link_mode(cmd, advertising,
412 Asym_Pause);
413 break;
414 case ixgbe_fc_tx_pause:
415 ethtool_link_ksettings_add_link_mode(cmd, advertising,
416 Asym_Pause);
417 break;
418 default:
419 ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause);
420 ethtool_link_ksettings_del_link_mode(cmd, advertising,
421 Asym_Pause);
422 }
423
424 if (netif_carrier_ok(netdev)) {
425 switch (adapter->link_speed) {
426 case IXGBE_LINK_SPEED_10GB_FULL:
427 cmd->base.speed = SPEED_10000;
428 break;
429 case IXGBE_LINK_SPEED_5GB_FULL:
430 cmd->base.speed = SPEED_5000;
431 break;
432 case IXGBE_LINK_SPEED_2_5GB_FULL:
433 cmd->base.speed = SPEED_2500;
434 break;
435 case IXGBE_LINK_SPEED_1GB_FULL:
436 cmd->base.speed = SPEED_1000;
437 break;
438 case IXGBE_LINK_SPEED_100_FULL:
439 cmd->base.speed = SPEED_100;
440 break;
441 case IXGBE_LINK_SPEED_10_FULL:
442 cmd->base.speed = SPEED_10;
443 break;
444 default:
445 break;
446 }
447 cmd->base.duplex = DUPLEX_FULL;
448 } else {
449 cmd->base.speed = SPEED_UNKNOWN;
450 cmd->base.duplex = DUPLEX_UNKNOWN;
451 }
452
453 return 0;
454}
455
456static int ixgbe_set_link_ksettings(struct net_device *netdev,
457 const struct ethtool_link_ksettings *cmd)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 struct ixgbe_hw *hw = &adapter->hw;
461 u32 advertised, old;
462 s32 err = 0;
463
464 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
465 (hw->phy.multispeed_fiber)) {
466 /*
467 * this function does not support duplex forcing, but can
468 * limit the advertising of the adapter to the specified speed
469 */
470 if (!bitmap_subset(cmd->link_modes.advertising,
471 cmd->link_modes.supported,
472 __ETHTOOL_LINK_MODE_MASK_NBITS))
473 return -EINVAL;
474
475 /* only allow one speed at a time if no autoneg */
476 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) {
477 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
478 10000baseT_Full) &&
479 ethtool_link_ksettings_test_link_mode(cmd, advertising,
480 1000baseT_Full))
481 return -EINVAL;
482 }
483
484 old = hw->phy.autoneg_advertised;
485 advertised = 0;
486 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
487 10000baseT_Full))
488 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
489 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
490 5000baseT_Full))
491 advertised |= IXGBE_LINK_SPEED_5GB_FULL;
492 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
493 2500baseT_Full))
494 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
495 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
496 1000baseT_Full))
497 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
498
499 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
500 100baseT_Full))
501 advertised |= IXGBE_LINK_SPEED_100_FULL;
502
503 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
504 10baseT_Full))
505 advertised |= IXGBE_LINK_SPEED_10_FULL;
506
507 if (old == advertised)
508 return err;
509 /* this sets the link speed and restarts auto-neg */
510 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
511 usleep_range(1000, 2000);
512
513 hw->mac.autotry_restart = true;
514 err = hw->mac.ops.setup_link(hw, advertised, true);
515 if (err) {
516 e_info(probe, "setup link failed with code %d\n", err);
517 hw->mac.ops.setup_link(hw, old, true);
518 }
519 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
520 } else {
521 /* in this case we currently only support 10Gb/FULL */
522 u32 speed = cmd->base.speed;
523
524 if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
525 (!ethtool_link_ksettings_test_link_mode(cmd, advertising,
526 10000baseT_Full)) ||
527 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL))
528 return -EINVAL;
529 }
530
531 return err;
532}
533
534static void ixgbe_get_pauseparam(struct net_device *netdev,
535 struct ethtool_pauseparam *pause)
536{
537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
538 struct ixgbe_hw *hw = &adapter->hw;
539
540 if (ixgbe_device_supports_autoneg_fc(hw) &&
541 !hw->fc.disable_fc_autoneg)
542 pause->autoneg = 1;
543 else
544 pause->autoneg = 0;
545
546 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
547 pause->rx_pause = 1;
548 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
549 pause->tx_pause = 1;
550 } else if (hw->fc.current_mode == ixgbe_fc_full) {
551 pause->rx_pause = 1;
552 pause->tx_pause = 1;
553 }
554}
555
556static int ixgbe_set_pauseparam(struct net_device *netdev,
557 struct ethtool_pauseparam *pause)
558{
559 struct ixgbe_adapter *adapter = netdev_priv(netdev);
560 struct ixgbe_hw *hw = &adapter->hw;
561 struct ixgbe_fc_info fc = hw->fc;
562
563 /* 82598 does no support link flow control with DCB enabled */
564 if ((hw->mac.type == ixgbe_mac_82598EB) &&
565 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
566 return -EINVAL;
567
568 /* some devices do not support autoneg of link flow control */
569 if ((pause->autoneg == AUTONEG_ENABLE) &&
570 !ixgbe_device_supports_autoneg_fc(hw))
571 return -EINVAL;
572
573 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
574
575 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
576 fc.requested_mode = ixgbe_fc_full;
577 else if (pause->rx_pause && !pause->tx_pause)
578 fc.requested_mode = ixgbe_fc_rx_pause;
579 else if (!pause->rx_pause && pause->tx_pause)
580 fc.requested_mode = ixgbe_fc_tx_pause;
581 else
582 fc.requested_mode = ixgbe_fc_none;
583
584 /* if the thing changed then we'll update and use new autoneg */
585 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
586 hw->fc = fc;
587 if (netif_running(netdev))
588 ixgbe_reinit_locked(adapter);
589 else
590 ixgbe_reset(adapter);
591 }
592
593 return 0;
594}
595
596static u32 ixgbe_get_msglevel(struct net_device *netdev)
597{
598 struct ixgbe_adapter *adapter = netdev_priv(netdev);
599 return adapter->msg_enable;
600}
601
602static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
603{
604 struct ixgbe_adapter *adapter = netdev_priv(netdev);
605 adapter->msg_enable = data;
606}
607
608static int ixgbe_get_regs_len(struct net_device *netdev)
609{
610#define IXGBE_REGS_LEN 1145
611 return IXGBE_REGS_LEN * sizeof(u32);
612}
613
614#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
615
616static void ixgbe_get_regs(struct net_device *netdev,
617 struct ethtool_regs *regs, void *p)
618{
619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
620 struct ixgbe_hw *hw = &adapter->hw;
621 u32 *regs_buff = p;
622 u8 i;
623
624 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
625
626 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
627 hw->device_id;
628
629 /* General Registers */
630 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
631 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
632 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
633 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
634 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
635 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
636 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
637 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
638
639 /* NVM Register */
640 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
641 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
642 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
643 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
644 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
645 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
646 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
647 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
648 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
649 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
650
651 /* Interrupt */
652 /* don't read EICR because it can clear interrupt causes, instead
653 * read EICS which is a shadow but doesn't clear EICR */
654 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
655 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
656 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
657 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
658 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
659 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
660 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
661 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
662 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
663 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
664 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
665 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
666
667 /* Flow Control */
668 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
669 for (i = 0; i < 4; i++)
670 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
671 for (i = 0; i < 8; i++) {
672 switch (hw->mac.type) {
673 case ixgbe_mac_82598EB:
674 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
675 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
676 break;
677 case ixgbe_mac_82599EB:
678 case ixgbe_mac_X540:
679 case ixgbe_mac_X550:
680 case ixgbe_mac_X550EM_x:
681 case ixgbe_mac_x550em_a:
682 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
683 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
684 break;
685 default:
686 break;
687 }
688 }
689 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
690 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
691
692 /* Receive DMA */
693 for (i = 0; i < 64; i++)
694 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
695 for (i = 0; i < 64; i++)
696 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
697 for (i = 0; i < 64; i++)
698 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
699 for (i = 0; i < 64; i++)
700 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
701 for (i = 0; i < 64; i++)
702 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
703 for (i = 0; i < 64; i++)
704 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
705 for (i = 0; i < 16; i++)
706 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
707 for (i = 0; i < 16; i++)
708 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
709 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
710 for (i = 0; i < 8; i++)
711 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
712 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
713 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
714
715 /* Receive */
716 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
717 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
718 for (i = 0; i < 16; i++)
719 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
720 for (i = 0; i < 16; i++)
721 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
722 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
723 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
724 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
725 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
726 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
727 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
728 for (i = 0; i < 8; i++)
729 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
730 for (i = 0; i < 8; i++)
731 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
732 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
733
734 /* Transmit */
735 for (i = 0; i < 32; i++)
736 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
737 for (i = 0; i < 32; i++)
738 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
739 for (i = 0; i < 32; i++)
740 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
741 for (i = 0; i < 32; i++)
742 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
743 for (i = 0; i < 32; i++)
744 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
745 for (i = 0; i < 32; i++)
746 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
747 for (i = 0; i < 32; i++)
748 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
749 for (i = 0; i < 32; i++)
750 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
751 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
752 for (i = 0; i < 16; i++)
753 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
754 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
755 for (i = 0; i < 8; i++)
756 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
757 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
758
759 /* Wake Up */
760 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
761 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
762 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
763 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
764 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
765 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
766 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
767 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
768 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
769
770 /* DCB */
771 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
772 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
773
774 switch (hw->mac.type) {
775 case ixgbe_mac_82598EB:
776 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
777 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
778 for (i = 0; i < 8; i++)
779 regs_buff[833 + i] =
780 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
781 for (i = 0; i < 8; i++)
782 regs_buff[841 + i] =
783 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
784 for (i = 0; i < 8; i++)
785 regs_buff[849 + i] =
786 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
787 for (i = 0; i < 8; i++)
788 regs_buff[857 + i] =
789 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
790 break;
791 case ixgbe_mac_82599EB:
792 case ixgbe_mac_X540:
793 case ixgbe_mac_X550:
794 case ixgbe_mac_X550EM_x:
795 case ixgbe_mac_x550em_a:
796 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
797 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
798 for (i = 0; i < 8; i++)
799 regs_buff[833 + i] =
800 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
801 for (i = 0; i < 8; i++)
802 regs_buff[841 + i] =
803 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
804 for (i = 0; i < 8; i++)
805 regs_buff[849 + i] =
806 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
807 for (i = 0; i < 8; i++)
808 regs_buff[857 + i] =
809 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
810 break;
811 default:
812 break;
813 }
814
815 for (i = 0; i < 8; i++)
816 regs_buff[865 + i] =
817 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
818 for (i = 0; i < 8; i++)
819 regs_buff[873 + i] =
820 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
821
822 /* Statistics */
823 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
824 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
825 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
826 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
827 for (i = 0; i < 8; i++)
828 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
829 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
830 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
831 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
832 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
833 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
834 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
835 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
836 for (i = 0; i < 8; i++)
837 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
838 for (i = 0; i < 8; i++)
839 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
840 for (i = 0; i < 8; i++)
841 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
842 for (i = 0; i < 8; i++)
843 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
844 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
845 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
846 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
847 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
848 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
849 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
850 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
851 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
852 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
853 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
854 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
855 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
856 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
857 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
858 for (i = 0; i < 8; i++)
859 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
860 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
861 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
862 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
863 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
864 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
865 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
866 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
867 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
868 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
869 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
870 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
871 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
872 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
873 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
874 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
875 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
876 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
877 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
878 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
879 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
880 for (i = 0; i < 16; i++)
881 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
882 for (i = 0; i < 16; i++)
883 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
884 for (i = 0; i < 16; i++)
885 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
886 for (i = 0; i < 16; i++)
887 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
888
889 /* MAC */
890 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
891 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
892 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
893 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
894 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
895 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
896 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
897 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
898 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
899 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
900 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
901 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
902 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
903 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
904 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
905 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
906 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
907 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
908 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
909 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
910 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
911 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
912 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
913 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
914 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
915 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
916 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
917 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
918 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
919 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
920 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
921 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
922 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
923
924 /* Diagnostic */
925 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
926 for (i = 0; i < 8; i++)
927 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
928 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
929 for (i = 0; i < 4; i++)
930 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
931 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
932 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
933 for (i = 0; i < 8; i++)
934 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
935 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
936 for (i = 0; i < 4; i++)
937 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
938 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
939 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
940 for (i = 0; i < 4; i++)
941 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
942 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
943 for (i = 0; i < 4; i++)
944 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
945 for (i = 0; i < 8; i++)
946 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
947 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
948 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
949 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
950 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
951 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
952 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
953 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
954 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
955 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
956
957 /* 82599 X540 specific registers */
958 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
959
960 /* 82599 X540 specific DCB registers */
961 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
962 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
963 for (i = 0; i < 4; i++)
964 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
965 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
966 /* same as RTTQCNRM */
967 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
968 /* same as RTTQCNRR */
969
970 /* X540 specific DCB registers */
971 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
972 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
973
974 /* Security config registers */
975 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
976 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
977 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF);
978 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
979 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
980 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
981}
982
983static int ixgbe_get_eeprom_len(struct net_device *netdev)
984{
985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
986 return adapter->hw.eeprom.word_size * 2;
987}
988
989static int ixgbe_get_eeprom(struct net_device *netdev,
990 struct ethtool_eeprom *eeprom, u8 *bytes)
991{
992 struct ixgbe_adapter *adapter = netdev_priv(netdev);
993 struct ixgbe_hw *hw = &adapter->hw;
994 u16 *eeprom_buff;
995 int first_word, last_word, eeprom_len;
996 int ret_val = 0;
997 u16 i;
998
999 if (eeprom->len == 0)
1000 return -EINVAL;
1001
1002 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1003
1004 first_word = eeprom->offset >> 1;
1005 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1006 eeprom_len = last_word - first_word + 1;
1007
1008 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL);
1009 if (!eeprom_buff)
1010 return -ENOMEM;
1011
1012 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
1013 eeprom_buff);
1014
1015 /* Device's eeprom is always little-endian, word addressable */
1016 for (i = 0; i < eeprom_len; i++)
1017 le16_to_cpus(&eeprom_buff[i]);
1018
1019 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
1020 kfree(eeprom_buff);
1021
1022 return ret_val;
1023}
1024
1025static int ixgbe_set_eeprom(struct net_device *netdev,
1026 struct ethtool_eeprom *eeprom, u8 *bytes)
1027{
1028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1029 struct ixgbe_hw *hw = &adapter->hw;
1030 u16 *eeprom_buff;
1031 void *ptr;
1032 int max_len, first_word, last_word, ret_val = 0;
1033 u16 i;
1034
1035 if (eeprom->len == 0)
1036 return -EINVAL;
1037
1038 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1039 return -EINVAL;
1040
1041 max_len = hw->eeprom.word_size * 2;
1042
1043 first_word = eeprom->offset >> 1;
1044 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1045 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1046 if (!eeprom_buff)
1047 return -ENOMEM;
1048
1049 ptr = eeprom_buff;
1050
1051 if (eeprom->offset & 1) {
1052 /*
1053 * need read/modify/write of first changed EEPROM word
1054 * only the second byte of the word is being modified
1055 */
1056 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
1057 if (ret_val)
1058 goto err;
1059
1060 ptr++;
1061 }
1062 if ((eeprom->offset + eeprom->len) & 1) {
1063 /*
1064 * need read/modify/write of last changed EEPROM word
1065 * only the first byte of the word is being modified
1066 */
1067 ret_val = hw->eeprom.ops.read(hw, last_word,
1068 &eeprom_buff[last_word - first_word]);
1069 if (ret_val)
1070 goto err;
1071 }
1072
1073 /* Device's eeprom is always little-endian, word addressable */
1074 for (i = 0; i < last_word - first_word + 1; i++)
1075 le16_to_cpus(&eeprom_buff[i]);
1076
1077 memcpy(ptr, bytes, eeprom->len);
1078
1079 for (i = 0; i < last_word - first_word + 1; i++)
1080 cpu_to_le16s(&eeprom_buff[i]);
1081
1082 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
1083 last_word - first_word + 1,
1084 eeprom_buff);
1085
1086 /* Update the checksum */
1087 if (ret_val == 0)
1088 hw->eeprom.ops.update_checksum(hw);
1089
1090err:
1091 kfree(eeprom_buff);
1092 return ret_val;
1093}
1094
1095static void ixgbe_get_drvinfo(struct net_device *netdev,
1096 struct ethtool_drvinfo *drvinfo)
1097{
1098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1099
1100 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
1101
1102 strlcpy(drvinfo->fw_version, adapter->eeprom_id,
1103 sizeof(drvinfo->fw_version));
1104
1105 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
1106 sizeof(drvinfo->bus_info));
1107
1108 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN;
1109}
1110
1111static void ixgbe_get_ringparam(struct net_device *netdev,
1112 struct ethtool_ringparam *ring)
1113{
1114 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1115 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1116 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1117
1118 ring->rx_max_pending = IXGBE_MAX_RXD;
1119 ring->tx_max_pending = IXGBE_MAX_TXD;
1120 ring->rx_pending = rx_ring->count;
1121 ring->tx_pending = tx_ring->count;
1122}
1123
1124static int ixgbe_set_ringparam(struct net_device *netdev,
1125 struct ethtool_ringparam *ring)
1126{
1127 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1128 struct ixgbe_ring *temp_ring;
1129 int i, j, err = 0;
1130 u32 new_rx_count, new_tx_count;
1131
1132 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1133 return -EINVAL;
1134
1135 new_tx_count = clamp_t(u32, ring->tx_pending,
1136 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
1137 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1138
1139 new_rx_count = clamp_t(u32, ring->rx_pending,
1140 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
1141 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1142
1143 if ((new_tx_count == adapter->tx_ring_count) &&
1144 (new_rx_count == adapter->rx_ring_count)) {
1145 /* nothing to do */
1146 return 0;
1147 }
1148
1149 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1150 usleep_range(1000, 2000);
1151
1152 if (!netif_running(adapter->netdev)) {
1153 for (i = 0; i < adapter->num_tx_queues; i++)
1154 adapter->tx_ring[i]->count = new_tx_count;
1155 for (i = 0; i < adapter->num_xdp_queues; i++)
1156 adapter->xdp_ring[i]->count = new_tx_count;
1157 for (i = 0; i < adapter->num_rx_queues; i++)
1158 adapter->rx_ring[i]->count = new_rx_count;
1159 adapter->tx_ring_count = new_tx_count;
1160 adapter->xdp_ring_count = new_tx_count;
1161 adapter->rx_ring_count = new_rx_count;
1162 goto clear_reset;
1163 }
1164
1165 /* allocate temporary buffer to store rings in */
1166 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues,
1167 adapter->num_rx_queues);
1168 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring)));
1169
1170 if (!temp_ring) {
1171 err = -ENOMEM;
1172 goto clear_reset;
1173 }
1174
1175 ixgbe_down(adapter);
1176
1177 /*
1178 * Setup new Tx resources and free the old Tx resources in that order.
1179 * We can then assign the new resources to the rings via a memcpy.
1180 * The advantage to this approach is that we are guaranteed to still
1181 * have resources even in the case of an allocation failure.
1182 */
1183 if (new_tx_count != adapter->tx_ring_count) {
1184 for (i = 0; i < adapter->num_tx_queues; i++) {
1185 memcpy(&temp_ring[i], adapter->tx_ring[i],
1186 sizeof(struct ixgbe_ring));
1187
1188 temp_ring[i].count = new_tx_count;
1189 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1190 if (err) {
1191 while (i) {
1192 i--;
1193 ixgbe_free_tx_resources(&temp_ring[i]);
1194 }
1195 goto err_setup;
1196 }
1197 }
1198
1199 for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1200 memcpy(&temp_ring[i], adapter->xdp_ring[j],
1201 sizeof(struct ixgbe_ring));
1202
1203 temp_ring[i].count = new_tx_count;
1204 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1205 if (err) {
1206 while (i) {
1207 i--;
1208 ixgbe_free_tx_resources(&temp_ring[i]);
1209 }
1210 goto err_setup;
1211 }
1212 }
1213
1214 for (i = 0; i < adapter->num_tx_queues; i++) {
1215 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1216
1217 memcpy(adapter->tx_ring[i], &temp_ring[i],
1218 sizeof(struct ixgbe_ring));
1219 }
1220 for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1221 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
1222
1223 memcpy(adapter->xdp_ring[j], &temp_ring[i],
1224 sizeof(struct ixgbe_ring));
1225 }
1226
1227 adapter->tx_ring_count = new_tx_count;
1228 }
1229
1230 /* Repeat the process for the Rx rings if needed */
1231 if (new_rx_count != adapter->rx_ring_count) {
1232 for (i = 0; i < adapter->num_rx_queues; i++) {
1233 memcpy(&temp_ring[i], adapter->rx_ring[i],
1234 sizeof(struct ixgbe_ring));
1235
1236 /* Clear copied XDP RX-queue info */
1237 memset(&temp_ring[i].xdp_rxq, 0,
1238 sizeof(temp_ring[i].xdp_rxq));
1239
1240 temp_ring[i].count = new_rx_count;
1241 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]);
1242 if (err) {
1243 while (i) {
1244 i--;
1245 ixgbe_free_rx_resources(&temp_ring[i]);
1246 }
1247 goto err_setup;
1248 }
1249
1250 }
1251
1252 for (i = 0; i < adapter->num_rx_queues; i++) {
1253 ixgbe_free_rx_resources(adapter->rx_ring[i]);
1254
1255 memcpy(adapter->rx_ring[i], &temp_ring[i],
1256 sizeof(struct ixgbe_ring));
1257 }
1258
1259 adapter->rx_ring_count = new_rx_count;
1260 }
1261
1262err_setup:
1263 ixgbe_up(adapter);
1264 vfree(temp_ring);
1265clear_reset:
1266 clear_bit(__IXGBE_RESETTING, &adapter->state);
1267 return err;
1268}
1269
1270static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1271{
1272 switch (sset) {
1273 case ETH_SS_TEST:
1274 return IXGBE_TEST_LEN;
1275 case ETH_SS_STATS:
1276 return IXGBE_STATS_LEN;
1277 case ETH_SS_PRIV_FLAGS:
1278 return IXGBE_PRIV_FLAGS_STR_LEN;
1279 default:
1280 return -EOPNOTSUPP;
1281 }
1282}
1283
1284static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1285 struct ethtool_stats *stats, u64 *data)
1286{
1287 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1288 struct rtnl_link_stats64 temp;
1289 const struct rtnl_link_stats64 *net_stats;
1290 unsigned int start;
1291 struct ixgbe_ring *ring;
1292 int i, j;
1293 char *p = NULL;
1294
1295 ixgbe_update_stats(adapter);
1296 net_stats = dev_get_stats(netdev, &temp);
1297 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1298 switch (ixgbe_gstrings_stats[i].type) {
1299 case NETDEV_STATS:
1300 p = (char *) net_stats +
1301 ixgbe_gstrings_stats[i].stat_offset;
1302 break;
1303 case IXGBE_STATS:
1304 p = (char *) adapter +
1305 ixgbe_gstrings_stats[i].stat_offset;
1306 break;
1307 default:
1308 data[i] = 0;
1309 continue;
1310 }
1311
1312 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1313 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1314 }
1315 for (j = 0; j < netdev->num_tx_queues; j++) {
1316 ring = adapter->tx_ring[j];
1317 if (!ring) {
1318 data[i] = 0;
1319 data[i+1] = 0;
1320 i += 2;
1321 continue;
1322 }
1323
1324 do {
1325 start = u64_stats_fetch_begin_irq(&ring->syncp);
1326 data[i] = ring->stats.packets;
1327 data[i+1] = ring->stats.bytes;
1328 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1329 i += 2;
1330 }
1331 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1332 ring = adapter->rx_ring[j];
1333 if (!ring) {
1334 data[i] = 0;
1335 data[i+1] = 0;
1336 i += 2;
1337 continue;
1338 }
1339
1340 do {
1341 start = u64_stats_fetch_begin_irq(&ring->syncp);
1342 data[i] = ring->stats.packets;
1343 data[i+1] = ring->stats.bytes;
1344 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1345 i += 2;
1346 }
1347
1348 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1349 data[i++] = adapter->stats.pxontxc[j];
1350 data[i++] = adapter->stats.pxofftxc[j];
1351 }
1352 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1353 data[i++] = adapter->stats.pxonrxc[j];
1354 data[i++] = adapter->stats.pxoffrxc[j];
1355 }
1356}
1357
1358static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1359 u8 *data)
1360{
1361 char *p = (char *)data;
1362 unsigned int i;
1363
1364 switch (stringset) {
1365 case ETH_SS_TEST:
1366 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1367 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1368 data += ETH_GSTRING_LEN;
1369 }
1370 break;
1371 case ETH_SS_STATS:
1372 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1373 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1374 ETH_GSTRING_LEN);
1375 p += ETH_GSTRING_LEN;
1376 }
1377 for (i = 0; i < netdev->num_tx_queues; i++) {
1378 sprintf(p, "tx_queue_%u_packets", i);
1379 p += ETH_GSTRING_LEN;
1380 sprintf(p, "tx_queue_%u_bytes", i);
1381 p += ETH_GSTRING_LEN;
1382 }
1383 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1384 sprintf(p, "rx_queue_%u_packets", i);
1385 p += ETH_GSTRING_LEN;
1386 sprintf(p, "rx_queue_%u_bytes", i);
1387 p += ETH_GSTRING_LEN;
1388 }
1389 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1390 sprintf(p, "tx_pb_%u_pxon", i);
1391 p += ETH_GSTRING_LEN;
1392 sprintf(p, "tx_pb_%u_pxoff", i);
1393 p += ETH_GSTRING_LEN;
1394 }
1395 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1396 sprintf(p, "rx_pb_%u_pxon", i);
1397 p += ETH_GSTRING_LEN;
1398 sprintf(p, "rx_pb_%u_pxoff", i);
1399 p += ETH_GSTRING_LEN;
1400 }
1401 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1402 break;
1403 case ETH_SS_PRIV_FLAGS:
1404 memcpy(data, ixgbe_priv_flags_strings,
1405 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
1406 }
1407}
1408
1409static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1410{
1411 struct ixgbe_hw *hw = &adapter->hw;
1412 bool link_up;
1413 u32 link_speed = 0;
1414
1415 if (ixgbe_removed(hw->hw_addr)) {
1416 *data = 1;
1417 return 1;
1418 }
1419 *data = 0;
1420
1421 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1422 if (link_up)
1423 return *data;
1424 else
1425 *data = 1;
1426 return *data;
1427}
1428
1429/* ethtool register test data */
1430struct ixgbe_reg_test {
1431 u16 reg;
1432 u8 array_len;
1433 u8 test_type;
1434 u32 mask;
1435 u32 write;
1436};
1437
1438/* In the hardware, registers are laid out either singly, in arrays
1439 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1440 * most tests take place on arrays or single registers (handled
1441 * as a single-element array) and special-case the tables.
1442 * Table tests are always pattern tests.
1443 *
1444 * We also make provision for some required setup steps by specifying
1445 * registers to be written without any read-back testing.
1446 */
1447
1448#define PATTERN_TEST 1
1449#define SET_READ_TEST 2
1450#define WRITE_NO_TEST 3
1451#define TABLE32_TEST 4
1452#define TABLE64_TEST_LO 5
1453#define TABLE64_TEST_HI 6
1454
1455/* default 82599 register test */
1456static const struct ixgbe_reg_test reg_test_82599[] = {
1457 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1458 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1459 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1460 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1461 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1462 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1463 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1464 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1465 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1466 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1467 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1468 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1469 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1470 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1471 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1472 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1473 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1474 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1475 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1476 { .reg = 0 }
1477};
1478
1479/* default 82598 register test */
1480static const struct ixgbe_reg_test reg_test_82598[] = {
1481 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1482 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1483 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1484 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1485 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1486 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1487 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1488 /* Enable all four RX queues before testing. */
1489 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1490 /* RDH is read-only for 82598, only test RDT. */
1491 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1492 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1493 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1494 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1495 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1496 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1497 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1498 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1499 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1500 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1501 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1502 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1503 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1504 { .reg = 0 }
1505};
1506
1507static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1508 u32 mask, u32 write)
1509{
1510 u32 pat, val, before;
1511 static const u32 test_pattern[] = {
1512 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1513
1514 if (ixgbe_removed(adapter->hw.hw_addr)) {
1515 *data = 1;
1516 return true;
1517 }
1518 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1519 before = ixgbe_read_reg(&adapter->hw, reg);
1520 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1521 val = ixgbe_read_reg(&adapter->hw, reg);
1522 if (val != (test_pattern[pat] & write & mask)) {
1523 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1524 reg, val, (test_pattern[pat] & write & mask));
1525 *data = reg;
1526 ixgbe_write_reg(&adapter->hw, reg, before);
1527 return true;
1528 }
1529 ixgbe_write_reg(&adapter->hw, reg, before);
1530 }
1531 return false;
1532}
1533
1534static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1535 u32 mask, u32 write)
1536{
1537 u32 val, before;
1538
1539 if (ixgbe_removed(adapter->hw.hw_addr)) {
1540 *data = 1;
1541 return true;
1542 }
1543 before = ixgbe_read_reg(&adapter->hw, reg);
1544 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1545 val = ixgbe_read_reg(&adapter->hw, reg);
1546 if ((write & mask) != (val & mask)) {
1547 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1548 reg, (val & mask), (write & mask));
1549 *data = reg;
1550 ixgbe_write_reg(&adapter->hw, reg, before);
1551 return true;
1552 }
1553 ixgbe_write_reg(&adapter->hw, reg, before);
1554 return false;
1555}
1556
1557static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1558{
1559 const struct ixgbe_reg_test *test;
1560 u32 value, before, after;
1561 u32 i, toggle;
1562
1563 if (ixgbe_removed(adapter->hw.hw_addr)) {
1564 e_err(drv, "Adapter removed - register test blocked\n");
1565 *data = 1;
1566 return 1;
1567 }
1568 switch (adapter->hw.mac.type) {
1569 case ixgbe_mac_82598EB:
1570 toggle = 0x7FFFF3FF;
1571 test = reg_test_82598;
1572 break;
1573 case ixgbe_mac_82599EB:
1574 case ixgbe_mac_X540:
1575 case ixgbe_mac_X550:
1576 case ixgbe_mac_X550EM_x:
1577 case ixgbe_mac_x550em_a:
1578 toggle = 0x7FFFF30F;
1579 test = reg_test_82599;
1580 break;
1581 default:
1582 *data = 1;
1583 return 1;
1584 }
1585
1586 /*
1587 * Because the status register is such a special case,
1588 * we handle it separately from the rest of the register
1589 * tests. Some bits are read-only, some toggle, and some
1590 * are writeable on newer MACs.
1591 */
1592 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1593 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1594 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1595 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1596 if (value != after) {
1597 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1598 after, value);
1599 *data = 1;
1600 return 1;
1601 }
1602 /* restore previous status */
1603 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1604
1605 /*
1606 * Perform the remainder of the register test, looping through
1607 * the test table until we either fail or reach the null entry.
1608 */
1609 while (test->reg) {
1610 for (i = 0; i < test->array_len; i++) {
1611 bool b = false;
1612
1613 switch (test->test_type) {
1614 case PATTERN_TEST:
1615 b = reg_pattern_test(adapter, data,
1616 test->reg + (i * 0x40),
1617 test->mask,
1618 test->write);
1619 break;
1620 case SET_READ_TEST:
1621 b = reg_set_and_check(adapter, data,
1622 test->reg + (i * 0x40),
1623 test->mask,
1624 test->write);
1625 break;
1626 case WRITE_NO_TEST:
1627 ixgbe_write_reg(&adapter->hw,
1628 test->reg + (i * 0x40),
1629 test->write);
1630 break;
1631 case TABLE32_TEST:
1632 b = reg_pattern_test(adapter, data,
1633 test->reg + (i * 4),
1634 test->mask,
1635 test->write);
1636 break;
1637 case TABLE64_TEST_LO:
1638 b = reg_pattern_test(adapter, data,
1639 test->reg + (i * 8),
1640 test->mask,
1641 test->write);
1642 break;
1643 case TABLE64_TEST_HI:
1644 b = reg_pattern_test(adapter, data,
1645 (test->reg + 4) + (i * 8),
1646 test->mask,
1647 test->write);
1648 break;
1649 }
1650 if (b)
1651 return 1;
1652 }
1653 test++;
1654 }
1655
1656 *data = 0;
1657 return 0;
1658}
1659
1660static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1661{
1662 struct ixgbe_hw *hw = &adapter->hw;
1663 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1664 *data = 1;
1665 else
1666 *data = 0;
1667 return *data;
1668}
1669
1670static irqreturn_t ixgbe_test_intr(int irq, void *data)
1671{
1672 struct net_device *netdev = (struct net_device *) data;
1673 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1674
1675 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1676
1677 return IRQ_HANDLED;
1678}
1679
1680static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1681{
1682 struct net_device *netdev = adapter->netdev;
1683 u32 mask, i = 0, shared_int = true;
1684 u32 irq = adapter->pdev->irq;
1685
1686 *data = 0;
1687
1688 /* Hook up test interrupt handler just for this test */
1689 if (adapter->msix_entries) {
1690 /* NOTE: we don't test MSI-X interrupts here, yet */
1691 return 0;
1692 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1693 shared_int = false;
1694 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1695 netdev)) {
1696 *data = 1;
1697 return -1;
1698 }
1699 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1700 netdev->name, netdev)) {
1701 shared_int = false;
1702 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1703 netdev->name, netdev)) {
1704 *data = 1;
1705 return -1;
1706 }
1707 e_info(hw, "testing %s interrupt\n", shared_int ?
1708 "shared" : "unshared");
1709
1710 /* Disable all the interrupts */
1711 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1712 IXGBE_WRITE_FLUSH(&adapter->hw);
1713 usleep_range(10000, 20000);
1714
1715 /* Test each interrupt */
1716 for (; i < 10; i++) {
1717 /* Interrupt to test */
1718 mask = BIT(i);
1719
1720 if (!shared_int) {
1721 /*
1722 * Disable the interrupts to be reported in
1723 * the cause register and then force the same
1724 * interrupt and see if one gets posted. If
1725 * an interrupt was posted to the bus, the
1726 * test failed.
1727 */
1728 adapter->test_icr = 0;
1729 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1730 ~mask & 0x00007FFF);
1731 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1732 ~mask & 0x00007FFF);
1733 IXGBE_WRITE_FLUSH(&adapter->hw);
1734 usleep_range(10000, 20000);
1735
1736 if (adapter->test_icr & mask) {
1737 *data = 3;
1738 break;
1739 }
1740 }
1741
1742 /*
1743 * Enable the interrupt to be reported in the cause
1744 * register and then force the same interrupt and see
1745 * if one gets posted. If an interrupt was not posted
1746 * to the bus, the test failed.
1747 */
1748 adapter->test_icr = 0;
1749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1750 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1751 IXGBE_WRITE_FLUSH(&adapter->hw);
1752 usleep_range(10000, 20000);
1753
1754 if (!(adapter->test_icr & mask)) {
1755 *data = 4;
1756 break;
1757 }
1758
1759 if (!shared_int) {
1760 /*
1761 * Disable the other interrupts to be reported in
1762 * the cause register and then force the other
1763 * interrupts and see if any get posted. If
1764 * an interrupt was posted to the bus, the
1765 * test failed.
1766 */
1767 adapter->test_icr = 0;
1768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1769 ~mask & 0x00007FFF);
1770 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1771 ~mask & 0x00007FFF);
1772 IXGBE_WRITE_FLUSH(&adapter->hw);
1773 usleep_range(10000, 20000);
1774
1775 if (adapter->test_icr) {
1776 *data = 5;
1777 break;
1778 }
1779 }
1780 }
1781
1782 /* Disable all the interrupts */
1783 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1784 IXGBE_WRITE_FLUSH(&adapter->hw);
1785 usleep_range(10000, 20000);
1786
1787 /* Unhook test interrupt handler */
1788 free_irq(irq, netdev);
1789
1790 return *data;
1791}
1792
1793static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1794{
1795 /* Shut down the DMA engines now so they can be reinitialized later,
1796 * since the test rings and normally used rings should overlap on
1797 * queue 0 we can just use the standard disable Rx/Tx calls and they
1798 * will take care of disabling the test rings for us.
1799 */
1800
1801 /* first Rx */
1802 ixgbe_disable_rx(adapter);
1803
1804 /* now Tx */
1805 ixgbe_disable_tx(adapter);
1806
1807 ixgbe_reset(adapter);
1808
1809 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1810 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1811}
1812
1813static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1814{
1815 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1816 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1817 struct ixgbe_hw *hw = &adapter->hw;
1818 u32 rctl, reg_data;
1819 int ret_val;
1820 int err;
1821
1822 /* Setup Tx descriptor ring and Tx buffers */
1823 tx_ring->count = IXGBE_DEFAULT_TXD;
1824 tx_ring->queue_index = 0;
1825 tx_ring->dev = &adapter->pdev->dev;
1826 tx_ring->netdev = adapter->netdev;
1827 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1828
1829 err = ixgbe_setup_tx_resources(tx_ring);
1830 if (err)
1831 return 1;
1832
1833 switch (adapter->hw.mac.type) {
1834 case ixgbe_mac_82599EB:
1835 case ixgbe_mac_X540:
1836 case ixgbe_mac_X550:
1837 case ixgbe_mac_X550EM_x:
1838 case ixgbe_mac_x550em_a:
1839 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1840 reg_data |= IXGBE_DMATXCTL_TE;
1841 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1842 break;
1843 default:
1844 break;
1845 }
1846
1847 ixgbe_configure_tx_ring(adapter, tx_ring);
1848
1849 /* Setup Rx Descriptor ring and Rx buffers */
1850 rx_ring->count = IXGBE_DEFAULT_RXD;
1851 rx_ring->queue_index = 0;
1852 rx_ring->dev = &adapter->pdev->dev;
1853 rx_ring->netdev = adapter->netdev;
1854 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1855
1856 err = ixgbe_setup_rx_resources(adapter, rx_ring);
1857 if (err) {
1858 ret_val = 4;
1859 goto err_nomem;
1860 }
1861
1862 hw->mac.ops.disable_rx(hw);
1863
1864 ixgbe_configure_rx_ring(adapter, rx_ring);
1865
1866 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1867 rctl |= IXGBE_RXCTRL_DMBYPS;
1868 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1869
1870 hw->mac.ops.enable_rx(hw);
1871
1872 return 0;
1873
1874err_nomem:
1875 ixgbe_free_desc_rings(adapter);
1876 return ret_val;
1877}
1878
1879static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1880{
1881 struct ixgbe_hw *hw = &adapter->hw;
1882 u32 reg_data;
1883
1884
1885 /* Setup MAC loopback */
1886 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1887 reg_data |= IXGBE_HLREG0_LPBK;
1888 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1889
1890 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1891 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1892 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1893
1894 /* X540 and X550 needs to set the MACC.FLU bit to force link up */
1895 switch (adapter->hw.mac.type) {
1896 case ixgbe_mac_X540:
1897 case ixgbe_mac_X550:
1898 case ixgbe_mac_X550EM_x:
1899 case ixgbe_mac_x550em_a:
1900 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1901 reg_data |= IXGBE_MACC_FLU;
1902 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1903 break;
1904 default:
1905 if (hw->mac.orig_autoc) {
1906 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1907 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1908 } else {
1909 return 10;
1910 }
1911 }
1912 IXGBE_WRITE_FLUSH(hw);
1913 usleep_range(10000, 20000);
1914
1915 /* Disable Atlas Tx lanes; re-enabled in reset path */
1916 if (hw->mac.type == ixgbe_mac_82598EB) {
1917 u8 atlas;
1918
1919 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1920 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1921 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1922
1923 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1924 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1925 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1926
1927 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1928 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1929 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1930
1931 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1932 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1933 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1934 }
1935
1936 return 0;
1937}
1938
1939static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1940{
1941 u32 reg_data;
1942
1943 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1944 reg_data &= ~IXGBE_HLREG0_LPBK;
1945 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1946}
1947
1948static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1949 unsigned int frame_size)
1950{
1951 memset(skb->data, 0xFF, frame_size);
1952 frame_size >>= 1;
1953 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1954 skb->data[frame_size + 10] = 0xBE;
1955 skb->data[frame_size + 12] = 0xAF;
1956}
1957
1958static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1959 unsigned int frame_size)
1960{
1961 unsigned char *data;
1962 bool match = true;
1963
1964 frame_size >>= 1;
1965
1966 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1967
1968 if (data[3] != 0xFF ||
1969 data[frame_size + 10] != 0xBE ||
1970 data[frame_size + 12] != 0xAF)
1971 match = false;
1972
1973 kunmap(rx_buffer->page);
1974
1975 return match;
1976}
1977
1978static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1979 struct ixgbe_ring *tx_ring,
1980 unsigned int size)
1981{
1982 union ixgbe_adv_rx_desc *rx_desc;
1983 u16 rx_ntc, tx_ntc, count = 0;
1984
1985 /* initialize next to clean and descriptor values */
1986 rx_ntc = rx_ring->next_to_clean;
1987 tx_ntc = tx_ring->next_to_clean;
1988 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1989
1990 while (tx_ntc != tx_ring->next_to_use) {
1991 union ixgbe_adv_tx_desc *tx_desc;
1992 struct ixgbe_tx_buffer *tx_buffer;
1993
1994 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc);
1995
1996 /* if DD is not set transmit has not completed */
1997 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1998 return count;
1999
2000 /* unmap buffer on Tx side */
2001 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
2002
2003 /* Free all the Tx ring sk_buffs */
2004 dev_kfree_skb_any(tx_buffer->skb);
2005
2006 /* unmap skb header data */
2007 dma_unmap_single(tx_ring->dev,
2008 dma_unmap_addr(tx_buffer, dma),
2009 dma_unmap_len(tx_buffer, len),
2010 DMA_TO_DEVICE);
2011 dma_unmap_len_set(tx_buffer, len, 0);
2012
2013 /* increment Tx next to clean counter */
2014 tx_ntc++;
2015 if (tx_ntc == tx_ring->count)
2016 tx_ntc = 0;
2017 }
2018
2019 while (rx_desc->wb.upper.length) {
2020 struct ixgbe_rx_buffer *rx_buffer;
2021
2022 /* check Rx buffer */
2023 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
2024
2025 /* sync Rx buffer for CPU read */
2026 dma_sync_single_for_cpu(rx_ring->dev,
2027 rx_buffer->dma,
2028 ixgbe_rx_bufsz(rx_ring),
2029 DMA_FROM_DEVICE);
2030
2031 /* verify contents of skb */
2032 if (ixgbe_check_lbtest_frame(rx_buffer, size))
2033 count++;
2034 else
2035 break;
2036
2037 /* sync Rx buffer for device write */
2038 dma_sync_single_for_device(rx_ring->dev,
2039 rx_buffer->dma,
2040 ixgbe_rx_bufsz(rx_ring),
2041 DMA_FROM_DEVICE);
2042
2043 /* increment Rx next to clean counter */
2044 rx_ntc++;
2045 if (rx_ntc == rx_ring->count)
2046 rx_ntc = 0;
2047
2048 /* fetch next descriptor */
2049 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
2050 }
2051
2052 netdev_tx_reset_queue(txring_txq(tx_ring));
2053
2054 /* re-map buffers to ring, store next to clean values */
2055 ixgbe_alloc_rx_buffers(rx_ring, count);
2056 rx_ring->next_to_clean = rx_ntc;
2057 tx_ring->next_to_clean = tx_ntc;
2058
2059 return count;
2060}
2061
2062static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
2063{
2064 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
2065 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
2066 int i, j, lc, good_cnt, ret_val = 0;
2067 unsigned int size = 1024;
2068 netdev_tx_t tx_ret_val;
2069 struct sk_buff *skb;
2070 u32 flags_orig = adapter->flags;
2071
2072 /* DCB can modify the frames on Tx */
2073 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2074
2075 /* allocate test skb */
2076 skb = alloc_skb(size, GFP_KERNEL);
2077 if (!skb)
2078 return 11;
2079
2080 /* place data into test skb */
2081 ixgbe_create_lbtest_frame(skb, size);
2082 skb_put(skb, size);
2083
2084 /*
2085 * Calculate the loop count based on the largest descriptor ring
2086 * The idea is to wrap the largest ring a number of times using 64
2087 * send/receive pairs during each loop
2088 */
2089
2090 if (rx_ring->count <= tx_ring->count)
2091 lc = ((tx_ring->count / 64) * 2) + 1;
2092 else
2093 lc = ((rx_ring->count / 64) * 2) + 1;
2094
2095 for (j = 0; j <= lc; j++) {
2096 /* reset count of good packets */
2097 good_cnt = 0;
2098
2099 /* place 64 packets on the transmit queue*/
2100 for (i = 0; i < 64; i++) {
2101 skb_get(skb);
2102 tx_ret_val = ixgbe_xmit_frame_ring(skb,
2103 adapter,
2104 tx_ring);
2105 if (tx_ret_val == NETDEV_TX_OK)
2106 good_cnt++;
2107 }
2108
2109 if (good_cnt != 64) {
2110 ret_val = 12;
2111 break;
2112 }
2113
2114 /* allow 200 milliseconds for packets to go from Tx to Rx */
2115 msleep(200);
2116
2117 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
2118 if (good_cnt != 64) {
2119 ret_val = 13;
2120 break;
2121 }
2122 }
2123
2124 /* free the original skb */
2125 kfree_skb(skb);
2126 adapter->flags = flags_orig;
2127
2128 return ret_val;
2129}
2130
2131static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
2132{
2133 *data = ixgbe_setup_desc_rings(adapter);
2134 if (*data)
2135 goto out;
2136 *data = ixgbe_setup_loopback_test(adapter);
2137 if (*data)
2138 goto err_loopback;
2139 *data = ixgbe_run_loopback_test(adapter);
2140 ixgbe_loopback_cleanup(adapter);
2141
2142err_loopback:
2143 ixgbe_free_desc_rings(adapter);
2144out:
2145 return *data;
2146}
2147
2148static void ixgbe_diag_test(struct net_device *netdev,
2149 struct ethtool_test *eth_test, u64 *data)
2150{
2151 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2152 bool if_running = netif_running(netdev);
2153
2154 if (ixgbe_removed(adapter->hw.hw_addr)) {
2155 e_err(hw, "Adapter removed - test blocked\n");
2156 data[0] = 1;
2157 data[1] = 1;
2158 data[2] = 1;
2159 data[3] = 1;
2160 data[4] = 1;
2161 eth_test->flags |= ETH_TEST_FL_FAILED;
2162 return;
2163 }
2164 set_bit(__IXGBE_TESTING, &adapter->state);
2165 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2166 struct ixgbe_hw *hw = &adapter->hw;
2167
2168 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2169 int i;
2170 for (i = 0; i < adapter->num_vfs; i++) {
2171 if (adapter->vfinfo[i].clear_to_send) {
2172 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
2173 data[0] = 1;
2174 data[1] = 1;
2175 data[2] = 1;
2176 data[3] = 1;
2177 data[4] = 1;
2178 eth_test->flags |= ETH_TEST_FL_FAILED;
2179 clear_bit(__IXGBE_TESTING,
2180 &adapter->state);
2181 return;
2182 }
2183 }
2184 }
2185
2186 /* Offline tests */
2187 e_info(hw, "offline testing starting\n");
2188
2189 /* Link test performed before hardware reset so autoneg doesn't
2190 * interfere with test result
2191 */
2192 if (ixgbe_link_test(adapter, &data[4]))
2193 eth_test->flags |= ETH_TEST_FL_FAILED;
2194
2195 if (if_running)
2196 /* indicate we're in test mode */
2197 ixgbe_close(netdev);
2198 else
2199 ixgbe_reset(adapter);
2200
2201 e_info(hw, "register testing starting\n");
2202 if (ixgbe_reg_test(adapter, &data[0]))
2203 eth_test->flags |= ETH_TEST_FL_FAILED;
2204
2205 ixgbe_reset(adapter);
2206 e_info(hw, "eeprom testing starting\n");
2207 if (ixgbe_eeprom_test(adapter, &data[1]))
2208 eth_test->flags |= ETH_TEST_FL_FAILED;
2209
2210 ixgbe_reset(adapter);
2211 e_info(hw, "interrupt testing starting\n");
2212 if (ixgbe_intr_test(adapter, &data[2]))
2213 eth_test->flags |= ETH_TEST_FL_FAILED;
2214
2215 /* If SRIOV or VMDq is enabled then skip MAC
2216 * loopback diagnostic. */
2217 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2218 IXGBE_FLAG_VMDQ_ENABLED)) {
2219 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2220 data[3] = 0;
2221 goto skip_loopback;
2222 }
2223
2224 ixgbe_reset(adapter);
2225 e_info(hw, "loopback testing starting\n");
2226 if (ixgbe_loopback_test(adapter, &data[3]))
2227 eth_test->flags |= ETH_TEST_FL_FAILED;
2228
2229skip_loopback:
2230 ixgbe_reset(adapter);
2231
2232 /* clear testing bit and return adapter to previous state */
2233 clear_bit(__IXGBE_TESTING, &adapter->state);
2234 if (if_running)
2235 ixgbe_open(netdev);
2236 else if (hw->mac.ops.disable_tx_laser)
2237 hw->mac.ops.disable_tx_laser(hw);
2238 } else {
2239 e_info(hw, "online testing starting\n");
2240
2241 /* Online tests */
2242 if (ixgbe_link_test(adapter, &data[4]))
2243 eth_test->flags |= ETH_TEST_FL_FAILED;
2244
2245 /* Offline tests aren't run; pass by default */
2246 data[0] = 0;
2247 data[1] = 0;
2248 data[2] = 0;
2249 data[3] = 0;
2250
2251 clear_bit(__IXGBE_TESTING, &adapter->state);
2252 }
2253}
2254
2255static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2256 struct ethtool_wolinfo *wol)
2257{
2258 struct ixgbe_hw *hw = &adapter->hw;
2259 int retval = 0;
2260
2261 /* WOL not supported for all devices */
2262 if (!ixgbe_wol_supported(adapter, hw->device_id,
2263 hw->subsystem_device_id)) {
2264 retval = 1;
2265 wol->supported = 0;
2266 }
2267
2268 return retval;
2269}
2270
2271static void ixgbe_get_wol(struct net_device *netdev,
2272 struct ethtool_wolinfo *wol)
2273{
2274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2275
2276 wol->supported = WAKE_UCAST | WAKE_MCAST |
2277 WAKE_BCAST | WAKE_MAGIC;
2278 wol->wolopts = 0;
2279
2280 if (ixgbe_wol_exclusion(adapter, wol) ||
2281 !device_can_wakeup(&adapter->pdev->dev))
2282 return;
2283
2284 if (adapter->wol & IXGBE_WUFC_EX)
2285 wol->wolopts |= WAKE_UCAST;
2286 if (adapter->wol & IXGBE_WUFC_MC)
2287 wol->wolopts |= WAKE_MCAST;
2288 if (adapter->wol & IXGBE_WUFC_BC)
2289 wol->wolopts |= WAKE_BCAST;
2290 if (adapter->wol & IXGBE_WUFC_MAG)
2291 wol->wolopts |= WAKE_MAGIC;
2292}
2293
2294static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2295{
2296 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2297
2298 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE |
2299 WAKE_FILTER))
2300 return -EOPNOTSUPP;
2301
2302 if (ixgbe_wol_exclusion(adapter, wol))
2303 return wol->wolopts ? -EOPNOTSUPP : 0;
2304
2305 adapter->wol = 0;
2306
2307 if (wol->wolopts & WAKE_UCAST)
2308 adapter->wol |= IXGBE_WUFC_EX;
2309 if (wol->wolopts & WAKE_MCAST)
2310 adapter->wol |= IXGBE_WUFC_MC;
2311 if (wol->wolopts & WAKE_BCAST)
2312 adapter->wol |= IXGBE_WUFC_BC;
2313 if (wol->wolopts & WAKE_MAGIC)
2314 adapter->wol |= IXGBE_WUFC_MAG;
2315
2316 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2317
2318 return 0;
2319}
2320
2321static int ixgbe_nway_reset(struct net_device *netdev)
2322{
2323 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2324
2325 if (netif_running(netdev))
2326 ixgbe_reinit_locked(adapter);
2327
2328 return 0;
2329}
2330
2331static int ixgbe_set_phys_id(struct net_device *netdev,
2332 enum ethtool_phys_id_state state)
2333{
2334 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2335 struct ixgbe_hw *hw = &adapter->hw;
2336
2337 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off)
2338 return -EOPNOTSUPP;
2339
2340 switch (state) {
2341 case ETHTOOL_ID_ACTIVE:
2342 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2343 return 2;
2344
2345 case ETHTOOL_ID_ON:
2346 hw->mac.ops.led_on(hw, hw->mac.led_link_act);
2347 break;
2348
2349 case ETHTOOL_ID_OFF:
2350 hw->mac.ops.led_off(hw, hw->mac.led_link_act);
2351 break;
2352
2353 case ETHTOOL_ID_INACTIVE:
2354 /* Restore LED settings */
2355 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2356 break;
2357 }
2358
2359 return 0;
2360}
2361
2362static int ixgbe_get_coalesce(struct net_device *netdev,
2363 struct ethtool_coalesce *ec)
2364{
2365 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2366
2367 /* only valid if in constant ITR mode */
2368 if (adapter->rx_itr_setting <= 1)
2369 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2370 else
2371 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2372
2373 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2374 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2375 return 0;
2376
2377 /* only valid if in constant ITR mode */
2378 if (adapter->tx_itr_setting <= 1)
2379 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2380 else
2381 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2382
2383 return 0;
2384}
2385
2386/*
2387 * this function must be called before setting the new value of
2388 * rx_itr_setting
2389 */
2390static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2391{
2392 struct net_device *netdev = adapter->netdev;
2393
2394 /* nothing to do if LRO or RSC are not enabled */
2395 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2396 !(netdev->features & NETIF_F_LRO))
2397 return false;
2398
2399 /* check the feature flag value and enable RSC if necessary */
2400 if (adapter->rx_itr_setting == 1 ||
2401 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2402 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2403 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2404 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2405 return true;
2406 }
2407 /* if interrupt rate is too high then disable RSC */
2408 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2409 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2410 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2411 return true;
2412 }
2413 return false;
2414}
2415
2416static int ixgbe_set_coalesce(struct net_device *netdev,
2417 struct ethtool_coalesce *ec)
2418{
2419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2420 struct ixgbe_q_vector *q_vector;
2421 int i;
2422 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2423 bool need_reset = false;
2424
2425 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2426 /* reject Tx specific changes in case of mixed RxTx vectors */
2427 if (ec->tx_coalesce_usecs)
2428 return -EINVAL;
2429 tx_itr_prev = adapter->rx_itr_setting;
2430 } else {
2431 tx_itr_prev = adapter->tx_itr_setting;
2432 }
2433
2434 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2435 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2436 return -EINVAL;
2437
2438 if (ec->rx_coalesce_usecs > 1)
2439 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2440 else
2441 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2442
2443 if (adapter->rx_itr_setting == 1)
2444 rx_itr_param = IXGBE_20K_ITR;
2445 else
2446 rx_itr_param = adapter->rx_itr_setting;
2447
2448 if (ec->tx_coalesce_usecs > 1)
2449 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2450 else
2451 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2452
2453 if (adapter->tx_itr_setting == 1)
2454 tx_itr_param = IXGBE_12K_ITR;
2455 else
2456 tx_itr_param = adapter->tx_itr_setting;
2457
2458 /* mixed Rx/Tx */
2459 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2460 adapter->tx_itr_setting = adapter->rx_itr_setting;
2461
2462 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2463 if ((adapter->tx_itr_setting != 1) &&
2464 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2465 if ((tx_itr_prev == 1) ||
2466 (tx_itr_prev >= IXGBE_100K_ITR))
2467 need_reset = true;
2468 } else {
2469 if ((tx_itr_prev != 1) &&
2470 (tx_itr_prev < IXGBE_100K_ITR))
2471 need_reset = true;
2472 }
2473
2474 /* check the old value and enable RSC if necessary */
2475 need_reset |= ixgbe_update_rsc(adapter);
2476
2477 for (i = 0; i < adapter->num_q_vectors; i++) {
2478 q_vector = adapter->q_vector[i];
2479 if (q_vector->tx.count && !q_vector->rx.count)
2480 /* tx only */
2481 q_vector->itr = tx_itr_param;
2482 else
2483 /* rx only or mixed */
2484 q_vector->itr = rx_itr_param;
2485 ixgbe_write_eitr(q_vector);
2486 }
2487
2488 /*
2489 * do reset here at the end to make sure EITR==0 case is handled
2490 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2491 * also locks in RSC enable/disable which requires reset
2492 */
2493 if (need_reset)
2494 ixgbe_do_reset(netdev);
2495
2496 return 0;
2497}
2498
2499static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2500 struct ethtool_rxnfc *cmd)
2501{
2502 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2503 struct ethtool_rx_flow_spec *fsp =
2504 (struct ethtool_rx_flow_spec *)&cmd->fs;
2505 struct hlist_node *node2;
2506 struct ixgbe_fdir_filter *rule = NULL;
2507
2508 /* report total rule count */
2509 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2510
2511 hlist_for_each_entry_safe(rule, node2,
2512 &adapter->fdir_filter_list, fdir_node) {
2513 if (fsp->location <= rule->sw_idx)
2514 break;
2515 }
2516
2517 if (!rule || fsp->location != rule->sw_idx)
2518 return -EINVAL;
2519
2520 /* fill out the flow spec entry */
2521
2522 /* set flow type field */
2523 switch (rule->filter.formatted.flow_type) {
2524 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2525 fsp->flow_type = TCP_V4_FLOW;
2526 break;
2527 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2528 fsp->flow_type = UDP_V4_FLOW;
2529 break;
2530 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2531 fsp->flow_type = SCTP_V4_FLOW;
2532 break;
2533 case IXGBE_ATR_FLOW_TYPE_IPV4:
2534 fsp->flow_type = IP_USER_FLOW;
2535 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2536 fsp->h_u.usr_ip4_spec.proto = 0;
2537 fsp->m_u.usr_ip4_spec.proto = 0;
2538 break;
2539 default:
2540 return -EINVAL;
2541 }
2542
2543 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2544 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2545 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2546 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2547 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2548 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2549 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2550 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2551 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2552 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2553 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2554 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2555 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2556 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2557 fsp->flow_type |= FLOW_EXT;
2558
2559 /* record action */
2560 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2561 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2562 else
2563 fsp->ring_cookie = rule->action;
2564
2565 return 0;
2566}
2567
2568static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2569 struct ethtool_rxnfc *cmd,
2570 u32 *rule_locs)
2571{
2572 struct hlist_node *node2;
2573 struct ixgbe_fdir_filter *rule;
2574 int cnt = 0;
2575
2576 /* report total rule count */
2577 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2578
2579 hlist_for_each_entry_safe(rule, node2,
2580 &adapter->fdir_filter_list, fdir_node) {
2581 if (cnt == cmd->rule_cnt)
2582 return -EMSGSIZE;
2583 rule_locs[cnt] = rule->sw_idx;
2584 cnt++;
2585 }
2586
2587 cmd->rule_cnt = cnt;
2588
2589 return 0;
2590}
2591
2592static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2593 struct ethtool_rxnfc *cmd)
2594{
2595 cmd->data = 0;
2596
2597 /* Report default options for RSS on ixgbe */
2598 switch (cmd->flow_type) {
2599 case TCP_V4_FLOW:
2600 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2601 fallthrough;
2602 case UDP_V4_FLOW:
2603 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2604 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2605 fallthrough;
2606 case SCTP_V4_FLOW:
2607 case AH_ESP_V4_FLOW:
2608 case AH_V4_FLOW:
2609 case ESP_V4_FLOW:
2610 case IPV4_FLOW:
2611 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2612 break;
2613 case TCP_V6_FLOW:
2614 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2615 fallthrough;
2616 case UDP_V6_FLOW:
2617 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2618 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2619 fallthrough;
2620 case SCTP_V6_FLOW:
2621 case AH_ESP_V6_FLOW:
2622 case AH_V6_FLOW:
2623 case ESP_V6_FLOW:
2624 case IPV6_FLOW:
2625 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2626 break;
2627 default:
2628 return -EINVAL;
2629 }
2630
2631 return 0;
2632}
2633
2634static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2635 u32 *rule_locs)
2636{
2637 struct ixgbe_adapter *adapter = netdev_priv(dev);
2638 int ret = -EOPNOTSUPP;
2639
2640 switch (cmd->cmd) {
2641 case ETHTOOL_GRXRINGS:
2642 cmd->data = adapter->num_rx_queues;
2643 ret = 0;
2644 break;
2645 case ETHTOOL_GRXCLSRLCNT:
2646 cmd->rule_cnt = adapter->fdir_filter_count;
2647 ret = 0;
2648 break;
2649 case ETHTOOL_GRXCLSRULE:
2650 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2651 break;
2652 case ETHTOOL_GRXCLSRLALL:
2653 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2654 break;
2655 case ETHTOOL_GRXFH:
2656 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2657 break;
2658 default:
2659 break;
2660 }
2661
2662 return ret;
2663}
2664
2665int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2666 struct ixgbe_fdir_filter *input,
2667 u16 sw_idx)
2668{
2669 struct ixgbe_hw *hw = &adapter->hw;
2670 struct hlist_node *node2;
2671 struct ixgbe_fdir_filter *rule, *parent;
2672 int err = -EINVAL;
2673
2674 parent = NULL;
2675 rule = NULL;
2676
2677 hlist_for_each_entry_safe(rule, node2,
2678 &adapter->fdir_filter_list, fdir_node) {
2679 /* hash found, or no matching entry */
2680 if (rule->sw_idx >= sw_idx)
2681 break;
2682 parent = rule;
2683 }
2684
2685 /* if there is an old rule occupying our place remove it */
2686 if (rule && (rule->sw_idx == sw_idx)) {
2687 if (!input || (rule->filter.formatted.bkt_hash !=
2688 input->filter.formatted.bkt_hash)) {
2689 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2690 &rule->filter,
2691 sw_idx);
2692 }
2693
2694 hlist_del(&rule->fdir_node);
2695 kfree(rule);
2696 adapter->fdir_filter_count--;
2697 }
2698
2699 /*
2700 * If no input this was a delete, err should be 0 if a rule was
2701 * successfully found and removed from the list else -EINVAL
2702 */
2703 if (!input)
2704 return err;
2705
2706 /* initialize node and set software index */
2707 INIT_HLIST_NODE(&input->fdir_node);
2708
2709 /* add filter to the list */
2710 if (parent)
2711 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
2712 else
2713 hlist_add_head(&input->fdir_node,
2714 &adapter->fdir_filter_list);
2715
2716 /* update counts */
2717 adapter->fdir_filter_count++;
2718
2719 return 0;
2720}
2721
2722static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2723 u8 *flow_type)
2724{
2725 switch (fsp->flow_type & ~FLOW_EXT) {
2726 case TCP_V4_FLOW:
2727 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2728 break;
2729 case UDP_V4_FLOW:
2730 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2731 break;
2732 case SCTP_V4_FLOW:
2733 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2734 break;
2735 case IP_USER_FLOW:
2736 switch (fsp->h_u.usr_ip4_spec.proto) {
2737 case IPPROTO_TCP:
2738 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2739 break;
2740 case IPPROTO_UDP:
2741 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2742 break;
2743 case IPPROTO_SCTP:
2744 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2745 break;
2746 case 0:
2747 if (!fsp->m_u.usr_ip4_spec.proto) {
2748 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2749 break;
2750 }
2751 fallthrough;
2752 default:
2753 return 0;
2754 }
2755 break;
2756 default:
2757 return 0;
2758 }
2759
2760 return 1;
2761}
2762
2763static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2764 struct ethtool_rxnfc *cmd)
2765{
2766 struct ethtool_rx_flow_spec *fsp =
2767 (struct ethtool_rx_flow_spec *)&cmd->fs;
2768 struct ixgbe_hw *hw = &adapter->hw;
2769 struct ixgbe_fdir_filter *input;
2770 union ixgbe_atr_input mask;
2771 u8 queue;
2772 int err;
2773
2774 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2775 return -EOPNOTSUPP;
2776
2777 /* ring_cookie is a masked into a set of queues and ixgbe pools or
2778 * we use the drop index.
2779 */
2780 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2781 queue = IXGBE_FDIR_DROP_QUEUE;
2782 } else {
2783 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2784 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2785
2786 if (!vf && (ring >= adapter->num_rx_queues))
2787 return -EINVAL;
2788 else if (vf &&
2789 ((vf > adapter->num_vfs) ||
2790 ring >= adapter->num_rx_queues_per_pool))
2791 return -EINVAL;
2792
2793 /* Map the ring onto the absolute queue index */
2794 if (!vf)
2795 queue = adapter->rx_ring[ring]->reg_idx;
2796 else
2797 queue = ((vf - 1) *
2798 adapter->num_rx_queues_per_pool) + ring;
2799 }
2800
2801 /* Don't allow indexes to exist outside of available space */
2802 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2803 e_err(drv, "Location out of range\n");
2804 return -EINVAL;
2805 }
2806
2807 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2808 if (!input)
2809 return -ENOMEM;
2810
2811 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2812
2813 /* set SW index */
2814 input->sw_idx = fsp->location;
2815
2816 /* record flow type */
2817 if (!ixgbe_flowspec_to_flow_type(fsp,
2818 &input->filter.formatted.flow_type)) {
2819 e_err(drv, "Unrecognized flow type\n");
2820 goto err_out;
2821 }
2822
2823 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2824 IXGBE_ATR_L4TYPE_MASK;
2825
2826 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2827 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2828
2829 /* Copy input into formatted structures */
2830 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2831 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2832 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2833 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2834 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2835 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2836 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2837 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2838
2839 if (fsp->flow_type & FLOW_EXT) {
2840 input->filter.formatted.vm_pool =
2841 (unsigned char)ntohl(fsp->h_ext.data[1]);
2842 mask.formatted.vm_pool =
2843 (unsigned char)ntohl(fsp->m_ext.data[1]);
2844 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2845 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2846 input->filter.formatted.flex_bytes =
2847 fsp->h_ext.vlan_etype;
2848 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2849 }
2850
2851 /* determine if we need to drop or route the packet */
2852 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2853 input->action = IXGBE_FDIR_DROP_QUEUE;
2854 else
2855 input->action = fsp->ring_cookie;
2856
2857 spin_lock(&adapter->fdir_perfect_lock);
2858
2859 if (hlist_empty(&adapter->fdir_filter_list)) {
2860 /* save mask and program input mask into HW */
2861 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2862 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2863 if (err) {
2864 e_err(drv, "Error writing mask\n");
2865 goto err_out_w_lock;
2866 }
2867 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2868 e_err(drv, "Only one mask supported per port\n");
2869 goto err_out_w_lock;
2870 }
2871
2872 /* apply mask and compute/store hash */
2873 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2874
2875 /* program filters to filter memory */
2876 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2877 &input->filter, input->sw_idx, queue);
2878 if (err)
2879 goto err_out_w_lock;
2880
2881 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2882
2883 spin_unlock(&adapter->fdir_perfect_lock);
2884
2885 return err;
2886err_out_w_lock:
2887 spin_unlock(&adapter->fdir_perfect_lock);
2888err_out:
2889 kfree(input);
2890 return -EINVAL;
2891}
2892
2893static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2894 struct ethtool_rxnfc *cmd)
2895{
2896 struct ethtool_rx_flow_spec *fsp =
2897 (struct ethtool_rx_flow_spec *)&cmd->fs;
2898 int err;
2899
2900 spin_lock(&adapter->fdir_perfect_lock);
2901 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2902 spin_unlock(&adapter->fdir_perfect_lock);
2903
2904 return err;
2905}
2906
2907#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2908 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2909static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2910 struct ethtool_rxnfc *nfc)
2911{
2912 u32 flags2 = adapter->flags2;
2913
2914 /*
2915 * RSS does not support anything other than hashing
2916 * to queues on src and dst IPs and ports
2917 */
2918 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2919 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2920 return -EINVAL;
2921
2922 switch (nfc->flow_type) {
2923 case TCP_V4_FLOW:
2924 case TCP_V6_FLOW:
2925 if (!(nfc->data & RXH_IP_SRC) ||
2926 !(nfc->data & RXH_IP_DST) ||
2927 !(nfc->data & RXH_L4_B_0_1) ||
2928 !(nfc->data & RXH_L4_B_2_3))
2929 return -EINVAL;
2930 break;
2931 case UDP_V4_FLOW:
2932 if (!(nfc->data & RXH_IP_SRC) ||
2933 !(nfc->data & RXH_IP_DST))
2934 return -EINVAL;
2935 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2936 case 0:
2937 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2938 break;
2939 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2940 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2941 break;
2942 default:
2943 return -EINVAL;
2944 }
2945 break;
2946 case UDP_V6_FLOW:
2947 if (!(nfc->data & RXH_IP_SRC) ||
2948 !(nfc->data & RXH_IP_DST))
2949 return -EINVAL;
2950 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2951 case 0:
2952 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2953 break;
2954 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2955 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2956 break;
2957 default:
2958 return -EINVAL;
2959 }
2960 break;
2961 case AH_ESP_V4_FLOW:
2962 case AH_V4_FLOW:
2963 case ESP_V4_FLOW:
2964 case SCTP_V4_FLOW:
2965 case AH_ESP_V6_FLOW:
2966 case AH_V6_FLOW:
2967 case ESP_V6_FLOW:
2968 case SCTP_V6_FLOW:
2969 if (!(nfc->data & RXH_IP_SRC) ||
2970 !(nfc->data & RXH_IP_DST) ||
2971 (nfc->data & RXH_L4_B_0_1) ||
2972 (nfc->data & RXH_L4_B_2_3))
2973 return -EINVAL;
2974 break;
2975 default:
2976 return -EINVAL;
2977 }
2978
2979 /* if we changed something we need to update flags */
2980 if (flags2 != adapter->flags2) {
2981 struct ixgbe_hw *hw = &adapter->hw;
2982 u32 mrqc;
2983 unsigned int pf_pool = adapter->num_vfs;
2984
2985 if ((hw->mac.type >= ixgbe_mac_X550) &&
2986 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2987 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2988 else
2989 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2990
2991 if ((flags2 & UDP_RSS_FLAGS) &&
2992 !(adapter->flags2 & UDP_RSS_FLAGS))
2993 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2994
2995 adapter->flags2 = flags2;
2996
2997 /* Perform hash on these packet types */
2998 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2999 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
3000 | IXGBE_MRQC_RSS_FIELD_IPV6
3001 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3002
3003 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
3004 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
3005
3006 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3007 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3008
3009 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3010 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3011
3012 if ((hw->mac.type >= ixgbe_mac_X550) &&
3013 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3014 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
3015 else
3016 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3017 }
3018
3019 return 0;
3020}
3021
3022static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3023{
3024 struct ixgbe_adapter *adapter = netdev_priv(dev);
3025 int ret = -EOPNOTSUPP;
3026
3027 switch (cmd->cmd) {
3028 case ETHTOOL_SRXCLSRLINS:
3029 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
3030 break;
3031 case ETHTOOL_SRXCLSRLDEL:
3032 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
3033 break;
3034 case ETHTOOL_SRXFH:
3035 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
3036 break;
3037 default:
3038 break;
3039 }
3040
3041 return ret;
3042}
3043
3044static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
3045{
3046 if (adapter->hw.mac.type < ixgbe_mac_X550)
3047 return 16;
3048 else
3049 return 64;
3050}
3051
3052static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
3053{
3054 return IXGBE_RSS_KEY_SIZE;
3055}
3056
3057static u32 ixgbe_rss_indir_size(struct net_device *netdev)
3058{
3059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3060
3061 return ixgbe_rss_indir_tbl_entries(adapter);
3062}
3063
3064static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
3065{
3066 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
3067 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask;
3068
3069 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3070 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1;
3071
3072 for (i = 0; i < reta_size; i++)
3073 indir[i] = adapter->rss_indir_tbl[i] & rss_m;
3074}
3075
3076static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3077 u8 *hfunc)
3078{
3079 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3080
3081 if (hfunc)
3082 *hfunc = ETH_RSS_HASH_TOP;
3083
3084 if (indir)
3085 ixgbe_get_reta(adapter, indir);
3086
3087 if (key)
3088 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
3089
3090 return 0;
3091}
3092
3093static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
3094 const u8 *key, const u8 hfunc)
3095{
3096 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3097 int i;
3098 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3099
3100 if (hfunc)
3101 return -EINVAL;
3102
3103 /* Fill out the redirection table */
3104 if (indir) {
3105 int max_queues = min_t(int, adapter->num_rx_queues,
3106 ixgbe_rss_indir_tbl_max(adapter));
3107
3108 /*Allow at least 2 queues w/ SR-IOV.*/
3109 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3110 (max_queues < 2))
3111 max_queues = 2;
3112
3113 /* Verify user input. */
3114 for (i = 0; i < reta_entries; i++)
3115 if (indir[i] >= max_queues)
3116 return -EINVAL;
3117
3118 for (i = 0; i < reta_entries; i++)
3119 adapter->rss_indir_tbl[i] = indir[i];
3120
3121 ixgbe_store_reta(adapter);
3122 }
3123
3124 /* Fill out the rss hash key */
3125 if (key) {
3126 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
3127 ixgbe_store_key(adapter);
3128 }
3129
3130 return 0;
3131}
3132
3133static int ixgbe_get_ts_info(struct net_device *dev,
3134 struct ethtool_ts_info *info)
3135{
3136 struct ixgbe_adapter *adapter = netdev_priv(dev);
3137
3138 /* we always support timestamping disabled */
3139 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
3140
3141 switch (adapter->hw.mac.type) {
3142 case ixgbe_mac_X550:
3143 case ixgbe_mac_X550EM_x:
3144 case ixgbe_mac_x550em_a:
3145 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3146 break;
3147 case ixgbe_mac_X540:
3148 case ixgbe_mac_82599EB:
3149 info->rx_filters |=
3150 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3151 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3152 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3153 break;
3154 default:
3155 return ethtool_op_get_ts_info(dev, info);
3156 }
3157
3158 info->so_timestamping =
3159 SOF_TIMESTAMPING_TX_SOFTWARE |
3160 SOF_TIMESTAMPING_RX_SOFTWARE |
3161 SOF_TIMESTAMPING_SOFTWARE |
3162 SOF_TIMESTAMPING_TX_HARDWARE |
3163 SOF_TIMESTAMPING_RX_HARDWARE |
3164 SOF_TIMESTAMPING_RAW_HARDWARE;
3165
3166 if (adapter->ptp_clock)
3167 info->phc_index = ptp_clock_index(adapter->ptp_clock);
3168 else
3169 info->phc_index = -1;
3170
3171 info->tx_types =
3172 BIT(HWTSTAMP_TX_OFF) |
3173 BIT(HWTSTAMP_TX_ON);
3174
3175 return 0;
3176}
3177
3178static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3179{
3180 unsigned int max_combined;
3181 u8 tcs = adapter->hw_tcs;
3182
3183 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3184 /* We only support one q_vector without MSI-X */
3185 max_combined = 1;
3186 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3187 /* Limit value based on the queue mask */
3188 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1;
3189 } else if (tcs > 1) {
3190 /* For DCB report channels per traffic class */
3191 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3192 /* 8 TC w/ 4 queues per TC */
3193 max_combined = 4;
3194 } else if (tcs > 4) {
3195 /* 8 TC w/ 8 queues per TC */
3196 max_combined = 8;
3197 } else {
3198 /* 4 TC w/ 16 queues per TC */
3199 max_combined = 16;
3200 }
3201 } else if (adapter->atr_sample_rate) {
3202 /* support up to 64 queues with ATR */
3203 max_combined = IXGBE_MAX_FDIR_INDICES;
3204 } else {
3205 /* support up to 16 queues with RSS */
3206 max_combined = ixgbe_max_rss_indices(adapter);
3207 }
3208
3209 return max_combined;
3210}
3211
3212static void ixgbe_get_channels(struct net_device *dev,
3213 struct ethtool_channels *ch)
3214{
3215 struct ixgbe_adapter *adapter = netdev_priv(dev);
3216
3217 /* report maximum channels */
3218 ch->max_combined = ixgbe_max_channels(adapter);
3219
3220 /* report info for other vector */
3221 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3222 ch->max_other = NON_Q_VECTORS;
3223 ch->other_count = NON_Q_VECTORS;
3224 }
3225
3226 /* record RSS queues */
3227 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3228
3229 /* nothing else to report if RSS is disabled */
3230 if (ch->combined_count == 1)
3231 return;
3232
3233 /* we do not support ATR queueing if SR-IOV is enabled */
3234 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3235 return;
3236
3237 /* same thing goes for being DCB enabled */
3238 if (adapter->hw_tcs > 1)
3239 return;
3240
3241 /* if ATR is disabled we can exit */
3242 if (!adapter->atr_sample_rate)
3243 return;
3244
3245 /* report flow director queues as maximum channels */
3246 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3247}
3248
3249static int ixgbe_set_channels(struct net_device *dev,
3250 struct ethtool_channels *ch)
3251{
3252 struct ixgbe_adapter *adapter = netdev_priv(dev);
3253 unsigned int count = ch->combined_count;
3254 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3255
3256 /* verify they are not requesting separate vectors */
3257 if (!count || ch->rx_count || ch->tx_count)
3258 return -EINVAL;
3259
3260 /* verify other_count has not changed */
3261 if (ch->other_count != NON_Q_VECTORS)
3262 return -EINVAL;
3263
3264 /* verify the number of channels does not exceed hardware limits */
3265 if (count > ixgbe_max_channels(adapter))
3266 return -EINVAL;
3267
3268 /* update feature limits from largest to smallest supported values */
3269 adapter->ring_feature[RING_F_FDIR].limit = count;
3270
3271 /* cap RSS limit */
3272 if (count > max_rss_indices)
3273 count = max_rss_indices;
3274 adapter->ring_feature[RING_F_RSS].limit = count;
3275
3276#ifdef IXGBE_FCOE
3277 /* cap FCoE limit at 8 */
3278 if (count > IXGBE_FCRETA_SIZE)
3279 count = IXGBE_FCRETA_SIZE;
3280 adapter->ring_feature[RING_F_FCOE].limit = count;
3281
3282#endif
3283 /* use setup TC to update any traffic class queue mapping */
3284 return ixgbe_setup_tc(dev, adapter->hw_tcs);
3285}
3286
3287static int ixgbe_get_module_info(struct net_device *dev,
3288 struct ethtool_modinfo *modinfo)
3289{
3290 struct ixgbe_adapter *adapter = netdev_priv(dev);
3291 struct ixgbe_hw *hw = &adapter->hw;
3292 s32 status;
3293 u8 sff8472_rev, addr_mode;
3294 bool page_swap = false;
3295
3296 if (hw->phy.type == ixgbe_phy_fw)
3297 return -ENXIO;
3298
3299 /* Check whether we support SFF-8472 or not */
3300 status = hw->phy.ops.read_i2c_eeprom(hw,
3301 IXGBE_SFF_SFF_8472_COMP,
3302 &sff8472_rev);
3303 if (status)
3304 return -EIO;
3305
3306 /* addressing mode is not supported */
3307 status = hw->phy.ops.read_i2c_eeprom(hw,
3308 IXGBE_SFF_SFF_8472_SWAP,
3309 &addr_mode);
3310 if (status)
3311 return -EIO;
3312
3313 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3314 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3315 page_swap = true;
3316 }
3317
3318 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap ||
3319 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) {
3320 /* We have a SFP, but it does not support SFF-8472 */
3321 modinfo->type = ETH_MODULE_SFF_8079;
3322 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3323 } else {
3324 /* We have a SFP which supports a revision of SFF-8472. */
3325 modinfo->type = ETH_MODULE_SFF_8472;
3326 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3327 }
3328
3329 return 0;
3330}
3331
3332static int ixgbe_get_module_eeprom(struct net_device *dev,
3333 struct ethtool_eeprom *ee,
3334 u8 *data)
3335{
3336 struct ixgbe_adapter *adapter = netdev_priv(dev);
3337 struct ixgbe_hw *hw = &adapter->hw;
3338 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3339 u8 databyte = 0xFF;
3340 int i = 0;
3341
3342 if (ee->len == 0)
3343 return -EINVAL;
3344
3345 if (hw->phy.type == ixgbe_phy_fw)
3346 return -ENXIO;
3347
3348 for (i = ee->offset; i < ee->offset + ee->len; i++) {
3349 /* I2C reads can take long time */
3350 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3351 return -EBUSY;
3352
3353 if (i < ETH_MODULE_SFF_8079_LEN)
3354 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3355 else
3356 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3357
3358 if (status)
3359 return -EIO;
3360
3361 data[i - ee->offset] = databyte;
3362 }
3363
3364 return 0;
3365}
3366
3367static const struct {
3368 ixgbe_link_speed mac_speed;
3369 u32 supported;
3370} ixgbe_ls_map[] = {
3371 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full },
3372 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full },
3373 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full },
3374 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full },
3375 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full },
3376};
3377
3378static const struct {
3379 u32 lp_advertised;
3380 u32 mac_speed;
3381} ixgbe_lp_map[] = {
3382 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full },
3383 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full },
3384 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full },
3385 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full },
3386 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full },
3387 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full},
3388};
3389
3390static int
3391ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata)
3392{
3393 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 s32 rc;
3396 u16 i;
3397
3398 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info);
3399 if (rc)
3400 return rc;
3401
3402 edata->lp_advertised = 0;
3403 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) {
3404 if (info[0] & ixgbe_lp_map[i].lp_advertised)
3405 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed;
3406 }
3407
3408 edata->supported = 0;
3409 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3410 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed)
3411 edata->supported |= ixgbe_ls_map[i].supported;
3412 }
3413
3414 edata->advertised = 0;
3415 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3416 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed)
3417 edata->advertised |= ixgbe_ls_map[i].supported;
3418 }
3419
3420 edata->eee_enabled = !!edata->advertised;
3421 edata->tx_lpi_enabled = edata->eee_enabled;
3422 if (edata->advertised & edata->lp_advertised)
3423 edata->eee_active = true;
3424
3425 return 0;
3426}
3427
3428static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3429{
3430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3431 struct ixgbe_hw *hw = &adapter->hw;
3432
3433 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3434 return -EOPNOTSUPP;
3435
3436 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw)
3437 return ixgbe_get_eee_fw(adapter, edata);
3438
3439 return -EOPNOTSUPP;
3440}
3441
3442static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
3443{
3444 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3445 struct ixgbe_hw *hw = &adapter->hw;
3446 struct ethtool_eee eee_data;
3447 s32 ret_val;
3448
3449 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3450 return -EOPNOTSUPP;
3451
3452 memset(&eee_data, 0, sizeof(struct ethtool_eee));
3453
3454 ret_val = ixgbe_get_eee(netdev, &eee_data);
3455 if (ret_val)
3456 return ret_val;
3457
3458 if (eee_data.eee_enabled && !edata->eee_enabled) {
3459 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) {
3460 e_err(drv, "Setting EEE tx-lpi is not supported\n");
3461 return -EINVAL;
3462 }
3463
3464 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) {
3465 e_err(drv,
3466 "Setting EEE Tx LPI timer is not supported\n");
3467 return -EINVAL;
3468 }
3469
3470 if (eee_data.advertised != edata->advertised) {
3471 e_err(drv,
3472 "Setting EEE advertised speeds is not supported\n");
3473 return -EINVAL;
3474 }
3475 }
3476
3477 if (eee_data.eee_enabled != edata->eee_enabled) {
3478 if (edata->eee_enabled) {
3479 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
3480 hw->phy.eee_speeds_advertised =
3481 hw->phy.eee_speeds_supported;
3482 } else {
3483 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
3484 hw->phy.eee_speeds_advertised = 0;
3485 }
3486
3487 /* reset link */
3488 if (netif_running(netdev))
3489 ixgbe_reinit_locked(adapter);
3490 else
3491 ixgbe_reset(adapter);
3492 }
3493
3494 return 0;
3495}
3496
3497static u32 ixgbe_get_priv_flags(struct net_device *netdev)
3498{
3499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3500 u32 priv_flags = 0;
3501
3502 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
3503 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX;
3504
3505 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED)
3506 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN;
3507
3508 return priv_flags;
3509}
3510
3511static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3512{
3513 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3514 unsigned int flags2 = adapter->flags2;
3515
3516 flags2 &= ~IXGBE_FLAG2_RX_LEGACY;
3517 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX)
3518 flags2 |= IXGBE_FLAG2_RX_LEGACY;
3519
3520 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED;
3521 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN)
3522 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED;
3523
3524 if (flags2 != adapter->flags2) {
3525 adapter->flags2 = flags2;
3526
3527 /* reset interface to repopulate queues */
3528 if (netif_running(netdev))
3529 ixgbe_reinit_locked(adapter);
3530 }
3531
3532 return 0;
3533}
3534
3535static const struct ethtool_ops ixgbe_ethtool_ops = {
3536 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3537 .get_drvinfo = ixgbe_get_drvinfo,
3538 .get_regs_len = ixgbe_get_regs_len,
3539 .get_regs = ixgbe_get_regs,
3540 .get_wol = ixgbe_get_wol,
3541 .set_wol = ixgbe_set_wol,
3542 .nway_reset = ixgbe_nway_reset,
3543 .get_link = ethtool_op_get_link,
3544 .get_eeprom_len = ixgbe_get_eeprom_len,
3545 .get_eeprom = ixgbe_get_eeprom,
3546 .set_eeprom = ixgbe_set_eeprom,
3547 .get_ringparam = ixgbe_get_ringparam,
3548 .set_ringparam = ixgbe_set_ringparam,
3549 .get_pauseparam = ixgbe_get_pauseparam,
3550 .set_pauseparam = ixgbe_set_pauseparam,
3551 .get_msglevel = ixgbe_get_msglevel,
3552 .set_msglevel = ixgbe_set_msglevel,
3553 .self_test = ixgbe_diag_test,
3554 .get_strings = ixgbe_get_strings,
3555 .set_phys_id = ixgbe_set_phys_id,
3556 .get_sset_count = ixgbe_get_sset_count,
3557 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3558 .get_coalesce = ixgbe_get_coalesce,
3559 .set_coalesce = ixgbe_set_coalesce,
3560 .get_rxnfc = ixgbe_get_rxnfc,
3561 .set_rxnfc = ixgbe_set_rxnfc,
3562 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3563 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3564 .get_rxfh = ixgbe_get_rxfh,
3565 .set_rxfh = ixgbe_set_rxfh,
3566 .get_eee = ixgbe_get_eee,
3567 .set_eee = ixgbe_set_eee,
3568 .get_channels = ixgbe_get_channels,
3569 .set_channels = ixgbe_set_channels,
3570 .get_priv_flags = ixgbe_get_priv_flags,
3571 .set_priv_flags = ixgbe_set_priv_flags,
3572 .get_ts_info = ixgbe_get_ts_info,
3573 .get_module_info = ixgbe_get_module_info,
3574 .get_module_eeprom = ixgbe_get_module_eeprom,
3575 .get_link_ksettings = ixgbe_get_link_ksettings,
3576 .set_link_ksettings = ixgbe_set_link_ksettings,
3577};
3578
3579void ixgbe_set_ethtool_ops(struct net_device *netdev)
3580{
3581 netdev->ethtool_ops = &ixgbe_ethtool_ops;
3582}