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1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <linux/delay.h>
21#include <linux/export.h>
22#include <linux/gpio.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/platform_data/b53.h>
26#include <linux/phy.h>
27#include <linux/phylink.h>
28#include <linux/etherdevice.h>
29#include <linux/if_bridge.h>
30#include <net/dsa.h>
31
32#include "b53_regs.h"
33#include "b53_priv.h"
34
35struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39};
40
41/* BCM5365 MIB counters */
42static const struct b53_mib_desc b53_mibs_65[] = {
43 { 8, 0x00, "TxOctets" },
44 { 4, 0x08, "TxDropPkts" },
45 { 4, 0x10, "TxBroadcastPkts" },
46 { 4, 0x14, "TxMulticastPkts" },
47 { 4, 0x18, "TxUnicastPkts" },
48 { 4, 0x1c, "TxCollisions" },
49 { 4, 0x20, "TxSingleCollision" },
50 { 4, 0x24, "TxMultipleCollision" },
51 { 4, 0x28, "TxDeferredTransmit" },
52 { 4, 0x2c, "TxLateCollision" },
53 { 4, 0x30, "TxExcessiveCollision" },
54 { 4, 0x38, "TxPausePkts" },
55 { 8, 0x44, "RxOctets" },
56 { 4, 0x4c, "RxUndersizePkts" },
57 { 4, 0x50, "RxPausePkts" },
58 { 4, 0x54, "Pkts64Octets" },
59 { 4, 0x58, "Pkts65to127Octets" },
60 { 4, 0x5c, "Pkts128to255Octets" },
61 { 4, 0x60, "Pkts256to511Octets" },
62 { 4, 0x64, "Pkts512to1023Octets" },
63 { 4, 0x68, "Pkts1024to1522Octets" },
64 { 4, 0x6c, "RxOversizePkts" },
65 { 4, 0x70, "RxJabbers" },
66 { 4, 0x74, "RxAlignmentErrors" },
67 { 4, 0x78, "RxFCSErrors" },
68 { 8, 0x7c, "RxGoodOctets" },
69 { 4, 0x84, "RxDropPkts" },
70 { 4, 0x88, "RxUnicastPkts" },
71 { 4, 0x8c, "RxMulticastPkts" },
72 { 4, 0x90, "RxBroadcastPkts" },
73 { 4, 0x94, "RxSAChanges" },
74 { 4, 0x98, "RxFragments" },
75};
76
77#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
78
79/* BCM63xx MIB counters */
80static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123};
124
125#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
126
127/* MIB counters */
128static const struct b53_mib_desc b53_mibs[] = {
129 { 8, 0x00, "TxOctets" },
130 { 4, 0x08, "TxDropPkts" },
131 { 4, 0x10, "TxBroadcastPkts" },
132 { 4, 0x14, "TxMulticastPkts" },
133 { 4, 0x18, "TxUnicastPkts" },
134 { 4, 0x1c, "TxCollisions" },
135 { 4, 0x20, "TxSingleCollision" },
136 { 4, 0x24, "TxMultipleCollision" },
137 { 4, 0x28, "TxDeferredTransmit" },
138 { 4, 0x2c, "TxLateCollision" },
139 { 4, 0x30, "TxExcessiveCollision" },
140 { 4, 0x38, "TxPausePkts" },
141 { 8, 0x50, "RxOctets" },
142 { 4, 0x58, "RxUndersizePkts" },
143 { 4, 0x5c, "RxPausePkts" },
144 { 4, 0x60, "Pkts64Octets" },
145 { 4, 0x64, "Pkts65to127Octets" },
146 { 4, 0x68, "Pkts128to255Octets" },
147 { 4, 0x6c, "Pkts256to511Octets" },
148 { 4, 0x70, "Pkts512to1023Octets" },
149 { 4, 0x74, "Pkts1024to1522Octets" },
150 { 4, 0x78, "RxOversizePkts" },
151 { 4, 0x7c, "RxJabbers" },
152 { 4, 0x80, "RxAlignmentErrors" },
153 { 4, 0x84, "RxFCSErrors" },
154 { 8, 0x88, "RxGoodOctets" },
155 { 4, 0x90, "RxDropPkts" },
156 { 4, 0x94, "RxUnicastPkts" },
157 { 4, 0x98, "RxMulticastPkts" },
158 { 4, 0x9c, "RxBroadcastPkts" },
159 { 4, 0xa0, "RxSAChanges" },
160 { 4, 0xa4, "RxFragments" },
161 { 4, 0xa8, "RxJumboPkts" },
162 { 4, 0xac, "RxSymbolErrors" },
163 { 4, 0xc0, "RxDiscarded" },
164};
165
166#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
167
168static const struct b53_mib_desc b53_mibs_58xx[] = {
169 { 8, 0x00, "TxOctets" },
170 { 4, 0x08, "TxDropPkts" },
171 { 4, 0x0c, "TxQPKTQ0" },
172 { 4, 0x10, "TxBroadcastPkts" },
173 { 4, 0x14, "TxMulticastPkts" },
174 { 4, 0x18, "TxUnicastPKts" },
175 { 4, 0x1c, "TxCollisions" },
176 { 4, 0x20, "TxSingleCollision" },
177 { 4, 0x24, "TxMultipleCollision" },
178 { 4, 0x28, "TxDeferredCollision" },
179 { 4, 0x2c, "TxLateCollision" },
180 { 4, 0x30, "TxExcessiveCollision" },
181 { 4, 0x34, "TxFrameInDisc" },
182 { 4, 0x38, "TxPausePkts" },
183 { 4, 0x3c, "TxQPKTQ1" },
184 { 4, 0x40, "TxQPKTQ2" },
185 { 4, 0x44, "TxQPKTQ3" },
186 { 4, 0x48, "TxQPKTQ4" },
187 { 4, 0x4c, "TxQPKTQ5" },
188 { 8, 0x50, "RxOctets" },
189 { 4, 0x58, "RxUndersizePkts" },
190 { 4, 0x5c, "RxPausePkts" },
191 { 4, 0x60, "RxPkts64Octets" },
192 { 4, 0x64, "RxPkts65to127Octets" },
193 { 4, 0x68, "RxPkts128to255Octets" },
194 { 4, 0x6c, "RxPkts256to511Octets" },
195 { 4, 0x70, "RxPkts512to1023Octets" },
196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
197 { 4, 0x78, "RxOversizePkts" },
198 { 4, 0x7c, "RxJabbers" },
199 { 4, 0x80, "RxAlignmentErrors" },
200 { 4, 0x84, "RxFCSErrors" },
201 { 8, 0x88, "RxGoodOctets" },
202 { 4, 0x90, "RxDropPkts" },
203 { 4, 0x94, "RxUnicastPkts" },
204 { 4, 0x98, "RxMulticastPkts" },
205 { 4, 0x9c, "RxBroadcastPkts" },
206 { 4, 0xa0, "RxSAChanges" },
207 { 4, 0xa4, "RxFragments" },
208 { 4, 0xa8, "RxJumboPkt" },
209 { 4, 0xac, "RxSymblErr" },
210 { 4, 0xb0, "InRangeErrCount" },
211 { 4, 0xb4, "OutRangeErrCount" },
212 { 4, 0xb8, "EEELpiEvent" },
213 { 4, 0xbc, "EEELpiDuration" },
214 { 4, 0xc0, "RxDiscard" },
215 { 4, 0xc8, "TxQPKTQ6" },
216 { 4, 0xcc, "TxQPKTQ7" },
217 { 4, 0xd0, "TxPkts64Octets" },
218 { 4, 0xd4, "TxPkts65to127Octets" },
219 { 4, 0xd8, "TxPkts128to255Octets" },
220 { 4, 0xdc, "TxPkts256to511Ocets" },
221 { 4, 0xe0, "TxPkts512to1023Ocets" },
222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
223};
224
225#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
226
227static int b53_do_vlan_op(struct b53_device *dev, u8 op)
228{
229 unsigned int i;
230
231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
232
233 for (i = 0; i < 10; i++) {
234 u8 vta;
235
236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
237 if (!(vta & VTA_START_CMD))
238 return 0;
239
240 usleep_range(100, 200);
241 }
242
243 return -EIO;
244}
245
246static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
247 struct b53_vlan *vlan)
248{
249 if (is5325(dev)) {
250 u32 entry = 0;
251
252 if (vlan->members) {
253 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
254 VA_UNTAG_S_25) | vlan->members;
255 if (dev->core_rev >= 3)
256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
257 else
258 entry |= VA_VALID_25;
259 }
260
261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
263 VTA_RW_STATE_WR | VTA_RW_OP_EN);
264 } else if (is5365(dev)) {
265 u16 entry = 0;
266
267 if (vlan->members)
268 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
270
271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
273 VTA_RW_STATE_WR | VTA_RW_OP_EN);
274 } else {
275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
277 (vlan->untag << VTE_UNTAG_S) | vlan->members);
278
279 b53_do_vlan_op(dev, VTA_CMD_WRITE);
280 }
281
282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
283 vid, vlan->members, vlan->untag);
284}
285
286static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
287 struct b53_vlan *vlan)
288{
289 if (is5325(dev)) {
290 u32 entry = 0;
291
292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
293 VTA_RW_STATE_RD | VTA_RW_OP_EN);
294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
295
296 if (dev->core_rev >= 3)
297 vlan->valid = !!(entry & VA_VALID_25_R4);
298 else
299 vlan->valid = !!(entry & VA_VALID_25);
300 vlan->members = entry & VA_MEMBER_MASK;
301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
302
303 } else if (is5365(dev)) {
304 u16 entry = 0;
305
306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
307 VTA_RW_STATE_WR | VTA_RW_OP_EN);
308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
309
310 vlan->valid = !!(entry & VA_VALID_65);
311 vlan->members = entry & VA_MEMBER_MASK;
312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
313 } else {
314 u32 entry = 0;
315
316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
317 b53_do_vlan_op(dev, VTA_CMD_READ);
318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
319 vlan->members = entry & VTE_MEMBERS;
320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
321 vlan->valid = true;
322 }
323}
324
325static void b53_set_forwarding(struct b53_device *dev, int enable)
326{
327 u8 mgmt;
328
329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
330
331 if (enable)
332 mgmt |= SM_SW_FWD_EN;
333 else
334 mgmt &= ~SM_SW_FWD_EN;
335
336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
337
338 /* Include IMP port in dumb forwarding mode
339 */
340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
341 mgmt |= B53_MII_DUMB_FWDG_EN;
342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
343
344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
345 * frames should be flooded or not.
346 */
347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
350}
351
352static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
353 bool enable_filtering)
354{
355 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
360
361 if (is5325(dev) || is5365(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
364 } else if (is63xx(dev)) {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
367 } else {
368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
370 }
371
372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 if (enable_filtering) {
377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
378 vc5 |= VC5_DROP_VTABLE_MISS;
379 } else {
380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
381 vc5 &= ~VC5_DROP_VTABLE_MISS;
382 }
383
384 if (is5325(dev))
385 vc0 &= ~VC0_RESERVED_1;
386
387 if (is5325(dev) || is5365(dev))
388 vc1 |= VC1_RX_MCST_TAG_EN;
389
390 } else {
391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
393 vc4 &= ~VC4_ING_VID_CHECK_MASK;
394 vc5 &= ~VC5_DROP_VTABLE_MISS;
395
396 if (is5325(dev) || is5365(dev))
397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
398 else
399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
400
401 if (is5325(dev) || is5365(dev))
402 vc1 &= ~VC1_RX_MCST_TAG_EN;
403 }
404
405 if (!is5325(dev) && !is5365(dev))
406 vc5 &= ~VC5_VID_FFF_EN;
407
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
410
411 if (is5325(dev) || is5365(dev)) {
412 /* enable the high 8 bit vid check on 5325 */
413 if (is5325(dev) && enable)
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
415 VC3_HIGH_8BIT_EN);
416 else
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
418
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
421 } else if (is63xx(dev)) {
422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
425 } else {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
429 }
430
431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
432
433 dev->vlan_enabled = enable;
434
435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
436 port, enable, enable_filtering);
437}
438
439static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
440{
441 u32 port_mask = 0;
442 u16 max_size = JMS_MIN_SIZE;
443
444 if (is5325(dev) || is5365(dev))
445 return -EINVAL;
446
447 if (enable) {
448 port_mask = dev->enabled_ports;
449 max_size = JMS_MAX_SIZE;
450 if (allow_10_100)
451 port_mask |= JPM_10_100_JUMBO_EN;
452 }
453
454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
456}
457
458static int b53_flush_arl(struct b53_device *dev, u8 mask)
459{
460 unsigned int i;
461
462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
464
465 for (i = 0; i < 10; i++) {
466 u8 fast_age_ctrl;
467
468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
469 &fast_age_ctrl);
470
471 if (!(fast_age_ctrl & FAST_AGE_DONE))
472 goto out;
473
474 msleep(1);
475 }
476
477 return -ETIMEDOUT;
478out:
479 /* Only age dynamic entries (default behavior) */
480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
481 return 0;
482}
483
484static int b53_fast_age_port(struct b53_device *dev, int port)
485{
486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
487
488 return b53_flush_arl(dev, FAST_AGE_PORT);
489}
490
491static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
492{
493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
494
495 return b53_flush_arl(dev, FAST_AGE_VLAN);
496}
497
498void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
499{
500 struct b53_device *dev = ds->priv;
501 unsigned int i;
502 u16 pvlan;
503
504 /* Enable the IMP port to be in the same VLAN as the other ports
505 * on a per-port basis such that we only have Port i and IMP in
506 * the same VLAN.
507 */
508 b53_for_each_port(dev, i) {
509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
510 pvlan |= BIT(cpu_port);
511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
512 }
513}
514EXPORT_SYMBOL(b53_imp_vlan_setup);
515
516static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
517 bool unicast)
518{
519 u16 uc;
520
521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
522 if (unicast)
523 uc |= BIT(port);
524 else
525 uc &= ~BIT(port);
526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
527}
528
529static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
530 bool multicast)
531{
532 u16 mc;
533
534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
535 if (multicast)
536 mc |= BIT(port);
537 else
538 mc &= ~BIT(port);
539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
540
541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
542 if (multicast)
543 mc |= BIT(port);
544 else
545 mc &= ~BIT(port);
546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
547}
548
549static void b53_port_set_learning(struct b53_device *dev, int port,
550 bool learning)
551{
552 u16 reg;
553
554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
555 if (learning)
556 reg &= ~BIT(port);
557 else
558 reg |= BIT(port);
559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
560}
561
562int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
563{
564 struct b53_device *dev = ds->priv;
565 unsigned int cpu_port;
566 int ret = 0;
567 u16 pvlan;
568
569 if (!dsa_is_user_port(ds, port))
570 return 0;
571
572 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
573
574 b53_port_set_ucast_flood(dev, port, true);
575 b53_port_set_mcast_flood(dev, port, true);
576 b53_port_set_learning(dev, port, false);
577
578 if (dev->ops->irq_enable)
579 ret = dev->ops->irq_enable(dev, port);
580 if (ret)
581 return ret;
582
583 /* Clear the Rx and Tx disable bits and set to no spanning tree */
584 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
585
586 /* Set this port, and only this one to be in the default VLAN,
587 * if member of a bridge, restore its membership prior to
588 * bringing down this port.
589 */
590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
591 pvlan &= ~0x1ff;
592 pvlan |= BIT(port);
593 pvlan |= dev->ports[port].vlan_ctl_mask;
594 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
595
596 b53_imp_vlan_setup(ds, cpu_port);
597
598 /* If EEE was enabled, restore it */
599 if (dev->ports[port].eee.eee_enabled)
600 b53_eee_enable_set(ds, port, true);
601
602 return 0;
603}
604EXPORT_SYMBOL(b53_enable_port);
605
606void b53_disable_port(struct dsa_switch *ds, int port)
607{
608 struct b53_device *dev = ds->priv;
609 u8 reg;
610
611 /* Disable Tx/Rx for the port */
612 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
613 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
615
616 if (dev->ops->irq_disable)
617 dev->ops->irq_disable(dev, port);
618}
619EXPORT_SYMBOL(b53_disable_port);
620
621void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
622{
623 struct b53_device *dev = ds->priv;
624 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
625 u8 hdr_ctl, val;
626 u16 reg;
627
628 /* Resolve which bit controls the Broadcom tag */
629 switch (port) {
630 case 8:
631 val = BRCM_HDR_P8_EN;
632 break;
633 case 7:
634 val = BRCM_HDR_P7_EN;
635 break;
636 case 5:
637 val = BRCM_HDR_P5_EN;
638 break;
639 default:
640 val = 0;
641 break;
642 }
643
644 /* Enable management mode if tagging is requested */
645 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
646 if (tag_en)
647 hdr_ctl |= SM_SW_FWD_MODE;
648 else
649 hdr_ctl &= ~SM_SW_FWD_MODE;
650 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
651
652 /* Configure the appropriate IMP port */
653 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
654 if (port == 8)
655 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
656 else if (port == 5)
657 hdr_ctl |= GC_FRM_MGMT_PORT_M;
658 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
659
660 /* Enable Broadcom tags for IMP port */
661 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
662 if (tag_en)
663 hdr_ctl |= val;
664 else
665 hdr_ctl &= ~val;
666 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
667
668 /* Registers below are only accessible on newer devices */
669 if (!is58xx(dev))
670 return;
671
672 /* Enable reception Broadcom tag for CPU TX (switch RX) to
673 * allow us to tag outgoing frames
674 */
675 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
676 if (tag_en)
677 reg &= ~BIT(port);
678 else
679 reg |= BIT(port);
680 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
681
682 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
683 * allow delivering frames to the per-port net_devices
684 */
685 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
686 if (tag_en)
687 reg &= ~BIT(port);
688 else
689 reg |= BIT(port);
690 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
691}
692EXPORT_SYMBOL(b53_brcm_hdr_setup);
693
694static void b53_enable_cpu_port(struct b53_device *dev, int port)
695{
696 u8 port_ctrl;
697
698 /* BCM5325 CPU port is at 8 */
699 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
700 port = B53_CPU_PORT;
701
702 port_ctrl = PORT_CTRL_RX_BCST_EN |
703 PORT_CTRL_RX_MCST_EN |
704 PORT_CTRL_RX_UCST_EN;
705 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
706
707 b53_brcm_hdr_setup(dev->ds, port);
708
709 b53_port_set_ucast_flood(dev, port, true);
710 b53_port_set_mcast_flood(dev, port, true);
711 b53_port_set_learning(dev, port, false);
712}
713
714static void b53_enable_mib(struct b53_device *dev)
715{
716 u8 gc;
717
718 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
719 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
720 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
721}
722
723static u16 b53_default_pvid(struct b53_device *dev)
724{
725 if (is5325(dev) || is5365(dev))
726 return 1;
727 else
728 return 0;
729}
730
731static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
732{
733 struct b53_device *dev = ds->priv;
734
735 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
736}
737
738int b53_configure_vlan(struct dsa_switch *ds)
739{
740 struct b53_device *dev = ds->priv;
741 struct b53_vlan vl = { 0 };
742 struct b53_vlan *v;
743 int i, def_vid;
744 u16 vid;
745
746 def_vid = b53_default_pvid(dev);
747
748 /* clear all vlan entries */
749 if (is5325(dev) || is5365(dev)) {
750 for (i = def_vid; i < dev->num_vlans; i++)
751 b53_set_vlan_entry(dev, i, &vl);
752 } else {
753 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
754 }
755
756 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
757
758 /* Create an untagged VLAN entry for the default PVID in case
759 * CONFIG_VLAN_8021Q is disabled and there are no calls to
760 * dsa_user_vlan_rx_add_vid() to create the default VLAN
761 * entry. Do this only when the tagging protocol is not
762 * DSA_TAG_PROTO_NONE
763 */
764 b53_for_each_port(dev, i) {
765 v = &dev->vlans[def_vid];
766 v->members |= BIT(i);
767 if (!b53_vlan_port_needs_forced_tagged(ds, i))
768 v->untag = v->members;
769 b53_write16(dev, B53_VLAN_PAGE,
770 B53_VLAN_PORT_DEF_TAG(i), def_vid);
771 }
772
773 /* Upon initial call we have not set-up any VLANs, but upon
774 * system resume, we need to restore all VLAN entries.
775 */
776 for (vid = def_vid; vid < dev->num_vlans; vid++) {
777 v = &dev->vlans[vid];
778
779 if (!v->members)
780 continue;
781
782 b53_set_vlan_entry(dev, vid, v);
783 b53_fast_age_vlan(dev, vid);
784 }
785
786 return 0;
787}
788EXPORT_SYMBOL(b53_configure_vlan);
789
790static void b53_switch_reset_gpio(struct b53_device *dev)
791{
792 int gpio = dev->reset_gpio;
793
794 if (gpio < 0)
795 return;
796
797 /* Reset sequence: RESET low(50ms)->high(20ms)
798 */
799 gpio_set_value(gpio, 0);
800 mdelay(50);
801
802 gpio_set_value(gpio, 1);
803 mdelay(20);
804
805 dev->current_page = 0xff;
806}
807
808static int b53_switch_reset(struct b53_device *dev)
809{
810 unsigned int timeout = 1000;
811 u8 mgmt, reg;
812
813 b53_switch_reset_gpio(dev);
814
815 if (is539x(dev)) {
816 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
817 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
818 }
819
820 /* This is specific to 58xx devices here, do not use is58xx() which
821 * covers the larger Starfigther 2 family, including 7445/7278 which
822 * still use this driver as a library and need to perform the reset
823 * earlier.
824 */
825 if (dev->chip_id == BCM58XX_DEVICE_ID ||
826 dev->chip_id == BCM583XX_DEVICE_ID) {
827 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
828 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
829 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
830
831 do {
832 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
833 if (!(reg & SW_RST))
834 break;
835
836 usleep_range(1000, 2000);
837 } while (timeout-- > 0);
838
839 if (timeout == 0) {
840 dev_err(dev->dev,
841 "Timeout waiting for SW_RST to clear!\n");
842 return -ETIMEDOUT;
843 }
844 }
845
846 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
847
848 if (!(mgmt & SM_SW_FWD_EN)) {
849 mgmt &= ~SM_SW_FWD_MODE;
850 mgmt |= SM_SW_FWD_EN;
851
852 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
853 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
854
855 if (!(mgmt & SM_SW_FWD_EN)) {
856 dev_err(dev->dev, "Failed to enable switch!\n");
857 return -EINVAL;
858 }
859 }
860
861 b53_enable_mib(dev);
862
863 return b53_flush_arl(dev, FAST_AGE_STATIC);
864}
865
866static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
867{
868 struct b53_device *priv = ds->priv;
869 u16 value = 0;
870 int ret;
871
872 if (priv->ops->phy_read16)
873 ret = priv->ops->phy_read16(priv, addr, reg, &value);
874 else
875 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
876 reg * 2, &value);
877
878 return ret ? ret : value;
879}
880
881static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
882{
883 struct b53_device *priv = ds->priv;
884
885 if (priv->ops->phy_write16)
886 return priv->ops->phy_write16(priv, addr, reg, val);
887
888 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
889}
890
891static int b53_reset_switch(struct b53_device *priv)
892{
893 /* reset vlans */
894 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
895 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
896
897 priv->serdes_lane = B53_INVALID_LANE;
898
899 return b53_switch_reset(priv);
900}
901
902static int b53_apply_config(struct b53_device *priv)
903{
904 /* disable switching */
905 b53_set_forwarding(priv, 0);
906
907 b53_configure_vlan(priv->ds);
908
909 /* enable switching */
910 b53_set_forwarding(priv, 1);
911
912 return 0;
913}
914
915static void b53_reset_mib(struct b53_device *priv)
916{
917 u8 gc;
918
919 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
920
921 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
922 msleep(1);
923 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
924 msleep(1);
925}
926
927static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
928{
929 if (is5365(dev))
930 return b53_mibs_65;
931 else if (is63xx(dev))
932 return b53_mibs_63xx;
933 else if (is58xx(dev))
934 return b53_mibs_58xx;
935 else
936 return b53_mibs;
937}
938
939static unsigned int b53_get_mib_size(struct b53_device *dev)
940{
941 if (is5365(dev))
942 return B53_MIBS_65_SIZE;
943 else if (is63xx(dev))
944 return B53_MIBS_63XX_SIZE;
945 else if (is58xx(dev))
946 return B53_MIBS_58XX_SIZE;
947 else
948 return B53_MIBS_SIZE;
949}
950
951static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
952{
953 /* These ports typically do not have built-in PHYs */
954 switch (port) {
955 case B53_CPU_PORT_25:
956 case 7:
957 case B53_CPU_PORT:
958 return NULL;
959 }
960
961 return mdiobus_get_phy(ds->user_mii_bus, port);
962}
963
964void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
965 uint8_t *data)
966{
967 struct b53_device *dev = ds->priv;
968 const struct b53_mib_desc *mibs = b53_get_mib(dev);
969 unsigned int mib_size = b53_get_mib_size(dev);
970 struct phy_device *phydev;
971 unsigned int i;
972
973 if (stringset == ETH_SS_STATS) {
974 for (i = 0; i < mib_size; i++)
975 strscpy(data + i * ETH_GSTRING_LEN,
976 mibs[i].name, ETH_GSTRING_LEN);
977 } else if (stringset == ETH_SS_PHY_STATS) {
978 phydev = b53_get_phy_device(ds, port);
979 if (!phydev)
980 return;
981
982 phy_ethtool_get_strings(phydev, data);
983 }
984}
985EXPORT_SYMBOL(b53_get_strings);
986
987void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
988{
989 struct b53_device *dev = ds->priv;
990 const struct b53_mib_desc *mibs = b53_get_mib(dev);
991 unsigned int mib_size = b53_get_mib_size(dev);
992 const struct b53_mib_desc *s;
993 unsigned int i;
994 u64 val = 0;
995
996 if (is5365(dev) && port == 5)
997 port = 8;
998
999 mutex_lock(&dev->stats_mutex);
1000
1001 for (i = 0; i < mib_size; i++) {
1002 s = &mibs[i];
1003
1004 if (s->size == 8) {
1005 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1006 } else {
1007 u32 val32;
1008
1009 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1010 &val32);
1011 val = val32;
1012 }
1013 data[i] = (u64)val;
1014 }
1015
1016 mutex_unlock(&dev->stats_mutex);
1017}
1018EXPORT_SYMBOL(b53_get_ethtool_stats);
1019
1020void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1021{
1022 struct phy_device *phydev;
1023
1024 phydev = b53_get_phy_device(ds, port);
1025 if (!phydev)
1026 return;
1027
1028 phy_ethtool_get_stats(phydev, NULL, data);
1029}
1030EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1031
1032int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1033{
1034 struct b53_device *dev = ds->priv;
1035 struct phy_device *phydev;
1036
1037 if (sset == ETH_SS_STATS) {
1038 return b53_get_mib_size(dev);
1039 } else if (sset == ETH_SS_PHY_STATS) {
1040 phydev = b53_get_phy_device(ds, port);
1041 if (!phydev)
1042 return 0;
1043
1044 return phy_ethtool_get_sset_count(phydev);
1045 }
1046
1047 return 0;
1048}
1049EXPORT_SYMBOL(b53_get_sset_count);
1050
1051enum b53_devlink_resource_id {
1052 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1053};
1054
1055static u64 b53_devlink_vlan_table_get(void *priv)
1056{
1057 struct b53_device *dev = priv;
1058 struct b53_vlan *vl;
1059 unsigned int i;
1060 u64 count = 0;
1061
1062 for (i = 0; i < dev->num_vlans; i++) {
1063 vl = &dev->vlans[i];
1064 if (vl->members)
1065 count++;
1066 }
1067
1068 return count;
1069}
1070
1071int b53_setup_devlink_resources(struct dsa_switch *ds)
1072{
1073 struct devlink_resource_size_params size_params;
1074 struct b53_device *dev = ds->priv;
1075 int err;
1076
1077 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1078 dev->num_vlans,
1079 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1080
1081 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1082 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1083 DEVLINK_RESOURCE_ID_PARENT_TOP,
1084 &size_params);
1085 if (err)
1086 goto out;
1087
1088 dsa_devlink_resource_occ_get_register(ds,
1089 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1090 b53_devlink_vlan_table_get, dev);
1091
1092 return 0;
1093out:
1094 dsa_devlink_resources_unregister(ds);
1095 return err;
1096}
1097EXPORT_SYMBOL(b53_setup_devlink_resources);
1098
1099static int b53_setup(struct dsa_switch *ds)
1100{
1101 struct b53_device *dev = ds->priv;
1102 unsigned int port;
1103 int ret;
1104
1105 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1106 * which forces the CPU port to be tagged in all VLANs.
1107 */
1108 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1109
1110 ret = b53_reset_switch(dev);
1111 if (ret) {
1112 dev_err(ds->dev, "failed to reset switch\n");
1113 return ret;
1114 }
1115
1116 b53_reset_mib(dev);
1117
1118 ret = b53_apply_config(dev);
1119 if (ret) {
1120 dev_err(ds->dev, "failed to apply configuration\n");
1121 return ret;
1122 }
1123
1124 /* Configure IMP/CPU port, disable all other ports. Enabled
1125 * ports will be configured with .port_enable
1126 */
1127 for (port = 0; port < dev->num_ports; port++) {
1128 if (dsa_is_cpu_port(ds, port))
1129 b53_enable_cpu_port(dev, port);
1130 else
1131 b53_disable_port(ds, port);
1132 }
1133
1134 return b53_setup_devlink_resources(ds);
1135}
1136
1137static void b53_teardown(struct dsa_switch *ds)
1138{
1139 dsa_devlink_resources_unregister(ds);
1140}
1141
1142static void b53_force_link(struct b53_device *dev, int port, int link)
1143{
1144 u8 reg, val, off;
1145
1146 /* Override the port settings */
1147 if (port == dev->imp_port) {
1148 off = B53_PORT_OVERRIDE_CTRL;
1149 val = PORT_OVERRIDE_EN;
1150 } else {
1151 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1152 val = GMII_PO_EN;
1153 }
1154
1155 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1156 reg |= val;
1157 if (link)
1158 reg |= PORT_OVERRIDE_LINK;
1159 else
1160 reg &= ~PORT_OVERRIDE_LINK;
1161 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1162}
1163
1164static void b53_force_port_config(struct b53_device *dev, int port,
1165 int speed, int duplex,
1166 bool tx_pause, bool rx_pause)
1167{
1168 u8 reg, val, off;
1169
1170 /* Override the port settings */
1171 if (port == dev->imp_port) {
1172 off = B53_PORT_OVERRIDE_CTRL;
1173 val = PORT_OVERRIDE_EN;
1174 } else {
1175 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1176 val = GMII_PO_EN;
1177 }
1178
1179 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1180 reg |= val;
1181 if (duplex == DUPLEX_FULL)
1182 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1183 else
1184 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1185
1186 switch (speed) {
1187 case 2000:
1188 reg |= PORT_OVERRIDE_SPEED_2000M;
1189 fallthrough;
1190 case SPEED_1000:
1191 reg |= PORT_OVERRIDE_SPEED_1000M;
1192 break;
1193 case SPEED_100:
1194 reg |= PORT_OVERRIDE_SPEED_100M;
1195 break;
1196 case SPEED_10:
1197 reg |= PORT_OVERRIDE_SPEED_10M;
1198 break;
1199 default:
1200 dev_err(dev->dev, "unknown speed: %d\n", speed);
1201 return;
1202 }
1203
1204 if (rx_pause)
1205 reg |= PORT_OVERRIDE_RX_FLOW;
1206 if (tx_pause)
1207 reg |= PORT_OVERRIDE_TX_FLOW;
1208
1209 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1210}
1211
1212static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1213 phy_interface_t interface)
1214{
1215 struct b53_device *dev = ds->priv;
1216 u8 rgmii_ctrl = 0, off;
1217
1218 if (port == dev->imp_port)
1219 off = B53_RGMII_CTRL_IMP;
1220 else
1221 off = B53_RGMII_CTRL_P(port);
1222
1223 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1224
1225 switch (interface) {
1226 case PHY_INTERFACE_MODE_RGMII_ID:
1227 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1228 break;
1229 case PHY_INTERFACE_MODE_RGMII_RXID:
1230 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC);
1231 rgmii_ctrl |= RGMII_CTRL_DLL_RXC;
1232 break;
1233 case PHY_INTERFACE_MODE_RGMII_TXID:
1234 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC);
1235 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1236 break;
1237 case PHY_INTERFACE_MODE_RGMII:
1238 default:
1239 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1240 break;
1241 }
1242
1243 if (port != dev->imp_port) {
1244 if (is63268(dev))
1245 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1246
1247 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1248 }
1249
1250 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1251
1252 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1253 phy_modes(interface));
1254}
1255
1256static void b53_adjust_link(struct dsa_switch *ds, int port,
1257 struct phy_device *phydev)
1258{
1259 struct b53_device *dev = ds->priv;
1260 struct ethtool_eee *p = &dev->ports[port].eee;
1261 u8 rgmii_ctrl = 0, reg = 0, off;
1262 bool tx_pause = false;
1263 bool rx_pause = false;
1264
1265 if (!phy_is_pseudo_fixed_link(phydev))
1266 return;
1267
1268 /* Enable flow control on BCM5301x's CPU port */
1269 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1270 tx_pause = rx_pause = true;
1271
1272 if (phydev->pause) {
1273 if (phydev->asym_pause)
1274 tx_pause = true;
1275 rx_pause = true;
1276 }
1277
1278 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1279 tx_pause, rx_pause);
1280 b53_force_link(dev, port, phydev->link);
1281
1282 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1283 b53_adjust_63xx_rgmii(ds, port, phydev->interface);
1284
1285 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1286 if (port == dev->imp_port)
1287 off = B53_RGMII_CTRL_IMP;
1288 else
1289 off = B53_RGMII_CTRL_P(port);
1290
1291 /* Configure the port RGMII clock delay by DLL disabled and
1292 * tx_clk aligned timing (restoring to reset defaults)
1293 */
1294 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1295 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1296 RGMII_CTRL_TIMING_SEL);
1297
1298 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1299 * sure that we enable the port TX clock internal delay to
1300 * account for this internal delay that is inserted, otherwise
1301 * the switch won't be able to receive correctly.
1302 *
1303 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1304 * any delay neither on transmission nor reception, so the
1305 * BCM53125 must also be configured accordingly to account for
1306 * the lack of delay and introduce
1307 *
1308 * The BCM53125 switch has its RX clock and TX clock control
1309 * swapped, hence the reason why we modify the TX clock path in
1310 * the "RGMII" case
1311 */
1312 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1313 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1314 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1315 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1316 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1317 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1318
1319 dev_info(ds->dev, "Configured port %d for %s\n", port,
1320 phy_modes(phydev->interface));
1321 }
1322
1323 /* configure MII port if necessary */
1324 if (is5325(dev)) {
1325 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1326 ®);
1327
1328 /* reverse mii needs to be enabled */
1329 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1330 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1331 reg | PORT_OVERRIDE_RV_MII_25);
1332 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1333 ®);
1334
1335 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1336 dev_err(ds->dev,
1337 "Failed to enable reverse MII mode\n");
1338 return;
1339 }
1340 }
1341 }
1342
1343 /* Re-negotiate EEE if it was enabled already */
1344 p->eee_enabled = b53_eee_init(ds, port, phydev);
1345}
1346
1347void b53_port_event(struct dsa_switch *ds, int port)
1348{
1349 struct b53_device *dev = ds->priv;
1350 bool link;
1351 u16 sts;
1352
1353 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1354 link = !!(sts & BIT(port));
1355 dsa_port_phylink_mac_change(ds, port, link);
1356}
1357EXPORT_SYMBOL(b53_port_event);
1358
1359static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1360 struct phylink_config *config)
1361{
1362 struct b53_device *dev = ds->priv;
1363
1364 /* Internal ports need GMII for PHYLIB */
1365 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1366
1367 /* These switches appear to support MII and RevMII too, but beyond
1368 * this, the code gives very few clues. FIXME: We probably need more
1369 * interface modes here.
1370 *
1371 * According to b53_srab_mux_init(), ports 3..5 can support:
1372 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1373 * However, the interface mode read from the MUX configuration is
1374 * not passed back to DSA, so phylink uses NA.
1375 * DT can specify RGMII for ports 0, 1.
1376 * For MDIO, port 8 can be RGMII_TXID.
1377 */
1378 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1379 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1380
1381 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1382 MAC_10 | MAC_100;
1383
1384 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1385 * Note: the original code also exclulded Gigagbit for MII, RevMII
1386 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1387 * so will be excluded by the generic validator implementation.
1388 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1389 */
1390 if (!(is5325(dev) || is5365(dev)))
1391 config->mac_capabilities |= MAC_1000;
1392
1393 /* Get the implementation specific capabilities */
1394 if (dev->ops->phylink_get_caps)
1395 dev->ops->phylink_get_caps(dev, port, config);
1396}
1397
1398static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
1399 int port,
1400 phy_interface_t interface)
1401{
1402 struct b53_device *dev = ds->priv;
1403
1404 if (!dev->ops->phylink_mac_select_pcs)
1405 return NULL;
1406
1407 return dev->ops->phylink_mac_select_pcs(dev, port, interface);
1408}
1409
1410void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1411 unsigned int mode,
1412 const struct phylink_link_state *state)
1413{
1414}
1415EXPORT_SYMBOL(b53_phylink_mac_config);
1416
1417void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1418 unsigned int mode,
1419 phy_interface_t interface)
1420{
1421 struct b53_device *dev = ds->priv;
1422
1423 if (mode == MLO_AN_PHY)
1424 return;
1425
1426 if (mode == MLO_AN_FIXED) {
1427 b53_force_link(dev, port, false);
1428 return;
1429 }
1430
1431 if (phy_interface_mode_is_8023z(interface) &&
1432 dev->ops->serdes_link_set)
1433 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1434}
1435EXPORT_SYMBOL(b53_phylink_mac_link_down);
1436
1437void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1438 unsigned int mode,
1439 phy_interface_t interface,
1440 struct phy_device *phydev,
1441 int speed, int duplex,
1442 bool tx_pause, bool rx_pause)
1443{
1444 struct b53_device *dev = ds->priv;
1445
1446 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1447 b53_adjust_63xx_rgmii(ds, port, interface);
1448
1449 if (mode == MLO_AN_PHY)
1450 return;
1451
1452 if (mode == MLO_AN_FIXED) {
1453 b53_force_port_config(dev, port, speed, duplex,
1454 tx_pause, rx_pause);
1455 b53_force_link(dev, port, true);
1456 return;
1457 }
1458
1459 if (phy_interface_mode_is_8023z(interface) &&
1460 dev->ops->serdes_link_set)
1461 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1462}
1463EXPORT_SYMBOL(b53_phylink_mac_link_up);
1464
1465int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1466 struct netlink_ext_ack *extack)
1467{
1468 struct b53_device *dev = ds->priv;
1469
1470 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1471
1472 return 0;
1473}
1474EXPORT_SYMBOL(b53_vlan_filtering);
1475
1476static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1477 const struct switchdev_obj_port_vlan *vlan)
1478{
1479 struct b53_device *dev = ds->priv;
1480
1481 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1482 return -EOPNOTSUPP;
1483
1484 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1485 * receiving VLAN tagged frames at all, we can still allow the port to
1486 * be configured for egress untagged.
1487 */
1488 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1489 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1490 return -EINVAL;
1491
1492 if (vlan->vid >= dev->num_vlans)
1493 return -ERANGE;
1494
1495 b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1496
1497 return 0;
1498}
1499
1500int b53_vlan_add(struct dsa_switch *ds, int port,
1501 const struct switchdev_obj_port_vlan *vlan,
1502 struct netlink_ext_ack *extack)
1503{
1504 struct b53_device *dev = ds->priv;
1505 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1506 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1507 struct b53_vlan *vl;
1508 int err;
1509
1510 err = b53_vlan_prepare(ds, port, vlan);
1511 if (err)
1512 return err;
1513
1514 vl = &dev->vlans[vlan->vid];
1515
1516 b53_get_vlan_entry(dev, vlan->vid, vl);
1517
1518 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1519 untagged = true;
1520
1521 vl->members |= BIT(port);
1522 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1523 vl->untag |= BIT(port);
1524 else
1525 vl->untag &= ~BIT(port);
1526
1527 b53_set_vlan_entry(dev, vlan->vid, vl);
1528 b53_fast_age_vlan(dev, vlan->vid);
1529
1530 if (pvid && !dsa_is_cpu_port(ds, port)) {
1531 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1532 vlan->vid);
1533 b53_fast_age_vlan(dev, vlan->vid);
1534 }
1535
1536 return 0;
1537}
1538EXPORT_SYMBOL(b53_vlan_add);
1539
1540int b53_vlan_del(struct dsa_switch *ds, int port,
1541 const struct switchdev_obj_port_vlan *vlan)
1542{
1543 struct b53_device *dev = ds->priv;
1544 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1545 struct b53_vlan *vl;
1546 u16 pvid;
1547
1548 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1549
1550 vl = &dev->vlans[vlan->vid];
1551
1552 b53_get_vlan_entry(dev, vlan->vid, vl);
1553
1554 vl->members &= ~BIT(port);
1555
1556 if (pvid == vlan->vid)
1557 pvid = b53_default_pvid(dev);
1558
1559 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1560 vl->untag &= ~(BIT(port));
1561
1562 b53_set_vlan_entry(dev, vlan->vid, vl);
1563 b53_fast_age_vlan(dev, vlan->vid);
1564
1565 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1566 b53_fast_age_vlan(dev, pvid);
1567
1568 return 0;
1569}
1570EXPORT_SYMBOL(b53_vlan_del);
1571
1572/* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
1573static int b53_arl_op_wait(struct b53_device *dev)
1574{
1575 unsigned int timeout = 10;
1576 u8 reg;
1577
1578 do {
1579 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1580 if (!(reg & ARLTBL_START_DONE))
1581 return 0;
1582
1583 usleep_range(1000, 2000);
1584 } while (timeout--);
1585
1586 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1587
1588 return -ETIMEDOUT;
1589}
1590
1591static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1592{
1593 u8 reg;
1594
1595 if (op > ARLTBL_RW)
1596 return -EINVAL;
1597
1598 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1599 reg |= ARLTBL_START_DONE;
1600 if (op)
1601 reg |= ARLTBL_RW;
1602 else
1603 reg &= ~ARLTBL_RW;
1604 if (dev->vlan_enabled)
1605 reg &= ~ARLTBL_IVL_SVL_SELECT;
1606 else
1607 reg |= ARLTBL_IVL_SVL_SELECT;
1608 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1609
1610 return b53_arl_op_wait(dev);
1611}
1612
1613static int b53_arl_read(struct b53_device *dev, u64 mac,
1614 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1615{
1616 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1617 unsigned int i;
1618 int ret;
1619
1620 ret = b53_arl_op_wait(dev);
1621 if (ret)
1622 return ret;
1623
1624 bitmap_zero(free_bins, dev->num_arl_bins);
1625
1626 /* Read the bins */
1627 for (i = 0; i < dev->num_arl_bins; i++) {
1628 u64 mac_vid;
1629 u32 fwd_entry;
1630
1631 b53_read64(dev, B53_ARLIO_PAGE,
1632 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1633 b53_read32(dev, B53_ARLIO_PAGE,
1634 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1635 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1636
1637 if (!(fwd_entry & ARLTBL_VALID)) {
1638 set_bit(i, free_bins);
1639 continue;
1640 }
1641 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1642 continue;
1643 if (dev->vlan_enabled &&
1644 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1645 continue;
1646 *idx = i;
1647 return 0;
1648 }
1649
1650 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1651 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1652}
1653
1654static int b53_arl_op(struct b53_device *dev, int op, int port,
1655 const unsigned char *addr, u16 vid, bool is_valid)
1656{
1657 struct b53_arl_entry ent;
1658 u32 fwd_entry;
1659 u64 mac, mac_vid = 0;
1660 u8 idx = 0;
1661 int ret;
1662
1663 /* Convert the array into a 64-bit MAC */
1664 mac = ether_addr_to_u64(addr);
1665
1666 /* Perform a read for the given MAC and VID */
1667 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1668 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1669
1670 /* Issue a read operation for this MAC */
1671 ret = b53_arl_rw_op(dev, 1);
1672 if (ret)
1673 return ret;
1674
1675 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1676
1677 /* If this is a read, just finish now */
1678 if (op)
1679 return ret;
1680
1681 switch (ret) {
1682 case -ETIMEDOUT:
1683 return ret;
1684 case -ENOSPC:
1685 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1686 addr, vid);
1687 return is_valid ? ret : 0;
1688 case -ENOENT:
1689 /* We could not find a matching MAC, so reset to a new entry */
1690 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1691 addr, vid, idx);
1692 fwd_entry = 0;
1693 break;
1694 default:
1695 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1696 addr, vid, idx);
1697 break;
1698 }
1699
1700 /* For multicast address, the port is a bitmask and the validity
1701 * is determined by having at least one port being still active
1702 */
1703 if (!is_multicast_ether_addr(addr)) {
1704 ent.port = port;
1705 ent.is_valid = is_valid;
1706 } else {
1707 if (is_valid)
1708 ent.port |= BIT(port);
1709 else
1710 ent.port &= ~BIT(port);
1711
1712 ent.is_valid = !!(ent.port);
1713 }
1714
1715 ent.vid = vid;
1716 ent.is_static = true;
1717 ent.is_age = false;
1718 memcpy(ent.mac, addr, ETH_ALEN);
1719 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1720
1721 b53_write64(dev, B53_ARLIO_PAGE,
1722 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1723 b53_write32(dev, B53_ARLIO_PAGE,
1724 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1725
1726 return b53_arl_rw_op(dev, 0);
1727}
1728
1729int b53_fdb_add(struct dsa_switch *ds, int port,
1730 const unsigned char *addr, u16 vid,
1731 struct dsa_db db)
1732{
1733 struct b53_device *priv = ds->priv;
1734 int ret;
1735
1736 /* 5325 and 5365 require some more massaging, but could
1737 * be supported eventually
1738 */
1739 if (is5325(priv) || is5365(priv))
1740 return -EOPNOTSUPP;
1741
1742 mutex_lock(&priv->arl_mutex);
1743 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1744 mutex_unlock(&priv->arl_mutex);
1745
1746 return ret;
1747}
1748EXPORT_SYMBOL(b53_fdb_add);
1749
1750int b53_fdb_del(struct dsa_switch *ds, int port,
1751 const unsigned char *addr, u16 vid,
1752 struct dsa_db db)
1753{
1754 struct b53_device *priv = ds->priv;
1755 int ret;
1756
1757 mutex_lock(&priv->arl_mutex);
1758 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1759 mutex_unlock(&priv->arl_mutex);
1760
1761 return ret;
1762}
1763EXPORT_SYMBOL(b53_fdb_del);
1764
1765static int b53_arl_search_wait(struct b53_device *dev)
1766{
1767 unsigned int timeout = 1000;
1768 u8 reg;
1769
1770 do {
1771 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1772 if (!(reg & ARL_SRCH_STDN))
1773 return 0;
1774
1775 if (reg & ARL_SRCH_VLID)
1776 return 0;
1777
1778 usleep_range(1000, 2000);
1779 } while (timeout--);
1780
1781 return -ETIMEDOUT;
1782}
1783
1784static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1785 struct b53_arl_entry *ent)
1786{
1787 u64 mac_vid;
1788 u32 fwd_entry;
1789
1790 b53_read64(dev, B53_ARLIO_PAGE,
1791 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1792 b53_read32(dev, B53_ARLIO_PAGE,
1793 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1794 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1795}
1796
1797static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1798 dsa_fdb_dump_cb_t *cb, void *data)
1799{
1800 if (!ent->is_valid)
1801 return 0;
1802
1803 if (port != ent->port)
1804 return 0;
1805
1806 return cb(ent->mac, ent->vid, ent->is_static, data);
1807}
1808
1809int b53_fdb_dump(struct dsa_switch *ds, int port,
1810 dsa_fdb_dump_cb_t *cb, void *data)
1811{
1812 struct b53_device *priv = ds->priv;
1813 struct b53_arl_entry results[2];
1814 unsigned int count = 0;
1815 int ret;
1816 u8 reg;
1817
1818 mutex_lock(&priv->arl_mutex);
1819
1820 /* Start search operation */
1821 reg = ARL_SRCH_STDN;
1822 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1823
1824 do {
1825 ret = b53_arl_search_wait(priv);
1826 if (ret)
1827 break;
1828
1829 b53_arl_search_rd(priv, 0, &results[0]);
1830 ret = b53_fdb_copy(port, &results[0], cb, data);
1831 if (ret)
1832 break;
1833
1834 if (priv->num_arl_bins > 2) {
1835 b53_arl_search_rd(priv, 1, &results[1]);
1836 ret = b53_fdb_copy(port, &results[1], cb, data);
1837 if (ret)
1838 break;
1839
1840 if (!results[0].is_valid && !results[1].is_valid)
1841 break;
1842 }
1843
1844 } while (count++ < b53_max_arl_entries(priv) / 2);
1845
1846 mutex_unlock(&priv->arl_mutex);
1847
1848 return 0;
1849}
1850EXPORT_SYMBOL(b53_fdb_dump);
1851
1852int b53_mdb_add(struct dsa_switch *ds, int port,
1853 const struct switchdev_obj_port_mdb *mdb,
1854 struct dsa_db db)
1855{
1856 struct b53_device *priv = ds->priv;
1857 int ret;
1858
1859 /* 5325 and 5365 require some more massaging, but could
1860 * be supported eventually
1861 */
1862 if (is5325(priv) || is5365(priv))
1863 return -EOPNOTSUPP;
1864
1865 mutex_lock(&priv->arl_mutex);
1866 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1867 mutex_unlock(&priv->arl_mutex);
1868
1869 return ret;
1870}
1871EXPORT_SYMBOL(b53_mdb_add);
1872
1873int b53_mdb_del(struct dsa_switch *ds, int port,
1874 const struct switchdev_obj_port_mdb *mdb,
1875 struct dsa_db db)
1876{
1877 struct b53_device *priv = ds->priv;
1878 int ret;
1879
1880 mutex_lock(&priv->arl_mutex);
1881 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1882 mutex_unlock(&priv->arl_mutex);
1883 if (ret)
1884 dev_err(ds->dev, "failed to delete MDB entry\n");
1885
1886 return ret;
1887}
1888EXPORT_SYMBOL(b53_mdb_del);
1889
1890int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1891 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1892{
1893 struct b53_device *dev = ds->priv;
1894 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1895 u16 pvlan, reg;
1896 unsigned int i;
1897
1898 /* On 7278, port 7 which connects to the ASP should only receive
1899 * traffic from matching CFP rules.
1900 */
1901 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1902 return -EINVAL;
1903
1904 /* Make this port leave the all VLANs join since we will have proper
1905 * VLAN entries from now on
1906 */
1907 if (is58xx(dev)) {
1908 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1909 reg &= ~BIT(port);
1910 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1911 reg &= ~BIT(cpu_port);
1912 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1913 }
1914
1915 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1916
1917 b53_for_each_port(dev, i) {
1918 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1919 continue;
1920
1921 /* Add this local port to the remote port VLAN control
1922 * membership and update the remote port bitmask
1923 */
1924 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1925 reg |= BIT(port);
1926 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1927 dev->ports[i].vlan_ctl_mask = reg;
1928
1929 pvlan |= BIT(i);
1930 }
1931
1932 /* Configure the local port VLAN control membership to include
1933 * remote ports and update the local port bitmask
1934 */
1935 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1936 dev->ports[port].vlan_ctl_mask = pvlan;
1937
1938 return 0;
1939}
1940EXPORT_SYMBOL(b53_br_join);
1941
1942void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1943{
1944 struct b53_device *dev = ds->priv;
1945 struct b53_vlan *vl = &dev->vlans[0];
1946 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1947 unsigned int i;
1948 u16 pvlan, reg, pvid;
1949
1950 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1951
1952 b53_for_each_port(dev, i) {
1953 /* Don't touch the remaining ports */
1954 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1955 continue;
1956
1957 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1958 reg &= ~BIT(port);
1959 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1960 dev->ports[port].vlan_ctl_mask = reg;
1961
1962 /* Prevent self removal to preserve isolation */
1963 if (port != i)
1964 pvlan &= ~BIT(i);
1965 }
1966
1967 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1968 dev->ports[port].vlan_ctl_mask = pvlan;
1969
1970 pvid = b53_default_pvid(dev);
1971
1972 /* Make this port join all VLANs without VLAN entries */
1973 if (is58xx(dev)) {
1974 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1975 reg |= BIT(port);
1976 if (!(reg & BIT(cpu_port)))
1977 reg |= BIT(cpu_port);
1978 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1979 } else {
1980 b53_get_vlan_entry(dev, pvid, vl);
1981 vl->members |= BIT(port) | BIT(cpu_port);
1982 vl->untag |= BIT(port) | BIT(cpu_port);
1983 b53_set_vlan_entry(dev, pvid, vl);
1984 }
1985}
1986EXPORT_SYMBOL(b53_br_leave);
1987
1988void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1989{
1990 struct b53_device *dev = ds->priv;
1991 u8 hw_state;
1992 u8 reg;
1993
1994 switch (state) {
1995 case BR_STATE_DISABLED:
1996 hw_state = PORT_CTRL_DIS_STATE;
1997 break;
1998 case BR_STATE_LISTENING:
1999 hw_state = PORT_CTRL_LISTEN_STATE;
2000 break;
2001 case BR_STATE_LEARNING:
2002 hw_state = PORT_CTRL_LEARN_STATE;
2003 break;
2004 case BR_STATE_FORWARDING:
2005 hw_state = PORT_CTRL_FWD_STATE;
2006 break;
2007 case BR_STATE_BLOCKING:
2008 hw_state = PORT_CTRL_BLOCK_STATE;
2009 break;
2010 default:
2011 dev_err(ds->dev, "invalid STP state: %d\n", state);
2012 return;
2013 }
2014
2015 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
2016 reg &= ~PORT_CTRL_STP_STATE_MASK;
2017 reg |= hw_state;
2018 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2019}
2020EXPORT_SYMBOL(b53_br_set_stp_state);
2021
2022void b53_br_fast_age(struct dsa_switch *ds, int port)
2023{
2024 struct b53_device *dev = ds->priv;
2025
2026 if (b53_fast_age_port(dev, port))
2027 dev_err(ds->dev, "fast ageing failed\n");
2028}
2029EXPORT_SYMBOL(b53_br_fast_age);
2030
2031int b53_br_flags_pre(struct dsa_switch *ds, int port,
2032 struct switchdev_brport_flags flags,
2033 struct netlink_ext_ack *extack)
2034{
2035 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
2036 return -EINVAL;
2037
2038 return 0;
2039}
2040EXPORT_SYMBOL(b53_br_flags_pre);
2041
2042int b53_br_flags(struct dsa_switch *ds, int port,
2043 struct switchdev_brport_flags flags,
2044 struct netlink_ext_ack *extack)
2045{
2046 if (flags.mask & BR_FLOOD)
2047 b53_port_set_ucast_flood(ds->priv, port,
2048 !!(flags.val & BR_FLOOD));
2049 if (flags.mask & BR_MCAST_FLOOD)
2050 b53_port_set_mcast_flood(ds->priv, port,
2051 !!(flags.val & BR_MCAST_FLOOD));
2052 if (flags.mask & BR_LEARNING)
2053 b53_port_set_learning(ds->priv, port,
2054 !!(flags.val & BR_LEARNING));
2055
2056 return 0;
2057}
2058EXPORT_SYMBOL(b53_br_flags);
2059
2060static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2061{
2062 /* Broadcom switches will accept enabling Broadcom tags on the
2063 * following ports: 5, 7 and 8, any other port is not supported
2064 */
2065 switch (port) {
2066 case B53_CPU_PORT_25:
2067 case 7:
2068 case B53_CPU_PORT:
2069 return true;
2070 }
2071
2072 return false;
2073}
2074
2075static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2076 enum dsa_tag_protocol tag_protocol)
2077{
2078 bool ret = b53_possible_cpu_port(ds, port);
2079
2080 if (!ret) {
2081 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2082 port);
2083 return ret;
2084 }
2085
2086 switch (tag_protocol) {
2087 case DSA_TAG_PROTO_BRCM:
2088 case DSA_TAG_PROTO_BRCM_PREPEND:
2089 dev_warn(ds->dev,
2090 "Port %d is stacked to Broadcom tag switch\n", port);
2091 ret = false;
2092 break;
2093 default:
2094 ret = true;
2095 break;
2096 }
2097
2098 return ret;
2099}
2100
2101enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2102 enum dsa_tag_protocol mprot)
2103{
2104 struct b53_device *dev = ds->priv;
2105
2106 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2107 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2108 goto out;
2109 }
2110
2111 /* Older models require a different 6 byte tag */
2112 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2113 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2114 goto out;
2115 }
2116
2117 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2118 * which requires us to use the prepended Broadcom tag type
2119 */
2120 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2121 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2122 goto out;
2123 }
2124
2125 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2126out:
2127 return dev->tag_protocol;
2128}
2129EXPORT_SYMBOL(b53_get_tag_protocol);
2130
2131int b53_mirror_add(struct dsa_switch *ds, int port,
2132 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2133 struct netlink_ext_ack *extack)
2134{
2135 struct b53_device *dev = ds->priv;
2136 u16 reg, loc;
2137
2138 if (ingress)
2139 loc = B53_IG_MIR_CTL;
2140 else
2141 loc = B53_EG_MIR_CTL;
2142
2143 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2144 reg |= BIT(port);
2145 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2146
2147 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2148 reg &= ~CAP_PORT_MASK;
2149 reg |= mirror->to_local_port;
2150 reg |= MIRROR_EN;
2151 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2152
2153 return 0;
2154}
2155EXPORT_SYMBOL(b53_mirror_add);
2156
2157void b53_mirror_del(struct dsa_switch *ds, int port,
2158 struct dsa_mall_mirror_tc_entry *mirror)
2159{
2160 struct b53_device *dev = ds->priv;
2161 bool loc_disable = false, other_loc_disable = false;
2162 u16 reg, loc;
2163
2164 if (mirror->ingress)
2165 loc = B53_IG_MIR_CTL;
2166 else
2167 loc = B53_EG_MIR_CTL;
2168
2169 /* Update the desired ingress/egress register */
2170 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2171 reg &= ~BIT(port);
2172 if (!(reg & MIRROR_MASK))
2173 loc_disable = true;
2174 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2175
2176 /* Now look at the other one to know if we can disable mirroring
2177 * entirely
2178 */
2179 if (mirror->ingress)
2180 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2181 else
2182 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2183 if (!(reg & MIRROR_MASK))
2184 other_loc_disable = true;
2185
2186 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2187 /* Both no longer have ports, let's disable mirroring */
2188 if (loc_disable && other_loc_disable) {
2189 reg &= ~MIRROR_EN;
2190 reg &= ~mirror->to_local_port;
2191 }
2192 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2193}
2194EXPORT_SYMBOL(b53_mirror_del);
2195
2196void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2197{
2198 struct b53_device *dev = ds->priv;
2199 u16 reg;
2200
2201 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
2202 if (enable)
2203 reg |= BIT(port);
2204 else
2205 reg &= ~BIT(port);
2206 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2207}
2208EXPORT_SYMBOL(b53_eee_enable_set);
2209
2210
2211/* Returns 0 if EEE was not enabled, or 1 otherwise
2212 */
2213int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2214{
2215 int ret;
2216
2217 ret = phy_init_eee(phy, false);
2218 if (ret)
2219 return 0;
2220
2221 b53_eee_enable_set(ds, port, true);
2222
2223 return 1;
2224}
2225EXPORT_SYMBOL(b53_eee_init);
2226
2227int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2228{
2229 struct b53_device *dev = ds->priv;
2230 struct ethtool_eee *p = &dev->ports[port].eee;
2231 u16 reg;
2232
2233 if (is5325(dev) || is5365(dev))
2234 return -EOPNOTSUPP;
2235
2236 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
2237 e->eee_enabled = p->eee_enabled;
2238 e->eee_active = !!(reg & BIT(port));
2239
2240 return 0;
2241}
2242EXPORT_SYMBOL(b53_get_mac_eee);
2243
2244int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2245{
2246 struct b53_device *dev = ds->priv;
2247 struct ethtool_eee *p = &dev->ports[port].eee;
2248
2249 if (is5325(dev) || is5365(dev))
2250 return -EOPNOTSUPP;
2251
2252 p->eee_enabled = e->eee_enabled;
2253 b53_eee_enable_set(ds, port, e->eee_enabled);
2254
2255 return 0;
2256}
2257EXPORT_SYMBOL(b53_set_mac_eee);
2258
2259static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2260{
2261 struct b53_device *dev = ds->priv;
2262 bool enable_jumbo;
2263 bool allow_10_100;
2264
2265 if (is5325(dev) || is5365(dev))
2266 return -EOPNOTSUPP;
2267
2268 enable_jumbo = (mtu >= JMS_MIN_SIZE);
2269 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2270
2271 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2272}
2273
2274static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2275{
2276 return JMS_MAX_SIZE;
2277}
2278
2279static const struct dsa_switch_ops b53_switch_ops = {
2280 .get_tag_protocol = b53_get_tag_protocol,
2281 .setup = b53_setup,
2282 .teardown = b53_teardown,
2283 .get_strings = b53_get_strings,
2284 .get_ethtool_stats = b53_get_ethtool_stats,
2285 .get_sset_count = b53_get_sset_count,
2286 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2287 .phy_read = b53_phy_read16,
2288 .phy_write = b53_phy_write16,
2289 .adjust_link = b53_adjust_link,
2290 .phylink_get_caps = b53_phylink_get_caps,
2291 .phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
2292 .phylink_mac_config = b53_phylink_mac_config,
2293 .phylink_mac_link_down = b53_phylink_mac_link_down,
2294 .phylink_mac_link_up = b53_phylink_mac_link_up,
2295 .port_enable = b53_enable_port,
2296 .port_disable = b53_disable_port,
2297 .get_mac_eee = b53_get_mac_eee,
2298 .set_mac_eee = b53_set_mac_eee,
2299 .port_bridge_join = b53_br_join,
2300 .port_bridge_leave = b53_br_leave,
2301 .port_pre_bridge_flags = b53_br_flags_pre,
2302 .port_bridge_flags = b53_br_flags,
2303 .port_stp_state_set = b53_br_set_stp_state,
2304 .port_fast_age = b53_br_fast_age,
2305 .port_vlan_filtering = b53_vlan_filtering,
2306 .port_vlan_add = b53_vlan_add,
2307 .port_vlan_del = b53_vlan_del,
2308 .port_fdb_dump = b53_fdb_dump,
2309 .port_fdb_add = b53_fdb_add,
2310 .port_fdb_del = b53_fdb_del,
2311 .port_mirror_add = b53_mirror_add,
2312 .port_mirror_del = b53_mirror_del,
2313 .port_mdb_add = b53_mdb_add,
2314 .port_mdb_del = b53_mdb_del,
2315 .port_max_mtu = b53_get_max_mtu,
2316 .port_change_mtu = b53_change_mtu,
2317};
2318
2319struct b53_chip_data {
2320 u32 chip_id;
2321 const char *dev_name;
2322 u16 vlans;
2323 u16 enabled_ports;
2324 u8 imp_port;
2325 u8 cpu_port;
2326 u8 vta_regs[3];
2327 u8 arl_bins;
2328 u16 arl_buckets;
2329 u8 duplex_reg;
2330 u8 jumbo_pm_reg;
2331 u8 jumbo_size_reg;
2332};
2333
2334#define B53_VTA_REGS \
2335 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2336#define B53_VTA_REGS_9798 \
2337 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2338#define B53_VTA_REGS_63XX \
2339 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2340
2341static const struct b53_chip_data b53_switch_chips[] = {
2342 {
2343 .chip_id = BCM5325_DEVICE_ID,
2344 .dev_name = "BCM5325",
2345 .vlans = 16,
2346 .enabled_ports = 0x3f,
2347 .arl_bins = 2,
2348 .arl_buckets = 1024,
2349 .imp_port = 5,
2350 .duplex_reg = B53_DUPLEX_STAT_FE,
2351 },
2352 {
2353 .chip_id = BCM5365_DEVICE_ID,
2354 .dev_name = "BCM5365",
2355 .vlans = 256,
2356 .enabled_ports = 0x3f,
2357 .arl_bins = 2,
2358 .arl_buckets = 1024,
2359 .imp_port = 5,
2360 .duplex_reg = B53_DUPLEX_STAT_FE,
2361 },
2362 {
2363 .chip_id = BCM5389_DEVICE_ID,
2364 .dev_name = "BCM5389",
2365 .vlans = 4096,
2366 .enabled_ports = 0x11f,
2367 .arl_bins = 4,
2368 .arl_buckets = 1024,
2369 .imp_port = 8,
2370 .vta_regs = B53_VTA_REGS,
2371 .duplex_reg = B53_DUPLEX_STAT_GE,
2372 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2373 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2374 },
2375 {
2376 .chip_id = BCM5395_DEVICE_ID,
2377 .dev_name = "BCM5395",
2378 .vlans = 4096,
2379 .enabled_ports = 0x11f,
2380 .arl_bins = 4,
2381 .arl_buckets = 1024,
2382 .imp_port = 8,
2383 .vta_regs = B53_VTA_REGS,
2384 .duplex_reg = B53_DUPLEX_STAT_GE,
2385 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2386 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2387 },
2388 {
2389 .chip_id = BCM5397_DEVICE_ID,
2390 .dev_name = "BCM5397",
2391 .vlans = 4096,
2392 .enabled_ports = 0x11f,
2393 .arl_bins = 4,
2394 .arl_buckets = 1024,
2395 .imp_port = 8,
2396 .vta_regs = B53_VTA_REGS_9798,
2397 .duplex_reg = B53_DUPLEX_STAT_GE,
2398 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2399 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2400 },
2401 {
2402 .chip_id = BCM5398_DEVICE_ID,
2403 .dev_name = "BCM5398",
2404 .vlans = 4096,
2405 .enabled_ports = 0x17f,
2406 .arl_bins = 4,
2407 .arl_buckets = 1024,
2408 .imp_port = 8,
2409 .vta_regs = B53_VTA_REGS_9798,
2410 .duplex_reg = B53_DUPLEX_STAT_GE,
2411 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2412 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2413 },
2414 {
2415 .chip_id = BCM53115_DEVICE_ID,
2416 .dev_name = "BCM53115",
2417 .vlans = 4096,
2418 .enabled_ports = 0x11f,
2419 .arl_bins = 4,
2420 .arl_buckets = 1024,
2421 .vta_regs = B53_VTA_REGS,
2422 .imp_port = 8,
2423 .duplex_reg = B53_DUPLEX_STAT_GE,
2424 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2425 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2426 },
2427 {
2428 .chip_id = BCM53125_DEVICE_ID,
2429 .dev_name = "BCM53125",
2430 .vlans = 4096,
2431 .enabled_ports = 0x1ff,
2432 .arl_bins = 4,
2433 .arl_buckets = 1024,
2434 .imp_port = 8,
2435 .vta_regs = B53_VTA_REGS,
2436 .duplex_reg = B53_DUPLEX_STAT_GE,
2437 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2438 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2439 },
2440 {
2441 .chip_id = BCM53128_DEVICE_ID,
2442 .dev_name = "BCM53128",
2443 .vlans = 4096,
2444 .enabled_ports = 0x1ff,
2445 .arl_bins = 4,
2446 .arl_buckets = 1024,
2447 .imp_port = 8,
2448 .vta_regs = B53_VTA_REGS,
2449 .duplex_reg = B53_DUPLEX_STAT_GE,
2450 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2451 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2452 },
2453 {
2454 .chip_id = BCM63XX_DEVICE_ID,
2455 .dev_name = "BCM63xx",
2456 .vlans = 4096,
2457 .enabled_ports = 0, /* pdata must provide them */
2458 .arl_bins = 4,
2459 .arl_buckets = 1024,
2460 .imp_port = 8,
2461 .vta_regs = B53_VTA_REGS_63XX,
2462 .duplex_reg = B53_DUPLEX_STAT_63XX,
2463 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2464 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2465 },
2466 {
2467 .chip_id = BCM63268_DEVICE_ID,
2468 .dev_name = "BCM63268",
2469 .vlans = 4096,
2470 .enabled_ports = 0, /* pdata must provide them */
2471 .arl_bins = 4,
2472 .arl_buckets = 1024,
2473 .imp_port = 8,
2474 .vta_regs = B53_VTA_REGS_63XX,
2475 .duplex_reg = B53_DUPLEX_STAT_63XX,
2476 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2477 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2478 },
2479 {
2480 .chip_id = BCM53010_DEVICE_ID,
2481 .dev_name = "BCM53010",
2482 .vlans = 4096,
2483 .enabled_ports = 0x1bf,
2484 .arl_bins = 4,
2485 .arl_buckets = 1024,
2486 .imp_port = 8,
2487 .vta_regs = B53_VTA_REGS,
2488 .duplex_reg = B53_DUPLEX_STAT_GE,
2489 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2490 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2491 },
2492 {
2493 .chip_id = BCM53011_DEVICE_ID,
2494 .dev_name = "BCM53011",
2495 .vlans = 4096,
2496 .enabled_ports = 0x1bf,
2497 .arl_bins = 4,
2498 .arl_buckets = 1024,
2499 .imp_port = 8,
2500 .vta_regs = B53_VTA_REGS,
2501 .duplex_reg = B53_DUPLEX_STAT_GE,
2502 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2503 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2504 },
2505 {
2506 .chip_id = BCM53012_DEVICE_ID,
2507 .dev_name = "BCM53012",
2508 .vlans = 4096,
2509 .enabled_ports = 0x1bf,
2510 .arl_bins = 4,
2511 .arl_buckets = 1024,
2512 .imp_port = 8,
2513 .vta_regs = B53_VTA_REGS,
2514 .duplex_reg = B53_DUPLEX_STAT_GE,
2515 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2516 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2517 },
2518 {
2519 .chip_id = BCM53018_DEVICE_ID,
2520 .dev_name = "BCM53018",
2521 .vlans = 4096,
2522 .enabled_ports = 0x1bf,
2523 .arl_bins = 4,
2524 .arl_buckets = 1024,
2525 .imp_port = 8,
2526 .vta_regs = B53_VTA_REGS,
2527 .duplex_reg = B53_DUPLEX_STAT_GE,
2528 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2529 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2530 },
2531 {
2532 .chip_id = BCM53019_DEVICE_ID,
2533 .dev_name = "BCM53019",
2534 .vlans = 4096,
2535 .enabled_ports = 0x1bf,
2536 .arl_bins = 4,
2537 .arl_buckets = 1024,
2538 .imp_port = 8,
2539 .vta_regs = B53_VTA_REGS,
2540 .duplex_reg = B53_DUPLEX_STAT_GE,
2541 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2542 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2543 },
2544 {
2545 .chip_id = BCM58XX_DEVICE_ID,
2546 .dev_name = "BCM585xx/586xx/88312",
2547 .vlans = 4096,
2548 .enabled_ports = 0x1ff,
2549 .arl_bins = 4,
2550 .arl_buckets = 1024,
2551 .imp_port = 8,
2552 .vta_regs = B53_VTA_REGS,
2553 .duplex_reg = B53_DUPLEX_STAT_GE,
2554 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2555 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2556 },
2557 {
2558 .chip_id = BCM583XX_DEVICE_ID,
2559 .dev_name = "BCM583xx/11360",
2560 .vlans = 4096,
2561 .enabled_ports = 0x103,
2562 .arl_bins = 4,
2563 .arl_buckets = 1024,
2564 .imp_port = 8,
2565 .vta_regs = B53_VTA_REGS,
2566 .duplex_reg = B53_DUPLEX_STAT_GE,
2567 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2568 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2569 },
2570 /* Starfighter 2 */
2571 {
2572 .chip_id = BCM4908_DEVICE_ID,
2573 .dev_name = "BCM4908",
2574 .vlans = 4096,
2575 .enabled_ports = 0x1bf,
2576 .arl_bins = 4,
2577 .arl_buckets = 256,
2578 .imp_port = 8,
2579 .vta_regs = B53_VTA_REGS,
2580 .duplex_reg = B53_DUPLEX_STAT_GE,
2581 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2582 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2583 },
2584 {
2585 .chip_id = BCM7445_DEVICE_ID,
2586 .dev_name = "BCM7445",
2587 .vlans = 4096,
2588 .enabled_ports = 0x1ff,
2589 .arl_bins = 4,
2590 .arl_buckets = 1024,
2591 .imp_port = 8,
2592 .vta_regs = B53_VTA_REGS,
2593 .duplex_reg = B53_DUPLEX_STAT_GE,
2594 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2595 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2596 },
2597 {
2598 .chip_id = BCM7278_DEVICE_ID,
2599 .dev_name = "BCM7278",
2600 .vlans = 4096,
2601 .enabled_ports = 0x1ff,
2602 .arl_bins = 4,
2603 .arl_buckets = 256,
2604 .imp_port = 8,
2605 .vta_regs = B53_VTA_REGS,
2606 .duplex_reg = B53_DUPLEX_STAT_GE,
2607 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2608 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2609 },
2610 {
2611 .chip_id = BCM53134_DEVICE_ID,
2612 .dev_name = "BCM53134",
2613 .vlans = 4096,
2614 .enabled_ports = 0x12f,
2615 .imp_port = 8,
2616 .cpu_port = B53_CPU_PORT,
2617 .vta_regs = B53_VTA_REGS,
2618 .arl_bins = 4,
2619 .arl_buckets = 1024,
2620 .duplex_reg = B53_DUPLEX_STAT_GE,
2621 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2622 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2623 },
2624};
2625
2626static int b53_switch_init(struct b53_device *dev)
2627{
2628 unsigned int i;
2629 int ret;
2630
2631 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2632 const struct b53_chip_data *chip = &b53_switch_chips[i];
2633
2634 if (chip->chip_id == dev->chip_id) {
2635 if (!dev->enabled_ports)
2636 dev->enabled_ports = chip->enabled_ports;
2637 dev->name = chip->dev_name;
2638 dev->duplex_reg = chip->duplex_reg;
2639 dev->vta_regs[0] = chip->vta_regs[0];
2640 dev->vta_regs[1] = chip->vta_regs[1];
2641 dev->vta_regs[2] = chip->vta_regs[2];
2642 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2643 dev->imp_port = chip->imp_port;
2644 dev->num_vlans = chip->vlans;
2645 dev->num_arl_bins = chip->arl_bins;
2646 dev->num_arl_buckets = chip->arl_buckets;
2647 break;
2648 }
2649 }
2650
2651 /* check which BCM5325x version we have */
2652 if (is5325(dev)) {
2653 u8 vc4;
2654
2655 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2656
2657 /* check reserved bits */
2658 switch (vc4 & 3) {
2659 case 1:
2660 /* BCM5325E */
2661 break;
2662 case 3:
2663 /* BCM5325F - do not use port 4 */
2664 dev->enabled_ports &= ~BIT(4);
2665 break;
2666 default:
2667/* On the BCM47XX SoCs this is the supported internal switch.*/
2668#ifndef CONFIG_BCM47XX
2669 /* BCM5325M */
2670 return -EINVAL;
2671#else
2672 break;
2673#endif
2674 }
2675 }
2676
2677 dev->num_ports = fls(dev->enabled_ports);
2678
2679 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2680
2681 /* Include non standard CPU port built-in PHYs to be probed */
2682 if (is539x(dev) || is531x5(dev)) {
2683 for (i = 0; i < dev->num_ports; i++) {
2684 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2685 !b53_possible_cpu_port(dev->ds, i))
2686 dev->ds->phys_mii_mask |= BIT(i);
2687 }
2688 }
2689
2690 dev->ports = devm_kcalloc(dev->dev,
2691 dev->num_ports, sizeof(struct b53_port),
2692 GFP_KERNEL);
2693 if (!dev->ports)
2694 return -ENOMEM;
2695
2696 dev->vlans = devm_kcalloc(dev->dev,
2697 dev->num_vlans, sizeof(struct b53_vlan),
2698 GFP_KERNEL);
2699 if (!dev->vlans)
2700 return -ENOMEM;
2701
2702 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2703 if (dev->reset_gpio >= 0) {
2704 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2705 GPIOF_OUT_INIT_HIGH, "robo_reset");
2706 if (ret)
2707 return ret;
2708 }
2709
2710 return 0;
2711}
2712
2713struct b53_device *b53_switch_alloc(struct device *base,
2714 const struct b53_io_ops *ops,
2715 void *priv)
2716{
2717 struct dsa_switch *ds;
2718 struct b53_device *dev;
2719
2720 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2721 if (!ds)
2722 return NULL;
2723
2724 ds->dev = base;
2725
2726 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2727 if (!dev)
2728 return NULL;
2729
2730 ds->priv = dev;
2731 dev->dev = base;
2732
2733 dev->ds = ds;
2734 dev->priv = priv;
2735 dev->ops = ops;
2736 ds->ops = &b53_switch_ops;
2737 dev->vlan_enabled = true;
2738 /* Let DSA handle the case were multiple bridges span the same switch
2739 * device and different VLAN awareness settings are requested, which
2740 * would be breaking filtering semantics for any of the other bridge
2741 * devices. (not hardware supported)
2742 */
2743 ds->vlan_filtering_is_global = true;
2744
2745 mutex_init(&dev->reg_mutex);
2746 mutex_init(&dev->stats_mutex);
2747 mutex_init(&dev->arl_mutex);
2748
2749 return dev;
2750}
2751EXPORT_SYMBOL(b53_switch_alloc);
2752
2753int b53_switch_detect(struct b53_device *dev)
2754{
2755 u32 id32;
2756 u16 tmp;
2757 u8 id8;
2758 int ret;
2759
2760 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2761 if (ret)
2762 return ret;
2763
2764 switch (id8) {
2765 case 0:
2766 /* BCM5325 and BCM5365 do not have this register so reads
2767 * return 0. But the read operation did succeed, so assume this
2768 * is one of them.
2769 *
2770 * Next check if we can write to the 5325's VTA register; for
2771 * 5365 it is read only.
2772 */
2773 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2774 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2775
2776 if (tmp == 0xf)
2777 dev->chip_id = BCM5325_DEVICE_ID;
2778 else
2779 dev->chip_id = BCM5365_DEVICE_ID;
2780 break;
2781 case BCM5389_DEVICE_ID:
2782 case BCM5395_DEVICE_ID:
2783 case BCM5397_DEVICE_ID:
2784 case BCM5398_DEVICE_ID:
2785 dev->chip_id = id8;
2786 break;
2787 default:
2788 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2789 if (ret)
2790 return ret;
2791
2792 switch (id32) {
2793 case BCM53115_DEVICE_ID:
2794 case BCM53125_DEVICE_ID:
2795 case BCM53128_DEVICE_ID:
2796 case BCM53010_DEVICE_ID:
2797 case BCM53011_DEVICE_ID:
2798 case BCM53012_DEVICE_ID:
2799 case BCM53018_DEVICE_ID:
2800 case BCM53019_DEVICE_ID:
2801 case BCM53134_DEVICE_ID:
2802 dev->chip_id = id32;
2803 break;
2804 default:
2805 dev_err(dev->dev,
2806 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2807 id8, id32);
2808 return -ENODEV;
2809 }
2810 }
2811
2812 if (dev->chip_id == BCM5325_DEVICE_ID)
2813 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2814 &dev->core_rev);
2815 else
2816 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2817 &dev->core_rev);
2818}
2819EXPORT_SYMBOL(b53_switch_detect);
2820
2821int b53_switch_register(struct b53_device *dev)
2822{
2823 int ret;
2824
2825 if (dev->pdata) {
2826 dev->chip_id = dev->pdata->chip_id;
2827 dev->enabled_ports = dev->pdata->enabled_ports;
2828 }
2829
2830 if (!dev->chip_id && b53_switch_detect(dev))
2831 return -EINVAL;
2832
2833 ret = b53_switch_init(dev);
2834 if (ret)
2835 return ret;
2836
2837 dev_info(dev->dev, "found switch: %s, rev %i\n",
2838 dev->name, dev->core_rev);
2839
2840 return dsa_register_switch(dev->ds);
2841}
2842EXPORT_SYMBOL(b53_switch_register);
2843
2844MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2845MODULE_DESCRIPTION("B53 switch library");
2846MODULE_LICENSE("Dual BSD/GPL");
1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
29#include <linux/phylink.h>
30#include <linux/etherdevice.h>
31#include <linux/if_bridge.h>
32#include <net/dsa.h>
33
34#include "b53_regs.h"
35#include "b53_priv.h"
36
37struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41};
42
43/* BCM5365 MIB counters */
44static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77};
78
79#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81/* BCM63xx MIB counters */
82static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125};
126
127#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129/* MIB counters */
130static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166};
167
168#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
170static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
225};
226
227#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228
229static int b53_do_vlan_op(struct b53_device *dev, u8 op)
230{
231 unsigned int i;
232
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234
235 for (i = 0; i < 10; i++) {
236 u8 vta;
237
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
240 return 0;
241
242 usleep_range(100, 200);
243 }
244
245 return -EIO;
246}
247
248static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
250{
251 if (is5325(dev)) {
252 u32 entry = 0;
253
254 if (vlan->members) {
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 else
260 entry |= VA_VALID_25;
261 }
262
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
267 u16 entry = 0;
268
269 if (vlan->members)
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
272
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 } else {
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
280
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
282 }
283
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
286}
287
288static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
290{
291 if (is5325(dev)) {
292 u32 entry = 0;
293
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
300 else
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304
305 } else if (is5365(dev)) {
306 u16 entry = 0;
307
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
315 } else {
316 u32 entry = 0;
317
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
323 vlan->valid = true;
324 }
325}
326
327static void b53_set_forwarding(struct b53_device *dev, int enable)
328{
329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
339
340 /* Include IMP port in dumb forwarding mode
341 */
342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
343 mgmt |= B53_MII_DUMB_FWDG_EN;
344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
345
346 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
347 * frames should be flooded or not.
348 */
349 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
350 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
351 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
352}
353
354static void b53_enable_vlan(struct b53_device *dev, bool enable,
355 bool enable_filtering)
356{
357 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
358
359 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
362
363 if (is5325(dev) || is5365(dev)) {
364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
366 } else if (is63xx(dev)) {
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
369 } else {
370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
371 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
372 }
373
374 if (enable) {
375 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
376 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
377 vc4 &= ~VC4_ING_VID_CHECK_MASK;
378 if (enable_filtering) {
379 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
380 vc5 |= VC5_DROP_VTABLE_MISS;
381 } else {
382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
383 vc5 &= ~VC5_DROP_VTABLE_MISS;
384 }
385
386 if (is5325(dev))
387 vc0 &= ~VC0_RESERVED_1;
388
389 if (is5325(dev) || is5365(dev))
390 vc1 |= VC1_RX_MCST_TAG_EN;
391
392 } else {
393 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
394 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
395 vc4 &= ~VC4_ING_VID_CHECK_MASK;
396 vc5 &= ~VC5_DROP_VTABLE_MISS;
397
398 if (is5325(dev) || is5365(dev))
399 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
400 else
401 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
402
403 if (is5325(dev) || is5365(dev))
404 vc1 &= ~VC1_RX_MCST_TAG_EN;
405 }
406
407 if (!is5325(dev) && !is5365(dev))
408 vc5 &= ~VC5_VID_FFF_EN;
409
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
412
413 if (is5325(dev) || is5365(dev)) {
414 /* enable the high 8 bit vid check on 5325 */
415 if (is5325(dev) && enable)
416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
417 VC3_HIGH_8BIT_EN);
418 else
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
420
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
423 } else if (is63xx(dev)) {
424 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
427 } else {
428 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
429 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
431 }
432
433 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
434
435 dev->vlan_enabled = enable;
436}
437
438static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
439{
440 u32 port_mask = 0;
441 u16 max_size = JMS_MIN_SIZE;
442
443 if (is5325(dev) || is5365(dev))
444 return -EINVAL;
445
446 if (enable) {
447 port_mask = dev->enabled_ports;
448 max_size = JMS_MAX_SIZE;
449 if (allow_10_100)
450 port_mask |= JPM_10_100_JUMBO_EN;
451 }
452
453 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
454 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
455}
456
457static int b53_flush_arl(struct b53_device *dev, u8 mask)
458{
459 unsigned int i;
460
461 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
462 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
463
464 for (i = 0; i < 10; i++) {
465 u8 fast_age_ctrl;
466
467 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
468 &fast_age_ctrl);
469
470 if (!(fast_age_ctrl & FAST_AGE_DONE))
471 goto out;
472
473 msleep(1);
474 }
475
476 return -ETIMEDOUT;
477out:
478 /* Only age dynamic entries (default behavior) */
479 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
480 return 0;
481}
482
483static int b53_fast_age_port(struct b53_device *dev, int port)
484{
485 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
486
487 return b53_flush_arl(dev, FAST_AGE_PORT);
488}
489
490static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
491{
492 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
493
494 return b53_flush_arl(dev, FAST_AGE_VLAN);
495}
496
497void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
498{
499 struct b53_device *dev = ds->priv;
500 unsigned int i;
501 u16 pvlan;
502
503 /* Enable the IMP port to be in the same VLAN as the other ports
504 * on a per-port basis such that we only have Port i and IMP in
505 * the same VLAN.
506 */
507 b53_for_each_port(dev, i) {
508 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
509 pvlan |= BIT(cpu_port);
510 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
511 }
512}
513EXPORT_SYMBOL(b53_imp_vlan_setup);
514
515int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
516{
517 struct b53_device *dev = ds->priv;
518 unsigned int cpu_port;
519 int ret = 0;
520 u16 pvlan;
521
522 if (!dsa_is_user_port(ds, port))
523 return 0;
524
525 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
526
527 b53_br_egress_floods(ds, port, true, true);
528
529 if (dev->ops->irq_enable)
530 ret = dev->ops->irq_enable(dev, port);
531 if (ret)
532 return ret;
533
534 /* Clear the Rx and Tx disable bits and set to no spanning tree */
535 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
536
537 /* Set this port, and only this one to be in the default VLAN,
538 * if member of a bridge, restore its membership prior to
539 * bringing down this port.
540 */
541 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
542 pvlan &= ~0x1ff;
543 pvlan |= BIT(port);
544 pvlan |= dev->ports[port].vlan_ctl_mask;
545 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
546
547 b53_imp_vlan_setup(ds, cpu_port);
548
549 /* If EEE was enabled, restore it */
550 if (dev->ports[port].eee.eee_enabled)
551 b53_eee_enable_set(ds, port, true);
552
553 return 0;
554}
555EXPORT_SYMBOL(b53_enable_port);
556
557void b53_disable_port(struct dsa_switch *ds, int port)
558{
559 struct b53_device *dev = ds->priv;
560 u8 reg;
561
562 /* Disable Tx/Rx for the port */
563 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
564 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
565 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
566
567 if (dev->ops->irq_disable)
568 dev->ops->irq_disable(dev, port);
569}
570EXPORT_SYMBOL(b53_disable_port);
571
572void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
573{
574 struct b53_device *dev = ds->priv;
575 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
576 u8 hdr_ctl, val;
577 u16 reg;
578
579 /* Resolve which bit controls the Broadcom tag */
580 switch (port) {
581 case 8:
582 val = BRCM_HDR_P8_EN;
583 break;
584 case 7:
585 val = BRCM_HDR_P7_EN;
586 break;
587 case 5:
588 val = BRCM_HDR_P5_EN;
589 break;
590 default:
591 val = 0;
592 break;
593 }
594
595 /* Enable management mode if tagging is requested */
596 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
597 if (tag_en)
598 hdr_ctl |= SM_SW_FWD_MODE;
599 else
600 hdr_ctl &= ~SM_SW_FWD_MODE;
601 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
602
603 /* Configure the appropriate IMP port */
604 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
605 if (port == 8)
606 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
607 else if (port == 5)
608 hdr_ctl |= GC_FRM_MGMT_PORT_M;
609 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
610
611 /* Enable Broadcom tags for IMP port */
612 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
613 if (tag_en)
614 hdr_ctl |= val;
615 else
616 hdr_ctl &= ~val;
617 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
618
619 /* Registers below are only accessible on newer devices */
620 if (!is58xx(dev))
621 return;
622
623 /* Enable reception Broadcom tag for CPU TX (switch RX) to
624 * allow us to tag outgoing frames
625 */
626 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
627 if (tag_en)
628 reg &= ~BIT(port);
629 else
630 reg |= BIT(port);
631 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
632
633 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
634 * allow delivering frames to the per-port net_devices
635 */
636 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
637 if (tag_en)
638 reg &= ~BIT(port);
639 else
640 reg |= BIT(port);
641 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
642}
643EXPORT_SYMBOL(b53_brcm_hdr_setup);
644
645static void b53_enable_cpu_port(struct b53_device *dev, int port)
646{
647 u8 port_ctrl;
648
649 /* BCM5325 CPU port is at 8 */
650 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
651 port = B53_CPU_PORT;
652
653 port_ctrl = PORT_CTRL_RX_BCST_EN |
654 PORT_CTRL_RX_MCST_EN |
655 PORT_CTRL_RX_UCST_EN;
656 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
657
658 b53_brcm_hdr_setup(dev->ds, port);
659
660 b53_br_egress_floods(dev->ds, port, true, true);
661}
662
663static void b53_enable_mib(struct b53_device *dev)
664{
665 u8 gc;
666
667 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
668 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
669 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
670}
671
672static u16 b53_default_pvid(struct b53_device *dev)
673{
674 if (is5325(dev) || is5365(dev))
675 return 1;
676 else
677 return 0;
678}
679
680int b53_configure_vlan(struct dsa_switch *ds)
681{
682 struct b53_device *dev = ds->priv;
683 struct b53_vlan vl = { 0 };
684 struct b53_vlan *v;
685 int i, def_vid;
686 u16 vid;
687
688 def_vid = b53_default_pvid(dev);
689
690 /* clear all vlan entries */
691 if (is5325(dev) || is5365(dev)) {
692 for (i = def_vid; i < dev->num_vlans; i++)
693 b53_set_vlan_entry(dev, i, &vl);
694 } else {
695 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
696 }
697
698 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering);
699
700 b53_for_each_port(dev, i)
701 b53_write16(dev, B53_VLAN_PAGE,
702 B53_VLAN_PORT_DEF_TAG(i), def_vid);
703
704 /* Upon initial call we have not set-up any VLANs, but upon
705 * system resume, we need to restore all VLAN entries.
706 */
707 for (vid = def_vid; vid < dev->num_vlans; vid++) {
708 v = &dev->vlans[vid];
709
710 if (!v->members)
711 continue;
712
713 b53_set_vlan_entry(dev, vid, v);
714 b53_fast_age_vlan(dev, vid);
715 }
716
717 return 0;
718}
719EXPORT_SYMBOL(b53_configure_vlan);
720
721static void b53_switch_reset_gpio(struct b53_device *dev)
722{
723 int gpio = dev->reset_gpio;
724
725 if (gpio < 0)
726 return;
727
728 /* Reset sequence: RESET low(50ms)->high(20ms)
729 */
730 gpio_set_value(gpio, 0);
731 mdelay(50);
732
733 gpio_set_value(gpio, 1);
734 mdelay(20);
735
736 dev->current_page = 0xff;
737}
738
739static int b53_switch_reset(struct b53_device *dev)
740{
741 unsigned int timeout = 1000;
742 u8 mgmt, reg;
743
744 b53_switch_reset_gpio(dev);
745
746 if (is539x(dev)) {
747 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
748 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
749 }
750
751 /* This is specific to 58xx devices here, do not use is58xx() which
752 * covers the larger Starfigther 2 family, including 7445/7278 which
753 * still use this driver as a library and need to perform the reset
754 * earlier.
755 */
756 if (dev->chip_id == BCM58XX_DEVICE_ID ||
757 dev->chip_id == BCM583XX_DEVICE_ID) {
758 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
759 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
760 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
761
762 do {
763 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
764 if (!(reg & SW_RST))
765 break;
766
767 usleep_range(1000, 2000);
768 } while (timeout-- > 0);
769
770 if (timeout == 0)
771 return -ETIMEDOUT;
772 }
773
774 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
775
776 if (!(mgmt & SM_SW_FWD_EN)) {
777 mgmt &= ~SM_SW_FWD_MODE;
778 mgmt |= SM_SW_FWD_EN;
779
780 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
781 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
782
783 if (!(mgmt & SM_SW_FWD_EN)) {
784 dev_err(dev->dev, "Failed to enable switch!\n");
785 return -EINVAL;
786 }
787 }
788
789 b53_enable_mib(dev);
790
791 return b53_flush_arl(dev, FAST_AGE_STATIC);
792}
793
794static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
795{
796 struct b53_device *priv = ds->priv;
797 u16 value = 0;
798 int ret;
799
800 if (priv->ops->phy_read16)
801 ret = priv->ops->phy_read16(priv, addr, reg, &value);
802 else
803 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
804 reg * 2, &value);
805
806 return ret ? ret : value;
807}
808
809static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
810{
811 struct b53_device *priv = ds->priv;
812
813 if (priv->ops->phy_write16)
814 return priv->ops->phy_write16(priv, addr, reg, val);
815
816 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
817}
818
819static int b53_reset_switch(struct b53_device *priv)
820{
821 /* reset vlans */
822 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
823 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
824
825 priv->serdes_lane = B53_INVALID_LANE;
826
827 return b53_switch_reset(priv);
828}
829
830static int b53_apply_config(struct b53_device *priv)
831{
832 /* disable switching */
833 b53_set_forwarding(priv, 0);
834
835 b53_configure_vlan(priv->ds);
836
837 /* enable switching */
838 b53_set_forwarding(priv, 1);
839
840 return 0;
841}
842
843static void b53_reset_mib(struct b53_device *priv)
844{
845 u8 gc;
846
847 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
848
849 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
850 msleep(1);
851 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
852 msleep(1);
853}
854
855static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
856{
857 if (is5365(dev))
858 return b53_mibs_65;
859 else if (is63xx(dev))
860 return b53_mibs_63xx;
861 else if (is58xx(dev))
862 return b53_mibs_58xx;
863 else
864 return b53_mibs;
865}
866
867static unsigned int b53_get_mib_size(struct b53_device *dev)
868{
869 if (is5365(dev))
870 return B53_MIBS_65_SIZE;
871 else if (is63xx(dev))
872 return B53_MIBS_63XX_SIZE;
873 else if (is58xx(dev))
874 return B53_MIBS_58XX_SIZE;
875 else
876 return B53_MIBS_SIZE;
877}
878
879static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
880{
881 /* These ports typically do not have built-in PHYs */
882 switch (port) {
883 case B53_CPU_PORT_25:
884 case 7:
885 case B53_CPU_PORT:
886 return NULL;
887 }
888
889 return mdiobus_get_phy(ds->slave_mii_bus, port);
890}
891
892void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
893 uint8_t *data)
894{
895 struct b53_device *dev = ds->priv;
896 const struct b53_mib_desc *mibs = b53_get_mib(dev);
897 unsigned int mib_size = b53_get_mib_size(dev);
898 struct phy_device *phydev;
899 unsigned int i;
900
901 if (stringset == ETH_SS_STATS) {
902 for (i = 0; i < mib_size; i++)
903 strlcpy(data + i * ETH_GSTRING_LEN,
904 mibs[i].name, ETH_GSTRING_LEN);
905 } else if (stringset == ETH_SS_PHY_STATS) {
906 phydev = b53_get_phy_device(ds, port);
907 if (!phydev)
908 return;
909
910 phy_ethtool_get_strings(phydev, data);
911 }
912}
913EXPORT_SYMBOL(b53_get_strings);
914
915void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
916{
917 struct b53_device *dev = ds->priv;
918 const struct b53_mib_desc *mibs = b53_get_mib(dev);
919 unsigned int mib_size = b53_get_mib_size(dev);
920 const struct b53_mib_desc *s;
921 unsigned int i;
922 u64 val = 0;
923
924 if (is5365(dev) && port == 5)
925 port = 8;
926
927 mutex_lock(&dev->stats_mutex);
928
929 for (i = 0; i < mib_size; i++) {
930 s = &mibs[i];
931
932 if (s->size == 8) {
933 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
934 } else {
935 u32 val32;
936
937 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
938 &val32);
939 val = val32;
940 }
941 data[i] = (u64)val;
942 }
943
944 mutex_unlock(&dev->stats_mutex);
945}
946EXPORT_SYMBOL(b53_get_ethtool_stats);
947
948void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
949{
950 struct phy_device *phydev;
951
952 phydev = b53_get_phy_device(ds, port);
953 if (!phydev)
954 return;
955
956 phy_ethtool_get_stats(phydev, NULL, data);
957}
958EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
959
960int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
961{
962 struct b53_device *dev = ds->priv;
963 struct phy_device *phydev;
964
965 if (sset == ETH_SS_STATS) {
966 return b53_get_mib_size(dev);
967 } else if (sset == ETH_SS_PHY_STATS) {
968 phydev = b53_get_phy_device(ds, port);
969 if (!phydev)
970 return 0;
971
972 return phy_ethtool_get_sset_count(phydev);
973 }
974
975 return 0;
976}
977EXPORT_SYMBOL(b53_get_sset_count);
978
979static int b53_setup(struct dsa_switch *ds)
980{
981 struct b53_device *dev = ds->priv;
982 unsigned int port;
983 int ret;
984
985 ret = b53_reset_switch(dev);
986 if (ret) {
987 dev_err(ds->dev, "failed to reset switch\n");
988 return ret;
989 }
990
991 b53_reset_mib(dev);
992
993 ret = b53_apply_config(dev);
994 if (ret)
995 dev_err(ds->dev, "failed to apply configuration\n");
996
997 /* Configure IMP/CPU port, disable all other ports. Enabled
998 * ports will be configured with .port_enable
999 */
1000 for (port = 0; port < dev->num_ports; port++) {
1001 if (dsa_is_cpu_port(ds, port))
1002 b53_enable_cpu_port(dev, port);
1003 else
1004 b53_disable_port(ds, port);
1005 }
1006
1007 /* Let DSA handle the case were multiple bridges span the same switch
1008 * device and different VLAN awareness settings are requested, which
1009 * would be breaking filtering semantics for any of the other bridge
1010 * devices. (not hardware supported)
1011 */
1012 ds->vlan_filtering_is_global = true;
1013
1014 return ret;
1015}
1016
1017static void b53_force_link(struct b53_device *dev, int port, int link)
1018{
1019 u8 reg, val, off;
1020
1021 /* Override the port settings */
1022 if (port == dev->cpu_port) {
1023 off = B53_PORT_OVERRIDE_CTRL;
1024 val = PORT_OVERRIDE_EN;
1025 } else {
1026 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1027 val = GMII_PO_EN;
1028 }
1029
1030 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1031 reg |= val;
1032 if (link)
1033 reg |= PORT_OVERRIDE_LINK;
1034 else
1035 reg &= ~PORT_OVERRIDE_LINK;
1036 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1037}
1038
1039static void b53_force_port_config(struct b53_device *dev, int port,
1040 int speed, int duplex,
1041 bool tx_pause, bool rx_pause)
1042{
1043 u8 reg, val, off;
1044
1045 /* Override the port settings */
1046 if (port == dev->cpu_port) {
1047 off = B53_PORT_OVERRIDE_CTRL;
1048 val = PORT_OVERRIDE_EN;
1049 } else {
1050 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1051 val = GMII_PO_EN;
1052 }
1053
1054 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1055 reg |= val;
1056 if (duplex == DUPLEX_FULL)
1057 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1058 else
1059 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1060
1061 switch (speed) {
1062 case 2000:
1063 reg |= PORT_OVERRIDE_SPEED_2000M;
1064 fallthrough;
1065 case SPEED_1000:
1066 reg |= PORT_OVERRIDE_SPEED_1000M;
1067 break;
1068 case SPEED_100:
1069 reg |= PORT_OVERRIDE_SPEED_100M;
1070 break;
1071 case SPEED_10:
1072 reg |= PORT_OVERRIDE_SPEED_10M;
1073 break;
1074 default:
1075 dev_err(dev->dev, "unknown speed: %d\n", speed);
1076 return;
1077 }
1078
1079 if (rx_pause)
1080 reg |= PORT_OVERRIDE_RX_FLOW;
1081 if (tx_pause)
1082 reg |= PORT_OVERRIDE_TX_FLOW;
1083
1084 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1085}
1086
1087static void b53_adjust_link(struct dsa_switch *ds, int port,
1088 struct phy_device *phydev)
1089{
1090 struct b53_device *dev = ds->priv;
1091 struct ethtool_eee *p = &dev->ports[port].eee;
1092 u8 rgmii_ctrl = 0, reg = 0, off;
1093 bool tx_pause = false;
1094 bool rx_pause = false;
1095
1096 if (!phy_is_pseudo_fixed_link(phydev))
1097 return;
1098
1099 /* Enable flow control on BCM5301x's CPU port */
1100 if (is5301x(dev) && port == dev->cpu_port)
1101 tx_pause = rx_pause = true;
1102
1103 if (phydev->pause) {
1104 if (phydev->asym_pause)
1105 tx_pause = true;
1106 rx_pause = true;
1107 }
1108
1109 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1110 tx_pause, rx_pause);
1111 b53_force_link(dev, port, phydev->link);
1112
1113 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1114 if (port == 8)
1115 off = B53_RGMII_CTRL_IMP;
1116 else
1117 off = B53_RGMII_CTRL_P(port);
1118
1119 /* Configure the port RGMII clock delay by DLL disabled and
1120 * tx_clk aligned timing (restoring to reset defaults)
1121 */
1122 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1123 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1124 RGMII_CTRL_TIMING_SEL);
1125
1126 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1127 * sure that we enable the port TX clock internal delay to
1128 * account for this internal delay that is inserted, otherwise
1129 * the switch won't be able to receive correctly.
1130 *
1131 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1132 * any delay neither on transmission nor reception, so the
1133 * BCM53125 must also be configured accordingly to account for
1134 * the lack of delay and introduce
1135 *
1136 * The BCM53125 switch has its RX clock and TX clock control
1137 * swapped, hence the reason why we modify the TX clock path in
1138 * the "RGMII" case
1139 */
1140 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1141 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1142 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1143 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1144 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1145 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1146
1147 dev_info(ds->dev, "Configured port %d for %s\n", port,
1148 phy_modes(phydev->interface));
1149 }
1150
1151 /* configure MII port if necessary */
1152 if (is5325(dev)) {
1153 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1154 ®);
1155
1156 /* reverse mii needs to be enabled */
1157 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1158 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1159 reg | PORT_OVERRIDE_RV_MII_25);
1160 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1161 ®);
1162
1163 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1164 dev_err(ds->dev,
1165 "Failed to enable reverse MII mode\n");
1166 return;
1167 }
1168 }
1169 } else if (is5301x(dev)) {
1170 if (port != dev->cpu_port) {
1171 b53_force_port_config(dev, dev->cpu_port, 2000,
1172 DUPLEX_FULL, true, true);
1173 b53_force_link(dev, dev->cpu_port, 1);
1174 }
1175 }
1176
1177 /* Re-negotiate EEE if it was enabled already */
1178 p->eee_enabled = b53_eee_init(ds, port, phydev);
1179}
1180
1181void b53_port_event(struct dsa_switch *ds, int port)
1182{
1183 struct b53_device *dev = ds->priv;
1184 bool link;
1185 u16 sts;
1186
1187 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1188 link = !!(sts & BIT(port));
1189 dsa_port_phylink_mac_change(ds, port, link);
1190}
1191EXPORT_SYMBOL(b53_port_event);
1192
1193void b53_phylink_validate(struct dsa_switch *ds, int port,
1194 unsigned long *supported,
1195 struct phylink_link_state *state)
1196{
1197 struct b53_device *dev = ds->priv;
1198 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1199
1200 if (dev->ops->serdes_phylink_validate)
1201 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1202
1203 /* Allow all the expected bits */
1204 phylink_set(mask, Autoneg);
1205 phylink_set_port_modes(mask);
1206 phylink_set(mask, Pause);
1207 phylink_set(mask, Asym_Pause);
1208
1209 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1210 * support Gigabit, including Half duplex.
1211 */
1212 if (state->interface != PHY_INTERFACE_MODE_MII &&
1213 state->interface != PHY_INTERFACE_MODE_REVMII &&
1214 !phy_interface_mode_is_8023z(state->interface) &&
1215 !(is5325(dev) || is5365(dev))) {
1216 phylink_set(mask, 1000baseT_Full);
1217 phylink_set(mask, 1000baseT_Half);
1218 }
1219
1220 if (!phy_interface_mode_is_8023z(state->interface)) {
1221 phylink_set(mask, 10baseT_Half);
1222 phylink_set(mask, 10baseT_Full);
1223 phylink_set(mask, 100baseT_Half);
1224 phylink_set(mask, 100baseT_Full);
1225 }
1226
1227 bitmap_and(supported, supported, mask,
1228 __ETHTOOL_LINK_MODE_MASK_NBITS);
1229 bitmap_and(state->advertising, state->advertising, mask,
1230 __ETHTOOL_LINK_MODE_MASK_NBITS);
1231
1232 phylink_helper_basex_speed(state);
1233}
1234EXPORT_SYMBOL(b53_phylink_validate);
1235
1236int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1237 struct phylink_link_state *state)
1238{
1239 struct b53_device *dev = ds->priv;
1240 int ret = -EOPNOTSUPP;
1241
1242 if ((phy_interface_mode_is_8023z(state->interface) ||
1243 state->interface == PHY_INTERFACE_MODE_SGMII) &&
1244 dev->ops->serdes_link_state)
1245 ret = dev->ops->serdes_link_state(dev, port, state);
1246
1247 return ret;
1248}
1249EXPORT_SYMBOL(b53_phylink_mac_link_state);
1250
1251void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1252 unsigned int mode,
1253 const struct phylink_link_state *state)
1254{
1255 struct b53_device *dev = ds->priv;
1256
1257 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED)
1258 return;
1259
1260 if ((phy_interface_mode_is_8023z(state->interface) ||
1261 state->interface == PHY_INTERFACE_MODE_SGMII) &&
1262 dev->ops->serdes_config)
1263 dev->ops->serdes_config(dev, port, mode, state);
1264}
1265EXPORT_SYMBOL(b53_phylink_mac_config);
1266
1267void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1268{
1269 struct b53_device *dev = ds->priv;
1270
1271 if (dev->ops->serdes_an_restart)
1272 dev->ops->serdes_an_restart(dev, port);
1273}
1274EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1275
1276void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1277 unsigned int mode,
1278 phy_interface_t interface)
1279{
1280 struct b53_device *dev = ds->priv;
1281
1282 if (mode == MLO_AN_PHY)
1283 return;
1284
1285 if (mode == MLO_AN_FIXED) {
1286 b53_force_link(dev, port, false);
1287 return;
1288 }
1289
1290 if (phy_interface_mode_is_8023z(interface) &&
1291 dev->ops->serdes_link_set)
1292 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1293}
1294EXPORT_SYMBOL(b53_phylink_mac_link_down);
1295
1296void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1297 unsigned int mode,
1298 phy_interface_t interface,
1299 struct phy_device *phydev,
1300 int speed, int duplex,
1301 bool tx_pause, bool rx_pause)
1302{
1303 struct b53_device *dev = ds->priv;
1304
1305 if (mode == MLO_AN_PHY)
1306 return;
1307
1308 if (mode == MLO_AN_FIXED) {
1309 b53_force_port_config(dev, port, speed, duplex,
1310 tx_pause, rx_pause);
1311 b53_force_link(dev, port, true);
1312 return;
1313 }
1314
1315 if (phy_interface_mode_is_8023z(interface) &&
1316 dev->ops->serdes_link_set)
1317 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1318}
1319EXPORT_SYMBOL(b53_phylink_mac_link_up);
1320
1321int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1322{
1323 struct b53_device *dev = ds->priv;
1324 u16 pvid, new_pvid;
1325
1326 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1327 if (!vlan_filtering) {
1328 /* Filtering is currently enabled, use the default PVID since
1329 * the bridge does not expect tagging anymore
1330 */
1331 dev->ports[port].pvid = pvid;
1332 new_pvid = b53_default_pvid(dev);
1333 } else {
1334 /* Filtering is currently disabled, restore the previous PVID */
1335 new_pvid = dev->ports[port].pvid;
1336 }
1337
1338 if (pvid != new_pvid)
1339 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1340 new_pvid);
1341
1342 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1343
1344 return 0;
1345}
1346EXPORT_SYMBOL(b53_vlan_filtering);
1347
1348int b53_vlan_prepare(struct dsa_switch *ds, int port,
1349 const struct switchdev_obj_port_vlan *vlan)
1350{
1351 struct b53_device *dev = ds->priv;
1352
1353 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1354 return -EOPNOTSUPP;
1355
1356 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1357 * receiving VLAN tagged frames at all, we can still allow the port to
1358 * be configured for egress untagged.
1359 */
1360 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1361 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1362 return -EINVAL;
1363
1364 if (vlan->vid_end > dev->num_vlans)
1365 return -ERANGE;
1366
1367 b53_enable_vlan(dev, true, ds->vlan_filtering);
1368
1369 return 0;
1370}
1371EXPORT_SYMBOL(b53_vlan_prepare);
1372
1373void b53_vlan_add(struct dsa_switch *ds, int port,
1374 const struct switchdev_obj_port_vlan *vlan)
1375{
1376 struct b53_device *dev = ds->priv;
1377 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1378 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1379 struct b53_vlan *vl;
1380 u16 vid;
1381
1382 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1383 vl = &dev->vlans[vid];
1384
1385 b53_get_vlan_entry(dev, vid, vl);
1386
1387 if (vid == 0 && vid == b53_default_pvid(dev))
1388 untagged = true;
1389
1390 vl->members |= BIT(port);
1391 if (untagged && !dsa_is_cpu_port(ds, port))
1392 vl->untag |= BIT(port);
1393 else
1394 vl->untag &= ~BIT(port);
1395
1396 b53_set_vlan_entry(dev, vid, vl);
1397 b53_fast_age_vlan(dev, vid);
1398 }
1399
1400 if (pvid && !dsa_is_cpu_port(ds, port)) {
1401 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1402 vlan->vid_end);
1403 b53_fast_age_vlan(dev, vid);
1404 }
1405}
1406EXPORT_SYMBOL(b53_vlan_add);
1407
1408int b53_vlan_del(struct dsa_switch *ds, int port,
1409 const struct switchdev_obj_port_vlan *vlan)
1410{
1411 struct b53_device *dev = ds->priv;
1412 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1413 struct b53_vlan *vl;
1414 u16 vid;
1415 u16 pvid;
1416
1417 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1418
1419 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1420 vl = &dev->vlans[vid];
1421
1422 b53_get_vlan_entry(dev, vid, vl);
1423
1424 vl->members &= ~BIT(port);
1425
1426 if (pvid == vid)
1427 pvid = b53_default_pvid(dev);
1428
1429 if (untagged && !dsa_is_cpu_port(ds, port))
1430 vl->untag &= ~(BIT(port));
1431
1432 b53_set_vlan_entry(dev, vid, vl);
1433 b53_fast_age_vlan(dev, vid);
1434 }
1435
1436 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1437 b53_fast_age_vlan(dev, pvid);
1438
1439 return 0;
1440}
1441EXPORT_SYMBOL(b53_vlan_del);
1442
1443/* Address Resolution Logic routines */
1444static int b53_arl_op_wait(struct b53_device *dev)
1445{
1446 unsigned int timeout = 10;
1447 u8 reg;
1448
1449 do {
1450 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1451 if (!(reg & ARLTBL_START_DONE))
1452 return 0;
1453
1454 usleep_range(1000, 2000);
1455 } while (timeout--);
1456
1457 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1458
1459 return -ETIMEDOUT;
1460}
1461
1462static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1463{
1464 u8 reg;
1465
1466 if (op > ARLTBL_RW)
1467 return -EINVAL;
1468
1469 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1470 reg |= ARLTBL_START_DONE;
1471 if (op)
1472 reg |= ARLTBL_RW;
1473 else
1474 reg &= ~ARLTBL_RW;
1475 if (dev->vlan_enabled)
1476 reg &= ~ARLTBL_IVL_SVL_SELECT;
1477 else
1478 reg |= ARLTBL_IVL_SVL_SELECT;
1479 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1480
1481 return b53_arl_op_wait(dev);
1482}
1483
1484static int b53_arl_read(struct b53_device *dev, u64 mac,
1485 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1486{
1487 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1488 unsigned int i;
1489 int ret;
1490
1491 ret = b53_arl_op_wait(dev);
1492 if (ret)
1493 return ret;
1494
1495 bitmap_zero(free_bins, dev->num_arl_bins);
1496
1497 /* Read the bins */
1498 for (i = 0; i < dev->num_arl_bins; i++) {
1499 u64 mac_vid;
1500 u32 fwd_entry;
1501
1502 b53_read64(dev, B53_ARLIO_PAGE,
1503 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1504 b53_read32(dev, B53_ARLIO_PAGE,
1505 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1506 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1507
1508 if (!(fwd_entry & ARLTBL_VALID)) {
1509 set_bit(i, free_bins);
1510 continue;
1511 }
1512 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1513 continue;
1514 if (dev->vlan_enabled &&
1515 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1516 continue;
1517 *idx = i;
1518 return 0;
1519 }
1520
1521 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0)
1522 return -ENOSPC;
1523
1524 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1525
1526 return -ENOENT;
1527}
1528
1529static int b53_arl_op(struct b53_device *dev, int op, int port,
1530 const unsigned char *addr, u16 vid, bool is_valid)
1531{
1532 struct b53_arl_entry ent;
1533 u32 fwd_entry;
1534 u64 mac, mac_vid = 0;
1535 u8 idx = 0;
1536 int ret;
1537
1538 /* Convert the array into a 64-bit MAC */
1539 mac = ether_addr_to_u64(addr);
1540
1541 /* Perform a read for the given MAC and VID */
1542 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1543 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1544
1545 /* Issue a read operation for this MAC */
1546 ret = b53_arl_rw_op(dev, 1);
1547 if (ret)
1548 return ret;
1549
1550 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1551
1552 /* If this is a read, just finish now */
1553 if (op)
1554 return ret;
1555
1556 switch (ret) {
1557 case -ETIMEDOUT:
1558 return ret;
1559 case -ENOSPC:
1560 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1561 addr, vid);
1562 return is_valid ? ret : 0;
1563 case -ENOENT:
1564 /* We could not find a matching MAC, so reset to a new entry */
1565 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1566 addr, vid, idx);
1567 fwd_entry = 0;
1568 break;
1569 default:
1570 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1571 addr, vid, idx);
1572 break;
1573 }
1574
1575 /* For multicast address, the port is a bitmask and the validity
1576 * is determined by having at least one port being still active
1577 */
1578 if (!is_multicast_ether_addr(addr)) {
1579 ent.port = port;
1580 ent.is_valid = is_valid;
1581 } else {
1582 if (is_valid)
1583 ent.port |= BIT(port);
1584 else
1585 ent.port &= ~BIT(port);
1586
1587 ent.is_valid = !!(ent.port);
1588 }
1589
1590 ent.vid = vid;
1591 ent.is_static = true;
1592 ent.is_age = false;
1593 memcpy(ent.mac, addr, ETH_ALEN);
1594 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1595
1596 b53_write64(dev, B53_ARLIO_PAGE,
1597 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1598 b53_write32(dev, B53_ARLIO_PAGE,
1599 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1600
1601 return b53_arl_rw_op(dev, 0);
1602}
1603
1604int b53_fdb_add(struct dsa_switch *ds, int port,
1605 const unsigned char *addr, u16 vid)
1606{
1607 struct b53_device *priv = ds->priv;
1608
1609 /* 5325 and 5365 require some more massaging, but could
1610 * be supported eventually
1611 */
1612 if (is5325(priv) || is5365(priv))
1613 return -EOPNOTSUPP;
1614
1615 return b53_arl_op(priv, 0, port, addr, vid, true);
1616}
1617EXPORT_SYMBOL(b53_fdb_add);
1618
1619int b53_fdb_del(struct dsa_switch *ds, int port,
1620 const unsigned char *addr, u16 vid)
1621{
1622 struct b53_device *priv = ds->priv;
1623
1624 return b53_arl_op(priv, 0, port, addr, vid, false);
1625}
1626EXPORT_SYMBOL(b53_fdb_del);
1627
1628static int b53_arl_search_wait(struct b53_device *dev)
1629{
1630 unsigned int timeout = 1000;
1631 u8 reg;
1632
1633 do {
1634 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1635 if (!(reg & ARL_SRCH_STDN))
1636 return 0;
1637
1638 if (reg & ARL_SRCH_VLID)
1639 return 0;
1640
1641 usleep_range(1000, 2000);
1642 } while (timeout--);
1643
1644 return -ETIMEDOUT;
1645}
1646
1647static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1648 struct b53_arl_entry *ent)
1649{
1650 u64 mac_vid;
1651 u32 fwd_entry;
1652
1653 b53_read64(dev, B53_ARLIO_PAGE,
1654 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1655 b53_read32(dev, B53_ARLIO_PAGE,
1656 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1657 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1658}
1659
1660static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1661 dsa_fdb_dump_cb_t *cb, void *data)
1662{
1663 if (!ent->is_valid)
1664 return 0;
1665
1666 if (port != ent->port)
1667 return 0;
1668
1669 return cb(ent->mac, ent->vid, ent->is_static, data);
1670}
1671
1672int b53_fdb_dump(struct dsa_switch *ds, int port,
1673 dsa_fdb_dump_cb_t *cb, void *data)
1674{
1675 struct b53_device *priv = ds->priv;
1676 struct b53_arl_entry results[2];
1677 unsigned int count = 0;
1678 int ret;
1679 u8 reg;
1680
1681 /* Start search operation */
1682 reg = ARL_SRCH_STDN;
1683 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1684
1685 do {
1686 ret = b53_arl_search_wait(priv);
1687 if (ret)
1688 return ret;
1689
1690 b53_arl_search_rd(priv, 0, &results[0]);
1691 ret = b53_fdb_copy(port, &results[0], cb, data);
1692 if (ret)
1693 return ret;
1694
1695 if (priv->num_arl_bins > 2) {
1696 b53_arl_search_rd(priv, 1, &results[1]);
1697 ret = b53_fdb_copy(port, &results[1], cb, data);
1698 if (ret)
1699 return ret;
1700
1701 if (!results[0].is_valid && !results[1].is_valid)
1702 break;
1703 }
1704
1705 } while (count++ < b53_max_arl_entries(priv) / 2);
1706
1707 return 0;
1708}
1709EXPORT_SYMBOL(b53_fdb_dump);
1710
1711int b53_mdb_prepare(struct dsa_switch *ds, int port,
1712 const struct switchdev_obj_port_mdb *mdb)
1713{
1714 struct b53_device *priv = ds->priv;
1715
1716 /* 5325 and 5365 require some more massaging, but could
1717 * be supported eventually
1718 */
1719 if (is5325(priv) || is5365(priv))
1720 return -EOPNOTSUPP;
1721
1722 return 0;
1723}
1724EXPORT_SYMBOL(b53_mdb_prepare);
1725
1726void b53_mdb_add(struct dsa_switch *ds, int port,
1727 const struct switchdev_obj_port_mdb *mdb)
1728{
1729 struct b53_device *priv = ds->priv;
1730 int ret;
1731
1732 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1733 if (ret)
1734 dev_err(ds->dev, "failed to add MDB entry\n");
1735}
1736EXPORT_SYMBOL(b53_mdb_add);
1737
1738int b53_mdb_del(struct dsa_switch *ds, int port,
1739 const struct switchdev_obj_port_mdb *mdb)
1740{
1741 struct b53_device *priv = ds->priv;
1742 int ret;
1743
1744 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1745 if (ret)
1746 dev_err(ds->dev, "failed to delete MDB entry\n");
1747
1748 return ret;
1749}
1750EXPORT_SYMBOL(b53_mdb_del);
1751
1752int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1753{
1754 struct b53_device *dev = ds->priv;
1755 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1756 u16 pvlan, reg;
1757 unsigned int i;
1758
1759 /* On 7278, port 7 which connects to the ASP should only receive
1760 * traffic from matching CFP rules.
1761 */
1762 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1763 return -EINVAL;
1764
1765 /* Make this port leave the all VLANs join since we will have proper
1766 * VLAN entries from now on
1767 */
1768 if (is58xx(dev)) {
1769 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1770 reg &= ~BIT(port);
1771 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1772 reg &= ~BIT(cpu_port);
1773 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1774 }
1775
1776 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1777
1778 b53_for_each_port(dev, i) {
1779 if (dsa_to_port(ds, i)->bridge_dev != br)
1780 continue;
1781
1782 /* Add this local port to the remote port VLAN control
1783 * membership and update the remote port bitmask
1784 */
1785 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1786 reg |= BIT(port);
1787 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1788 dev->ports[i].vlan_ctl_mask = reg;
1789
1790 pvlan |= BIT(i);
1791 }
1792
1793 /* Configure the local port VLAN control membership to include
1794 * remote ports and update the local port bitmask
1795 */
1796 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1797 dev->ports[port].vlan_ctl_mask = pvlan;
1798
1799 return 0;
1800}
1801EXPORT_SYMBOL(b53_br_join);
1802
1803void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1804{
1805 struct b53_device *dev = ds->priv;
1806 struct b53_vlan *vl = &dev->vlans[0];
1807 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1808 unsigned int i;
1809 u16 pvlan, reg, pvid;
1810
1811 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1812
1813 b53_for_each_port(dev, i) {
1814 /* Don't touch the remaining ports */
1815 if (dsa_to_port(ds, i)->bridge_dev != br)
1816 continue;
1817
1818 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1819 reg &= ~BIT(port);
1820 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1821 dev->ports[port].vlan_ctl_mask = reg;
1822
1823 /* Prevent self removal to preserve isolation */
1824 if (port != i)
1825 pvlan &= ~BIT(i);
1826 }
1827
1828 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1829 dev->ports[port].vlan_ctl_mask = pvlan;
1830
1831 pvid = b53_default_pvid(dev);
1832
1833 /* Make this port join all VLANs without VLAN entries */
1834 if (is58xx(dev)) {
1835 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1836 reg |= BIT(port);
1837 if (!(reg & BIT(cpu_port)))
1838 reg |= BIT(cpu_port);
1839 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1840 } else {
1841 b53_get_vlan_entry(dev, pvid, vl);
1842 vl->members |= BIT(port) | BIT(cpu_port);
1843 vl->untag |= BIT(port) | BIT(cpu_port);
1844 b53_set_vlan_entry(dev, pvid, vl);
1845 }
1846}
1847EXPORT_SYMBOL(b53_br_leave);
1848
1849void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1850{
1851 struct b53_device *dev = ds->priv;
1852 u8 hw_state;
1853 u8 reg;
1854
1855 switch (state) {
1856 case BR_STATE_DISABLED:
1857 hw_state = PORT_CTRL_DIS_STATE;
1858 break;
1859 case BR_STATE_LISTENING:
1860 hw_state = PORT_CTRL_LISTEN_STATE;
1861 break;
1862 case BR_STATE_LEARNING:
1863 hw_state = PORT_CTRL_LEARN_STATE;
1864 break;
1865 case BR_STATE_FORWARDING:
1866 hw_state = PORT_CTRL_FWD_STATE;
1867 break;
1868 case BR_STATE_BLOCKING:
1869 hw_state = PORT_CTRL_BLOCK_STATE;
1870 break;
1871 default:
1872 dev_err(ds->dev, "invalid STP state: %d\n", state);
1873 return;
1874 }
1875
1876 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1877 reg &= ~PORT_CTRL_STP_STATE_MASK;
1878 reg |= hw_state;
1879 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1880}
1881EXPORT_SYMBOL(b53_br_set_stp_state);
1882
1883void b53_br_fast_age(struct dsa_switch *ds, int port)
1884{
1885 struct b53_device *dev = ds->priv;
1886
1887 if (b53_fast_age_port(dev, port))
1888 dev_err(ds->dev, "fast ageing failed\n");
1889}
1890EXPORT_SYMBOL(b53_br_fast_age);
1891
1892int b53_br_egress_floods(struct dsa_switch *ds, int port,
1893 bool unicast, bool multicast)
1894{
1895 struct b53_device *dev = ds->priv;
1896 u16 uc, mc;
1897
1898 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
1899 if (unicast)
1900 uc |= BIT(port);
1901 else
1902 uc &= ~BIT(port);
1903 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
1904
1905 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
1906 if (multicast)
1907 mc |= BIT(port);
1908 else
1909 mc &= ~BIT(port);
1910 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
1911
1912 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
1913 if (multicast)
1914 mc |= BIT(port);
1915 else
1916 mc &= ~BIT(port);
1917 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
1918
1919 return 0;
1920
1921}
1922EXPORT_SYMBOL(b53_br_egress_floods);
1923
1924static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1925{
1926 /* Broadcom switches will accept enabling Broadcom tags on the
1927 * following ports: 5, 7 and 8, any other port is not supported
1928 */
1929 switch (port) {
1930 case B53_CPU_PORT_25:
1931 case 7:
1932 case B53_CPU_PORT:
1933 return true;
1934 }
1935
1936 return false;
1937}
1938
1939static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
1940 enum dsa_tag_protocol tag_protocol)
1941{
1942 bool ret = b53_possible_cpu_port(ds, port);
1943
1944 if (!ret) {
1945 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1946 port);
1947 return ret;
1948 }
1949
1950 switch (tag_protocol) {
1951 case DSA_TAG_PROTO_BRCM:
1952 case DSA_TAG_PROTO_BRCM_PREPEND:
1953 dev_warn(ds->dev,
1954 "Port %d is stacked to Broadcom tag switch\n", port);
1955 ret = false;
1956 break;
1957 default:
1958 ret = true;
1959 break;
1960 }
1961
1962 return ret;
1963}
1964
1965enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
1966 enum dsa_tag_protocol mprot)
1967{
1968 struct b53_device *dev = ds->priv;
1969
1970 /* Older models (5325, 5365) support a different tag format that we do
1971 * not support in net/dsa/tag_brcm.c yet.
1972 */
1973 if (is5325(dev) || is5365(dev) ||
1974 !b53_can_enable_brcm_tags(ds, port, mprot)) {
1975 dev->tag_protocol = DSA_TAG_PROTO_NONE;
1976 goto out;
1977 }
1978
1979 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1980 * which requires us to use the prepended Broadcom tag type
1981 */
1982 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
1983 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
1984 goto out;
1985 }
1986
1987 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
1988out:
1989 return dev->tag_protocol;
1990}
1991EXPORT_SYMBOL(b53_get_tag_protocol);
1992
1993int b53_mirror_add(struct dsa_switch *ds, int port,
1994 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1995{
1996 struct b53_device *dev = ds->priv;
1997 u16 reg, loc;
1998
1999 if (ingress)
2000 loc = B53_IG_MIR_CTL;
2001 else
2002 loc = B53_EG_MIR_CTL;
2003
2004 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2005 reg |= BIT(port);
2006 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2007
2008 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2009 reg &= ~CAP_PORT_MASK;
2010 reg |= mirror->to_local_port;
2011 reg |= MIRROR_EN;
2012 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2013
2014 return 0;
2015}
2016EXPORT_SYMBOL(b53_mirror_add);
2017
2018void b53_mirror_del(struct dsa_switch *ds, int port,
2019 struct dsa_mall_mirror_tc_entry *mirror)
2020{
2021 struct b53_device *dev = ds->priv;
2022 bool loc_disable = false, other_loc_disable = false;
2023 u16 reg, loc;
2024
2025 if (mirror->ingress)
2026 loc = B53_IG_MIR_CTL;
2027 else
2028 loc = B53_EG_MIR_CTL;
2029
2030 /* Update the desired ingress/egress register */
2031 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2032 reg &= ~BIT(port);
2033 if (!(reg & MIRROR_MASK))
2034 loc_disable = true;
2035 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2036
2037 /* Now look at the other one to know if we can disable mirroring
2038 * entirely
2039 */
2040 if (mirror->ingress)
2041 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2042 else
2043 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2044 if (!(reg & MIRROR_MASK))
2045 other_loc_disable = true;
2046
2047 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2048 /* Both no longer have ports, let's disable mirroring */
2049 if (loc_disable && other_loc_disable) {
2050 reg &= ~MIRROR_EN;
2051 reg &= ~mirror->to_local_port;
2052 }
2053 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2054}
2055EXPORT_SYMBOL(b53_mirror_del);
2056
2057void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2058{
2059 struct b53_device *dev = ds->priv;
2060 u16 reg;
2061
2062 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
2063 if (enable)
2064 reg |= BIT(port);
2065 else
2066 reg &= ~BIT(port);
2067 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2068}
2069EXPORT_SYMBOL(b53_eee_enable_set);
2070
2071
2072/* Returns 0 if EEE was not enabled, or 1 otherwise
2073 */
2074int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2075{
2076 int ret;
2077
2078 ret = phy_init_eee(phy, 0);
2079 if (ret)
2080 return 0;
2081
2082 b53_eee_enable_set(ds, port, true);
2083
2084 return 1;
2085}
2086EXPORT_SYMBOL(b53_eee_init);
2087
2088int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2089{
2090 struct b53_device *dev = ds->priv;
2091 struct ethtool_eee *p = &dev->ports[port].eee;
2092 u16 reg;
2093
2094 if (is5325(dev) || is5365(dev))
2095 return -EOPNOTSUPP;
2096
2097 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
2098 e->eee_enabled = p->eee_enabled;
2099 e->eee_active = !!(reg & BIT(port));
2100
2101 return 0;
2102}
2103EXPORT_SYMBOL(b53_get_mac_eee);
2104
2105int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2106{
2107 struct b53_device *dev = ds->priv;
2108 struct ethtool_eee *p = &dev->ports[port].eee;
2109
2110 if (is5325(dev) || is5365(dev))
2111 return -EOPNOTSUPP;
2112
2113 p->eee_enabled = e->eee_enabled;
2114 b53_eee_enable_set(ds, port, e->eee_enabled);
2115
2116 return 0;
2117}
2118EXPORT_SYMBOL(b53_set_mac_eee);
2119
2120static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2121{
2122 struct b53_device *dev = ds->priv;
2123 bool enable_jumbo;
2124 bool allow_10_100;
2125
2126 if (is5325(dev) || is5365(dev))
2127 return -EOPNOTSUPP;
2128
2129 enable_jumbo = (mtu >= JMS_MIN_SIZE);
2130 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2131
2132 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2133}
2134
2135static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2136{
2137 return JMS_MAX_SIZE;
2138}
2139
2140static const struct dsa_switch_ops b53_switch_ops = {
2141 .get_tag_protocol = b53_get_tag_protocol,
2142 .setup = b53_setup,
2143 .get_strings = b53_get_strings,
2144 .get_ethtool_stats = b53_get_ethtool_stats,
2145 .get_sset_count = b53_get_sset_count,
2146 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2147 .phy_read = b53_phy_read16,
2148 .phy_write = b53_phy_write16,
2149 .adjust_link = b53_adjust_link,
2150 .phylink_validate = b53_phylink_validate,
2151 .phylink_mac_link_state = b53_phylink_mac_link_state,
2152 .phylink_mac_config = b53_phylink_mac_config,
2153 .phylink_mac_an_restart = b53_phylink_mac_an_restart,
2154 .phylink_mac_link_down = b53_phylink_mac_link_down,
2155 .phylink_mac_link_up = b53_phylink_mac_link_up,
2156 .port_enable = b53_enable_port,
2157 .port_disable = b53_disable_port,
2158 .get_mac_eee = b53_get_mac_eee,
2159 .set_mac_eee = b53_set_mac_eee,
2160 .port_bridge_join = b53_br_join,
2161 .port_bridge_leave = b53_br_leave,
2162 .port_stp_state_set = b53_br_set_stp_state,
2163 .port_fast_age = b53_br_fast_age,
2164 .port_egress_floods = b53_br_egress_floods,
2165 .port_vlan_filtering = b53_vlan_filtering,
2166 .port_vlan_prepare = b53_vlan_prepare,
2167 .port_vlan_add = b53_vlan_add,
2168 .port_vlan_del = b53_vlan_del,
2169 .port_fdb_dump = b53_fdb_dump,
2170 .port_fdb_add = b53_fdb_add,
2171 .port_fdb_del = b53_fdb_del,
2172 .port_mirror_add = b53_mirror_add,
2173 .port_mirror_del = b53_mirror_del,
2174 .port_mdb_prepare = b53_mdb_prepare,
2175 .port_mdb_add = b53_mdb_add,
2176 .port_mdb_del = b53_mdb_del,
2177 .port_max_mtu = b53_get_max_mtu,
2178 .port_change_mtu = b53_change_mtu,
2179};
2180
2181struct b53_chip_data {
2182 u32 chip_id;
2183 const char *dev_name;
2184 u16 vlans;
2185 u16 enabled_ports;
2186 u8 cpu_port;
2187 u8 vta_regs[3];
2188 u8 arl_bins;
2189 u16 arl_buckets;
2190 u8 duplex_reg;
2191 u8 jumbo_pm_reg;
2192 u8 jumbo_size_reg;
2193};
2194
2195#define B53_VTA_REGS \
2196 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2197#define B53_VTA_REGS_9798 \
2198 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2199#define B53_VTA_REGS_63XX \
2200 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2201
2202static const struct b53_chip_data b53_switch_chips[] = {
2203 {
2204 .chip_id = BCM5325_DEVICE_ID,
2205 .dev_name = "BCM5325",
2206 .vlans = 16,
2207 .enabled_ports = 0x1f,
2208 .arl_bins = 2,
2209 .arl_buckets = 1024,
2210 .cpu_port = B53_CPU_PORT_25,
2211 .duplex_reg = B53_DUPLEX_STAT_FE,
2212 },
2213 {
2214 .chip_id = BCM5365_DEVICE_ID,
2215 .dev_name = "BCM5365",
2216 .vlans = 256,
2217 .enabled_ports = 0x1f,
2218 .arl_bins = 2,
2219 .arl_buckets = 1024,
2220 .cpu_port = B53_CPU_PORT_25,
2221 .duplex_reg = B53_DUPLEX_STAT_FE,
2222 },
2223 {
2224 .chip_id = BCM5389_DEVICE_ID,
2225 .dev_name = "BCM5389",
2226 .vlans = 4096,
2227 .enabled_ports = 0x1f,
2228 .arl_bins = 4,
2229 .arl_buckets = 1024,
2230 .cpu_port = B53_CPU_PORT,
2231 .vta_regs = B53_VTA_REGS,
2232 .duplex_reg = B53_DUPLEX_STAT_GE,
2233 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2234 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2235 },
2236 {
2237 .chip_id = BCM5395_DEVICE_ID,
2238 .dev_name = "BCM5395",
2239 .vlans = 4096,
2240 .enabled_ports = 0x1f,
2241 .arl_bins = 4,
2242 .arl_buckets = 1024,
2243 .cpu_port = B53_CPU_PORT,
2244 .vta_regs = B53_VTA_REGS,
2245 .duplex_reg = B53_DUPLEX_STAT_GE,
2246 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2247 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2248 },
2249 {
2250 .chip_id = BCM5397_DEVICE_ID,
2251 .dev_name = "BCM5397",
2252 .vlans = 4096,
2253 .enabled_ports = 0x1f,
2254 .arl_bins = 4,
2255 .arl_buckets = 1024,
2256 .cpu_port = B53_CPU_PORT,
2257 .vta_regs = B53_VTA_REGS_9798,
2258 .duplex_reg = B53_DUPLEX_STAT_GE,
2259 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2260 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2261 },
2262 {
2263 .chip_id = BCM5398_DEVICE_ID,
2264 .dev_name = "BCM5398",
2265 .vlans = 4096,
2266 .enabled_ports = 0x7f,
2267 .arl_bins = 4,
2268 .arl_buckets = 1024,
2269 .cpu_port = B53_CPU_PORT,
2270 .vta_regs = B53_VTA_REGS_9798,
2271 .duplex_reg = B53_DUPLEX_STAT_GE,
2272 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2273 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2274 },
2275 {
2276 .chip_id = BCM53115_DEVICE_ID,
2277 .dev_name = "BCM53115",
2278 .vlans = 4096,
2279 .enabled_ports = 0x1f,
2280 .arl_bins = 4,
2281 .arl_buckets = 1024,
2282 .vta_regs = B53_VTA_REGS,
2283 .cpu_port = B53_CPU_PORT,
2284 .duplex_reg = B53_DUPLEX_STAT_GE,
2285 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2286 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2287 },
2288 {
2289 .chip_id = BCM53125_DEVICE_ID,
2290 .dev_name = "BCM53125",
2291 .vlans = 4096,
2292 .enabled_ports = 0xff,
2293 .arl_bins = 4,
2294 .arl_buckets = 1024,
2295 .cpu_port = B53_CPU_PORT,
2296 .vta_regs = B53_VTA_REGS,
2297 .duplex_reg = B53_DUPLEX_STAT_GE,
2298 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2299 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2300 },
2301 {
2302 .chip_id = BCM53128_DEVICE_ID,
2303 .dev_name = "BCM53128",
2304 .vlans = 4096,
2305 .enabled_ports = 0x1ff,
2306 .arl_bins = 4,
2307 .arl_buckets = 1024,
2308 .cpu_port = B53_CPU_PORT,
2309 .vta_regs = B53_VTA_REGS,
2310 .duplex_reg = B53_DUPLEX_STAT_GE,
2311 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2312 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2313 },
2314 {
2315 .chip_id = BCM63XX_DEVICE_ID,
2316 .dev_name = "BCM63xx",
2317 .vlans = 4096,
2318 .enabled_ports = 0, /* pdata must provide them */
2319 .arl_bins = 4,
2320 .arl_buckets = 1024,
2321 .cpu_port = B53_CPU_PORT,
2322 .vta_regs = B53_VTA_REGS_63XX,
2323 .duplex_reg = B53_DUPLEX_STAT_63XX,
2324 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2325 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2326 },
2327 {
2328 .chip_id = BCM53010_DEVICE_ID,
2329 .dev_name = "BCM53010",
2330 .vlans = 4096,
2331 .enabled_ports = 0x1f,
2332 .arl_bins = 4,
2333 .arl_buckets = 1024,
2334 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2335 .vta_regs = B53_VTA_REGS,
2336 .duplex_reg = B53_DUPLEX_STAT_GE,
2337 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2338 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2339 },
2340 {
2341 .chip_id = BCM53011_DEVICE_ID,
2342 .dev_name = "BCM53011",
2343 .vlans = 4096,
2344 .enabled_ports = 0x1bf,
2345 .arl_bins = 4,
2346 .arl_buckets = 1024,
2347 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2348 .vta_regs = B53_VTA_REGS,
2349 .duplex_reg = B53_DUPLEX_STAT_GE,
2350 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2351 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2352 },
2353 {
2354 .chip_id = BCM53012_DEVICE_ID,
2355 .dev_name = "BCM53012",
2356 .vlans = 4096,
2357 .enabled_ports = 0x1bf,
2358 .arl_bins = 4,
2359 .arl_buckets = 1024,
2360 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2361 .vta_regs = B53_VTA_REGS,
2362 .duplex_reg = B53_DUPLEX_STAT_GE,
2363 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2364 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2365 },
2366 {
2367 .chip_id = BCM53018_DEVICE_ID,
2368 .dev_name = "BCM53018",
2369 .vlans = 4096,
2370 .enabled_ports = 0x1f,
2371 .arl_bins = 4,
2372 .arl_buckets = 1024,
2373 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2374 .vta_regs = B53_VTA_REGS,
2375 .duplex_reg = B53_DUPLEX_STAT_GE,
2376 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2377 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2378 },
2379 {
2380 .chip_id = BCM53019_DEVICE_ID,
2381 .dev_name = "BCM53019",
2382 .vlans = 4096,
2383 .enabled_ports = 0x1f,
2384 .arl_bins = 4,
2385 .arl_buckets = 1024,
2386 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2387 .vta_regs = B53_VTA_REGS,
2388 .duplex_reg = B53_DUPLEX_STAT_GE,
2389 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2390 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2391 },
2392 {
2393 .chip_id = BCM58XX_DEVICE_ID,
2394 .dev_name = "BCM585xx/586xx/88312",
2395 .vlans = 4096,
2396 .enabled_ports = 0x1ff,
2397 .arl_bins = 4,
2398 .arl_buckets = 1024,
2399 .cpu_port = B53_CPU_PORT,
2400 .vta_regs = B53_VTA_REGS,
2401 .duplex_reg = B53_DUPLEX_STAT_GE,
2402 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2403 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2404 },
2405 {
2406 .chip_id = BCM583XX_DEVICE_ID,
2407 .dev_name = "BCM583xx/11360",
2408 .vlans = 4096,
2409 .enabled_ports = 0x103,
2410 .arl_bins = 4,
2411 .arl_buckets = 1024,
2412 .cpu_port = B53_CPU_PORT,
2413 .vta_regs = B53_VTA_REGS,
2414 .duplex_reg = B53_DUPLEX_STAT_GE,
2415 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2416 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2417 },
2418 {
2419 .chip_id = BCM7445_DEVICE_ID,
2420 .dev_name = "BCM7445",
2421 .vlans = 4096,
2422 .enabled_ports = 0x1ff,
2423 .arl_bins = 4,
2424 .arl_buckets = 1024,
2425 .cpu_port = B53_CPU_PORT,
2426 .vta_regs = B53_VTA_REGS,
2427 .duplex_reg = B53_DUPLEX_STAT_GE,
2428 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2429 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2430 },
2431 {
2432 .chip_id = BCM7278_DEVICE_ID,
2433 .dev_name = "BCM7278",
2434 .vlans = 4096,
2435 .enabled_ports = 0x1ff,
2436 .arl_bins = 4,
2437 .arl_buckets = 256,
2438 .cpu_port = B53_CPU_PORT,
2439 .vta_regs = B53_VTA_REGS,
2440 .duplex_reg = B53_DUPLEX_STAT_GE,
2441 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2442 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2443 },
2444};
2445
2446static int b53_switch_init(struct b53_device *dev)
2447{
2448 unsigned int i;
2449 int ret;
2450
2451 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2452 const struct b53_chip_data *chip = &b53_switch_chips[i];
2453
2454 if (chip->chip_id == dev->chip_id) {
2455 if (!dev->enabled_ports)
2456 dev->enabled_ports = chip->enabled_ports;
2457 dev->name = chip->dev_name;
2458 dev->duplex_reg = chip->duplex_reg;
2459 dev->vta_regs[0] = chip->vta_regs[0];
2460 dev->vta_regs[1] = chip->vta_regs[1];
2461 dev->vta_regs[2] = chip->vta_regs[2];
2462 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2463 dev->cpu_port = chip->cpu_port;
2464 dev->num_vlans = chip->vlans;
2465 dev->num_arl_bins = chip->arl_bins;
2466 dev->num_arl_buckets = chip->arl_buckets;
2467 break;
2468 }
2469 }
2470
2471 /* check which BCM5325x version we have */
2472 if (is5325(dev)) {
2473 u8 vc4;
2474
2475 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2476
2477 /* check reserved bits */
2478 switch (vc4 & 3) {
2479 case 1:
2480 /* BCM5325E */
2481 break;
2482 case 3:
2483 /* BCM5325F - do not use port 4 */
2484 dev->enabled_ports &= ~BIT(4);
2485 break;
2486 default:
2487/* On the BCM47XX SoCs this is the supported internal switch.*/
2488#ifndef CONFIG_BCM47XX
2489 /* BCM5325M */
2490 return -EINVAL;
2491#else
2492 break;
2493#endif
2494 }
2495 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2496 u64 strap_value;
2497
2498 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2499 /* use second IMP port if GMII is enabled */
2500 if (strap_value & SV_GMII_CTRL_115)
2501 dev->cpu_port = 5;
2502 }
2503
2504 /* cpu port is always last */
2505 dev->num_ports = dev->cpu_port + 1;
2506 dev->enabled_ports |= BIT(dev->cpu_port);
2507
2508 /* Include non standard CPU port built-in PHYs to be probed */
2509 if (is539x(dev) || is531x5(dev)) {
2510 for (i = 0; i < dev->num_ports; i++) {
2511 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2512 !b53_possible_cpu_port(dev->ds, i))
2513 dev->ds->phys_mii_mask |= BIT(i);
2514 }
2515 }
2516
2517 dev->ports = devm_kcalloc(dev->dev,
2518 dev->num_ports, sizeof(struct b53_port),
2519 GFP_KERNEL);
2520 if (!dev->ports)
2521 return -ENOMEM;
2522
2523 dev->vlans = devm_kcalloc(dev->dev,
2524 dev->num_vlans, sizeof(struct b53_vlan),
2525 GFP_KERNEL);
2526 if (!dev->vlans)
2527 return -ENOMEM;
2528
2529 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2530 if (dev->reset_gpio >= 0) {
2531 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2532 GPIOF_OUT_INIT_HIGH, "robo_reset");
2533 if (ret)
2534 return ret;
2535 }
2536
2537 return 0;
2538}
2539
2540struct b53_device *b53_switch_alloc(struct device *base,
2541 const struct b53_io_ops *ops,
2542 void *priv)
2543{
2544 struct dsa_switch *ds;
2545 struct b53_device *dev;
2546
2547 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2548 if (!ds)
2549 return NULL;
2550
2551 ds->dev = base;
2552 ds->num_ports = DSA_MAX_PORTS;
2553
2554 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2555 if (!dev)
2556 return NULL;
2557
2558 ds->priv = dev;
2559 dev->dev = base;
2560
2561 dev->ds = ds;
2562 dev->priv = priv;
2563 dev->ops = ops;
2564 ds->ops = &b53_switch_ops;
2565 mutex_init(&dev->reg_mutex);
2566 mutex_init(&dev->stats_mutex);
2567
2568 return dev;
2569}
2570EXPORT_SYMBOL(b53_switch_alloc);
2571
2572int b53_switch_detect(struct b53_device *dev)
2573{
2574 u32 id32;
2575 u16 tmp;
2576 u8 id8;
2577 int ret;
2578
2579 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2580 if (ret)
2581 return ret;
2582
2583 switch (id8) {
2584 case 0:
2585 /* BCM5325 and BCM5365 do not have this register so reads
2586 * return 0. But the read operation did succeed, so assume this
2587 * is one of them.
2588 *
2589 * Next check if we can write to the 5325's VTA register; for
2590 * 5365 it is read only.
2591 */
2592 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2593 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2594
2595 if (tmp == 0xf)
2596 dev->chip_id = BCM5325_DEVICE_ID;
2597 else
2598 dev->chip_id = BCM5365_DEVICE_ID;
2599 break;
2600 case BCM5389_DEVICE_ID:
2601 case BCM5395_DEVICE_ID:
2602 case BCM5397_DEVICE_ID:
2603 case BCM5398_DEVICE_ID:
2604 dev->chip_id = id8;
2605 break;
2606 default:
2607 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2608 if (ret)
2609 return ret;
2610
2611 switch (id32) {
2612 case BCM53115_DEVICE_ID:
2613 case BCM53125_DEVICE_ID:
2614 case BCM53128_DEVICE_ID:
2615 case BCM53010_DEVICE_ID:
2616 case BCM53011_DEVICE_ID:
2617 case BCM53012_DEVICE_ID:
2618 case BCM53018_DEVICE_ID:
2619 case BCM53019_DEVICE_ID:
2620 dev->chip_id = id32;
2621 break;
2622 default:
2623 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2624 id8, id32);
2625 return -ENODEV;
2626 }
2627 }
2628
2629 if (dev->chip_id == BCM5325_DEVICE_ID)
2630 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2631 &dev->core_rev);
2632 else
2633 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2634 &dev->core_rev);
2635}
2636EXPORT_SYMBOL(b53_switch_detect);
2637
2638int b53_switch_register(struct b53_device *dev)
2639{
2640 int ret;
2641
2642 if (dev->pdata) {
2643 dev->chip_id = dev->pdata->chip_id;
2644 dev->enabled_ports = dev->pdata->enabled_ports;
2645 }
2646
2647 if (!dev->chip_id && b53_switch_detect(dev))
2648 return -EINVAL;
2649
2650 ret = b53_switch_init(dev);
2651 if (ret)
2652 return ret;
2653
2654 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2655
2656 return dsa_register_switch(dev->ds);
2657}
2658EXPORT_SYMBOL(b53_switch_register);
2659
2660MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2661MODULE_DESCRIPTION("B53 switch library");
2662MODULE_LICENSE("Dual BSD/GPL");