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1// SPDX-License-Identifier: GPL-2.0
2// SPI to CAN driver for the Texas Instruments TCAN4x5x
3// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
4
5#include <linux/regmap.h>
6#include <linux/spi/spi.h>
7
8#include <linux/regulator/consumer.h>
9#include <linux/gpio/consumer.h>
10
11#include "m_can.h"
12
13#define DEVICE_NAME "tcan4x5x"
14#define TCAN4X5X_EXT_CLK_DEF 40000000
15
16#define TCAN4X5X_DEV_ID0 0x00
17#define TCAN4X5X_DEV_ID1 0x04
18#define TCAN4X5X_REV 0x08
19#define TCAN4X5X_STATUS 0x0C
20#define TCAN4X5X_ERROR_STATUS 0x10
21#define TCAN4X5X_CONTROL 0x14
22
23#define TCAN4X5X_CONFIG 0x800
24#define TCAN4X5X_TS_PRESCALE 0x804
25#define TCAN4X5X_TEST_REG 0x808
26#define TCAN4X5X_INT_FLAGS 0x820
27#define TCAN4X5X_MCAN_INT_REG 0x824
28#define TCAN4X5X_INT_EN 0x830
29
30/* Interrupt bits */
31#define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
32#define TCAN4X5X_CANHCANL_INT_EN BIT(29)
33#define TCAN4X5X_CANHBAT_INT_EN BIT(28)
34#define TCAN4X5X_CANLGND_INT_EN BIT(27)
35#define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
36#define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
37#define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
38#define TCAN4X5X_UVSUP_INT_EN BIT(22)
39#define TCAN4X5X_UVIO_INT_EN BIT(21)
40#define TCAN4X5X_TSD_INT_EN BIT(19)
41#define TCAN4X5X_ECCERR_INT_EN BIT(16)
42#define TCAN4X5X_CANINT_INT_EN BIT(15)
43#define TCAN4X5X_LWU_INT_EN BIT(14)
44#define TCAN4X5X_CANSLNT_INT_EN BIT(10)
45#define TCAN4X5X_CANDOM_INT_EN BIT(8)
46#define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
47#define TCAN4X5X_BUS_FAULT BIT(4)
48#define TCAN4X5X_MCAN_INT BIT(1)
49#define TCAN4X5X_ENABLE_TCAN_INT \
50 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
51 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
52
53/* MCAN Interrupt bits */
54#define TCAN4X5X_MCAN_IR_ARA BIT(29)
55#define TCAN4X5X_MCAN_IR_PED BIT(28)
56#define TCAN4X5X_MCAN_IR_PEA BIT(27)
57#define TCAN4X5X_MCAN_IR_WD BIT(26)
58#define TCAN4X5X_MCAN_IR_BO BIT(25)
59#define TCAN4X5X_MCAN_IR_EW BIT(24)
60#define TCAN4X5X_MCAN_IR_EP BIT(23)
61#define TCAN4X5X_MCAN_IR_ELO BIT(22)
62#define TCAN4X5X_MCAN_IR_BEU BIT(21)
63#define TCAN4X5X_MCAN_IR_BEC BIT(20)
64#define TCAN4X5X_MCAN_IR_DRX BIT(19)
65#define TCAN4X5X_MCAN_IR_TOO BIT(18)
66#define TCAN4X5X_MCAN_IR_MRAF BIT(17)
67#define TCAN4X5X_MCAN_IR_TSW BIT(16)
68#define TCAN4X5X_MCAN_IR_TEFL BIT(15)
69#define TCAN4X5X_MCAN_IR_TEFF BIT(14)
70#define TCAN4X5X_MCAN_IR_TEFW BIT(13)
71#define TCAN4X5X_MCAN_IR_TEFN BIT(12)
72#define TCAN4X5X_MCAN_IR_TFE BIT(11)
73#define TCAN4X5X_MCAN_IR_TCF BIT(10)
74#define TCAN4X5X_MCAN_IR_TC BIT(9)
75#define TCAN4X5X_MCAN_IR_HPM BIT(8)
76#define TCAN4X5X_MCAN_IR_RF1L BIT(7)
77#define TCAN4X5X_MCAN_IR_RF1F BIT(6)
78#define TCAN4X5X_MCAN_IR_RF1W BIT(5)
79#define TCAN4X5X_MCAN_IR_RF1N BIT(4)
80#define TCAN4X5X_MCAN_IR_RF0L BIT(3)
81#define TCAN4X5X_MCAN_IR_RF0F BIT(2)
82#define TCAN4X5X_MCAN_IR_RF0W BIT(1)
83#define TCAN4X5X_MCAN_IR_RF0N BIT(0)
84#define TCAN4X5X_ENABLE_MCAN_INT \
85 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
86 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
87 TCAN4X5X_MCAN_IR_RF1F)
88
89#define TCAN4X5X_MRAM_START 0x8000
90#define TCAN4X5X_MCAN_OFFSET 0x1000
91#define TCAN4X5X_MAX_REGISTER 0x8fff
92
93#define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
94#define TCAN4X5X_SET_ALL_INT 0xffffffff
95
96#define TCAN4X5X_WRITE_CMD (0x61 << 24)
97#define TCAN4X5X_READ_CMD (0x41 << 24)
98
99#define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
100#define TCAN4X5X_MODE_SLEEP 0x00
101#define TCAN4X5X_MODE_STANDBY BIT(6)
102#define TCAN4X5X_MODE_NORMAL BIT(7)
103
104#define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30))
105#define TCAN4X5X_DISABLE_INH_MSK BIT(9)
106
107#define TCAN4X5X_SW_RESET BIT(2)
108
109#define TCAN4X5X_MCAN_CONFIGURED BIT(5)
110#define TCAN4X5X_WATCHDOG_EN BIT(3)
111#define TCAN4X5X_WD_60_MS_TIMER 0
112#define TCAN4X5X_WD_600_MS_TIMER BIT(28)
113#define TCAN4X5X_WD_3_S_TIMER BIT(29)
114#define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
115
116struct tcan4x5x_priv {
117 struct regmap *regmap;
118 struct spi_device *spi;
119
120 struct m_can_classdev *mcan_dev;
121
122 struct gpio_desc *reset_gpio;
123 struct gpio_desc *device_wake_gpio;
124 struct gpio_desc *device_state_gpio;
125 struct regulator *power;
126
127 /* Register based ip */
128 int mram_start;
129 int reg_offset;
130};
131
132static struct can_bittiming_const tcan4x5x_bittiming_const = {
133 .name = DEVICE_NAME,
134 .tseg1_min = 2,
135 .tseg1_max = 31,
136 .tseg2_min = 2,
137 .tseg2_max = 16,
138 .sjw_max = 16,
139 .brp_min = 1,
140 .brp_max = 32,
141 .brp_inc = 1,
142};
143
144static struct can_bittiming_const tcan4x5x_data_bittiming_const = {
145 .name = DEVICE_NAME,
146 .tseg1_min = 1,
147 .tseg1_max = 32,
148 .tseg2_min = 1,
149 .tseg2_max = 16,
150 .sjw_max = 16,
151 .brp_min = 1,
152 .brp_max = 32,
153 .brp_inc = 1,
154};
155
156static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
157{
158 int wake_state = 0;
159
160 if (priv->device_state_gpio)
161 wake_state = gpiod_get_value(priv->device_state_gpio);
162
163 if (priv->device_wake_gpio && wake_state) {
164 gpiod_set_value(priv->device_wake_gpio, 0);
165 usleep_range(5, 50);
166 gpiod_set_value(priv->device_wake_gpio, 1);
167 }
168}
169
170static int tcan4x5x_reset(struct tcan4x5x_priv *priv)
171{
172 int ret = 0;
173
174 if (priv->reset_gpio) {
175 gpiod_set_value(priv->reset_gpio, 1);
176
177 /* tpulse_width minimum 30us */
178 usleep_range(30, 100);
179 gpiod_set_value(priv->reset_gpio, 0);
180 } else {
181 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG,
182 TCAN4X5X_SW_RESET);
183 if (ret)
184 return ret;
185 }
186
187 usleep_range(700, 1000);
188
189 return ret;
190}
191
192static int regmap_spi_gather_write(void *context, const void *reg,
193 size_t reg_len, const void *val,
194 size_t val_len)
195{
196 struct device *dev = context;
197 struct spi_device *spi = to_spi_device(dev);
198 struct spi_message m;
199 u32 addr;
200 struct spi_transfer t[2] = {
201 { .tx_buf = &addr, .len = reg_len, .cs_change = 0,},
202 { .tx_buf = val, .len = val_len, },
203 };
204
205 addr = TCAN4X5X_WRITE_CMD | (*((u16 *)reg) << 8) | val_len >> 2;
206
207 spi_message_init(&m);
208 spi_message_add_tail(&t[0], &m);
209 spi_message_add_tail(&t[1], &m);
210
211 return spi_sync(spi, &m);
212}
213
214static int tcan4x5x_regmap_write(void *context, const void *data, size_t count)
215{
216 u16 *reg = (u16 *)(data);
217 const u32 *val = data + 4;
218
219 return regmap_spi_gather_write(context, reg, 4, val, count - 4);
220}
221
222static int regmap_spi_async_write(void *context,
223 const void *reg, size_t reg_len,
224 const void *val, size_t val_len,
225 struct regmap_async *a)
226{
227 return -ENOTSUPP;
228}
229
230static struct regmap_async *regmap_spi_async_alloc(void)
231{
232 return NULL;
233}
234
235static int tcan4x5x_regmap_read(void *context,
236 const void *reg, size_t reg_size,
237 void *val, size_t val_size)
238{
239 struct device *dev = context;
240 struct spi_device *spi = to_spi_device(dev);
241
242 u32 addr = TCAN4X5X_READ_CMD | (*((u16 *)reg) << 8) | val_size >> 2;
243
244 return spi_write_then_read(spi, &addr, reg_size, (u32 *)val, val_size);
245}
246
247static struct regmap_bus tcan4x5x_bus = {
248 .write = tcan4x5x_regmap_write,
249 .gather_write = regmap_spi_gather_write,
250 .async_write = regmap_spi_async_write,
251 .async_alloc = regmap_spi_async_alloc,
252 .read = tcan4x5x_regmap_read,
253 .read_flag_mask = 0x00,
254 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
255 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
256};
257
258static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
259{
260 struct tcan4x5x_priv *priv = cdev->device_data;
261 u32 val;
262
263 regmap_read(priv->regmap, priv->reg_offset + reg, &val);
264
265 return val;
266}
267
268static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
269{
270 struct tcan4x5x_priv *priv = cdev->device_data;
271 u32 val;
272
273 regmap_read(priv->regmap, priv->mram_start + addr_offset, &val);
274
275 return val;
276}
277
278static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
279{
280 struct tcan4x5x_priv *priv = cdev->device_data;
281
282 return regmap_write(priv->regmap, priv->reg_offset + reg, val);
283}
284
285static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
286 int addr_offset, int val)
287{
288 struct tcan4x5x_priv *priv = cdev->device_data;
289
290 return regmap_write(priv->regmap, priv->mram_start + addr_offset, val);
291}
292
293static int tcan4x5x_power_enable(struct regulator *reg, int enable)
294{
295 if (IS_ERR_OR_NULL(reg))
296 return 0;
297
298 if (enable)
299 return regulator_enable(reg);
300 else
301 return regulator_disable(reg);
302}
303
304static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
305 int reg, int val)
306{
307 struct tcan4x5x_priv *priv = cdev->device_data;
308
309 return regmap_write(priv->regmap, reg, val);
310}
311
312static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
313{
314 int ret;
315
316 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
317 TCAN4X5X_CLEAR_ALL_INT);
318 if (ret)
319 return ret;
320
321 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG,
322 TCAN4X5X_ENABLE_MCAN_INT);
323 if (ret)
324 return ret;
325
326 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
327 TCAN4X5X_CLEAR_ALL_INT);
328 if (ret)
329 return ret;
330
331 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS,
332 TCAN4X5X_CLEAR_ALL_INT);
333 if (ret)
334 return ret;
335
336 return ret;
337}
338
339static int tcan4x5x_init(struct m_can_classdev *cdev)
340{
341 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
342 int ret;
343
344 tcan4x5x_check_wake(tcan4x5x);
345
346 ret = tcan4x5x_clear_interrupts(cdev);
347 if (ret)
348 return ret;
349
350 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
351 TCAN4X5X_ENABLE_TCAN_INT);
352 if (ret)
353 return ret;
354
355 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
356 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
357 if (ret)
358 return ret;
359
360 /* Zero out the MCAN buffers */
361 m_can_init_ram(cdev);
362
363 return ret;
364}
365
366static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
367{
368 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
369
370 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
371 TCAN4X5X_DISABLE_WAKE_MSK, 0x00);
372}
373
374static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
375{
376 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
377
378 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
379 TCAN4X5X_DISABLE_INH_MSK, 0x01);
380}
381
382static int tcan4x5x_parse_config(struct m_can_classdev *cdev)
383{
384 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
385 int ret;
386
387 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
388 GPIOD_OUT_HIGH);
389 if (IS_ERR(tcan4x5x->device_wake_gpio)) {
390 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER)
391 return -EPROBE_DEFER;
392
393 tcan4x5x_disable_wake(cdev);
394 }
395
396 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
397 GPIOD_OUT_LOW);
398 if (IS_ERR(tcan4x5x->reset_gpio))
399 tcan4x5x->reset_gpio = NULL;
400
401 ret = tcan4x5x_reset(tcan4x5x);
402 if (ret)
403 return ret;
404
405 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
406 "device-state",
407 GPIOD_IN);
408 if (IS_ERR(tcan4x5x->device_state_gpio)) {
409 tcan4x5x->device_state_gpio = NULL;
410 tcan4x5x_disable_state(cdev);
411 }
412
413 return 0;
414}
415
416static const struct regmap_config tcan4x5x_regmap = {
417 .reg_bits = 32,
418 .val_bits = 32,
419 .cache_type = REGCACHE_NONE,
420 .max_register = TCAN4X5X_MAX_REGISTER,
421};
422
423static struct m_can_ops tcan4x5x_ops = {
424 .init = tcan4x5x_init,
425 .read_reg = tcan4x5x_read_reg,
426 .write_reg = tcan4x5x_write_reg,
427 .write_fifo = tcan4x5x_write_fifo,
428 .read_fifo = tcan4x5x_read_fifo,
429 .clear_interrupts = tcan4x5x_clear_interrupts,
430};
431
432static int tcan4x5x_can_probe(struct spi_device *spi)
433{
434 struct tcan4x5x_priv *priv;
435 struct m_can_classdev *mcan_class;
436 int freq, ret;
437
438 mcan_class = m_can_class_allocate_dev(&spi->dev);
439 if (!mcan_class)
440 return -ENOMEM;
441
442 priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
443 if (!priv)
444 return -ENOMEM;
445
446 priv->power = devm_regulator_get_optional(&spi->dev, "vsup");
447 if (PTR_ERR(priv->power) == -EPROBE_DEFER)
448 return -EPROBE_DEFER;
449 else
450 priv->power = NULL;
451
452 mcan_class->device_data = priv;
453
454 m_can_class_get_clocks(mcan_class);
455 if (IS_ERR(mcan_class->cclk)) {
456 dev_err(&spi->dev, "no CAN clock source defined\n");
457 freq = TCAN4X5X_EXT_CLK_DEF;
458 } else {
459 freq = clk_get_rate(mcan_class->cclk);
460 }
461
462 /* Sanity check */
463 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF)
464 return -ERANGE;
465
466 priv->reg_offset = TCAN4X5X_MCAN_OFFSET;
467 priv->mram_start = TCAN4X5X_MRAM_START;
468 priv->spi = spi;
469 priv->mcan_dev = mcan_class;
470
471 mcan_class->pm_clock_support = 0;
472 mcan_class->can.clock.freq = freq;
473 mcan_class->dev = &spi->dev;
474 mcan_class->ops = &tcan4x5x_ops;
475 mcan_class->is_peripheral = true;
476 mcan_class->bit_timing = &tcan4x5x_bittiming_const;
477 mcan_class->data_timing = &tcan4x5x_data_bittiming_const;
478 mcan_class->net->irq = spi->irq;
479
480 spi_set_drvdata(spi, priv);
481
482 /* Configure the SPI bus */
483 spi->bits_per_word = 32;
484 ret = spi_setup(spi);
485 if (ret)
486 goto out_clk;
487
488 priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus,
489 &spi->dev, &tcan4x5x_regmap);
490
491 ret = tcan4x5x_power_enable(priv->power, 1);
492 if (ret)
493 goto out_clk;
494
495 ret = tcan4x5x_parse_config(mcan_class);
496 if (ret)
497 goto out_power;
498
499 ret = tcan4x5x_init(mcan_class);
500 if (ret)
501 goto out_power;
502
503 ret = m_can_class_register(mcan_class);
504 if (ret)
505 goto out_power;
506
507 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
508 return 0;
509
510out_power:
511 tcan4x5x_power_enable(priv->power, 0);
512out_clk:
513 if (!IS_ERR(mcan_class->cclk)) {
514 clk_disable_unprepare(mcan_class->cclk);
515 clk_disable_unprepare(mcan_class->hclk);
516 }
517
518 dev_err(&spi->dev, "Probe failed, err=%d\n", ret);
519 return ret;
520}
521
522static int tcan4x5x_can_remove(struct spi_device *spi)
523{
524 struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
525
526 tcan4x5x_power_enable(priv->power, 0);
527
528 m_can_class_unregister(priv->mcan_dev);
529
530 return 0;
531}
532
533static const struct of_device_id tcan4x5x_of_match[] = {
534 { .compatible = "ti,tcan4x5x", },
535 { }
536};
537MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
538
539static const struct spi_device_id tcan4x5x_id_table[] = {
540 {
541 .name = "tcan4x5x",
542 .driver_data = 0,
543 },
544 { }
545};
546MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
547
548static struct spi_driver tcan4x5x_can_driver = {
549 .driver = {
550 .name = DEVICE_NAME,
551 .of_match_table = tcan4x5x_of_match,
552 .pm = NULL,
553 },
554 .id_table = tcan4x5x_id_table,
555 .probe = tcan4x5x_can_probe,
556 .remove = tcan4x5x_can_remove,
557};
558module_spi_driver(tcan4x5x_can_driver);
559
560MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
561MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
562MODULE_LICENSE("GPL v2");