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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/cleanup.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio/driver.h>
13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/mfd/stmpe.h>
16#include <linux/seq_file.h>
17#include <linux/bitops.h>
18
19/*
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
22 */
23enum { REG_RE, REG_FE, REG_IE };
24
25enum { LSB, CSB, MSB };
26
27#define CACHE_NR_REGS 3
28/* No variant has more than 24 GPIOs */
29#define CACHE_NR_BANKS (24 / 8)
30
31struct stmpe_gpio {
32 struct gpio_chip chip;
33 struct stmpe *stmpe;
34 struct device *dev;
35 struct mutex irq_lock;
36 u32 norequest_mask;
37 /* Caches of interrupt control registers for bus_lock */
38 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
39 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
40};
41
42static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
43{
44 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
45 struct stmpe *stmpe = stmpe_gpio->stmpe;
46 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
47 u8 mask = BIT(offset % 8);
48 int ret;
49
50 ret = stmpe_reg_read(stmpe, reg);
51 if (ret < 0)
52 return ret;
53
54 return !!(ret & mask);
55}
56
57static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
58{
59 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
60 struct stmpe *stmpe = stmpe_gpio->stmpe;
61 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
62 u8 reg = stmpe->regs[which + (offset / 8)];
63 u8 mask = BIT(offset % 8);
64
65 /*
66 * Some variants have single register for gpio set/clear functionality.
67 * For them we need to write 0 to clear and 1 to set.
68 */
69 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
70 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
71 else
72 stmpe_reg_write(stmpe, reg, mask);
73}
74
75static int stmpe_gpio_get_direction(struct gpio_chip *chip,
76 unsigned offset)
77{
78 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
79 struct stmpe *stmpe = stmpe_gpio->stmpe;
80 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
81 u8 mask = BIT(offset % 8);
82 int ret;
83
84 ret = stmpe_reg_read(stmpe, reg);
85 if (ret < 0)
86 return ret;
87
88 if (ret & mask)
89 return GPIO_LINE_DIRECTION_OUT;
90
91 return GPIO_LINE_DIRECTION_IN;
92}
93
94static int stmpe_gpio_direction_output(struct gpio_chip *chip,
95 unsigned offset, int val)
96{
97 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
98 struct stmpe *stmpe = stmpe_gpio->stmpe;
99 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
100 u8 mask = BIT(offset % 8);
101
102 stmpe_gpio_set(chip, offset, val);
103
104 return stmpe_set_bits(stmpe, reg, mask, mask);
105}
106
107static int stmpe_gpio_direction_input(struct gpio_chip *chip,
108 unsigned offset)
109{
110 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
111 struct stmpe *stmpe = stmpe_gpio->stmpe;
112 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
113 u8 mask = BIT(offset % 8);
114
115 return stmpe_set_bits(stmpe, reg, mask, 0);
116}
117
118static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
119{
120 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
121 struct stmpe *stmpe = stmpe_gpio->stmpe;
122
123 if (stmpe_gpio->norequest_mask & BIT(offset))
124 return -EINVAL;
125
126 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
127}
128
129static const struct gpio_chip template_chip = {
130 .label = "stmpe",
131 .owner = THIS_MODULE,
132 .get_direction = stmpe_gpio_get_direction,
133 .direction_input = stmpe_gpio_direction_input,
134 .get = stmpe_gpio_get,
135 .direction_output = stmpe_gpio_direction_output,
136 .set = stmpe_gpio_set,
137 .request = stmpe_gpio_request,
138 .can_sleep = true,
139};
140
141static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
142{
143 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
144 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
145 int offset = d->hwirq;
146 int regoffset = offset / 8;
147 int mask = BIT(offset % 8);
148
149 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
150 return -EINVAL;
151
152 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
153 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
154 stmpe_gpio->stmpe->partnum == STMPE1600)
155 return 0;
156
157 if (type & IRQ_TYPE_EDGE_RISING)
158 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
159 else
160 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
161
162 if (type & IRQ_TYPE_EDGE_FALLING)
163 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
164 else
165 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
166
167 return 0;
168}
169
170static void stmpe_gpio_irq_lock(struct irq_data *d)
171{
172 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
173 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
174
175 mutex_lock(&stmpe_gpio->irq_lock);
176}
177
178static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
179{
180 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
181 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
182 struct stmpe *stmpe = stmpe_gpio->stmpe;
183 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
184 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
185 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
186 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
187 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
188 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
189 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
190 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
191 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
192 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
193 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
194 };
195 int i, j;
196
197 /*
198 * STMPE1600: to be able to get IRQ from pins,
199 * a read must be done on GPMR register, or a write in
200 * GPSR or GPCR registers
201 */
202 if (stmpe->partnum == STMPE1600) {
203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
204 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
205 }
206
207 for (i = 0; i < CACHE_NR_REGS; i++) {
208 /* STMPE801 and STMPE1600 don't have RE and FE registers */
209 if ((stmpe->partnum == STMPE801 ||
210 stmpe->partnum == STMPE1600) &&
211 (i != REG_IE))
212 continue;
213
214 for (j = 0; j < num_banks; j++) {
215 u8 old = stmpe_gpio->oldregs[i][j];
216 u8 new = stmpe_gpio->regs[i][j];
217
218 if (new == old)
219 continue;
220
221 stmpe_gpio->oldregs[i][j] = new;
222 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
223 }
224 }
225
226 mutex_unlock(&stmpe_gpio->irq_lock);
227}
228
229static void stmpe_gpio_irq_mask(struct irq_data *d)
230{
231 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
232 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
233 int offset = d->hwirq;
234 int regoffset = offset / 8;
235 int mask = BIT(offset % 8);
236
237 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
238 gpiochip_disable_irq(gc, offset);
239}
240
241static void stmpe_gpio_irq_unmask(struct irq_data *d)
242{
243 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
244 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
245 int offset = d->hwirq;
246 int regoffset = offset / 8;
247 int mask = BIT(offset % 8);
248
249 gpiochip_enable_irq(gc, offset);
250 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
251}
252
253static void stmpe_dbg_show_one(struct seq_file *s,
254 struct gpio_chip *gc,
255 unsigned offset, unsigned gpio)
256{
257 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
258 struct stmpe *stmpe = stmpe_gpio->stmpe;
259 bool val = !!stmpe_gpio_get(gc, offset);
260 u8 bank = offset / 8;
261 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
262 u8 mask = BIT(offset % 8);
263 int ret;
264 u8 dir;
265
266 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
267 if (IS_ERR(label))
268 return;
269
270 ret = stmpe_reg_read(stmpe, dir_reg);
271 if (ret < 0)
272 return;
273 dir = !!(ret & mask);
274
275 if (dir) {
276 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
277 gpio, label ?: "(none)",
278 val ? "hi" : "lo");
279 } else {
280 u8 edge_det_reg;
281 u8 rise_reg;
282 u8 fall_reg;
283 u8 irqen_reg;
284
285 static const char * const edge_det_values[] = {
286 "edge-inactive",
287 "edge-asserted",
288 "not-supported"
289 };
290 static const char * const rise_values[] = {
291 "no-rising-edge-detection",
292 "rising-edge-detection",
293 "not-supported"
294 };
295 static const char * const fall_values[] = {
296 "no-falling-edge-detection",
297 "falling-edge-detection",
298 "not-supported"
299 };
300 #define NOT_SUPPORTED_IDX 2
301 u8 edge_det = NOT_SUPPORTED_IDX;
302 u8 rise = NOT_SUPPORTED_IDX;
303 u8 fall = NOT_SUPPORTED_IDX;
304 bool irqen;
305
306 switch (stmpe->partnum) {
307 case STMPE610:
308 case STMPE811:
309 case STMPE1601:
310 case STMPE2401:
311 case STMPE2403:
312 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
313 ret = stmpe_reg_read(stmpe, edge_det_reg);
314 if (ret < 0)
315 return;
316 edge_det = !!(ret & mask);
317 fallthrough;
318 case STMPE1801:
319 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
320 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
321
322 ret = stmpe_reg_read(stmpe, rise_reg);
323 if (ret < 0)
324 return;
325 rise = !!(ret & mask);
326 ret = stmpe_reg_read(stmpe, fall_reg);
327 if (ret < 0)
328 return;
329 fall = !!(ret & mask);
330 fallthrough;
331 case STMPE801:
332 case STMPE1600:
333 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
334 break;
335
336 default:
337 return;
338 }
339
340 ret = stmpe_reg_read(stmpe, irqen_reg);
341 if (ret < 0)
342 return;
343 irqen = !!(ret & mask);
344
345 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
346 gpio, label ?: "(none)",
347 val ? "hi" : "lo",
348 edge_det_values[edge_det],
349 irqen ? "IRQ-enabled" : "IRQ-disabled",
350 rise_values[rise],
351 fall_values[fall]);
352 }
353}
354
355static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
356{
357 unsigned i;
358 unsigned gpio = gc->base;
359
360 for (i = 0; i < gc->ngpio; i++, gpio++) {
361 stmpe_dbg_show_one(s, gc, i, gpio);
362 seq_putc(s, '\n');
363 }
364}
365
366static const struct irq_chip stmpe_gpio_irq_chip = {
367 .name = "stmpe-gpio",
368 .irq_bus_lock = stmpe_gpio_irq_lock,
369 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
370 .irq_mask = stmpe_gpio_irq_mask,
371 .irq_unmask = stmpe_gpio_irq_unmask,
372 .irq_set_type = stmpe_gpio_irq_set_type,
373 .flags = IRQCHIP_IMMUTABLE,
374 GPIOCHIP_IRQ_RESOURCE_HELPERS,
375};
376
377#define MAX_GPIOS 24
378
379static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
380{
381 struct stmpe_gpio *stmpe_gpio = dev;
382 struct stmpe *stmpe = stmpe_gpio->stmpe;
383 u8 statmsbreg;
384 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
385 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
386 int ret;
387 int i;
388
389 /*
390 * the stmpe_block_read() call below, imposes to set statmsbreg
391 * with the register located at the lowest address. As STMPE1600
392 * variant is the only one which respect registers address's order
393 * (LSB regs located at lowest address than MSB ones) whereas all
394 * the others have a registers layout with MSB located before the
395 * LSB regs.
396 */
397 if (stmpe->partnum == STMPE1600)
398 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
399 else
400 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
401
402 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
403 if (ret < 0)
404 return IRQ_NONE;
405
406 for (i = 0; i < num_banks; i++) {
407 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
408 num_banks - i - 1;
409 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
410 unsigned int stat = status[i];
411
412 stat &= enabled;
413 if (!stat)
414 continue;
415
416 while (stat) {
417 int bit = __ffs(stat);
418 int line = bank * 8 + bit;
419 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
420 line);
421
422 handle_nested_irq(child_irq);
423 stat &= ~BIT(bit);
424 }
425
426 /*
427 * interrupt status register write has no effect on
428 * 801/1801/1600, bits are cleared when read.
429 * Edge detect register is not present on 801/1600/1801
430 */
431 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
432 stmpe->partnum != STMPE1801) {
433 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
434 stmpe_reg_write(stmpe,
435 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
436 status[i]);
437 }
438 }
439
440 return IRQ_HANDLED;
441}
442
443static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
444 unsigned long *valid_mask,
445 unsigned int ngpios)
446{
447 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
448 int i;
449
450 if (!stmpe_gpio->norequest_mask)
451 return;
452
453 /* Forbid unused lines to be mapped as IRQs */
454 for (i = 0; i < sizeof(u32); i++) {
455 if (stmpe_gpio->norequest_mask & BIT(i))
456 clear_bit(i, valid_mask);
457 }
458}
459
460static void stmpe_gpio_disable(void *stmpe)
461{
462 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
463}
464
465static int stmpe_gpio_probe(struct platform_device *pdev)
466{
467 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
468 struct device_node *np = pdev->dev.of_node;
469 struct stmpe_gpio *stmpe_gpio;
470 int ret, irq;
471
472 if (stmpe->num_gpios > MAX_GPIOS) {
473 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
474 return -EINVAL;
475 }
476
477 stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
478 if (!stmpe_gpio)
479 return -ENOMEM;
480
481 mutex_init(&stmpe_gpio->irq_lock);
482
483 stmpe_gpio->dev = &pdev->dev;
484 stmpe_gpio->stmpe = stmpe;
485 stmpe_gpio->chip = template_chip;
486 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
487 stmpe_gpio->chip.parent = &pdev->dev;
488 stmpe_gpio->chip.base = -1;
489
490 if (IS_ENABLED(CONFIG_DEBUG_FS))
491 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
492
493 of_property_read_u32(np, "st,norequest-mask",
494 &stmpe_gpio->norequest_mask);
495
496 irq = platform_get_irq(pdev, 0);
497 if (irq < 0)
498 dev_info(&pdev->dev,
499 "device configured in no-irq mode: "
500 "irqs are not available\n");
501
502 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
503 if (ret)
504 return ret;
505
506 ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
507 if (ret)
508 return ret;
509
510 if (irq > 0) {
511 struct gpio_irq_chip *girq;
512
513 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
514 stmpe_gpio_irq, IRQF_ONESHOT,
515 "stmpe-gpio", stmpe_gpio);
516 if (ret) {
517 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
518 return ret;
519 }
520
521 girq = &stmpe_gpio->chip.irq;
522 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
523 /* This will let us handle the parent IRQ in the driver */
524 girq->parent_handler = NULL;
525 girq->num_parents = 0;
526 girq->parents = NULL;
527 girq->default_type = IRQ_TYPE_NONE;
528 girq->handler = handle_simple_irq;
529 girq->threaded = true;
530 girq->init_valid_mask = stmpe_init_irq_valid_mask;
531 }
532
533 return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
534}
535
536static struct platform_driver stmpe_gpio_driver = {
537 .driver = {
538 .suppress_bind_attrs = true,
539 .name = "stmpe-gpio",
540 },
541 .probe = stmpe_gpio_probe,
542};
543
544static int __init stmpe_gpio_init(void)
545{
546 return platform_driver_register(&stmpe_gpio_driver);
547}
548subsys_initcall(stmpe_gpio_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/slab.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/of.h>
14#include <linux/mfd/stmpe.h>
15#include <linux/seq_file.h>
16#include <linux/bitops.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
24enum { LSB, CSB, MSB };
25
26#define CACHE_NR_REGS 3
27/* No variant has more than 24 GPIOs */
28#define CACHE_NR_BANKS (24 / 8)
29
30struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72}
73
74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 if (ret & mask)
88 return GPIO_LINE_DIRECTION_OUT;
89
90 return GPIO_LINE_DIRECTION_IN;
91}
92
93static int stmpe_gpio_direction_output(struct gpio_chip *chip,
94 unsigned offset, int val)
95{
96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
97 struct stmpe *stmpe = stmpe_gpio->stmpe;
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
99 u8 mask = BIT(offset % 8);
100
101 stmpe_gpio_set(chip, offset, val);
102
103 return stmpe_set_bits(stmpe, reg, mask, mask);
104}
105
106static int stmpe_gpio_direction_input(struct gpio_chip *chip,
107 unsigned offset)
108{
109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
110 struct stmpe *stmpe = stmpe_gpio->stmpe;
111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
112 u8 mask = BIT(offset % 8);
113
114 return stmpe_set_bits(stmpe, reg, mask, 0);
115}
116
117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
118{
119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
120 struct stmpe *stmpe = stmpe_gpio->stmpe;
121
122 if (stmpe_gpio->norequest_mask & BIT(offset))
123 return -EINVAL;
124
125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
126}
127
128static const struct gpio_chip template_chip = {
129 .label = "stmpe",
130 .owner = THIS_MODULE,
131 .get_direction = stmpe_gpio_get_direction,
132 .direction_input = stmpe_gpio_direction_input,
133 .get = stmpe_gpio_get,
134 .direction_output = stmpe_gpio_direction_output,
135 .set = stmpe_gpio_set,
136 .request = stmpe_gpio_request,
137 .can_sleep = true,
138};
139
140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
141{
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
144 int offset = d->hwirq;
145 int regoffset = offset / 8;
146 int mask = BIT(offset % 8);
147
148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
149 return -EINVAL;
150
151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
152 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
153 stmpe_gpio->stmpe->partnum == STMPE1600)
154 return 0;
155
156 if (type & IRQ_TYPE_EDGE_RISING)
157 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
158 else
159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
160
161 if (type & IRQ_TYPE_EDGE_FALLING)
162 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
163 else
164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
165
166 return 0;
167}
168
169static void stmpe_gpio_irq_lock(struct irq_data *d)
170{
171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
173
174 mutex_lock(&stmpe_gpio->irq_lock);
175}
176
177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
178{
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
181 struct stmpe *stmpe = stmpe_gpio->stmpe;
182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
193 };
194 int i, j;
195
196 /*
197 * STMPE1600: to be able to get IRQ from pins,
198 * a read must be done on GPMR register, or a write in
199 * GPSR or GPCR registers
200 */
201 if (stmpe->partnum == STMPE1600) {
202 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
204 }
205
206 for (i = 0; i < CACHE_NR_REGS; i++) {
207 /* STMPE801 and STMPE1600 don't have RE and FE registers */
208 if ((stmpe->partnum == STMPE801 ||
209 stmpe->partnum == STMPE1600) &&
210 (i != REG_IE))
211 continue;
212
213 for (j = 0; j < num_banks; j++) {
214 u8 old = stmpe_gpio->oldregs[i][j];
215 u8 new = stmpe_gpio->regs[i][j];
216
217 if (new == old)
218 continue;
219
220 stmpe_gpio->oldregs[i][j] = new;
221 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
222 }
223 }
224
225 mutex_unlock(&stmpe_gpio->irq_lock);
226}
227
228static void stmpe_gpio_irq_mask(struct irq_data *d)
229{
230 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
231 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
232 int offset = d->hwirq;
233 int regoffset = offset / 8;
234 int mask = BIT(offset % 8);
235
236 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
237}
238
239static void stmpe_gpio_irq_unmask(struct irq_data *d)
240{
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
243 int offset = d->hwirq;
244 int regoffset = offset / 8;
245 int mask = BIT(offset % 8);
246
247 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
248}
249
250static void stmpe_dbg_show_one(struct seq_file *s,
251 struct gpio_chip *gc,
252 unsigned offset, unsigned gpio)
253{
254 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
255 struct stmpe *stmpe = stmpe_gpio->stmpe;
256 const char *label = gpiochip_is_requested(gc, offset);
257 bool val = !!stmpe_gpio_get(gc, offset);
258 u8 bank = offset / 8;
259 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
260 u8 mask = BIT(offset % 8);
261 int ret;
262 u8 dir;
263
264 ret = stmpe_reg_read(stmpe, dir_reg);
265 if (ret < 0)
266 return;
267 dir = !!(ret & mask);
268
269 if (dir) {
270 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
271 gpio, label ?: "(none)",
272 val ? "hi" : "lo");
273 } else {
274 u8 edge_det_reg;
275 u8 rise_reg;
276 u8 fall_reg;
277 u8 irqen_reg;
278
279 static const char * const edge_det_values[] = {
280 "edge-inactive",
281 "edge-asserted",
282 "not-supported"
283 };
284 static const char * const rise_values[] = {
285 "no-rising-edge-detection",
286 "rising-edge-detection",
287 "not-supported"
288 };
289 static const char * const fall_values[] = {
290 "no-falling-edge-detection",
291 "falling-edge-detection",
292 "not-supported"
293 };
294 #define NOT_SUPPORTED_IDX 2
295 u8 edge_det = NOT_SUPPORTED_IDX;
296 u8 rise = NOT_SUPPORTED_IDX;
297 u8 fall = NOT_SUPPORTED_IDX;
298 bool irqen;
299
300 switch (stmpe->partnum) {
301 case STMPE610:
302 case STMPE811:
303 case STMPE1601:
304 case STMPE2401:
305 case STMPE2403:
306 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
307 ret = stmpe_reg_read(stmpe, edge_det_reg);
308 if (ret < 0)
309 return;
310 edge_det = !!(ret & mask);
311 fallthrough;
312 case STMPE1801:
313 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
314 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
315
316 ret = stmpe_reg_read(stmpe, rise_reg);
317 if (ret < 0)
318 return;
319 rise = !!(ret & mask);
320 ret = stmpe_reg_read(stmpe, fall_reg);
321 if (ret < 0)
322 return;
323 fall = !!(ret & mask);
324 fallthrough;
325 case STMPE801:
326 case STMPE1600:
327 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
328 break;
329
330 default:
331 return;
332 }
333
334 ret = stmpe_reg_read(stmpe, irqen_reg);
335 if (ret < 0)
336 return;
337 irqen = !!(ret & mask);
338
339 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
340 gpio, label ?: "(none)",
341 val ? "hi" : "lo",
342 edge_det_values[edge_det],
343 irqen ? "IRQ-enabled" : "IRQ-disabled",
344 rise_values[rise],
345 fall_values[fall]);
346 }
347}
348
349static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
350{
351 unsigned i;
352 unsigned gpio = gc->base;
353
354 for (i = 0; i < gc->ngpio; i++, gpio++) {
355 stmpe_dbg_show_one(s, gc, i, gpio);
356 seq_putc(s, '\n');
357 }
358}
359
360static struct irq_chip stmpe_gpio_irq_chip = {
361 .name = "stmpe-gpio",
362 .irq_bus_lock = stmpe_gpio_irq_lock,
363 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
364 .irq_mask = stmpe_gpio_irq_mask,
365 .irq_unmask = stmpe_gpio_irq_unmask,
366 .irq_set_type = stmpe_gpio_irq_set_type,
367};
368
369#define MAX_GPIOS 24
370
371static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
372{
373 struct stmpe_gpio *stmpe_gpio = dev;
374 struct stmpe *stmpe = stmpe_gpio->stmpe;
375 u8 statmsbreg;
376 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
377 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
378 int ret;
379 int i;
380
381 /*
382 * the stmpe_block_read() call below, imposes to set statmsbreg
383 * with the register located at the lowest address. As STMPE1600
384 * variant is the only one which respect registers address's order
385 * (LSB regs located at lowest address than MSB ones) whereas all
386 * the others have a registers layout with MSB located before the
387 * LSB regs.
388 */
389 if (stmpe->partnum == STMPE1600)
390 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
391 else
392 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
393
394 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
395 if (ret < 0)
396 return IRQ_NONE;
397
398 for (i = 0; i < num_banks; i++) {
399 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
400 num_banks - i - 1;
401 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
402 unsigned int stat = status[i];
403
404 stat &= enabled;
405 if (!stat)
406 continue;
407
408 while (stat) {
409 int bit = __ffs(stat);
410 int line = bank * 8 + bit;
411 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
412 line);
413
414 handle_nested_irq(child_irq);
415 stat &= ~BIT(bit);
416 }
417
418 /*
419 * interrupt status register write has no effect on
420 * 801/1801/1600, bits are cleared when read.
421 * Edge detect register is not present on 801/1600/1801
422 */
423 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
424 stmpe->partnum != STMPE1801) {
425 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
426 stmpe_reg_write(stmpe,
427 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
428 status[i]);
429 }
430 }
431
432 return IRQ_HANDLED;
433}
434
435static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
436 unsigned long *valid_mask,
437 unsigned int ngpios)
438{
439 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
440 int i;
441
442 if (!stmpe_gpio->norequest_mask)
443 return;
444
445 /* Forbid unused lines to be mapped as IRQs */
446 for (i = 0; i < sizeof(u32); i++) {
447 if (stmpe_gpio->norequest_mask & BIT(i))
448 clear_bit(i, valid_mask);
449 }
450}
451
452static int stmpe_gpio_probe(struct platform_device *pdev)
453{
454 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
455 struct device_node *np = pdev->dev.of_node;
456 struct stmpe_gpio *stmpe_gpio;
457 int ret, irq;
458
459 if (stmpe->num_gpios > MAX_GPIOS) {
460 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
461 return -EINVAL;
462 }
463
464 stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
465 if (!stmpe_gpio)
466 return -ENOMEM;
467
468 mutex_init(&stmpe_gpio->irq_lock);
469
470 stmpe_gpio->dev = &pdev->dev;
471 stmpe_gpio->stmpe = stmpe;
472 stmpe_gpio->chip = template_chip;
473 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
474 stmpe_gpio->chip.parent = &pdev->dev;
475 stmpe_gpio->chip.of_node = np;
476 stmpe_gpio->chip.base = -1;
477 /*
478 * REVISIT: this makes sure the valid mask gets allocated and
479 * filled in when adding the gpio_chip, but the rest of the
480 * gpio_irqchip is still filled in using the old method
481 * in gpiochip_irqchip_add_nested() so clean this up once we
482 * get the gpio_irqchip to initialize while adding the
483 * gpio_chip also for threaded irqchips.
484 */
485 stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask;
486
487 if (IS_ENABLED(CONFIG_DEBUG_FS))
488 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
489
490 of_property_read_u32(np, "st,norequest-mask",
491 &stmpe_gpio->norequest_mask);
492
493 irq = platform_get_irq(pdev, 0);
494 if (irq < 0)
495 dev_info(&pdev->dev,
496 "device configured in no-irq mode: "
497 "irqs are not available\n");
498
499 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
500 if (ret)
501 goto out_free;
502
503 if (irq > 0) {
504 struct gpio_irq_chip *girq;
505
506 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
507 stmpe_gpio_irq, IRQF_ONESHOT,
508 "stmpe-gpio", stmpe_gpio);
509 if (ret) {
510 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
511 goto out_disable;
512 }
513
514 girq = &stmpe_gpio->chip.irq;
515 girq->chip = &stmpe_gpio_irq_chip;
516 /* This will let us handle the parent IRQ in the driver */
517 girq->parent_handler = NULL;
518 girq->num_parents = 0;
519 girq->parents = NULL;
520 girq->default_type = IRQ_TYPE_NONE;
521 girq->handler = handle_simple_irq;
522 girq->threaded = true;
523 }
524
525 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
526 if (ret) {
527 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
528 goto out_disable;
529 }
530
531 platform_set_drvdata(pdev, stmpe_gpio);
532
533 return 0;
534
535out_disable:
536 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
537 gpiochip_remove(&stmpe_gpio->chip);
538out_free:
539 kfree(stmpe_gpio);
540 return ret;
541}
542
543static struct platform_driver stmpe_gpio_driver = {
544 .driver = {
545 .suppress_bind_attrs = true,
546 .name = "stmpe-gpio",
547 },
548 .probe = stmpe_gpio_probe,
549};
550
551static int __init stmpe_gpio_init(void)
552{
553 return platform_driver_register(&stmpe_gpio_driver);
554}
555subsys_initcall(stmpe_gpio_init);