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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/dma-mapping.h>
8#include <linux/interconnect.h>
9#include <linux/interrupt.h>
10#include <linux/module.h>
11#include <linux/mod_devicetable.h>
12#include <linux/platform_device.h>
13#include <linux/spinlock.h>
14#include <linux/types.h>
15#include <crypto/algapi.h>
16#include <crypto/internal/hash.h>
17
18#include "core.h"
19#include "cipher.h"
20#include "sha.h"
21#include "aead.h"
22
23#define QCE_MAJOR_VERSION5 0x05
24#define QCE_QUEUE_LENGTH 1
25
26#define QCE_DEFAULT_MEM_BANDWIDTH 393600
27
28static const struct qce_algo_ops *qce_ops[] = {
29#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
30 &skcipher_ops,
31#endif
32#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
33 &ahash_ops,
34#endif
35#ifdef CONFIG_CRYPTO_DEV_QCE_AEAD
36 &aead_ops,
37#endif
38};
39
40static void qce_unregister_algs(struct qce_device *qce)
41{
42 const struct qce_algo_ops *ops;
43 int i;
44
45 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
46 ops = qce_ops[i];
47 ops->unregister_algs(qce);
48 }
49}
50
51static int qce_register_algs(struct qce_device *qce)
52{
53 const struct qce_algo_ops *ops;
54 int i, ret = -ENODEV;
55
56 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
57 ops = qce_ops[i];
58 ret = ops->register_algs(qce);
59 if (ret)
60 break;
61 }
62
63 return ret;
64}
65
66static int qce_handle_request(struct crypto_async_request *async_req)
67{
68 int ret = -EINVAL, i;
69 const struct qce_algo_ops *ops;
70 u32 type = crypto_tfm_alg_type(async_req->tfm);
71
72 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
73 ops = qce_ops[i];
74 if (type != ops->type)
75 continue;
76 ret = ops->async_req_handle(async_req);
77 break;
78 }
79
80 return ret;
81}
82
83static int qce_handle_queue(struct qce_device *qce,
84 struct crypto_async_request *req)
85{
86 struct crypto_async_request *async_req, *backlog;
87 unsigned long flags;
88 int ret = 0, err;
89
90 spin_lock_irqsave(&qce->lock, flags);
91
92 if (req)
93 ret = crypto_enqueue_request(&qce->queue, req);
94
95 /* busy, do not dequeue request */
96 if (qce->req) {
97 spin_unlock_irqrestore(&qce->lock, flags);
98 return ret;
99 }
100
101 backlog = crypto_get_backlog(&qce->queue);
102 async_req = crypto_dequeue_request(&qce->queue);
103 if (async_req)
104 qce->req = async_req;
105
106 spin_unlock_irqrestore(&qce->lock, flags);
107
108 if (!async_req)
109 return ret;
110
111 if (backlog) {
112 spin_lock_bh(&qce->lock);
113 crypto_request_complete(backlog, -EINPROGRESS);
114 spin_unlock_bh(&qce->lock);
115 }
116
117 err = qce_handle_request(async_req);
118 if (err) {
119 qce->result = err;
120 tasklet_schedule(&qce->done_tasklet);
121 }
122
123 return ret;
124}
125
126static void qce_tasklet_req_done(unsigned long data)
127{
128 struct qce_device *qce = (struct qce_device *)data;
129 struct crypto_async_request *req;
130 unsigned long flags;
131
132 spin_lock_irqsave(&qce->lock, flags);
133 req = qce->req;
134 qce->req = NULL;
135 spin_unlock_irqrestore(&qce->lock, flags);
136
137 if (req)
138 crypto_request_complete(req, qce->result);
139
140 qce_handle_queue(qce, NULL);
141}
142
143static int qce_async_request_enqueue(struct qce_device *qce,
144 struct crypto_async_request *req)
145{
146 return qce_handle_queue(qce, req);
147}
148
149static void qce_async_request_done(struct qce_device *qce, int ret)
150{
151 qce->result = ret;
152 tasklet_schedule(&qce->done_tasklet);
153}
154
155static int qce_check_version(struct qce_device *qce)
156{
157 u32 major, minor, step;
158
159 qce_get_version(qce, &major, &minor, &step);
160
161 /*
162 * the driver does not support v5 with minor 0 because it has special
163 * alignment requirements.
164 */
165 if (major != QCE_MAJOR_VERSION5 || minor == 0)
166 return -ENODEV;
167
168 qce->burst_size = QCE_BAM_BURST_SIZE;
169
170 /*
171 * Rx and tx pipes are treated as a pair inside CE.
172 * Pipe pair number depends on the actual BAM dma pipe
173 * that is used for transfers. The BAM dma pipes are passed
174 * from the device tree and used to derive the pipe pair
175 * id in the CE driver as follows.
176 * BAM dma pipes(rx, tx) CE pipe pair id
177 * 0,1 0
178 * 2,3 1
179 * 4,5 2
180 * 6,7 3
181 * ...
182 */
183 qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1;
184
185 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
186 major, minor, step);
187
188 return 0;
189}
190
191static int qce_crypto_probe(struct platform_device *pdev)
192{
193 struct device *dev = &pdev->dev;
194 struct qce_device *qce;
195 int ret;
196
197 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
198 if (!qce)
199 return -ENOMEM;
200
201 qce->dev = dev;
202 platform_set_drvdata(pdev, qce);
203
204 qce->base = devm_platform_ioremap_resource(pdev, 0);
205 if (IS_ERR(qce->base))
206 return PTR_ERR(qce->base);
207
208 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
209 if (ret < 0)
210 return ret;
211
212 qce->core = devm_clk_get_optional(qce->dev, "core");
213 if (IS_ERR(qce->core))
214 return PTR_ERR(qce->core);
215
216 qce->iface = devm_clk_get_optional(qce->dev, "iface");
217 if (IS_ERR(qce->iface))
218 return PTR_ERR(qce->iface);
219
220 qce->bus = devm_clk_get_optional(qce->dev, "bus");
221 if (IS_ERR(qce->bus))
222 return PTR_ERR(qce->bus);
223
224 qce->mem_path = devm_of_icc_get(qce->dev, "memory");
225 if (IS_ERR(qce->mem_path))
226 return PTR_ERR(qce->mem_path);
227
228 ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
229 if (ret)
230 return ret;
231
232 ret = clk_prepare_enable(qce->core);
233 if (ret)
234 goto err_mem_path_disable;
235
236 ret = clk_prepare_enable(qce->iface);
237 if (ret)
238 goto err_clks_core;
239
240 ret = clk_prepare_enable(qce->bus);
241 if (ret)
242 goto err_clks_iface;
243
244 ret = qce_dma_request(qce->dev, &qce->dma);
245 if (ret)
246 goto err_clks;
247
248 ret = qce_check_version(qce);
249 if (ret)
250 goto err_clks;
251
252 spin_lock_init(&qce->lock);
253 tasklet_init(&qce->done_tasklet, qce_tasklet_req_done,
254 (unsigned long)qce);
255 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH);
256
257 qce->async_req_enqueue = qce_async_request_enqueue;
258 qce->async_req_done = qce_async_request_done;
259
260 ret = qce_register_algs(qce);
261 if (ret)
262 goto err_dma;
263
264 return 0;
265
266err_dma:
267 qce_dma_release(&qce->dma);
268err_clks:
269 clk_disable_unprepare(qce->bus);
270err_clks_iface:
271 clk_disable_unprepare(qce->iface);
272err_clks_core:
273 clk_disable_unprepare(qce->core);
274err_mem_path_disable:
275 icc_set_bw(qce->mem_path, 0, 0);
276
277 return ret;
278}
279
280static void qce_crypto_remove(struct platform_device *pdev)
281{
282 struct qce_device *qce = platform_get_drvdata(pdev);
283
284 tasklet_kill(&qce->done_tasklet);
285 qce_unregister_algs(qce);
286 qce_dma_release(&qce->dma);
287 clk_disable_unprepare(qce->bus);
288 clk_disable_unprepare(qce->iface);
289 clk_disable_unprepare(qce->core);
290}
291
292static const struct of_device_id qce_crypto_of_match[] = {
293 { .compatible = "qcom,crypto-v5.1", },
294 { .compatible = "qcom,crypto-v5.4", },
295 { .compatible = "qcom,qce", },
296 {}
297};
298MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
299
300static struct platform_driver qce_crypto_driver = {
301 .probe = qce_crypto_probe,
302 .remove_new = qce_crypto_remove,
303 .driver = {
304 .name = KBUILD_MODNAME,
305 .of_match_table = qce_crypto_of_match,
306 },
307};
308module_platform_driver(qce_crypto_driver);
309
310MODULE_LICENSE("GPL v2");
311MODULE_DESCRIPTION("Qualcomm crypto engine driver");
312MODULE_ALIAS("platform:" KBUILD_MODNAME);
313MODULE_AUTHOR("The Linux Foundation");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/interrupt.h>
8#include <linux/module.h>
9#include <linux/mod_devicetable.h>
10#include <linux/platform_device.h>
11#include <linux/spinlock.h>
12#include <linux/types.h>
13#include <crypto/algapi.h>
14#include <crypto/internal/hash.h>
15#include <crypto/sha.h>
16
17#include "core.h"
18#include "cipher.h"
19#include "sha.h"
20
21#define QCE_MAJOR_VERSION5 0x05
22#define QCE_QUEUE_LENGTH 1
23
24static const struct qce_algo_ops *qce_ops[] = {
25#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
26 &skcipher_ops,
27#endif
28#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
29 &ahash_ops,
30#endif
31};
32
33static void qce_unregister_algs(struct qce_device *qce)
34{
35 const struct qce_algo_ops *ops;
36 int i;
37
38 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
39 ops = qce_ops[i];
40 ops->unregister_algs(qce);
41 }
42}
43
44static int qce_register_algs(struct qce_device *qce)
45{
46 const struct qce_algo_ops *ops;
47 int i, ret = -ENODEV;
48
49 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
50 ops = qce_ops[i];
51 ret = ops->register_algs(qce);
52 if (ret)
53 break;
54 }
55
56 return ret;
57}
58
59static int qce_handle_request(struct crypto_async_request *async_req)
60{
61 int ret = -EINVAL, i;
62 const struct qce_algo_ops *ops;
63 u32 type = crypto_tfm_alg_type(async_req->tfm);
64
65 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
66 ops = qce_ops[i];
67 if (type != ops->type)
68 continue;
69 ret = ops->async_req_handle(async_req);
70 break;
71 }
72
73 return ret;
74}
75
76static int qce_handle_queue(struct qce_device *qce,
77 struct crypto_async_request *req)
78{
79 struct crypto_async_request *async_req, *backlog;
80 unsigned long flags;
81 int ret = 0, err;
82
83 spin_lock_irqsave(&qce->lock, flags);
84
85 if (req)
86 ret = crypto_enqueue_request(&qce->queue, req);
87
88 /* busy, do not dequeue request */
89 if (qce->req) {
90 spin_unlock_irqrestore(&qce->lock, flags);
91 return ret;
92 }
93
94 backlog = crypto_get_backlog(&qce->queue);
95 async_req = crypto_dequeue_request(&qce->queue);
96 if (async_req)
97 qce->req = async_req;
98
99 spin_unlock_irqrestore(&qce->lock, flags);
100
101 if (!async_req)
102 return ret;
103
104 if (backlog) {
105 spin_lock_bh(&qce->lock);
106 backlog->complete(backlog, -EINPROGRESS);
107 spin_unlock_bh(&qce->lock);
108 }
109
110 err = qce_handle_request(async_req);
111 if (err) {
112 qce->result = err;
113 tasklet_schedule(&qce->done_tasklet);
114 }
115
116 return ret;
117}
118
119static void qce_tasklet_req_done(unsigned long data)
120{
121 struct qce_device *qce = (struct qce_device *)data;
122 struct crypto_async_request *req;
123 unsigned long flags;
124
125 spin_lock_irqsave(&qce->lock, flags);
126 req = qce->req;
127 qce->req = NULL;
128 spin_unlock_irqrestore(&qce->lock, flags);
129
130 if (req)
131 req->complete(req, qce->result);
132
133 qce_handle_queue(qce, NULL);
134}
135
136static int qce_async_request_enqueue(struct qce_device *qce,
137 struct crypto_async_request *req)
138{
139 return qce_handle_queue(qce, req);
140}
141
142static void qce_async_request_done(struct qce_device *qce, int ret)
143{
144 qce->result = ret;
145 tasklet_schedule(&qce->done_tasklet);
146}
147
148static int qce_check_version(struct qce_device *qce)
149{
150 u32 major, minor, step;
151
152 qce_get_version(qce, &major, &minor, &step);
153
154 /*
155 * the driver does not support v5 with minor 0 because it has special
156 * alignment requirements.
157 */
158 if (major != QCE_MAJOR_VERSION5 || minor == 0)
159 return -ENODEV;
160
161 qce->burst_size = QCE_BAM_BURST_SIZE;
162 qce->pipe_pair_id = 1;
163
164 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
165 major, minor, step);
166
167 return 0;
168}
169
170static int qce_crypto_probe(struct platform_device *pdev)
171{
172 struct device *dev = &pdev->dev;
173 struct qce_device *qce;
174 int ret;
175
176 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
177 if (!qce)
178 return -ENOMEM;
179
180 qce->dev = dev;
181 platform_set_drvdata(pdev, qce);
182
183 qce->base = devm_platform_ioremap_resource(pdev, 0);
184 if (IS_ERR(qce->base))
185 return PTR_ERR(qce->base);
186
187 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
188 if (ret < 0)
189 return ret;
190
191 qce->core = devm_clk_get(qce->dev, "core");
192 if (IS_ERR(qce->core))
193 return PTR_ERR(qce->core);
194
195 qce->iface = devm_clk_get(qce->dev, "iface");
196 if (IS_ERR(qce->iface))
197 return PTR_ERR(qce->iface);
198
199 qce->bus = devm_clk_get(qce->dev, "bus");
200 if (IS_ERR(qce->bus))
201 return PTR_ERR(qce->bus);
202
203 ret = clk_prepare_enable(qce->core);
204 if (ret)
205 return ret;
206
207 ret = clk_prepare_enable(qce->iface);
208 if (ret)
209 goto err_clks_core;
210
211 ret = clk_prepare_enable(qce->bus);
212 if (ret)
213 goto err_clks_iface;
214
215 ret = qce_dma_request(qce->dev, &qce->dma);
216 if (ret)
217 goto err_clks;
218
219 ret = qce_check_version(qce);
220 if (ret)
221 goto err_clks;
222
223 spin_lock_init(&qce->lock);
224 tasklet_init(&qce->done_tasklet, qce_tasklet_req_done,
225 (unsigned long)qce);
226 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH);
227
228 qce->async_req_enqueue = qce_async_request_enqueue;
229 qce->async_req_done = qce_async_request_done;
230
231 ret = qce_register_algs(qce);
232 if (ret)
233 goto err_dma;
234
235 return 0;
236
237err_dma:
238 qce_dma_release(&qce->dma);
239err_clks:
240 clk_disable_unprepare(qce->bus);
241err_clks_iface:
242 clk_disable_unprepare(qce->iface);
243err_clks_core:
244 clk_disable_unprepare(qce->core);
245 return ret;
246}
247
248static int qce_crypto_remove(struct platform_device *pdev)
249{
250 struct qce_device *qce = platform_get_drvdata(pdev);
251
252 tasklet_kill(&qce->done_tasklet);
253 qce_unregister_algs(qce);
254 qce_dma_release(&qce->dma);
255 clk_disable_unprepare(qce->bus);
256 clk_disable_unprepare(qce->iface);
257 clk_disable_unprepare(qce->core);
258 return 0;
259}
260
261static const struct of_device_id qce_crypto_of_match[] = {
262 { .compatible = "qcom,crypto-v5.1", },
263 {}
264};
265MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
266
267static struct platform_driver qce_crypto_driver = {
268 .probe = qce_crypto_probe,
269 .remove = qce_crypto_remove,
270 .driver = {
271 .name = KBUILD_MODNAME,
272 .of_match_table = qce_crypto_of_match,
273 },
274};
275module_platform_driver(qce_crypto_driver);
276
277MODULE_LICENSE("GPL v2");
278MODULE_DESCRIPTION("Qualcomm crypto engine driver");
279MODULE_ALIAS("platform:" KBUILD_MODNAME);
280MODULE_AUTHOR("The Linux Foundation");