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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Marvell Orion SoC timer handling.
4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * Timer 0 is used as free-running clocksource, while timer 1 is
8 * used as clock_event_device.
9 */
10
11#include <linux/kernel.h>
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/clockchips.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/spinlock.h>
20#include <linux/sched_clock.h>
21
22#define TIMER_CTRL 0x00
23#define TIMER0_EN BIT(0)
24#define TIMER0_RELOAD_EN BIT(1)
25#define TIMER1_EN BIT(2)
26#define TIMER1_RELOAD_EN BIT(3)
27#define TIMER0_RELOAD 0x10
28#define TIMER0_VAL 0x14
29#define TIMER1_RELOAD 0x18
30#define TIMER1_VAL 0x1c
31
32#define ORION_ONESHOT_MIN 1
33#define ORION_ONESHOT_MAX 0xfffffffe
34
35static void __iomem *timer_base;
36
37static unsigned long notrace orion_read_timer(void)
38{
39 return ~readl(timer_base + TIMER0_VAL);
40}
41
42static struct delay_timer orion_delay_timer = {
43 .read_current_timer = orion_read_timer,
44};
45
46static void orion_delay_timer_init(unsigned long rate)
47{
48 orion_delay_timer.freq = rate;
49 register_current_timer_delay(&orion_delay_timer);
50}
51
52/*
53 * Free-running clocksource handling.
54 */
55static u64 notrace orion_read_sched_clock(void)
56{
57 return ~readl(timer_base + TIMER0_VAL);
58}
59
60/*
61 * Clockevent handling.
62 */
63static u32 ticks_per_jiffy;
64
65static int orion_clkevt_next_event(unsigned long delta,
66 struct clock_event_device *dev)
67{
68 /* setup and enable one-shot timer */
69 writel(delta, timer_base + TIMER1_VAL);
70 atomic_io_modify(timer_base + TIMER_CTRL,
71 TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN);
72
73 return 0;
74}
75
76static int orion_clkevt_shutdown(struct clock_event_device *dev)
77{
78 /* disable timer */
79 atomic_io_modify(timer_base + TIMER_CTRL,
80 TIMER1_RELOAD_EN | TIMER1_EN, 0);
81 return 0;
82}
83
84static int orion_clkevt_set_periodic(struct clock_event_device *dev)
85{
86 /* setup and enable periodic timer at 1/HZ intervals */
87 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
88 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
89 atomic_io_modify(timer_base + TIMER_CTRL,
90 TIMER1_RELOAD_EN | TIMER1_EN,
91 TIMER1_RELOAD_EN | TIMER1_EN);
92 return 0;
93}
94
95static struct clock_event_device orion_clkevt = {
96 .name = "orion_event",
97 .features = CLOCK_EVT_FEAT_ONESHOT |
98 CLOCK_EVT_FEAT_PERIODIC,
99 .shift = 32,
100 .rating = 300,
101 .set_next_event = orion_clkevt_next_event,
102 .set_state_shutdown = orion_clkevt_shutdown,
103 .set_state_periodic = orion_clkevt_set_periodic,
104 .set_state_oneshot = orion_clkevt_shutdown,
105 .tick_resume = orion_clkevt_shutdown,
106};
107
108static irqreturn_t orion_clkevt_irq_handler(int irq, void *dev_id)
109{
110 orion_clkevt.event_handler(&orion_clkevt);
111 return IRQ_HANDLED;
112}
113
114static int __init orion_timer_init(struct device_node *np)
115{
116 unsigned long rate;
117 struct clk *clk;
118 int irq, ret;
119
120 /* timer registers are shared with watchdog timer */
121 timer_base = of_iomap(np, 0);
122 if (!timer_base) {
123 pr_err("%pOFn: unable to map resource\n", np);
124 return -ENXIO;
125 }
126
127 clk = of_clk_get(np, 0);
128 if (IS_ERR(clk)) {
129 pr_err("%pOFn: unable to get clk\n", np);
130 return PTR_ERR(clk);
131 }
132
133 ret = clk_prepare_enable(clk);
134 if (ret) {
135 pr_err("Failed to prepare clock\n");
136 return ret;
137 }
138
139 /* we are only interested in timer1 irq */
140 irq = irq_of_parse_and_map(np, 1);
141 if (irq <= 0) {
142 pr_err("%pOFn: unable to parse timer1 irq\n", np);
143 ret = -EINVAL;
144 goto out_unprep_clk;
145 }
146
147 rate = clk_get_rate(clk);
148
149 /* setup timer0 as free-running clocksource */
150 writel(~0, timer_base + TIMER0_VAL);
151 writel(~0, timer_base + TIMER0_RELOAD);
152 atomic_io_modify(timer_base + TIMER_CTRL,
153 TIMER0_RELOAD_EN | TIMER0_EN,
154 TIMER0_RELOAD_EN | TIMER0_EN);
155
156 ret = clocksource_mmio_init(timer_base + TIMER0_VAL,
157 "orion_clocksource", rate, 300, 32,
158 clocksource_mmio_readl_down);
159 if (ret) {
160 pr_err("Failed to initialize mmio timer\n");
161 goto out_unprep_clk;
162 }
163
164 sched_clock_register(orion_read_sched_clock, 32, rate);
165
166 /* setup timer1 as clockevent timer */
167 ret = request_irq(irq, orion_clkevt_irq_handler, IRQF_TIMER,
168 "orion_event", NULL);
169 if (ret) {
170 pr_err("%pOFn: unable to setup irq\n", np);
171 goto out_unprep_clk;
172 }
173
174 ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ;
175 orion_clkevt.cpumask = cpumask_of(0);
176 orion_clkevt.irq = irq;
177 clockevents_config_and_register(&orion_clkevt, rate,
178 ORION_ONESHOT_MIN, ORION_ONESHOT_MAX);
179
180
181 orion_delay_timer_init(rate);
182
183 return 0;
184
185out_unprep_clk:
186 clk_disable_unprepare(clk);
187 return ret;
188}
189TIMER_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);
1/*
2 * Marvell Orion SoC timer handling.
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * Timer 0 is used as free-running clocksource, while timer 1 is
11 * used as clock_event_device.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/spinlock.h>
23#include <linux/sched_clock.h>
24
25#define TIMER_CTRL 0x00
26#define TIMER0_EN BIT(0)
27#define TIMER0_RELOAD_EN BIT(1)
28#define TIMER1_EN BIT(2)
29#define TIMER1_RELOAD_EN BIT(3)
30#define TIMER0_RELOAD 0x10
31#define TIMER0_VAL 0x14
32#define TIMER1_RELOAD 0x18
33#define TIMER1_VAL 0x1c
34
35#define ORION_ONESHOT_MIN 1
36#define ORION_ONESHOT_MAX 0xfffffffe
37
38static void __iomem *timer_base;
39
40static unsigned long notrace orion_read_timer(void)
41{
42 return ~readl(timer_base + TIMER0_VAL);
43}
44
45static struct delay_timer orion_delay_timer = {
46 .read_current_timer = orion_read_timer,
47};
48
49static void orion_delay_timer_init(unsigned long rate)
50{
51 orion_delay_timer.freq = rate;
52 register_current_timer_delay(&orion_delay_timer);
53}
54
55/*
56 * Free-running clocksource handling.
57 */
58static u64 notrace orion_read_sched_clock(void)
59{
60 return ~readl(timer_base + TIMER0_VAL);
61}
62
63/*
64 * Clockevent handling.
65 */
66static u32 ticks_per_jiffy;
67
68static int orion_clkevt_next_event(unsigned long delta,
69 struct clock_event_device *dev)
70{
71 /* setup and enable one-shot timer */
72 writel(delta, timer_base + TIMER1_VAL);
73 atomic_io_modify(timer_base + TIMER_CTRL,
74 TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN);
75
76 return 0;
77}
78
79static int orion_clkevt_shutdown(struct clock_event_device *dev)
80{
81 /* disable timer */
82 atomic_io_modify(timer_base + TIMER_CTRL,
83 TIMER1_RELOAD_EN | TIMER1_EN, 0);
84 return 0;
85}
86
87static int orion_clkevt_set_periodic(struct clock_event_device *dev)
88{
89 /* setup and enable periodic timer at 1/HZ intervals */
90 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
91 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
92 atomic_io_modify(timer_base + TIMER_CTRL,
93 TIMER1_RELOAD_EN | TIMER1_EN,
94 TIMER1_RELOAD_EN | TIMER1_EN);
95 return 0;
96}
97
98static struct clock_event_device orion_clkevt = {
99 .name = "orion_event",
100 .features = CLOCK_EVT_FEAT_ONESHOT |
101 CLOCK_EVT_FEAT_PERIODIC,
102 .shift = 32,
103 .rating = 300,
104 .set_next_event = orion_clkevt_next_event,
105 .set_state_shutdown = orion_clkevt_shutdown,
106 .set_state_periodic = orion_clkevt_set_periodic,
107 .set_state_oneshot = orion_clkevt_shutdown,
108 .tick_resume = orion_clkevt_shutdown,
109};
110
111static irqreturn_t orion_clkevt_irq_handler(int irq, void *dev_id)
112{
113 orion_clkevt.event_handler(&orion_clkevt);
114 return IRQ_HANDLED;
115}
116
117static int __init orion_timer_init(struct device_node *np)
118{
119 unsigned long rate;
120 struct clk *clk;
121 int irq, ret;
122
123 /* timer registers are shared with watchdog timer */
124 timer_base = of_iomap(np, 0);
125 if (!timer_base) {
126 pr_err("%pOFn: unable to map resource\n", np);
127 return -ENXIO;
128 }
129
130 clk = of_clk_get(np, 0);
131 if (IS_ERR(clk)) {
132 pr_err("%pOFn: unable to get clk\n", np);
133 return PTR_ERR(clk);
134 }
135
136 ret = clk_prepare_enable(clk);
137 if (ret) {
138 pr_err("Failed to prepare clock\n");
139 return ret;
140 }
141
142 /* we are only interested in timer1 irq */
143 irq = irq_of_parse_and_map(np, 1);
144 if (irq <= 0) {
145 pr_err("%pOFn: unable to parse timer1 irq\n", np);
146 return -EINVAL;
147 }
148
149 rate = clk_get_rate(clk);
150
151 /* setup timer0 as free-running clocksource */
152 writel(~0, timer_base + TIMER0_VAL);
153 writel(~0, timer_base + TIMER0_RELOAD);
154 atomic_io_modify(timer_base + TIMER_CTRL,
155 TIMER0_RELOAD_EN | TIMER0_EN,
156 TIMER0_RELOAD_EN | TIMER0_EN);
157
158 ret = clocksource_mmio_init(timer_base + TIMER0_VAL,
159 "orion_clocksource", rate, 300, 32,
160 clocksource_mmio_readl_down);
161 if (ret) {
162 pr_err("Failed to initialize mmio timer\n");
163 return ret;
164 }
165
166 sched_clock_register(orion_read_sched_clock, 32, rate);
167
168 /* setup timer1 as clockevent timer */
169 ret = request_irq(irq, orion_clkevt_irq_handler, IRQF_TIMER,
170 "orion_event", NULL);
171 if (ret) {
172 pr_err("%pOFn: unable to setup irq\n", np);
173 return ret;
174 }
175
176 ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ;
177 orion_clkevt.cpumask = cpumask_of(0);
178 orion_clkevt.irq = irq;
179 clockevents_config_and_register(&orion_clkevt, rate,
180 ORION_ONESHOT_MIN, ORION_ONESHOT_MAX);
181
182
183 orion_delay_timer_init(rate);
184
185 return 0;
186}
187TIMER_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);