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1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
41};
42
43/* controller at 0x9000 */
44&pci0 {
45 compatible = "fsl,mpc8548-pcie";
46 device_type = "pci";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
51 interrupts = <16 2 0 0>;
52
53 pcie@0 {
54 reg = <0 0 0 0 0>;
55 #interrupt-cells = <1>;
56 #size-cells = <2>;
57 #address-cells = <3>;
58 device_type = "pci";
59 interrupts = <16 2 0 0>;
60 interrupt-map-mask = <0xf800 0 0 7>;
61 interrupt-map = <
62 /* IDSEL 0x0 */
63 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
64 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
65 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
66 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
67 >;
68 };
69};
70
71/* controller at 0xa000 */
72&pci1 {
73 compatible = "fsl,mpc8548-pcie";
74 device_type = "pci";
75 #size-cells = <2>;
76 #address-cells = <3>;
77 bus-range = <0 255>;
78 clock-frequency = <33333333>;
79 interrupts = <16 2 0 0>;
80
81 pcie@0 {
82 reg = <0 0 0 0 0>;
83 #interrupt-cells = <1>;
84 #size-cells = <2>;
85 #address-cells = <3>;
86 device_type = "pci";
87 interrupts = <16 2 0 0>;
88 interrupt-map-mask = <0xf800 0 0 7>;
89
90 interrupt-map = <
91 /* IDSEL 0x0 */
92 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
93 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
94 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
95 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
96 >;
97 };
98};
99
100&soc {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 device_type = "soc";
104 compatible = "fsl,p1021-immr", "simple-bus";
105 bus-frequency = <0>; // Filled out by uboot.
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <12>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,p1021-ecm", "fsl,ecm";
115 reg = <0x1000 0x1000>;
116 interrupts = <16 2 0 0>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,p1021-memory-controller";
121 reg = <0x2000 0x1000>;
122 interrupts = <16 2 0 0>;
123 };
124
125/include/ "pq3-i2c-0.dtsi"
126/include/ "pq3-i2c-1.dtsi"
127/include/ "pq3-duart-0.dtsi"
128
129/include/ "pq3-espi-0.dtsi"
130 spi@7000 {
131 fsl,espi-num-chipselects = <4>;
132 };
133
134/include/ "pq3-gpio-0.dtsi"
135
136 L2: l2-cache-controller@20000 {
137 compatible = "fsl,p1021-l2-cache-controller";
138 reg = <0x20000 0x1000>;
139 cache-line-size = <32>; // 32 bytes
140 cache-size = <0x40000>; // L2,256K
141 interrupts = <16 2 0 0>;
142 };
143
144/include/ "pq3-dma-0.dtsi"
145/include/ "pq3-usb2-dr-0.dtsi"
146 usb@22000 {
147 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
148 };
149
150/include/ "pq3-esdhc-0.dtsi"
151 sdhc@2e000 {
152 sdhci,auto-cmd12;
153 };
154
155/include/ "pq3-sec3.3-0.dtsi"
156
157/include/ "pq3-mpic.dtsi"
158/include/ "pq3-mpic-timer-B.dtsi"
159
160/include/ "pq3-etsec2-0.dtsi"
161 enet0: enet0_grp2: ethernet@b0000 {
162 };
163
164/include/ "pq3-etsec2-1.dtsi"
165 enet1: enet1_grp2: ethernet@b1000 {
166 };
167
168/include/ "pq3-etsec2-2.dtsi"
169 enet2: enet2_grp2: ethernet@b2000 {
170 };
171
172 global-utilities@e0000 {
173 compatible = "fsl,p1021-guts";
174 reg = <0xe0000 0x1000>;
175 fsl,has-rstcr;
176 };
177};
178
179&qe {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "qe";
183 compatible = "fsl,qe";
184 fsl,qe-num-riscs = <1>;
185 fsl,qe-num-snums = <28>;
186
187 qeic: interrupt-controller@80 {
188 interrupt-controller;
189 compatible = "fsl,qe-ic";
190 #address-cells = <0>;
191 #interrupt-cells = <1>;
192 reg = <0x80 0x80>;
193 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
194 };
195
196 ucc@2000 {
197 cell-index = <1>;
198 reg = <0x2000 0x200>;
199 interrupts = <32>;
200 interrupt-parent = <&qeic>;
201 };
202
203 mdio@2120 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 reg = <0x2120 0x18>;
207 compatible = "fsl,ucc-mdio";
208 };
209
210 ucc@2400 {
211 cell-index = <5>;
212 reg = <0x2400 0x200>;
213 interrupts = <40>;
214 interrupt-parent = <&qeic>;
215 };
216
217 ucc@2600 {
218 cell-index = <7>;
219 reg = <0x2600 0x200>;
220 interrupts = <42>;
221 interrupt-parent = <&qeic>;
222 };
223
224 ucc@2200 {
225 cell-index = <3>;
226 reg = <0x2200 0x200>;
227 interrupts = <34>;
228 interrupt-parent = <&qeic>;
229 };
230
231 muram@10000 {
232 #address-cells = <1>;
233 #size-cells = <1>;
234 compatible = "fsl,qe-muram", "fsl,cpm-muram";
235 ranges = <0x0 0x10000 0x6000>;
236
237 data-only@0 {
238 compatible = "fsl,qe-muram-data",
239 "fsl,cpm-muram-data";
240 reg = <0x0 0x6000>;
241 };
242 };
243};
244
245/include/ "pq3-etsec2-grp2-0.dtsi"
246/include/ "pq3-etsec2-grp2-1.dtsi"
247/include/ "pq3-etsec2-grp2-2.dtsi"
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
41};
42
43/* controller at 0x9000 */
44&pci0 {
45 compatible = "fsl,mpc8548-pcie";
46 device_type = "pci";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
51 interrupts = <16 2 0 0>;
52
53 pcie@0 {
54 reg = <0 0 0 0 0>;
55 #interrupt-cells = <1>;
56 #size-cells = <2>;
57 #address-cells = <3>;
58 device_type = "pci";
59 interrupts = <16 2 0 0>;
60 interrupt-map-mask = <0xf800 0 0 7>;
61 interrupt-map = <
62 /* IDSEL 0x0 */
63 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
64 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
65 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
66 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
67 >;
68 };
69};
70
71/* controller at 0xa000 */
72&pci1 {
73 compatible = "fsl,mpc8548-pcie";
74 device_type = "pci";
75 #size-cells = <2>;
76 #address-cells = <3>;
77 bus-range = <0 255>;
78 clock-frequency = <33333333>;
79 interrupts = <16 2 0 0>;
80
81 pcie@0 {
82 reg = <0 0 0 0 0>;
83 #interrupt-cells = <1>;
84 #size-cells = <2>;
85 #address-cells = <3>;
86 device_type = "pci";
87 interrupts = <16 2 0 0>;
88 interrupt-map-mask = <0xf800 0 0 7>;
89
90 interrupt-map = <
91 /* IDSEL 0x0 */
92 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
93 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
94 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
95 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
96 >;
97 };
98};
99
100&soc {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 device_type = "soc";
104 compatible = "fsl,p1021-immr", "simple-bus";
105 bus-frequency = <0>; // Filled out by uboot.
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <12>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,p1021-ecm", "fsl,ecm";
115 reg = <0x1000 0x1000>;
116 interrupts = <16 2 0 0>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,p1021-memory-controller";
121 reg = <0x2000 0x1000>;
122 interrupts = <16 2 0 0>;
123 };
124
125/include/ "pq3-i2c-0.dtsi"
126/include/ "pq3-i2c-1.dtsi"
127/include/ "pq3-duart-0.dtsi"
128
129/include/ "pq3-espi-0.dtsi"
130 spi@7000 {
131 fsl,espi-num-chipselects = <4>;
132 };
133
134/include/ "pq3-gpio-0.dtsi"
135
136 L2: l2-cache-controller@20000 {
137 compatible = "fsl,p1021-l2-cache-controller";
138 reg = <0x20000 0x1000>;
139 cache-line-size = <32>; // 32 bytes
140 cache-size = <0x40000>; // L2,256K
141 interrupts = <16 2 0 0>;
142 };
143
144/include/ "pq3-dma-0.dtsi"
145/include/ "pq3-usb2-dr-0.dtsi"
146 usb@22000 {
147 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
148 };
149
150/include/ "pq3-esdhc-0.dtsi"
151 sdhc@2e000 {
152 sdhci,auto-cmd12;
153 };
154
155/include/ "pq3-sec3.3-0.dtsi"
156
157/include/ "pq3-mpic.dtsi"
158/include/ "pq3-mpic-timer-B.dtsi"
159
160/include/ "pq3-etsec2-0.dtsi"
161 enet0: enet0_grp2: ethernet@b0000 {
162 };
163
164/include/ "pq3-etsec2-1.dtsi"
165 enet1: enet1_grp2: ethernet@b1000 {
166 };
167
168/include/ "pq3-etsec2-2.dtsi"
169 enet2: enet2_grp2: ethernet@b2000 {
170 };
171
172 global-utilities@e0000 {
173 compatible = "fsl,p1021-guts";
174 reg = <0xe0000 0x1000>;
175 fsl,has-rstcr;
176 };
177};
178
179&qe {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "qe";
183 compatible = "fsl,qe";
184 fsl,qe-num-riscs = <1>;
185 fsl,qe-num-snums = <28>;
186
187 qeic: interrupt-controller@80 {
188 interrupt-controller;
189 compatible = "fsl,qe-ic";
190 #address-cells = <0>;
191 #interrupt-cells = <1>;
192 reg = <0x80 0x80>;
193 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
194 };
195
196 ucc@2000 {
197 cell-index = <1>;
198 reg = <0x2000 0x200>;
199 interrupts = <32>;
200 interrupt-parent = <&qeic>;
201 };
202
203 mdio@2120 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 reg = <0x2120 0x18>;
207 compatible = "fsl,ucc-mdio";
208 };
209
210 ucc@2400 {
211 cell-index = <5>;
212 reg = <0x2400 0x200>;
213 interrupts = <40>;
214 interrupt-parent = <&qeic>;
215 };
216
217 ucc@2600 {
218 cell-index = <7>;
219 reg = <0x2600 0x200>;
220 interrupts = <42>;
221 interrupt-parent = <&qeic>;
222 };
223
224 ucc@2200 {
225 cell-index = <3>;
226 reg = <0x2200 0x200>;
227 interrupts = <34>;
228 interrupt-parent = <&qeic>;
229 };
230
231 muram@10000 {
232 #address-cells = <1>;
233 #size-cells = <1>;
234 compatible = "fsl,qe-muram", "fsl,cpm-muram";
235 ranges = <0x0 0x10000 0x6000>;
236
237 data-only@0 {
238 compatible = "fsl,qe-muram-data",
239 "fsl,cpm-muram-data";
240 reg = <0x0 0x6000>;
241 };
242 };
243};
244
245/include/ "pq3-etsec2-grp2-0.dtsi"
246/include/ "pq3-etsec2-grp2-1.dtsi"
247/include/ "pq3-etsec2-grp2-2.dtsi"