1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
 7 */
 8#ifndef __ASM_MIPS_MACH_IP22_WAR_H
 9#define __ASM_MIPS_MACH_IP22_WAR_H
10
11/*
12 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
13 */
14
15#define R4600_V1_INDEX_ICACHEOP_WAR	1
16#define R4600_V1_HIT_CACHEOP_WAR	1
17#define R4600_V2_HIT_CACHEOP_WAR	1
18#define BCM1250_M3_WAR			0
19#define SIBYTE_1956_WAR			0
20#define MIPS4K_ICACHE_REFILL_WAR	0
21#define MIPS_CACHE_SYNC_WAR		0
22#define TX49XX_ICACHE_INDEX_INV_WAR	0
23#define ICACHE_REFILLS_WORKAROUND_WAR	0
24#define R10000_LLSC_WAR			0
25#define MIPS34K_MISSED_ITLB_WAR		0
26
27#endif /* __ASM_MIPS_MACH_IP22_WAR_H */