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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/reset.h>
19#include <linux/spinlock.h>
20
21#include <sound/dmaengine_pcm.h>
22#include <sound/pcm_params.h>
23
24#define STM32_I2S_CR1_REG 0x0
25#define STM32_I2S_CFG1_REG 0x08
26#define STM32_I2S_CFG2_REG 0x0C
27#define STM32_I2S_IER_REG 0x10
28#define STM32_I2S_SR_REG 0x14
29#define STM32_I2S_IFCR_REG 0x18
30#define STM32_I2S_TXDR_REG 0X20
31#define STM32_I2S_RXDR_REG 0x30
32#define STM32_I2S_CGFR_REG 0X50
33#define STM32_I2S_HWCFGR_REG 0x3F0
34#define STM32_I2S_VERR_REG 0x3F4
35#define STM32_I2S_IPIDR_REG 0x3F8
36#define STM32_I2S_SIDR_REG 0x3FC
37
38/* Bit definition for SPI2S_CR1 register */
39#define I2S_CR1_SPE BIT(0)
40#define I2S_CR1_CSTART BIT(9)
41#define I2S_CR1_CSUSP BIT(10)
42#define I2S_CR1_HDDIR BIT(11)
43#define I2S_CR1_SSI BIT(12)
44#define I2S_CR1_CRC33_17 BIT(13)
45#define I2S_CR1_RCRCI BIT(14)
46#define I2S_CR1_TCRCI BIT(15)
47
48/* Bit definition for SPI_CFG2 register */
49#define I2S_CFG2_IOSWP_SHIFT 15
50#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
51#define I2S_CFG2_LSBFRST BIT(23)
52#define I2S_CFG2_AFCNTR BIT(31)
53
54/* Bit definition for SPI_CFG1 register */
55#define I2S_CFG1_FTHVL_SHIFT 5
56#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
57#define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
58
59#define I2S_CFG1_TXDMAEN BIT(15)
60#define I2S_CFG1_RXDMAEN BIT(14)
61
62/* Bit definition for SPI2S_IER register */
63#define I2S_IER_RXPIE BIT(0)
64#define I2S_IER_TXPIE BIT(1)
65#define I2S_IER_DPXPIE BIT(2)
66#define I2S_IER_EOTIE BIT(3)
67#define I2S_IER_TXTFIE BIT(4)
68#define I2S_IER_UDRIE BIT(5)
69#define I2S_IER_OVRIE BIT(6)
70#define I2S_IER_CRCEIE BIT(7)
71#define I2S_IER_TIFREIE BIT(8)
72#define I2S_IER_MODFIE BIT(9)
73#define I2S_IER_TSERFIE BIT(10)
74
75/* Bit definition for SPI2S_SR register */
76#define I2S_SR_RXP BIT(0)
77#define I2S_SR_TXP BIT(1)
78#define I2S_SR_DPXP BIT(2)
79#define I2S_SR_EOT BIT(3)
80#define I2S_SR_TXTF BIT(4)
81#define I2S_SR_UDR BIT(5)
82#define I2S_SR_OVR BIT(6)
83#define I2S_SR_CRCERR BIT(7)
84#define I2S_SR_TIFRE BIT(8)
85#define I2S_SR_MODF BIT(9)
86#define I2S_SR_TSERF BIT(10)
87#define I2S_SR_SUSP BIT(11)
88#define I2S_SR_TXC BIT(12)
89#define I2S_SR_RXPLVL GENMASK(14, 13)
90#define I2S_SR_RXWNE BIT(15)
91
92#define I2S_SR_MASK GENMASK(15, 0)
93
94/* Bit definition for SPI_IFCR register */
95#define I2S_IFCR_EOTC BIT(3)
96#define I2S_IFCR_TXTFC BIT(4)
97#define I2S_IFCR_UDRC BIT(5)
98#define I2S_IFCR_OVRC BIT(6)
99#define I2S_IFCR_CRCEC BIT(7)
100#define I2S_IFCR_TIFREC BIT(8)
101#define I2S_IFCR_MODFC BIT(9)
102#define I2S_IFCR_TSERFC BIT(10)
103#define I2S_IFCR_SUSPC BIT(11)
104
105#define I2S_IFCR_MASK GENMASK(11, 3)
106
107/* Bit definition for SPI_I2SCGFR register */
108#define I2S_CGFR_I2SMOD BIT(0)
109
110#define I2S_CGFR_I2SCFG_SHIFT 1
111#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
112#define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
113
114#define I2S_CGFR_I2SSTD_SHIFT 4
115#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
116#define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
117
118#define I2S_CGFR_PCMSYNC BIT(7)
119
120#define I2S_CGFR_DATLEN_SHIFT 8
121#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
122#define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
123
124#define I2S_CGFR_CHLEN_SHIFT 10
125#define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
126#define I2S_CGFR_CKPOL BIT(11)
127#define I2S_CGFR_FIXCH BIT(12)
128#define I2S_CGFR_WSINV BIT(13)
129#define I2S_CGFR_DATFMT BIT(14)
130
131#define I2S_CGFR_I2SDIV_SHIFT 16
132#define I2S_CGFR_I2SDIV_BIT_H 23
133#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
134 I2S_CGFR_I2SDIV_SHIFT)
135#define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
136#define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
138
139#define I2S_CGFR_ODD_SHIFT 24
140#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
141#define I2S_CGFR_MCKOE BIT(25)
142
143/* Registers below apply to I2S version 1.1 and more */
144
145/* Bit definition for SPI_HWCFGR register */
146#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
147
148/* Bit definition for SPI_VERR register */
149#define I2S_VERR_MIN_MASK GENMASK(3, 0)
150#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
151
152/* Bit definition for SPI_IPIDR register */
153#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
154
155/* Bit definition for SPI_SIDR register */
156#define I2S_SIDR_ID_MASK GENMASK(31, 0)
157
158#define I2S_IPIDR_NUMBER 0x00130022
159
160enum i2s_master_mode {
161 I2S_MS_NOT_SET,
162 I2S_MS_MASTER,
163 I2S_MS_SLAVE,
164};
165
166enum i2s_mode {
167 I2S_I2SMOD_TX_SLAVE,
168 I2S_I2SMOD_RX_SLAVE,
169 I2S_I2SMOD_TX_MASTER,
170 I2S_I2SMOD_RX_MASTER,
171 I2S_I2SMOD_FD_SLAVE,
172 I2S_I2SMOD_FD_MASTER,
173};
174
175enum i2s_fifo_th {
176 I2S_FIFO_TH_NONE,
177 I2S_FIFO_TH_ONE_QUARTER,
178 I2S_FIFO_TH_HALF,
179 I2S_FIFO_TH_THREE_QUARTER,
180 I2S_FIFO_TH_FULL,
181};
182
183enum i2s_std {
184 I2S_STD_I2S,
185 I2S_STD_LEFT_J,
186 I2S_STD_RIGHT_J,
187 I2S_STD_DSP,
188};
189
190enum i2s_datlen {
191 I2S_I2SMOD_DATLEN_16,
192 I2S_I2SMOD_DATLEN_24,
193 I2S_I2SMOD_DATLEN_32,
194};
195
196#define STM32_I2S_FIFO_SIZE 16
197
198#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
200
201#define STM32_I2S_NAME_LEN 32
202#define STM32_I2S_RATE_11K 11025
203
204/**
205 * struct stm32_i2s_data - private data of I2S
206 * @regmap_conf: I2S register map configuration pointer
207 * @regmap: I2S register map pointer
208 * @pdev: device data pointer
209 * @dai_drv: DAI driver pointer
210 * @dma_data_tx: dma configuration data for tx channel
211 * @dma_data_rx: dma configuration data for tx channel
212 * @substream: PCM substream data pointer
213 * @i2sclk: kernel clock feeding the I2S clock generator
214 * @i2smclk: master clock from I2S mclk provider
215 * @pclk: peripheral clock driving bus interface
216 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
217 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
218 * @base: mmio register base virtual address
219 * @phys_addr: I2S registers physical base address
220 * @lock_fd: lock to manage race conditions in full duplex mode
221 * @irq_lock: prevent race condition with IRQ
222 * @mclk_rate: master clock frequency (Hz)
223 * @fmt: DAI protocol
224 * @divider: prescaler division ratio
225 * @div: prescaler div field
226 * @odd: prescaler odd field
227 * @refcount: keep count of opened streams on I2S
228 * @ms_flg: master mode flag.
229 */
230struct stm32_i2s_data {
231 const struct regmap_config *regmap_conf;
232 struct regmap *regmap;
233 struct platform_device *pdev;
234 struct snd_soc_dai_driver *dai_drv;
235 struct snd_dmaengine_dai_dma_data dma_data_tx;
236 struct snd_dmaengine_dai_dma_data dma_data_rx;
237 struct snd_pcm_substream *substream;
238 struct clk *i2sclk;
239 struct clk *i2smclk;
240 struct clk *pclk;
241 struct clk *x8kclk;
242 struct clk *x11kclk;
243 void __iomem *base;
244 dma_addr_t phys_addr;
245 spinlock_t lock_fd; /* Manage race conditions for full duplex */
246 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
247 unsigned int mclk_rate;
248 unsigned int fmt;
249 unsigned int divider;
250 unsigned int div;
251 bool odd;
252 int refcount;
253 int ms_flg;
254};
255
256struct stm32_i2smclk_data {
257 struct clk_hw hw;
258 unsigned long freq;
259 struct stm32_i2s_data *i2s_data;
260};
261
262#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
263
264static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
265 unsigned long input_rate,
266 unsigned long output_rate)
267{
268 unsigned int ratio, div, divider = 1;
269 bool odd;
270
271 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
272
273 /* Check the parity of the divider */
274 odd = ratio & 0x1;
275
276 /* Compute the div prescaler */
277 div = ratio >> 1;
278
279 /* If div is 0 actual divider is 1 */
280 if (div) {
281 divider = ((2 * div) + odd);
282 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
283 div, odd, divider);
284 }
285
286 /* Division by three is not allowed by I2S prescaler */
287 if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
288 dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
289 return -EINVAL;
290 }
291
292 if (input_rate % divider)
293 dev_dbg(&i2s->pdev->dev,
294 "Rate not accurate. requested (%ld), actual (%ld)\n",
295 output_rate, input_rate / divider);
296
297 i2s->div = div;
298 i2s->odd = odd;
299 i2s->divider = divider;
300
301 return 0;
302}
303
304static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
305{
306 u32 cgfr, cgfr_mask;
307
308 cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
309 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
310
311 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
312 cgfr_mask, cgfr);
313}
314
315static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
316 unsigned int rate)
317{
318 struct platform_device *pdev = i2s->pdev;
319 struct clk *parent_clk;
320 int ret;
321
322 if (!(rate % STM32_I2S_RATE_11K))
323 parent_clk = i2s->x11kclk;
324 else
325 parent_clk = i2s->x8kclk;
326
327 ret = clk_set_parent(i2s->i2sclk, parent_clk);
328 if (ret)
329 dev_err(&pdev->dev,
330 "Error %d setting i2sclk parent clock\n", ret);
331
332 return ret;
333}
334
335static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
336 unsigned long *prate)
337{
338 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
339 struct stm32_i2s_data *i2s = mclk->i2s_data;
340 int ret;
341
342 ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
343 if (ret)
344 return ret;
345
346 mclk->freq = *prate / i2s->divider;
347
348 return mclk->freq;
349}
350
351static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
352 unsigned long parent_rate)
353{
354 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
355
356 return mclk->freq;
357}
358
359static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
360 unsigned long parent_rate)
361{
362 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
363 struct stm32_i2s_data *i2s = mclk->i2s_data;
364 int ret;
365
366 ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
367 if (ret)
368 return ret;
369
370 ret = stm32_i2s_set_clk_div(i2s);
371 if (ret)
372 return ret;
373
374 mclk->freq = rate;
375
376 return 0;
377}
378
379static int stm32_i2smclk_enable(struct clk_hw *hw)
380{
381 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
382 struct stm32_i2s_data *i2s = mclk->i2s_data;
383
384 dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
385
386 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
387 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
388}
389
390static void stm32_i2smclk_disable(struct clk_hw *hw)
391{
392 struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
393 struct stm32_i2s_data *i2s = mclk->i2s_data;
394
395 dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
396
397 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
398}
399
400static const struct clk_ops mclk_ops = {
401 .enable = stm32_i2smclk_enable,
402 .disable = stm32_i2smclk_disable,
403 .recalc_rate = stm32_i2smclk_recalc_rate,
404 .round_rate = stm32_i2smclk_round_rate,
405 .set_rate = stm32_i2smclk_set_rate,
406};
407
408static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
409{
410 struct clk_hw *hw;
411 struct stm32_i2smclk_data *mclk;
412 struct device *dev = &i2s->pdev->dev;
413 const char *pname = __clk_get_name(i2s->i2sclk);
414 char *mclk_name, *p, *s = (char *)pname;
415 int ret, i = 0;
416
417 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
418 if (!mclk)
419 return -ENOMEM;
420
421 mclk_name = devm_kcalloc(dev, sizeof(char),
422 STM32_I2S_NAME_LEN, GFP_KERNEL);
423 if (!mclk_name)
424 return -ENOMEM;
425
426 /*
427 * Forge mclk clock name from parent clock name and suffix.
428 * String after "_" char is stripped in parent name.
429 */
430 p = mclk_name;
431 while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
432 *p++ = *s++;
433 i++;
434 }
435 strcat(p, "_mclk");
436
437 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
438 mclk->i2s_data = i2s;
439 hw = &mclk->hw;
440
441 dev_dbg(dev, "Register master clock %s\n", mclk_name);
442 ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
443 if (ret) {
444 dev_err(dev, "mclk register fails with error %d\n", ret);
445 return ret;
446 }
447 i2s->i2smclk = hw->clk;
448
449 /* register mclk provider */
450 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
451}
452
453static irqreturn_t stm32_i2s_isr(int irq, void *devid)
454{
455 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
456 struct platform_device *pdev = i2s->pdev;
457 u32 sr, ier;
458 unsigned long flags;
459 int err = 0;
460
461 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
462 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
463
464 flags = sr & ier;
465 if (!flags) {
466 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
467 sr, ier);
468 return IRQ_NONE;
469 }
470
471 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
472 I2S_IFCR_MASK, flags);
473
474 if (flags & I2S_SR_OVR) {
475 dev_dbg(&pdev->dev, "Overrun\n");
476 err = 1;
477 }
478
479 if (flags & I2S_SR_UDR) {
480 dev_dbg(&pdev->dev, "Underrun\n");
481 err = 1;
482 }
483
484 if (flags & I2S_SR_TIFRE)
485 dev_dbg(&pdev->dev, "Frame error\n");
486
487 spin_lock(&i2s->irq_lock);
488 if (err && i2s->substream)
489 snd_pcm_stop_xrun(i2s->substream);
490 spin_unlock(&i2s->irq_lock);
491
492 return IRQ_HANDLED;
493}
494
495static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
496{
497 switch (reg) {
498 case STM32_I2S_CR1_REG:
499 case STM32_I2S_CFG1_REG:
500 case STM32_I2S_CFG2_REG:
501 case STM32_I2S_IER_REG:
502 case STM32_I2S_SR_REG:
503 case STM32_I2S_RXDR_REG:
504 case STM32_I2S_CGFR_REG:
505 case STM32_I2S_HWCFGR_REG:
506 case STM32_I2S_VERR_REG:
507 case STM32_I2S_IPIDR_REG:
508 case STM32_I2S_SIDR_REG:
509 return true;
510 default:
511 return false;
512 }
513}
514
515static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
516{
517 switch (reg) {
518 case STM32_I2S_SR_REG:
519 case STM32_I2S_RXDR_REG:
520 return true;
521 default:
522 return false;
523 }
524}
525
526static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
527{
528 switch (reg) {
529 case STM32_I2S_CR1_REG:
530 case STM32_I2S_CFG1_REG:
531 case STM32_I2S_CFG2_REG:
532 case STM32_I2S_IER_REG:
533 case STM32_I2S_IFCR_REG:
534 case STM32_I2S_TXDR_REG:
535 case STM32_I2S_CGFR_REG:
536 return true;
537 default:
538 return false;
539 }
540}
541
542static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
543{
544 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
545 u32 cgfr;
546 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
547 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
548
549 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
550
551 /*
552 * winv = 0 : default behavior (high/low) for all standards
553 * ckpol = 0 for all standards.
554 */
555 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
556 case SND_SOC_DAIFMT_I2S:
557 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
558 break;
559 case SND_SOC_DAIFMT_MSB:
560 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
561 break;
562 case SND_SOC_DAIFMT_LSB:
563 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
564 break;
565 case SND_SOC_DAIFMT_DSP_A:
566 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
567 break;
568 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
569 default:
570 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
571 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
572 return -EINVAL;
573 }
574
575 /* DAI clock strobing */
576 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
577 case SND_SOC_DAIFMT_NB_NF:
578 break;
579 case SND_SOC_DAIFMT_IB_NF:
580 cgfr |= I2S_CGFR_CKPOL;
581 break;
582 case SND_SOC_DAIFMT_NB_IF:
583 cgfr |= I2S_CGFR_WSINV;
584 break;
585 case SND_SOC_DAIFMT_IB_IF:
586 cgfr |= I2S_CGFR_CKPOL;
587 cgfr |= I2S_CGFR_WSINV;
588 break;
589 default:
590 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
591 fmt & SND_SOC_DAIFMT_INV_MASK);
592 return -EINVAL;
593 }
594
595 /* DAI clock master masks */
596 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
597 case SND_SOC_DAIFMT_BC_FC:
598 i2s->ms_flg = I2S_MS_SLAVE;
599 break;
600 case SND_SOC_DAIFMT_BP_FP:
601 i2s->ms_flg = I2S_MS_MASTER;
602 break;
603 default:
604 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
605 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
606 return -EINVAL;
607 }
608
609 i2s->fmt = fmt;
610 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
611 cgfr_mask, cgfr);
612}
613
614static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
615 int clk_id, unsigned int freq, int dir)
616{
617 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
618 int ret = 0;
619
620 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
621 freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
622 dir ? "output" : "input");
623
624 /* MCLK generation is available only in master mode */
625 if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
626 if (!i2s->i2smclk) {
627 dev_dbg(cpu_dai->dev, "No MCLK registered\n");
628 return 0;
629 }
630
631 /* Assume shutdown if requested frequency is 0Hz */
632 if (!freq) {
633 /* Release mclk rate only if rate was actually set */
634 if (i2s->mclk_rate) {
635 clk_rate_exclusive_put(i2s->i2smclk);
636 i2s->mclk_rate = 0;
637 }
638 return regmap_update_bits(i2s->regmap,
639 STM32_I2S_CGFR_REG,
640 I2S_CGFR_MCKOE, 0);
641 }
642 /* If master clock is used, set parent clock now */
643 ret = stm32_i2s_set_parent_clock(i2s, freq);
644 if (ret)
645 return ret;
646 ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
647 if (ret) {
648 dev_err(cpu_dai->dev, "Could not set mclk rate\n");
649 return ret;
650 }
651 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
652 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
653 if (!ret)
654 i2s->mclk_rate = freq;
655 }
656
657 return ret;
658}
659
660static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
661 struct snd_pcm_hw_params *params)
662{
663 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
664 unsigned long i2s_clock_rate;
665 unsigned int nb_bits, frame_len;
666 unsigned int rate = params_rate(params);
667 u32 cgfr;
668 int ret;
669
670 if (!(rate % 11025))
671 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
672 else
673 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
674 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
675
676 /*
677 * mckl = mclk_ratio x ws
678 * i2s mode : mclk_ratio = 256
679 * dsp mode : mclk_ratio = 128
680 *
681 * mclk on
682 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
683 * dsp mode : div = i2s_clk / (mclk_ratio * ws)
684 * mclk off
685 * i2s mode : div = i2s_clk / (nb_bits x ws)
686 * dsp mode : div = i2s_clk / (nb_bits x ws)
687 */
688 if (i2s->mclk_rate) {
689 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
690 i2s->mclk_rate);
691 if (ret)
692 return ret;
693 } else {
694 frame_len = 32;
695 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
696 SND_SOC_DAIFMT_DSP_A)
697 frame_len = 16;
698
699 /* master clock not enabled */
700 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
701 if (ret < 0)
702 return ret;
703
704 nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
705 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
706 (nb_bits * rate));
707 if (ret)
708 return ret;
709 }
710
711 ret = stm32_i2s_set_clk_div(i2s);
712 if (ret < 0)
713 return ret;
714
715 /* Set bitclock and frameclock to their inactive state */
716 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
717 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
718}
719
720static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
721 struct snd_pcm_hw_params *params,
722 struct snd_pcm_substream *substream)
723{
724 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
725 int format = params_width(params);
726 u32 cfgr, cfgr_mask, cfg1;
727 unsigned int fthlv;
728 int ret;
729
730 switch (format) {
731 case 16:
732 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
733 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
734 break;
735 case 32:
736 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
737 I2S_CGFR_CHLEN;
738 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
739 break;
740 default:
741 dev_err(cpu_dai->dev, "Unexpected format %d", format);
742 return -EINVAL;
743 }
744
745 if (STM32_I2S_IS_SLAVE(i2s)) {
746 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
747
748 /* As data length is either 16 or 32 bits, fixch always set */
749 cfgr |= I2S_CGFR_FIXCH;
750 cfgr_mask |= I2S_CGFR_FIXCH;
751 } else {
752 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
753 }
754 cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
755
756 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
757 cfgr_mask, cfgr);
758 if (ret < 0)
759 return ret;
760
761 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
762 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
763
764 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
765 I2S_CFG1_FTHVL_MASK, cfg1);
766}
767
768static int stm32_i2s_startup(struct snd_pcm_substream *substream,
769 struct snd_soc_dai *cpu_dai)
770{
771 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
772 unsigned long flags;
773 int ret;
774
775 spin_lock_irqsave(&i2s->irq_lock, flags);
776 i2s->substream = substream;
777 spin_unlock_irqrestore(&i2s->irq_lock, flags);
778
779 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
780 snd_pcm_hw_constraint_single(substream->runtime,
781 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
782
783 ret = clk_prepare_enable(i2s->i2sclk);
784 if (ret < 0) {
785 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
786 return ret;
787 }
788
789 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
790 I2S_IFCR_MASK, I2S_IFCR_MASK);
791}
792
793static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
794 struct snd_pcm_hw_params *params,
795 struct snd_soc_dai *cpu_dai)
796{
797 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
798 int ret;
799
800 ret = stm32_i2s_configure(cpu_dai, params, substream);
801 if (ret < 0) {
802 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
803 return ret;
804 }
805
806 if (STM32_I2S_IS_MASTER(i2s))
807 ret = stm32_i2s_configure_clock(cpu_dai, params);
808
809 return ret;
810}
811
812static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
813 struct snd_soc_dai *cpu_dai)
814{
815 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
816 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
817 u32 cfg1_mask, ier;
818 int ret;
819
820 switch (cmd) {
821 case SNDRV_PCM_TRIGGER_START:
822 case SNDRV_PCM_TRIGGER_RESUME:
823 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
824 /* Enable i2s */
825 dev_dbg(cpu_dai->dev, "start I2S %s\n",
826 playback_flg ? "playback" : "capture");
827
828 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
829 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
830 cfg1_mask, cfg1_mask);
831
832 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
833 I2S_CR1_SPE, I2S_CR1_SPE);
834 if (ret < 0) {
835 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
836 return ret;
837 }
838
839 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
840 I2S_CR1_CSTART, I2S_CR1_CSTART);
841 if (ret < 0) {
842 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
843 return ret;
844 }
845
846 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
847 I2S_IFCR_MASK, I2S_IFCR_MASK);
848
849 spin_lock(&i2s->lock_fd);
850 i2s->refcount++;
851 if (playback_flg) {
852 ier = I2S_IER_UDRIE;
853 } else {
854 ier = I2S_IER_OVRIE;
855
856 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
857 /* dummy write to gate bus clocks */
858 regmap_write(i2s->regmap,
859 STM32_I2S_TXDR_REG, 0);
860 }
861 spin_unlock(&i2s->lock_fd);
862
863 if (STM32_I2S_IS_SLAVE(i2s))
864 ier |= I2S_IER_TIFREIE;
865
866 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
867 break;
868 case SNDRV_PCM_TRIGGER_STOP:
869 case SNDRV_PCM_TRIGGER_SUSPEND:
870 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
871 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
872 playback_flg ? "playback" : "capture");
873
874 if (playback_flg)
875 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
876 I2S_IER_UDRIE,
877 (unsigned int)~I2S_IER_UDRIE);
878 else
879 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
880 I2S_IER_OVRIE,
881 (unsigned int)~I2S_IER_OVRIE);
882
883 spin_lock(&i2s->lock_fd);
884 i2s->refcount--;
885 if (i2s->refcount) {
886 spin_unlock(&i2s->lock_fd);
887 break;
888 }
889
890 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
891 I2S_CR1_SPE, 0);
892 if (ret < 0) {
893 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
894 spin_unlock(&i2s->lock_fd);
895 return ret;
896 }
897 spin_unlock(&i2s->lock_fd);
898
899 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
900 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
901 cfg1_mask, 0);
902 break;
903 default:
904 return -EINVAL;
905 }
906
907 return 0;
908}
909
910static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
911 struct snd_soc_dai *cpu_dai)
912{
913 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
914 unsigned long flags;
915
916 clk_disable_unprepare(i2s->i2sclk);
917
918 spin_lock_irqsave(&i2s->irq_lock, flags);
919 i2s->substream = NULL;
920 spin_unlock_irqrestore(&i2s->irq_lock, flags);
921}
922
923static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
924{
925 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
926 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
927 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
928
929 /* Buswidth will be set by framework */
930 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
931 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
932 dma_data_tx->maxburst = 1;
933 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
934 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
935 dma_data_rx->maxburst = 1;
936
937 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
938
939 return 0;
940}
941
942static const struct regmap_config stm32_h7_i2s_regmap_conf = {
943 .reg_bits = 32,
944 .reg_stride = 4,
945 .val_bits = 32,
946 .max_register = STM32_I2S_SIDR_REG,
947 .readable_reg = stm32_i2s_readable_reg,
948 .volatile_reg = stm32_i2s_volatile_reg,
949 .writeable_reg = stm32_i2s_writeable_reg,
950 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
951 .fast_io = true,
952 .cache_type = REGCACHE_FLAT,
953};
954
955static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
956 .probe = stm32_i2s_dai_probe,
957 .set_sysclk = stm32_i2s_set_sysclk,
958 .set_fmt = stm32_i2s_set_dai_fmt,
959 .startup = stm32_i2s_startup,
960 .hw_params = stm32_i2s_hw_params,
961 .trigger = stm32_i2s_trigger,
962 .shutdown = stm32_i2s_shutdown,
963};
964
965static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
966 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
967 .buffer_bytes_max = 8 * PAGE_SIZE,
968 .period_bytes_min = 1024,
969 .period_bytes_max = 4 * PAGE_SIZE,
970 .periods_min = 2,
971 .periods_max = 8,
972};
973
974static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
975 .pcm_hardware = &stm32_i2s_pcm_hw,
976 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
977 .prealloc_buffer_size = PAGE_SIZE * 8,
978};
979
980static const struct snd_soc_component_driver stm32_i2s_component = {
981 .name = "stm32-i2s",
982 .legacy_dai_naming = 1,
983};
984
985static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
986 char *stream_name)
987{
988 stream->stream_name = stream_name;
989 stream->channels_min = 1;
990 stream->channels_max = 2;
991 stream->rates = SNDRV_PCM_RATE_8000_192000;
992 stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
993 SNDRV_PCM_FMTBIT_S32_LE;
994}
995
996static int stm32_i2s_dais_init(struct platform_device *pdev,
997 struct stm32_i2s_data *i2s)
998{
999 struct snd_soc_dai_driver *dai_ptr;
1000
1001 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
1002 GFP_KERNEL);
1003 if (!dai_ptr)
1004 return -ENOMEM;
1005
1006 dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
1007 dai_ptr->id = 1;
1008 stm32_i2s_dai_init(&dai_ptr->playback, "playback");
1009 stm32_i2s_dai_init(&dai_ptr->capture, "capture");
1010 i2s->dai_drv = dai_ptr;
1011
1012 return 0;
1013}
1014
1015static const struct of_device_id stm32_i2s_ids[] = {
1016 {
1017 .compatible = "st,stm32h7-i2s",
1018 .data = &stm32_h7_i2s_regmap_conf
1019 },
1020 {},
1021};
1022
1023static int stm32_i2s_parse_dt(struct platform_device *pdev,
1024 struct stm32_i2s_data *i2s)
1025{
1026 struct device_node *np = pdev->dev.of_node;
1027 struct reset_control *rst;
1028 struct resource *res;
1029 int irq, ret;
1030
1031 if (!np)
1032 return -ENODEV;
1033
1034 i2s->regmap_conf = device_get_match_data(&pdev->dev);
1035 if (!i2s->regmap_conf)
1036 return -EINVAL;
1037
1038 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1039 if (IS_ERR(i2s->base))
1040 return PTR_ERR(i2s->base);
1041
1042 i2s->phys_addr = res->start;
1043
1044 /* Get clocks */
1045 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1046 if (IS_ERR(i2s->pclk))
1047 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
1048 "Could not get pclk\n");
1049
1050 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1051 if (IS_ERR(i2s->i2sclk))
1052 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
1053 "Could not get i2sclk\n");
1054
1055 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
1056 if (IS_ERR(i2s->x8kclk))
1057 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
1058 "Could not get x8k parent clock\n");
1059
1060 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
1061 if (IS_ERR(i2s->x11kclk))
1062 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
1063 "Could not get x11k parent clock\n");
1064
1065 /* Register mclk provider if requested */
1066 if (of_property_present(np, "#clock-cells")) {
1067 ret = stm32_i2s_add_mclk_provider(i2s);
1068 if (ret < 0)
1069 return ret;
1070 }
1071
1072 /* Get irqs */
1073 irq = platform_get_irq(pdev, 0);
1074 if (irq < 0)
1075 return irq;
1076
1077 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0,
1078 dev_name(&pdev->dev), i2s);
1079 if (ret) {
1080 dev_err(&pdev->dev, "irq request returned %d\n", ret);
1081 return ret;
1082 }
1083
1084 /* Reset */
1085 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1086 if (IS_ERR(rst))
1087 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
1088 "Reset controller error\n");
1089
1090 reset_control_assert(rst);
1091 udelay(2);
1092 reset_control_deassert(rst);
1093
1094 return 0;
1095}
1096
1097static void stm32_i2s_remove(struct platform_device *pdev)
1098{
1099 snd_dmaengine_pcm_unregister(&pdev->dev);
1100 snd_soc_unregister_component(&pdev->dev);
1101 pm_runtime_disable(&pdev->dev);
1102}
1103
1104static int stm32_i2s_probe(struct platform_device *pdev)
1105{
1106 struct stm32_i2s_data *i2s;
1107 u32 val;
1108 int ret;
1109
1110 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1111 if (!i2s)
1112 return -ENOMEM;
1113
1114 i2s->pdev = pdev;
1115 i2s->ms_flg = I2S_MS_NOT_SET;
1116 spin_lock_init(&i2s->lock_fd);
1117 spin_lock_init(&i2s->irq_lock);
1118 platform_set_drvdata(pdev, i2s);
1119
1120 ret = stm32_i2s_parse_dt(pdev, i2s);
1121 if (ret)
1122 return ret;
1123
1124 ret = stm32_i2s_dais_init(pdev, i2s);
1125 if (ret)
1126 return ret;
1127
1128 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1129 i2s->base, i2s->regmap_conf);
1130 if (IS_ERR(i2s->regmap))
1131 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
1132 "Regmap init error\n");
1133
1134 ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
1135 if (ret)
1136 return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
1137
1138 ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
1139 i2s->dai_drv, 1);
1140 if (ret) {
1141 snd_dmaengine_pcm_unregister(&pdev->dev);
1142 return ret;
1143 }
1144
1145 /* Set SPI/I2S in i2s mode */
1146 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1147 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
1148 if (ret)
1149 goto error;
1150
1151 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1152 if (ret)
1153 goto error;
1154
1155 if (val == I2S_IPIDR_NUMBER) {
1156 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1157 if (ret)
1158 goto error;
1159
1160 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
1161 dev_err(&pdev->dev,
1162 "Device does not support i2s mode\n");
1163 ret = -EPERM;
1164 goto error;
1165 }
1166
1167 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1168 if (ret)
1169 goto error;
1170
1171 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
1172 FIELD_GET(I2S_VERR_MAJ_MASK, val),
1173 FIELD_GET(I2S_VERR_MIN_MASK, val));
1174 }
1175
1176 pm_runtime_enable(&pdev->dev);
1177
1178 return ret;
1179
1180error:
1181 stm32_i2s_remove(pdev);
1182
1183 return ret;
1184}
1185
1186MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
1187
1188#ifdef CONFIG_PM_SLEEP
1189static int stm32_i2s_suspend(struct device *dev)
1190{
1191 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1192
1193 regcache_cache_only(i2s->regmap, true);
1194 regcache_mark_dirty(i2s->regmap);
1195
1196 return 0;
1197}
1198
1199static int stm32_i2s_resume(struct device *dev)
1200{
1201 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1202
1203 regcache_cache_only(i2s->regmap, false);
1204 return regcache_sync(i2s->regmap);
1205}
1206#endif /* CONFIG_PM_SLEEP */
1207
1208static const struct dev_pm_ops stm32_i2s_pm_ops = {
1209 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1210};
1211
1212static struct platform_driver stm32_i2s_driver = {
1213 .driver = {
1214 .name = "st,stm32-i2s",
1215 .of_match_table = stm32_i2s_ids,
1216 .pm = &stm32_i2s_pm_ops,
1217 },
1218 .probe = stm32_i2s_probe,
1219 .remove_new = stm32_i2s_remove,
1220};
1221
1222module_platform_driver(stm32_i2s_driver);
1223
1224MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1225MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1226MODULE_ALIAS("platform:stm32-i2s");
1227MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/module.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/regmap.h>
16#include <linux/reset.h>
17#include <linux/spinlock.h>
18
19#include <sound/dmaengine_pcm.h>
20#include <sound/pcm_params.h>
21
22#define STM32_I2S_CR1_REG 0x0
23#define STM32_I2S_CFG1_REG 0x08
24#define STM32_I2S_CFG2_REG 0x0C
25#define STM32_I2S_IER_REG 0x10
26#define STM32_I2S_SR_REG 0x14
27#define STM32_I2S_IFCR_REG 0x18
28#define STM32_I2S_TXDR_REG 0X20
29#define STM32_I2S_RXDR_REG 0x30
30#define STM32_I2S_CGFR_REG 0X50
31#define STM32_I2S_HWCFGR_REG 0x3F0
32#define STM32_I2S_VERR_REG 0x3F4
33#define STM32_I2S_IPIDR_REG 0x3F8
34#define STM32_I2S_SIDR_REG 0x3FC
35
36/* Bit definition for SPI2S_CR1 register */
37#define I2S_CR1_SPE BIT(0)
38#define I2S_CR1_CSTART BIT(9)
39#define I2S_CR1_CSUSP BIT(10)
40#define I2S_CR1_HDDIR BIT(11)
41#define I2S_CR1_SSI BIT(12)
42#define I2S_CR1_CRC33_17 BIT(13)
43#define I2S_CR1_RCRCI BIT(14)
44#define I2S_CR1_TCRCI BIT(15)
45
46/* Bit definition for SPI_CFG2 register */
47#define I2S_CFG2_IOSWP_SHIFT 15
48#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
49#define I2S_CFG2_LSBFRST BIT(23)
50#define I2S_CFG2_AFCNTR BIT(31)
51
52/* Bit definition for SPI_CFG1 register */
53#define I2S_CFG1_FTHVL_SHIFT 5
54#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
55#define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
56
57#define I2S_CFG1_TXDMAEN BIT(15)
58#define I2S_CFG1_RXDMAEN BIT(14)
59
60/* Bit definition for SPI2S_IER register */
61#define I2S_IER_RXPIE BIT(0)
62#define I2S_IER_TXPIE BIT(1)
63#define I2S_IER_DPXPIE BIT(2)
64#define I2S_IER_EOTIE BIT(3)
65#define I2S_IER_TXTFIE BIT(4)
66#define I2S_IER_UDRIE BIT(5)
67#define I2S_IER_OVRIE BIT(6)
68#define I2S_IER_CRCEIE BIT(7)
69#define I2S_IER_TIFREIE BIT(8)
70#define I2S_IER_MODFIE BIT(9)
71#define I2S_IER_TSERFIE BIT(10)
72
73/* Bit definition for SPI2S_SR register */
74#define I2S_SR_RXP BIT(0)
75#define I2S_SR_TXP BIT(1)
76#define I2S_SR_DPXP BIT(2)
77#define I2S_SR_EOT BIT(3)
78#define I2S_SR_TXTF BIT(4)
79#define I2S_SR_UDR BIT(5)
80#define I2S_SR_OVR BIT(6)
81#define I2S_SR_CRCERR BIT(7)
82#define I2S_SR_TIFRE BIT(8)
83#define I2S_SR_MODF BIT(9)
84#define I2S_SR_TSERF BIT(10)
85#define I2S_SR_SUSP BIT(11)
86#define I2S_SR_TXC BIT(12)
87#define I2S_SR_RXPLVL GENMASK(14, 13)
88#define I2S_SR_RXWNE BIT(15)
89
90#define I2S_SR_MASK GENMASK(15, 0)
91
92/* Bit definition for SPI_IFCR register */
93#define I2S_IFCR_EOTC BIT(3)
94#define I2S_IFCR_TXTFC BIT(4)
95#define I2S_IFCR_UDRC BIT(5)
96#define I2S_IFCR_OVRC BIT(6)
97#define I2S_IFCR_CRCEC BIT(7)
98#define I2S_IFCR_TIFREC BIT(8)
99#define I2S_IFCR_MODFC BIT(9)
100#define I2S_IFCR_TSERFC BIT(10)
101#define I2S_IFCR_SUSPC BIT(11)
102
103#define I2S_IFCR_MASK GENMASK(11, 3)
104
105/* Bit definition for SPI_I2SCGFR register */
106#define I2S_CGFR_I2SMOD BIT(0)
107
108#define I2S_CGFR_I2SCFG_SHIFT 1
109#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
110#define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
111
112#define I2S_CGFR_I2SSTD_SHIFT 4
113#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
114#define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
115
116#define I2S_CGFR_PCMSYNC BIT(7)
117
118#define I2S_CGFR_DATLEN_SHIFT 8
119#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
120#define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
121
122#define I2S_CGFR_CHLEN_SHIFT 10
123#define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
124#define I2S_CGFR_CKPOL BIT(11)
125#define I2S_CGFR_FIXCH BIT(12)
126#define I2S_CGFR_WSINV BIT(13)
127#define I2S_CGFR_DATFMT BIT(14)
128
129#define I2S_CGFR_I2SDIV_SHIFT 16
130#define I2S_CGFR_I2SDIV_BIT_H 23
131#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
132 I2S_CGFR_I2SDIV_SHIFT)
133#define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
134#define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
135 I2S_CGFR_I2SDIV_SHIFT)) - 1)
136
137#define I2S_CGFR_ODD_SHIFT 24
138#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
139#define I2S_CGFR_MCKOE BIT(25)
140
141/* Registers below apply to I2S version 1.1 and more */
142
143/* Bit definition for SPI_HWCFGR register */
144#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
145
146/* Bit definition for SPI_VERR register */
147#define I2S_VERR_MIN_MASK GENMASK(3, 0)
148#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
149
150/* Bit definition for SPI_IPIDR register */
151#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
152
153/* Bit definition for SPI_SIDR register */
154#define I2S_SIDR_ID_MASK GENMASK(31, 0)
155
156#define I2S_IPIDR_NUMBER 0x00130022
157
158enum i2s_master_mode {
159 I2S_MS_NOT_SET,
160 I2S_MS_MASTER,
161 I2S_MS_SLAVE,
162};
163
164enum i2s_mode {
165 I2S_I2SMOD_TX_SLAVE,
166 I2S_I2SMOD_RX_SLAVE,
167 I2S_I2SMOD_TX_MASTER,
168 I2S_I2SMOD_RX_MASTER,
169 I2S_I2SMOD_FD_SLAVE,
170 I2S_I2SMOD_FD_MASTER,
171};
172
173enum i2s_fifo_th {
174 I2S_FIFO_TH_NONE,
175 I2S_FIFO_TH_ONE_QUARTER,
176 I2S_FIFO_TH_HALF,
177 I2S_FIFO_TH_THREE_QUARTER,
178 I2S_FIFO_TH_FULL,
179};
180
181enum i2s_std {
182 I2S_STD_I2S,
183 I2S_STD_LEFT_J,
184 I2S_STD_RIGHT_J,
185 I2S_STD_DSP,
186};
187
188enum i2s_datlen {
189 I2S_I2SMOD_DATLEN_16,
190 I2S_I2SMOD_DATLEN_24,
191 I2S_I2SMOD_DATLEN_32,
192};
193
194#define STM32_I2S_FIFO_SIZE 16
195
196#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
197#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
198
199/**
200 * struct stm32_i2s_data - private data of I2S
201 * @regmap_conf: I2S register map configuration pointer
202 * @regmap: I2S register map pointer
203 * @pdev: device data pointer
204 * @dai_drv: DAI driver pointer
205 * @dma_data_tx: dma configuration data for tx channel
206 * @dma_data_rx: dma configuration data for tx channel
207 * @substream: PCM substream data pointer
208 * @i2sclk: kernel clock feeding the I2S clock generator
209 * @pclk: peripheral clock driving bus interface
210 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
211 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
212 * @base: mmio register base virtual address
213 * @phys_addr: I2S registers physical base address
214 * @lock_fd: lock to manage race conditions in full duplex mode
215 * @irq_lock: prevent race condition with IRQ
216 * @mclk_rate: master clock frequency (Hz)
217 * @fmt: DAI protocol
218 * @refcount: keep count of opened streams on I2S
219 * @ms_flg: master mode flag.
220 */
221struct stm32_i2s_data {
222 const struct regmap_config *regmap_conf;
223 struct regmap *regmap;
224 struct platform_device *pdev;
225 struct snd_soc_dai_driver *dai_drv;
226 struct snd_dmaengine_dai_dma_data dma_data_tx;
227 struct snd_dmaengine_dai_dma_data dma_data_rx;
228 struct snd_pcm_substream *substream;
229 struct clk *i2sclk;
230 struct clk *pclk;
231 struct clk *x8kclk;
232 struct clk *x11kclk;
233 void __iomem *base;
234 dma_addr_t phys_addr;
235 spinlock_t lock_fd; /* Manage race conditions for full duplex */
236 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
237 unsigned int mclk_rate;
238 unsigned int fmt;
239 int refcount;
240 int ms_flg;
241};
242
243static irqreturn_t stm32_i2s_isr(int irq, void *devid)
244{
245 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
246 struct platform_device *pdev = i2s->pdev;
247 u32 sr, ier;
248 unsigned long flags;
249 int err = 0;
250
251 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
252 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
253
254 flags = sr & ier;
255 if (!flags) {
256 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
257 sr, ier);
258 return IRQ_NONE;
259 }
260
261 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
262 I2S_IFCR_MASK, flags);
263
264 if (flags & I2S_SR_OVR) {
265 dev_dbg(&pdev->dev, "Overrun\n");
266 err = 1;
267 }
268
269 if (flags & I2S_SR_UDR) {
270 dev_dbg(&pdev->dev, "Underrun\n");
271 err = 1;
272 }
273
274 if (flags & I2S_SR_TIFRE)
275 dev_dbg(&pdev->dev, "Frame error\n");
276
277 spin_lock(&i2s->irq_lock);
278 if (err && i2s->substream)
279 snd_pcm_stop_xrun(i2s->substream);
280 spin_unlock(&i2s->irq_lock);
281
282 return IRQ_HANDLED;
283}
284
285static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
286{
287 switch (reg) {
288 case STM32_I2S_CR1_REG:
289 case STM32_I2S_CFG1_REG:
290 case STM32_I2S_CFG2_REG:
291 case STM32_I2S_IER_REG:
292 case STM32_I2S_SR_REG:
293 case STM32_I2S_RXDR_REG:
294 case STM32_I2S_CGFR_REG:
295 case STM32_I2S_HWCFGR_REG:
296 case STM32_I2S_VERR_REG:
297 case STM32_I2S_IPIDR_REG:
298 case STM32_I2S_SIDR_REG:
299 return true;
300 default:
301 return false;
302 }
303}
304
305static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
306{
307 switch (reg) {
308 case STM32_I2S_SR_REG:
309 case STM32_I2S_RXDR_REG:
310 return true;
311 default:
312 return false;
313 }
314}
315
316static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
317{
318 switch (reg) {
319 case STM32_I2S_CR1_REG:
320 case STM32_I2S_CFG1_REG:
321 case STM32_I2S_CFG2_REG:
322 case STM32_I2S_IER_REG:
323 case STM32_I2S_IFCR_REG:
324 case STM32_I2S_TXDR_REG:
325 case STM32_I2S_CGFR_REG:
326 return true;
327 default:
328 return false;
329 }
330}
331
332static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
333{
334 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
335 u32 cgfr;
336 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
337 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
338
339 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
340
341 /*
342 * winv = 0 : default behavior (high/low) for all standards
343 * ckpol = 0 for all standards.
344 */
345 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
346 case SND_SOC_DAIFMT_I2S:
347 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
348 break;
349 case SND_SOC_DAIFMT_MSB:
350 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
351 break;
352 case SND_SOC_DAIFMT_LSB:
353 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
354 break;
355 case SND_SOC_DAIFMT_DSP_A:
356 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
357 break;
358 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
359 default:
360 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
361 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
362 return -EINVAL;
363 }
364
365 /* DAI clock strobing */
366 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
367 case SND_SOC_DAIFMT_NB_NF:
368 break;
369 case SND_SOC_DAIFMT_IB_NF:
370 cgfr |= I2S_CGFR_CKPOL;
371 break;
372 case SND_SOC_DAIFMT_NB_IF:
373 cgfr |= I2S_CGFR_WSINV;
374 break;
375 case SND_SOC_DAIFMT_IB_IF:
376 cgfr |= I2S_CGFR_CKPOL;
377 cgfr |= I2S_CGFR_WSINV;
378 break;
379 default:
380 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
381 fmt & SND_SOC_DAIFMT_INV_MASK);
382 return -EINVAL;
383 }
384
385 /* DAI clock master masks */
386 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
387 case SND_SOC_DAIFMT_CBM_CFM:
388 i2s->ms_flg = I2S_MS_SLAVE;
389 break;
390 case SND_SOC_DAIFMT_CBS_CFS:
391 i2s->ms_flg = I2S_MS_MASTER;
392 break;
393 default:
394 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
395 fmt & SND_SOC_DAIFMT_MASTER_MASK);
396 return -EINVAL;
397 }
398
399 i2s->fmt = fmt;
400 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
401 cgfr_mask, cgfr);
402}
403
404static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
405 int clk_id, unsigned int freq, int dir)
406{
407 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
408
409 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
410
411 if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
412 i2s->mclk_rate = freq;
413
414 /* Enable master clock if master mode and mclk-fs are set */
415 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
416 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
417 }
418
419 return 0;
420}
421
422static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
423 struct snd_pcm_hw_params *params)
424{
425 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
426 unsigned long i2s_clock_rate;
427 unsigned int tmp, div, real_div, nb_bits, frame_len;
428 unsigned int rate = params_rate(params);
429 int ret;
430 u32 cgfr, cgfr_mask;
431 bool odd;
432
433 if (!(rate % 11025))
434 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
435 else
436 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
437 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
438
439 /*
440 * mckl = mclk_ratio x ws
441 * i2s mode : mclk_ratio = 256
442 * dsp mode : mclk_ratio = 128
443 *
444 * mclk on
445 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
446 * dsp mode : div = i2s_clk / (mclk_ratio * ws)
447 * mclk off
448 * i2s mode : div = i2s_clk / (nb_bits x ws)
449 * dsp mode : div = i2s_clk / (nb_bits x ws)
450 */
451 if (i2s->mclk_rate) {
452 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
453 } else {
454 frame_len = 32;
455 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
456 SND_SOC_DAIFMT_DSP_A)
457 frame_len = 16;
458
459 /* master clock not enabled */
460 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
461 if (ret < 0)
462 return ret;
463
464 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
465 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
466 }
467
468 /* Check the parity of the divider */
469 odd = tmp & 0x1;
470
471 /* Compute the div prescaler */
472 div = tmp >> 1;
473
474 cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
475 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
476
477 real_div = ((2 * div) + odd);
478 dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
479 i2s_clock_rate, rate);
480 dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
481 div, odd, real_div);
482
483 if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
484 dev_err(cpu_dai->dev, "Wrong divider setting\n");
485 return -EINVAL;
486 }
487
488 if (!div && !odd)
489 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
490
491 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
492 cgfr_mask, cgfr);
493 if (ret < 0)
494 return ret;
495
496 /* Set bitclock and frameclock to their inactive state */
497 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
498 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
499}
500
501static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
502 struct snd_pcm_hw_params *params,
503 struct snd_pcm_substream *substream)
504{
505 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
506 int format = params_width(params);
507 u32 cfgr, cfgr_mask, cfg1;
508 unsigned int fthlv;
509 int ret;
510
511 switch (format) {
512 case 16:
513 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
514 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
515 break;
516 case 32:
517 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
518 I2S_CGFR_CHLEN;
519 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
520 break;
521 default:
522 dev_err(cpu_dai->dev, "Unexpected format %d", format);
523 return -EINVAL;
524 }
525
526 if (STM32_I2S_IS_SLAVE(i2s)) {
527 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
528
529 /* As data length is either 16 or 32 bits, fixch always set */
530 cfgr |= I2S_CGFR_FIXCH;
531 cfgr_mask |= I2S_CGFR_FIXCH;
532 } else {
533 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
534 }
535 cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
536
537 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
538 cfgr_mask, cfgr);
539 if (ret < 0)
540 return ret;
541
542 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
543 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
544
545 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
546 I2S_CFG1_FTHVL_MASK, cfg1);
547}
548
549static int stm32_i2s_startup(struct snd_pcm_substream *substream,
550 struct snd_soc_dai *cpu_dai)
551{
552 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
553 unsigned long flags;
554 int ret;
555
556 spin_lock_irqsave(&i2s->irq_lock, flags);
557 i2s->substream = substream;
558 spin_unlock_irqrestore(&i2s->irq_lock, flags);
559
560 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
561 snd_pcm_hw_constraint_single(substream->runtime,
562 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
563
564 ret = clk_prepare_enable(i2s->i2sclk);
565 if (ret < 0) {
566 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
567 return ret;
568 }
569
570 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
571 I2S_IFCR_MASK, I2S_IFCR_MASK);
572}
573
574static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
575 struct snd_pcm_hw_params *params,
576 struct snd_soc_dai *cpu_dai)
577{
578 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
579 int ret;
580
581 ret = stm32_i2s_configure(cpu_dai, params, substream);
582 if (ret < 0) {
583 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
584 return ret;
585 }
586
587 if (STM32_I2S_IS_MASTER(i2s))
588 ret = stm32_i2s_configure_clock(cpu_dai, params);
589
590 return ret;
591}
592
593static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
594 struct snd_soc_dai *cpu_dai)
595{
596 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
597 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
598 u32 cfg1_mask, ier;
599 int ret;
600
601 switch (cmd) {
602 case SNDRV_PCM_TRIGGER_START:
603 case SNDRV_PCM_TRIGGER_RESUME:
604 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
605 /* Enable i2s */
606 dev_dbg(cpu_dai->dev, "start I2S %s\n",
607 playback_flg ? "playback" : "capture");
608
609 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
610 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
611 cfg1_mask, cfg1_mask);
612
613 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
614 I2S_CR1_SPE, I2S_CR1_SPE);
615 if (ret < 0) {
616 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
617 return ret;
618 }
619
620 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
621 I2S_CR1_CSTART, I2S_CR1_CSTART);
622 if (ret < 0) {
623 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
624 return ret;
625 }
626
627 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
628 I2S_IFCR_MASK, I2S_IFCR_MASK);
629
630 spin_lock(&i2s->lock_fd);
631 i2s->refcount++;
632 if (playback_flg) {
633 ier = I2S_IER_UDRIE;
634 } else {
635 ier = I2S_IER_OVRIE;
636
637 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
638 /* dummy write to gate bus clocks */
639 regmap_write(i2s->regmap,
640 STM32_I2S_TXDR_REG, 0);
641 }
642 spin_unlock(&i2s->lock_fd);
643
644 if (STM32_I2S_IS_SLAVE(i2s))
645 ier |= I2S_IER_TIFREIE;
646
647 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
648 break;
649 case SNDRV_PCM_TRIGGER_STOP:
650 case SNDRV_PCM_TRIGGER_SUSPEND:
651 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
652 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
653 playback_flg ? "playback" : "capture");
654
655 if (playback_flg)
656 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
657 I2S_IER_UDRIE,
658 (unsigned int)~I2S_IER_UDRIE);
659 else
660 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
661 I2S_IER_OVRIE,
662 (unsigned int)~I2S_IER_OVRIE);
663
664 spin_lock(&i2s->lock_fd);
665 i2s->refcount--;
666 if (i2s->refcount) {
667 spin_unlock(&i2s->lock_fd);
668 break;
669 }
670
671 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
672 I2S_CR1_SPE, 0);
673 if (ret < 0) {
674 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
675 spin_unlock(&i2s->lock_fd);
676 return ret;
677 }
678 spin_unlock(&i2s->lock_fd);
679
680 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
681 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
682 cfg1_mask, 0);
683 break;
684 default:
685 return -EINVAL;
686 }
687
688 return 0;
689}
690
691static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
692 struct snd_soc_dai *cpu_dai)
693{
694 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
695 unsigned long flags;
696
697 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
698 I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
699
700 clk_disable_unprepare(i2s->i2sclk);
701
702 spin_lock_irqsave(&i2s->irq_lock, flags);
703 i2s->substream = NULL;
704 spin_unlock_irqrestore(&i2s->irq_lock, flags);
705}
706
707static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
708{
709 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
710 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
711 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
712
713 /* Buswidth will be set by framework */
714 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
715 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
716 dma_data_tx->maxburst = 1;
717 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
718 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
719 dma_data_rx->maxburst = 1;
720
721 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
722
723 return 0;
724}
725
726static const struct regmap_config stm32_h7_i2s_regmap_conf = {
727 .reg_bits = 32,
728 .reg_stride = 4,
729 .val_bits = 32,
730 .max_register = STM32_I2S_SIDR_REG,
731 .readable_reg = stm32_i2s_readable_reg,
732 .volatile_reg = stm32_i2s_volatile_reg,
733 .writeable_reg = stm32_i2s_writeable_reg,
734 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
735 .fast_io = true,
736 .cache_type = REGCACHE_FLAT,
737};
738
739static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
740 .set_sysclk = stm32_i2s_set_sysclk,
741 .set_fmt = stm32_i2s_set_dai_fmt,
742 .startup = stm32_i2s_startup,
743 .hw_params = stm32_i2s_hw_params,
744 .trigger = stm32_i2s_trigger,
745 .shutdown = stm32_i2s_shutdown,
746};
747
748static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
749 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
750 .buffer_bytes_max = 8 * PAGE_SIZE,
751 .period_bytes_min = 1024,
752 .period_bytes_max = 4 * PAGE_SIZE,
753 .periods_min = 2,
754 .periods_max = 8,
755};
756
757static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
758 .pcm_hardware = &stm32_i2s_pcm_hw,
759 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
760 .prealloc_buffer_size = PAGE_SIZE * 8,
761};
762
763static const struct snd_soc_component_driver stm32_i2s_component = {
764 .name = "stm32-i2s",
765};
766
767static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
768 char *stream_name)
769{
770 stream->stream_name = stream_name;
771 stream->channels_min = 1;
772 stream->channels_max = 2;
773 stream->rates = SNDRV_PCM_RATE_8000_192000;
774 stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
775 SNDRV_PCM_FMTBIT_S32_LE;
776}
777
778static int stm32_i2s_dais_init(struct platform_device *pdev,
779 struct stm32_i2s_data *i2s)
780{
781 struct snd_soc_dai_driver *dai_ptr;
782
783 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
784 GFP_KERNEL);
785 if (!dai_ptr)
786 return -ENOMEM;
787
788 dai_ptr->probe = stm32_i2s_dai_probe;
789 dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
790 dai_ptr->id = 1;
791 stm32_i2s_dai_init(&dai_ptr->playback, "playback");
792 stm32_i2s_dai_init(&dai_ptr->capture, "capture");
793 i2s->dai_drv = dai_ptr;
794
795 return 0;
796}
797
798static const struct of_device_id stm32_i2s_ids[] = {
799 {
800 .compatible = "st,stm32h7-i2s",
801 .data = &stm32_h7_i2s_regmap_conf
802 },
803 {},
804};
805
806static int stm32_i2s_parse_dt(struct platform_device *pdev,
807 struct stm32_i2s_data *i2s)
808{
809 struct device_node *np = pdev->dev.of_node;
810 const struct of_device_id *of_id;
811 struct reset_control *rst;
812 struct resource *res;
813 int irq, ret;
814
815 if (!np)
816 return -ENODEV;
817
818 of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
819 if (of_id)
820 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
821 else
822 return -EINVAL;
823
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 i2s->base = devm_ioremap_resource(&pdev->dev, res);
826 if (IS_ERR(i2s->base))
827 return PTR_ERR(i2s->base);
828
829 i2s->phys_addr = res->start;
830
831 /* Get clocks */
832 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
833 if (IS_ERR(i2s->pclk)) {
834 if (PTR_ERR(i2s->pclk) != -EPROBE_DEFER)
835 dev_err(&pdev->dev, "Could not get pclk: %ld\n",
836 PTR_ERR(i2s->pclk));
837 return PTR_ERR(i2s->pclk);
838 }
839
840 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
841 if (IS_ERR(i2s->i2sclk)) {
842 if (PTR_ERR(i2s->i2sclk) != -EPROBE_DEFER)
843 dev_err(&pdev->dev, "Could not get i2sclk: %ld\n",
844 PTR_ERR(i2s->i2sclk));
845 return PTR_ERR(i2s->i2sclk);
846 }
847
848 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
849 if (IS_ERR(i2s->x8kclk)) {
850 if (PTR_ERR(i2s->x8kclk) != -EPROBE_DEFER)
851 dev_err(&pdev->dev, "Could not get x8k parent clock: %ld\n",
852 PTR_ERR(i2s->x8kclk));
853 return PTR_ERR(i2s->x8kclk);
854 }
855
856 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
857 if (IS_ERR(i2s->x11kclk)) {
858 if (PTR_ERR(i2s->x11kclk) != -EPROBE_DEFER)
859 dev_err(&pdev->dev, "Could not get x11k parent clock: %ld\n",
860 PTR_ERR(i2s->x11kclk));
861 return PTR_ERR(i2s->x11kclk);
862 }
863
864 /* Get irqs */
865 irq = platform_get_irq(pdev, 0);
866 if (irq < 0)
867 return irq;
868
869 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
870 dev_name(&pdev->dev), i2s);
871 if (ret) {
872 dev_err(&pdev->dev, "irq request returned %d\n", ret);
873 return ret;
874 }
875
876 /* Reset */
877 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
878 if (IS_ERR(rst)) {
879 if (PTR_ERR(rst) != -EPROBE_DEFER)
880 dev_err(&pdev->dev, "Reset controller error %ld\n",
881 PTR_ERR(rst));
882 return PTR_ERR(rst);
883 }
884 reset_control_assert(rst);
885 udelay(2);
886 reset_control_deassert(rst);
887
888 return 0;
889}
890
891static int stm32_i2s_remove(struct platform_device *pdev)
892{
893 snd_dmaengine_pcm_unregister(&pdev->dev);
894 snd_soc_unregister_component(&pdev->dev);
895
896 return 0;
897}
898
899static int stm32_i2s_probe(struct platform_device *pdev)
900{
901 struct stm32_i2s_data *i2s;
902 u32 val;
903 int ret;
904
905 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
906 if (!i2s)
907 return -ENOMEM;
908
909 ret = stm32_i2s_parse_dt(pdev, i2s);
910 if (ret)
911 return ret;
912
913 i2s->pdev = pdev;
914 i2s->ms_flg = I2S_MS_NOT_SET;
915 spin_lock_init(&i2s->lock_fd);
916 spin_lock_init(&i2s->irq_lock);
917 platform_set_drvdata(pdev, i2s);
918
919 ret = stm32_i2s_dais_init(pdev, i2s);
920 if (ret)
921 return ret;
922
923 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
924 i2s->base, i2s->regmap_conf);
925 if (IS_ERR(i2s->regmap)) {
926 if (PTR_ERR(i2s->regmap) != -EPROBE_DEFER)
927 dev_err(&pdev->dev, "Regmap init error %ld\n",
928 PTR_ERR(i2s->regmap));
929 return PTR_ERR(i2s->regmap);
930 }
931
932 ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
933 if (ret) {
934 if (ret != -EPROBE_DEFER)
935 dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);
936 return ret;
937 }
938
939 ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
940 i2s->dai_drv, 1);
941 if (ret) {
942 snd_dmaengine_pcm_unregister(&pdev->dev);
943 return ret;
944 }
945
946 /* Set SPI/I2S in i2s mode */
947 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
948 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
949 if (ret)
950 goto error;
951
952 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
953 if (ret)
954 goto error;
955
956 if (val == I2S_IPIDR_NUMBER) {
957 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
958 if (ret)
959 goto error;
960
961 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
962 dev_err(&pdev->dev,
963 "Device does not support i2s mode\n");
964 ret = -EPERM;
965 goto error;
966 }
967
968 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
969 if (ret)
970 goto error;
971
972 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
973 FIELD_GET(I2S_VERR_MAJ_MASK, val),
974 FIELD_GET(I2S_VERR_MIN_MASK, val));
975 }
976
977 return ret;
978
979error:
980 stm32_i2s_remove(pdev);
981
982 return ret;
983}
984
985MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
986
987#ifdef CONFIG_PM_SLEEP
988static int stm32_i2s_suspend(struct device *dev)
989{
990 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
991
992 regcache_cache_only(i2s->regmap, true);
993 regcache_mark_dirty(i2s->regmap);
994
995 return 0;
996}
997
998static int stm32_i2s_resume(struct device *dev)
999{
1000 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1001
1002 regcache_cache_only(i2s->regmap, false);
1003 return regcache_sync(i2s->regmap);
1004}
1005#endif /* CONFIG_PM_SLEEP */
1006
1007static const struct dev_pm_ops stm32_i2s_pm_ops = {
1008 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1009};
1010
1011static struct platform_driver stm32_i2s_driver = {
1012 .driver = {
1013 .name = "st,stm32-i2s",
1014 .of_match_table = stm32_i2s_ids,
1015 .pm = &stm32_i2s_pm_ops,
1016 },
1017 .probe = stm32_i2s_probe,
1018 .remove = stm32_i2s_remove,
1019};
1020
1021module_platform_driver(stm32_i2s_driver);
1022
1023MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1024MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1025MODULE_ALIAS("platform:stm32-i2s");
1026MODULE_LICENSE("GPL v2");