1// SPDX-License-Identifier: GPL-2.0-only
   2//
   3// Driver for Cadence QSPI Controller
   4//
   5// Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6// Copyright Intel Corporation (C) 2019-2020. All rights reserved.
   7// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
   8
   9#include <linux/clk.h>
  10#include <linux/completion.h>
  11#include <linux/delay.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/dmaengine.h>
  14#include <linux/err.h>
  15#include <linux/errno.h>
  16#include <linux/firmware/xlnx-zynqmp.h>
  17#include <linux/interrupt.h>
  18#include <linux/io.h>
  19#include <linux/iopoll.h>
  20#include <linux/jiffies.h>
  21#include <linux/kernel.h>
  22#include <linux/log2.h>
  23#include <linux/module.h>
 
  24#include <linux/of.h>
  25#include <linux/platform_device.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/reset.h>
  28#include <linux/sched.h>
  29#include <linux/spi/spi.h>
  30#include <linux/spi/spi-mem.h>
  31#include <linux/timer.h>
  32
  33#define CQSPI_NAME			"cadence-qspi"
  34#define CQSPI_MAX_CHIPSELECT		16
  35
  36/* Quirks */
  37#define CQSPI_NEEDS_WR_DELAY		BIT(0)
  38#define CQSPI_DISABLE_DAC_MODE		BIT(1)
  39#define CQSPI_SUPPORT_EXTERNAL_DMA	BIT(2)
  40#define CQSPI_NO_SUPPORT_WR_COMPLETION	BIT(3)
  41#define CQSPI_SLOW_SRAM		BIT(4)
  42#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR	BIT(5)
  43
  44/* Capabilities */
  45#define CQSPI_SUPPORTS_OCTAL		BIT(0)
  46
  47#define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
  48
  49enum {
  50	CLK_QSPI_APB = 0,
  51	CLK_QSPI_AHB,
  52	CLK_QSPI_NUM,
  53};
  54
  55struct cqspi_st;
  56
  57struct cqspi_flash_pdata {
  58	struct cqspi_st	*cqspi;
  59	u32		clk_rate;
  60	u32		read_delay;
  61	u32		tshsl_ns;
  62	u32		tsd2d_ns;
  63	u32		tchsh_ns;
  64	u32		tslch_ns;
 
 
 
  65	u8		cs;
  66};
  67
  68struct cqspi_st {
  69	struct platform_device	*pdev;
  70	struct spi_controller	*host;
  71	struct clk		*clk;
  72	struct clk		*clks[CLK_QSPI_NUM];
  73	unsigned int		sclk;
  74
  75	void __iomem		*iobase;
  76	void __iomem		*ahb_base;
  77	resource_size_t		ahb_size;
  78	struct completion	transfer_complete;
  79
  80	struct dma_chan		*rx_chan;
  81	struct completion	rx_dma_complete;
  82	dma_addr_t		mmap_phys_base;
  83
  84	int			current_cs;
  85	unsigned long		master_ref_clk_hz;
  86	bool			is_decoded_cs;
  87	u32			fifo_depth;
  88	u32			fifo_width;
  89	u32			num_chipselect;
  90	bool			rclk_en;
  91	u32			trigger_address;
  92	u32			wr_delay;
  93	bool			use_direct_mode;
  94	bool			use_direct_mode_wr;
  95	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  96	bool			use_dma_read;
  97	u32			pd_dev_id;
  98	bool			wr_completion;
  99	bool			slow_sram;
 100	bool			apb_ahb_hazard;
 101
 102	bool			is_jh7110; /* Flag for StarFive JH7110 SoC */
 103};
 104
 105struct cqspi_driver_platdata {
 106	u32 hwcaps_mask;
 107	u8 quirks;
 108	int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
 109				 u_char *rxbuf, loff_t from_addr, size_t n_rx);
 110	u32 (*get_dma_status)(struct cqspi_st *cqspi);
 111	int (*jh7110_clk_init)(struct platform_device *pdev,
 112			       struct cqspi_st *cqspi);
 113};
 114
 115/* Operation timeout value */
 116#define CQSPI_TIMEOUT_MS			500
 117#define CQSPI_READ_TIMEOUT_MS			10
 118
 119/* Runtime_pm autosuspend delay */
 120#define CQSPI_AUTOSUSPEND_TIMEOUT		2000
 
 
 
 121
 122#define CQSPI_DUMMY_CLKS_PER_BYTE		8
 123#define CQSPI_DUMMY_BYTES_MAX			4
 124#define CQSPI_DUMMY_CLKS_MAX			31
 125
 126#define CQSPI_STIG_DATA_LEN_MAX			8
 127
 128/* Register map */
 129#define CQSPI_REG_CONFIG			0x00
 130#define CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
 131#define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL	BIT(7)
 132#define CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
 133#define CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
 134#define CQSPI_REG_CONFIG_DMA_MASK		BIT(15)
 135#define CQSPI_REG_CONFIG_BAUD_LSB		19
 136#define CQSPI_REG_CONFIG_DTR_PROTO		BIT(24)
 137#define CQSPI_REG_CONFIG_DUAL_OPCODE		BIT(30)
 138#define CQSPI_REG_CONFIG_IDLE_LSB		31
 139#define CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
 140#define CQSPI_REG_CONFIG_BAUD_MASK		0xF
 141
 142#define CQSPI_REG_RD_INSTR			0x04
 143#define CQSPI_REG_RD_INSTR_OPCODE_LSB		0
 144#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB	8
 145#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB	12
 146#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
 147#define CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
 148#define CQSPI_REG_RD_INSTR_DUMMY_LSB		24
 149#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
 150#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
 151#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
 152#define CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
 153
 154#define CQSPI_REG_WR_INSTR			0x08
 155#define CQSPI_REG_WR_INSTR_OPCODE_LSB		0
 156#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB	12
 157#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB	16
 158
 159#define CQSPI_REG_DELAY				0x0C
 160#define CQSPI_REG_DELAY_TSLCH_LSB		0
 161#define CQSPI_REG_DELAY_TCHSH_LSB		8
 162#define CQSPI_REG_DELAY_TSD2D_LSB		16
 163#define CQSPI_REG_DELAY_TSHSL_LSB		24
 164#define CQSPI_REG_DELAY_TSLCH_MASK		0xFF
 165#define CQSPI_REG_DELAY_TCHSH_MASK		0xFF
 166#define CQSPI_REG_DELAY_TSD2D_MASK		0xFF
 167#define CQSPI_REG_DELAY_TSHSL_MASK		0xFF
 168
 169#define CQSPI_REG_READCAPTURE			0x10
 170#define CQSPI_REG_READCAPTURE_BYPASS_LSB	0
 171#define CQSPI_REG_READCAPTURE_DELAY_LSB		1
 172#define CQSPI_REG_READCAPTURE_DELAY_MASK	0xF
 173
 174#define CQSPI_REG_SIZE				0x14
 175#define CQSPI_REG_SIZE_ADDRESS_LSB		0
 176#define CQSPI_REG_SIZE_PAGE_LSB			4
 177#define CQSPI_REG_SIZE_BLOCK_LSB		16
 178#define CQSPI_REG_SIZE_ADDRESS_MASK		0xF
 179#define CQSPI_REG_SIZE_PAGE_MASK		0xFFF
 180#define CQSPI_REG_SIZE_BLOCK_MASK		0x3F
 181
 182#define CQSPI_REG_SRAMPARTITION			0x18
 183#define CQSPI_REG_INDIRECTTRIGGER		0x1C
 184
 185#define CQSPI_REG_DMA				0x20
 186#define CQSPI_REG_DMA_SINGLE_LSB		0
 187#define CQSPI_REG_DMA_BURST_LSB			8
 188#define CQSPI_REG_DMA_SINGLE_MASK		0xFF
 189#define CQSPI_REG_DMA_BURST_MASK		0xFF
 190
 191#define CQSPI_REG_REMAP				0x24
 192#define CQSPI_REG_MODE_BIT			0x28
 193
 194#define CQSPI_REG_SDRAMLEVEL			0x2C
 195#define CQSPI_REG_SDRAMLEVEL_RD_LSB		0
 196#define CQSPI_REG_SDRAMLEVEL_WR_LSB		16
 197#define CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
 198#define CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
 199
 200#define CQSPI_REG_WR_COMPLETION_CTRL		0x38
 201#define CQSPI_REG_WR_DISABLE_AUTO_POLL		BIT(14)
 202
 203#define CQSPI_REG_IRQSTATUS			0x40
 204#define CQSPI_REG_IRQMASK			0x44
 205
 206#define CQSPI_REG_INDIRECTRD			0x60
 207#define CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
 208#define CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
 209#define CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
 210
 211#define CQSPI_REG_INDIRECTRDWATERMARK		0x64
 212#define CQSPI_REG_INDIRECTRDSTARTADDR		0x68
 213#define CQSPI_REG_INDIRECTRDBYTES		0x6C
 214
 215#define CQSPI_REG_CMDCTRL			0x90
 216#define CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
 217#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
 218#define CQSPI_REG_CMDCTRL_DUMMY_LSB		7
 219#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
 220#define CQSPI_REG_CMDCTRL_WR_EN_LSB		15
 221#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB		16
 222#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB		19
 223#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
 224#define CQSPI_REG_CMDCTRL_RD_EN_LSB		23
 225#define CQSPI_REG_CMDCTRL_OPCODE_LSB		24
 226#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
 227#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
 228#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
 229#define CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
 230
 231#define CQSPI_REG_INDIRECTWR			0x70
 232#define CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
 233#define CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
 234#define CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
 235
 236#define CQSPI_REG_INDIRECTWRWATERMARK		0x74
 237#define CQSPI_REG_INDIRECTWRSTARTADDR		0x78
 238#define CQSPI_REG_INDIRECTWRBYTES		0x7C
 239
 240#define CQSPI_REG_INDTRIG_ADDRRANGE		0x80
 241
 242#define CQSPI_REG_CMDADDRESS			0x94
 243#define CQSPI_REG_CMDREADDATALOWER		0xA0
 244#define CQSPI_REG_CMDREADDATAUPPER		0xA4
 245#define CQSPI_REG_CMDWRITEDATALOWER		0xA8
 246#define CQSPI_REG_CMDWRITEDATAUPPER		0xAC
 247
 248#define CQSPI_REG_POLLING_STATUS		0xB0
 249#define CQSPI_REG_POLLING_STATUS_DUMMY_LSB	16
 250
 251#define CQSPI_REG_OP_EXT_LOWER			0xE0
 252#define CQSPI_REG_OP_EXT_READ_LSB		24
 253#define CQSPI_REG_OP_EXT_WRITE_LSB		16
 254#define CQSPI_REG_OP_EXT_STIG_LSB		0
 255
 256#define CQSPI_REG_VERSAL_DMA_SRC_ADDR		0x1000
 257
 258#define CQSPI_REG_VERSAL_DMA_DST_ADDR		0x1800
 259#define CQSPI_REG_VERSAL_DMA_DST_SIZE		0x1804
 260
 261#define CQSPI_REG_VERSAL_DMA_DST_CTRL		0x180C
 262
 263#define CQSPI_REG_VERSAL_DMA_DST_I_STS		0x1814
 264#define CQSPI_REG_VERSAL_DMA_DST_I_EN		0x1818
 265#define CQSPI_REG_VERSAL_DMA_DST_I_DIS		0x181C
 266#define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK	BIT(1)
 267
 268#define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB	0x1828
 269
 270#define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL	0xF43FFA00
 271#define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL	0x6
 272
 273/* Interrupt status bits */
 274#define CQSPI_REG_IRQ_MODE_ERR			BIT(0)
 275#define CQSPI_REG_IRQ_UNDERFLOW			BIT(1)
 276#define CQSPI_REG_IRQ_IND_COMP			BIT(2)
 277#define CQSPI_REG_IRQ_IND_RD_REJECT		BIT(3)
 278#define CQSPI_REG_IRQ_WR_PROTECTED_ERR		BIT(4)
 279#define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR		BIT(5)
 280#define CQSPI_REG_IRQ_WATERMARK			BIT(6)
 281#define CQSPI_REG_IRQ_IND_SRAM_FULL		BIT(12)
 282
 283#define CQSPI_IRQ_MASK_RD		(CQSPI_REG_IRQ_WATERMARK	| \
 284					 CQSPI_REG_IRQ_IND_SRAM_FULL	| \
 285					 CQSPI_REG_IRQ_IND_COMP)
 286
 287#define CQSPI_IRQ_MASK_WR		(CQSPI_REG_IRQ_IND_COMP		| \
 288					 CQSPI_REG_IRQ_WATERMARK	| \
 289					 CQSPI_REG_IRQ_UNDERFLOW)
 290
 291#define CQSPI_IRQ_STATUS_MASK		0x1FFFF
 292#define CQSPI_DMA_UNALIGN		0x3
 293
 294#define CQSPI_REG_VERSAL_DMA_VAL		0x602
 295
 296static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 297{
 298	u32 val;
 299
 300	return readl_relaxed_poll_timeout(reg, val,
 301					  (((clr ? ~val : val) & mask) == mask),
 302					  10, CQSPI_TIMEOUT_MS * 1000);
 303}
 304
 305static bool cqspi_is_idle(struct cqspi_st *cqspi)
 306{
 307	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 308
 309	return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 310}
 311
 312static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 313{
 314	u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 315
 316	reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 317	return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 318}
 319
 320static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
 321{
 322	u32 dma_status;
 323
 324	dma_status = readl(cqspi->iobase +
 325					   CQSPI_REG_VERSAL_DMA_DST_I_STS);
 326	writel(dma_status, cqspi->iobase +
 327		   CQSPI_REG_VERSAL_DMA_DST_I_STS);
 328
 329	return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
 330}
 331
 332static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 333{
 334	struct cqspi_st *cqspi = dev;
 335	unsigned int irq_status;
 336	struct device *device = &cqspi->pdev->dev;
 337	const struct cqspi_driver_platdata *ddata;
 338
 339	ddata = of_device_get_match_data(device);
 340
 341	/* Read interrupt status */
 342	irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 343
 344	/* Clear interrupt */
 345	writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 346
 347	if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
 348		if (ddata->get_dma_status(cqspi)) {
 349			complete(&cqspi->transfer_complete);
 350			return IRQ_HANDLED;
 351		}
 352	}
 353
 354	else if (!cqspi->slow_sram)
 355		irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 356	else
 357		irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
 358
 359	if (irq_status)
 360		complete(&cqspi->transfer_complete);
 361
 362	return IRQ_HANDLED;
 363}
 364
 365static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op)
 366{
 367	u32 rdreg = 0;
 368
 369	rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 370	rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 371	rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 372
 373	return rdreg;
 374}
 375
 376static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
 377{
 378	unsigned int dummy_clk;
 379
 380	if (!op->dummy.nbytes)
 381		return 0;
 382
 383	dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 384	if (op->cmd.dtr)
 385		dummy_clk /= 2;
 386
 387	return dummy_clk;
 388}
 389
 390static int cqspi_wait_idle(struct cqspi_st *cqspi)
 391{
 392	const unsigned int poll_idle_retry = 3;
 393	unsigned int count = 0;
 394	unsigned long timeout;
 395
 396	timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 397	while (1) {
 398		/*
 399		 * Read few times in succession to ensure the controller
 400		 * is indeed idle, that is, the bit does not transition
 401		 * low again.
 402		 */
 403		if (cqspi_is_idle(cqspi))
 404			count++;
 405		else
 406			count = 0;
 407
 408		if (count >= poll_idle_retry)
 409			return 0;
 410
 411		if (time_after(jiffies, timeout)) {
 412			/* Timeout, in busy mode. */
 413			dev_err(&cqspi->pdev->dev,
 414				"QSPI is still busy after %dms timeout.\n",
 415				CQSPI_TIMEOUT_MS);
 416			return -ETIMEDOUT;
 417		}
 418
 419		cpu_relax();
 420	}
 421}
 422
 423static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 424{
 425	void __iomem *reg_base = cqspi->iobase;
 426	int ret;
 427
 428	/* Write the CMDCTRL without start execution. */
 429	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 430	/* Start execute */
 431	reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 432	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 433
 434	/* Polling for completion. */
 435	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 436				 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 437	if (ret) {
 438		dev_err(&cqspi->pdev->dev,
 439			"Flash command execution timed out.\n");
 440		return ret;
 441	}
 442
 443	/* Polling QSPI idle status. */
 444	return cqspi_wait_idle(cqspi);
 445}
 446
 447static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
 448				  const struct spi_mem_op *op,
 449				  unsigned int shift)
 450{
 451	struct cqspi_st *cqspi = f_pdata->cqspi;
 452	void __iomem *reg_base = cqspi->iobase;
 453	unsigned int reg;
 454	u8 ext;
 455
 456	if (op->cmd.nbytes != 2)
 457		return -EINVAL;
 458
 459	/* Opcode extension is the LSB. */
 460	ext = op->cmd.opcode & 0xff;
 461
 462	reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
 463	reg &= ~(0xff << shift);
 464	reg |= ext << shift;
 465	writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
 466
 467	return 0;
 468}
 469
 470static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
 471			    const struct spi_mem_op *op, unsigned int shift)
 472{
 473	struct cqspi_st *cqspi = f_pdata->cqspi;
 474	void __iomem *reg_base = cqspi->iobase;
 475	unsigned int reg;
 476	int ret;
 477
 478	reg = readl(reg_base + CQSPI_REG_CONFIG);
 479
 480	/*
 481	 * We enable dual byte opcode here. The callers have to set up the
 482	 * extension opcode based on which type of operation it is.
 483	 */
 484	if (op->cmd.dtr) {
 485		reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 486		reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 487
 488		/* Set up command opcode extension. */
 489		ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
 490		if (ret)
 491			return ret;
 492	} else {
 493		reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 494		reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 495	}
 496
 497	writel(reg, reg_base + CQSPI_REG_CONFIG);
 498
 499	return cqspi_wait_idle(cqspi);
 500}
 501
 502static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 503			      const struct spi_mem_op *op)
 504{
 505	struct cqspi_st *cqspi = f_pdata->cqspi;
 506	void __iomem *reg_base = cqspi->iobase;
 507	u8 *rxbuf = op->data.buf.in;
 508	u8 opcode;
 509	size_t n_rx = op->data.nbytes;
 510	unsigned int rdreg;
 511	unsigned int reg;
 512	unsigned int dummy_clk;
 513	size_t read_len;
 514	int status;
 515
 516	status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
 517	if (status)
 518		return status;
 519
 520	if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 521		dev_err(&cqspi->pdev->dev,
 522			"Invalid input argument, len %zu rxbuf 0x%p\n",
 523			n_rx, rxbuf);
 524		return -EINVAL;
 525	}
 526
 527	if (op->cmd.dtr)
 528		opcode = op->cmd.opcode >> 8;
 529	else
 530		opcode = op->cmd.opcode;
 531
 532	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 533
 534	rdreg = cqspi_calc_rdreg(op);
 535	writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 536
 537	dummy_clk = cqspi_calc_dummy(op);
 538	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 539		return -EOPNOTSUPP;
 540
 541	if (dummy_clk)
 542		reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 543		     << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 544
 545	reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 546
 547	/* 0 means 1 byte. */
 548	reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 549		<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 550
 551	/* setup ADDR BIT field */
 552	if (op->addr.nbytes) {
 553		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 554		reg |= ((op->addr.nbytes - 1) &
 555			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 556			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 557
 558		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 559	}
 560
 561	status = cqspi_exec_flash_cmd(cqspi, reg);
 562	if (status)
 563		return status;
 564
 565	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 566
 567	/* Put the read value into rx_buf */
 568	read_len = (n_rx > 4) ? 4 : n_rx;
 569	memcpy(rxbuf, &reg, read_len);
 570	rxbuf += read_len;
 571
 572	if (n_rx > 4) {
 573		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 574
 575		read_len = n_rx - read_len;
 576		memcpy(rxbuf, &reg, read_len);
 577	}
 578
 579	/* Reset CMD_CTRL Reg once command read completes */
 580	writel(0, reg_base + CQSPI_REG_CMDCTRL);
 581
 582	return 0;
 583}
 584
 585static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
 586			       const struct spi_mem_op *op)
 587{
 588	struct cqspi_st *cqspi = f_pdata->cqspi;
 589	void __iomem *reg_base = cqspi->iobase;
 590	u8 opcode;
 591	const u8 *txbuf = op->data.buf.out;
 592	size_t n_tx = op->data.nbytes;
 593	unsigned int reg;
 594	unsigned int data;
 595	size_t write_len;
 596	int ret;
 597
 598	ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
 599	if (ret)
 600		return ret;
 601
 602	if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 603		dev_err(&cqspi->pdev->dev,
 604			"Invalid input argument, cmdlen %zu txbuf 0x%p\n",
 605			n_tx, txbuf);
 606		return -EINVAL;
 607	}
 608
 609	reg = cqspi_calc_rdreg(op);
 610	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 611
 612	if (op->cmd.dtr)
 613		opcode = op->cmd.opcode >> 8;
 614	else
 615		opcode = op->cmd.opcode;
 616
 617	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 618
 619	if (op->addr.nbytes) {
 620		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 621		reg |= ((op->addr.nbytes - 1) &
 622			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 623			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 624
 625		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 626	}
 627
 628	if (n_tx) {
 629		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 630		reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 631			<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 632		data = 0;
 633		write_len = (n_tx > 4) ? 4 : n_tx;
 634		memcpy(&data, txbuf, write_len);
 635		txbuf += write_len;
 636		writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 637
 638		if (n_tx > 4) {
 639			data = 0;
 640			write_len = n_tx - 4;
 641			memcpy(&data, txbuf, write_len);
 642			writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 643		}
 644	}
 645
 646	ret = cqspi_exec_flash_cmd(cqspi, reg);
 647
 648	/* Reset CMD_CTRL Reg once command write completes */
 649	writel(0, reg_base + CQSPI_REG_CMDCTRL);
 650
 651	return ret;
 652}
 653
 654static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 655			    const struct spi_mem_op *op)
 656{
 657	struct cqspi_st *cqspi = f_pdata->cqspi;
 658	void __iomem *reg_base = cqspi->iobase;
 659	unsigned int dummy_clk = 0;
 660	unsigned int reg;
 661	int ret;
 662	u8 opcode;
 663
 664	ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB);
 665	if (ret)
 666		return ret;
 667
 668	if (op->cmd.dtr)
 669		opcode = op->cmd.opcode >> 8;
 670	else
 671		opcode = op->cmd.opcode;
 672
 673	reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 674	reg |= cqspi_calc_rdreg(op);
 675
 676	/* Setup dummy clock cycles */
 677	dummy_clk = cqspi_calc_dummy(op);
 678
 679	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 680		return -EOPNOTSUPP;
 681
 682	if (dummy_clk)
 683		reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 684		       << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 685
 686	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 687
 688	/* Set address width */
 689	reg = readl(reg_base + CQSPI_REG_SIZE);
 690	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 691	reg |= (op->addr.nbytes - 1);
 692	writel(reg, reg_base + CQSPI_REG_SIZE);
 693	return 0;
 694}
 695
 696static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 697				       u8 *rxbuf, loff_t from_addr,
 698				       const size_t n_rx)
 699{
 700	struct cqspi_st *cqspi = f_pdata->cqspi;
 701	struct device *dev = &cqspi->pdev->dev;
 702	void __iomem *reg_base = cqspi->iobase;
 703	void __iomem *ahb_base = cqspi->ahb_base;
 704	unsigned int remaining = n_rx;
 705	unsigned int mod_bytes = n_rx % 4;
 706	unsigned int bytes_to_read = 0;
 707	u8 *rxbuf_end = rxbuf + n_rx;
 708	int ret = 0;
 709
 710	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 711	writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 712
 713	/* Clear all interrupts. */
 714	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 715
 716	/*
 717	 * On SoCFPGA platform reading the SRAM is slow due to
 718	 * hardware limitation and causing read interrupt storm to CPU,
 719	 * so enabling only watermark interrupt to disable all read
 720	 * interrupts later as we want to run "bytes to read" loop with
 721	 * all the read interrupts disabled for max performance.
 722	 */
 723
 724	if (!cqspi->slow_sram)
 725		writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 726	else
 727		writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
 728
 729	reinit_completion(&cqspi->transfer_complete);
 730	writel(CQSPI_REG_INDIRECTRD_START_MASK,
 731	       reg_base + CQSPI_REG_INDIRECTRD);
 732
 733	while (remaining > 0) {
 734		if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 735						 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 736			ret = -ETIMEDOUT;
 737
 738		/*
 739		 * Disable all read interrupts until
 740		 * we are out of "bytes to read"
 741		 */
 742		if (cqspi->slow_sram)
 743			writel(0x0, reg_base + CQSPI_REG_IRQMASK);
 744
 745		bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 746
 747		if (ret && bytes_to_read == 0) {
 748			dev_err(dev, "Indirect read timeout, no bytes\n");
 749			goto failrd;
 750		}
 751
 752		while (bytes_to_read != 0) {
 753			unsigned int word_remain = round_down(remaining, 4);
 754
 755			bytes_to_read *= cqspi->fifo_width;
 756			bytes_to_read = bytes_to_read > remaining ?
 757					remaining : bytes_to_read;
 758			bytes_to_read = round_down(bytes_to_read, 4);
 759			/* Read 4 byte word chunks then single bytes */
 760			if (bytes_to_read) {
 761				ioread32_rep(ahb_base, rxbuf,
 762					     (bytes_to_read / 4));
 763			} else if (!word_remain && mod_bytes) {
 764				unsigned int temp = ioread32(ahb_base);
 765
 766				bytes_to_read = mod_bytes;
 767				memcpy(rxbuf, &temp, min((unsigned int)
 768							 (rxbuf_end - rxbuf),
 769							 bytes_to_read));
 770			}
 771			rxbuf += bytes_to_read;
 772			remaining -= bytes_to_read;
 773			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 774		}
 775
 776		if (remaining > 0) {
 777			reinit_completion(&cqspi->transfer_complete);
 778			if (cqspi->slow_sram)
 779				writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
 780		}
 781	}
 782
 783	/* Check indirect done status */
 784	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 785				 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 786	if (ret) {
 787		dev_err(dev, "Indirect read completion error (%i)\n", ret);
 788		goto failrd;
 789	}
 790
 791	/* Disable interrupt */
 792	writel(0, reg_base + CQSPI_REG_IRQMASK);
 793
 794	/* Clear indirect completion status */
 795	writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 796
 797	return 0;
 798
 799failrd:
 800	/* Disable interrupt */
 801	writel(0, reg_base + CQSPI_REG_IRQMASK);
 802
 803	/* Cancel the indirect read */
 804	writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 805	       reg_base + CQSPI_REG_INDIRECTRD);
 806	return ret;
 807}
 808
 809static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 810{
 811	void __iomem *reg_base = cqspi->iobase;
 812	unsigned int reg;
 813
 814	reg = readl(reg_base + CQSPI_REG_CONFIG);
 815
 816	if (enable)
 817		reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 818	else
 819		reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 820
 821	writel(reg, reg_base + CQSPI_REG_CONFIG);
 822}
 823
 824static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
 825					  u_char *rxbuf, loff_t from_addr,
 826					  size_t n_rx)
 827{
 828	struct cqspi_st *cqspi = f_pdata->cqspi;
 829	struct device *dev = &cqspi->pdev->dev;
 830	void __iomem *reg_base = cqspi->iobase;
 831	u32 reg, bytes_to_dma;
 832	loff_t addr = from_addr;
 833	void *buf = rxbuf;
 834	dma_addr_t dma_addr;
 835	u8 bytes_rem;
 836	int ret = 0;
 837
 838	bytes_rem = n_rx % 4;
 839	bytes_to_dma = (n_rx - bytes_rem);
 840
 841	if (!bytes_to_dma)
 842		goto nondmard;
 843
 844	ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
 845	if (ret)
 846		return ret;
 847
 848	cqspi_controller_enable(cqspi, 0);
 849
 850	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 851	reg |= CQSPI_REG_CONFIG_DMA_MASK;
 852	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 853
 854	cqspi_controller_enable(cqspi, 1);
 855
 856	dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
 857	if (dma_mapping_error(dev, dma_addr)) {
 858		dev_err(dev, "dma mapping failed\n");
 859		return -ENOMEM;
 860	}
 861
 862	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 863	writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 864	writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
 865	       reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
 866
 867	/* Clear all interrupts. */
 868	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 869
 870	/* Enable DMA done interrupt */
 871	writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
 872	       reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
 873
 874	/* Default DMA periph configuration */
 875	writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
 876
 877	/* Configure DMA Dst address */
 878	writel(lower_32_bits(dma_addr),
 879	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
 880	writel(upper_32_bits(dma_addr),
 881	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
 882
 883	/* Configure DMA Src address */
 884	writel(cqspi->trigger_address, reg_base +
 885	       CQSPI_REG_VERSAL_DMA_SRC_ADDR);
 886
 887	/* Set DMA destination size */
 888	writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
 889
 890	/* Set DMA destination control */
 891	writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
 892	       reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
 893
 894	writel(CQSPI_REG_INDIRECTRD_START_MASK,
 895	       reg_base + CQSPI_REG_INDIRECTRD);
 896
 897	reinit_completion(&cqspi->transfer_complete);
 898
 899	if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 900					 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) {
 901		ret = -ETIMEDOUT;
 902		goto failrd;
 903	}
 904
 905	/* Disable DMA interrupt */
 906	writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 907
 908	/* Clear indirect completion status */
 909	writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 910	       cqspi->iobase + CQSPI_REG_INDIRECTRD);
 911	dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 912
 913	cqspi_controller_enable(cqspi, 0);
 914
 915	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 916	reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 917	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 918
 919	cqspi_controller_enable(cqspi, 1);
 920
 921	ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
 922					PM_OSPI_MUX_SEL_LINEAR);
 923	if (ret)
 924		return ret;
 925
 926nondmard:
 927	if (bytes_rem) {
 928		addr += bytes_to_dma;
 929		buf += bytes_to_dma;
 930		ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
 931						  bytes_rem);
 932		if (ret)
 933			return ret;
 934	}
 935
 936	return 0;
 937
 938failrd:
 939	/* Disable DMA interrupt */
 940	writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 941
 942	/* Cancel the indirect read */
 943	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 944	       reg_base + CQSPI_REG_INDIRECTRD);
 945
 946	dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 947
 948	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 949	reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 950	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 951
 952	zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
 953
 954	return ret;
 955}
 956
 957static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 958			     const struct spi_mem_op *op)
 959{
 960	unsigned int reg;
 961	int ret;
 962	struct cqspi_st *cqspi = f_pdata->cqspi;
 963	void __iomem *reg_base = cqspi->iobase;
 964	u8 opcode;
 965
 966	ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB);
 967	if (ret)
 968		return ret;
 969
 970	if (op->cmd.dtr)
 971		opcode = op->cmd.opcode >> 8;
 972	else
 973		opcode = op->cmd.opcode;
 974
 975	/* Set opcode. */
 976	reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 977	reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 978	reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 979	writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 980	reg = cqspi_calc_rdreg(op);
 981	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 982
 983	/*
 984	 * SPI NAND flashes require the address of the status register to be
 985	 * passed in the Read SR command. Also, some SPI NOR flashes like the
 986	 * cypress Semper flash expect a 4-byte dummy address in the Read SR
 987	 * command in DTR mode.
 988	 *
 989	 * But this controller does not support address phase in the Read SR
 990	 * command when doing auto-HW polling. So, disable write completion
 991	 * polling on the controller's side. spinand and spi-nor will take
 992	 * care of polling the status register.
 993	 */
 994	if (cqspi->wr_completion) {
 995		reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 996		reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
 997		writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 998		/*
 999		 * DAC mode require auto polling as flash needs to be polled
1000		 * for write completion in case of bubble in SPI transaction
1001		 * due to slow CPU/DMA master.
1002		 */
1003		cqspi->use_direct_mode_wr = false;
1004	}
1005
1006	reg = readl(reg_base + CQSPI_REG_SIZE);
1007	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
1008	reg |= (op->addr.nbytes - 1);
1009	writel(reg, reg_base + CQSPI_REG_SIZE);
1010	return 0;
1011}
1012
1013static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
1014					loff_t to_addr, const u8 *txbuf,
1015					const size_t n_tx)
1016{
1017	struct cqspi_st *cqspi = f_pdata->cqspi;
1018	struct device *dev = &cqspi->pdev->dev;
1019	void __iomem *reg_base = cqspi->iobase;
1020	unsigned int remaining = n_tx;
1021	unsigned int write_bytes;
1022	int ret;
1023
1024	writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
1025	writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
1026
1027	/* Clear all interrupts. */
1028	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
1029
1030	writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
1031
1032	reinit_completion(&cqspi->transfer_complete);
1033	writel(CQSPI_REG_INDIRECTWR_START_MASK,
1034	       reg_base + CQSPI_REG_INDIRECTWR);
1035	/*
1036	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
1037	 * Controller programming sequence, couple of cycles of
1038	 * QSPI_REF_CLK delay is required for the above bit to
1039	 * be internally synchronized by the QSPI module. Provide 5
1040	 * cycles of delay.
1041	 */
1042	if (cqspi->wr_delay)
1043		ndelay(cqspi->wr_delay);
1044
1045	/*
1046	 * If a hazard exists between the APB and AHB interfaces, perform a
1047	 * dummy readback from the controller to ensure synchronization.
1048	 */
1049	if (cqspi->apb_ahb_hazard)
1050		readl(reg_base + CQSPI_REG_INDIRECTWR);
1051
1052	while (remaining > 0) {
1053		size_t write_words, mod_bytes;
1054
1055		write_bytes = remaining;
1056		write_words = write_bytes / 4;
1057		mod_bytes = write_bytes % 4;
1058		/* Write 4 bytes at a time then single bytes. */
1059		if (write_words) {
1060			iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1061			txbuf += (write_words * 4);
1062		}
1063		if (mod_bytes) {
1064			unsigned int temp = 0xFFFFFFFF;
1065
1066			memcpy(&temp, txbuf, mod_bytes);
1067			iowrite32(temp, cqspi->ahb_base);
1068			txbuf += mod_bytes;
1069		}
1070
1071		if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1072						 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
1073			dev_err(dev, "Indirect write timeout\n");
1074			ret = -ETIMEDOUT;
1075			goto failwr;
1076		}
1077
1078		remaining -= write_bytes;
1079
1080		if (remaining > 0)
1081			reinit_completion(&cqspi->transfer_complete);
1082	}
1083
1084	/* Check indirect done status */
1085	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
1086				 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
1087	if (ret) {
1088		dev_err(dev, "Indirect write completion error (%i)\n", ret);
1089		goto failwr;
1090	}
1091
1092	/* Disable interrupt. */
1093	writel(0, reg_base + CQSPI_REG_IRQMASK);
1094
1095	/* Clear indirect completion status */
1096	writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
1097
1098	cqspi_wait_idle(cqspi);
1099
1100	return 0;
1101
1102failwr:
1103	/* Disable interrupt. */
1104	writel(0, reg_base + CQSPI_REG_IRQMASK);
1105
1106	/* Cancel the indirect write */
1107	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
1108	       reg_base + CQSPI_REG_INDIRECTWR);
1109	return ret;
1110}
1111
1112static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
1113{
1114	struct cqspi_st *cqspi = f_pdata->cqspi;
1115	void __iomem *reg_base = cqspi->iobase;
1116	unsigned int chip_select = f_pdata->cs;
1117	unsigned int reg;
1118
1119	reg = readl(reg_base + CQSPI_REG_CONFIG);
1120	if (cqspi->is_decoded_cs) {
1121		reg |= CQSPI_REG_CONFIG_DECODE_MASK;
1122	} else {
1123		reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
1124
1125		/* Convert CS if without decoder.
1126		 * CS0 to 4b'1110
1127		 * CS1 to 4b'1101
1128		 * CS2 to 4b'1011
1129		 * CS3 to 4b'0111
1130		 */
1131		chip_select = 0xF & ~(1 << chip_select);
1132	}
1133
1134	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
1135		 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
1136	reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
1137	    << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
1138	writel(reg, reg_base + CQSPI_REG_CONFIG);
1139}
1140
1141static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
1142					   const unsigned int ns_val)
1143{
1144	unsigned int ticks;
1145
1146	ticks = ref_clk_hz / 1000;	/* kHz */
1147	ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
1148
1149	return ticks;
1150}
1151
1152static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
1153{
1154	struct cqspi_st *cqspi = f_pdata->cqspi;
1155	void __iomem *iobase = cqspi->iobase;
1156	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1157	unsigned int tshsl, tchsh, tslch, tsd2d;
1158	unsigned int reg;
1159	unsigned int tsclk;
1160
1161	/* calculate the number of ref ticks for one sclk tick */
1162	tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1163
1164	tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
1165	/* this particular value must be at least one sclk */
1166	if (tshsl < tsclk)
1167		tshsl = tsclk;
1168
1169	tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
1170	tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
1171	tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
1172
1173	reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
1174	       << CQSPI_REG_DELAY_TSHSL_LSB;
1175	reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
1176		<< CQSPI_REG_DELAY_TCHSH_LSB;
1177	reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
1178		<< CQSPI_REG_DELAY_TSLCH_LSB;
1179	reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
1180		<< CQSPI_REG_DELAY_TSD2D_LSB;
1181	writel(reg, iobase + CQSPI_REG_DELAY);
1182}
1183
1184static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1185{
1186	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1187	void __iomem *reg_base = cqspi->iobase;
1188	u32 reg, div;
1189
1190	/* Recalculate the baudrate divisor based on QSPI specification. */
1191	div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1192
1193	/* Maximum baud divisor */
1194	if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
1195		div = CQSPI_REG_CONFIG_BAUD_MASK;
1196		dev_warn(&cqspi->pdev->dev,
1197			"Unable to adjust clock <= %d hz. Reduced to %d hz\n",
1198			cqspi->sclk, ref_clk_hz/((div+1)*2));
1199	}
1200
1201	reg = readl(reg_base + CQSPI_REG_CONFIG);
1202	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1203	reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1204	writel(reg, reg_base + CQSPI_REG_CONFIG);
1205}
1206
1207static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1208				   const bool bypass,
1209				   const unsigned int delay)
1210{
1211	void __iomem *reg_base = cqspi->iobase;
1212	unsigned int reg;
1213
1214	reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1215
1216	if (bypass)
1217		reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1218	else
1219		reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1220
1221	reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1222		 << CQSPI_REG_READCAPTURE_DELAY_LSB);
1223
1224	reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1225		<< CQSPI_REG_READCAPTURE_DELAY_LSB;
1226
1227	writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1228}
1229
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1230static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1231			    unsigned long sclk)
1232{
1233	struct cqspi_st *cqspi = f_pdata->cqspi;
1234	int switch_cs = (cqspi->current_cs != f_pdata->cs);
1235	int switch_ck = (cqspi->sclk != sclk);
1236
1237	if (switch_cs || switch_ck)
1238		cqspi_controller_enable(cqspi, 0);
1239
1240	/* Switch chip select. */
1241	if (switch_cs) {
1242		cqspi->current_cs = f_pdata->cs;
1243		cqspi_chipselect(f_pdata);
1244	}
1245
1246	/* Setup baudrate divisor and delays */
1247	if (switch_ck) {
1248		cqspi->sclk = sclk;
1249		cqspi_config_baudrate_div(cqspi);
1250		cqspi_delay(f_pdata);
1251		cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1252				       f_pdata->read_delay);
1253	}
1254
1255	if (switch_cs || switch_ck)
1256		cqspi_controller_enable(cqspi, 1);
1257}
1258
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1259static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1260			   const struct spi_mem_op *op)
1261{
1262	struct cqspi_st *cqspi = f_pdata->cqspi;
1263	loff_t to = op->addr.val;
1264	size_t len = op->data.nbytes;
1265	const u_char *buf = op->data.buf.out;
1266	int ret;
1267
 
 
 
 
1268	ret = cqspi_write_setup(f_pdata, op);
1269	if (ret)
1270		return ret;
1271
1272	/*
1273	 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1274	 * address (all 0s) with the read status register command in DTR mode.
1275	 * But this controller does not support sending dummy address bytes to
1276	 * the flash when it is polling the write completion register in DTR
1277	 * mode. So, we can not use direct mode when in DTR mode for writing
1278	 * data.
1279	 */
1280	if (!op->cmd.dtr && cqspi->use_direct_mode &&
1281	    cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
1282		memcpy_toio(cqspi->ahb_base + to, buf, len);
1283		return cqspi_wait_idle(cqspi);
1284	}
1285
1286	return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1287}
1288
1289static void cqspi_rx_dma_callback(void *param)
1290{
1291	struct cqspi_st *cqspi = param;
1292
1293	complete(&cqspi->rx_dma_complete);
1294}
1295
1296static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1297				     u_char *buf, loff_t from, size_t len)
1298{
1299	struct cqspi_st *cqspi = f_pdata->cqspi;
1300	struct device *dev = &cqspi->pdev->dev;
1301	enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1302	dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1303	int ret = 0;
1304	struct dma_async_tx_descriptor *tx;
1305	dma_cookie_t cookie;
1306	dma_addr_t dma_dst;
1307	struct device *ddev;
1308
1309	if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1310		memcpy_fromio(buf, cqspi->ahb_base + from, len);
1311		return 0;
1312	}
1313
1314	ddev = cqspi->rx_chan->device->dev;
1315	dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1316	if (dma_mapping_error(ddev, dma_dst)) {
1317		dev_err(dev, "dma mapping failed\n");
1318		return -ENOMEM;
1319	}
1320	tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1321				       len, flags);
1322	if (!tx) {
1323		dev_err(dev, "device_prep_dma_memcpy error\n");
1324		ret = -EIO;
1325		goto err_unmap;
1326	}
1327
1328	tx->callback = cqspi_rx_dma_callback;
1329	tx->callback_param = cqspi;
1330	cookie = tx->tx_submit(tx);
1331	reinit_completion(&cqspi->rx_dma_complete);
1332
1333	ret = dma_submit_error(cookie);
1334	if (ret) {
1335		dev_err(dev, "dma_submit_error %d\n", cookie);
1336		ret = -EIO;
1337		goto err_unmap;
1338	}
1339
1340	dma_async_issue_pending(cqspi->rx_chan);
1341	if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1342					 msecs_to_jiffies(max_t(size_t, len, 500)))) {
1343		dmaengine_terminate_sync(cqspi->rx_chan);
1344		dev_err(dev, "DMA wait_for_completion_timeout\n");
1345		ret = -ETIMEDOUT;
1346		goto err_unmap;
1347	}
1348
1349err_unmap:
1350	dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1351
1352	return ret;
1353}
1354
1355static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1356			  const struct spi_mem_op *op)
1357{
1358	struct cqspi_st *cqspi = f_pdata->cqspi;
1359	struct device *dev = &cqspi->pdev->dev;
1360	const struct cqspi_driver_platdata *ddata;
1361	loff_t from = op->addr.val;
1362	size_t len = op->data.nbytes;
1363	u_char *buf = op->data.buf.in;
1364	u64 dma_align = (u64)(uintptr_t)buf;
1365	int ret;
1366
1367	ddata = of_device_get_match_data(dev);
 
 
1368
1369	ret = cqspi_read_setup(f_pdata, op);
1370	if (ret)
1371		return ret;
1372
1373	if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1374		return cqspi_direct_read_execute(f_pdata, buf, from, len);
1375
1376	if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1377	    virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
1378		return ddata->indirect_read_dma(f_pdata, buf, from, len);
1379
1380	return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1381}
1382
1383static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1384{
1385	struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1386	struct cqspi_flash_pdata *f_pdata;
1387
1388	f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
1389	cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1390
1391	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1392	/*
1393	 * Performing reads in DAC mode forces to read minimum 4 bytes
1394	 * which is unsupported on some flash devices during register
1395	 * reads, prefer STIG mode for such small reads.
1396	 */
1397		if (!op->addr.nbytes ||
1398		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
1399			return cqspi_command_read(f_pdata, op);
1400
1401		return cqspi_read(f_pdata, op);
1402	}
1403
1404	if (!op->addr.nbytes || !op->data.buf.out)
1405		return cqspi_command_write(f_pdata, op);
1406
1407	return cqspi_write(f_pdata, op);
1408}
1409
1410static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1411{
1412	int ret;
1413	struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1414	struct device *dev = &cqspi->pdev->dev;
1415
1416	ret = pm_runtime_resume_and_get(dev);
1417	if (ret) {
1418		dev_err(&mem->spi->dev, "resume failed with %d\n", ret);
1419		return ret;
1420	}
1421
1422	ret = cqspi_mem_process(mem, op);
1423
1424	pm_runtime_mark_last_busy(dev);
1425	pm_runtime_put_autosuspend(dev);
1426
1427	if (ret)
1428		dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1429
1430	return ret;
1431}
1432
1433static bool cqspi_supports_mem_op(struct spi_mem *mem,
1434				  const struct spi_mem_op *op)
1435{
1436	bool all_true, all_false;
1437
1438	/*
1439	 * op->dummy.dtr is required for converting nbytes into ncycles.
1440	 * Also, don't check the dtr field of the op phase having zero nbytes.
1441	 */
1442	all_true = op->cmd.dtr &&
1443		   (!op->addr.nbytes || op->addr.dtr) &&
1444		   (!op->dummy.nbytes || op->dummy.dtr) &&
1445		   (!op->data.nbytes || op->data.dtr);
1446
1447	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1448		    !op->data.dtr;
1449
1450	if (all_true) {
1451		/* Right now we only support 8-8-8 DTR mode. */
1452		if (op->cmd.nbytes && op->cmd.buswidth != 8)
1453			return false;
1454		if (op->addr.nbytes && op->addr.buswidth != 8)
1455			return false;
1456		if (op->data.nbytes && op->data.buswidth != 8)
1457			return false;
1458	} else if (!all_false) {
1459		/* Mixed DTR modes are not supported. */
1460		return false;
1461	}
1462
1463	return spi_mem_default_supports_op(mem, op);
1464}
1465
1466static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1467				    struct cqspi_flash_pdata *f_pdata,
1468				    struct device_node *np)
1469{
1470	if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1471		dev_err(&pdev->dev, "couldn't determine read-delay\n");
1472		return -ENXIO;
1473	}
1474
1475	if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1476		dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1477		return -ENXIO;
1478	}
1479
1480	if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1481		dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1482		return -ENXIO;
1483	}
1484
1485	if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1486		dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1487		return -ENXIO;
1488	}
1489
1490	if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1491		dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1492		return -ENXIO;
1493	}
1494
1495	if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1496		dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1497		return -ENXIO;
1498	}
1499
1500	return 0;
1501}
1502
1503static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1504{
1505	struct device *dev = &cqspi->pdev->dev;
1506	struct device_node *np = dev->of_node;
1507	u32 id[2];
1508
1509	cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1510
1511	if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1512		dev_err(dev, "couldn't determine fifo-depth\n");
1513		return -ENXIO;
1514	}
1515
1516	if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1517		dev_err(dev, "couldn't determine fifo-width\n");
1518		return -ENXIO;
1519	}
1520
1521	if (of_property_read_u32(np, "cdns,trigger-address",
1522				 &cqspi->trigger_address)) {
1523		dev_err(dev, "couldn't determine trigger-address\n");
1524		return -ENXIO;
1525	}
1526
1527	if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1528		cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1529
1530	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1531
1532	if (!of_property_read_u32_array(np, "power-domains", id,
1533					ARRAY_SIZE(id)))
1534		cqspi->pd_dev_id = id[1];
1535
1536	return 0;
1537}
1538
1539static void cqspi_controller_init(struct cqspi_st *cqspi)
1540{
1541	u32 reg;
1542
1543	cqspi_controller_enable(cqspi, 0);
1544
1545	/* Configure the remap address register, no remap */
1546	writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1547
1548	/* Disable all interrupts. */
1549	writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1550
1551	/* Configure the SRAM split to 1:1 . */
1552	writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1553
1554	/* Load indirect trigger address. */
1555	writel(cqspi->trigger_address,
1556	       cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1557
1558	/* Program read watermark -- 1/2 of the FIFO. */
1559	writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1560	       cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1561	/* Program write watermark -- 1/8 of the FIFO. */
1562	writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1563	       cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1564
1565	/* Disable direct access controller */
1566	if (!cqspi->use_direct_mode) {
1567		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1568		reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1569		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1570	}
1571
1572	/* Enable DMA interface */
1573	if (cqspi->use_dma_read) {
1574		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1575		reg |= CQSPI_REG_CONFIG_DMA_MASK;
1576		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1577	}
1578
1579	cqspi_controller_enable(cqspi, 1);
1580}
1581
1582static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1583{
1584	dma_cap_mask_t mask;
1585
1586	dma_cap_zero(mask);
1587	dma_cap_set(DMA_MEMCPY, mask);
1588
1589	cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1590	if (IS_ERR(cqspi->rx_chan)) {
1591		int ret = PTR_ERR(cqspi->rx_chan);
1592
 
 
1593		cqspi->rx_chan = NULL;
1594		return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1595	}
1596	init_completion(&cqspi->rx_dma_complete);
1597
1598	return 0;
1599}
1600
1601static const char *cqspi_get_name(struct spi_mem *mem)
1602{
1603	struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1604	struct device *dev = &cqspi->pdev->dev;
1605
1606	return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
1607			      spi_get_chipselect(mem->spi, 0));
1608}
1609
1610static const struct spi_controller_mem_ops cqspi_mem_ops = {
1611	.exec_op = cqspi_exec_mem_op,
1612	.get_name = cqspi_get_name,
1613	.supports_op = cqspi_supports_mem_op,
1614};
1615
1616static const struct spi_controller_mem_caps cqspi_mem_caps = {
1617	.dtr = true,
1618};
1619
1620static int cqspi_setup_flash(struct cqspi_st *cqspi)
1621{
1622	struct platform_device *pdev = cqspi->pdev;
1623	struct device *dev = &pdev->dev;
1624	struct device_node *np = dev->of_node;
1625	struct cqspi_flash_pdata *f_pdata;
1626	unsigned int cs;
1627	int ret;
1628
1629	/* Get flash device data */
1630	for_each_available_child_of_node(dev->of_node, np) {
1631		ret = of_property_read_u32(np, "reg", &cs);
1632		if (ret) {
1633			dev_err(dev, "Couldn't determine chip select.\n");
1634			of_node_put(np);
1635			return ret;
1636		}
1637
1638		if (cs >= CQSPI_MAX_CHIPSELECT) {
1639			dev_err(dev, "Chip select %d out of range.\n", cs);
1640			of_node_put(np);
1641			return -EINVAL;
1642		}
1643
1644		f_pdata = &cqspi->f_pdata[cs];
1645		f_pdata->cqspi = cqspi;
1646		f_pdata->cs = cs;
1647
1648		ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1649		if (ret) {
1650			of_node_put(np);
1651			return ret;
1652		}
1653	}
1654
1655	return 0;
1656}
1657
1658static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi)
1659{
1660	static struct clk_bulk_data qspiclk[] = {
1661		{ .id = "apb" },
1662		{ .id = "ahb" },
1663	};
1664
1665	int ret = 0;
1666
1667	ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk);
1668	if (ret) {
1669		dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__);
1670		return ret;
1671	}
1672
1673	cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;
1674	cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;
1675
1676	ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
1677	if (ret) {
1678		dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__);
1679		return ret;
1680	}
1681
1682	ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
1683	if (ret) {
1684		dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__);
1685		goto disable_apb_clk;
1686	}
1687
1688	cqspi->is_jh7110 = true;
1689
1690	return 0;
1691
1692disable_apb_clk:
1693	clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1694
1695	return ret;
1696}
1697
1698static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi)
1699{
1700	clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);
1701	clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1702}
1703static int cqspi_probe(struct platform_device *pdev)
1704{
1705	const struct cqspi_driver_platdata *ddata;
1706	struct reset_control *rstc, *rstc_ocp, *rstc_ref;
1707	struct device *dev = &pdev->dev;
1708	struct spi_controller *host;
1709	struct resource *res_ahb;
1710	struct cqspi_st *cqspi;
 
1711	int ret;
1712	int irq;
1713
1714	host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
1715	if (!host) {
1716		dev_err(&pdev->dev, "devm_spi_alloc_host failed\n");
1717		return -ENOMEM;
1718	}
1719	host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1720	host->mem_ops = &cqspi_mem_ops;
1721	host->mem_caps = &cqspi_mem_caps;
1722	host->dev.of_node = pdev->dev.of_node;
1723
1724	cqspi = spi_controller_get_devdata(host);
1725
1726	cqspi->pdev = pdev;
1727	cqspi->host = host;
1728	cqspi->is_jh7110 = false;
1729	platform_set_drvdata(pdev, cqspi);
1730
1731	/* Obtain configuration from OF. */
1732	ret = cqspi_of_get_pdata(cqspi);
1733	if (ret) {
1734		dev_err(dev, "Cannot get mandatory OF data.\n");
1735		return -ENODEV;
 
1736	}
1737
1738	/* Obtain QSPI clock. */
1739	cqspi->clk = devm_clk_get(dev, NULL);
1740	if (IS_ERR(cqspi->clk)) {
1741		dev_err(dev, "Cannot claim QSPI clock.\n");
1742		ret = PTR_ERR(cqspi->clk);
1743		return ret;
1744	}
1745
1746	/* Obtain and remap controller address. */
1747	cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
 
1748	if (IS_ERR(cqspi->iobase)) {
1749		dev_err(dev, "Cannot remap controller address.\n");
1750		ret = PTR_ERR(cqspi->iobase);
1751		return ret;
1752	}
1753
1754	/* Obtain and remap AHB address. */
1755	cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
 
1756	if (IS_ERR(cqspi->ahb_base)) {
1757		dev_err(dev, "Cannot remap AHB address.\n");
1758		ret = PTR_ERR(cqspi->ahb_base);
1759		return ret;
1760	}
1761	cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1762	cqspi->ahb_size = resource_size(res_ahb);
1763
1764	init_completion(&cqspi->transfer_complete);
1765
1766	/* Obtain IRQ line. */
1767	irq = platform_get_irq(pdev, 0);
1768	if (irq < 0)
1769		return -ENXIO;
1770
1771	ret = pm_runtime_set_active(dev);
1772	if (ret)
1773		return ret;
1774
 
 
 
 
 
 
1775
1776	ret = clk_prepare_enable(cqspi->clk);
1777	if (ret) {
1778		dev_err(dev, "Cannot enable QSPI clock.\n");
1779		goto probe_clk_failed;
1780	}
1781
1782	/* Obtain QSPI reset control */
1783	rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1784	if (IS_ERR(rstc)) {
1785		ret = PTR_ERR(rstc);
1786		dev_err(dev, "Cannot get QSPI reset.\n");
1787		goto probe_reset_failed;
1788	}
1789
1790	rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1791	if (IS_ERR(rstc_ocp)) {
1792		ret = PTR_ERR(rstc_ocp);
1793		dev_err(dev, "Cannot get QSPI OCP reset.\n");
1794		goto probe_reset_failed;
1795	}
1796
1797	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
1798		rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
1799		if (IS_ERR(rstc_ref)) {
1800			ret = PTR_ERR(rstc_ref);
1801			dev_err(dev, "Cannot get QSPI REF reset.\n");
1802			goto probe_reset_failed;
1803		}
1804		reset_control_assert(rstc_ref);
1805		reset_control_deassert(rstc_ref);
1806	}
1807
1808	reset_control_assert(rstc);
1809	reset_control_deassert(rstc);
1810
1811	reset_control_assert(rstc_ocp);
1812	reset_control_deassert(rstc_ocp);
1813
1814	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1815	host->max_speed_hz = cqspi->master_ref_clk_hz;
1816
1817	/* write completion is supported by default */
1818	cqspi->wr_completion = true;
1819
1820	ddata  = of_device_get_match_data(dev);
1821	if (ddata) {
1822		if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1823			cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1824						cqspi->master_ref_clk_hz);
1825		if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1826			host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1827		if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
1828			cqspi->use_direct_mode = true;
1829			cqspi->use_direct_mode_wr = true;
1830		}
1831		if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1832			cqspi->use_dma_read = true;
1833		if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1834			cqspi->wr_completion = false;
1835		if (ddata->quirks & CQSPI_SLOW_SRAM)
1836			cqspi->slow_sram = true;
1837		if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
1838			cqspi->apb_ahb_hazard = true;
1839
1840		if (ddata->jh7110_clk_init) {
1841			ret = cqspi_jh7110_clk_init(pdev, cqspi);
1842			if (ret)
1843				goto probe_reset_failed;
1844		}
1845
1846		if (of_device_is_compatible(pdev->dev.of_node,
1847					    "xlnx,versal-ospi-1.0")) {
1848			ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1849			if (ret)
1850				goto probe_reset_failed;
1851		}
1852	}
1853
1854	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1855			       pdev->name, cqspi);
1856	if (ret) {
1857		dev_err(dev, "Cannot request IRQ.\n");
1858		goto probe_reset_failed;
1859	}
1860
1861	cqspi_wait_idle(cqspi);
1862	cqspi_controller_init(cqspi);
1863	cqspi->current_cs = -1;
1864	cqspi->sclk = 0;
1865
1866	host->num_chipselect = cqspi->num_chipselect;
1867
1868	ret = cqspi_setup_flash(cqspi);
1869	if (ret) {
1870		dev_err(dev, "failed to setup flash parameters %d\n", ret);
1871		goto probe_setup_failed;
1872	}
1873
1874	if (cqspi->use_direct_mode) {
1875		ret = cqspi_request_mmap_dma(cqspi);
1876		if (ret == -EPROBE_DEFER)
1877			goto probe_setup_failed;
1878	}
1879
1880	ret = devm_pm_runtime_enable(dev);
1881	if (ret) {
1882		if (cqspi->rx_chan)
1883			dma_release_channel(cqspi->rx_chan);
1884		goto probe_setup_failed;
1885	}
1886
1887	pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT);
1888	pm_runtime_use_autosuspend(dev);
1889	pm_runtime_get_noresume(dev);
1890
1891	ret = spi_register_controller(host);
1892	if (ret) {
1893		dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1894		goto probe_setup_failed;
1895	}
1896
1897	pm_runtime_mark_last_busy(dev);
1898	pm_runtime_put_autosuspend(dev);
1899
1900	return 0;
1901probe_setup_failed:
1902	cqspi_controller_enable(cqspi, 0);
1903probe_reset_failed:
1904	if (cqspi->is_jh7110)
1905		cqspi_jh7110_disable_clk(pdev, cqspi);
1906	clk_disable_unprepare(cqspi->clk);
1907probe_clk_failed:
 
 
 
 
1908	return ret;
1909}
1910
1911static void cqspi_remove(struct platform_device *pdev)
1912{
1913	struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1914
1915	spi_unregister_controller(cqspi->host);
1916	cqspi_controller_enable(cqspi, 0);
1917
1918	if (cqspi->rx_chan)
1919		dma_release_channel(cqspi->rx_chan);
1920
1921	clk_disable_unprepare(cqspi->clk);
1922
1923	if (cqspi->is_jh7110)
1924		cqspi_jh7110_disable_clk(pdev, cqspi);
1925
1926	pm_runtime_put_sync(&pdev->dev);
1927	pm_runtime_disable(&pdev->dev);
1928}
1929
1930static int cqspi_runtime_suspend(struct device *dev)
1931{
1932	struct cqspi_st *cqspi = dev_get_drvdata(dev);
1933
1934	cqspi_controller_enable(cqspi, 0);
1935	clk_disable_unprepare(cqspi->clk);
1936	return 0;
1937}
1938
1939static int cqspi_runtime_resume(struct device *dev)
1940{
1941	struct cqspi_st *cqspi = dev_get_drvdata(dev);
1942
1943	clk_prepare_enable(cqspi->clk);
1944	cqspi_wait_idle(cqspi);
1945	cqspi_controller_init(cqspi);
1946
1947	cqspi->current_cs = -1;
1948	cqspi->sclk = 0;
1949	return 0;
1950}
1951
 
1952static int cqspi_suspend(struct device *dev)
1953{
1954	struct cqspi_st *cqspi = dev_get_drvdata(dev);
1955
1956	return spi_controller_suspend(cqspi->host);
 
1957}
1958
1959static int cqspi_resume(struct device *dev)
1960{
1961	struct cqspi_st *cqspi = dev_get_drvdata(dev);
1962
1963	return spi_controller_resume(cqspi->host);
 
1964}
1965
1966static const struct dev_pm_ops cqspi_dev_pm_ops = {
1967	RUNTIME_PM_OPS(cqspi_runtime_suspend, cqspi_runtime_resume, NULL)
1968	SYSTEM_SLEEP_PM_OPS(cqspi_suspend, cqspi_resume)
1969};
1970
 
 
 
 
 
1971static const struct cqspi_driver_platdata cdns_qspi = {
1972	.quirks = CQSPI_DISABLE_DAC_MODE,
1973};
1974
1975static const struct cqspi_driver_platdata k2g_qspi = {
1976	.quirks = CQSPI_NEEDS_WR_DELAY,
1977};
1978
1979static const struct cqspi_driver_platdata am654_ospi = {
1980	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1981	.quirks = CQSPI_NEEDS_WR_DELAY,
1982};
1983
1984static const struct cqspi_driver_platdata intel_lgm_qspi = {
1985	.quirks = CQSPI_DISABLE_DAC_MODE,
1986};
1987
1988static const struct cqspi_driver_platdata socfpga_qspi = {
1989	.quirks = CQSPI_DISABLE_DAC_MODE
1990			| CQSPI_NO_SUPPORT_WR_COMPLETION
1991			| CQSPI_SLOW_SRAM,
1992};
1993
1994static const struct cqspi_driver_platdata versal_ospi = {
1995	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1996	.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
1997	.indirect_read_dma = cqspi_versal_indirect_read_dma,
1998	.get_dma_status = cqspi_get_versal_dma_status,
1999};
2000
2001static const struct cqspi_driver_platdata jh7110_qspi = {
2002	.quirks = CQSPI_DISABLE_DAC_MODE,
2003	.jh7110_clk_init = cqspi_jh7110_clk_init,
2004};
2005
2006static const struct cqspi_driver_platdata pensando_cdns_qspi = {
2007	.quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
2008};
2009
2010static const struct of_device_id cqspi_dt_ids[] = {
2011	{
2012		.compatible = "cdns,qspi-nor",
2013		.data = &cdns_qspi,
2014	},
2015	{
2016		.compatible = "ti,k2g-qspi",
2017		.data = &k2g_qspi,
2018	},
2019	{
2020		.compatible = "ti,am654-ospi",
2021		.data = &am654_ospi,
2022	},
2023	{
2024		.compatible = "intel,lgm-qspi",
2025		.data = &intel_lgm_qspi,
2026	},
2027	{
2028		.compatible = "xlnx,versal-ospi-1.0",
2029		.data = &versal_ospi,
2030	},
2031	{
2032		.compatible = "intel,socfpga-qspi",
2033		.data = &socfpga_qspi,
2034	},
2035	{
2036		.compatible = "starfive,jh7110-qspi",
2037		.data = &jh7110_qspi,
2038	},
2039	{
2040		.compatible = "amd,pensando-elba-qspi",
2041		.data = &pensando_cdns_qspi,
2042	},
2043	{ /* end of table */ }
2044};
2045
2046MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
2047
2048static struct platform_driver cqspi_platform_driver = {
2049	.probe = cqspi_probe,
2050	.remove_new = cqspi_remove,
2051	.driver = {
2052		.name = CQSPI_NAME,
2053		.pm = pm_ptr(&cqspi_dev_pm_ops),
2054		.of_match_table = cqspi_dt_ids,
2055	},
2056};
2057
2058module_platform_driver(cqspi_platform_driver);
2059
2060MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
2061MODULE_LICENSE("GPL v2");
2062MODULE_ALIAS("platform:" CQSPI_NAME);
2063MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
2064MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
2065MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
2066MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
2067MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");