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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
5 * JZ4740 SoC RTC driver
6 */
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_wakeirq.h>
17#include <linux/property.h>
18#include <linux/reboot.h>
19#include <linux/rtc.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22
23#define JZ_REG_RTC_CTRL 0x00
24#define JZ_REG_RTC_SEC 0x04
25#define JZ_REG_RTC_SEC_ALARM 0x08
26#define JZ_REG_RTC_REGULATOR 0x0C
27#define JZ_REG_RTC_HIBERNATE 0x20
28#define JZ_REG_RTC_WAKEUP_FILTER 0x24
29#define JZ_REG_RTC_RESET_COUNTER 0x28
30#define JZ_REG_RTC_SCRATCHPAD 0x34
31#define JZ_REG_RTC_CKPCR 0x40
32
33/* The following are present on the jz4780 */
34#define JZ_REG_RTC_WENR 0x3C
35#define JZ_RTC_WENR_WEN BIT(31)
36
37#define JZ_RTC_CTRL_WRDY BIT(7)
38#define JZ_RTC_CTRL_1HZ BIT(6)
39#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
40#define JZ_RTC_CTRL_AF BIT(4)
41#define JZ_RTC_CTRL_AF_IRQ BIT(3)
42#define JZ_RTC_CTRL_AE BIT(2)
43#define JZ_RTC_CTRL_ENABLE BIT(0)
44
45/* Magic value to enable writes on jz4780 */
46#define JZ_RTC_WENR_MAGIC 0xA55A
47
48#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
49#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
50
51#define JZ_RTC_CKPCR_CK32PULL_DIS BIT(4)
52#define JZ_RTC_CKPCR_CK32CTL_EN (BIT(2) | BIT(1))
53
54enum jz4740_rtc_type {
55 ID_JZ4740,
56 ID_JZ4760,
57 ID_JZ4780,
58};
59
60struct jz4740_rtc {
61 void __iomem *base;
62 enum jz4740_rtc_type type;
63
64 struct rtc_device *rtc;
65
66 struct clk_hw clk32k;
67
68 spinlock_t lock;
69};
70
71static struct device *dev_for_power_off;
72
73static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
74{
75 return readl(rtc->base + reg);
76}
77
78static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
79{
80 uint32_t ctrl;
81
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl,
83 ctrl & JZ_RTC_CTRL_WRDY, 0, 1000);
84}
85
86static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
87{
88 uint32_t ctrl;
89 int ret;
90
91 ret = jz4740_rtc_wait_write_ready(rtc);
92 if (ret != 0)
93 return ret;
94
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
96
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl,
98 ctrl & JZ_RTC_WENR_WEN, 0, 1000);
99}
100
101static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
102 uint32_t val)
103{
104 int ret = 0;
105
106 if (rtc->type >= ID_JZ4760)
107 ret = jz4780_rtc_enable_write(rtc);
108 if (ret == 0)
109 ret = jz4740_rtc_wait_write_ready(rtc);
110 if (ret == 0)
111 writel(val, rtc->base + reg);
112
113 return ret;
114}
115
116static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
117 bool set)
118{
119 int ret;
120 unsigned long flags;
121 uint32_t ctrl;
122
123 spin_lock_irqsave(&rtc->lock, flags);
124
125 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
126
127 /* Don't clear interrupt flags by accident */
128 ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
129
130 if (set)
131 ctrl |= mask;
132 else
133 ctrl &= ~mask;
134
135 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
136
137 spin_unlock_irqrestore(&rtc->lock, flags);
138
139 return ret;
140}
141
142static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
143{
144 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
145 uint32_t secs, secs2;
146 int timeout = 5;
147
148 if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
149 return -EINVAL;
150
151 /* If the seconds register is read while it is updated, it can contain a
152 * bogus value. This can be avoided by making sure that two consecutive
153 * reads have the same value.
154 */
155 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
156 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
157
158 while (secs != secs2 && --timeout) {
159 secs = secs2;
160 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
161 }
162
163 if (timeout == 0)
164 return -EIO;
165
166 rtc_time64_to_tm(secs, time);
167
168 return 0;
169}
170
171static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
172{
173 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
174 int ret;
175
176 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
177 if (ret)
178 return ret;
179
180 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
181}
182
183static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
184{
185 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
186 uint32_t secs;
187 uint32_t ctrl;
188
189 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
190
191 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
192
193 alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
194 alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
195
196 rtc_time64_to_tm(secs, &alrm->time);
197
198 return 0;
199}
200
201static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
202{
203 int ret;
204 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
205 uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
206
207 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
208 if (!ret)
209 ret = jz4740_rtc_ctrl_set_bits(rtc,
210 JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
211
212 return ret;
213}
214
215static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
216{
217 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
218 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
219}
220
221static const struct rtc_class_ops jz4740_rtc_ops = {
222 .read_time = jz4740_rtc_read_time,
223 .set_time = jz4740_rtc_set_time,
224 .read_alarm = jz4740_rtc_read_alarm,
225 .set_alarm = jz4740_rtc_set_alarm,
226 .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
227};
228
229static irqreturn_t jz4740_rtc_irq(int irq, void *data)
230{
231 struct jz4740_rtc *rtc = data;
232 uint32_t ctrl;
233 unsigned long events = 0;
234
235 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
236
237 if (ctrl & JZ_RTC_CTRL_1HZ)
238 events |= (RTC_UF | RTC_IRQF);
239
240 if (ctrl & JZ_RTC_CTRL_AF)
241 events |= (RTC_AF | RTC_IRQF);
242
243 rtc_update_irq(rtc->rtc, 1, events);
244
245 jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
246
247 return IRQ_HANDLED;
248}
249
250static void jz4740_rtc_poweroff(struct device *dev)
251{
252 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
253 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
254}
255
256static void jz4740_rtc_power_off(void)
257{
258 jz4740_rtc_poweroff(dev_for_power_off);
259 kernel_halt();
260}
261
262static const struct of_device_id jz4740_rtc_of_match[] = {
263 { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
264 { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
265 { .compatible = "ingenic,jz4770-rtc", .data = (void *)ID_JZ4780 },
266 { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
267 {},
268};
269MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
270
271static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
272 struct device_node *np,
273 unsigned long rate)
274{
275 unsigned long wakeup_ticks, reset_ticks;
276 unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
277 unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
278
279 of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
280 &reset_pin_assert_time);
281 of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
282 &min_wakeup_pin_assert_time);
283
284 /*
285 * Set minimum wakeup pin assertion time: 100 ms.
286 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
287 */
288 wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
289 if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
290 wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
291 else
292 wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
293 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
294
295 /*
296 * Set reset pin low-level assertion time after wakeup: 60 ms.
297 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
298 */
299 reset_ticks = (reset_pin_assert_time * rate) / 1000;
300 if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
301 reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
302 else
303 reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
304 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
305}
306
307static int jz4740_rtc_clk32k_enable(struct clk_hw *hw)
308{
309 struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);
310
311 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR,
312 JZ_RTC_CKPCR_CK32PULL_DIS |
313 JZ_RTC_CKPCR_CK32CTL_EN);
314}
315
316static void jz4740_rtc_clk32k_disable(struct clk_hw *hw)
317{
318 struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);
319
320 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, 0);
321}
322
323static int jz4740_rtc_clk32k_is_enabled(struct clk_hw *hw)
324{
325 struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);
326 u32 ckpcr;
327
328 ckpcr = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CKPCR);
329
330 return !!(ckpcr & JZ_RTC_CKPCR_CK32CTL_EN);
331}
332
333static const struct clk_ops jz4740_rtc_clk32k_ops = {
334 .enable = jz4740_rtc_clk32k_enable,
335 .disable = jz4740_rtc_clk32k_disable,
336 .is_enabled = jz4740_rtc_clk32k_is_enabled,
337};
338
339static int jz4740_rtc_probe(struct platform_device *pdev)
340{
341 struct device *dev = &pdev->dev;
342 struct device_node *np = dev->of_node;
343 struct jz4740_rtc *rtc;
344 unsigned long rate;
345 struct clk *clk;
346 int ret, irq;
347
348 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
349 if (!rtc)
350 return -ENOMEM;
351
352 rtc->type = (uintptr_t)device_get_match_data(dev);
353
354 irq = platform_get_irq(pdev, 0);
355 if (irq < 0)
356 return irq;
357
358 rtc->base = devm_platform_ioremap_resource(pdev, 0);
359 if (IS_ERR(rtc->base))
360 return PTR_ERR(rtc->base);
361
362 clk = devm_clk_get_enabled(dev, "rtc");
363 if (IS_ERR(clk))
364 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get RTC clock\n");
365
366 spin_lock_init(&rtc->lock);
367
368 platform_set_drvdata(pdev, rtc);
369
370 device_init_wakeup(dev, 1);
371
372 ret = dev_pm_set_wake_irq(dev, irq);
373 if (ret)
374 return dev_err_probe(dev, ret, "Failed to set wake irq\n");
375
376 rtc->rtc = devm_rtc_allocate_device(dev);
377 if (IS_ERR(rtc->rtc))
378 return dev_err_probe(dev, PTR_ERR(rtc->rtc),
379 "Failed to allocate rtc device\n");
380
381 rtc->rtc->ops = &jz4740_rtc_ops;
382 rtc->rtc->range_max = U32_MAX;
383
384 rate = clk_get_rate(clk);
385 jz4740_rtc_set_wakeup_params(rtc, np, rate);
386
387 /* Each 1 Hz pulse should happen after (rate) ticks */
388 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
389
390 ret = devm_rtc_register_device(rtc->rtc);
391 if (ret)
392 return ret;
393
394 ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
395 pdev->name, rtc);
396 if (ret)
397 return dev_err_probe(dev, ret, "Failed to request rtc irq\n");
398
399 if (of_device_is_system_power_controller(np)) {
400 dev_for_power_off = dev;
401
402 if (!pm_power_off)
403 pm_power_off = jz4740_rtc_power_off;
404 else
405 dev_warn(dev, "Poweroff handler already present!\n");
406 }
407
408 if (device_property_present(dev, "#clock-cells")) {
409 rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk),
410 &jz4740_rtc_clk32k_ops, 0);
411
412 ret = devm_clk_hw_register(dev, &rtc->clk32k);
413 if (ret)
414 return dev_err_probe(dev, ret,
415 "Unable to register clk32k clock\n");
416
417 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
418 &rtc->clk32k);
419 if (ret)
420 return dev_err_probe(dev, ret,
421 "Unable to register clk32k clock provider\n");
422 }
423
424 return 0;
425}
426
427static struct platform_driver jz4740_rtc_driver = {
428 .probe = jz4740_rtc_probe,
429 .driver = {
430 .name = "jz4740-rtc",
431 .of_match_table = jz4740_rtc_of_match,
432 },
433};
434
435module_platform_driver(jz4740_rtc_driver);
436
437MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
438MODULE_LICENSE("GPL");
439MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
440MODULE_ALIAS("platform:jz4740-rtc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
5 * JZ4740 SoC RTC driver
6 */
7
8#include <linux/clk.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_wakeirq.h>
15#include <linux/reboot.h>
16#include <linux/rtc.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19
20#define JZ_REG_RTC_CTRL 0x00
21#define JZ_REG_RTC_SEC 0x04
22#define JZ_REG_RTC_SEC_ALARM 0x08
23#define JZ_REG_RTC_REGULATOR 0x0C
24#define JZ_REG_RTC_HIBERNATE 0x20
25#define JZ_REG_RTC_WAKEUP_FILTER 0x24
26#define JZ_REG_RTC_RESET_COUNTER 0x28
27#define JZ_REG_RTC_SCRATCHPAD 0x34
28
29/* The following are present on the jz4780 */
30#define JZ_REG_RTC_WENR 0x3C
31#define JZ_RTC_WENR_WEN BIT(31)
32
33#define JZ_RTC_CTRL_WRDY BIT(7)
34#define JZ_RTC_CTRL_1HZ BIT(6)
35#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
36#define JZ_RTC_CTRL_AF BIT(4)
37#define JZ_RTC_CTRL_AF_IRQ BIT(3)
38#define JZ_RTC_CTRL_AE BIT(2)
39#define JZ_RTC_CTRL_ENABLE BIT(0)
40
41/* Magic value to enable writes on jz4780 */
42#define JZ_RTC_WENR_MAGIC 0xA55A
43
44#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
45#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
46
47enum jz4740_rtc_type {
48 ID_JZ4740,
49 ID_JZ4760,
50 ID_JZ4780,
51};
52
53struct jz4740_rtc {
54 void __iomem *base;
55 enum jz4740_rtc_type type;
56
57 struct rtc_device *rtc;
58
59 spinlock_t lock;
60};
61
62static struct device *dev_for_power_off;
63
64static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
65{
66 return readl(rtc->base + reg);
67}
68
69static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
70{
71 uint32_t ctrl;
72 int timeout = 10000;
73
74 do {
75 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
77
78 return timeout ? 0 : -EIO;
79}
80
81static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
82{
83 uint32_t ctrl;
84 int ret, timeout = 10000;
85
86 ret = jz4740_rtc_wait_write_ready(rtc);
87 if (ret != 0)
88 return ret;
89
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
91
92 do {
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
94 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
95
96 return timeout ? 0 : -EIO;
97}
98
99static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
100 uint32_t val)
101{
102 int ret = 0;
103
104 if (rtc->type >= ID_JZ4760)
105 ret = jz4780_rtc_enable_write(rtc);
106 if (ret == 0)
107 ret = jz4740_rtc_wait_write_ready(rtc);
108 if (ret == 0)
109 writel(val, rtc->base + reg);
110
111 return ret;
112}
113
114static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
115 bool set)
116{
117 int ret;
118 unsigned long flags;
119 uint32_t ctrl;
120
121 spin_lock_irqsave(&rtc->lock, flags);
122
123 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
124
125 /* Don't clear interrupt flags by accident */
126 ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
127
128 if (set)
129 ctrl |= mask;
130 else
131 ctrl &= ~mask;
132
133 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
134
135 spin_unlock_irqrestore(&rtc->lock, flags);
136
137 return ret;
138}
139
140static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
141{
142 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
143 uint32_t secs, secs2;
144 int timeout = 5;
145
146 if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
147 return -EINVAL;
148
149 /* If the seconds register is read while it is updated, it can contain a
150 * bogus value. This can be avoided by making sure that two consecutive
151 * reads have the same value.
152 */
153 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
154 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
155
156 while (secs != secs2 && --timeout) {
157 secs = secs2;
158 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
159 }
160
161 if (timeout == 0)
162 return -EIO;
163
164 rtc_time64_to_tm(secs, time);
165
166 return 0;
167}
168
169static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
170{
171 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
172 int ret;
173
174 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
175 if (ret)
176 return ret;
177
178 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
179}
180
181static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
182{
183 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
184 uint32_t secs;
185 uint32_t ctrl;
186
187 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
188
189 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
190
191 alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
192 alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
193
194 rtc_time64_to_tm(secs, &alrm->time);
195
196 return 0;
197}
198
199static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
200{
201 int ret;
202 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
203 uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
204
205 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
206 if (!ret)
207 ret = jz4740_rtc_ctrl_set_bits(rtc,
208 JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
209
210 return ret;
211}
212
213static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
214{
215 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
216 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
217}
218
219static const struct rtc_class_ops jz4740_rtc_ops = {
220 .read_time = jz4740_rtc_read_time,
221 .set_time = jz4740_rtc_set_time,
222 .read_alarm = jz4740_rtc_read_alarm,
223 .set_alarm = jz4740_rtc_set_alarm,
224 .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
225};
226
227static irqreturn_t jz4740_rtc_irq(int irq, void *data)
228{
229 struct jz4740_rtc *rtc = data;
230 uint32_t ctrl;
231 unsigned long events = 0;
232
233 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
234
235 if (ctrl & JZ_RTC_CTRL_1HZ)
236 events |= (RTC_UF | RTC_IRQF);
237
238 if (ctrl & JZ_RTC_CTRL_AF)
239 events |= (RTC_AF | RTC_IRQF);
240
241 rtc_update_irq(rtc->rtc, 1, events);
242
243 jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
244
245 return IRQ_HANDLED;
246}
247
248static void jz4740_rtc_poweroff(struct device *dev)
249{
250 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
251 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
252}
253
254static void jz4740_rtc_power_off(void)
255{
256 jz4740_rtc_poweroff(dev_for_power_off);
257 kernel_halt();
258}
259
260static void jz4740_rtc_clk_disable(void *data)
261{
262 clk_disable_unprepare(data);
263}
264
265static const struct of_device_id jz4740_rtc_of_match[] = {
266 { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
267 { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
268 { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
269 {},
270};
271MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
272
273static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
274 struct device_node *np,
275 unsigned long rate)
276{
277 unsigned long wakeup_ticks, reset_ticks;
278 unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
279 unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
280
281 of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
282 &reset_pin_assert_time);
283 of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
284 &min_wakeup_pin_assert_time);
285
286 /*
287 * Set minimum wakeup pin assertion time: 100 ms.
288 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
289 */
290 wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
291 if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
292 wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
293 else
294 wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
295 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
296
297 /*
298 * Set reset pin low-level assertion time after wakeup: 60 ms.
299 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
300 */
301 reset_ticks = (reset_pin_assert_time * rate) / 1000;
302 if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
303 reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
304 else
305 reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
306 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
307}
308
309static int jz4740_rtc_probe(struct platform_device *pdev)
310{
311 struct device *dev = &pdev->dev;
312 struct device_node *np = dev->of_node;
313 struct jz4740_rtc *rtc;
314 unsigned long rate;
315 struct clk *clk;
316 int ret, irq;
317
318 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
319 if (!rtc)
320 return -ENOMEM;
321
322 rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
323
324 irq = platform_get_irq(pdev, 0);
325 if (irq < 0)
326 return irq;
327
328 rtc->base = devm_platform_ioremap_resource(pdev, 0);
329 if (IS_ERR(rtc->base))
330 return PTR_ERR(rtc->base);
331
332 clk = devm_clk_get(dev, "rtc");
333 if (IS_ERR(clk)) {
334 dev_err(dev, "Failed to get RTC clock\n");
335 return PTR_ERR(clk);
336 }
337
338 ret = clk_prepare_enable(clk);
339 if (ret) {
340 dev_err(dev, "Failed to enable clock\n");
341 return ret;
342 }
343
344 ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
345 if (ret) {
346 dev_err(dev, "Failed to register devm action\n");
347 return ret;
348 }
349
350 spin_lock_init(&rtc->lock);
351
352 platform_set_drvdata(pdev, rtc);
353
354 device_init_wakeup(dev, 1);
355
356 ret = dev_pm_set_wake_irq(dev, irq);
357 if (ret) {
358 dev_err(dev, "Failed to set wake irq: %d\n", ret);
359 return ret;
360 }
361
362 rtc->rtc = devm_rtc_allocate_device(dev);
363 if (IS_ERR(rtc->rtc)) {
364 ret = PTR_ERR(rtc->rtc);
365 dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
366 return ret;
367 }
368
369 rtc->rtc->ops = &jz4740_rtc_ops;
370 rtc->rtc->range_max = U32_MAX;
371
372 rate = clk_get_rate(clk);
373 jz4740_rtc_set_wakeup_params(rtc, np, rate);
374
375 /* Each 1 Hz pulse should happen after (rate) ticks */
376 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
377
378 ret = rtc_register_device(rtc->rtc);
379 if (ret)
380 return ret;
381
382 ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
383 pdev->name, rtc);
384 if (ret) {
385 dev_err(dev, "Failed to request rtc irq: %d\n", ret);
386 return ret;
387 }
388
389 if (of_device_is_system_power_controller(np)) {
390 dev_for_power_off = dev;
391
392 if (!pm_power_off)
393 pm_power_off = jz4740_rtc_power_off;
394 else
395 dev_warn(dev, "Poweroff handler already present!\n");
396 }
397
398 return 0;
399}
400
401static struct platform_driver jz4740_rtc_driver = {
402 .probe = jz4740_rtc_probe,
403 .driver = {
404 .name = "jz4740-rtc",
405 .of_match_table = jz4740_rtc_of_match,
406 },
407};
408
409module_platform_driver(jz4740_rtc_driver);
410
411MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
412MODULE_LICENSE("GPL");
413MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
414MODULE_ALIAS("platform:jz4740-rtc");