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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_pci.h>
12#include <linux/pci_hotplug.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/cpumask.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/hypervisor.h>
19#include <linux/irqdomain.h>
20#include <linux/pm_runtime.h>
21#include <linux/bitfield.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34/* Ugh. Need to stop exporting this to modules. */
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68/*
69 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
71 * is no device to be found on the pci_bus_type.
72 */
73int no_pci_devices(void)
74{
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82}
83EXPORT_SYMBOL(no_pci_devices);
84
85/*
86 * PCI Bus Class
87 */
88static void release_pcibus_dev(struct device *dev)
89{
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96}
97
98static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102};
103
104static int __init pcibus_class_init(void)
105{
106 return class_register(&pcibus_class);
107}
108postcore_initcall(pcibus_class_init);
109
110static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111{
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
115
116 /*
117 * Get the lowest of them to find the decode size, and from that
118 * the extent.
119 */
120 size = size & ~(size-1);
121
122 /*
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
125 */
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
127 return 0;
128
129 return size;
130}
131
132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
133{
134 u32 mem_type;
135 unsigned long flags;
136
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
141 }
142
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
147
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153 /* 1M mem BAR treated as 32-bit BAR */
154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
157 break;
158 default:
159 /* mem unknown type treated as 32-bit BAR */
160 break;
161 }
162 return flags;
163}
164
165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166
167/**
168 * __pci_read_base - Read a PCI BAR
169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
173 *
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 */
176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
178{
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
181 u16 orig_cmd;
182 struct pci_bus_region region, inverted_region;
183 const char *res_name = pci_resource_name(dev, res - dev->resource);
184
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 }
194 }
195
196 res->name = pci_name(dev);
197
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
202
203 /*
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 * 1 must be clear.
208 */
209 if (PCI_POSSIBLE_ERROR(sz))
210 sz = 0;
211
212 /*
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
215 */
216 if (PCI_POSSIBLE_ERROR(l))
217 l = 0;
218
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 } else {
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 }
231 } else {
232 if (l & PCI_ROM_ADDRESS_ENABLE)
233 res->flags |= IORESOURCE_ROM_ENABLE;
234 l64 = l & PCI_ROM_ADDRESS_MASK;
235 sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 mask64 = PCI_ROM_ADDRESS_MASK;
237 }
238
239 if (res->flags & IORESOURCE_MEM_64) {
240 pci_read_config_dword(dev, pos + 4, &l);
241 pci_write_config_dword(dev, pos + 4, ~0);
242 pci_read_config_dword(dev, pos + 4, &sz);
243 pci_write_config_dword(dev, pos + 4, l);
244
245 l64 |= ((u64)l << 32);
246 sz64 |= ((u64)sz << 32);
247 mask64 |= ((u64)~0 << 32);
248 }
249
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252
253 if (!sz64)
254 goto fail;
255
256 sz64 = pci_size(l64, sz64, mask64);
257 if (!sz64) {
258 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n",
269 res_name, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64 - 1;
278 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n",
279 res_name, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64 - 1;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290 /*
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
295 *
296 * resource_to_bus(bus_to_resource(A)) == A
297 *
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
300 */
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 pci_info(dev, "%s: initial BAR value %#010llx invalid\n",
306 res_name, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 pci_info(dev, "%s %pR\n", res_name, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 if (dev->non_compliant_bars)
326 return;
327
328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
329 if (dev->is_virtfn)
330 return;
331
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
336 }
337
338 if (rom) {
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 }
345}
346
347static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res,
348 bool log)
349{
350 u8 io_base_lo, io_limit_lo;
351 unsigned long io_mask, io_granularity, base, limit;
352 struct pci_bus_region region;
353
354 io_mask = PCI_IO_RANGE_MASK;
355 io_granularity = 0x1000;
356 if (dev->io_window_1k) {
357 /* Support 1K I/O space granularity */
358 io_mask = PCI_IO_1K_RANGE_MASK;
359 io_granularity = 0x400;
360 }
361
362 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
363 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
364 base = (io_base_lo & io_mask) << 8;
365 limit = (io_limit_lo & io_mask) << 8;
366
367 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
368 u16 io_base_hi, io_limit_hi;
369
370 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
371 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
372 base |= ((unsigned long) io_base_hi << 16);
373 limit |= ((unsigned long) io_limit_hi << 16);
374 }
375
376 if (base <= limit) {
377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
378 region.start = base;
379 region.end = limit + io_granularity - 1;
380 pcibios_bus_to_resource(dev->bus, res, ®ion);
381 if (log)
382 pci_info(dev, " bridge window %pR\n", res);
383 }
384}
385
386static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res,
387 bool log)
388{
389 u16 mem_base_lo, mem_limit_lo;
390 unsigned long base, limit;
391 struct pci_bus_region region;
392
393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
397 if (base <= limit) {
398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
399 region.start = base;
400 region.end = limit + 0xfffff;
401 pcibios_bus_to_resource(dev->bus, res, ®ion);
402 if (log)
403 pci_info(dev, " bridge window %pR\n", res);
404 }
405}
406
407static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res,
408 bool log)
409{
410 u16 mem_base_lo, mem_limit_lo;
411 u64 base64, limit64;
412 pci_bus_addr_t base, limit;
413 struct pci_bus_region region;
414
415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
417 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
418 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
419
420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
421 u32 mem_base_hi, mem_limit_hi;
422
423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
425
426 /*
427 * Some bridges set the base > limit by default, and some
428 * (broken) BIOSes do not initialize them. If we find
429 * this, just assume they are not being used.
430 */
431 if (mem_base_hi <= mem_limit_hi) {
432 base64 |= (u64) mem_base_hi << 32;
433 limit64 |= (u64) mem_limit_hi << 32;
434 }
435 }
436
437 base = (pci_bus_addr_t) base64;
438 limit = (pci_bus_addr_t) limit64;
439
440 if (base != base64) {
441 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
442 (unsigned long long) base64);
443 return;
444 }
445
446 if (base <= limit) {
447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
448 IORESOURCE_MEM | IORESOURCE_PREFETCH;
449 if (res->flags & PCI_PREF_RANGE_TYPE_64)
450 res->flags |= IORESOURCE_MEM_64;
451 region.start = base;
452 region.end = limit + 0xfffff;
453 pcibios_bus_to_resource(dev->bus, res, ®ion);
454 if (log)
455 pci_info(dev, " bridge window %pR\n", res);
456 }
457}
458
459static void pci_read_bridge_windows(struct pci_dev *bridge)
460{
461 u32 buses;
462 u16 io;
463 u32 pmem, tmp;
464 struct resource res;
465
466 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);
467 res.flags = IORESOURCE_BUS;
468 res.start = (buses >> 8) & 0xff;
469 res.end = (buses >> 16) & 0xff;
470 pci_info(bridge, "PCI bridge to %pR%s\n", &res,
471 bridge->transparent ? " (subtractive decode)" : "");
472
473 pci_read_config_word(bridge, PCI_IO_BASE, &io);
474 if (!io) {
475 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
476 pci_read_config_word(bridge, PCI_IO_BASE, &io);
477 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
478 }
479 if (io) {
480 bridge->io_window = 1;
481 pci_read_bridge_io(bridge, &res, true);
482 }
483
484 pci_read_bridge_mmio(bridge, &res, true);
485
486 /*
487 * DECchip 21050 pass 2 errata: the bridge may miss an address
488 * disconnect boundary by one PCI data phase. Workaround: do not
489 * use prefetching on this device.
490 */
491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
492 return;
493
494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
495 if (!pmem) {
496 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
497 0xffe0fff0);
498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
499 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
500 }
501 if (!pmem)
502 return;
503
504 bridge->pref_window = 1;
505
506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
507
508 /*
509 * Bridge claims to have a 64-bit prefetchable memory
510 * window; verify that the upper bits are actually
511 * writable.
512 */
513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
514 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
515 0xffffffff);
516 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
518 if (tmp)
519 bridge->pref_64_window = 1;
520 }
521
522 pci_read_bridge_mmio_pref(bridge, &res, true);
523}
524
525void pci_read_bridge_bases(struct pci_bus *child)
526{
527 struct pci_dev *dev = child->self;
528 struct resource *res;
529 int i;
530
531 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
532 return;
533
534 pci_info(dev, "PCI bridge to %pR%s\n",
535 &child->busn_res,
536 dev->transparent ? " (subtractive decode)" : "");
537
538 pci_bus_remove_resources(child);
539 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
541
542 pci_read_bridge_io(child->self, child->resource[0], false);
543 pci_read_bridge_mmio(child->self, child->resource[1], false);
544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false);
545
546 if (dev->transparent) {
547 pci_bus_for_each_resource(child->parent, res) {
548 if (res && res->flags) {
549 pci_bus_add_resource(child, res,
550 PCI_SUBTRACTIVE_DECODE);
551 pci_info(dev, " bridge window %pR (subtractive decode)\n",
552 res);
553 }
554 }
555 }
556}
557
558static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
559{
560 struct pci_bus *b;
561
562 b = kzalloc(sizeof(*b), GFP_KERNEL);
563 if (!b)
564 return NULL;
565
566 INIT_LIST_HEAD(&b->node);
567 INIT_LIST_HEAD(&b->children);
568 INIT_LIST_HEAD(&b->devices);
569 INIT_LIST_HEAD(&b->slots);
570 INIT_LIST_HEAD(&b->resources);
571 b->max_bus_speed = PCI_SPEED_UNKNOWN;
572 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
573#ifdef CONFIG_PCI_DOMAINS_GENERIC
574 if (parent)
575 b->domain_nr = parent->domain_nr;
576#endif
577 return b;
578}
579
580static void pci_release_host_bridge_dev(struct device *dev)
581{
582 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
583
584 if (bridge->release_fn)
585 bridge->release_fn(bridge);
586
587 pci_free_resource_list(&bridge->windows);
588 pci_free_resource_list(&bridge->dma_ranges);
589 kfree(bridge);
590}
591
592static void pci_init_host_bridge(struct pci_host_bridge *bridge)
593{
594 INIT_LIST_HEAD(&bridge->windows);
595 INIT_LIST_HEAD(&bridge->dma_ranges);
596
597 /*
598 * We assume we can manage these PCIe features. Some systems may
599 * reserve these for use by the platform itself, e.g., an ACPI BIOS
600 * may implement its own AER handling and use _OSC to prevent the
601 * OS from interfering.
602 */
603 bridge->native_aer = 1;
604 bridge->native_pcie_hotplug = 1;
605 bridge->native_shpc_hotplug = 1;
606 bridge->native_pme = 1;
607 bridge->native_ltr = 1;
608 bridge->native_dpc = 1;
609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
610 bridge->native_cxl_error = 1;
611
612 device_initialize(&bridge->dev);
613}
614
615struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
616{
617 struct pci_host_bridge *bridge;
618
619 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
620 if (!bridge)
621 return NULL;
622
623 pci_init_host_bridge(bridge);
624 bridge->dev.release = pci_release_host_bridge_dev;
625
626 return bridge;
627}
628EXPORT_SYMBOL(pci_alloc_host_bridge);
629
630static void devm_pci_alloc_host_bridge_release(void *data)
631{
632 pci_free_host_bridge(data);
633}
634
635struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
636 size_t priv)
637{
638 int ret;
639 struct pci_host_bridge *bridge;
640
641 bridge = pci_alloc_host_bridge(priv);
642 if (!bridge)
643 return NULL;
644
645 bridge->dev.parent = dev;
646
647 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
648 bridge);
649 if (ret)
650 return NULL;
651
652 ret = devm_of_pci_bridge_init(dev, bridge);
653 if (ret)
654 return NULL;
655
656 return bridge;
657}
658EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
659
660void pci_free_host_bridge(struct pci_host_bridge *bridge)
661{
662 put_device(&bridge->dev);
663}
664EXPORT_SYMBOL(pci_free_host_bridge);
665
666/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
667static const unsigned char pcix_bus_speed[] = {
668 PCI_SPEED_UNKNOWN, /* 0 */
669 PCI_SPEED_66MHz_PCIX, /* 1 */
670 PCI_SPEED_100MHz_PCIX, /* 2 */
671 PCI_SPEED_133MHz_PCIX, /* 3 */
672 PCI_SPEED_UNKNOWN, /* 4 */
673 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
674 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
675 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
676 PCI_SPEED_UNKNOWN, /* 8 */
677 PCI_SPEED_66MHz_PCIX_266, /* 9 */
678 PCI_SPEED_100MHz_PCIX_266, /* A */
679 PCI_SPEED_133MHz_PCIX_266, /* B */
680 PCI_SPEED_UNKNOWN, /* C */
681 PCI_SPEED_66MHz_PCIX_533, /* D */
682 PCI_SPEED_100MHz_PCIX_533, /* E */
683 PCI_SPEED_133MHz_PCIX_533 /* F */
684};
685
686/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
687const unsigned char pcie_link_speed[] = {
688 PCI_SPEED_UNKNOWN, /* 0 */
689 PCIE_SPEED_2_5GT, /* 1 */
690 PCIE_SPEED_5_0GT, /* 2 */
691 PCIE_SPEED_8_0GT, /* 3 */
692 PCIE_SPEED_16_0GT, /* 4 */
693 PCIE_SPEED_32_0GT, /* 5 */
694 PCIE_SPEED_64_0GT, /* 6 */
695 PCI_SPEED_UNKNOWN, /* 7 */
696 PCI_SPEED_UNKNOWN, /* 8 */
697 PCI_SPEED_UNKNOWN, /* 9 */
698 PCI_SPEED_UNKNOWN, /* A */
699 PCI_SPEED_UNKNOWN, /* B */
700 PCI_SPEED_UNKNOWN, /* C */
701 PCI_SPEED_UNKNOWN, /* D */
702 PCI_SPEED_UNKNOWN, /* E */
703 PCI_SPEED_UNKNOWN /* F */
704};
705EXPORT_SYMBOL_GPL(pcie_link_speed);
706
707const char *pci_speed_string(enum pci_bus_speed speed)
708{
709 /* Indexed by the pci_bus_speed enum */
710 static const char *speed_strings[] = {
711 "33 MHz PCI", /* 0x00 */
712 "66 MHz PCI", /* 0x01 */
713 "66 MHz PCI-X", /* 0x02 */
714 "100 MHz PCI-X", /* 0x03 */
715 "133 MHz PCI-X", /* 0x04 */
716 NULL, /* 0x05 */
717 NULL, /* 0x06 */
718 NULL, /* 0x07 */
719 NULL, /* 0x08 */
720 "66 MHz PCI-X 266", /* 0x09 */
721 "100 MHz PCI-X 266", /* 0x0a */
722 "133 MHz PCI-X 266", /* 0x0b */
723 "Unknown AGP", /* 0x0c */
724 "1x AGP", /* 0x0d */
725 "2x AGP", /* 0x0e */
726 "4x AGP", /* 0x0f */
727 "8x AGP", /* 0x10 */
728 "66 MHz PCI-X 533", /* 0x11 */
729 "100 MHz PCI-X 533", /* 0x12 */
730 "133 MHz PCI-X 533", /* 0x13 */
731 "2.5 GT/s PCIe", /* 0x14 */
732 "5.0 GT/s PCIe", /* 0x15 */
733 "8.0 GT/s PCIe", /* 0x16 */
734 "16.0 GT/s PCIe", /* 0x17 */
735 "32.0 GT/s PCIe", /* 0x18 */
736 "64.0 GT/s PCIe", /* 0x19 */
737 };
738
739 if (speed < ARRAY_SIZE(speed_strings))
740 return speed_strings[speed];
741 return "Unknown";
742}
743EXPORT_SYMBOL_GPL(pci_speed_string);
744
745void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
746{
747 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
748}
749EXPORT_SYMBOL_GPL(pcie_update_link_speed);
750
751static unsigned char agp_speeds[] = {
752 AGP_UNKNOWN,
753 AGP_1X,
754 AGP_2X,
755 AGP_4X,
756 AGP_8X
757};
758
759static enum pci_bus_speed agp_speed(int agp3, int agpstat)
760{
761 int index = 0;
762
763 if (agpstat & 4)
764 index = 3;
765 else if (agpstat & 2)
766 index = 2;
767 else if (agpstat & 1)
768 index = 1;
769 else
770 goto out;
771
772 if (agp3) {
773 index += 2;
774 if (index == 5)
775 index = 0;
776 }
777
778 out:
779 return agp_speeds[index];
780}
781
782static void pci_set_bus_speed(struct pci_bus *bus)
783{
784 struct pci_dev *bridge = bus->self;
785 int pos;
786
787 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
788 if (!pos)
789 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
790 if (pos) {
791 u32 agpstat, agpcmd;
792
793 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
794 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
795
796 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
797 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
798 }
799
800 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
801 if (pos) {
802 u16 status;
803 enum pci_bus_speed max;
804
805 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
806 &status);
807
808 if (status & PCI_X_SSTATUS_533MHZ) {
809 max = PCI_SPEED_133MHz_PCIX_533;
810 } else if (status & PCI_X_SSTATUS_266MHZ) {
811 max = PCI_SPEED_133MHz_PCIX_266;
812 } else if (status & PCI_X_SSTATUS_133MHZ) {
813 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
814 max = PCI_SPEED_133MHz_PCIX_ECC;
815 else
816 max = PCI_SPEED_133MHz_PCIX;
817 } else {
818 max = PCI_SPEED_66MHz_PCIX;
819 }
820
821 bus->max_bus_speed = max;
822 bus->cur_bus_speed =
823 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)];
824
825 return;
826 }
827
828 if (pci_is_pcie(bridge)) {
829 u32 linkcap;
830 u16 linksta;
831
832 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
833 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
834
835 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
836 pcie_update_link_speed(bus, linksta);
837 }
838}
839
840static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
841{
842 struct irq_domain *d;
843
844 /* If the host bridge driver sets a MSI domain of the bridge, use it */
845 d = dev_get_msi_domain(bus->bridge);
846
847 /*
848 * Any firmware interface that can resolve the msi_domain
849 * should be called from here.
850 */
851 if (!d)
852 d = pci_host_bridge_of_msi_domain(bus);
853 if (!d)
854 d = pci_host_bridge_acpi_msi_domain(bus);
855
856 /*
857 * If no IRQ domain was found via the OF tree, try looking it up
858 * directly through the fwnode_handle.
859 */
860 if (!d) {
861 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
862
863 if (fwnode)
864 d = irq_find_matching_fwnode(fwnode,
865 DOMAIN_BUS_PCI_MSI);
866 }
867
868 return d;
869}
870
871static void pci_set_bus_msi_domain(struct pci_bus *bus)
872{
873 struct irq_domain *d;
874 struct pci_bus *b;
875
876 /*
877 * The bus can be a root bus, a subordinate bus, or a virtual bus
878 * created by an SR-IOV device. Walk up to the first bridge device
879 * found or derive the domain from the host bridge.
880 */
881 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
882 if (b->self)
883 d = dev_get_msi_domain(&b->self->dev);
884 }
885
886 if (!d)
887 d = pci_host_bridge_msi_domain(b);
888
889 dev_set_msi_domain(&bus->dev, d);
890}
891
892static int pci_register_host_bridge(struct pci_host_bridge *bridge)
893{
894 struct device *parent = bridge->dev.parent;
895 struct resource_entry *window, *next, *n;
896 struct pci_bus *bus, *b;
897 resource_size_t offset, next_offset;
898 LIST_HEAD(resources);
899 struct resource *res, *next_res;
900 char addr[64], *fmt;
901 const char *name;
902 int err;
903
904 bus = pci_alloc_bus(NULL);
905 if (!bus)
906 return -ENOMEM;
907
908 bridge->bus = bus;
909
910 bus->sysdata = bridge->sysdata;
911 bus->ops = bridge->ops;
912 bus->number = bus->busn_res.start = bridge->busnr;
913#ifdef CONFIG_PCI_DOMAINS_GENERIC
914 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
915 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
916 else
917 bus->domain_nr = bridge->domain_nr;
918 if (bus->domain_nr < 0) {
919 err = bus->domain_nr;
920 goto free;
921 }
922#endif
923
924 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
925 if (b) {
926 /* Ignore it if we already got here via a different bridge */
927 dev_dbg(&b->dev, "bus already known\n");
928 err = -EEXIST;
929 goto free;
930 }
931
932 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
933 bridge->busnr);
934
935 err = pcibios_root_bridge_prepare(bridge);
936 if (err)
937 goto free;
938
939 /* Temporarily move resources off the list */
940 list_splice_init(&bridge->windows, &resources);
941 err = device_add(&bridge->dev);
942 if (err) {
943 put_device(&bridge->dev);
944 goto free;
945 }
946 bus->bridge = get_device(&bridge->dev);
947 device_enable_async_suspend(bus->bridge);
948 pci_set_bus_of_node(bus);
949 pci_set_bus_msi_domain(bus);
950 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
951 !pci_host_of_has_msi_map(parent))
952 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
953
954 if (!parent)
955 set_dev_node(bus->bridge, pcibus_to_node(bus));
956
957 bus->dev.class = &pcibus_class;
958 bus->dev.parent = bus->bridge;
959
960 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
961 name = dev_name(&bus->dev);
962
963 err = device_register(&bus->dev);
964 if (err)
965 goto unregister;
966
967 pcibios_add_bus(bus);
968
969 if (bus->ops->add_bus) {
970 err = bus->ops->add_bus(bus);
971 if (WARN_ON(err < 0))
972 dev_err(&bus->dev, "failed to add bus: %d\n", err);
973 }
974
975 /* Create legacy_io and legacy_mem files for this bus */
976 pci_create_legacy_files(bus);
977
978 if (parent)
979 dev_info(parent, "PCI host bridge to bus %s\n", name);
980 else
981 pr_info("PCI host bridge to bus %s\n", name);
982
983 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
984 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
985
986 /* Coalesce contiguous windows */
987 resource_list_for_each_entry_safe(window, n, &resources) {
988 if (list_is_last(&window->node, &resources))
989 break;
990
991 next = list_next_entry(window, node);
992 offset = window->offset;
993 res = window->res;
994 next_offset = next->offset;
995 next_res = next->res;
996
997 if (res->flags != next_res->flags || offset != next_offset)
998 continue;
999
1000 if (res->end + 1 == next_res->start) {
1001 next_res->start = res->start;
1002 res->flags = res->start = res->end = 0;
1003 }
1004 }
1005
1006 /* Add initial resources to the bus */
1007 resource_list_for_each_entry_safe(window, n, &resources) {
1008 offset = window->offset;
1009 res = window->res;
1010 if (!res->flags && !res->start && !res->end) {
1011 release_resource(res);
1012 resource_list_destroy_entry(window);
1013 continue;
1014 }
1015
1016 list_move_tail(&window->node, &bridge->windows);
1017
1018 if (res->flags & IORESOURCE_BUS)
1019 pci_bus_insert_busn_res(bus, bus->number, res->end);
1020 else
1021 pci_bus_add_resource(bus, res, 0);
1022
1023 if (offset) {
1024 if (resource_type(res) == IORESOURCE_IO)
1025 fmt = " (bus address [%#06llx-%#06llx])";
1026 else
1027 fmt = " (bus address [%#010llx-%#010llx])";
1028
1029 snprintf(addr, sizeof(addr), fmt,
1030 (unsigned long long)(res->start - offset),
1031 (unsigned long long)(res->end - offset));
1032 } else
1033 addr[0] = '\0';
1034
1035 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1036 }
1037
1038 down_write(&pci_bus_sem);
1039 list_add_tail(&bus->node, &pci_root_buses);
1040 up_write(&pci_bus_sem);
1041
1042 return 0;
1043
1044unregister:
1045 put_device(&bridge->dev);
1046 device_del(&bridge->dev);
1047
1048free:
1049#ifdef CONFIG_PCI_DOMAINS_GENERIC
1050 pci_bus_release_domain_nr(bus, parent);
1051#endif
1052 kfree(bus);
1053 return err;
1054}
1055
1056static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1057{
1058 int pos;
1059 u32 status;
1060
1061 /*
1062 * If extended config space isn't accessible on a bridge's primary
1063 * bus, we certainly can't access it on the secondary bus.
1064 */
1065 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1066 return false;
1067
1068 /*
1069 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1070 * extended config space is accessible on the primary, it's also
1071 * accessible on the secondary.
1072 */
1073 if (pci_is_pcie(bridge) &&
1074 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1075 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1076 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1077 return true;
1078
1079 /*
1080 * For the other bridge types:
1081 * - PCI-to-PCI bridges
1082 * - PCIe-to-PCI/PCI-X forward bridges
1083 * - PCI/PCI-X-to-PCIe reverse bridges
1084 * extended config space on the secondary side is only accessible
1085 * if the bridge supports PCI-X Mode 2.
1086 */
1087 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1088 if (!pos)
1089 return false;
1090
1091 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1092 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1093}
1094
1095static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1096 struct pci_dev *bridge, int busnr)
1097{
1098 struct pci_bus *child;
1099 struct pci_host_bridge *host;
1100 int i;
1101 int ret;
1102
1103 /* Allocate a new bus and inherit stuff from the parent */
1104 child = pci_alloc_bus(parent);
1105 if (!child)
1106 return NULL;
1107
1108 child->parent = parent;
1109 child->sysdata = parent->sysdata;
1110 child->bus_flags = parent->bus_flags;
1111
1112 host = pci_find_host_bridge(parent);
1113 if (host->child_ops)
1114 child->ops = host->child_ops;
1115 else
1116 child->ops = parent->ops;
1117
1118 /*
1119 * Initialize some portions of the bus device, but don't register
1120 * it now as the parent is not properly set up yet.
1121 */
1122 child->dev.class = &pcibus_class;
1123 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1124
1125 /* Set up the primary, secondary and subordinate bus numbers */
1126 child->number = child->busn_res.start = busnr;
1127 child->primary = parent->busn_res.start;
1128 child->busn_res.end = 0xff;
1129
1130 if (!bridge) {
1131 child->dev.parent = parent->bridge;
1132 goto add_dev;
1133 }
1134
1135 child->self = bridge;
1136 child->bridge = get_device(&bridge->dev);
1137 child->dev.parent = child->bridge;
1138 pci_set_bus_of_node(child);
1139 pci_set_bus_speed(child);
1140
1141 /*
1142 * Check whether extended config space is accessible on the child
1143 * bus. Note that we currently assume it is always accessible on
1144 * the root bus.
1145 */
1146 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1147 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1148 pci_info(child, "extended config space not accessible\n");
1149 }
1150
1151 /* Set up default resource pointers and names */
1152 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1153 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1154 child->resource[i]->name = child->name;
1155 }
1156 bridge->subordinate = child;
1157
1158add_dev:
1159 pci_set_bus_msi_domain(child);
1160 ret = device_register(&child->dev);
1161 WARN_ON(ret < 0);
1162
1163 pcibios_add_bus(child);
1164
1165 if (child->ops->add_bus) {
1166 ret = child->ops->add_bus(child);
1167 if (WARN_ON(ret < 0))
1168 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1169 }
1170
1171 /* Create legacy_io and legacy_mem files for this bus */
1172 pci_create_legacy_files(child);
1173
1174 return child;
1175}
1176
1177struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1178 int busnr)
1179{
1180 struct pci_bus *child;
1181
1182 child = pci_alloc_child_bus(parent, dev, busnr);
1183 if (child) {
1184 down_write(&pci_bus_sem);
1185 list_add_tail(&child->node, &parent->children);
1186 up_write(&pci_bus_sem);
1187 }
1188 return child;
1189}
1190EXPORT_SYMBOL(pci_add_new_bus);
1191
1192static void pci_enable_crs(struct pci_dev *pdev)
1193{
1194 u16 root_cap = 0;
1195
1196 /* Enable CRS Software Visibility if supported */
1197 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1198 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1199 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1200 PCI_EXP_RTCTL_CRSSVE);
1201}
1202
1203static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1204 unsigned int available_buses);
1205/**
1206 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1207 * numbers from EA capability.
1208 * @dev: Bridge
1209 * @sec: updated with secondary bus number from EA
1210 * @sub: updated with subordinate bus number from EA
1211 *
1212 * If @dev is a bridge with EA capability that specifies valid secondary
1213 * and subordinate bus numbers, return true with the bus numbers in @sec
1214 * and @sub. Otherwise return false.
1215 */
1216static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1217{
1218 int ea, offset;
1219 u32 dw;
1220 u8 ea_sec, ea_sub;
1221
1222 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1223 return false;
1224
1225 /* find PCI EA capability in list */
1226 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1227 if (!ea)
1228 return false;
1229
1230 offset = ea + PCI_EA_FIRST_ENT;
1231 pci_read_config_dword(dev, offset, &dw);
1232 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw);
1233 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw);
1234 if (ea_sec == 0 || ea_sub < ea_sec)
1235 return false;
1236
1237 *sec = ea_sec;
1238 *sub = ea_sub;
1239 return true;
1240}
1241
1242/*
1243 * pci_scan_bridge_extend() - Scan buses behind a bridge
1244 * @bus: Parent bus the bridge is on
1245 * @dev: Bridge itself
1246 * @max: Starting subordinate number of buses behind this bridge
1247 * @available_buses: Total number of buses available for this bridge and
1248 * the devices below. After the minimal bus space has
1249 * been allocated the remaining buses will be
1250 * distributed equally between hotplug-capable bridges.
1251 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1252 * that need to be reconfigured.
1253 *
1254 * If it's a bridge, configure it and scan the bus behind it.
1255 * For CardBus bridges, we don't scan behind as the devices will
1256 * be handled by the bridge driver itself.
1257 *
1258 * We need to process bridges in two passes -- first we scan those
1259 * already configured by the BIOS and after we are done with all of
1260 * them, we proceed to assigning numbers to the remaining buses in
1261 * order to avoid overlaps between old and new bus numbers.
1262 *
1263 * Return: New subordinate number covering all buses behind this bridge.
1264 */
1265static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1266 int max, unsigned int available_buses,
1267 int pass)
1268{
1269 struct pci_bus *child;
1270 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1271 u32 buses, i, j = 0;
1272 u16 bctl;
1273 u8 primary, secondary, subordinate;
1274 int broken = 0;
1275 bool fixed_buses;
1276 u8 fixed_sec, fixed_sub;
1277 int next_busnr;
1278
1279 /*
1280 * Make sure the bridge is powered on to be able to access config
1281 * space of devices below it.
1282 */
1283 pm_runtime_get_sync(&dev->dev);
1284
1285 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1286 primary = buses & 0xFF;
1287 secondary = (buses >> 8) & 0xFF;
1288 subordinate = (buses >> 16) & 0xFF;
1289
1290 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1291 secondary, subordinate, pass);
1292
1293 if (!primary && (primary != bus->number) && secondary && subordinate) {
1294 pci_warn(dev, "Primary bus is hard wired to 0\n");
1295 primary = bus->number;
1296 }
1297
1298 /* Check if setup is sensible at all */
1299 if (!pass &&
1300 (primary != bus->number || secondary <= bus->number ||
1301 secondary > subordinate)) {
1302 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1303 secondary, subordinate);
1304 broken = 1;
1305 }
1306
1307 /*
1308 * Disable Master-Abort Mode during probing to avoid reporting of
1309 * bus errors in some architectures.
1310 */
1311 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1312 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1313 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1314
1315 pci_enable_crs(dev);
1316
1317 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1318 !is_cardbus && !broken) {
1319 unsigned int cmax, buses;
1320
1321 /*
1322 * Bus already configured by firmware, process it in the
1323 * first pass and just note the configuration.
1324 */
1325 if (pass)
1326 goto out;
1327
1328 /*
1329 * The bus might already exist for two reasons: Either we
1330 * are rescanning the bus or the bus is reachable through
1331 * more than one bridge. The second case can happen with
1332 * the i450NX chipset.
1333 */
1334 child = pci_find_bus(pci_domain_nr(bus), secondary);
1335 if (!child) {
1336 child = pci_add_new_bus(bus, dev, secondary);
1337 if (!child)
1338 goto out;
1339 child->primary = primary;
1340 pci_bus_insert_busn_res(child, secondary, subordinate);
1341 child->bridge_ctl = bctl;
1342 }
1343
1344 buses = subordinate - secondary;
1345 cmax = pci_scan_child_bus_extend(child, buses);
1346 if (cmax > subordinate)
1347 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1348 subordinate, cmax);
1349
1350 /* Subordinate should equal child->busn_res.end */
1351 if (subordinate > max)
1352 max = subordinate;
1353 } else {
1354
1355 /*
1356 * We need to assign a number to this bus which we always
1357 * do in the second pass.
1358 */
1359 if (!pass) {
1360 if (pcibios_assign_all_busses() || broken || is_cardbus)
1361
1362 /*
1363 * Temporarily disable forwarding of the
1364 * configuration cycles on all bridges in
1365 * this bus segment to avoid possible
1366 * conflicts in the second pass between two
1367 * bridges programmed with overlapping bus
1368 * ranges.
1369 */
1370 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1371 buses & ~0xffffff);
1372 goto out;
1373 }
1374
1375 /* Clear errors */
1376 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1377
1378 /* Read bus numbers from EA Capability (if present) */
1379 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1380 if (fixed_buses)
1381 next_busnr = fixed_sec;
1382 else
1383 next_busnr = max + 1;
1384
1385 /*
1386 * Prevent assigning a bus number that already exists.
1387 * This can happen when a bridge is hot-plugged, so in this
1388 * case we only re-scan this bus.
1389 */
1390 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1391 if (!child) {
1392 child = pci_add_new_bus(bus, dev, next_busnr);
1393 if (!child)
1394 goto out;
1395 pci_bus_insert_busn_res(child, next_busnr,
1396 bus->busn_res.end);
1397 }
1398 max++;
1399 if (available_buses)
1400 available_buses--;
1401
1402 buses = (buses & 0xff000000)
1403 | ((unsigned int)(child->primary) << 0)
1404 | ((unsigned int)(child->busn_res.start) << 8)
1405 | ((unsigned int)(child->busn_res.end) << 16);
1406
1407 /*
1408 * yenta.c forces a secondary latency timer of 176.
1409 * Copy that behaviour here.
1410 */
1411 if (is_cardbus) {
1412 buses &= ~0xff000000;
1413 buses |= CARDBUS_LATENCY_TIMER << 24;
1414 }
1415
1416 /* We need to blast all three values with a single write */
1417 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1418
1419 if (!is_cardbus) {
1420 child->bridge_ctl = bctl;
1421 max = pci_scan_child_bus_extend(child, available_buses);
1422 } else {
1423
1424 /*
1425 * For CardBus bridges, we leave 4 bus numbers as
1426 * cards with a PCI-to-PCI bridge can be inserted
1427 * later.
1428 */
1429 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1430 struct pci_bus *parent = bus;
1431 if (pci_find_bus(pci_domain_nr(bus),
1432 max+i+1))
1433 break;
1434 while (parent->parent) {
1435 if ((!pcibios_assign_all_busses()) &&
1436 (parent->busn_res.end > max) &&
1437 (parent->busn_res.end <= max+i)) {
1438 j = 1;
1439 }
1440 parent = parent->parent;
1441 }
1442 if (j) {
1443
1444 /*
1445 * Often, there are two CardBus
1446 * bridges -- try to leave one
1447 * valid bus number for each one.
1448 */
1449 i /= 2;
1450 break;
1451 }
1452 }
1453 max += i;
1454 }
1455
1456 /*
1457 * Set subordinate bus number to its real value.
1458 * If fixed subordinate bus number exists from EA
1459 * capability then use it.
1460 */
1461 if (fixed_buses)
1462 max = fixed_sub;
1463 pci_bus_update_busn_res_end(child, max);
1464 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1465 }
1466
1467 sprintf(child->name,
1468 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1469 pci_domain_nr(bus), child->number);
1470
1471 /* Check that all devices are accessible */
1472 while (bus->parent) {
1473 if ((child->busn_res.end > bus->busn_res.end) ||
1474 (child->number > bus->busn_res.end) ||
1475 (child->number < bus->number) ||
1476 (child->busn_res.end < bus->number)) {
1477 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1478 &child->busn_res);
1479 break;
1480 }
1481 bus = bus->parent;
1482 }
1483
1484out:
1485 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1486
1487 pm_runtime_put(&dev->dev);
1488
1489 return max;
1490}
1491
1492/*
1493 * pci_scan_bridge() - Scan buses behind a bridge
1494 * @bus: Parent bus the bridge is on
1495 * @dev: Bridge itself
1496 * @max: Starting subordinate number of buses behind this bridge
1497 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1498 * that need to be reconfigured.
1499 *
1500 * If it's a bridge, configure it and scan the bus behind it.
1501 * For CardBus bridges, we don't scan behind as the devices will
1502 * be handled by the bridge driver itself.
1503 *
1504 * We need to process bridges in two passes -- first we scan those
1505 * already configured by the BIOS and after we are done with all of
1506 * them, we proceed to assigning numbers to the remaining buses in
1507 * order to avoid overlaps between old and new bus numbers.
1508 *
1509 * Return: New subordinate number covering all buses behind this bridge.
1510 */
1511int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1512{
1513 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1514}
1515EXPORT_SYMBOL(pci_scan_bridge);
1516
1517/*
1518 * Read interrupt line and base address registers.
1519 * The architecture-dependent code can tweak these, of course.
1520 */
1521static void pci_read_irq(struct pci_dev *dev)
1522{
1523 unsigned char irq;
1524
1525 /* VFs are not allowed to use INTx, so skip the config reads */
1526 if (dev->is_virtfn) {
1527 dev->pin = 0;
1528 dev->irq = 0;
1529 return;
1530 }
1531
1532 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1533 dev->pin = irq;
1534 if (irq)
1535 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1536 dev->irq = irq;
1537}
1538
1539void set_pcie_port_type(struct pci_dev *pdev)
1540{
1541 int pos;
1542 u16 reg16;
1543 u32 reg32;
1544 int type;
1545 struct pci_dev *parent;
1546
1547 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1548 if (!pos)
1549 return;
1550
1551 pdev->pcie_cap = pos;
1552 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1553 pdev->pcie_flags_reg = reg16;
1554 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1555 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1556
1557 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
1558 if (reg32 & PCI_EXP_LNKCAP_DLLLARC)
1559 pdev->link_active_reporting = 1;
1560
1561 parent = pci_upstream_bridge(pdev);
1562 if (!parent)
1563 return;
1564
1565 /*
1566 * Some systems do not identify their upstream/downstream ports
1567 * correctly so detect impossible configurations here and correct
1568 * the port type accordingly.
1569 */
1570 type = pci_pcie_type(pdev);
1571 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1572 /*
1573 * If pdev claims to be downstream port but the parent
1574 * device is also downstream port assume pdev is actually
1575 * upstream port.
1576 */
1577 if (pcie_downstream_port(parent)) {
1578 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1579 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1580 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1581 }
1582 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1583 /*
1584 * If pdev claims to be upstream port but the parent
1585 * device is also upstream port assume pdev is actually
1586 * downstream port.
1587 */
1588 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1589 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1590 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1591 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1592 }
1593 }
1594}
1595
1596void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1597{
1598 u32 reg32;
1599
1600 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1601 if (reg32 & PCI_EXP_SLTCAP_HPC)
1602 pdev->is_hotplug_bridge = 1;
1603}
1604
1605static void set_pcie_thunderbolt(struct pci_dev *dev)
1606{
1607 u16 vsec;
1608
1609 /* Is the device part of a Thunderbolt controller? */
1610 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1611 if (vsec)
1612 dev->is_thunderbolt = 1;
1613}
1614
1615static void set_pcie_untrusted(struct pci_dev *dev)
1616{
1617 struct pci_dev *parent;
1618
1619 /*
1620 * If the upstream bridge is untrusted we treat this device
1621 * untrusted as well.
1622 */
1623 parent = pci_upstream_bridge(dev);
1624 if (parent && (parent->untrusted || parent->external_facing))
1625 dev->untrusted = true;
1626}
1627
1628static void pci_set_removable(struct pci_dev *dev)
1629{
1630 struct pci_dev *parent = pci_upstream_bridge(dev);
1631
1632 /*
1633 * We (only) consider everything downstream from an external_facing
1634 * device to be removable by the user. We're mainly concerned with
1635 * consumer platforms with user accessible thunderbolt ports that are
1636 * vulnerable to DMA attacks, and we expect those ports to be marked by
1637 * the firmware as external_facing. Devices in traditional hotplug
1638 * slots can technically be removed, but the expectation is that unless
1639 * the port is marked with external_facing, such devices are less
1640 * accessible to user / may not be removed by end user, and thus not
1641 * exposed as "removable" to userspace.
1642 */
1643 if (parent &&
1644 (parent->external_facing || dev_is_removable(&parent->dev)))
1645 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1646}
1647
1648/**
1649 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1650 * @dev: PCI device
1651 *
1652 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1653 * when forwarding a type1 configuration request the bridge must check that
1654 * the extended register address field is zero. The bridge is not permitted
1655 * to forward the transactions and must handle it as an Unsupported Request.
1656 * Some bridges do not follow this rule and simply drop the extended register
1657 * bits, resulting in the standard config space being aliased, every 256
1658 * bytes across the entire configuration space. Test for this condition by
1659 * comparing the first dword of each potential alias to the vendor/device ID.
1660 * Known offenders:
1661 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1662 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1663 */
1664static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1665{
1666#ifdef CONFIG_PCI_QUIRKS
1667 int pos, ret;
1668 u32 header, tmp;
1669
1670 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1671
1672 for (pos = PCI_CFG_SPACE_SIZE;
1673 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1674 ret = pci_read_config_dword(dev, pos, &tmp);
1675 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp))
1676 return false;
1677 }
1678
1679 return true;
1680#else
1681 return false;
1682#endif
1683}
1684
1685/**
1686 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1687 * @dev: PCI device
1688 *
1689 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1690 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1691 * access it. Maybe we don't have a way to generate extended config space
1692 * accesses, or the device is behind a reverse Express bridge. So we try
1693 * reading the dword at 0x100 which must either be 0 or a valid extended
1694 * capability header.
1695 */
1696static int pci_cfg_space_size_ext(struct pci_dev *dev)
1697{
1698 u32 status;
1699 int pos = PCI_CFG_SPACE_SIZE;
1700
1701 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1702 return PCI_CFG_SPACE_SIZE;
1703 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1704 return PCI_CFG_SPACE_SIZE;
1705
1706 return PCI_CFG_SPACE_EXP_SIZE;
1707}
1708
1709int pci_cfg_space_size(struct pci_dev *dev)
1710{
1711 int pos;
1712 u32 status;
1713 u16 class;
1714
1715#ifdef CONFIG_PCI_IOV
1716 /*
1717 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1718 * implement a PCIe capability and therefore must implement extended
1719 * config space. We can skip the NO_EXTCFG test below and the
1720 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1721 * the fact that the SR-IOV capability on the PF resides in extended
1722 * config space and must be accessible and non-aliased to have enabled
1723 * support for this VF. This is a micro performance optimization for
1724 * systems supporting many VFs.
1725 */
1726 if (dev->is_virtfn)
1727 return PCI_CFG_SPACE_EXP_SIZE;
1728#endif
1729
1730 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1731 return PCI_CFG_SPACE_SIZE;
1732
1733 class = dev->class >> 8;
1734 if (class == PCI_CLASS_BRIDGE_HOST)
1735 return pci_cfg_space_size_ext(dev);
1736
1737 if (pci_is_pcie(dev))
1738 return pci_cfg_space_size_ext(dev);
1739
1740 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1741 if (!pos)
1742 return PCI_CFG_SPACE_SIZE;
1743
1744 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1745 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1746 return pci_cfg_space_size_ext(dev);
1747
1748 return PCI_CFG_SPACE_SIZE;
1749}
1750
1751static u32 pci_class(struct pci_dev *dev)
1752{
1753 u32 class;
1754
1755#ifdef CONFIG_PCI_IOV
1756 if (dev->is_virtfn)
1757 return dev->physfn->sriov->class;
1758#endif
1759 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1760 return class;
1761}
1762
1763static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1764{
1765#ifdef CONFIG_PCI_IOV
1766 if (dev->is_virtfn) {
1767 *vendor = dev->physfn->sriov->subsystem_vendor;
1768 *device = dev->physfn->sriov->subsystem_device;
1769 return;
1770 }
1771#endif
1772 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1773 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1774}
1775
1776static u8 pci_hdr_type(struct pci_dev *dev)
1777{
1778 u8 hdr_type;
1779
1780#ifdef CONFIG_PCI_IOV
1781 if (dev->is_virtfn)
1782 return dev->physfn->sriov->hdr_type;
1783#endif
1784 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1785 return hdr_type;
1786}
1787
1788#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1789
1790/**
1791 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1792 * @dev: PCI device
1793 *
1794 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1795 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1796 */
1797static int pci_intx_mask_broken(struct pci_dev *dev)
1798{
1799 u16 orig, toggle, new;
1800
1801 pci_read_config_word(dev, PCI_COMMAND, &orig);
1802 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1803 pci_write_config_word(dev, PCI_COMMAND, toggle);
1804 pci_read_config_word(dev, PCI_COMMAND, &new);
1805
1806 pci_write_config_word(dev, PCI_COMMAND, orig);
1807
1808 /*
1809 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1810 * r2.3, so strictly speaking, a device is not *broken* if it's not
1811 * writable. But we'll live with the misnomer for now.
1812 */
1813 if (new != toggle)
1814 return 1;
1815 return 0;
1816}
1817
1818static void early_dump_pci_device(struct pci_dev *pdev)
1819{
1820 u32 value[256 / 4];
1821 int i;
1822
1823 pci_info(pdev, "config space:\n");
1824
1825 for (i = 0; i < 256; i += 4)
1826 pci_read_config_dword(pdev, i, &value[i / 4]);
1827
1828 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1829 value, 256, false);
1830}
1831
1832static const char *pci_type_str(struct pci_dev *dev)
1833{
1834 static const char * const str[] = {
1835 "PCIe Endpoint",
1836 "PCIe Legacy Endpoint",
1837 "PCIe unknown",
1838 "PCIe unknown",
1839 "PCIe Root Port",
1840 "PCIe Switch Upstream Port",
1841 "PCIe Switch Downstream Port",
1842 "PCIe to PCI/PCI-X bridge",
1843 "PCI/PCI-X to PCIe bridge",
1844 "PCIe Root Complex Integrated Endpoint",
1845 "PCIe Root Complex Event Collector",
1846 };
1847 int type;
1848
1849 if (pci_is_pcie(dev)) {
1850 type = pci_pcie_type(dev);
1851 if (type < ARRAY_SIZE(str))
1852 return str[type];
1853
1854 return "PCIe unknown";
1855 }
1856
1857 switch (dev->hdr_type) {
1858 case PCI_HEADER_TYPE_NORMAL:
1859 return "conventional PCI endpoint";
1860 case PCI_HEADER_TYPE_BRIDGE:
1861 return "conventional PCI bridge";
1862 case PCI_HEADER_TYPE_CARDBUS:
1863 return "CardBus bridge";
1864 default:
1865 return "conventional PCI";
1866 }
1867}
1868
1869/**
1870 * pci_setup_device - Fill in class and map information of a device
1871 * @dev: the device structure to fill
1872 *
1873 * Initialize the device structure with information about the device's
1874 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1875 * Called at initialisation of the PCI subsystem and by CardBus services.
1876 * Returns 0 on success and negative if unknown type of device (not normal,
1877 * bridge or CardBus).
1878 */
1879int pci_setup_device(struct pci_dev *dev)
1880{
1881 u32 class;
1882 u16 cmd;
1883 u8 hdr_type;
1884 int err, pos = 0;
1885 struct pci_bus_region region;
1886 struct resource *res;
1887
1888 hdr_type = pci_hdr_type(dev);
1889
1890 dev->sysdata = dev->bus->sysdata;
1891 dev->dev.parent = dev->bus->bridge;
1892 dev->dev.bus = &pci_bus_type;
1893 dev->hdr_type = hdr_type & 0x7f;
1894 dev->multifunction = !!(hdr_type & 0x80);
1895 dev->error_state = pci_channel_io_normal;
1896 set_pcie_port_type(dev);
1897
1898 err = pci_set_of_node(dev);
1899 if (err)
1900 return err;
1901 pci_set_acpi_fwnode(dev);
1902
1903 pci_dev_assign_slot(dev);
1904
1905 /*
1906 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1907 * set this higher, assuming the system even supports it.
1908 */
1909 dev->dma_mask = 0xffffffff;
1910
1911 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1912 dev->bus->number, PCI_SLOT(dev->devfn),
1913 PCI_FUNC(dev->devfn));
1914
1915 class = pci_class(dev);
1916
1917 dev->revision = class & 0xff;
1918 dev->class = class >> 8; /* upper 3 bytes */
1919
1920 if (pci_early_dump)
1921 early_dump_pci_device(dev);
1922
1923 /* Need to have dev->class ready */
1924 dev->cfg_size = pci_cfg_space_size(dev);
1925
1926 /* Need to have dev->cfg_size ready */
1927 set_pcie_thunderbolt(dev);
1928
1929 set_pcie_untrusted(dev);
1930
1931 /* "Unknown power state" */
1932 dev->current_state = PCI_UNKNOWN;
1933
1934 /* Early fixups, before probing the BARs */
1935 pci_fixup_device(pci_fixup_early, dev);
1936
1937 pci_set_removable(dev);
1938
1939 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n",
1940 dev->vendor, dev->device, dev->hdr_type, dev->class,
1941 pci_type_str(dev));
1942
1943 /* Device class may be changed after fixup */
1944 class = dev->class >> 8;
1945
1946 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1947 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1948 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1949 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1950 cmd &= ~PCI_COMMAND_IO;
1951 cmd &= ~PCI_COMMAND_MEMORY;
1952 pci_write_config_word(dev, PCI_COMMAND, cmd);
1953 }
1954 }
1955
1956 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1957
1958 switch (dev->hdr_type) { /* header type */
1959 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1960 if (class == PCI_CLASS_BRIDGE_PCI)
1961 goto bad;
1962 pci_read_irq(dev);
1963 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1964
1965 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1966
1967 /*
1968 * Do the ugly legacy mode stuff here rather than broken chip
1969 * quirk code. Legacy mode ATA controllers have fixed
1970 * addresses. These are not always echoed in BAR0-3, and
1971 * BAR0-3 in a few cases contain junk!
1972 */
1973 if (class == PCI_CLASS_STORAGE_IDE) {
1974 u8 progif;
1975 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1976 if ((progif & 1) == 0) {
1977 region.start = 0x1F0;
1978 region.end = 0x1F7;
1979 res = &dev->resource[0];
1980 res->flags = LEGACY_IO_RESOURCE;
1981 pcibios_bus_to_resource(dev->bus, res, ®ion);
1982 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n",
1983 res);
1984 region.start = 0x3F6;
1985 region.end = 0x3F6;
1986 res = &dev->resource[1];
1987 res->flags = LEGACY_IO_RESOURCE;
1988 pcibios_bus_to_resource(dev->bus, res, ®ion);
1989 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n",
1990 res);
1991 }
1992 if ((progif & 4) == 0) {
1993 region.start = 0x170;
1994 region.end = 0x177;
1995 res = &dev->resource[2];
1996 res->flags = LEGACY_IO_RESOURCE;
1997 pcibios_bus_to_resource(dev->bus, res, ®ion);
1998 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n",
1999 res);
2000 region.start = 0x376;
2001 region.end = 0x376;
2002 res = &dev->resource[3];
2003 res->flags = LEGACY_IO_RESOURCE;
2004 pcibios_bus_to_resource(dev->bus, res, ®ion);
2005 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n",
2006 res);
2007 }
2008 }
2009 break;
2010
2011 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
2012 /*
2013 * The PCI-to-PCI bridge spec requires that subtractive
2014 * decoding (i.e. transparent) bridge must have programming
2015 * interface code of 0x01.
2016 */
2017 pci_read_irq(dev);
2018 dev->transparent = ((dev->class & 0xff) == 1);
2019 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
2020 pci_read_bridge_windows(dev);
2021 set_pcie_hotplug_bridge(dev);
2022 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
2023 if (pos) {
2024 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
2025 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
2026 }
2027 break;
2028
2029 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
2030 if (class != PCI_CLASS_BRIDGE_CARDBUS)
2031 goto bad;
2032 pci_read_irq(dev);
2033 pci_read_bases(dev, 1, 0);
2034 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
2035 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
2036 break;
2037
2038 default: /* unknown header */
2039 pci_err(dev, "unknown header type %02x, ignoring device\n",
2040 dev->hdr_type);
2041 pci_release_of_node(dev);
2042 return -EIO;
2043
2044 bad:
2045 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
2046 dev->class, dev->hdr_type);
2047 dev->class = PCI_CLASS_NOT_DEFINED << 8;
2048 }
2049
2050 /* We found a fine healthy device, go go go... */
2051 return 0;
2052}
2053
2054static void pci_configure_mps(struct pci_dev *dev)
2055{
2056 struct pci_dev *bridge = pci_upstream_bridge(dev);
2057 int mps, mpss, p_mps, rc;
2058
2059 if (!pci_is_pcie(dev))
2060 return;
2061
2062 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2063 if (dev->is_virtfn)
2064 return;
2065
2066 /*
2067 * For Root Complex Integrated Endpoints, program the maximum
2068 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2069 */
2070 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2071 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2072 mps = 128;
2073 else
2074 mps = 128 << dev->pcie_mpss;
2075 rc = pcie_set_mps(dev, mps);
2076 if (rc) {
2077 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2078 mps);
2079 }
2080 return;
2081 }
2082
2083 if (!bridge || !pci_is_pcie(bridge))
2084 return;
2085
2086 mps = pcie_get_mps(dev);
2087 p_mps = pcie_get_mps(bridge);
2088
2089 if (mps == p_mps)
2090 return;
2091
2092 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2093 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2094 mps, pci_name(bridge), p_mps);
2095 return;
2096 }
2097
2098 /*
2099 * Fancier MPS configuration is done later by
2100 * pcie_bus_configure_settings()
2101 */
2102 if (pcie_bus_config != PCIE_BUS_DEFAULT)
2103 return;
2104
2105 mpss = 128 << dev->pcie_mpss;
2106 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2107 pcie_set_mps(bridge, mpss);
2108 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2109 mpss, p_mps, 128 << bridge->pcie_mpss);
2110 p_mps = pcie_get_mps(bridge);
2111 }
2112
2113 rc = pcie_set_mps(dev, p_mps);
2114 if (rc) {
2115 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2116 p_mps);
2117 return;
2118 }
2119
2120 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2121 p_mps, mps, mpss);
2122}
2123
2124int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2125{
2126 struct pci_host_bridge *host;
2127 u32 cap;
2128 u16 ctl;
2129 int ret;
2130
2131 if (!pci_is_pcie(dev))
2132 return 0;
2133
2134 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2135 if (ret)
2136 return 0;
2137
2138 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2139 return 0;
2140
2141 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2142 if (ret)
2143 return 0;
2144
2145 host = pci_find_host_bridge(dev->bus);
2146 if (!host)
2147 return 0;
2148
2149 /*
2150 * If some device in the hierarchy doesn't handle Extended Tags
2151 * correctly, make sure they're disabled.
2152 */
2153 if (host->no_ext_tags) {
2154 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2155 pci_info(dev, "disabling Extended Tags\n");
2156 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2157 PCI_EXP_DEVCTL_EXT_TAG);
2158 }
2159 return 0;
2160 }
2161
2162 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2163 pci_info(dev, "enabling Extended Tags\n");
2164 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2165 PCI_EXP_DEVCTL_EXT_TAG);
2166 }
2167 return 0;
2168}
2169
2170/**
2171 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2172 * @dev: PCI device to query
2173 *
2174 * Returns true if the device has enabled relaxed ordering attribute.
2175 */
2176bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2177{
2178 u16 v;
2179
2180 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2181
2182 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2183}
2184EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2185
2186static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2187{
2188 struct pci_dev *root;
2189
2190 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */
2191 if (dev->is_virtfn)
2192 return;
2193
2194 if (!pcie_relaxed_ordering_enabled(dev))
2195 return;
2196
2197 /*
2198 * For now, we only deal with Relaxed Ordering issues with Root
2199 * Ports. Peer-to-Peer DMA is another can of worms.
2200 */
2201 root = pcie_find_root_port(dev);
2202 if (!root)
2203 return;
2204
2205 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2206 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2207 PCI_EXP_DEVCTL_RELAX_EN);
2208 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2209 }
2210}
2211
2212static void pci_configure_ltr(struct pci_dev *dev)
2213{
2214#ifdef CONFIG_PCIEASPM
2215 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2216 struct pci_dev *bridge;
2217 u32 cap, ctl;
2218
2219 if (!pci_is_pcie(dev))
2220 return;
2221
2222 /* Read L1 PM substate capabilities */
2223 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2224
2225 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2226 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2227 return;
2228
2229 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2230 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2231 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2232 dev->ltr_path = 1;
2233 return;
2234 }
2235
2236 bridge = pci_upstream_bridge(dev);
2237 if (bridge && bridge->ltr_path)
2238 dev->ltr_path = 1;
2239
2240 return;
2241 }
2242
2243 if (!host->native_ltr)
2244 return;
2245
2246 /*
2247 * Software must not enable LTR in an Endpoint unless the Root
2248 * Complex and all intermediate Switches indicate support for LTR.
2249 * PCIe r4.0, sec 6.18.
2250 */
2251 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2252 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2253 PCI_EXP_DEVCTL2_LTR_EN);
2254 dev->ltr_path = 1;
2255 return;
2256 }
2257
2258 /*
2259 * If we're configuring a hot-added device, LTR was likely
2260 * disabled in the upstream bridge, so re-enable it before enabling
2261 * it in the new device.
2262 */
2263 bridge = pci_upstream_bridge(dev);
2264 if (bridge && bridge->ltr_path) {
2265 pci_bridge_reconfigure_ltr(dev);
2266 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2267 PCI_EXP_DEVCTL2_LTR_EN);
2268 dev->ltr_path = 1;
2269 }
2270#endif
2271}
2272
2273static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2274{
2275#ifdef CONFIG_PCI_PASID
2276 struct pci_dev *bridge;
2277 int pcie_type;
2278 u32 cap;
2279
2280 if (!pci_is_pcie(dev))
2281 return;
2282
2283 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2284 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2285 return;
2286
2287 pcie_type = pci_pcie_type(dev);
2288 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2289 pcie_type == PCI_EXP_TYPE_RC_END)
2290 dev->eetlp_prefix_path = 1;
2291 else {
2292 bridge = pci_upstream_bridge(dev);
2293 if (bridge && bridge->eetlp_prefix_path)
2294 dev->eetlp_prefix_path = 1;
2295 }
2296#endif
2297}
2298
2299static void pci_configure_serr(struct pci_dev *dev)
2300{
2301 u16 control;
2302
2303 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2304
2305 /*
2306 * A bridge will not forward ERR_ messages coming from an
2307 * endpoint unless SERR# forwarding is enabled.
2308 */
2309 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2310 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2311 control |= PCI_BRIDGE_CTL_SERR;
2312 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2313 }
2314 }
2315}
2316
2317static void pci_configure_device(struct pci_dev *dev)
2318{
2319 pci_configure_mps(dev);
2320 pci_configure_extended_tags(dev, NULL);
2321 pci_configure_relaxed_ordering(dev);
2322 pci_configure_ltr(dev);
2323 pci_configure_eetlp_prefix(dev);
2324 pci_configure_serr(dev);
2325
2326 pci_acpi_program_hp_params(dev);
2327}
2328
2329static void pci_release_capabilities(struct pci_dev *dev)
2330{
2331 pci_aer_exit(dev);
2332 pci_rcec_exit(dev);
2333 pci_iov_release(dev);
2334 pci_free_cap_save_buffers(dev);
2335}
2336
2337/**
2338 * pci_release_dev - Free a PCI device structure when all users of it are
2339 * finished
2340 * @dev: device that's been disconnected
2341 *
2342 * Will be called only by the device core when all users of this PCI device are
2343 * done.
2344 */
2345static void pci_release_dev(struct device *dev)
2346{
2347 struct pci_dev *pci_dev;
2348
2349 pci_dev = to_pci_dev(dev);
2350 pci_release_capabilities(pci_dev);
2351 pci_release_of_node(pci_dev);
2352 pcibios_release_device(pci_dev);
2353 pci_bus_put(pci_dev->bus);
2354 kfree(pci_dev->driver_override);
2355 bitmap_free(pci_dev->dma_alias_mask);
2356 dev_dbg(dev, "device released\n");
2357 kfree(pci_dev);
2358}
2359
2360struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2361{
2362 struct pci_dev *dev;
2363
2364 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2365 if (!dev)
2366 return NULL;
2367
2368 INIT_LIST_HEAD(&dev->bus_list);
2369 dev->dev.type = &pci_dev_type;
2370 dev->bus = pci_bus_get(bus);
2371 dev->driver_exclusive_resource = (struct resource) {
2372 .name = "PCI Exclusive",
2373 .start = 0,
2374 .end = -1,
2375 };
2376
2377 spin_lock_init(&dev->pcie_cap_lock);
2378#ifdef CONFIG_PCI_MSI
2379 raw_spin_lock_init(&dev->msi_lock);
2380#endif
2381 return dev;
2382}
2383EXPORT_SYMBOL(pci_alloc_dev);
2384
2385static bool pci_bus_crs_vendor_id(u32 l)
2386{
2387 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
2388}
2389
2390static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2391 int timeout)
2392{
2393 int delay = 1;
2394
2395 if (!pci_bus_crs_vendor_id(*l))
2396 return true; /* not a CRS completion */
2397
2398 if (!timeout)
2399 return false; /* CRS, but caller doesn't want to wait */
2400
2401 /*
2402 * We got the reserved Vendor ID that indicates a completion with
2403 * Configuration Request Retry Status (CRS). Retry until we get a
2404 * valid Vendor ID or we time out.
2405 */
2406 while (pci_bus_crs_vendor_id(*l)) {
2407 if (delay > timeout) {
2408 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2409 pci_domain_nr(bus), bus->number,
2410 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2411
2412 return false;
2413 }
2414 if (delay >= 1000)
2415 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2416 pci_domain_nr(bus), bus->number,
2417 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2418
2419 msleep(delay);
2420 delay *= 2;
2421
2422 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2423 return false;
2424 }
2425
2426 if (delay >= 1000)
2427 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2428 pci_domain_nr(bus), bus->number,
2429 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2430
2431 return true;
2432}
2433
2434bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2435 int timeout)
2436{
2437 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2438 return false;
2439
2440 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2441 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2442 *l == 0x0000ffff || *l == 0xffff0000)
2443 return false;
2444
2445 if (pci_bus_crs_vendor_id(*l))
2446 return pci_bus_wait_crs(bus, devfn, l, timeout);
2447
2448 return true;
2449}
2450
2451bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2452 int timeout)
2453{
2454#ifdef CONFIG_PCI_QUIRKS
2455 struct pci_dev *bridge = bus->self;
2456
2457 /*
2458 * Certain IDT switches have an issue where they improperly trigger
2459 * ACS Source Validation errors on completions for config reads.
2460 */
2461 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2462 bridge->device == 0x80b5)
2463 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2464#endif
2465
2466 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2467}
2468EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2469
2470/*
2471 * Read the config data for a PCI device, sanity-check it,
2472 * and fill in the dev structure.
2473 */
2474static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2475{
2476 struct pci_dev *dev;
2477 u32 l;
2478
2479 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2480 return NULL;
2481
2482 dev = pci_alloc_dev(bus);
2483 if (!dev)
2484 return NULL;
2485
2486 dev->devfn = devfn;
2487 dev->vendor = l & 0xffff;
2488 dev->device = (l >> 16) & 0xffff;
2489
2490 if (pci_setup_device(dev)) {
2491 pci_bus_put(dev->bus);
2492 kfree(dev);
2493 return NULL;
2494 }
2495
2496 return dev;
2497}
2498
2499void pcie_report_downtraining(struct pci_dev *dev)
2500{
2501 if (!pci_is_pcie(dev))
2502 return;
2503
2504 /* Look from the device up to avoid downstream ports with no devices */
2505 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2506 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2507 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2508 return;
2509
2510 /* Multi-function PCIe devices share the same link/status */
2511 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2512 return;
2513
2514 /* Print link status only if the device is constrained by the fabric */
2515 __pcie_print_link_status(dev, false);
2516}
2517
2518static void pci_init_capabilities(struct pci_dev *dev)
2519{
2520 pci_ea_init(dev); /* Enhanced Allocation */
2521 pci_msi_init(dev); /* Disable MSI */
2522 pci_msix_init(dev); /* Disable MSI-X */
2523
2524 /* Buffers for saving PCIe and PCI-X capabilities */
2525 pci_allocate_cap_save_buffers(dev);
2526
2527 pci_pm_init(dev); /* Power Management */
2528 pci_vpd_init(dev); /* Vital Product Data */
2529 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2530 pci_iov_init(dev); /* Single Root I/O Virtualization */
2531 pci_ats_init(dev); /* Address Translation Services */
2532 pci_pri_init(dev); /* Page Request Interface */
2533 pci_pasid_init(dev); /* Process Address Space ID */
2534 pci_acs_init(dev); /* Access Control Services */
2535 pci_ptm_init(dev); /* Precision Time Measurement */
2536 pci_aer_init(dev); /* Advanced Error Reporting */
2537 pci_dpc_init(dev); /* Downstream Port Containment */
2538 pci_rcec_init(dev); /* Root Complex Event Collector */
2539 pci_doe_init(dev); /* Data Object Exchange */
2540
2541 pcie_report_downtraining(dev);
2542 pci_init_reset_methods(dev);
2543}
2544
2545/*
2546 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2547 * devices. Firmware interfaces that can select the MSI domain on a
2548 * per-device basis should be called from here.
2549 */
2550static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2551{
2552 struct irq_domain *d;
2553
2554 /*
2555 * If a domain has been set through the pcibios_device_add()
2556 * callback, then this is the one (platform code knows best).
2557 */
2558 d = dev_get_msi_domain(&dev->dev);
2559 if (d)
2560 return d;
2561
2562 /*
2563 * Let's see if we have a firmware interface able to provide
2564 * the domain.
2565 */
2566 d = pci_msi_get_device_domain(dev);
2567 if (d)
2568 return d;
2569
2570 return NULL;
2571}
2572
2573static void pci_set_msi_domain(struct pci_dev *dev)
2574{
2575 struct irq_domain *d;
2576
2577 /*
2578 * If the platform or firmware interfaces cannot supply a
2579 * device-specific MSI domain, then inherit the default domain
2580 * from the host bridge itself.
2581 */
2582 d = pci_dev_msi_domain(dev);
2583 if (!d)
2584 d = dev_get_msi_domain(&dev->bus->dev);
2585
2586 dev_set_msi_domain(&dev->dev, d);
2587}
2588
2589void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2590{
2591 int ret;
2592
2593 pci_configure_device(dev);
2594
2595 device_initialize(&dev->dev);
2596 dev->dev.release = pci_release_dev;
2597
2598 set_dev_node(&dev->dev, pcibus_to_node(bus));
2599 dev->dev.dma_mask = &dev->dma_mask;
2600 dev->dev.dma_parms = &dev->dma_parms;
2601 dev->dev.coherent_dma_mask = 0xffffffffull;
2602
2603 dma_set_max_seg_size(&dev->dev, 65536);
2604 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2605
2606 pcie_failed_link_retrain(dev);
2607
2608 /* Fix up broken headers */
2609 pci_fixup_device(pci_fixup_header, dev);
2610
2611 pci_reassigndev_resource_alignment(dev);
2612
2613 dev->state_saved = false;
2614
2615 pci_init_capabilities(dev);
2616
2617 /*
2618 * Add the device to our list of discovered devices
2619 * and the bus list for fixup functions, etc.
2620 */
2621 down_write(&pci_bus_sem);
2622 list_add_tail(&dev->bus_list, &bus->devices);
2623 up_write(&pci_bus_sem);
2624
2625 ret = pcibios_device_add(dev);
2626 WARN_ON(ret < 0);
2627
2628 /* Set up MSI IRQ domain */
2629 pci_set_msi_domain(dev);
2630
2631 /* Notifier could use PCI capabilities */
2632 dev->match_driver = false;
2633 ret = device_add(&dev->dev);
2634 WARN_ON(ret < 0);
2635}
2636
2637struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2638{
2639 struct pci_dev *dev;
2640
2641 dev = pci_get_slot(bus, devfn);
2642 if (dev) {
2643 pci_dev_put(dev);
2644 return dev;
2645 }
2646
2647 dev = pci_scan_device(bus, devfn);
2648 if (!dev)
2649 return NULL;
2650
2651 pci_device_add(dev, bus);
2652
2653 return dev;
2654}
2655EXPORT_SYMBOL(pci_scan_single_device);
2656
2657static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2658{
2659 int pos;
2660 u16 cap = 0;
2661 unsigned int next_fn;
2662
2663 if (!dev)
2664 return -ENODEV;
2665
2666 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2667 if (!pos)
2668 return -ENODEV;
2669
2670 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2671 next_fn = PCI_ARI_CAP_NFN(cap);
2672 if (next_fn <= fn)
2673 return -ENODEV; /* protect against malformed list */
2674
2675 return next_fn;
2676}
2677
2678static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2679{
2680 if (pci_ari_enabled(bus))
2681 return next_ari_fn(bus, dev, fn);
2682
2683 if (fn >= 7)
2684 return -ENODEV;
2685 /* only multifunction devices may have more functions */
2686 if (dev && !dev->multifunction)
2687 return -ENODEV;
2688
2689 return fn + 1;
2690}
2691
2692static int only_one_child(struct pci_bus *bus)
2693{
2694 struct pci_dev *bridge = bus->self;
2695
2696 /*
2697 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2698 * we scan for all possible devices, not just Device 0.
2699 */
2700 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2701 return 0;
2702
2703 /*
2704 * A PCIe Downstream Port normally leads to a Link with only Device
2705 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2706 * only for Device 0 in that situation.
2707 */
2708 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2709 return 1;
2710
2711 return 0;
2712}
2713
2714/**
2715 * pci_scan_slot - Scan a PCI slot on a bus for devices
2716 * @bus: PCI bus to scan
2717 * @devfn: slot number to scan (must have zero function)
2718 *
2719 * Scan a PCI slot on the specified PCI bus for devices, adding
2720 * discovered devices to the @bus->devices list. New devices
2721 * will not have is_added set.
2722 *
2723 * Returns the number of new devices found.
2724 */
2725int pci_scan_slot(struct pci_bus *bus, int devfn)
2726{
2727 struct pci_dev *dev;
2728 int fn = 0, nr = 0;
2729
2730 if (only_one_child(bus) && (devfn > 0))
2731 return 0; /* Already scanned the entire slot */
2732
2733 do {
2734 dev = pci_scan_single_device(bus, devfn + fn);
2735 if (dev) {
2736 if (!pci_dev_is_added(dev))
2737 nr++;
2738 if (fn > 0)
2739 dev->multifunction = 1;
2740 } else if (fn == 0) {
2741 /*
2742 * Function 0 is required unless we are running on
2743 * a hypervisor that passes through individual PCI
2744 * functions.
2745 */
2746 if (!hypervisor_isolated_pci_functions())
2747 break;
2748 }
2749 fn = next_fn(bus, dev, fn);
2750 } while (fn >= 0);
2751
2752 /* Only one slot has PCIe device */
2753 if (bus->self && nr)
2754 pcie_aspm_init_link_state(bus->self);
2755
2756 return nr;
2757}
2758EXPORT_SYMBOL(pci_scan_slot);
2759
2760static int pcie_find_smpss(struct pci_dev *dev, void *data)
2761{
2762 u8 *smpss = data;
2763
2764 if (!pci_is_pcie(dev))
2765 return 0;
2766
2767 /*
2768 * We don't have a way to change MPS settings on devices that have
2769 * drivers attached. A hot-added device might support only the minimum
2770 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2771 * where devices may be hot-added, we limit the fabric MPS to 128 so
2772 * hot-added devices will work correctly.
2773 *
2774 * However, if we hot-add a device to a slot directly below a Root
2775 * Port, it's impossible for there to be other existing devices below
2776 * the port. We don't limit the MPS in this case because we can
2777 * reconfigure MPS on both the Root Port and the hot-added device,
2778 * and there are no other devices involved.
2779 *
2780 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2781 */
2782 if (dev->is_hotplug_bridge &&
2783 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2784 *smpss = 0;
2785
2786 if (*smpss > dev->pcie_mpss)
2787 *smpss = dev->pcie_mpss;
2788
2789 return 0;
2790}
2791
2792static void pcie_write_mps(struct pci_dev *dev, int mps)
2793{
2794 int rc;
2795
2796 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2797 mps = 128 << dev->pcie_mpss;
2798
2799 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2800 dev->bus->self)
2801
2802 /*
2803 * For "Performance", the assumption is made that
2804 * downstream communication will never be larger than
2805 * the MRRS. So, the MPS only needs to be configured
2806 * for the upstream communication. This being the case,
2807 * walk from the top down and set the MPS of the child
2808 * to that of the parent bus.
2809 *
2810 * Configure the device MPS with the smaller of the
2811 * device MPSS or the bridge MPS (which is assumed to be
2812 * properly configured at this point to the largest
2813 * allowable MPS based on its parent bus).
2814 */
2815 mps = min(mps, pcie_get_mps(dev->bus->self));
2816 }
2817
2818 rc = pcie_set_mps(dev, mps);
2819 if (rc)
2820 pci_err(dev, "Failed attempting to set the MPS\n");
2821}
2822
2823static void pcie_write_mrrs(struct pci_dev *dev)
2824{
2825 int rc, mrrs;
2826
2827 /*
2828 * In the "safe" case, do not configure the MRRS. There appear to be
2829 * issues with setting MRRS to 0 on a number of devices.
2830 */
2831 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2832 return;
2833
2834 /*
2835 * For max performance, the MRRS must be set to the largest supported
2836 * value. However, it cannot be configured larger than the MPS the
2837 * device or the bus can support. This should already be properly
2838 * configured by a prior call to pcie_write_mps().
2839 */
2840 mrrs = pcie_get_mps(dev);
2841
2842 /*
2843 * MRRS is a R/W register. Invalid values can be written, but a
2844 * subsequent read will verify if the value is acceptable or not.
2845 * If the MRRS value provided is not acceptable (e.g., too large),
2846 * shrink the value until it is acceptable to the HW.
2847 */
2848 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2849 rc = pcie_set_readrq(dev, mrrs);
2850 if (!rc)
2851 break;
2852
2853 pci_warn(dev, "Failed attempting to set the MRRS\n");
2854 mrrs /= 2;
2855 }
2856
2857 if (mrrs < 128)
2858 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2859}
2860
2861static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2862{
2863 int mps, orig_mps;
2864
2865 if (!pci_is_pcie(dev))
2866 return 0;
2867
2868 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2869 pcie_bus_config == PCIE_BUS_DEFAULT)
2870 return 0;
2871
2872 mps = 128 << *(u8 *)data;
2873 orig_mps = pcie_get_mps(dev);
2874
2875 pcie_write_mps(dev, mps);
2876 pcie_write_mrrs(dev);
2877
2878 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2879 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2880 orig_mps, pcie_get_readrq(dev));
2881
2882 return 0;
2883}
2884
2885/*
2886 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2887 * parents then children fashion. If this changes, then this code will not
2888 * work as designed.
2889 */
2890void pcie_bus_configure_settings(struct pci_bus *bus)
2891{
2892 u8 smpss = 0;
2893
2894 if (!bus->self)
2895 return;
2896
2897 if (!pci_is_pcie(bus->self))
2898 return;
2899
2900 /*
2901 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2902 * to be aware of the MPS of the destination. To work around this,
2903 * simply force the MPS of the entire system to the smallest possible.
2904 */
2905 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2906 smpss = 0;
2907
2908 if (pcie_bus_config == PCIE_BUS_SAFE) {
2909 smpss = bus->self->pcie_mpss;
2910
2911 pcie_find_smpss(bus->self, &smpss);
2912 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2913 }
2914
2915 pcie_bus_configure_set(bus->self, &smpss);
2916 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2917}
2918EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2919
2920/*
2921 * Called after each bus is probed, but before its children are examined. This
2922 * is marked as __weak because multiple architectures define it.
2923 */
2924void __weak pcibios_fixup_bus(struct pci_bus *bus)
2925{
2926 /* nothing to do, expected to be removed in the future */
2927}
2928
2929/**
2930 * pci_scan_child_bus_extend() - Scan devices below a bus
2931 * @bus: Bus to scan for devices
2932 * @available_buses: Total number of buses available (%0 does not try to
2933 * extend beyond the minimal)
2934 *
2935 * Scans devices below @bus including subordinate buses. Returns new
2936 * subordinate number including all the found devices. Passing
2937 * @available_buses causes the remaining bus space to be distributed
2938 * equally between hotplug-capable bridges to allow future extension of the
2939 * hierarchy.
2940 */
2941static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2942 unsigned int available_buses)
2943{
2944 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2945 unsigned int start = bus->busn_res.start;
2946 unsigned int devfn, cmax, max = start;
2947 struct pci_dev *dev;
2948
2949 dev_dbg(&bus->dev, "scanning bus\n");
2950
2951 /* Go find them, Rover! */
2952 for (devfn = 0; devfn < 256; devfn += 8)
2953 pci_scan_slot(bus, devfn);
2954
2955 /* Reserve buses for SR-IOV capability */
2956 used_buses = pci_iov_bus_range(bus);
2957 max += used_buses;
2958
2959 /*
2960 * After performing arch-dependent fixup of the bus, look behind
2961 * all PCI-to-PCI bridges on this bus.
2962 */
2963 if (!bus->is_added) {
2964 dev_dbg(&bus->dev, "fixups for bus\n");
2965 pcibios_fixup_bus(bus);
2966 bus->is_added = 1;
2967 }
2968
2969 /*
2970 * Calculate how many hotplug bridges and normal bridges there
2971 * are on this bus. We will distribute the additional available
2972 * buses between hotplug bridges.
2973 */
2974 for_each_pci_bridge(dev, bus) {
2975 if (dev->is_hotplug_bridge)
2976 hotplug_bridges++;
2977 else
2978 normal_bridges++;
2979 }
2980
2981 /*
2982 * Scan bridges that are already configured. We don't touch them
2983 * unless they are misconfigured (which will be done in the second
2984 * scan below).
2985 */
2986 for_each_pci_bridge(dev, bus) {
2987 cmax = max;
2988 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2989
2990 /*
2991 * Reserve one bus for each bridge now to avoid extending
2992 * hotplug bridges too much during the second scan below.
2993 */
2994 used_buses++;
2995 if (max - cmax > 1)
2996 used_buses += max - cmax - 1;
2997 }
2998
2999 /* Scan bridges that need to be reconfigured */
3000 for_each_pci_bridge(dev, bus) {
3001 unsigned int buses = 0;
3002
3003 if (!hotplug_bridges && normal_bridges == 1) {
3004 /*
3005 * There is only one bridge on the bus (upstream
3006 * port) so it gets all available buses which it
3007 * can then distribute to the possible hotplug
3008 * bridges below.
3009 */
3010 buses = available_buses;
3011 } else if (dev->is_hotplug_bridge) {
3012 /*
3013 * Distribute the extra buses between hotplug
3014 * bridges if any.
3015 */
3016 buses = available_buses / hotplug_bridges;
3017 buses = min(buses, available_buses - used_buses + 1);
3018 }
3019
3020 cmax = max;
3021 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
3022 /* One bus is already accounted so don't add it again */
3023 if (max - cmax > 1)
3024 used_buses += max - cmax - 1;
3025 }
3026
3027 /*
3028 * Make sure a hotplug bridge has at least the minimum requested
3029 * number of buses but allow it to grow up to the maximum available
3030 * bus number if there is room.
3031 */
3032 if (bus->self && bus->self->is_hotplug_bridge) {
3033 used_buses = max_t(unsigned int, available_buses,
3034 pci_hotplug_bus_size - 1);
3035 if (max - start < used_buses) {
3036 max = start + used_buses;
3037
3038 /* Do not allocate more buses than we have room left */
3039 if (max > bus->busn_res.end)
3040 max = bus->busn_res.end;
3041
3042 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
3043 &bus->busn_res, max - start);
3044 }
3045 }
3046
3047 /*
3048 * We've scanned the bus and so we know all about what's on
3049 * the other side of any bridges that may be on this bus plus
3050 * any devices.
3051 *
3052 * Return how far we've got finding sub-buses.
3053 */
3054 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
3055 return max;
3056}
3057
3058/**
3059 * pci_scan_child_bus() - Scan devices below a bus
3060 * @bus: Bus to scan for devices
3061 *
3062 * Scans devices below @bus including subordinate buses. Returns new
3063 * subordinate number including all the found devices.
3064 */
3065unsigned int pci_scan_child_bus(struct pci_bus *bus)
3066{
3067 return pci_scan_child_bus_extend(bus, 0);
3068}
3069EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3070
3071/**
3072 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3073 * @bridge: Host bridge to set up
3074 *
3075 * Default empty implementation. Replace with an architecture-specific setup
3076 * routine, if necessary.
3077 */
3078int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3079{
3080 return 0;
3081}
3082
3083void __weak pcibios_add_bus(struct pci_bus *bus)
3084{
3085}
3086
3087void __weak pcibios_remove_bus(struct pci_bus *bus)
3088{
3089}
3090
3091struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3092 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3093{
3094 int error;
3095 struct pci_host_bridge *bridge;
3096
3097 bridge = pci_alloc_host_bridge(0);
3098 if (!bridge)
3099 return NULL;
3100
3101 bridge->dev.parent = parent;
3102
3103 list_splice_init(resources, &bridge->windows);
3104 bridge->sysdata = sysdata;
3105 bridge->busnr = bus;
3106 bridge->ops = ops;
3107
3108 error = pci_register_host_bridge(bridge);
3109 if (error < 0)
3110 goto err_out;
3111
3112 return bridge->bus;
3113
3114err_out:
3115 put_device(&bridge->dev);
3116 return NULL;
3117}
3118EXPORT_SYMBOL_GPL(pci_create_root_bus);
3119
3120int pci_host_probe(struct pci_host_bridge *bridge)
3121{
3122 struct pci_bus *bus, *child;
3123 int ret;
3124
3125 ret = pci_scan_root_bus_bridge(bridge);
3126 if (ret < 0) {
3127 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3128 return ret;
3129 }
3130
3131 bus = bridge->bus;
3132
3133 /*
3134 * We insert PCI resources into the iomem_resource and
3135 * ioport_resource trees in either pci_bus_claim_resources()
3136 * or pci_bus_assign_resources().
3137 */
3138 if (pci_has_flag(PCI_PROBE_ONLY)) {
3139 pci_bus_claim_resources(bus);
3140 } else {
3141 pci_bus_size_bridges(bus);
3142 pci_bus_assign_resources(bus);
3143
3144 list_for_each_entry(child, &bus->children, node)
3145 pcie_bus_configure_settings(child);
3146 }
3147
3148 pci_bus_add_devices(bus);
3149 return 0;
3150}
3151EXPORT_SYMBOL_GPL(pci_host_probe);
3152
3153int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3154{
3155 struct resource *res = &b->busn_res;
3156 struct resource *parent_res, *conflict;
3157
3158 res->start = bus;
3159 res->end = bus_max;
3160 res->flags = IORESOURCE_BUS;
3161
3162 if (!pci_is_root_bus(b))
3163 parent_res = &b->parent->busn_res;
3164 else {
3165 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3166 res->flags |= IORESOURCE_PCI_FIXED;
3167 }
3168
3169 conflict = request_resource_conflict(parent_res, res);
3170
3171 if (conflict)
3172 dev_info(&b->dev,
3173 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3174 res, pci_is_root_bus(b) ? "domain " : "",
3175 parent_res, conflict->name, conflict);
3176
3177 return conflict == NULL;
3178}
3179
3180int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3181{
3182 struct resource *res = &b->busn_res;
3183 struct resource old_res = *res;
3184 resource_size_t size;
3185 int ret;
3186
3187 if (res->start > bus_max)
3188 return -EINVAL;
3189
3190 size = bus_max - res->start + 1;
3191 ret = adjust_resource(res, res->start, size);
3192 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3193 &old_res, ret ? "can not be" : "is", bus_max);
3194
3195 if (!ret && !res->parent)
3196 pci_bus_insert_busn_res(b, res->start, res->end);
3197
3198 return ret;
3199}
3200
3201void pci_bus_release_busn_res(struct pci_bus *b)
3202{
3203 struct resource *res = &b->busn_res;
3204 int ret;
3205
3206 if (!res->flags || !res->parent)
3207 return;
3208
3209 ret = release_resource(res);
3210 dev_info(&b->dev, "busn_res: %pR %s released\n",
3211 res, ret ? "can not be" : "is");
3212}
3213
3214int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3215{
3216 struct resource_entry *window;
3217 bool found = false;
3218 struct pci_bus *b;
3219 int max, bus, ret;
3220
3221 if (!bridge)
3222 return -EINVAL;
3223
3224 resource_list_for_each_entry(window, &bridge->windows)
3225 if (window->res->flags & IORESOURCE_BUS) {
3226 bridge->busnr = window->res->start;
3227 found = true;
3228 break;
3229 }
3230
3231 ret = pci_register_host_bridge(bridge);
3232 if (ret < 0)
3233 return ret;
3234
3235 b = bridge->bus;
3236 bus = bridge->busnr;
3237
3238 if (!found) {
3239 dev_info(&b->dev,
3240 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3241 bus);
3242 pci_bus_insert_busn_res(b, bus, 255);
3243 }
3244
3245 max = pci_scan_child_bus(b);
3246
3247 if (!found)
3248 pci_bus_update_busn_res_end(b, max);
3249
3250 return 0;
3251}
3252EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3253
3254struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3255 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3256{
3257 struct resource_entry *window;
3258 bool found = false;
3259 struct pci_bus *b;
3260 int max;
3261
3262 resource_list_for_each_entry(window, resources)
3263 if (window->res->flags & IORESOURCE_BUS) {
3264 found = true;
3265 break;
3266 }
3267
3268 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3269 if (!b)
3270 return NULL;
3271
3272 if (!found) {
3273 dev_info(&b->dev,
3274 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3275 bus);
3276 pci_bus_insert_busn_res(b, bus, 255);
3277 }
3278
3279 max = pci_scan_child_bus(b);
3280
3281 if (!found)
3282 pci_bus_update_busn_res_end(b, max);
3283
3284 return b;
3285}
3286EXPORT_SYMBOL(pci_scan_root_bus);
3287
3288struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3289 void *sysdata)
3290{
3291 LIST_HEAD(resources);
3292 struct pci_bus *b;
3293
3294 pci_add_resource(&resources, &ioport_resource);
3295 pci_add_resource(&resources, &iomem_resource);
3296 pci_add_resource(&resources, &busn_resource);
3297 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3298 if (b) {
3299 pci_scan_child_bus(b);
3300 } else {
3301 pci_free_resource_list(&resources);
3302 }
3303 return b;
3304}
3305EXPORT_SYMBOL(pci_scan_bus);
3306
3307/**
3308 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3309 * @bridge: PCI bridge for the bus to scan
3310 *
3311 * Scan a PCI bus and child buses for new devices, add them,
3312 * and enable them, resizing bridge mmio/io resource if necessary
3313 * and possible. The caller must ensure the child devices are already
3314 * removed for resizing to occur.
3315 *
3316 * Returns the max number of subordinate bus discovered.
3317 */
3318unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3319{
3320 unsigned int max;
3321 struct pci_bus *bus = bridge->subordinate;
3322
3323 max = pci_scan_child_bus(bus);
3324
3325 pci_assign_unassigned_bridge_resources(bridge);
3326
3327 pci_bus_add_devices(bus);
3328
3329 return max;
3330}
3331
3332/**
3333 * pci_rescan_bus - Scan a PCI bus for devices
3334 * @bus: PCI bus to scan
3335 *
3336 * Scan a PCI bus and child buses for new devices, add them,
3337 * and enable them.
3338 *
3339 * Returns the max number of subordinate bus discovered.
3340 */
3341unsigned int pci_rescan_bus(struct pci_bus *bus)
3342{
3343 unsigned int max;
3344
3345 max = pci_scan_child_bus(bus);
3346 pci_assign_unassigned_bus_resources(bus);
3347 pci_bus_add_devices(bus);
3348
3349 return max;
3350}
3351EXPORT_SYMBOL_GPL(pci_rescan_bus);
3352
3353/*
3354 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3355 * routines should always be executed under this mutex.
3356 */
3357static DEFINE_MUTEX(pci_rescan_remove_lock);
3358
3359void pci_lock_rescan_remove(void)
3360{
3361 mutex_lock(&pci_rescan_remove_lock);
3362}
3363EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3364
3365void pci_unlock_rescan_remove(void)
3366{
3367 mutex_unlock(&pci_rescan_remove_lock);
3368}
3369EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3370
3371static int __init pci_sort_bf_cmp(const struct device *d_a,
3372 const struct device *d_b)
3373{
3374 const struct pci_dev *a = to_pci_dev(d_a);
3375 const struct pci_dev *b = to_pci_dev(d_b);
3376
3377 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3378 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3379
3380 if (a->bus->number < b->bus->number) return -1;
3381 else if (a->bus->number > b->bus->number) return 1;
3382
3383 if (a->devfn < b->devfn) return -1;
3384 else if (a->devfn > b->devfn) return 1;
3385
3386 return 0;
3387}
3388
3389void __init pci_sort_breadthfirst(void)
3390{
3391 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3392}
3393
3394int pci_hp_add_bridge(struct pci_dev *dev)
3395{
3396 struct pci_bus *parent = dev->bus;
3397 int busnr, start = parent->busn_res.start;
3398 unsigned int available_buses = 0;
3399 int end = parent->busn_res.end;
3400
3401 for (busnr = start; busnr <= end; busnr++) {
3402 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3403 break;
3404 }
3405 if (busnr-- > end) {
3406 pci_err(dev, "No bus number available for hot-added bridge\n");
3407 return -1;
3408 }
3409
3410 /* Scan bridges that are already configured */
3411 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3412
3413 /*
3414 * Distribute the available bus numbers between hotplug-capable
3415 * bridges to make extending the chain later possible.
3416 */
3417 available_buses = end - busnr;
3418
3419 /* Scan bridges that need to be reconfigured */
3420 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3421
3422 if (!dev->subordinate)
3423 return -1;
3424
3425 return 0;
3426}
3427EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_device.h>
12#include <linux/of_pci.h>
13#include <linux/pci_hotplug.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/cpumask.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34/* Ugh. Need to stop exporting this to modules. */
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68/*
69 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
71 * is no device to be found on the pci_bus_type.
72 */
73int no_pci_devices(void)
74{
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82}
83EXPORT_SYMBOL(no_pci_devices);
84
85/*
86 * PCI Bus Class
87 */
88static void release_pcibus_dev(struct device *dev)
89{
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96}
97
98static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102};
103
104static int __init pcibus_class_init(void)
105{
106 return class_register(&pcibus_class);
107}
108postcore_initcall(pcibus_class_init);
109
110static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111{
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
115
116 /*
117 * Get the lowest of them to find the decode size, and from that
118 * the extent.
119 */
120 size = size & ~(size-1);
121
122 /*
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
125 */
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
127 return 0;
128
129 return size;
130}
131
132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
133{
134 u32 mem_type;
135 unsigned long flags;
136
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
141 }
142
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
147
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153 /* 1M mem BAR treated as 32-bit BAR */
154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
157 break;
158 default:
159 /* mem unknown type treated as 32-bit BAR */
160 break;
161 }
162 return flags;
163}
164
165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166
167/**
168 * pci_read_base - Read a PCI BAR
169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
173 *
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 */
176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
178{
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
181 u16 orig_cmd;
182 struct pci_bus_region region, inverted_region;
183
184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185
186 /* No printks while decoding is disabled! */
187 if (!dev->mmio_always_on) {
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
190 pci_write_config_word(dev, PCI_COMMAND,
191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
192 }
193 }
194
195 res->name = pci_name(dev);
196
197 pci_read_config_dword(dev, pos, &l);
198 pci_write_config_dword(dev, pos, l | mask);
199 pci_read_config_dword(dev, pos, &sz);
200 pci_write_config_dword(dev, pos, l);
201
202 /*
203 * All bits set in sz means the device isn't working properly.
204 * If the BAR isn't implemented, all bits must be 0. If it's a
205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
206 * 1 must be clear.
207 */
208 if (sz == 0xffffffff)
209 sz = 0;
210
211 /*
212 * I don't know how l can have all bits set. Copied from old code.
213 * Maybe it fixes a bug on some ancient platform.
214 */
215 if (l == 0xffffffff)
216 l = 0;
217
218 if (type == pci_bar_unknown) {
219 res->flags = decode_bar(dev, l);
220 res->flags |= IORESOURCE_SIZEALIGN;
221 if (res->flags & IORESOURCE_IO) {
222 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 } else {
226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
229 }
230 } else {
231 if (l & PCI_ROM_ADDRESS_ENABLE)
232 res->flags |= IORESOURCE_ROM_ENABLE;
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = PCI_ROM_ADDRESS_MASK;
236 }
237
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
243
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
247 }
248
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251
252 if (!sz64)
253 goto fail;
254
255 sz64 = pci_size(l64, sz64, mask64);
256 if (!sz64) {
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 pos);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64 - 1;
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64 - 1;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290 /*
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
295 *
296 * resource_to_bus(bus_to_resource(A)) == A
297 *
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
300 */
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 if (dev->non_compliant_bars)
326 return;
327
328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
329 if (dev->is_virtfn)
330 return;
331
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
336 }
337
338 if (rom) {
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 }
345}
346
347static void pci_read_bridge_windows(struct pci_dev *bridge)
348{
349 u16 io;
350 u32 pmem, tmp;
351
352 pci_read_config_word(bridge, PCI_IO_BASE, &io);
353 if (!io) {
354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355 pci_read_config_word(bridge, PCI_IO_BASE, &io);
356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
357 }
358 if (io)
359 bridge->io_window = 1;
360
361 /*
362 * DECchip 21050 pass 2 errata: the bridge may miss an address
363 * disconnect boundary by one PCI data phase. Workaround: do not
364 * use prefetching on this device.
365 */
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367 return;
368
369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370 if (!pmem) {
371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372 0xffe0fff0);
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
375 }
376 if (!pmem)
377 return;
378
379 bridge->pref_window = 1;
380
381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
382
383 /*
384 * Bridge claims to have a 64-bit prefetchable memory
385 * window; verify that the upper bits are actually
386 * writable.
387 */
388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390 0xffffffff);
391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393 if (tmp)
394 bridge->pref_64_window = 1;
395 }
396}
397
398static void pci_read_bridge_io(struct pci_bus *child)
399{
400 struct pci_dev *dev = child->self;
401 u8 io_base_lo, io_limit_lo;
402 unsigned long io_mask, io_granularity, base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
405
406 io_mask = PCI_IO_RANGE_MASK;
407 io_granularity = 0x1000;
408 if (dev->io_window_1k) {
409 /* Support 1K I/O space granularity */
410 io_mask = PCI_IO_1K_RANGE_MASK;
411 io_granularity = 0x400;
412 }
413
414 res = child->resource[0];
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
417 base = (io_base_lo & io_mask) << 8;
418 limit = (io_limit_lo & io_mask) << 8;
419
420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
421 u16 io_base_hi, io_limit_hi;
422
423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
425 base |= ((unsigned long) io_base_hi << 16);
426 limit |= ((unsigned long) io_limit_hi << 16);
427 }
428
429 if (base <= limit) {
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
431 region.start = base;
432 region.end = limit + io_granularity - 1;
433 pcibios_bus_to_resource(dev->bus, res, ®ion);
434 pci_info(dev, " bridge window %pR\n", res);
435 }
436}
437
438static void pci_read_bridge_mmio(struct pci_bus *child)
439{
440 struct pci_dev *dev = child->self;
441 u16 mem_base_lo, mem_limit_lo;
442 unsigned long base, limit;
443 struct pci_bus_region region;
444 struct resource *res;
445
446 res = child->resource[1];
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 if (base <= limit) {
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
453 region.start = base;
454 region.end = limit + 0xfffff;
455 pcibios_bus_to_resource(dev->bus, res, ®ion);
456 pci_info(dev, " bridge window %pR\n", res);
457 }
458}
459
460static void pci_read_bridge_mmio_pref(struct pci_bus *child)
461{
462 struct pci_dev *dev = child->self;
463 u16 mem_base_lo, mem_limit_lo;
464 u64 base64, limit64;
465 pci_bus_addr_t base, limit;
466 struct pci_bus_region region;
467 struct resource *res;
468
469 res = child->resource[2];
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
474
475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
476 u32 mem_base_hi, mem_limit_hi;
477
478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
480
481 /*
482 * Some bridges set the base > limit by default, and some
483 * (broken) BIOSes do not initialize them. If we find
484 * this, just assume they are not being used.
485 */
486 if (mem_base_hi <= mem_limit_hi) {
487 base64 |= (u64) mem_base_hi << 32;
488 limit64 |= (u64) mem_limit_hi << 32;
489 }
490 }
491
492 base = (pci_bus_addr_t) base64;
493 limit = (pci_bus_addr_t) limit64;
494
495 if (base != base64) {
496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
497 (unsigned long long) base64);
498 return;
499 }
500
501 if (base <= limit) {
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
503 IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (res->flags & PCI_PREF_RANGE_TYPE_64)
505 res->flags |= IORESOURCE_MEM_64;
506 region.start = base;
507 region.end = limit + 0xfffff;
508 pcibios_bus_to_resource(dev->bus, res, ®ion);
509 pci_info(dev, " bridge window %pR\n", res);
510 }
511}
512
513void pci_read_bridge_bases(struct pci_bus *child)
514{
515 struct pci_dev *dev = child->self;
516 struct resource *res;
517 int i;
518
519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
520 return;
521
522 pci_info(dev, "PCI bridge to %pR%s\n",
523 &child->busn_res,
524 dev->transparent ? " (subtractive decode)" : "");
525
526 pci_bus_remove_resources(child);
527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
529
530 pci_read_bridge_io(child);
531 pci_read_bridge_mmio(child);
532 pci_read_bridge_mmio_pref(child);
533
534 if (dev->transparent) {
535 pci_bus_for_each_resource(child->parent, res, i) {
536 if (res && res->flags) {
537 pci_bus_add_resource(child, res,
538 PCI_SUBTRACTIVE_DECODE);
539 pci_info(dev, " bridge window %pR (subtractive decode)\n",
540 res);
541 }
542 }
543 }
544}
545
546static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
547{
548 struct pci_bus *b;
549
550 b = kzalloc(sizeof(*b), GFP_KERNEL);
551 if (!b)
552 return NULL;
553
554 INIT_LIST_HEAD(&b->node);
555 INIT_LIST_HEAD(&b->children);
556 INIT_LIST_HEAD(&b->devices);
557 INIT_LIST_HEAD(&b->slots);
558 INIT_LIST_HEAD(&b->resources);
559 b->max_bus_speed = PCI_SPEED_UNKNOWN;
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
561#ifdef CONFIG_PCI_DOMAINS_GENERIC
562 if (parent)
563 b->domain_nr = parent->domain_nr;
564#endif
565 return b;
566}
567
568static void pci_release_host_bridge_dev(struct device *dev)
569{
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
571
572 if (bridge->release_fn)
573 bridge->release_fn(bridge);
574
575 pci_free_resource_list(&bridge->windows);
576 pci_free_resource_list(&bridge->dma_ranges);
577 kfree(bridge);
578}
579
580static void pci_init_host_bridge(struct pci_host_bridge *bridge)
581{
582 INIT_LIST_HEAD(&bridge->windows);
583 INIT_LIST_HEAD(&bridge->dma_ranges);
584
585 /*
586 * We assume we can manage these PCIe features. Some systems may
587 * reserve these for use by the platform itself, e.g., an ACPI BIOS
588 * may implement its own AER handling and use _OSC to prevent the
589 * OS from interfering.
590 */
591 bridge->native_aer = 1;
592 bridge->native_pcie_hotplug = 1;
593 bridge->native_shpc_hotplug = 1;
594 bridge->native_pme = 1;
595 bridge->native_ltr = 1;
596 bridge->native_dpc = 1;
597
598 device_initialize(&bridge->dev);
599}
600
601struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
602{
603 struct pci_host_bridge *bridge;
604
605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
606 if (!bridge)
607 return NULL;
608
609 pci_init_host_bridge(bridge);
610 bridge->dev.release = pci_release_host_bridge_dev;
611
612 return bridge;
613}
614EXPORT_SYMBOL(pci_alloc_host_bridge);
615
616static void devm_pci_alloc_host_bridge_release(void *data)
617{
618 pci_free_host_bridge(data);
619}
620
621struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
622 size_t priv)
623{
624 int ret;
625 struct pci_host_bridge *bridge;
626
627 bridge = pci_alloc_host_bridge(priv);
628 if (!bridge)
629 return NULL;
630
631 bridge->dev.parent = dev;
632
633 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
634 bridge);
635 if (ret)
636 return NULL;
637
638 ret = devm_of_pci_bridge_init(dev, bridge);
639 if (ret)
640 return NULL;
641
642 return bridge;
643}
644EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
645
646void pci_free_host_bridge(struct pci_host_bridge *bridge)
647{
648 put_device(&bridge->dev);
649}
650EXPORT_SYMBOL(pci_free_host_bridge);
651
652/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
653static const unsigned char pcix_bus_speed[] = {
654 PCI_SPEED_UNKNOWN, /* 0 */
655 PCI_SPEED_66MHz_PCIX, /* 1 */
656 PCI_SPEED_100MHz_PCIX, /* 2 */
657 PCI_SPEED_133MHz_PCIX, /* 3 */
658 PCI_SPEED_UNKNOWN, /* 4 */
659 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
660 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
661 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
662 PCI_SPEED_UNKNOWN, /* 8 */
663 PCI_SPEED_66MHz_PCIX_266, /* 9 */
664 PCI_SPEED_100MHz_PCIX_266, /* A */
665 PCI_SPEED_133MHz_PCIX_266, /* B */
666 PCI_SPEED_UNKNOWN, /* C */
667 PCI_SPEED_66MHz_PCIX_533, /* D */
668 PCI_SPEED_100MHz_PCIX_533, /* E */
669 PCI_SPEED_133MHz_PCIX_533 /* F */
670};
671
672/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
673const unsigned char pcie_link_speed[] = {
674 PCI_SPEED_UNKNOWN, /* 0 */
675 PCIE_SPEED_2_5GT, /* 1 */
676 PCIE_SPEED_5_0GT, /* 2 */
677 PCIE_SPEED_8_0GT, /* 3 */
678 PCIE_SPEED_16_0GT, /* 4 */
679 PCIE_SPEED_32_0GT, /* 5 */
680 PCI_SPEED_UNKNOWN, /* 6 */
681 PCI_SPEED_UNKNOWN, /* 7 */
682 PCI_SPEED_UNKNOWN, /* 8 */
683 PCI_SPEED_UNKNOWN, /* 9 */
684 PCI_SPEED_UNKNOWN, /* A */
685 PCI_SPEED_UNKNOWN, /* B */
686 PCI_SPEED_UNKNOWN, /* C */
687 PCI_SPEED_UNKNOWN, /* D */
688 PCI_SPEED_UNKNOWN, /* E */
689 PCI_SPEED_UNKNOWN /* F */
690};
691EXPORT_SYMBOL_GPL(pcie_link_speed);
692
693const char *pci_speed_string(enum pci_bus_speed speed)
694{
695 /* Indexed by the pci_bus_speed enum */
696 static const char *speed_strings[] = {
697 "33 MHz PCI", /* 0x00 */
698 "66 MHz PCI", /* 0x01 */
699 "66 MHz PCI-X", /* 0x02 */
700 "100 MHz PCI-X", /* 0x03 */
701 "133 MHz PCI-X", /* 0x04 */
702 NULL, /* 0x05 */
703 NULL, /* 0x06 */
704 NULL, /* 0x07 */
705 NULL, /* 0x08 */
706 "66 MHz PCI-X 266", /* 0x09 */
707 "100 MHz PCI-X 266", /* 0x0a */
708 "133 MHz PCI-X 266", /* 0x0b */
709 "Unknown AGP", /* 0x0c */
710 "1x AGP", /* 0x0d */
711 "2x AGP", /* 0x0e */
712 "4x AGP", /* 0x0f */
713 "8x AGP", /* 0x10 */
714 "66 MHz PCI-X 533", /* 0x11 */
715 "100 MHz PCI-X 533", /* 0x12 */
716 "133 MHz PCI-X 533", /* 0x13 */
717 "2.5 GT/s PCIe", /* 0x14 */
718 "5.0 GT/s PCIe", /* 0x15 */
719 "8.0 GT/s PCIe", /* 0x16 */
720 "16.0 GT/s PCIe", /* 0x17 */
721 "32.0 GT/s PCIe", /* 0x18 */
722 };
723
724 if (speed < ARRAY_SIZE(speed_strings))
725 return speed_strings[speed];
726 return "Unknown";
727}
728EXPORT_SYMBOL_GPL(pci_speed_string);
729
730void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
731{
732 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
733}
734EXPORT_SYMBOL_GPL(pcie_update_link_speed);
735
736static unsigned char agp_speeds[] = {
737 AGP_UNKNOWN,
738 AGP_1X,
739 AGP_2X,
740 AGP_4X,
741 AGP_8X
742};
743
744static enum pci_bus_speed agp_speed(int agp3, int agpstat)
745{
746 int index = 0;
747
748 if (agpstat & 4)
749 index = 3;
750 else if (agpstat & 2)
751 index = 2;
752 else if (agpstat & 1)
753 index = 1;
754 else
755 goto out;
756
757 if (agp3) {
758 index += 2;
759 if (index == 5)
760 index = 0;
761 }
762
763 out:
764 return agp_speeds[index];
765}
766
767static void pci_set_bus_speed(struct pci_bus *bus)
768{
769 struct pci_dev *bridge = bus->self;
770 int pos;
771
772 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
773 if (!pos)
774 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
775 if (pos) {
776 u32 agpstat, agpcmd;
777
778 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
779 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
780
781 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
782 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
783 }
784
785 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
786 if (pos) {
787 u16 status;
788 enum pci_bus_speed max;
789
790 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
791 &status);
792
793 if (status & PCI_X_SSTATUS_533MHZ) {
794 max = PCI_SPEED_133MHz_PCIX_533;
795 } else if (status & PCI_X_SSTATUS_266MHZ) {
796 max = PCI_SPEED_133MHz_PCIX_266;
797 } else if (status & PCI_X_SSTATUS_133MHZ) {
798 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
799 max = PCI_SPEED_133MHz_PCIX_ECC;
800 else
801 max = PCI_SPEED_133MHz_PCIX;
802 } else {
803 max = PCI_SPEED_66MHz_PCIX;
804 }
805
806 bus->max_bus_speed = max;
807 bus->cur_bus_speed = pcix_bus_speed[
808 (status & PCI_X_SSTATUS_FREQ) >> 6];
809
810 return;
811 }
812
813 if (pci_is_pcie(bridge)) {
814 u32 linkcap;
815 u16 linksta;
816
817 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
818 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
819 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
820
821 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
822 pcie_update_link_speed(bus, linksta);
823 }
824}
825
826static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
827{
828 struct irq_domain *d;
829
830 /*
831 * Any firmware interface that can resolve the msi_domain
832 * should be called from here.
833 */
834 d = pci_host_bridge_of_msi_domain(bus);
835 if (!d)
836 d = pci_host_bridge_acpi_msi_domain(bus);
837
838#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
839 /*
840 * If no IRQ domain was found via the OF tree, try looking it up
841 * directly through the fwnode_handle.
842 */
843 if (!d) {
844 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
845
846 if (fwnode)
847 d = irq_find_matching_fwnode(fwnode,
848 DOMAIN_BUS_PCI_MSI);
849 }
850#endif
851
852 return d;
853}
854
855static void pci_set_bus_msi_domain(struct pci_bus *bus)
856{
857 struct irq_domain *d;
858 struct pci_bus *b;
859
860 /*
861 * The bus can be a root bus, a subordinate bus, or a virtual bus
862 * created by an SR-IOV device. Walk up to the first bridge device
863 * found or derive the domain from the host bridge.
864 */
865 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
866 if (b->self)
867 d = dev_get_msi_domain(&b->self->dev);
868 }
869
870 if (!d)
871 d = pci_host_bridge_msi_domain(b);
872
873 dev_set_msi_domain(&bus->dev, d);
874}
875
876static int pci_register_host_bridge(struct pci_host_bridge *bridge)
877{
878 struct device *parent = bridge->dev.parent;
879 struct resource_entry *window, *n;
880 struct pci_bus *bus, *b;
881 resource_size_t offset;
882 LIST_HEAD(resources);
883 struct resource *res;
884 char addr[64], *fmt;
885 const char *name;
886 int err;
887
888 bus = pci_alloc_bus(NULL);
889 if (!bus)
890 return -ENOMEM;
891
892 bridge->bus = bus;
893
894 /* Temporarily move resources off the list */
895 list_splice_init(&bridge->windows, &resources);
896 bus->sysdata = bridge->sysdata;
897 bus->msi = bridge->msi;
898 bus->ops = bridge->ops;
899 bus->number = bus->busn_res.start = bridge->busnr;
900#ifdef CONFIG_PCI_DOMAINS_GENERIC
901 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
902#endif
903
904 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
905 if (b) {
906 /* Ignore it if we already got here via a different bridge */
907 dev_dbg(&b->dev, "bus already known\n");
908 err = -EEXIST;
909 goto free;
910 }
911
912 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
913 bridge->busnr);
914
915 err = pcibios_root_bridge_prepare(bridge);
916 if (err)
917 goto free;
918
919 err = device_add(&bridge->dev);
920 if (err) {
921 put_device(&bridge->dev);
922 goto free;
923 }
924 bus->bridge = get_device(&bridge->dev);
925 device_enable_async_suspend(bus->bridge);
926 pci_set_bus_of_node(bus);
927 pci_set_bus_msi_domain(bus);
928
929 if (!parent)
930 set_dev_node(bus->bridge, pcibus_to_node(bus));
931
932 bus->dev.class = &pcibus_class;
933 bus->dev.parent = bus->bridge;
934
935 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
936 name = dev_name(&bus->dev);
937
938 err = device_register(&bus->dev);
939 if (err)
940 goto unregister;
941
942 pcibios_add_bus(bus);
943
944 /* Create legacy_io and legacy_mem files for this bus */
945 pci_create_legacy_files(bus);
946
947 if (parent)
948 dev_info(parent, "PCI host bridge to bus %s\n", name);
949 else
950 pr_info("PCI host bridge to bus %s\n", name);
951
952 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
953 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
954
955 /* Add initial resources to the bus */
956 resource_list_for_each_entry_safe(window, n, &resources) {
957 list_move_tail(&window->node, &bridge->windows);
958 offset = window->offset;
959 res = window->res;
960
961 if (res->flags & IORESOURCE_BUS)
962 pci_bus_insert_busn_res(bus, bus->number, res->end);
963 else
964 pci_bus_add_resource(bus, res, 0);
965
966 if (offset) {
967 if (resource_type(res) == IORESOURCE_IO)
968 fmt = " (bus address [%#06llx-%#06llx])";
969 else
970 fmt = " (bus address [%#010llx-%#010llx])";
971
972 snprintf(addr, sizeof(addr), fmt,
973 (unsigned long long)(res->start - offset),
974 (unsigned long long)(res->end - offset));
975 } else
976 addr[0] = '\0';
977
978 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
979 }
980
981 down_write(&pci_bus_sem);
982 list_add_tail(&bus->node, &pci_root_buses);
983 up_write(&pci_bus_sem);
984
985 return 0;
986
987unregister:
988 put_device(&bridge->dev);
989 device_del(&bridge->dev);
990
991free:
992 kfree(bus);
993 return err;
994}
995
996static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
997{
998 int pos;
999 u32 status;
1000
1001 /*
1002 * If extended config space isn't accessible on a bridge's primary
1003 * bus, we certainly can't access it on the secondary bus.
1004 */
1005 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1006 return false;
1007
1008 /*
1009 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1010 * extended config space is accessible on the primary, it's also
1011 * accessible on the secondary.
1012 */
1013 if (pci_is_pcie(bridge) &&
1014 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1015 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1016 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1017 return true;
1018
1019 /*
1020 * For the other bridge types:
1021 * - PCI-to-PCI bridges
1022 * - PCIe-to-PCI/PCI-X forward bridges
1023 * - PCI/PCI-X-to-PCIe reverse bridges
1024 * extended config space on the secondary side is only accessible
1025 * if the bridge supports PCI-X Mode 2.
1026 */
1027 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1028 if (!pos)
1029 return false;
1030
1031 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1032 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1033}
1034
1035static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1036 struct pci_dev *bridge, int busnr)
1037{
1038 struct pci_bus *child;
1039 int i;
1040 int ret;
1041
1042 /* Allocate a new bus and inherit stuff from the parent */
1043 child = pci_alloc_bus(parent);
1044 if (!child)
1045 return NULL;
1046
1047 child->parent = parent;
1048 child->ops = parent->ops;
1049 child->msi = parent->msi;
1050 child->sysdata = parent->sysdata;
1051 child->bus_flags = parent->bus_flags;
1052
1053 /*
1054 * Initialize some portions of the bus device, but don't register
1055 * it now as the parent is not properly set up yet.
1056 */
1057 child->dev.class = &pcibus_class;
1058 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1059
1060 /* Set up the primary, secondary and subordinate bus numbers */
1061 child->number = child->busn_res.start = busnr;
1062 child->primary = parent->busn_res.start;
1063 child->busn_res.end = 0xff;
1064
1065 if (!bridge) {
1066 child->dev.parent = parent->bridge;
1067 goto add_dev;
1068 }
1069
1070 child->self = bridge;
1071 child->bridge = get_device(&bridge->dev);
1072 child->dev.parent = child->bridge;
1073 pci_set_bus_of_node(child);
1074 pci_set_bus_speed(child);
1075
1076 /*
1077 * Check whether extended config space is accessible on the child
1078 * bus. Note that we currently assume it is always accessible on
1079 * the root bus.
1080 */
1081 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1082 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1083 pci_info(child, "extended config space not accessible\n");
1084 }
1085
1086 /* Set up default resource pointers and names */
1087 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1088 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1089 child->resource[i]->name = child->name;
1090 }
1091 bridge->subordinate = child;
1092
1093add_dev:
1094 pci_set_bus_msi_domain(child);
1095 ret = device_register(&child->dev);
1096 WARN_ON(ret < 0);
1097
1098 pcibios_add_bus(child);
1099
1100 if (child->ops->add_bus) {
1101 ret = child->ops->add_bus(child);
1102 if (WARN_ON(ret < 0))
1103 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1104 }
1105
1106 /* Create legacy_io and legacy_mem files for this bus */
1107 pci_create_legacy_files(child);
1108
1109 return child;
1110}
1111
1112struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1113 int busnr)
1114{
1115 struct pci_bus *child;
1116
1117 child = pci_alloc_child_bus(parent, dev, busnr);
1118 if (child) {
1119 down_write(&pci_bus_sem);
1120 list_add_tail(&child->node, &parent->children);
1121 up_write(&pci_bus_sem);
1122 }
1123 return child;
1124}
1125EXPORT_SYMBOL(pci_add_new_bus);
1126
1127static void pci_enable_crs(struct pci_dev *pdev)
1128{
1129 u16 root_cap = 0;
1130
1131 /* Enable CRS Software Visibility if supported */
1132 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1133 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1134 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1135 PCI_EXP_RTCTL_CRSSVE);
1136}
1137
1138static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1139 unsigned int available_buses);
1140/**
1141 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1142 * numbers from EA capability.
1143 * @dev: Bridge
1144 * @sec: updated with secondary bus number from EA
1145 * @sub: updated with subordinate bus number from EA
1146 *
1147 * If @dev is a bridge with EA capability that specifies valid secondary
1148 * and subordinate bus numbers, return true with the bus numbers in @sec
1149 * and @sub. Otherwise return false.
1150 */
1151static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1152{
1153 int ea, offset;
1154 u32 dw;
1155 u8 ea_sec, ea_sub;
1156
1157 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1158 return false;
1159
1160 /* find PCI EA capability in list */
1161 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1162 if (!ea)
1163 return false;
1164
1165 offset = ea + PCI_EA_FIRST_ENT;
1166 pci_read_config_dword(dev, offset, &dw);
1167 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1168 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1169 if (ea_sec == 0 || ea_sub < ea_sec)
1170 return false;
1171
1172 *sec = ea_sec;
1173 *sub = ea_sub;
1174 return true;
1175}
1176
1177/*
1178 * pci_scan_bridge_extend() - Scan buses behind a bridge
1179 * @bus: Parent bus the bridge is on
1180 * @dev: Bridge itself
1181 * @max: Starting subordinate number of buses behind this bridge
1182 * @available_buses: Total number of buses available for this bridge and
1183 * the devices below. After the minimal bus space has
1184 * been allocated the remaining buses will be
1185 * distributed equally between hotplug-capable bridges.
1186 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1187 * that need to be reconfigured.
1188 *
1189 * If it's a bridge, configure it and scan the bus behind it.
1190 * For CardBus bridges, we don't scan behind as the devices will
1191 * be handled by the bridge driver itself.
1192 *
1193 * We need to process bridges in two passes -- first we scan those
1194 * already configured by the BIOS and after we are done with all of
1195 * them, we proceed to assigning numbers to the remaining buses in
1196 * order to avoid overlaps between old and new bus numbers.
1197 *
1198 * Return: New subordinate number covering all buses behind this bridge.
1199 */
1200static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1201 int max, unsigned int available_buses,
1202 int pass)
1203{
1204 struct pci_bus *child;
1205 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1206 u32 buses, i, j = 0;
1207 u16 bctl;
1208 u8 primary, secondary, subordinate;
1209 int broken = 0;
1210 bool fixed_buses;
1211 u8 fixed_sec, fixed_sub;
1212 int next_busnr;
1213
1214 /*
1215 * Make sure the bridge is powered on to be able to access config
1216 * space of devices below it.
1217 */
1218 pm_runtime_get_sync(&dev->dev);
1219
1220 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1221 primary = buses & 0xFF;
1222 secondary = (buses >> 8) & 0xFF;
1223 subordinate = (buses >> 16) & 0xFF;
1224
1225 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1226 secondary, subordinate, pass);
1227
1228 if (!primary && (primary != bus->number) && secondary && subordinate) {
1229 pci_warn(dev, "Primary bus is hard wired to 0\n");
1230 primary = bus->number;
1231 }
1232
1233 /* Check if setup is sensible at all */
1234 if (!pass &&
1235 (primary != bus->number || secondary <= bus->number ||
1236 secondary > subordinate)) {
1237 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1238 secondary, subordinate);
1239 broken = 1;
1240 }
1241
1242 /*
1243 * Disable Master-Abort Mode during probing to avoid reporting of
1244 * bus errors in some architectures.
1245 */
1246 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1247 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1248 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1249
1250 pci_enable_crs(dev);
1251
1252 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1253 !is_cardbus && !broken) {
1254 unsigned int cmax;
1255
1256 /*
1257 * Bus already configured by firmware, process it in the
1258 * first pass and just note the configuration.
1259 */
1260 if (pass)
1261 goto out;
1262
1263 /*
1264 * The bus might already exist for two reasons: Either we
1265 * are rescanning the bus or the bus is reachable through
1266 * more than one bridge. The second case can happen with
1267 * the i450NX chipset.
1268 */
1269 child = pci_find_bus(pci_domain_nr(bus), secondary);
1270 if (!child) {
1271 child = pci_add_new_bus(bus, dev, secondary);
1272 if (!child)
1273 goto out;
1274 child->primary = primary;
1275 pci_bus_insert_busn_res(child, secondary, subordinate);
1276 child->bridge_ctl = bctl;
1277 }
1278
1279 cmax = pci_scan_child_bus(child);
1280 if (cmax > subordinate)
1281 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1282 subordinate, cmax);
1283
1284 /* Subordinate should equal child->busn_res.end */
1285 if (subordinate > max)
1286 max = subordinate;
1287 } else {
1288
1289 /*
1290 * We need to assign a number to this bus which we always
1291 * do in the second pass.
1292 */
1293 if (!pass) {
1294 if (pcibios_assign_all_busses() || broken || is_cardbus)
1295
1296 /*
1297 * Temporarily disable forwarding of the
1298 * configuration cycles on all bridges in
1299 * this bus segment to avoid possible
1300 * conflicts in the second pass between two
1301 * bridges programmed with overlapping bus
1302 * ranges.
1303 */
1304 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1305 buses & ~0xffffff);
1306 goto out;
1307 }
1308
1309 /* Clear errors */
1310 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1311
1312 /* Read bus numbers from EA Capability (if present) */
1313 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1314 if (fixed_buses)
1315 next_busnr = fixed_sec;
1316 else
1317 next_busnr = max + 1;
1318
1319 /*
1320 * Prevent assigning a bus number that already exists.
1321 * This can happen when a bridge is hot-plugged, so in this
1322 * case we only re-scan this bus.
1323 */
1324 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1325 if (!child) {
1326 child = pci_add_new_bus(bus, dev, next_busnr);
1327 if (!child)
1328 goto out;
1329 pci_bus_insert_busn_res(child, next_busnr,
1330 bus->busn_res.end);
1331 }
1332 max++;
1333 if (available_buses)
1334 available_buses--;
1335
1336 buses = (buses & 0xff000000)
1337 | ((unsigned int)(child->primary) << 0)
1338 | ((unsigned int)(child->busn_res.start) << 8)
1339 | ((unsigned int)(child->busn_res.end) << 16);
1340
1341 /*
1342 * yenta.c forces a secondary latency timer of 176.
1343 * Copy that behaviour here.
1344 */
1345 if (is_cardbus) {
1346 buses &= ~0xff000000;
1347 buses |= CARDBUS_LATENCY_TIMER << 24;
1348 }
1349
1350 /* We need to blast all three values with a single write */
1351 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1352
1353 if (!is_cardbus) {
1354 child->bridge_ctl = bctl;
1355 max = pci_scan_child_bus_extend(child, available_buses);
1356 } else {
1357
1358 /*
1359 * For CardBus bridges, we leave 4 bus numbers as
1360 * cards with a PCI-to-PCI bridge can be inserted
1361 * later.
1362 */
1363 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1364 struct pci_bus *parent = bus;
1365 if (pci_find_bus(pci_domain_nr(bus),
1366 max+i+1))
1367 break;
1368 while (parent->parent) {
1369 if ((!pcibios_assign_all_busses()) &&
1370 (parent->busn_res.end > max) &&
1371 (parent->busn_res.end <= max+i)) {
1372 j = 1;
1373 }
1374 parent = parent->parent;
1375 }
1376 if (j) {
1377
1378 /*
1379 * Often, there are two CardBus
1380 * bridges -- try to leave one
1381 * valid bus number for each one.
1382 */
1383 i /= 2;
1384 break;
1385 }
1386 }
1387 max += i;
1388 }
1389
1390 /*
1391 * Set subordinate bus number to its real value.
1392 * If fixed subordinate bus number exists from EA
1393 * capability then use it.
1394 */
1395 if (fixed_buses)
1396 max = fixed_sub;
1397 pci_bus_update_busn_res_end(child, max);
1398 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1399 }
1400
1401 sprintf(child->name,
1402 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1403 pci_domain_nr(bus), child->number);
1404
1405 /* Check that all devices are accessible */
1406 while (bus->parent) {
1407 if ((child->busn_res.end > bus->busn_res.end) ||
1408 (child->number > bus->busn_res.end) ||
1409 (child->number < bus->number) ||
1410 (child->busn_res.end < bus->number)) {
1411 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1412 &child->busn_res);
1413 break;
1414 }
1415 bus = bus->parent;
1416 }
1417
1418out:
1419 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1420
1421 pm_runtime_put(&dev->dev);
1422
1423 return max;
1424}
1425
1426/*
1427 * pci_scan_bridge() - Scan buses behind a bridge
1428 * @bus: Parent bus the bridge is on
1429 * @dev: Bridge itself
1430 * @max: Starting subordinate number of buses behind this bridge
1431 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1432 * that need to be reconfigured.
1433 *
1434 * If it's a bridge, configure it and scan the bus behind it.
1435 * For CardBus bridges, we don't scan behind as the devices will
1436 * be handled by the bridge driver itself.
1437 *
1438 * We need to process bridges in two passes -- first we scan those
1439 * already configured by the BIOS and after we are done with all of
1440 * them, we proceed to assigning numbers to the remaining buses in
1441 * order to avoid overlaps between old and new bus numbers.
1442 *
1443 * Return: New subordinate number covering all buses behind this bridge.
1444 */
1445int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1446{
1447 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1448}
1449EXPORT_SYMBOL(pci_scan_bridge);
1450
1451/*
1452 * Read interrupt line and base address registers.
1453 * The architecture-dependent code can tweak these, of course.
1454 */
1455static void pci_read_irq(struct pci_dev *dev)
1456{
1457 unsigned char irq;
1458
1459 /* VFs are not allowed to use INTx, so skip the config reads */
1460 if (dev->is_virtfn) {
1461 dev->pin = 0;
1462 dev->irq = 0;
1463 return;
1464 }
1465
1466 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1467 dev->pin = irq;
1468 if (irq)
1469 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1470 dev->irq = irq;
1471}
1472
1473void set_pcie_port_type(struct pci_dev *pdev)
1474{
1475 int pos;
1476 u16 reg16;
1477 int type;
1478 struct pci_dev *parent;
1479
1480 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1481 if (!pos)
1482 return;
1483
1484 pdev->pcie_cap = pos;
1485 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1486 pdev->pcie_flags_reg = reg16;
1487 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1488 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1489
1490 parent = pci_upstream_bridge(pdev);
1491 if (!parent)
1492 return;
1493
1494 /*
1495 * Some systems do not identify their upstream/downstream ports
1496 * correctly so detect impossible configurations here and correct
1497 * the port type accordingly.
1498 */
1499 type = pci_pcie_type(pdev);
1500 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1501 /*
1502 * If pdev claims to be downstream port but the parent
1503 * device is also downstream port assume pdev is actually
1504 * upstream port.
1505 */
1506 if (pcie_downstream_port(parent)) {
1507 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1508 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1509 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1510 }
1511 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1512 /*
1513 * If pdev claims to be upstream port but the parent
1514 * device is also upstream port assume pdev is actually
1515 * downstream port.
1516 */
1517 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1518 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1519 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1520 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1521 }
1522 }
1523}
1524
1525void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1526{
1527 u32 reg32;
1528
1529 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1530 if (reg32 & PCI_EXP_SLTCAP_HPC)
1531 pdev->is_hotplug_bridge = 1;
1532}
1533
1534static void set_pcie_thunderbolt(struct pci_dev *dev)
1535{
1536 int vsec = 0;
1537 u32 header;
1538
1539 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1540 PCI_EXT_CAP_ID_VNDR))) {
1541 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1542
1543 /* Is the device part of a Thunderbolt controller? */
1544 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1545 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1546 dev->is_thunderbolt = 1;
1547 return;
1548 }
1549 }
1550}
1551
1552static void set_pcie_untrusted(struct pci_dev *dev)
1553{
1554 struct pci_dev *parent;
1555
1556 /*
1557 * If the upstream bridge is untrusted we treat this device
1558 * untrusted as well.
1559 */
1560 parent = pci_upstream_bridge(dev);
1561 if (parent && (parent->untrusted || parent->external_facing))
1562 dev->untrusted = true;
1563}
1564
1565/**
1566 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1567 * @dev: PCI device
1568 *
1569 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1570 * when forwarding a type1 configuration request the bridge must check that
1571 * the extended register address field is zero. The bridge is not permitted
1572 * to forward the transactions and must handle it as an Unsupported Request.
1573 * Some bridges do not follow this rule and simply drop the extended register
1574 * bits, resulting in the standard config space being aliased, every 256
1575 * bytes across the entire configuration space. Test for this condition by
1576 * comparing the first dword of each potential alias to the vendor/device ID.
1577 * Known offenders:
1578 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1579 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1580 */
1581static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1582{
1583#ifdef CONFIG_PCI_QUIRKS
1584 int pos;
1585 u32 header, tmp;
1586
1587 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1588
1589 for (pos = PCI_CFG_SPACE_SIZE;
1590 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1591 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1592 || header != tmp)
1593 return false;
1594 }
1595
1596 return true;
1597#else
1598 return false;
1599#endif
1600}
1601
1602/**
1603 * pci_cfg_space_size - Get the configuration space size of the PCI device
1604 * @dev: PCI device
1605 *
1606 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1607 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1608 * access it. Maybe we don't have a way to generate extended config space
1609 * accesses, or the device is behind a reverse Express bridge. So we try
1610 * reading the dword at 0x100 which must either be 0 or a valid extended
1611 * capability header.
1612 */
1613static int pci_cfg_space_size_ext(struct pci_dev *dev)
1614{
1615 u32 status;
1616 int pos = PCI_CFG_SPACE_SIZE;
1617
1618 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1619 return PCI_CFG_SPACE_SIZE;
1620 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1621 return PCI_CFG_SPACE_SIZE;
1622
1623 return PCI_CFG_SPACE_EXP_SIZE;
1624}
1625
1626int pci_cfg_space_size(struct pci_dev *dev)
1627{
1628 int pos;
1629 u32 status;
1630 u16 class;
1631
1632#ifdef CONFIG_PCI_IOV
1633 /*
1634 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1635 * implement a PCIe capability and therefore must implement extended
1636 * config space. We can skip the NO_EXTCFG test below and the
1637 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1638 * the fact that the SR-IOV capability on the PF resides in extended
1639 * config space and must be accessible and non-aliased to have enabled
1640 * support for this VF. This is a micro performance optimization for
1641 * systems supporting many VFs.
1642 */
1643 if (dev->is_virtfn)
1644 return PCI_CFG_SPACE_EXP_SIZE;
1645#endif
1646
1647 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1648 return PCI_CFG_SPACE_SIZE;
1649
1650 class = dev->class >> 8;
1651 if (class == PCI_CLASS_BRIDGE_HOST)
1652 return pci_cfg_space_size_ext(dev);
1653
1654 if (pci_is_pcie(dev))
1655 return pci_cfg_space_size_ext(dev);
1656
1657 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1658 if (!pos)
1659 return PCI_CFG_SPACE_SIZE;
1660
1661 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1662 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1663 return pci_cfg_space_size_ext(dev);
1664
1665 return PCI_CFG_SPACE_SIZE;
1666}
1667
1668static u32 pci_class(struct pci_dev *dev)
1669{
1670 u32 class;
1671
1672#ifdef CONFIG_PCI_IOV
1673 if (dev->is_virtfn)
1674 return dev->physfn->sriov->class;
1675#endif
1676 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1677 return class;
1678}
1679
1680static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1681{
1682#ifdef CONFIG_PCI_IOV
1683 if (dev->is_virtfn) {
1684 *vendor = dev->physfn->sriov->subsystem_vendor;
1685 *device = dev->physfn->sriov->subsystem_device;
1686 return;
1687 }
1688#endif
1689 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1690 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1691}
1692
1693static u8 pci_hdr_type(struct pci_dev *dev)
1694{
1695 u8 hdr_type;
1696
1697#ifdef CONFIG_PCI_IOV
1698 if (dev->is_virtfn)
1699 return dev->physfn->sriov->hdr_type;
1700#endif
1701 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1702 return hdr_type;
1703}
1704
1705#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1706
1707static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1708{
1709 /*
1710 * Disable the MSI hardware to avoid screaming interrupts
1711 * during boot. This is the power on reset default so
1712 * usually this should be a noop.
1713 */
1714 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1715 if (dev->msi_cap)
1716 pci_msi_set_enable(dev, 0);
1717
1718 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1719 if (dev->msix_cap)
1720 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1721}
1722
1723/**
1724 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1725 * @dev: PCI device
1726 *
1727 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1728 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1729 */
1730static int pci_intx_mask_broken(struct pci_dev *dev)
1731{
1732 u16 orig, toggle, new;
1733
1734 pci_read_config_word(dev, PCI_COMMAND, &orig);
1735 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1736 pci_write_config_word(dev, PCI_COMMAND, toggle);
1737 pci_read_config_word(dev, PCI_COMMAND, &new);
1738
1739 pci_write_config_word(dev, PCI_COMMAND, orig);
1740
1741 /*
1742 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1743 * r2.3, so strictly speaking, a device is not *broken* if it's not
1744 * writable. But we'll live with the misnomer for now.
1745 */
1746 if (new != toggle)
1747 return 1;
1748 return 0;
1749}
1750
1751static void early_dump_pci_device(struct pci_dev *pdev)
1752{
1753 u32 value[256 / 4];
1754 int i;
1755
1756 pci_info(pdev, "config space:\n");
1757
1758 for (i = 0; i < 256; i += 4)
1759 pci_read_config_dword(pdev, i, &value[i / 4]);
1760
1761 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1762 value, 256, false);
1763}
1764
1765/**
1766 * pci_setup_device - Fill in class and map information of a device
1767 * @dev: the device structure to fill
1768 *
1769 * Initialize the device structure with information about the device's
1770 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1771 * Called at initialisation of the PCI subsystem and by CardBus services.
1772 * Returns 0 on success and negative if unknown type of device (not normal,
1773 * bridge or CardBus).
1774 */
1775int pci_setup_device(struct pci_dev *dev)
1776{
1777 u32 class;
1778 u16 cmd;
1779 u8 hdr_type;
1780 int pos = 0;
1781 struct pci_bus_region region;
1782 struct resource *res;
1783
1784 hdr_type = pci_hdr_type(dev);
1785
1786 dev->sysdata = dev->bus->sysdata;
1787 dev->dev.parent = dev->bus->bridge;
1788 dev->dev.bus = &pci_bus_type;
1789 dev->hdr_type = hdr_type & 0x7f;
1790 dev->multifunction = !!(hdr_type & 0x80);
1791 dev->error_state = pci_channel_io_normal;
1792 set_pcie_port_type(dev);
1793
1794 pci_dev_assign_slot(dev);
1795
1796 /*
1797 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1798 * set this higher, assuming the system even supports it.
1799 */
1800 dev->dma_mask = 0xffffffff;
1801
1802 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1803 dev->bus->number, PCI_SLOT(dev->devfn),
1804 PCI_FUNC(dev->devfn));
1805
1806 class = pci_class(dev);
1807
1808 dev->revision = class & 0xff;
1809 dev->class = class >> 8; /* upper 3 bytes */
1810
1811 if (pci_early_dump)
1812 early_dump_pci_device(dev);
1813
1814 /* Need to have dev->class ready */
1815 dev->cfg_size = pci_cfg_space_size(dev);
1816
1817 /* Need to have dev->cfg_size ready */
1818 set_pcie_thunderbolt(dev);
1819
1820 set_pcie_untrusted(dev);
1821
1822 /* "Unknown power state" */
1823 dev->current_state = PCI_UNKNOWN;
1824
1825 /* Early fixups, before probing the BARs */
1826 pci_fixup_device(pci_fixup_early, dev);
1827
1828 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1829 dev->vendor, dev->device, dev->hdr_type, dev->class);
1830
1831 /* Device class may be changed after fixup */
1832 class = dev->class >> 8;
1833
1834 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1835 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1836 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1837 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1838 cmd &= ~PCI_COMMAND_IO;
1839 cmd &= ~PCI_COMMAND_MEMORY;
1840 pci_write_config_word(dev, PCI_COMMAND, cmd);
1841 }
1842 }
1843
1844 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1845
1846 switch (dev->hdr_type) { /* header type */
1847 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1848 if (class == PCI_CLASS_BRIDGE_PCI)
1849 goto bad;
1850 pci_read_irq(dev);
1851 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1852
1853 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1854
1855 /*
1856 * Do the ugly legacy mode stuff here rather than broken chip
1857 * quirk code. Legacy mode ATA controllers have fixed
1858 * addresses. These are not always echoed in BAR0-3, and
1859 * BAR0-3 in a few cases contain junk!
1860 */
1861 if (class == PCI_CLASS_STORAGE_IDE) {
1862 u8 progif;
1863 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1864 if ((progif & 1) == 0) {
1865 region.start = 0x1F0;
1866 region.end = 0x1F7;
1867 res = &dev->resource[0];
1868 res->flags = LEGACY_IO_RESOURCE;
1869 pcibios_bus_to_resource(dev->bus, res, ®ion);
1870 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1871 res);
1872 region.start = 0x3F6;
1873 region.end = 0x3F6;
1874 res = &dev->resource[1];
1875 res->flags = LEGACY_IO_RESOURCE;
1876 pcibios_bus_to_resource(dev->bus, res, ®ion);
1877 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1878 res);
1879 }
1880 if ((progif & 4) == 0) {
1881 region.start = 0x170;
1882 region.end = 0x177;
1883 res = &dev->resource[2];
1884 res->flags = LEGACY_IO_RESOURCE;
1885 pcibios_bus_to_resource(dev->bus, res, ®ion);
1886 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1887 res);
1888 region.start = 0x376;
1889 region.end = 0x376;
1890 res = &dev->resource[3];
1891 res->flags = LEGACY_IO_RESOURCE;
1892 pcibios_bus_to_resource(dev->bus, res, ®ion);
1893 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1894 res);
1895 }
1896 }
1897 break;
1898
1899 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1900 /*
1901 * The PCI-to-PCI bridge spec requires that subtractive
1902 * decoding (i.e. transparent) bridge must have programming
1903 * interface code of 0x01.
1904 */
1905 pci_read_irq(dev);
1906 dev->transparent = ((dev->class & 0xff) == 1);
1907 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1908 pci_read_bridge_windows(dev);
1909 set_pcie_hotplug_bridge(dev);
1910 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1911 if (pos) {
1912 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1913 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1914 }
1915 break;
1916
1917 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1918 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1919 goto bad;
1920 pci_read_irq(dev);
1921 pci_read_bases(dev, 1, 0);
1922 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1923 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1924 break;
1925
1926 default: /* unknown header */
1927 pci_err(dev, "unknown header type %02x, ignoring device\n",
1928 dev->hdr_type);
1929 return -EIO;
1930
1931 bad:
1932 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1933 dev->class, dev->hdr_type);
1934 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1935 }
1936
1937 /* We found a fine healthy device, go go go... */
1938 return 0;
1939}
1940
1941static void pci_configure_mps(struct pci_dev *dev)
1942{
1943 struct pci_dev *bridge = pci_upstream_bridge(dev);
1944 int mps, mpss, p_mps, rc;
1945
1946 if (!pci_is_pcie(dev))
1947 return;
1948
1949 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1950 if (dev->is_virtfn)
1951 return;
1952
1953 /*
1954 * For Root Complex Integrated Endpoints, program the maximum
1955 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1956 */
1957 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1958 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1959 mps = 128;
1960 else
1961 mps = 128 << dev->pcie_mpss;
1962 rc = pcie_set_mps(dev, mps);
1963 if (rc) {
1964 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1965 mps);
1966 }
1967 return;
1968 }
1969
1970 if (!bridge || !pci_is_pcie(bridge))
1971 return;
1972
1973 mps = pcie_get_mps(dev);
1974 p_mps = pcie_get_mps(bridge);
1975
1976 if (mps == p_mps)
1977 return;
1978
1979 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1980 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1981 mps, pci_name(bridge), p_mps);
1982 return;
1983 }
1984
1985 /*
1986 * Fancier MPS configuration is done later by
1987 * pcie_bus_configure_settings()
1988 */
1989 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1990 return;
1991
1992 mpss = 128 << dev->pcie_mpss;
1993 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1994 pcie_set_mps(bridge, mpss);
1995 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1996 mpss, p_mps, 128 << bridge->pcie_mpss);
1997 p_mps = pcie_get_mps(bridge);
1998 }
1999
2000 rc = pcie_set_mps(dev, p_mps);
2001 if (rc) {
2002 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2003 p_mps);
2004 return;
2005 }
2006
2007 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2008 p_mps, mps, mpss);
2009}
2010
2011int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2012{
2013 struct pci_host_bridge *host;
2014 u32 cap;
2015 u16 ctl;
2016 int ret;
2017
2018 if (!pci_is_pcie(dev))
2019 return 0;
2020
2021 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2022 if (ret)
2023 return 0;
2024
2025 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2026 return 0;
2027
2028 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2029 if (ret)
2030 return 0;
2031
2032 host = pci_find_host_bridge(dev->bus);
2033 if (!host)
2034 return 0;
2035
2036 /*
2037 * If some device in the hierarchy doesn't handle Extended Tags
2038 * correctly, make sure they're disabled.
2039 */
2040 if (host->no_ext_tags) {
2041 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2042 pci_info(dev, "disabling Extended Tags\n");
2043 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2044 PCI_EXP_DEVCTL_EXT_TAG);
2045 }
2046 return 0;
2047 }
2048
2049 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2050 pci_info(dev, "enabling Extended Tags\n");
2051 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2052 PCI_EXP_DEVCTL_EXT_TAG);
2053 }
2054 return 0;
2055}
2056
2057/**
2058 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2059 * @dev: PCI device to query
2060 *
2061 * Returns true if the device has enabled relaxed ordering attribute.
2062 */
2063bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2064{
2065 u16 v;
2066
2067 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2068
2069 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2070}
2071EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2072
2073static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2074{
2075 struct pci_dev *root;
2076
2077 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2078 if (dev->is_virtfn)
2079 return;
2080
2081 if (!pcie_relaxed_ordering_enabled(dev))
2082 return;
2083
2084 /*
2085 * For now, we only deal with Relaxed Ordering issues with Root
2086 * Ports. Peer-to-Peer DMA is another can of worms.
2087 */
2088 root = pcie_find_root_port(dev);
2089 if (!root)
2090 return;
2091
2092 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2093 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2094 PCI_EXP_DEVCTL_RELAX_EN);
2095 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2096 }
2097}
2098
2099static void pci_configure_ltr(struct pci_dev *dev)
2100{
2101#ifdef CONFIG_PCIEASPM
2102 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2103 struct pci_dev *bridge;
2104 u32 cap, ctl;
2105
2106 if (!pci_is_pcie(dev))
2107 return;
2108
2109 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2110 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2111 return;
2112
2113 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2114 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2115 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2116 dev->ltr_path = 1;
2117 return;
2118 }
2119
2120 bridge = pci_upstream_bridge(dev);
2121 if (bridge && bridge->ltr_path)
2122 dev->ltr_path = 1;
2123
2124 return;
2125 }
2126
2127 if (!host->native_ltr)
2128 return;
2129
2130 /*
2131 * Software must not enable LTR in an Endpoint unless the Root
2132 * Complex and all intermediate Switches indicate support for LTR.
2133 * PCIe r4.0, sec 6.18.
2134 */
2135 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2136 ((bridge = pci_upstream_bridge(dev)) &&
2137 bridge->ltr_path)) {
2138 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2139 PCI_EXP_DEVCTL2_LTR_EN);
2140 dev->ltr_path = 1;
2141 }
2142#endif
2143}
2144
2145static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2146{
2147#ifdef CONFIG_PCI_PASID
2148 struct pci_dev *bridge;
2149 int pcie_type;
2150 u32 cap;
2151
2152 if (!pci_is_pcie(dev))
2153 return;
2154
2155 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2156 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2157 return;
2158
2159 pcie_type = pci_pcie_type(dev);
2160 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2161 pcie_type == PCI_EXP_TYPE_RC_END)
2162 dev->eetlp_prefix_path = 1;
2163 else {
2164 bridge = pci_upstream_bridge(dev);
2165 if (bridge && bridge->eetlp_prefix_path)
2166 dev->eetlp_prefix_path = 1;
2167 }
2168#endif
2169}
2170
2171static void pci_configure_serr(struct pci_dev *dev)
2172{
2173 u16 control;
2174
2175 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2176
2177 /*
2178 * A bridge will not forward ERR_ messages coming from an
2179 * endpoint unless SERR# forwarding is enabled.
2180 */
2181 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2182 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2183 control |= PCI_BRIDGE_CTL_SERR;
2184 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2185 }
2186 }
2187}
2188
2189static void pci_configure_device(struct pci_dev *dev)
2190{
2191 pci_configure_mps(dev);
2192 pci_configure_extended_tags(dev, NULL);
2193 pci_configure_relaxed_ordering(dev);
2194 pci_configure_ltr(dev);
2195 pci_configure_eetlp_prefix(dev);
2196 pci_configure_serr(dev);
2197
2198 pci_acpi_program_hp_params(dev);
2199}
2200
2201static void pci_release_capabilities(struct pci_dev *dev)
2202{
2203 pci_aer_exit(dev);
2204 pci_vpd_release(dev);
2205 pci_iov_release(dev);
2206 pci_free_cap_save_buffers(dev);
2207}
2208
2209/**
2210 * pci_release_dev - Free a PCI device structure when all users of it are
2211 * finished
2212 * @dev: device that's been disconnected
2213 *
2214 * Will be called only by the device core when all users of this PCI device are
2215 * done.
2216 */
2217static void pci_release_dev(struct device *dev)
2218{
2219 struct pci_dev *pci_dev;
2220
2221 pci_dev = to_pci_dev(dev);
2222 pci_release_capabilities(pci_dev);
2223 pci_release_of_node(pci_dev);
2224 pcibios_release_device(pci_dev);
2225 pci_bus_put(pci_dev->bus);
2226 kfree(pci_dev->driver_override);
2227 bitmap_free(pci_dev->dma_alias_mask);
2228 kfree(pci_dev);
2229}
2230
2231struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2232{
2233 struct pci_dev *dev;
2234
2235 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2236 if (!dev)
2237 return NULL;
2238
2239 INIT_LIST_HEAD(&dev->bus_list);
2240 dev->dev.type = &pci_dev_type;
2241 dev->bus = pci_bus_get(bus);
2242
2243 return dev;
2244}
2245EXPORT_SYMBOL(pci_alloc_dev);
2246
2247static bool pci_bus_crs_vendor_id(u32 l)
2248{
2249 return (l & 0xffff) == 0x0001;
2250}
2251
2252static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2253 int timeout)
2254{
2255 int delay = 1;
2256
2257 if (!pci_bus_crs_vendor_id(*l))
2258 return true; /* not a CRS completion */
2259
2260 if (!timeout)
2261 return false; /* CRS, but caller doesn't want to wait */
2262
2263 /*
2264 * We got the reserved Vendor ID that indicates a completion with
2265 * Configuration Request Retry Status (CRS). Retry until we get a
2266 * valid Vendor ID or we time out.
2267 */
2268 while (pci_bus_crs_vendor_id(*l)) {
2269 if (delay > timeout) {
2270 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2271 pci_domain_nr(bus), bus->number,
2272 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2273
2274 return false;
2275 }
2276 if (delay >= 1000)
2277 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2278 pci_domain_nr(bus), bus->number,
2279 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2280
2281 msleep(delay);
2282 delay *= 2;
2283
2284 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2285 return false;
2286 }
2287
2288 if (delay >= 1000)
2289 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2290 pci_domain_nr(bus), bus->number,
2291 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2292
2293 return true;
2294}
2295
2296bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2297 int timeout)
2298{
2299 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2300 return false;
2301
2302 /* Some broken boards return 0 or ~0 if a slot is empty: */
2303 if (*l == 0xffffffff || *l == 0x00000000 ||
2304 *l == 0x0000ffff || *l == 0xffff0000)
2305 return false;
2306
2307 if (pci_bus_crs_vendor_id(*l))
2308 return pci_bus_wait_crs(bus, devfn, l, timeout);
2309
2310 return true;
2311}
2312
2313bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2314 int timeout)
2315{
2316#ifdef CONFIG_PCI_QUIRKS
2317 struct pci_dev *bridge = bus->self;
2318
2319 /*
2320 * Certain IDT switches have an issue where they improperly trigger
2321 * ACS Source Validation errors on completions for config reads.
2322 */
2323 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2324 bridge->device == 0x80b5)
2325 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2326#endif
2327
2328 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2329}
2330EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2331
2332/*
2333 * Read the config data for a PCI device, sanity-check it,
2334 * and fill in the dev structure.
2335 */
2336static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2337{
2338 struct pci_dev *dev;
2339 u32 l;
2340
2341 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2342 return NULL;
2343
2344 dev = pci_alloc_dev(bus);
2345 if (!dev)
2346 return NULL;
2347
2348 dev->devfn = devfn;
2349 dev->vendor = l & 0xffff;
2350 dev->device = (l >> 16) & 0xffff;
2351
2352 pci_set_of_node(dev);
2353
2354 if (pci_setup_device(dev)) {
2355 pci_bus_put(dev->bus);
2356 kfree(dev);
2357 return NULL;
2358 }
2359
2360 return dev;
2361}
2362
2363void pcie_report_downtraining(struct pci_dev *dev)
2364{
2365 if (!pci_is_pcie(dev))
2366 return;
2367
2368 /* Look from the device up to avoid downstream ports with no devices */
2369 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2370 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2371 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2372 return;
2373
2374 /* Multi-function PCIe devices share the same link/status */
2375 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2376 return;
2377
2378 /* Print link status only if the device is constrained by the fabric */
2379 __pcie_print_link_status(dev, false);
2380}
2381
2382static void pci_init_capabilities(struct pci_dev *dev)
2383{
2384 pci_ea_init(dev); /* Enhanced Allocation */
2385
2386 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2387 pci_msi_setup_pci_dev(dev);
2388
2389 /* Buffers for saving PCIe and PCI-X capabilities */
2390 pci_allocate_cap_save_buffers(dev);
2391
2392 pci_pm_init(dev); /* Power Management */
2393 pci_vpd_init(dev); /* Vital Product Data */
2394 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2395 pci_iov_init(dev); /* Single Root I/O Virtualization */
2396 pci_ats_init(dev); /* Address Translation Services */
2397 pci_pri_init(dev); /* Page Request Interface */
2398 pci_pasid_init(dev); /* Process Address Space ID */
2399 pci_acs_init(dev); /* Access Control Services */
2400 pci_ptm_init(dev); /* Precision Time Measurement */
2401 pci_aer_init(dev); /* Advanced Error Reporting */
2402 pci_dpc_init(dev); /* Downstream Port Containment */
2403
2404 pcie_report_downtraining(dev);
2405
2406 if (pci_probe_reset_function(dev) == 0)
2407 dev->reset_fn = 1;
2408}
2409
2410/*
2411 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2412 * devices. Firmware interfaces that can select the MSI domain on a
2413 * per-device basis should be called from here.
2414 */
2415static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2416{
2417 struct irq_domain *d;
2418
2419 /*
2420 * If a domain has been set through the pcibios_add_device()
2421 * callback, then this is the one (platform code knows best).
2422 */
2423 d = dev_get_msi_domain(&dev->dev);
2424 if (d)
2425 return d;
2426
2427 /*
2428 * Let's see if we have a firmware interface able to provide
2429 * the domain.
2430 */
2431 d = pci_msi_get_device_domain(dev);
2432 if (d)
2433 return d;
2434
2435 return NULL;
2436}
2437
2438static void pci_set_msi_domain(struct pci_dev *dev)
2439{
2440 struct irq_domain *d;
2441
2442 /*
2443 * If the platform or firmware interfaces cannot supply a
2444 * device-specific MSI domain, then inherit the default domain
2445 * from the host bridge itself.
2446 */
2447 d = pci_dev_msi_domain(dev);
2448 if (!d)
2449 d = dev_get_msi_domain(&dev->bus->dev);
2450
2451 dev_set_msi_domain(&dev->dev, d);
2452}
2453
2454void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2455{
2456 int ret;
2457
2458 pci_configure_device(dev);
2459
2460 device_initialize(&dev->dev);
2461 dev->dev.release = pci_release_dev;
2462
2463 set_dev_node(&dev->dev, pcibus_to_node(bus));
2464 dev->dev.dma_mask = &dev->dma_mask;
2465 dev->dev.dma_parms = &dev->dma_parms;
2466 dev->dev.coherent_dma_mask = 0xffffffffull;
2467
2468 dma_set_max_seg_size(&dev->dev, 65536);
2469 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2470
2471 /* Fix up broken headers */
2472 pci_fixup_device(pci_fixup_header, dev);
2473
2474 pci_reassigndev_resource_alignment(dev);
2475
2476 dev->state_saved = false;
2477
2478 pci_init_capabilities(dev);
2479
2480 /*
2481 * Add the device to our list of discovered devices
2482 * and the bus list for fixup functions, etc.
2483 */
2484 down_write(&pci_bus_sem);
2485 list_add_tail(&dev->bus_list, &bus->devices);
2486 up_write(&pci_bus_sem);
2487
2488 ret = pcibios_add_device(dev);
2489 WARN_ON(ret < 0);
2490
2491 /* Set up MSI IRQ domain */
2492 pci_set_msi_domain(dev);
2493
2494 /* Notifier could use PCI capabilities */
2495 dev->match_driver = false;
2496 ret = device_add(&dev->dev);
2497 WARN_ON(ret < 0);
2498}
2499
2500struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2501{
2502 struct pci_dev *dev;
2503
2504 dev = pci_get_slot(bus, devfn);
2505 if (dev) {
2506 pci_dev_put(dev);
2507 return dev;
2508 }
2509
2510 dev = pci_scan_device(bus, devfn);
2511 if (!dev)
2512 return NULL;
2513
2514 pci_device_add(dev, bus);
2515
2516 return dev;
2517}
2518EXPORT_SYMBOL(pci_scan_single_device);
2519
2520static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2521{
2522 int pos;
2523 u16 cap = 0;
2524 unsigned next_fn;
2525
2526 if (pci_ari_enabled(bus)) {
2527 if (!dev)
2528 return 0;
2529 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2530 if (!pos)
2531 return 0;
2532
2533 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2534 next_fn = PCI_ARI_CAP_NFN(cap);
2535 if (next_fn <= fn)
2536 return 0; /* protect against malformed list */
2537
2538 return next_fn;
2539 }
2540
2541 /* dev may be NULL for non-contiguous multifunction devices */
2542 if (!dev || dev->multifunction)
2543 return (fn + 1) % 8;
2544
2545 return 0;
2546}
2547
2548static int only_one_child(struct pci_bus *bus)
2549{
2550 struct pci_dev *bridge = bus->self;
2551
2552 /*
2553 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2554 * we scan for all possible devices, not just Device 0.
2555 */
2556 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2557 return 0;
2558
2559 /*
2560 * A PCIe Downstream Port normally leads to a Link with only Device
2561 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2562 * only for Device 0 in that situation.
2563 */
2564 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2565 return 1;
2566
2567 return 0;
2568}
2569
2570/**
2571 * pci_scan_slot - Scan a PCI slot on a bus for devices
2572 * @bus: PCI bus to scan
2573 * @devfn: slot number to scan (must have zero function)
2574 *
2575 * Scan a PCI slot on the specified PCI bus for devices, adding
2576 * discovered devices to the @bus->devices list. New devices
2577 * will not have is_added set.
2578 *
2579 * Returns the number of new devices found.
2580 */
2581int pci_scan_slot(struct pci_bus *bus, int devfn)
2582{
2583 unsigned fn, nr = 0;
2584 struct pci_dev *dev;
2585
2586 if (only_one_child(bus) && (devfn > 0))
2587 return 0; /* Already scanned the entire slot */
2588
2589 dev = pci_scan_single_device(bus, devfn);
2590 if (!dev)
2591 return 0;
2592 if (!pci_dev_is_added(dev))
2593 nr++;
2594
2595 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2596 dev = pci_scan_single_device(bus, devfn + fn);
2597 if (dev) {
2598 if (!pci_dev_is_added(dev))
2599 nr++;
2600 dev->multifunction = 1;
2601 }
2602 }
2603
2604 /* Only one slot has PCIe device */
2605 if (bus->self && nr)
2606 pcie_aspm_init_link_state(bus->self);
2607
2608 return nr;
2609}
2610EXPORT_SYMBOL(pci_scan_slot);
2611
2612static int pcie_find_smpss(struct pci_dev *dev, void *data)
2613{
2614 u8 *smpss = data;
2615
2616 if (!pci_is_pcie(dev))
2617 return 0;
2618
2619 /*
2620 * We don't have a way to change MPS settings on devices that have
2621 * drivers attached. A hot-added device might support only the minimum
2622 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2623 * where devices may be hot-added, we limit the fabric MPS to 128 so
2624 * hot-added devices will work correctly.
2625 *
2626 * However, if we hot-add a device to a slot directly below a Root
2627 * Port, it's impossible for there to be other existing devices below
2628 * the port. We don't limit the MPS in this case because we can
2629 * reconfigure MPS on both the Root Port and the hot-added device,
2630 * and there are no other devices involved.
2631 *
2632 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2633 */
2634 if (dev->is_hotplug_bridge &&
2635 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2636 *smpss = 0;
2637
2638 if (*smpss > dev->pcie_mpss)
2639 *smpss = dev->pcie_mpss;
2640
2641 return 0;
2642}
2643
2644static void pcie_write_mps(struct pci_dev *dev, int mps)
2645{
2646 int rc;
2647
2648 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2649 mps = 128 << dev->pcie_mpss;
2650
2651 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2652 dev->bus->self)
2653
2654 /*
2655 * For "Performance", the assumption is made that
2656 * downstream communication will never be larger than
2657 * the MRRS. So, the MPS only needs to be configured
2658 * for the upstream communication. This being the case,
2659 * walk from the top down and set the MPS of the child
2660 * to that of the parent bus.
2661 *
2662 * Configure the device MPS with the smaller of the
2663 * device MPSS or the bridge MPS (which is assumed to be
2664 * properly configured at this point to the largest
2665 * allowable MPS based on its parent bus).
2666 */
2667 mps = min(mps, pcie_get_mps(dev->bus->self));
2668 }
2669
2670 rc = pcie_set_mps(dev, mps);
2671 if (rc)
2672 pci_err(dev, "Failed attempting to set the MPS\n");
2673}
2674
2675static void pcie_write_mrrs(struct pci_dev *dev)
2676{
2677 int rc, mrrs;
2678
2679 /*
2680 * In the "safe" case, do not configure the MRRS. There appear to be
2681 * issues with setting MRRS to 0 on a number of devices.
2682 */
2683 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2684 return;
2685
2686 /*
2687 * For max performance, the MRRS must be set to the largest supported
2688 * value. However, it cannot be configured larger than the MPS the
2689 * device or the bus can support. This should already be properly
2690 * configured by a prior call to pcie_write_mps().
2691 */
2692 mrrs = pcie_get_mps(dev);
2693
2694 /*
2695 * MRRS is a R/W register. Invalid values can be written, but a
2696 * subsequent read will verify if the value is acceptable or not.
2697 * If the MRRS value provided is not acceptable (e.g., too large),
2698 * shrink the value until it is acceptable to the HW.
2699 */
2700 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2701 rc = pcie_set_readrq(dev, mrrs);
2702 if (!rc)
2703 break;
2704
2705 pci_warn(dev, "Failed attempting to set the MRRS\n");
2706 mrrs /= 2;
2707 }
2708
2709 if (mrrs < 128)
2710 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2711}
2712
2713static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2714{
2715 int mps, orig_mps;
2716
2717 if (!pci_is_pcie(dev))
2718 return 0;
2719
2720 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2721 pcie_bus_config == PCIE_BUS_DEFAULT)
2722 return 0;
2723
2724 mps = 128 << *(u8 *)data;
2725 orig_mps = pcie_get_mps(dev);
2726
2727 pcie_write_mps(dev, mps);
2728 pcie_write_mrrs(dev);
2729
2730 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2731 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2732 orig_mps, pcie_get_readrq(dev));
2733
2734 return 0;
2735}
2736
2737/*
2738 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2739 * parents then children fashion. If this changes, then this code will not
2740 * work as designed.
2741 */
2742void pcie_bus_configure_settings(struct pci_bus *bus)
2743{
2744 u8 smpss = 0;
2745
2746 if (!bus->self)
2747 return;
2748
2749 if (!pci_is_pcie(bus->self))
2750 return;
2751
2752 /*
2753 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2754 * to be aware of the MPS of the destination. To work around this,
2755 * simply force the MPS of the entire system to the smallest possible.
2756 */
2757 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2758 smpss = 0;
2759
2760 if (pcie_bus_config == PCIE_BUS_SAFE) {
2761 smpss = bus->self->pcie_mpss;
2762
2763 pcie_find_smpss(bus->self, &smpss);
2764 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2765 }
2766
2767 pcie_bus_configure_set(bus->self, &smpss);
2768 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2769}
2770EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2771
2772/*
2773 * Called after each bus is probed, but before its children are examined. This
2774 * is marked as __weak because multiple architectures define it.
2775 */
2776void __weak pcibios_fixup_bus(struct pci_bus *bus)
2777{
2778 /* nothing to do, expected to be removed in the future */
2779}
2780
2781/**
2782 * pci_scan_child_bus_extend() - Scan devices below a bus
2783 * @bus: Bus to scan for devices
2784 * @available_buses: Total number of buses available (%0 does not try to
2785 * extend beyond the minimal)
2786 *
2787 * Scans devices below @bus including subordinate buses. Returns new
2788 * subordinate number including all the found devices. Passing
2789 * @available_buses causes the remaining bus space to be distributed
2790 * equally between hotplug-capable bridges to allow future extension of the
2791 * hierarchy.
2792 */
2793static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2794 unsigned int available_buses)
2795{
2796 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2797 unsigned int start = bus->busn_res.start;
2798 unsigned int devfn, fn, cmax, max = start;
2799 struct pci_dev *dev;
2800 int nr_devs;
2801
2802 dev_dbg(&bus->dev, "scanning bus\n");
2803
2804 /* Go find them, Rover! */
2805 for (devfn = 0; devfn < 256; devfn += 8) {
2806 nr_devs = pci_scan_slot(bus, devfn);
2807
2808 /*
2809 * The Jailhouse hypervisor may pass individual functions of a
2810 * multi-function device to a guest without passing function 0.
2811 * Look for them as well.
2812 */
2813 if (jailhouse_paravirt() && nr_devs == 0) {
2814 for (fn = 1; fn < 8; fn++) {
2815 dev = pci_scan_single_device(bus, devfn + fn);
2816 if (dev)
2817 dev->multifunction = 1;
2818 }
2819 }
2820 }
2821
2822 /* Reserve buses for SR-IOV capability */
2823 used_buses = pci_iov_bus_range(bus);
2824 max += used_buses;
2825
2826 /*
2827 * After performing arch-dependent fixup of the bus, look behind
2828 * all PCI-to-PCI bridges on this bus.
2829 */
2830 if (!bus->is_added) {
2831 dev_dbg(&bus->dev, "fixups for bus\n");
2832 pcibios_fixup_bus(bus);
2833 bus->is_added = 1;
2834 }
2835
2836 /*
2837 * Calculate how many hotplug bridges and normal bridges there
2838 * are on this bus. We will distribute the additional available
2839 * buses between hotplug bridges.
2840 */
2841 for_each_pci_bridge(dev, bus) {
2842 if (dev->is_hotplug_bridge)
2843 hotplug_bridges++;
2844 else
2845 normal_bridges++;
2846 }
2847
2848 /*
2849 * Scan bridges that are already configured. We don't touch them
2850 * unless they are misconfigured (which will be done in the second
2851 * scan below).
2852 */
2853 for_each_pci_bridge(dev, bus) {
2854 cmax = max;
2855 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2856
2857 /*
2858 * Reserve one bus for each bridge now to avoid extending
2859 * hotplug bridges too much during the second scan below.
2860 */
2861 used_buses++;
2862 if (cmax - max > 1)
2863 used_buses += cmax - max - 1;
2864 }
2865
2866 /* Scan bridges that need to be reconfigured */
2867 for_each_pci_bridge(dev, bus) {
2868 unsigned int buses = 0;
2869
2870 if (!hotplug_bridges && normal_bridges == 1) {
2871
2872 /*
2873 * There is only one bridge on the bus (upstream
2874 * port) so it gets all available buses which it
2875 * can then distribute to the possible hotplug
2876 * bridges below.
2877 */
2878 buses = available_buses;
2879 } else if (dev->is_hotplug_bridge) {
2880
2881 /*
2882 * Distribute the extra buses between hotplug
2883 * bridges if any.
2884 */
2885 buses = available_buses / hotplug_bridges;
2886 buses = min(buses, available_buses - used_buses + 1);
2887 }
2888
2889 cmax = max;
2890 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2891 /* One bus is already accounted so don't add it again */
2892 if (max - cmax > 1)
2893 used_buses += max - cmax - 1;
2894 }
2895
2896 /*
2897 * Make sure a hotplug bridge has at least the minimum requested
2898 * number of buses but allow it to grow up to the maximum available
2899 * bus number of there is room.
2900 */
2901 if (bus->self && bus->self->is_hotplug_bridge) {
2902 used_buses = max_t(unsigned int, available_buses,
2903 pci_hotplug_bus_size - 1);
2904 if (max - start < used_buses) {
2905 max = start + used_buses;
2906
2907 /* Do not allocate more buses than we have room left */
2908 if (max > bus->busn_res.end)
2909 max = bus->busn_res.end;
2910
2911 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2912 &bus->busn_res, max - start);
2913 }
2914 }
2915
2916 /*
2917 * We've scanned the bus and so we know all about what's on
2918 * the other side of any bridges that may be on this bus plus
2919 * any devices.
2920 *
2921 * Return how far we've got finding sub-buses.
2922 */
2923 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2924 return max;
2925}
2926
2927/**
2928 * pci_scan_child_bus() - Scan devices below a bus
2929 * @bus: Bus to scan for devices
2930 *
2931 * Scans devices below @bus including subordinate buses. Returns new
2932 * subordinate number including all the found devices.
2933 */
2934unsigned int pci_scan_child_bus(struct pci_bus *bus)
2935{
2936 return pci_scan_child_bus_extend(bus, 0);
2937}
2938EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2939
2940/**
2941 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2942 * @bridge: Host bridge to set up
2943 *
2944 * Default empty implementation. Replace with an architecture-specific setup
2945 * routine, if necessary.
2946 */
2947int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2948{
2949 return 0;
2950}
2951
2952void __weak pcibios_add_bus(struct pci_bus *bus)
2953{
2954}
2955
2956void __weak pcibios_remove_bus(struct pci_bus *bus)
2957{
2958}
2959
2960struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2961 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2962{
2963 int error;
2964 struct pci_host_bridge *bridge;
2965
2966 bridge = pci_alloc_host_bridge(0);
2967 if (!bridge)
2968 return NULL;
2969
2970 bridge->dev.parent = parent;
2971
2972 list_splice_init(resources, &bridge->windows);
2973 bridge->sysdata = sysdata;
2974 bridge->busnr = bus;
2975 bridge->ops = ops;
2976
2977 error = pci_register_host_bridge(bridge);
2978 if (error < 0)
2979 goto err_out;
2980
2981 return bridge->bus;
2982
2983err_out:
2984 put_device(&bridge->dev);
2985 return NULL;
2986}
2987EXPORT_SYMBOL_GPL(pci_create_root_bus);
2988
2989int pci_host_probe(struct pci_host_bridge *bridge)
2990{
2991 struct pci_bus *bus, *child;
2992 int ret;
2993
2994 ret = pci_scan_root_bus_bridge(bridge);
2995 if (ret < 0) {
2996 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2997 return ret;
2998 }
2999
3000 bus = bridge->bus;
3001
3002 /*
3003 * We insert PCI resources into the iomem_resource and
3004 * ioport_resource trees in either pci_bus_claim_resources()
3005 * or pci_bus_assign_resources().
3006 */
3007 if (pci_has_flag(PCI_PROBE_ONLY)) {
3008 pci_bus_claim_resources(bus);
3009 } else {
3010 pci_bus_size_bridges(bus);
3011 pci_bus_assign_resources(bus);
3012
3013 list_for_each_entry(child, &bus->children, node)
3014 pcie_bus_configure_settings(child);
3015 }
3016
3017 pci_bus_add_devices(bus);
3018 return 0;
3019}
3020EXPORT_SYMBOL_GPL(pci_host_probe);
3021
3022int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3023{
3024 struct resource *res = &b->busn_res;
3025 struct resource *parent_res, *conflict;
3026
3027 res->start = bus;
3028 res->end = bus_max;
3029 res->flags = IORESOURCE_BUS;
3030
3031 if (!pci_is_root_bus(b))
3032 parent_res = &b->parent->busn_res;
3033 else {
3034 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3035 res->flags |= IORESOURCE_PCI_FIXED;
3036 }
3037
3038 conflict = request_resource_conflict(parent_res, res);
3039
3040 if (conflict)
3041 dev_info(&b->dev,
3042 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3043 res, pci_is_root_bus(b) ? "domain " : "",
3044 parent_res, conflict->name, conflict);
3045
3046 return conflict == NULL;
3047}
3048
3049int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3050{
3051 struct resource *res = &b->busn_res;
3052 struct resource old_res = *res;
3053 resource_size_t size;
3054 int ret;
3055
3056 if (res->start > bus_max)
3057 return -EINVAL;
3058
3059 size = bus_max - res->start + 1;
3060 ret = adjust_resource(res, res->start, size);
3061 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3062 &old_res, ret ? "can not be" : "is", bus_max);
3063
3064 if (!ret && !res->parent)
3065 pci_bus_insert_busn_res(b, res->start, res->end);
3066
3067 return ret;
3068}
3069
3070void pci_bus_release_busn_res(struct pci_bus *b)
3071{
3072 struct resource *res = &b->busn_res;
3073 int ret;
3074
3075 if (!res->flags || !res->parent)
3076 return;
3077
3078 ret = release_resource(res);
3079 dev_info(&b->dev, "busn_res: %pR %s released\n",
3080 res, ret ? "can not be" : "is");
3081}
3082
3083int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3084{
3085 struct resource_entry *window;
3086 bool found = false;
3087 struct pci_bus *b;
3088 int max, bus, ret;
3089
3090 if (!bridge)
3091 return -EINVAL;
3092
3093 resource_list_for_each_entry(window, &bridge->windows)
3094 if (window->res->flags & IORESOURCE_BUS) {
3095 bridge->busnr = window->res->start;
3096 found = true;
3097 break;
3098 }
3099
3100 ret = pci_register_host_bridge(bridge);
3101 if (ret < 0)
3102 return ret;
3103
3104 b = bridge->bus;
3105 bus = bridge->busnr;
3106
3107 if (!found) {
3108 dev_info(&b->dev,
3109 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3110 bus);
3111 pci_bus_insert_busn_res(b, bus, 255);
3112 }
3113
3114 max = pci_scan_child_bus(b);
3115
3116 if (!found)
3117 pci_bus_update_busn_res_end(b, max);
3118
3119 return 0;
3120}
3121EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3122
3123struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3124 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3125{
3126 struct resource_entry *window;
3127 bool found = false;
3128 struct pci_bus *b;
3129 int max;
3130
3131 resource_list_for_each_entry(window, resources)
3132 if (window->res->flags & IORESOURCE_BUS) {
3133 found = true;
3134 break;
3135 }
3136
3137 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3138 if (!b)
3139 return NULL;
3140
3141 if (!found) {
3142 dev_info(&b->dev,
3143 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3144 bus);
3145 pci_bus_insert_busn_res(b, bus, 255);
3146 }
3147
3148 max = pci_scan_child_bus(b);
3149
3150 if (!found)
3151 pci_bus_update_busn_res_end(b, max);
3152
3153 return b;
3154}
3155EXPORT_SYMBOL(pci_scan_root_bus);
3156
3157struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3158 void *sysdata)
3159{
3160 LIST_HEAD(resources);
3161 struct pci_bus *b;
3162
3163 pci_add_resource(&resources, &ioport_resource);
3164 pci_add_resource(&resources, &iomem_resource);
3165 pci_add_resource(&resources, &busn_resource);
3166 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3167 if (b) {
3168 pci_scan_child_bus(b);
3169 } else {
3170 pci_free_resource_list(&resources);
3171 }
3172 return b;
3173}
3174EXPORT_SYMBOL(pci_scan_bus);
3175
3176/**
3177 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3178 * @bridge: PCI bridge for the bus to scan
3179 *
3180 * Scan a PCI bus and child buses for new devices, add them,
3181 * and enable them, resizing bridge mmio/io resource if necessary
3182 * and possible. The caller must ensure the child devices are already
3183 * removed for resizing to occur.
3184 *
3185 * Returns the max number of subordinate bus discovered.
3186 */
3187unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3188{
3189 unsigned int max;
3190 struct pci_bus *bus = bridge->subordinate;
3191
3192 max = pci_scan_child_bus(bus);
3193
3194 pci_assign_unassigned_bridge_resources(bridge);
3195
3196 pci_bus_add_devices(bus);
3197
3198 return max;
3199}
3200
3201/**
3202 * pci_rescan_bus - Scan a PCI bus for devices
3203 * @bus: PCI bus to scan
3204 *
3205 * Scan a PCI bus and child buses for new devices, add them,
3206 * and enable them.
3207 *
3208 * Returns the max number of subordinate bus discovered.
3209 */
3210unsigned int pci_rescan_bus(struct pci_bus *bus)
3211{
3212 unsigned int max;
3213
3214 max = pci_scan_child_bus(bus);
3215 pci_assign_unassigned_bus_resources(bus);
3216 pci_bus_add_devices(bus);
3217
3218 return max;
3219}
3220EXPORT_SYMBOL_GPL(pci_rescan_bus);
3221
3222/*
3223 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3224 * routines should always be executed under this mutex.
3225 */
3226static DEFINE_MUTEX(pci_rescan_remove_lock);
3227
3228void pci_lock_rescan_remove(void)
3229{
3230 mutex_lock(&pci_rescan_remove_lock);
3231}
3232EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3233
3234void pci_unlock_rescan_remove(void)
3235{
3236 mutex_unlock(&pci_rescan_remove_lock);
3237}
3238EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3239
3240static int __init pci_sort_bf_cmp(const struct device *d_a,
3241 const struct device *d_b)
3242{
3243 const struct pci_dev *a = to_pci_dev(d_a);
3244 const struct pci_dev *b = to_pci_dev(d_b);
3245
3246 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3247 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3248
3249 if (a->bus->number < b->bus->number) return -1;
3250 else if (a->bus->number > b->bus->number) return 1;
3251
3252 if (a->devfn < b->devfn) return -1;
3253 else if (a->devfn > b->devfn) return 1;
3254
3255 return 0;
3256}
3257
3258void __init pci_sort_breadthfirst(void)
3259{
3260 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3261}
3262
3263int pci_hp_add_bridge(struct pci_dev *dev)
3264{
3265 struct pci_bus *parent = dev->bus;
3266 int busnr, start = parent->busn_res.start;
3267 unsigned int available_buses = 0;
3268 int end = parent->busn_res.end;
3269
3270 for (busnr = start; busnr <= end; busnr++) {
3271 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3272 break;
3273 }
3274 if (busnr-- > end) {
3275 pci_err(dev, "No bus number available for hot-added bridge\n");
3276 return -1;
3277 }
3278
3279 /* Scan bridges that are already configured */
3280 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3281
3282 /*
3283 * Distribute the available bus numbers between hotplug-capable
3284 * bridges to make extending the chain later possible.
3285 */
3286 available_buses = end - busnr;
3287
3288 /* Scan bridges that need to be reconfigured */
3289 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3290
3291 if (!dev->subordinate)
3292 return -1;
3293
3294 return 0;
3295}
3296EXPORT_SYMBOL_GPL(pci_hp_add_bridge);