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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
6 *
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
10 *
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
13 */
14
15#define pr_fmt(fmt) "AER: " fmt
16#define dev_fmt pr_fmt
17
18#include <linux/bitops.h>
19#include <linux/cper.h>
20#include <linux/pci.h>
21#include <linux/pci-acpi.h>
22#include <linux/sched.h>
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/pm.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/kfifo.h>
30#include <linux/slab.h>
31#include <acpi/apei.h>
32#include <acpi/ghes.h>
33#include <ras/ras_event.h>
34
35#include "../pci.h"
36#include "portdrv.h"
37
38#define AER_ERROR_SOURCES_MAX 128
39
40#define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
41#define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
42
43struct aer_err_source {
44 u32 status; /* PCI_ERR_ROOT_STATUS */
45 u32 id; /* PCI_ERR_ROOT_ERR_SRC */
46};
47
48struct aer_rpc {
49 struct pci_dev *rpd; /* Root Port device */
50 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
51};
52
53/* AER stats for the device */
54struct aer_stats {
55
56 /*
57 * Fields for all AER capable devices. They indicate the errors
58 * "as seen by this device". Note that this may mean that if an
59 * end point is causing problems, the AER counters may increment
60 * at its link partner (e.g. root port) because the errors will be
61 * "seen" by the link partner and not the problematic end point
62 * itself (which may report all counters as 0 as it never saw any
63 * problems).
64 */
65 /* Counters for different type of correctable errors */
66 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
67 /* Counters for different type of fatal uncorrectable errors */
68 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
69 /* Counters for different type of nonfatal uncorrectable errors */
70 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
71 /* Total number of ERR_COR sent by this device */
72 u64 dev_total_cor_errs;
73 /* Total number of ERR_FATAL sent by this device */
74 u64 dev_total_fatal_errs;
75 /* Total number of ERR_NONFATAL sent by this device */
76 u64 dev_total_nonfatal_errs;
77
78 /*
79 * Fields for Root ports & root complex event collectors only, these
80 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
81 * messages received by the root port / event collector, INCLUDING the
82 * ones that are generated internally (by the rootport itself)
83 */
84 u64 rootport_total_cor_errs;
85 u64 rootport_total_fatal_errs;
86 u64 rootport_total_nonfatal_errs;
87};
88
89#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
90 PCI_ERR_UNC_ECRC| \
91 PCI_ERR_UNC_UNSUP| \
92 PCI_ERR_UNC_COMP_ABORT| \
93 PCI_ERR_UNC_UNX_COMP| \
94 PCI_ERR_UNC_MALF_TLP)
95
96#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
97 PCI_EXP_RTCTL_SENFEE| \
98 PCI_EXP_RTCTL_SEFEE)
99#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
100 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
101 PCI_ERR_ROOT_CMD_FATAL_EN)
102#define ERR_COR_ID(d) (d & 0xffff)
103#define ERR_UNCOR_ID(d) (d >> 16)
104
105#define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \
106 PCI_ERR_ROOT_COR_RCV | \
107 PCI_ERR_ROOT_MULTI_COR_RCV | \
108 PCI_ERR_ROOT_MULTI_UNCOR_RCV)
109
110static int pcie_aer_disable;
111static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
112
113void pci_no_aer(void)
114{
115 pcie_aer_disable = 1;
116}
117
118bool pci_aer_available(void)
119{
120 return !pcie_aer_disable && pci_msi_enabled();
121}
122
123#ifdef CONFIG_PCIE_ECRC
124
125#define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
126#define ECRC_POLICY_OFF 1 /* ECRC off for performance */
127#define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
128
129static int ecrc_policy = ECRC_POLICY_DEFAULT;
130
131static const char * const ecrc_policy_str[] = {
132 [ECRC_POLICY_DEFAULT] = "bios",
133 [ECRC_POLICY_OFF] = "off",
134 [ECRC_POLICY_ON] = "on"
135};
136
137/**
138 * enable_ecrc_checking - enable PCIe ECRC checking for a device
139 * @dev: the PCI device
140 *
141 * Returns 0 on success, or negative on failure.
142 */
143static int enable_ecrc_checking(struct pci_dev *dev)
144{
145 int aer = dev->aer_cap;
146 u32 reg32;
147
148 if (!aer)
149 return -ENODEV;
150
151 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
152 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
153 reg32 |= PCI_ERR_CAP_ECRC_GENE;
154 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
155 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
156 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
157
158 return 0;
159}
160
161/**
162 * disable_ecrc_checking - disables PCIe ECRC checking for a device
163 * @dev: the PCI device
164 *
165 * Returns 0 on success, or negative on failure.
166 */
167static int disable_ecrc_checking(struct pci_dev *dev)
168{
169 int aer = dev->aer_cap;
170 u32 reg32;
171
172 if (!aer)
173 return -ENODEV;
174
175 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
177 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
178
179 return 0;
180}
181
182/**
183 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
184 * @dev: the PCI device
185 */
186void pcie_set_ecrc_checking(struct pci_dev *dev)
187{
188 if (!pcie_aer_is_native(dev))
189 return;
190
191 switch (ecrc_policy) {
192 case ECRC_POLICY_DEFAULT:
193 return;
194 case ECRC_POLICY_OFF:
195 disable_ecrc_checking(dev);
196 break;
197 case ECRC_POLICY_ON:
198 enable_ecrc_checking(dev);
199 break;
200 default:
201 return;
202 }
203}
204
205/**
206 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
207 * @str: ECRC policy from kernel command line to use
208 */
209void pcie_ecrc_get_policy(char *str)
210{
211 int i;
212
213 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
214 if (i < 0)
215 return;
216
217 ecrc_policy = i;
218}
219#endif /* CONFIG_PCIE_ECRC */
220
221#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
222 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
223
224int pcie_aer_is_native(struct pci_dev *dev)
225{
226 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
227
228 if (!dev->aer_cap)
229 return 0;
230
231 return pcie_ports_native || host->native_aer;
232}
233EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, CXL);
234
235static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
236{
237 int rc;
238
239 if (!pcie_aer_is_native(dev))
240 return -EIO;
241
242 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
243 return pcibios_err_to_errno(rc);
244}
245
246int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
247{
248 int aer = dev->aer_cap;
249 u32 status, sev;
250
251 if (!pcie_aer_is_native(dev))
252 return -EIO;
253
254 /* Clear status bits for ERR_NONFATAL errors only */
255 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
256 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
257 status &= ~sev;
258 if (status)
259 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
260
261 return 0;
262}
263EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
264
265void pci_aer_clear_fatal_status(struct pci_dev *dev)
266{
267 int aer = dev->aer_cap;
268 u32 status, sev;
269
270 if (!pcie_aer_is_native(dev))
271 return;
272
273 /* Clear status bits for ERR_FATAL errors only */
274 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
275 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
276 status &= sev;
277 if (status)
278 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
279}
280
281/**
282 * pci_aer_raw_clear_status - Clear AER error registers.
283 * @dev: the PCI device
284 *
285 * Clearing AER error status registers unconditionally, regardless of
286 * whether they're owned by firmware or the OS.
287 *
288 * Returns 0 on success, or negative on failure.
289 */
290int pci_aer_raw_clear_status(struct pci_dev *dev)
291{
292 int aer = dev->aer_cap;
293 u32 status;
294 int port_type;
295
296 if (!aer)
297 return -EIO;
298
299 port_type = pci_pcie_type(dev);
300 if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
301 port_type == PCI_EXP_TYPE_RC_EC) {
302 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
303 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
304 }
305
306 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
307 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
308
309 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
310 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
311
312 return 0;
313}
314
315int pci_aer_clear_status(struct pci_dev *dev)
316{
317 if (!pcie_aer_is_native(dev))
318 return -EIO;
319
320 return pci_aer_raw_clear_status(dev);
321}
322
323void pci_save_aer_state(struct pci_dev *dev)
324{
325 int aer = dev->aer_cap;
326 struct pci_cap_saved_state *save_state;
327 u32 *cap;
328
329 if (!aer)
330 return;
331
332 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
333 if (!save_state)
334 return;
335
336 cap = &save_state->cap.data[0];
337 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
338 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
339 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
340 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
341 if (pcie_cap_has_rtctl(dev))
342 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
343}
344
345void pci_restore_aer_state(struct pci_dev *dev)
346{
347 int aer = dev->aer_cap;
348 struct pci_cap_saved_state *save_state;
349 u32 *cap;
350
351 if (!aer)
352 return;
353
354 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
355 if (!save_state)
356 return;
357
358 cap = &save_state->cap.data[0];
359 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
360 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
361 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
362 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
363 if (pcie_cap_has_rtctl(dev))
364 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
365}
366
367void pci_aer_init(struct pci_dev *dev)
368{
369 int n;
370
371 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
372 if (!dev->aer_cap)
373 return;
374
375 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
376
377 /*
378 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
379 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
380 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
381 * 7.8.4).
382 */
383 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
384 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
385
386 pci_aer_clear_status(dev);
387
388 if (pci_aer_available())
389 pci_enable_pcie_error_reporting(dev);
390
391 pcie_set_ecrc_checking(dev);
392}
393
394void pci_aer_exit(struct pci_dev *dev)
395{
396 kfree(dev->aer_stats);
397 dev->aer_stats = NULL;
398}
399
400#define AER_AGENT_RECEIVER 0
401#define AER_AGENT_REQUESTER 1
402#define AER_AGENT_COMPLETER 2
403#define AER_AGENT_TRANSMITTER 3
404
405#define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
406 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
407#define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
408 0 : PCI_ERR_UNC_COMP_ABORT)
409#define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
410 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
411
412#define AER_GET_AGENT(t, e) \
413 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
414 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
415 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
416 AER_AGENT_RECEIVER)
417
418#define AER_PHYSICAL_LAYER_ERROR 0
419#define AER_DATA_LINK_LAYER_ERROR 1
420#define AER_TRANSACTION_LAYER_ERROR 2
421
422#define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
423 PCI_ERR_COR_RCVR : 0)
424#define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
425 (PCI_ERR_COR_BAD_TLP| \
426 PCI_ERR_COR_BAD_DLLP| \
427 PCI_ERR_COR_REP_ROLL| \
428 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
429
430#define AER_GET_LAYER_ERROR(t, e) \
431 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
432 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
433 AER_TRANSACTION_LAYER_ERROR)
434
435/*
436 * AER error strings
437 */
438static const char * const aer_error_severity_string[] = {
439 "Uncorrectable (Non-Fatal)",
440 "Uncorrectable (Fatal)",
441 "Correctable"
442};
443
444static const char *aer_error_layer[] = {
445 "Physical Layer",
446 "Data Link Layer",
447 "Transaction Layer"
448};
449
450static const char *aer_correctable_error_string[] = {
451 "RxErr", /* Bit Position 0 */
452 NULL,
453 NULL,
454 NULL,
455 NULL,
456 NULL,
457 "BadTLP", /* Bit Position 6 */
458 "BadDLLP", /* Bit Position 7 */
459 "Rollover", /* Bit Position 8 */
460 NULL,
461 NULL,
462 NULL,
463 "Timeout", /* Bit Position 12 */
464 "NonFatalErr", /* Bit Position 13 */
465 "CorrIntErr", /* Bit Position 14 */
466 "HeaderOF", /* Bit Position 15 */
467 NULL, /* Bit Position 16 */
468 NULL, /* Bit Position 17 */
469 NULL, /* Bit Position 18 */
470 NULL, /* Bit Position 19 */
471 NULL, /* Bit Position 20 */
472 NULL, /* Bit Position 21 */
473 NULL, /* Bit Position 22 */
474 NULL, /* Bit Position 23 */
475 NULL, /* Bit Position 24 */
476 NULL, /* Bit Position 25 */
477 NULL, /* Bit Position 26 */
478 NULL, /* Bit Position 27 */
479 NULL, /* Bit Position 28 */
480 NULL, /* Bit Position 29 */
481 NULL, /* Bit Position 30 */
482 NULL, /* Bit Position 31 */
483};
484
485static const char *aer_uncorrectable_error_string[] = {
486 "Undefined", /* Bit Position 0 */
487 NULL,
488 NULL,
489 NULL,
490 "DLP", /* Bit Position 4 */
491 "SDES", /* Bit Position 5 */
492 NULL,
493 NULL,
494 NULL,
495 NULL,
496 NULL,
497 NULL,
498 "TLP", /* Bit Position 12 */
499 "FCP", /* Bit Position 13 */
500 "CmpltTO", /* Bit Position 14 */
501 "CmpltAbrt", /* Bit Position 15 */
502 "UnxCmplt", /* Bit Position 16 */
503 "RxOF", /* Bit Position 17 */
504 "MalfTLP", /* Bit Position 18 */
505 "ECRC", /* Bit Position 19 */
506 "UnsupReq", /* Bit Position 20 */
507 "ACSViol", /* Bit Position 21 */
508 "UncorrIntErr", /* Bit Position 22 */
509 "BlockedTLP", /* Bit Position 23 */
510 "AtomicOpBlocked", /* Bit Position 24 */
511 "TLPBlockedErr", /* Bit Position 25 */
512 "PoisonTLPBlocked", /* Bit Position 26 */
513 NULL, /* Bit Position 27 */
514 NULL, /* Bit Position 28 */
515 NULL, /* Bit Position 29 */
516 NULL, /* Bit Position 30 */
517 NULL, /* Bit Position 31 */
518};
519
520static const char *aer_agent_string[] = {
521 "Receiver ID",
522 "Requester ID",
523 "Completer ID",
524 "Transmitter ID"
525};
526
527#define aer_stats_dev_attr(name, stats_array, strings_array, \
528 total_string, total_field) \
529 static ssize_t \
530 name##_show(struct device *dev, struct device_attribute *attr, \
531 char *buf) \
532{ \
533 unsigned int i; \
534 struct pci_dev *pdev = to_pci_dev(dev); \
535 u64 *stats = pdev->aer_stats->stats_array; \
536 size_t len = 0; \
537 \
538 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\
539 if (strings_array[i]) \
540 len += sysfs_emit_at(buf, len, "%s %llu\n", \
541 strings_array[i], \
542 stats[i]); \
543 else if (stats[i]) \
544 len += sysfs_emit_at(buf, len, \
545 #stats_array "_bit[%d] %llu\n",\
546 i, stats[i]); \
547 } \
548 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \
549 pdev->aer_stats->total_field); \
550 return len; \
551} \
552static DEVICE_ATTR_RO(name)
553
554aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
555 aer_correctable_error_string, "ERR_COR",
556 dev_total_cor_errs);
557aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
558 aer_uncorrectable_error_string, "ERR_FATAL",
559 dev_total_fatal_errs);
560aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
561 aer_uncorrectable_error_string, "ERR_NONFATAL",
562 dev_total_nonfatal_errs);
563
564#define aer_stats_rootport_attr(name, field) \
565 static ssize_t \
566 name##_show(struct device *dev, struct device_attribute *attr, \
567 char *buf) \
568{ \
569 struct pci_dev *pdev = to_pci_dev(dev); \
570 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \
571} \
572static DEVICE_ATTR_RO(name)
573
574aer_stats_rootport_attr(aer_rootport_total_err_cor,
575 rootport_total_cor_errs);
576aer_stats_rootport_attr(aer_rootport_total_err_fatal,
577 rootport_total_fatal_errs);
578aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
579 rootport_total_nonfatal_errs);
580
581static struct attribute *aer_stats_attrs[] __ro_after_init = {
582 &dev_attr_aer_dev_correctable.attr,
583 &dev_attr_aer_dev_fatal.attr,
584 &dev_attr_aer_dev_nonfatal.attr,
585 &dev_attr_aer_rootport_total_err_cor.attr,
586 &dev_attr_aer_rootport_total_err_fatal.attr,
587 &dev_attr_aer_rootport_total_err_nonfatal.attr,
588 NULL
589};
590
591static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
592 struct attribute *a, int n)
593{
594 struct device *dev = kobj_to_dev(kobj);
595 struct pci_dev *pdev = to_pci_dev(dev);
596
597 if (!pdev->aer_stats)
598 return 0;
599
600 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
601 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
602 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
603 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
604 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC)))
605 return 0;
606
607 return a->mode;
608}
609
610const struct attribute_group aer_stats_attr_group = {
611 .attrs = aer_stats_attrs,
612 .is_visible = aer_stats_attrs_are_visible,
613};
614
615static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
616 struct aer_err_info *info)
617{
618 unsigned long status = info->status & ~info->mask;
619 int i, max = -1;
620 u64 *counter = NULL;
621 struct aer_stats *aer_stats = pdev->aer_stats;
622
623 if (!aer_stats)
624 return;
625
626 switch (info->severity) {
627 case AER_CORRECTABLE:
628 aer_stats->dev_total_cor_errs++;
629 counter = &aer_stats->dev_cor_errs[0];
630 max = AER_MAX_TYPEOF_COR_ERRS;
631 break;
632 case AER_NONFATAL:
633 aer_stats->dev_total_nonfatal_errs++;
634 counter = &aer_stats->dev_nonfatal_errs[0];
635 max = AER_MAX_TYPEOF_UNCOR_ERRS;
636 break;
637 case AER_FATAL:
638 aer_stats->dev_total_fatal_errs++;
639 counter = &aer_stats->dev_fatal_errs[0];
640 max = AER_MAX_TYPEOF_UNCOR_ERRS;
641 break;
642 }
643
644 for_each_set_bit(i, &status, max)
645 counter[i]++;
646}
647
648static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
649 struct aer_err_source *e_src)
650{
651 struct aer_stats *aer_stats = pdev->aer_stats;
652
653 if (!aer_stats)
654 return;
655
656 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
657 aer_stats->rootport_total_cor_errs++;
658
659 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
660 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
661 aer_stats->rootport_total_fatal_errs++;
662 else
663 aer_stats->rootport_total_nonfatal_errs++;
664 }
665}
666
667static void __print_tlp_header(struct pci_dev *dev,
668 struct aer_header_log_regs *t)
669{
670 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
671 t->dw0, t->dw1, t->dw2, t->dw3);
672}
673
674static void __aer_print_error(struct pci_dev *dev,
675 struct aer_err_info *info)
676{
677 const char **strings;
678 unsigned long status = info->status & ~info->mask;
679 const char *level, *errmsg;
680 int i;
681
682 if (info->severity == AER_CORRECTABLE) {
683 strings = aer_correctable_error_string;
684 level = KERN_WARNING;
685 } else {
686 strings = aer_uncorrectable_error_string;
687 level = KERN_ERR;
688 }
689
690 for_each_set_bit(i, &status, 32) {
691 errmsg = strings[i];
692 if (!errmsg)
693 errmsg = "Unknown Error Bit";
694
695 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
696 info->first_error == i ? " (First)" : "");
697 }
698 pci_dev_aer_stats_incr(dev, info);
699}
700
701void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
702{
703 int layer, agent;
704 int id = pci_dev_id(dev);
705 const char *level;
706
707 if (!info->status) {
708 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
709 aer_error_severity_string[info->severity]);
710 goto out;
711 }
712
713 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
714 agent = AER_GET_AGENT(info->severity, info->status);
715
716 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
717
718 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
719 aer_error_severity_string[info->severity],
720 aer_error_layer[layer], aer_agent_string[agent]);
721
722 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
723 dev->vendor, dev->device, info->status, info->mask);
724
725 __aer_print_error(dev, info);
726
727 if (info->tlp_header_valid)
728 __print_tlp_header(dev, &info->tlp);
729
730out:
731 if (info->id && info->error_dev_num > 1 && info->id == id)
732 pci_err(dev, " Error of this Agent is reported first\n");
733
734 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
735 info->severity, info->tlp_header_valid, &info->tlp);
736}
737
738static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
739{
740 u8 bus = info->id >> 8;
741 u8 devfn = info->id & 0xff;
742
743 pci_info(dev, "%s%s error message received from %04x:%02x:%02x.%d\n",
744 info->multi_error_valid ? "Multiple " : "",
745 aer_error_severity_string[info->severity],
746 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
747 PCI_FUNC(devfn));
748}
749
750#ifdef CONFIG_ACPI_APEI_PCIEAER
751int cper_severity_to_aer(int cper_severity)
752{
753 switch (cper_severity) {
754 case CPER_SEV_RECOVERABLE:
755 return AER_NONFATAL;
756 case CPER_SEV_FATAL:
757 return AER_FATAL;
758 default:
759 return AER_CORRECTABLE;
760 }
761}
762EXPORT_SYMBOL_GPL(cper_severity_to_aer);
763#endif
764
765void pci_print_aer(struct pci_dev *dev, int aer_severity,
766 struct aer_capability_regs *aer)
767{
768 int layer, agent, tlp_header_valid = 0;
769 u32 status, mask;
770 struct aer_err_info info;
771
772 if (aer_severity == AER_CORRECTABLE) {
773 status = aer->cor_status;
774 mask = aer->cor_mask;
775 } else {
776 status = aer->uncor_status;
777 mask = aer->uncor_mask;
778 tlp_header_valid = status & AER_LOG_TLP_MASKS;
779 }
780
781 layer = AER_GET_LAYER_ERROR(aer_severity, status);
782 agent = AER_GET_AGENT(aer_severity, status);
783
784 memset(&info, 0, sizeof(info));
785 info.severity = aer_severity;
786 info.status = status;
787 info.mask = mask;
788 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
789
790 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
791 __aer_print_error(dev, &info);
792 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
793 aer_error_layer[layer], aer_agent_string[agent]);
794
795 if (aer_severity != AER_CORRECTABLE)
796 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
797 aer->uncor_severity);
798
799 if (tlp_header_valid)
800 __print_tlp_header(dev, &aer->header_log);
801
802 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
803 aer_severity, tlp_header_valid, &aer->header_log);
804}
805EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL);
806
807/**
808 * add_error_device - list device to be handled
809 * @e_info: pointer to error info
810 * @dev: pointer to pci_dev to be added
811 */
812static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
813{
814 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
815 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
816 e_info->error_dev_num++;
817 return 0;
818 }
819 return -ENOSPC;
820}
821
822/**
823 * is_error_source - check whether the device is source of reported error
824 * @dev: pointer to pci_dev to be checked
825 * @e_info: pointer to reported error info
826 */
827static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
828{
829 int aer = dev->aer_cap;
830 u32 status, mask;
831 u16 reg16;
832
833 /*
834 * When bus id is equal to 0, it might be a bad id
835 * reported by root port.
836 */
837 if ((PCI_BUS_NUM(e_info->id) != 0) &&
838 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
839 /* Device ID match? */
840 if (e_info->id == pci_dev_id(dev))
841 return true;
842
843 /* Continue id comparing if there is no multiple error */
844 if (!e_info->multi_error_valid)
845 return false;
846 }
847
848 /*
849 * When either
850 * 1) bus id is equal to 0. Some ports might lose the bus
851 * id of error source id;
852 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
853 * 3) There are multiple errors and prior ID comparing fails;
854 * We check AER status registers to find possible reporter.
855 */
856 if (atomic_read(&dev->enable_cnt) == 0)
857 return false;
858
859 /* Check if AER is enabled */
860 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
861 if (!(reg16 & PCI_EXP_AER_FLAGS))
862 return false;
863
864 if (!aer)
865 return false;
866
867 /* Check if error is recorded */
868 if (e_info->severity == AER_CORRECTABLE) {
869 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
870 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
871 } else {
872 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
873 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
874 }
875 if (status & ~mask)
876 return true;
877
878 return false;
879}
880
881static int find_device_iter(struct pci_dev *dev, void *data)
882{
883 struct aer_err_info *e_info = (struct aer_err_info *)data;
884
885 if (is_error_source(dev, e_info)) {
886 /* List this device */
887 if (add_error_device(e_info, dev)) {
888 /* We cannot handle more... Stop iteration */
889 /* TODO: Should print error message here? */
890 return 1;
891 }
892
893 /* If there is only a single error, stop iteration */
894 if (!e_info->multi_error_valid)
895 return 1;
896 }
897 return 0;
898}
899
900/**
901 * find_source_device - search through device hierarchy for source device
902 * @parent: pointer to Root Port pci_dev data structure
903 * @e_info: including detailed error information such like id
904 *
905 * Return true if found.
906 *
907 * Invoked by DPC when error is detected at the Root Port.
908 * Caller of this function must set id, severity, and multi_error_valid of
909 * struct aer_err_info pointed by @e_info properly. This function must fill
910 * e_info->error_dev_num and e_info->dev[], based on the given information.
911 */
912static bool find_source_device(struct pci_dev *parent,
913 struct aer_err_info *e_info)
914{
915 struct pci_dev *dev = parent;
916 int result;
917
918 /* Must reset in this function */
919 e_info->error_dev_num = 0;
920
921 /* Is Root Port an agent that sends error message? */
922 result = find_device_iter(dev, e_info);
923 if (result)
924 return true;
925
926 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC)
927 pcie_walk_rcec(parent, find_device_iter, e_info);
928 else
929 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
930
931 if (!e_info->error_dev_num) {
932 u8 bus = e_info->id >> 8;
933 u8 devfn = e_info->id & 0xff;
934
935 pci_info(parent, "found no error details for %04x:%02x:%02x.%d\n",
936 pci_domain_nr(parent->bus), bus, PCI_SLOT(devfn),
937 PCI_FUNC(devfn));
938 return false;
939 }
940 return true;
941}
942
943#ifdef CONFIG_PCIEAER_CXL
944
945/**
946 * pci_aer_unmask_internal_errors - unmask internal errors
947 * @dev: pointer to the pcie_dev data structure
948 *
949 * Unmasks internal errors in the Uncorrectable and Correctable Error
950 * Mask registers.
951 *
952 * Note: AER must be enabled and supported by the device which must be
953 * checked in advance, e.g. with pcie_aer_is_native().
954 */
955static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
956{
957 int aer = dev->aer_cap;
958 u32 mask;
959
960 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
961 mask &= ~PCI_ERR_UNC_INTN;
962 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
963
964 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
965 mask &= ~PCI_ERR_COR_INTERNAL;
966 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
967}
968
969static bool is_cxl_mem_dev(struct pci_dev *dev)
970{
971 /*
972 * The capability, status, and control fields in Device 0,
973 * Function 0 DVSEC control the CXL functionality of the
974 * entire device (CXL 3.0, 8.1.3).
975 */
976 if (dev->devfn != PCI_DEVFN(0, 0))
977 return false;
978
979 /*
980 * CXL Memory Devices must have the 502h class code set (CXL
981 * 3.0, 8.1.12.1).
982 */
983 if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
984 return false;
985
986 return true;
987}
988
989static bool cxl_error_is_native(struct pci_dev *dev)
990{
991 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
992
993 return (pcie_ports_native || host->native_aer);
994}
995
996static bool is_internal_error(struct aer_err_info *info)
997{
998 if (info->severity == AER_CORRECTABLE)
999 return info->status & PCI_ERR_COR_INTERNAL;
1000
1001 return info->status & PCI_ERR_UNC_INTN;
1002}
1003
1004static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
1005{
1006 struct aer_err_info *info = (struct aer_err_info *)data;
1007 const struct pci_error_handlers *err_handler;
1008
1009 if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
1010 return 0;
1011
1012 /* protect dev->driver */
1013 device_lock(&dev->dev);
1014
1015 err_handler = dev->driver ? dev->driver->err_handler : NULL;
1016 if (!err_handler)
1017 goto out;
1018
1019 if (info->severity == AER_CORRECTABLE) {
1020 if (err_handler->cor_error_detected)
1021 err_handler->cor_error_detected(dev);
1022 } else if (err_handler->error_detected) {
1023 if (info->severity == AER_NONFATAL)
1024 err_handler->error_detected(dev, pci_channel_io_normal);
1025 else if (info->severity == AER_FATAL)
1026 err_handler->error_detected(dev, pci_channel_io_frozen);
1027 }
1028out:
1029 device_unlock(&dev->dev);
1030 return 0;
1031}
1032
1033static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
1034{
1035 /*
1036 * Internal errors of an RCEC indicate an AER error in an
1037 * RCH's downstream port. Check and handle them in the CXL.mem
1038 * device driver.
1039 */
1040 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
1041 is_internal_error(info))
1042 pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
1043}
1044
1045static int handles_cxl_error_iter(struct pci_dev *dev, void *data)
1046{
1047 bool *handles_cxl = data;
1048
1049 if (!*handles_cxl)
1050 *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev);
1051
1052 /* Non-zero terminates iteration */
1053 return *handles_cxl;
1054}
1055
1056static bool handles_cxl_errors(struct pci_dev *rcec)
1057{
1058 bool handles_cxl = false;
1059
1060 if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC &&
1061 pcie_aer_is_native(rcec))
1062 pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl);
1063
1064 return handles_cxl;
1065}
1066
1067static void cxl_rch_enable_rcec(struct pci_dev *rcec)
1068{
1069 if (!handles_cxl_errors(rcec))
1070 return;
1071
1072 pci_aer_unmask_internal_errors(rcec);
1073 pci_info(rcec, "CXL: Internal errors unmasked");
1074}
1075
1076#else
1077static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { }
1078static inline void cxl_rch_handle_error(struct pci_dev *dev,
1079 struct aer_err_info *info) { }
1080#endif
1081
1082/**
1083 * pci_aer_handle_error - handle logging error into an event log
1084 * @dev: pointer to pci_dev data structure of error source device
1085 * @info: comprehensive error information
1086 *
1087 * Invoked when an error being detected by Root Port.
1088 */
1089static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
1090{
1091 int aer = dev->aer_cap;
1092
1093 if (info->severity == AER_CORRECTABLE) {
1094 /*
1095 * Correctable error does not need software intervention.
1096 * No need to go through error recovery process.
1097 */
1098 if (aer)
1099 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1100 info->status);
1101 if (pcie_aer_is_native(dev)) {
1102 struct pci_driver *pdrv = dev->driver;
1103
1104 if (pdrv && pdrv->err_handler &&
1105 pdrv->err_handler->cor_error_detected)
1106 pdrv->err_handler->cor_error_detected(dev);
1107 pcie_clear_device_status(dev);
1108 }
1109 } else if (info->severity == AER_NONFATAL)
1110 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
1111 else if (info->severity == AER_FATAL)
1112 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
1113}
1114
1115static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
1116{
1117 cxl_rch_handle_error(dev, info);
1118 pci_aer_handle_error(dev, info);
1119 pci_dev_put(dev);
1120}
1121
1122#ifdef CONFIG_ACPI_APEI_PCIEAER
1123
1124#define AER_RECOVER_RING_SIZE 16
1125
1126struct aer_recover_entry {
1127 u8 bus;
1128 u8 devfn;
1129 u16 domain;
1130 int severity;
1131 struct aer_capability_regs *regs;
1132};
1133
1134static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
1135 AER_RECOVER_RING_SIZE);
1136
1137static void aer_recover_work_func(struct work_struct *work)
1138{
1139 struct aer_recover_entry entry;
1140 struct pci_dev *pdev;
1141
1142 while (kfifo_get(&aer_recover_ring, &entry)) {
1143 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
1144 entry.devfn);
1145 if (!pdev) {
1146 pr_err("no pci_dev for %04x:%02x:%02x.%x\n",
1147 entry.domain, entry.bus,
1148 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
1149 continue;
1150 }
1151 pci_print_aer(pdev, entry.severity, entry.regs);
1152 /*
1153 * Memory for aer_capability_regs(entry.regs) is being allocated from the
1154 * ghes_estatus_pool to protect it from overwriting when multiple sections
1155 * are present in the error status. Thus free the same after processing
1156 * the data.
1157 */
1158 ghes_estatus_pool_region_free((unsigned long)entry.regs,
1159 sizeof(struct aer_capability_regs));
1160
1161 if (entry.severity == AER_NONFATAL)
1162 pcie_do_recovery(pdev, pci_channel_io_normal,
1163 aer_root_reset);
1164 else if (entry.severity == AER_FATAL)
1165 pcie_do_recovery(pdev, pci_channel_io_frozen,
1166 aer_root_reset);
1167 pci_dev_put(pdev);
1168 }
1169}
1170
1171/*
1172 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1173 * need lock, because there is only one reader and lock is not needed
1174 * between reader and writer.
1175 */
1176static DEFINE_SPINLOCK(aer_recover_ring_lock);
1177static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1178
1179void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1180 int severity, struct aer_capability_regs *aer_regs)
1181{
1182 struct aer_recover_entry entry = {
1183 .bus = bus,
1184 .devfn = devfn,
1185 .domain = domain,
1186 .severity = severity,
1187 .regs = aer_regs,
1188 };
1189
1190 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
1191 &aer_recover_ring_lock))
1192 schedule_work(&aer_recover_work);
1193 else
1194 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n",
1195 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1196}
1197EXPORT_SYMBOL_GPL(aer_recover_queue);
1198#endif
1199
1200/**
1201 * aer_get_device_error_info - read error status from dev and store it to info
1202 * @dev: pointer to the device expected to have a error record
1203 * @info: pointer to structure to store the error record
1204 *
1205 * Return 1 on success, 0 on error.
1206 *
1207 * Note that @info is reused among all error devices. Clear fields properly.
1208 */
1209int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
1210{
1211 int type = pci_pcie_type(dev);
1212 int aer = dev->aer_cap;
1213 int temp;
1214
1215 /* Must reset in this function */
1216 info->status = 0;
1217 info->tlp_header_valid = 0;
1218
1219 /* The device might not support AER */
1220 if (!aer)
1221 return 0;
1222
1223 if (info->severity == AER_CORRECTABLE) {
1224 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1225 &info->status);
1226 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1227 &info->mask);
1228 if (!(info->status & ~info->mask))
1229 return 0;
1230 } else if (type == PCI_EXP_TYPE_ROOT_PORT ||
1231 type == PCI_EXP_TYPE_RC_EC ||
1232 type == PCI_EXP_TYPE_DOWNSTREAM ||
1233 info->severity == AER_NONFATAL) {
1234
1235 /* Link is still healthy for IO reads */
1236 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1237 &info->status);
1238 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1239 &info->mask);
1240 if (!(info->status & ~info->mask))
1241 return 0;
1242
1243 /* Get First Error Pointer */
1244 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1245 info->first_error = PCI_ERR_CAP_FEP(temp);
1246
1247 if (info->status & AER_LOG_TLP_MASKS) {
1248 info->tlp_header_valid = 1;
1249 pci_read_config_dword(dev,
1250 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1251 pci_read_config_dword(dev,
1252 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1253 pci_read_config_dword(dev,
1254 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1255 pci_read_config_dword(dev,
1256 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1257 }
1258 }
1259
1260 return 1;
1261}
1262
1263static inline void aer_process_err_devices(struct aer_err_info *e_info)
1264{
1265 int i;
1266
1267 /* Report all before handle them, not to lost records by reset etc. */
1268 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1269 if (aer_get_device_error_info(e_info->dev[i], e_info))
1270 aer_print_error(e_info->dev[i], e_info);
1271 }
1272 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1273 if (aer_get_device_error_info(e_info->dev[i], e_info))
1274 handle_error_source(e_info->dev[i], e_info);
1275 }
1276}
1277
1278/**
1279 * aer_isr_one_error - consume an error detected by root port
1280 * @rpc: pointer to the root port which holds an error
1281 * @e_src: pointer to an error source
1282 */
1283static void aer_isr_one_error(struct aer_rpc *rpc,
1284 struct aer_err_source *e_src)
1285{
1286 struct pci_dev *pdev = rpc->rpd;
1287 struct aer_err_info e_info;
1288
1289 pci_rootport_aer_stats_incr(pdev, e_src);
1290
1291 /*
1292 * There is a possibility that both correctable error and
1293 * uncorrectable error being logged. Report correctable error first.
1294 */
1295 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1296 e_info.id = ERR_COR_ID(e_src->id);
1297 e_info.severity = AER_CORRECTABLE;
1298
1299 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1300 e_info.multi_error_valid = 1;
1301 else
1302 e_info.multi_error_valid = 0;
1303 aer_print_port_info(pdev, &e_info);
1304
1305 if (find_source_device(pdev, &e_info))
1306 aer_process_err_devices(&e_info);
1307 }
1308
1309 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1310 e_info.id = ERR_UNCOR_ID(e_src->id);
1311
1312 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1313 e_info.severity = AER_FATAL;
1314 else
1315 e_info.severity = AER_NONFATAL;
1316
1317 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1318 e_info.multi_error_valid = 1;
1319 else
1320 e_info.multi_error_valid = 0;
1321
1322 aer_print_port_info(pdev, &e_info);
1323
1324 if (find_source_device(pdev, &e_info))
1325 aer_process_err_devices(&e_info);
1326 }
1327}
1328
1329/**
1330 * aer_isr - consume errors detected by root port
1331 * @irq: IRQ assigned to Root Port
1332 * @context: pointer to Root Port data structure
1333 *
1334 * Invoked, as DPC, when root port records new detected error
1335 */
1336static irqreturn_t aer_isr(int irq, void *context)
1337{
1338 struct pcie_device *dev = (struct pcie_device *)context;
1339 struct aer_rpc *rpc = get_service_data(dev);
1340 struct aer_err_source e_src;
1341
1342 if (kfifo_is_empty(&rpc->aer_fifo))
1343 return IRQ_NONE;
1344
1345 while (kfifo_get(&rpc->aer_fifo, &e_src))
1346 aer_isr_one_error(rpc, &e_src);
1347 return IRQ_HANDLED;
1348}
1349
1350/**
1351 * aer_irq - Root Port's ISR
1352 * @irq: IRQ assigned to Root Port
1353 * @context: pointer to Root Port data structure
1354 *
1355 * Invoked when Root Port detects AER messages.
1356 */
1357static irqreturn_t aer_irq(int irq, void *context)
1358{
1359 struct pcie_device *pdev = (struct pcie_device *)context;
1360 struct aer_rpc *rpc = get_service_data(pdev);
1361 struct pci_dev *rp = rpc->rpd;
1362 int aer = rp->aer_cap;
1363 struct aer_err_source e_src = {};
1364
1365 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1366 if (!(e_src.status & AER_ERR_STATUS_MASK))
1367 return IRQ_NONE;
1368
1369 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1370 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1371
1372 if (!kfifo_put(&rpc->aer_fifo, e_src))
1373 return IRQ_HANDLED;
1374
1375 return IRQ_WAKE_THREAD;
1376}
1377
1378static void aer_enable_irq(struct pci_dev *pdev)
1379{
1380 int aer = pdev->aer_cap;
1381 u32 reg32;
1382
1383 /* Enable Root Port's interrupt in response to error messages */
1384 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1385 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1386 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1387}
1388
1389static void aer_disable_irq(struct pci_dev *pdev)
1390{
1391 int aer = pdev->aer_cap;
1392 u32 reg32;
1393
1394 /* Disable Root's interrupt in response to error messages */
1395 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1396 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1397 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1398}
1399
1400/**
1401 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1402 * @rpc: pointer to a Root Port data structure
1403 *
1404 * Invoked when PCIe bus loads AER service driver.
1405 */
1406static void aer_enable_rootport(struct aer_rpc *rpc)
1407{
1408 struct pci_dev *pdev = rpc->rpd;
1409 int aer = pdev->aer_cap;
1410 u16 reg16;
1411 u32 reg32;
1412
1413 /* Clear PCIe Capability's Device Status */
1414 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1415 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1416
1417 /* Disable system error generation in response to error messages */
1418 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1419 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1420
1421 /* Clear error status */
1422 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1423 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1424 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1425 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1426 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1427 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1428
1429 aer_enable_irq(pdev);
1430}
1431
1432/**
1433 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1434 * @rpc: pointer to a Root Port data structure
1435 *
1436 * Invoked when PCIe bus unloads AER service driver.
1437 */
1438static void aer_disable_rootport(struct aer_rpc *rpc)
1439{
1440 struct pci_dev *pdev = rpc->rpd;
1441 int aer = pdev->aer_cap;
1442 u32 reg32;
1443
1444 aer_disable_irq(pdev);
1445
1446 /* Clear Root's error status reg */
1447 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1448 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1449}
1450
1451/**
1452 * aer_remove - clean up resources
1453 * @dev: pointer to the pcie_dev data structure
1454 *
1455 * Invoked when PCI Express bus unloads or AER probe fails.
1456 */
1457static void aer_remove(struct pcie_device *dev)
1458{
1459 struct aer_rpc *rpc = get_service_data(dev);
1460
1461 aer_disable_rootport(rpc);
1462}
1463
1464/**
1465 * aer_probe - initialize resources
1466 * @dev: pointer to the pcie_dev data structure
1467 *
1468 * Invoked when PCI Express bus loads AER service driver.
1469 */
1470static int aer_probe(struct pcie_device *dev)
1471{
1472 int status;
1473 struct aer_rpc *rpc;
1474 struct device *device = &dev->device;
1475 struct pci_dev *port = dev->port;
1476
1477 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) <
1478 AER_MAX_TYPEOF_COR_ERRS);
1479 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) <
1480 AER_MAX_TYPEOF_UNCOR_ERRS);
1481
1482 /* Limit to Root Ports or Root Complex Event Collectors */
1483 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) &&
1484 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT))
1485 return -ENODEV;
1486
1487 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1488 if (!rpc)
1489 return -ENOMEM;
1490
1491 rpc->rpd = port;
1492 INIT_KFIFO(rpc->aer_fifo);
1493 set_service_data(dev, rpc);
1494
1495 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1496 IRQF_SHARED, "aerdrv", dev);
1497 if (status) {
1498 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1499 return status;
1500 }
1501
1502 cxl_rch_enable_rcec(port);
1503 aer_enable_rootport(rpc);
1504 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1505 return 0;
1506}
1507
1508/**
1509 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP
1510 * @dev: pointer to Root Port, RCEC, or RCiEP
1511 *
1512 * Invoked by Port Bus driver when performing reset.
1513 */
1514static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1515{
1516 int type = pci_pcie_type(dev);
1517 struct pci_dev *root;
1518 int aer;
1519 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
1520 u32 reg32;
1521 int rc;
1522
1523 /*
1524 * Only Root Ports and RCECs have AER Root Command and Root Status
1525 * registers. If "dev" is an RCiEP, the relevant registers are in
1526 * the RCEC.
1527 */
1528 if (type == PCI_EXP_TYPE_RC_END)
1529 root = dev->rcec;
1530 else
1531 root = pcie_find_root_port(dev);
1532
1533 /*
1534 * If the platform retained control of AER, an RCiEP may not have
1535 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In
1536 * that case, firmware is responsible for these registers.
1537 */
1538 aer = root ? root->aer_cap : 0;
1539
1540 if ((host->native_aer || pcie_ports_native) && aer)
1541 aer_disable_irq(root);
1542
1543 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) {
1544 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET);
1545 if (!rc)
1546 pci_info(dev, "has been reset\n");
1547 else
1548 pci_info(dev, "not reset (no FLR support: %d)\n", rc);
1549 } else {
1550 rc = pci_bus_error_reset(dev);
1551 pci_info(dev, "%s Port link has been reset (%d)\n",
1552 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc);
1553 }
1554
1555 if ((host->native_aer || pcie_ports_native) && aer) {
1556 /* Clear Root Error Status */
1557 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32);
1558 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);
1559
1560 aer_enable_irq(root);
1561 }
1562
1563 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1564}
1565
1566static struct pcie_port_service_driver aerdriver = {
1567 .name = "aer",
1568 .port_type = PCIE_ANY_PORT,
1569 .service = PCIE_PORT_SERVICE_AER,
1570
1571 .probe = aer_probe,
1572 .remove = aer_remove,
1573};
1574
1575/**
1576 * pcie_aer_init - register AER root service driver
1577 *
1578 * Invoked when AER root service driver is loaded.
1579 */
1580int __init pcie_aer_init(void)
1581{
1582 if (!pci_aer_available())
1583 return -ENXIO;
1584 return pcie_port_service_register(&aerdriver);
1585}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
6 *
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
10 *
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
13 */
14
15#define pr_fmt(fmt) "AER: " fmt
16#define dev_fmt pr_fmt
17
18#include <linux/bitops.h>
19#include <linux/cper.h>
20#include <linux/pci.h>
21#include <linux/pci-acpi.h>
22#include <linux/sched.h>
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/pm.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/kfifo.h>
30#include <linux/slab.h>
31#include <acpi/apei.h>
32#include <ras/ras_event.h>
33
34#include "../pci.h"
35#include "portdrv.h"
36
37#define AER_ERROR_SOURCES_MAX 128
38
39#define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
40#define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
41
42struct aer_err_source {
43 unsigned int status;
44 unsigned int id;
45};
46
47struct aer_rpc {
48 struct pci_dev *rpd; /* Root Port device */
49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
50};
51
52/* AER stats for the device */
53struct aer_stats {
54
55 /*
56 * Fields for all AER capable devices. They indicate the errors
57 * "as seen by this device". Note that this may mean that if an
58 * end point is causing problems, the AER counters may increment
59 * at its link partner (e.g. root port) because the errors will be
60 * "seen" by the link partner and not the the problematic end point
61 * itself (which may report all counters as 0 as it never saw any
62 * problems).
63 */
64 /* Counters for different type of correctable errors */
65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
66 /* Counters for different type of fatal uncorrectable errors */
67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
68 /* Counters for different type of nonfatal uncorrectable errors */
69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
70 /* Total number of ERR_COR sent by this device */
71 u64 dev_total_cor_errs;
72 /* Total number of ERR_FATAL sent by this device */
73 u64 dev_total_fatal_errs;
74 /* Total number of ERR_NONFATAL sent by this device */
75 u64 dev_total_nonfatal_errs;
76
77 /*
78 * Fields for Root ports & root complex event collectors only, these
79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
80 * messages received by the root port / event collector, INCLUDING the
81 * ones that are generated internally (by the rootport itself)
82 */
83 u64 rootport_total_cor_errs;
84 u64 rootport_total_fatal_errs;
85 u64 rootport_total_nonfatal_errs;
86};
87
88#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
89 PCI_ERR_UNC_ECRC| \
90 PCI_ERR_UNC_UNSUP| \
91 PCI_ERR_UNC_COMP_ABORT| \
92 PCI_ERR_UNC_UNX_COMP| \
93 PCI_ERR_UNC_MALF_TLP)
94
95#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
96 PCI_EXP_RTCTL_SENFEE| \
97 PCI_EXP_RTCTL_SEFEE)
98#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
100 PCI_ERR_ROOT_CMD_FATAL_EN)
101#define ERR_COR_ID(d) (d & 0xffff)
102#define ERR_UNCOR_ID(d) (d >> 16)
103
104static int pcie_aer_disable;
105static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
106
107void pci_no_aer(void)
108{
109 pcie_aer_disable = 1;
110}
111
112bool pci_aer_available(void)
113{
114 return !pcie_aer_disable && pci_msi_enabled();
115}
116
117#ifdef CONFIG_PCIE_ECRC
118
119#define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
120#define ECRC_POLICY_OFF 1 /* ECRC off for performance */
121#define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
122
123static int ecrc_policy = ECRC_POLICY_DEFAULT;
124
125static const char * const ecrc_policy_str[] = {
126 [ECRC_POLICY_DEFAULT] = "bios",
127 [ECRC_POLICY_OFF] = "off",
128 [ECRC_POLICY_ON] = "on"
129};
130
131/**
132 * enable_ercr_checking - enable PCIe ECRC checking for a device
133 * @dev: the PCI device
134 *
135 * Returns 0 on success, or negative on failure.
136 */
137static int enable_ecrc_checking(struct pci_dev *dev)
138{
139 int aer = dev->aer_cap;
140 u32 reg32;
141
142 if (!aer)
143 return -ENODEV;
144
145 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
146 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
147 reg32 |= PCI_ERR_CAP_ECRC_GENE;
148 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
149 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
150 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
151
152 return 0;
153}
154
155/**
156 * disable_ercr_checking - disables PCIe ECRC checking for a device
157 * @dev: the PCI device
158 *
159 * Returns 0 on success, or negative on failure.
160 */
161static int disable_ecrc_checking(struct pci_dev *dev)
162{
163 int aer = dev->aer_cap;
164 u32 reg32;
165
166 if (!aer)
167 return -ENODEV;
168
169 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
170 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
171 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
172
173 return 0;
174}
175
176/**
177 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
178 * @dev: the PCI device
179 */
180void pcie_set_ecrc_checking(struct pci_dev *dev)
181{
182 switch (ecrc_policy) {
183 case ECRC_POLICY_DEFAULT:
184 return;
185 case ECRC_POLICY_OFF:
186 disable_ecrc_checking(dev);
187 break;
188 case ECRC_POLICY_ON:
189 enable_ecrc_checking(dev);
190 break;
191 default:
192 return;
193 }
194}
195
196/**
197 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
198 * @str: ECRC policy from kernel command line to use
199 */
200void pcie_ecrc_get_policy(char *str)
201{
202 int i;
203
204 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
205 if (i < 0)
206 return;
207
208 ecrc_policy = i;
209}
210#endif /* CONFIG_PCIE_ECRC */
211
212#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
213 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
214
215int pcie_aer_is_native(struct pci_dev *dev)
216{
217 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
218
219 if (!dev->aer_cap)
220 return 0;
221
222 return pcie_ports_native || host->native_aer;
223}
224
225int pci_enable_pcie_error_reporting(struct pci_dev *dev)
226{
227 int rc;
228
229 if (!pcie_aer_is_native(dev))
230 return -EIO;
231
232 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
233 return pcibios_err_to_errno(rc);
234}
235EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
236
237int pci_disable_pcie_error_reporting(struct pci_dev *dev)
238{
239 int rc;
240
241 if (!pcie_aer_is_native(dev))
242 return -EIO;
243
244 rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
245 return pcibios_err_to_errno(rc);
246}
247EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
248
249int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
250{
251 int aer = dev->aer_cap;
252 u32 status, sev;
253
254 if (!pcie_aer_is_native(dev))
255 return -EIO;
256
257 /* Clear status bits for ERR_NONFATAL errors only */
258 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
259 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
260 status &= ~sev;
261 if (status)
262 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
263
264 return 0;
265}
266EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
267
268void pci_aer_clear_fatal_status(struct pci_dev *dev)
269{
270 int aer = dev->aer_cap;
271 u32 status, sev;
272
273 if (!pcie_aer_is_native(dev))
274 return;
275
276 /* Clear status bits for ERR_FATAL errors only */
277 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
278 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
279 status &= sev;
280 if (status)
281 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
282}
283
284/**
285 * pci_aer_raw_clear_status - Clear AER error registers.
286 * @dev: the PCI device
287 *
288 * Clearing AER error status registers unconditionally, regardless of
289 * whether they're owned by firmware or the OS.
290 *
291 * Returns 0 on success, or negative on failure.
292 */
293int pci_aer_raw_clear_status(struct pci_dev *dev)
294{
295 int aer = dev->aer_cap;
296 u32 status;
297 int port_type;
298
299 if (!aer)
300 return -EIO;
301
302 port_type = pci_pcie_type(dev);
303 if (port_type == PCI_EXP_TYPE_ROOT_PORT) {
304 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
305 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
306 }
307
308 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
309 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
310
311 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
312 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
313
314 return 0;
315}
316
317int pci_aer_clear_status(struct pci_dev *dev)
318{
319 if (!pcie_aer_is_native(dev))
320 return -EIO;
321
322 return pci_aer_raw_clear_status(dev);
323}
324
325void pci_save_aer_state(struct pci_dev *dev)
326{
327 int aer = dev->aer_cap;
328 struct pci_cap_saved_state *save_state;
329 u32 *cap;
330
331 if (!aer)
332 return;
333
334 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
335 if (!save_state)
336 return;
337
338 cap = &save_state->cap.data[0];
339 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
340 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
341 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
342 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
343 if (pcie_cap_has_rtctl(dev))
344 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
345}
346
347void pci_restore_aer_state(struct pci_dev *dev)
348{
349 int aer = dev->aer_cap;
350 struct pci_cap_saved_state *save_state;
351 u32 *cap;
352
353 if (!aer)
354 return;
355
356 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
357 if (!save_state)
358 return;
359
360 cap = &save_state->cap.data[0];
361 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
362 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
363 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
364 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
365 if (pcie_cap_has_rtctl(dev))
366 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
367}
368
369void pci_aer_init(struct pci_dev *dev)
370{
371 int n;
372
373 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
374 if (!dev->aer_cap)
375 return;
376
377 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
378
379 /*
380 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
381 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
382 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
383 * 7.8.4).
384 */
385 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
386 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
387
388 pci_aer_clear_status(dev);
389}
390
391void pci_aer_exit(struct pci_dev *dev)
392{
393 kfree(dev->aer_stats);
394 dev->aer_stats = NULL;
395}
396
397#define AER_AGENT_RECEIVER 0
398#define AER_AGENT_REQUESTER 1
399#define AER_AGENT_COMPLETER 2
400#define AER_AGENT_TRANSMITTER 3
401
402#define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
403 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
404#define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
405 0 : PCI_ERR_UNC_COMP_ABORT)
406#define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
407 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
408
409#define AER_GET_AGENT(t, e) \
410 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
411 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
412 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
413 AER_AGENT_RECEIVER)
414
415#define AER_PHYSICAL_LAYER_ERROR 0
416#define AER_DATA_LINK_LAYER_ERROR 1
417#define AER_TRANSACTION_LAYER_ERROR 2
418
419#define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
420 PCI_ERR_COR_RCVR : 0)
421#define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
422 (PCI_ERR_COR_BAD_TLP| \
423 PCI_ERR_COR_BAD_DLLP| \
424 PCI_ERR_COR_REP_ROLL| \
425 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
426
427#define AER_GET_LAYER_ERROR(t, e) \
428 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
429 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
430 AER_TRANSACTION_LAYER_ERROR)
431
432/*
433 * AER error strings
434 */
435static const char *aer_error_severity_string[] = {
436 "Uncorrected (Non-Fatal)",
437 "Uncorrected (Fatal)",
438 "Corrected"
439};
440
441static const char *aer_error_layer[] = {
442 "Physical Layer",
443 "Data Link Layer",
444 "Transaction Layer"
445};
446
447static const char *aer_correctable_error_string[] = {
448 "RxErr", /* Bit Position 0 */
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453 NULL,
454 "BadTLP", /* Bit Position 6 */
455 "BadDLLP", /* Bit Position 7 */
456 "Rollover", /* Bit Position 8 */
457 NULL,
458 NULL,
459 NULL,
460 "Timeout", /* Bit Position 12 */
461 "NonFatalErr", /* Bit Position 13 */
462 "CorrIntErr", /* Bit Position 14 */
463 "HeaderOF", /* Bit Position 15 */
464 NULL, /* Bit Position 16 */
465 NULL, /* Bit Position 17 */
466 NULL, /* Bit Position 18 */
467 NULL, /* Bit Position 19 */
468 NULL, /* Bit Position 20 */
469 NULL, /* Bit Position 21 */
470 NULL, /* Bit Position 22 */
471 NULL, /* Bit Position 23 */
472 NULL, /* Bit Position 24 */
473 NULL, /* Bit Position 25 */
474 NULL, /* Bit Position 26 */
475 NULL, /* Bit Position 27 */
476 NULL, /* Bit Position 28 */
477 NULL, /* Bit Position 29 */
478 NULL, /* Bit Position 30 */
479 NULL, /* Bit Position 31 */
480};
481
482static const char *aer_uncorrectable_error_string[] = {
483 "Undefined", /* Bit Position 0 */
484 NULL,
485 NULL,
486 NULL,
487 "DLP", /* Bit Position 4 */
488 "SDES", /* Bit Position 5 */
489 NULL,
490 NULL,
491 NULL,
492 NULL,
493 NULL,
494 NULL,
495 "TLP", /* Bit Position 12 */
496 "FCP", /* Bit Position 13 */
497 "CmpltTO", /* Bit Position 14 */
498 "CmpltAbrt", /* Bit Position 15 */
499 "UnxCmplt", /* Bit Position 16 */
500 "RxOF", /* Bit Position 17 */
501 "MalfTLP", /* Bit Position 18 */
502 "ECRC", /* Bit Position 19 */
503 "UnsupReq", /* Bit Position 20 */
504 "ACSViol", /* Bit Position 21 */
505 "UncorrIntErr", /* Bit Position 22 */
506 "BlockedTLP", /* Bit Position 23 */
507 "AtomicOpBlocked", /* Bit Position 24 */
508 "TLPBlockedErr", /* Bit Position 25 */
509 "PoisonTLPBlocked", /* Bit Position 26 */
510 NULL, /* Bit Position 27 */
511 NULL, /* Bit Position 28 */
512 NULL, /* Bit Position 29 */
513 NULL, /* Bit Position 30 */
514 NULL, /* Bit Position 31 */
515};
516
517static const char *aer_agent_string[] = {
518 "Receiver ID",
519 "Requester ID",
520 "Completer ID",
521 "Transmitter ID"
522};
523
524#define aer_stats_dev_attr(name, stats_array, strings_array, \
525 total_string, total_field) \
526 static ssize_t \
527 name##_show(struct device *dev, struct device_attribute *attr, \
528 char *buf) \
529{ \
530 unsigned int i; \
531 char *str = buf; \
532 struct pci_dev *pdev = to_pci_dev(dev); \
533 u64 *stats = pdev->aer_stats->stats_array; \
534 \
535 for (i = 0; i < ARRAY_SIZE(strings_array); i++) { \
536 if (strings_array[i]) \
537 str += sprintf(str, "%s %llu\n", \
538 strings_array[i], stats[i]); \
539 else if (stats[i]) \
540 str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
541 i, stats[i]); \
542 } \
543 str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
544 pdev->aer_stats->total_field); \
545 return str-buf; \
546} \
547static DEVICE_ATTR_RO(name)
548
549aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
550 aer_correctable_error_string, "ERR_COR",
551 dev_total_cor_errs);
552aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
553 aer_uncorrectable_error_string, "ERR_FATAL",
554 dev_total_fatal_errs);
555aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
556 aer_uncorrectable_error_string, "ERR_NONFATAL",
557 dev_total_nonfatal_errs);
558
559#define aer_stats_rootport_attr(name, field) \
560 static ssize_t \
561 name##_show(struct device *dev, struct device_attribute *attr, \
562 char *buf) \
563{ \
564 struct pci_dev *pdev = to_pci_dev(dev); \
565 return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
566} \
567static DEVICE_ATTR_RO(name)
568
569aer_stats_rootport_attr(aer_rootport_total_err_cor,
570 rootport_total_cor_errs);
571aer_stats_rootport_attr(aer_rootport_total_err_fatal,
572 rootport_total_fatal_errs);
573aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
574 rootport_total_nonfatal_errs);
575
576static struct attribute *aer_stats_attrs[] __ro_after_init = {
577 &dev_attr_aer_dev_correctable.attr,
578 &dev_attr_aer_dev_fatal.attr,
579 &dev_attr_aer_dev_nonfatal.attr,
580 &dev_attr_aer_rootport_total_err_cor.attr,
581 &dev_attr_aer_rootport_total_err_fatal.attr,
582 &dev_attr_aer_rootport_total_err_nonfatal.attr,
583 NULL
584};
585
586static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
587 struct attribute *a, int n)
588{
589 struct device *dev = kobj_to_dev(kobj);
590 struct pci_dev *pdev = to_pci_dev(dev);
591
592 if (!pdev->aer_stats)
593 return 0;
594
595 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
596 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
597 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
598 pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT)
599 return 0;
600
601 return a->mode;
602}
603
604const struct attribute_group aer_stats_attr_group = {
605 .attrs = aer_stats_attrs,
606 .is_visible = aer_stats_attrs_are_visible,
607};
608
609static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
610 struct aer_err_info *info)
611{
612 unsigned long status = info->status & ~info->mask;
613 int i, max = -1;
614 u64 *counter = NULL;
615 struct aer_stats *aer_stats = pdev->aer_stats;
616
617 if (!aer_stats)
618 return;
619
620 switch (info->severity) {
621 case AER_CORRECTABLE:
622 aer_stats->dev_total_cor_errs++;
623 counter = &aer_stats->dev_cor_errs[0];
624 max = AER_MAX_TYPEOF_COR_ERRS;
625 break;
626 case AER_NONFATAL:
627 aer_stats->dev_total_nonfatal_errs++;
628 counter = &aer_stats->dev_nonfatal_errs[0];
629 max = AER_MAX_TYPEOF_UNCOR_ERRS;
630 break;
631 case AER_FATAL:
632 aer_stats->dev_total_fatal_errs++;
633 counter = &aer_stats->dev_fatal_errs[0];
634 max = AER_MAX_TYPEOF_UNCOR_ERRS;
635 break;
636 }
637
638 for_each_set_bit(i, &status, max)
639 counter[i]++;
640}
641
642static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
643 struct aer_err_source *e_src)
644{
645 struct aer_stats *aer_stats = pdev->aer_stats;
646
647 if (!aer_stats)
648 return;
649
650 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
651 aer_stats->rootport_total_cor_errs++;
652
653 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
654 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
655 aer_stats->rootport_total_fatal_errs++;
656 else
657 aer_stats->rootport_total_nonfatal_errs++;
658 }
659}
660
661static void __print_tlp_header(struct pci_dev *dev,
662 struct aer_header_log_regs *t)
663{
664 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
665 t->dw0, t->dw1, t->dw2, t->dw3);
666}
667
668static void __aer_print_error(struct pci_dev *dev,
669 struct aer_err_info *info)
670{
671 const char **strings;
672 unsigned long status = info->status & ~info->mask;
673 const char *level, *errmsg;
674 int i;
675
676 if (info->severity == AER_CORRECTABLE) {
677 strings = aer_correctable_error_string;
678 level = KERN_WARNING;
679 } else {
680 strings = aer_uncorrectable_error_string;
681 level = KERN_ERR;
682 }
683
684 for_each_set_bit(i, &status, 32) {
685 errmsg = strings[i];
686 if (!errmsg)
687 errmsg = "Unknown Error Bit";
688
689 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
690 info->first_error == i ? " (First)" : "");
691 }
692 pci_dev_aer_stats_incr(dev, info);
693}
694
695void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
696{
697 int layer, agent;
698 int id = ((dev->bus->number << 8) | dev->devfn);
699 const char *level;
700
701 if (!info->status) {
702 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
703 aer_error_severity_string[info->severity]);
704 goto out;
705 }
706
707 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
708 agent = AER_GET_AGENT(info->severity, info->status);
709
710 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
711
712 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
713 aer_error_severity_string[info->severity],
714 aer_error_layer[layer], aer_agent_string[agent]);
715
716 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
717 dev->vendor, dev->device, info->status, info->mask);
718
719 __aer_print_error(dev, info);
720
721 if (info->tlp_header_valid)
722 __print_tlp_header(dev, &info->tlp);
723
724out:
725 if (info->id && info->error_dev_num > 1 && info->id == id)
726 pci_err(dev, " Error of this Agent is reported first\n");
727
728 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
729 info->severity, info->tlp_header_valid, &info->tlp);
730}
731
732static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
733{
734 u8 bus = info->id >> 8;
735 u8 devfn = info->id & 0xff;
736
737 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
738 info->multi_error_valid ? "Multiple " : "",
739 aer_error_severity_string[info->severity],
740 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
741 PCI_FUNC(devfn));
742}
743
744#ifdef CONFIG_ACPI_APEI_PCIEAER
745int cper_severity_to_aer(int cper_severity)
746{
747 switch (cper_severity) {
748 case CPER_SEV_RECOVERABLE:
749 return AER_NONFATAL;
750 case CPER_SEV_FATAL:
751 return AER_FATAL;
752 default:
753 return AER_CORRECTABLE;
754 }
755}
756EXPORT_SYMBOL_GPL(cper_severity_to_aer);
757
758void cper_print_aer(struct pci_dev *dev, int aer_severity,
759 struct aer_capability_regs *aer)
760{
761 int layer, agent, tlp_header_valid = 0;
762 u32 status, mask;
763 struct aer_err_info info;
764
765 if (aer_severity == AER_CORRECTABLE) {
766 status = aer->cor_status;
767 mask = aer->cor_mask;
768 } else {
769 status = aer->uncor_status;
770 mask = aer->uncor_mask;
771 tlp_header_valid = status & AER_LOG_TLP_MASKS;
772 }
773
774 layer = AER_GET_LAYER_ERROR(aer_severity, status);
775 agent = AER_GET_AGENT(aer_severity, status);
776
777 memset(&info, 0, sizeof(info));
778 info.severity = aer_severity;
779 info.status = status;
780 info.mask = mask;
781 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
782
783 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
784 __aer_print_error(dev, &info);
785 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
786 aer_error_layer[layer], aer_agent_string[agent]);
787
788 if (aer_severity != AER_CORRECTABLE)
789 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
790 aer->uncor_severity);
791
792 if (tlp_header_valid)
793 __print_tlp_header(dev, &aer->header_log);
794
795 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
796 aer_severity, tlp_header_valid, &aer->header_log);
797}
798#endif
799
800/**
801 * add_error_device - list device to be handled
802 * @e_info: pointer to error info
803 * @dev: pointer to pci_dev to be added
804 */
805static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
806{
807 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
808 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
809 e_info->error_dev_num++;
810 return 0;
811 }
812 return -ENOSPC;
813}
814
815/**
816 * is_error_source - check whether the device is source of reported error
817 * @dev: pointer to pci_dev to be checked
818 * @e_info: pointer to reported error info
819 */
820static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
821{
822 int aer = dev->aer_cap;
823 u32 status, mask;
824 u16 reg16;
825
826 /*
827 * When bus id is equal to 0, it might be a bad id
828 * reported by root port.
829 */
830 if ((PCI_BUS_NUM(e_info->id) != 0) &&
831 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
832 /* Device ID match? */
833 if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
834 return true;
835
836 /* Continue id comparing if there is no multiple error */
837 if (!e_info->multi_error_valid)
838 return false;
839 }
840
841 /*
842 * When either
843 * 1) bus id is equal to 0. Some ports might lose the bus
844 * id of error source id;
845 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
846 * 3) There are multiple errors and prior ID comparing fails;
847 * We check AER status registers to find possible reporter.
848 */
849 if (atomic_read(&dev->enable_cnt) == 0)
850 return false;
851
852 /* Check if AER is enabled */
853 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
854 if (!(reg16 & PCI_EXP_AER_FLAGS))
855 return false;
856
857 if (!aer)
858 return false;
859
860 /* Check if error is recorded */
861 if (e_info->severity == AER_CORRECTABLE) {
862 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
863 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
864 } else {
865 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
866 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
867 }
868 if (status & ~mask)
869 return true;
870
871 return false;
872}
873
874static int find_device_iter(struct pci_dev *dev, void *data)
875{
876 struct aer_err_info *e_info = (struct aer_err_info *)data;
877
878 if (is_error_source(dev, e_info)) {
879 /* List this device */
880 if (add_error_device(e_info, dev)) {
881 /* We cannot handle more... Stop iteration */
882 /* TODO: Should print error message here? */
883 return 1;
884 }
885
886 /* If there is only a single error, stop iteration */
887 if (!e_info->multi_error_valid)
888 return 1;
889 }
890 return 0;
891}
892
893/**
894 * find_source_device - search through device hierarchy for source device
895 * @parent: pointer to Root Port pci_dev data structure
896 * @e_info: including detailed error information such like id
897 *
898 * Return true if found.
899 *
900 * Invoked by DPC when error is detected at the Root Port.
901 * Caller of this function must set id, severity, and multi_error_valid of
902 * struct aer_err_info pointed by @e_info properly. This function must fill
903 * e_info->error_dev_num and e_info->dev[], based on the given information.
904 */
905static bool find_source_device(struct pci_dev *parent,
906 struct aer_err_info *e_info)
907{
908 struct pci_dev *dev = parent;
909 int result;
910
911 /* Must reset in this function */
912 e_info->error_dev_num = 0;
913
914 /* Is Root Port an agent that sends error message? */
915 result = find_device_iter(dev, e_info);
916 if (result)
917 return true;
918
919 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
920
921 if (!e_info->error_dev_num) {
922 pci_info(parent, "can't find device of ID%04x\n", e_info->id);
923 return false;
924 }
925 return true;
926}
927
928/**
929 * handle_error_source - handle logging error into an event log
930 * @dev: pointer to pci_dev data structure of error source device
931 * @info: comprehensive error information
932 *
933 * Invoked when an error being detected by Root Port.
934 */
935static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
936{
937 int aer = dev->aer_cap;
938
939 if (info->severity == AER_CORRECTABLE) {
940 /*
941 * Correctable error does not need software intervention.
942 * No need to go through error recovery process.
943 */
944 if (aer)
945 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
946 info->status);
947 if (pcie_aer_is_native(dev))
948 pcie_clear_device_status(dev);
949 } else if (info->severity == AER_NONFATAL)
950 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
951 else if (info->severity == AER_FATAL)
952 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
953 pci_dev_put(dev);
954}
955
956#ifdef CONFIG_ACPI_APEI_PCIEAER
957
958#define AER_RECOVER_RING_ORDER 4
959#define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
960
961struct aer_recover_entry {
962 u8 bus;
963 u8 devfn;
964 u16 domain;
965 int severity;
966 struct aer_capability_regs *regs;
967};
968
969static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
970 AER_RECOVER_RING_SIZE);
971
972static void aer_recover_work_func(struct work_struct *work)
973{
974 struct aer_recover_entry entry;
975 struct pci_dev *pdev;
976
977 while (kfifo_get(&aer_recover_ring, &entry)) {
978 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
979 entry.devfn);
980 if (!pdev) {
981 pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
982 entry.domain, entry.bus,
983 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
984 continue;
985 }
986 cper_print_aer(pdev, entry.severity, entry.regs);
987 if (entry.severity == AER_NONFATAL)
988 pcie_do_recovery(pdev, pci_channel_io_normal,
989 aer_root_reset);
990 else if (entry.severity == AER_FATAL)
991 pcie_do_recovery(pdev, pci_channel_io_frozen,
992 aer_root_reset);
993 pci_dev_put(pdev);
994 }
995}
996
997/*
998 * Mutual exclusion for writers of aer_recover_ring, reader side don't
999 * need lock, because there is only one reader and lock is not needed
1000 * between reader and writer.
1001 */
1002static DEFINE_SPINLOCK(aer_recover_ring_lock);
1003static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1004
1005void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1006 int severity, struct aer_capability_regs *aer_regs)
1007{
1008 struct aer_recover_entry entry = {
1009 .bus = bus,
1010 .devfn = devfn,
1011 .domain = domain,
1012 .severity = severity,
1013 .regs = aer_regs,
1014 };
1015
1016 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
1017 &aer_recover_ring_lock))
1018 schedule_work(&aer_recover_work);
1019 else
1020 pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
1021 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1022}
1023EXPORT_SYMBOL_GPL(aer_recover_queue);
1024#endif
1025
1026/**
1027 * aer_get_device_error_info - read error status from dev and store it to info
1028 * @dev: pointer to the device expected to have a error record
1029 * @info: pointer to structure to store the error record
1030 *
1031 * Return 1 on success, 0 on error.
1032 *
1033 * Note that @info is reused among all error devices. Clear fields properly.
1034 */
1035int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
1036{
1037 int aer = dev->aer_cap;
1038 int temp;
1039
1040 /* Must reset in this function */
1041 info->status = 0;
1042 info->tlp_header_valid = 0;
1043
1044 /* The device might not support AER */
1045 if (!aer)
1046 return 0;
1047
1048 if (info->severity == AER_CORRECTABLE) {
1049 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1050 &info->status);
1051 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1052 &info->mask);
1053 if (!(info->status & ~info->mask))
1054 return 0;
1055 } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
1056 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
1057 info->severity == AER_NONFATAL) {
1058
1059 /* Link is still healthy for IO reads */
1060 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1061 &info->status);
1062 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1063 &info->mask);
1064 if (!(info->status & ~info->mask))
1065 return 0;
1066
1067 /* Get First Error Pointer */
1068 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1069 info->first_error = PCI_ERR_CAP_FEP(temp);
1070
1071 if (info->status & AER_LOG_TLP_MASKS) {
1072 info->tlp_header_valid = 1;
1073 pci_read_config_dword(dev,
1074 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1075 pci_read_config_dword(dev,
1076 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1077 pci_read_config_dword(dev,
1078 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1079 pci_read_config_dword(dev,
1080 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1081 }
1082 }
1083
1084 return 1;
1085}
1086
1087static inline void aer_process_err_devices(struct aer_err_info *e_info)
1088{
1089 int i;
1090
1091 /* Report all before handle them, not to lost records by reset etc. */
1092 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1093 if (aer_get_device_error_info(e_info->dev[i], e_info))
1094 aer_print_error(e_info->dev[i], e_info);
1095 }
1096 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1097 if (aer_get_device_error_info(e_info->dev[i], e_info))
1098 handle_error_source(e_info->dev[i], e_info);
1099 }
1100}
1101
1102/**
1103 * aer_isr_one_error - consume an error detected by root port
1104 * @rpc: pointer to the root port which holds an error
1105 * @e_src: pointer to an error source
1106 */
1107static void aer_isr_one_error(struct aer_rpc *rpc,
1108 struct aer_err_source *e_src)
1109{
1110 struct pci_dev *pdev = rpc->rpd;
1111 struct aer_err_info e_info;
1112
1113 pci_rootport_aer_stats_incr(pdev, e_src);
1114
1115 /*
1116 * There is a possibility that both correctable error and
1117 * uncorrectable error being logged. Report correctable error first.
1118 */
1119 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1120 e_info.id = ERR_COR_ID(e_src->id);
1121 e_info.severity = AER_CORRECTABLE;
1122
1123 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1124 e_info.multi_error_valid = 1;
1125 else
1126 e_info.multi_error_valid = 0;
1127 aer_print_port_info(pdev, &e_info);
1128
1129 if (find_source_device(pdev, &e_info))
1130 aer_process_err_devices(&e_info);
1131 }
1132
1133 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1134 e_info.id = ERR_UNCOR_ID(e_src->id);
1135
1136 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1137 e_info.severity = AER_FATAL;
1138 else
1139 e_info.severity = AER_NONFATAL;
1140
1141 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1142 e_info.multi_error_valid = 1;
1143 else
1144 e_info.multi_error_valid = 0;
1145
1146 aer_print_port_info(pdev, &e_info);
1147
1148 if (find_source_device(pdev, &e_info))
1149 aer_process_err_devices(&e_info);
1150 }
1151}
1152
1153/**
1154 * aer_isr - consume errors detected by root port
1155 * @irq: IRQ assigned to Root Port
1156 * @context: pointer to Root Port data structure
1157 *
1158 * Invoked, as DPC, when root port records new detected error
1159 */
1160static irqreturn_t aer_isr(int irq, void *context)
1161{
1162 struct pcie_device *dev = (struct pcie_device *)context;
1163 struct aer_rpc *rpc = get_service_data(dev);
1164 struct aer_err_source e_src;
1165
1166 if (kfifo_is_empty(&rpc->aer_fifo))
1167 return IRQ_NONE;
1168
1169 while (kfifo_get(&rpc->aer_fifo, &e_src))
1170 aer_isr_one_error(rpc, &e_src);
1171 return IRQ_HANDLED;
1172}
1173
1174/**
1175 * aer_irq - Root Port's ISR
1176 * @irq: IRQ assigned to Root Port
1177 * @context: pointer to Root Port data structure
1178 *
1179 * Invoked when Root Port detects AER messages.
1180 */
1181static irqreturn_t aer_irq(int irq, void *context)
1182{
1183 struct pcie_device *pdev = (struct pcie_device *)context;
1184 struct aer_rpc *rpc = get_service_data(pdev);
1185 struct pci_dev *rp = rpc->rpd;
1186 int aer = rp->aer_cap;
1187 struct aer_err_source e_src = {};
1188
1189 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1190 if (!(e_src.status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV)))
1191 return IRQ_NONE;
1192
1193 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1194 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1195
1196 if (!kfifo_put(&rpc->aer_fifo, e_src))
1197 return IRQ_HANDLED;
1198
1199 return IRQ_WAKE_THREAD;
1200}
1201
1202static int set_device_error_reporting(struct pci_dev *dev, void *data)
1203{
1204 bool enable = *((bool *)data);
1205 int type = pci_pcie_type(dev);
1206
1207 if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
1208 (type == PCI_EXP_TYPE_UPSTREAM) ||
1209 (type == PCI_EXP_TYPE_DOWNSTREAM)) {
1210 if (enable)
1211 pci_enable_pcie_error_reporting(dev);
1212 else
1213 pci_disable_pcie_error_reporting(dev);
1214 }
1215
1216 if (enable)
1217 pcie_set_ecrc_checking(dev);
1218
1219 return 0;
1220}
1221
1222/**
1223 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1224 * @dev: pointer to root port's pci_dev data structure
1225 * @enable: true = enable error reporting, false = disable error reporting.
1226 */
1227static void set_downstream_devices_error_reporting(struct pci_dev *dev,
1228 bool enable)
1229{
1230 set_device_error_reporting(dev, &enable);
1231
1232 if (!dev->subordinate)
1233 return;
1234 pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
1235}
1236
1237/**
1238 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1239 * @rpc: pointer to a Root Port data structure
1240 *
1241 * Invoked when PCIe bus loads AER service driver.
1242 */
1243static void aer_enable_rootport(struct aer_rpc *rpc)
1244{
1245 struct pci_dev *pdev = rpc->rpd;
1246 int aer = pdev->aer_cap;
1247 u16 reg16;
1248 u32 reg32;
1249
1250 /* Clear PCIe Capability's Device Status */
1251 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1252 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1253
1254 /* Disable system error generation in response to error messages */
1255 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1256 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1257
1258 /* Clear error status */
1259 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1260 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1261 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1262 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1263 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1264 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1265
1266 /*
1267 * Enable error reporting for the root port device and downstream port
1268 * devices.
1269 */
1270 set_downstream_devices_error_reporting(pdev, true);
1271
1272 /* Enable Root Port's interrupt in response to error messages */
1273 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1274 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1275 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1276}
1277
1278/**
1279 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1280 * @rpc: pointer to a Root Port data structure
1281 *
1282 * Invoked when PCIe bus unloads AER service driver.
1283 */
1284static void aer_disable_rootport(struct aer_rpc *rpc)
1285{
1286 struct pci_dev *pdev = rpc->rpd;
1287 int aer = pdev->aer_cap;
1288 u32 reg32;
1289
1290 /*
1291 * Disable error reporting for the root port device and downstream port
1292 * devices.
1293 */
1294 set_downstream_devices_error_reporting(pdev, false);
1295
1296 /* Disable Root's interrupt in response to error messages */
1297 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1298 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1299 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1300
1301 /* Clear Root's error status reg */
1302 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1303 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1304}
1305
1306/**
1307 * aer_remove - clean up resources
1308 * @dev: pointer to the pcie_dev data structure
1309 *
1310 * Invoked when PCI Express bus unloads or AER probe fails.
1311 */
1312static void aer_remove(struct pcie_device *dev)
1313{
1314 struct aer_rpc *rpc = get_service_data(dev);
1315
1316 aer_disable_rootport(rpc);
1317}
1318
1319/**
1320 * aer_probe - initialize resources
1321 * @dev: pointer to the pcie_dev data structure
1322 *
1323 * Invoked when PCI Express bus loads AER service driver.
1324 */
1325static int aer_probe(struct pcie_device *dev)
1326{
1327 int status;
1328 struct aer_rpc *rpc;
1329 struct device *device = &dev->device;
1330 struct pci_dev *port = dev->port;
1331
1332 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1333 if (!rpc)
1334 return -ENOMEM;
1335
1336 rpc->rpd = port;
1337 INIT_KFIFO(rpc->aer_fifo);
1338 set_service_data(dev, rpc);
1339
1340 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1341 IRQF_SHARED, "aerdrv", dev);
1342 if (status) {
1343 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1344 return status;
1345 }
1346
1347 aer_enable_rootport(rpc);
1348 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1349 return 0;
1350}
1351
1352/**
1353 * aer_root_reset - reset link on Root Port
1354 * @dev: pointer to Root Port's pci_dev data structure
1355 *
1356 * Invoked by Port Bus driver when performing link reset at Root Port.
1357 */
1358static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1359{
1360 int aer = dev->aer_cap;
1361 u32 reg32;
1362 int rc;
1363
1364
1365 /* Disable Root's interrupt in response to error messages */
1366 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1367 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1368 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1369
1370 rc = pci_bus_error_reset(dev);
1371 pci_info(dev, "Root Port link has been reset\n");
1372
1373 /* Clear Root Error Status */
1374 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, ®32);
1375 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, reg32);
1376
1377 /* Enable Root Port's interrupt in response to error messages */
1378 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1379 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1380 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1381
1382 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1383}
1384
1385static struct pcie_port_service_driver aerdriver = {
1386 .name = "aer",
1387 .port_type = PCI_EXP_TYPE_ROOT_PORT,
1388 .service = PCIE_PORT_SERVICE_AER,
1389
1390 .probe = aer_probe,
1391 .remove = aer_remove,
1392};
1393
1394/**
1395 * aer_service_init - register AER root service driver
1396 *
1397 * Invoked when AER root service driver is loaded.
1398 */
1399int __init pcie_aer_init(void)
1400{
1401 if (!pci_aer_available())
1402 return -ENXIO;
1403 return pcie_port_service_register(&aerdriver);
1404}