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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * New driver for Marvell Yukon 2 chipset.
4 * Based on earlier sk98lin, and skge driver.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/crc32.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/netdevice.h>
19#include <linux/dma-mapping.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/ip.h>
25#include <linux/slab.h>
26#include <net/ip.h>
27#include <linux/tcp.h>
28#include <linux/in.h>
29#include <linux/delay.h>
30#include <linux/workqueue.h>
31#include <linux/if_vlan.h>
32#include <linux/prefetch.h>
33#include <linux/debugfs.h>
34#include <linux/mii.h>
35#include <linux/of_net.h>
36#include <linux/dmi.h>
37
38#include <asm/irq.h>
39
40#include "sky2.h"
41
42#define DRV_NAME "sky2"
43#define DRV_VERSION "1.30"
44
45/*
46 * The Yukon II chipset takes 64 bit command blocks (called list elements)
47 * that are organized into three (receive, transmit, status) different rings
48 * similar to Tigon3.
49 */
50
51#define RX_LE_SIZE 1024
52#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
53#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
54#define RX_DEF_PENDING RX_MAX_PENDING
55
56/* This is the worst case number of transmit list elements for a single skb:
57 * VLAN:GSO + CKSUM + Data + skb_frags * DMA
58 */
59#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
60#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
61#define TX_MAX_PENDING 1024
62#define TX_DEF_PENDING 63
63
64#define TX_WATCHDOG (5 * HZ)
65#define PHY_RETRIES 1000
66
67#define SKY2_EEPROM_MAGIC 0x9955aabb
68
69#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
70
71static const u32 default_msg =
72 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
73 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
74 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
75
76static int debug = -1; /* defaults above */
77module_param(debug, int, 0);
78MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
79
80static int copybreak __read_mostly = 128;
81module_param(copybreak, int, 0);
82MODULE_PARM_DESC(copybreak, "Receive copy threshold");
83
84static int disable_msi = -1;
85module_param(disable_msi, int, 0);
86MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
87
88static int legacy_pme = 0;
89module_param(legacy_pme, int, 0);
90MODULE_PARM_DESC(legacy_pme, "Legacy power management");
91
92static const struct pci_device_id sky2_id_table[] = {
93 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
94 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
95 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
96 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
97 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
100 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
135 { 0 }
136};
137
138MODULE_DEVICE_TABLE(pci, sky2_id_table);
139
140/* Avoid conditionals by using array */
141static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
142static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
143static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
144
145static void sky2_set_multicast(struct net_device *dev);
146static irqreturn_t sky2_intr(int irq, void *dev_id);
147
148/* Access to PHY via serial interconnect */
149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
158 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
159 if (ctrl == 0xffff)
160 goto io_error;
161
162 if (!(ctrl & GM_SMI_CT_BUSY))
163 return 0;
164
165 udelay(10);
166 }
167
168 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
169 return -ETIMEDOUT;
170
171io_error:
172 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
173 return -EIO;
174}
175
176static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
177{
178 int i;
179
180 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
181 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
182
183 for (i = 0; i < PHY_RETRIES; i++) {
184 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
185 if (ctrl == 0xffff)
186 goto io_error;
187
188 if (ctrl & GM_SMI_CT_RD_VAL) {
189 *val = gma_read16(hw, port, GM_SMI_DATA);
190 return 0;
191 }
192
193 udelay(10);
194 }
195
196 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
197 return -ETIMEDOUT;
198io_error:
199 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
200 return -EIO;
201}
202
203static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
204{
205 u16 v = 0;
206 __gm_phy_read(hw, port, reg, &v);
207 return v;
208}
209
210
211static void sky2_power_on(struct sky2_hw *hw)
212{
213 /* switch power to VCC (WA for VAUX problem) */
214 sky2_write8(hw, B0_POWER_CTRL,
215 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
216
217 /* disable Core Clock Division, */
218 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
219
220 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
221 /* enable bits are inverted */
222 sky2_write8(hw, B2_Y2_CLK_GATE,
223 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
224 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
225 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
226 else
227 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
228
229 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
230 u32 reg;
231
232 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
233
234 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
235 /* set all bits to 0 except bits 15..12 and 8 */
236 reg &= P_ASPM_CONTROL_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
238
239 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
240 /* set all bits to 0 except bits 28 & 27 */
241 reg &= P_CTL_TIM_VMAIN_AV_MSK;
242 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
243
244 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
245
246 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
247
248 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
249 reg = sky2_read32(hw, B2_GP_IO);
250 reg |= GLB_GPIO_STAT_RACE_DIS;
251 sky2_write32(hw, B2_GP_IO, reg);
252
253 sky2_read32(hw, B2_GP_IO);
254 }
255
256 /* Turn on "driver loaded" LED */
257 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
258}
259
260static void sky2_power_aux(struct sky2_hw *hw)
261{
262 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
263 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
264 else
265 /* enable bits are inverted */
266 sky2_write8(hw, B2_Y2_CLK_GATE,
267 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
268 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
269 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
270
271 /* switch power to VAUX if supported and PME from D3cold */
272 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
273 pci_pme_capable(hw->pdev, PCI_D3cold))
274 sky2_write8(hw, B0_POWER_CTRL,
275 (PC_VAUX_ENA | PC_VCC_ENA |
276 PC_VAUX_ON | PC_VCC_OFF));
277
278 /* turn off "driver loaded LED" */
279 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
280}
281
282static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
283{
284 u16 reg;
285
286 /* disable all GMAC IRQ's */
287 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
288
289 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
290 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
291 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
292 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
293
294 reg = gma_read16(hw, port, GM_RX_CTRL);
295 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
296 gma_write16(hw, port, GM_RX_CTRL, reg);
297}
298
299/* flow control to advertise bits */
300static const u16 copper_fc_adv[] = {
301 [FC_NONE] = 0,
302 [FC_TX] = PHY_M_AN_ASP,
303 [FC_RX] = PHY_M_AN_PC,
304 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
305};
306
307/* flow control to advertise bits when using 1000BaseX */
308static const u16 fiber_fc_adv[] = {
309 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
310 [FC_TX] = PHY_M_P_ASYM_MD_X,
311 [FC_RX] = PHY_M_P_SYM_MD_X,
312 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
313};
314
315/* flow control to GMA disable bits */
316static const u16 gm_fc_disable[] = {
317 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
318 [FC_TX] = GM_GPCR_FC_RX_DIS,
319 [FC_RX] = GM_GPCR_FC_TX_DIS,
320 [FC_BOTH] = 0,
321};
322
323
324static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
325{
326 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
327 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
328
329 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
330 !(hw->flags & SKY2_HW_NEWER_PHY)) {
331 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
332
333 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
334 PHY_M_EC_MAC_S_MSK);
335 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
336
337 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
338 if (hw->chip_id == CHIP_ID_YUKON_EC)
339 /* set downshift counter to 3x and enable downshift */
340 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
341 else
342 /* set master & slave downshift counter to 1x */
343 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
344
345 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
346 }
347
348 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
349 if (sky2_is_copper(hw)) {
350 if (!(hw->flags & SKY2_HW_GIGABIT)) {
351 /* enable automatic crossover */
352 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
353
354 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
355 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
356 u16 spec;
357
358 /* Enable Class A driver for FE+ A0 */
359 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
360 spec |= PHY_M_FESC_SEL_CL_A;
361 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
362 }
363 } else {
364 /* disable energy detect */
365 ctrl &= ~PHY_M_PC_EN_DET_MSK;
366
367 /* enable automatic crossover */
368 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
369
370 /* downshift on PHY 88E1112 and 88E1149 is changed */
371 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
372 (hw->flags & SKY2_HW_NEWER_PHY)) {
373 /* set downshift counter to 3x and enable downshift */
374 ctrl &= ~PHY_M_PC_DSC_MSK;
375 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
376 }
377 }
378 } else {
379 /* workaround for deviation #4.88 (CRC errors) */
380 /* disable Automatic Crossover */
381
382 ctrl &= ~PHY_M_PC_MDIX_MSK;
383 }
384
385 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
386
387 /* special setup for PHY 88E1112 Fiber */
388 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
389 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
390
391 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
392 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
393 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
394 ctrl &= ~PHY_M_MAC_MD_MSK;
395 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
396 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
397
398 if (hw->pmd_type == 'P') {
399 /* select page 1 to access Fiber registers */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
401
402 /* for SFP-module set SIGDET polarity to low */
403 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
404 ctrl |= PHY_M_FIB_SIGD_POL;
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406 }
407
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
409 }
410
411 ctrl = PHY_CT_RESET;
412 ct1000 = 0;
413 adv = PHY_AN_CSMA;
414 reg = 0;
415
416 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
417 if (sky2_is_copper(hw)) {
418 if (sky2->advertising & ADVERTISED_1000baseT_Full)
419 ct1000 |= PHY_M_1000C_AFD;
420 if (sky2->advertising & ADVERTISED_1000baseT_Half)
421 ct1000 |= PHY_M_1000C_AHD;
422 if (sky2->advertising & ADVERTISED_100baseT_Full)
423 adv |= PHY_M_AN_100_FD;
424 if (sky2->advertising & ADVERTISED_100baseT_Half)
425 adv |= PHY_M_AN_100_HD;
426 if (sky2->advertising & ADVERTISED_10baseT_Full)
427 adv |= PHY_M_AN_10_FD;
428 if (sky2->advertising & ADVERTISED_10baseT_Half)
429 adv |= PHY_M_AN_10_HD;
430
431 } else { /* special defines for FIBER (88E1040S only) */
432 if (sky2->advertising & ADVERTISED_1000baseT_Full)
433 adv |= PHY_M_AN_1000X_AFD;
434 if (sky2->advertising & ADVERTISED_1000baseT_Half)
435 adv |= PHY_M_AN_1000X_AHD;
436 }
437
438 /* Restart Auto-negotiation */
439 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
440 } else {
441 /* forced speed/duplex settings */
442 ct1000 = PHY_M_1000C_MSE;
443
444 /* Disable auto update for duplex flow control and duplex */
445 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
446
447 switch (sky2->speed) {
448 case SPEED_1000:
449 ctrl |= PHY_CT_SP1000;
450 reg |= GM_GPCR_SPEED_1000;
451 break;
452 case SPEED_100:
453 ctrl |= PHY_CT_SP100;
454 reg |= GM_GPCR_SPEED_100;
455 break;
456 }
457
458 if (sky2->duplex == DUPLEX_FULL) {
459 reg |= GM_GPCR_DUP_FULL;
460 ctrl |= PHY_CT_DUP_MD;
461 } else if (sky2->speed < SPEED_1000)
462 sky2->flow_mode = FC_NONE;
463 }
464
465 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
466 if (sky2_is_copper(hw))
467 adv |= copper_fc_adv[sky2->flow_mode];
468 else
469 adv |= fiber_fc_adv[sky2->flow_mode];
470 } else {
471 reg |= GM_GPCR_AU_FCT_DIS;
472 reg |= gm_fc_disable[sky2->flow_mode];
473
474 /* Forward pause packets to GMAC? */
475 if (sky2->flow_mode & FC_RX)
476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
479 }
480
481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
483 if (hw->flags & SKY2_HW_GIGABIT)
484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
524 case CHIP_ID_YUKON_XL:
525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
545
546 /* restore page register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
548 break;
549
550 case CHIP_ID_YUKON_EC_U:
551 case CHIP_ID_YUKON_EX:
552 case CHIP_ID_YUKON_SUPR:
553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575
576 /* turn off the Rx LED (LED_RX) */
577 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
578 }
579
580 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
581 /* apply fixes in PHY AFE */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
583
584 /* increase differential signal amplitude in 10BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xaa99);
586 gm_phy_write(hw, port, 0x17, 0x2011);
587
588 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
589 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
590 gm_phy_write(hw, port, 0x18, 0xa204);
591 gm_phy_write(hw, port, 0x17, 0x2002);
592 }
593
594 /* set page register to 0 */
595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
596 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
597 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
598 /* apply workaround for integrated resistors calibration */
599 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
600 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
601 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
602 /* apply fixes in PHY AFE */
603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
604
605 /* apply RDAC termination workaround */
606 gm_phy_write(hw, port, 24, 0x2800);
607 gm_phy_write(hw, port, 23, 0x2001);
608
609 /* set page register back to 0 */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
611 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
612 hw->chip_id < CHIP_ID_YUKON_SUPR) {
613 /* no effect on Yukon-XL */
614 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
615
616 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
617 sky2->speed == SPEED_100) {
618 /* turn on 100 Mbps LED (LED_LINK100) */
619 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
620 }
621
622 if (ledover)
623 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
624
625 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
626 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
627 int i;
628 /* This a phy register setup workaround copied from vendor driver. */
629 static const struct {
630 u16 reg, val;
631 } eee_afe[] = {
632 { 0x156, 0x58ce },
633 { 0x153, 0x99eb },
634 { 0x141, 0x8064 },
635 /* { 0x155, 0x130b },*/
636 { 0x000, 0x0000 },
637 { 0x151, 0x8433 },
638 { 0x14b, 0x8c44 },
639 { 0x14c, 0x0f90 },
640 { 0x14f, 0x39aa },
641 /* { 0x154, 0x2f39 },*/
642 { 0x14d, 0xba33 },
643 { 0x144, 0x0048 },
644 { 0x152, 0x2010 },
645 /* { 0x158, 0x1223 },*/
646 { 0x140, 0x4444 },
647 { 0x154, 0x2f3b },
648 { 0x158, 0xb203 },
649 { 0x157, 0x2029 },
650 };
651
652 /* Start Workaround for OptimaEEE Rev.Z0 */
653 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
654
655 gm_phy_write(hw, port, 1, 0x4099);
656 gm_phy_write(hw, port, 3, 0x1120);
657 gm_phy_write(hw, port, 11, 0x113c);
658 gm_phy_write(hw, port, 14, 0x8100);
659 gm_phy_write(hw, port, 15, 0x112a);
660 gm_phy_write(hw, port, 17, 0x1008);
661
662 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
663 gm_phy_write(hw, port, 1, 0x20b0);
664
665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
666
667 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
668 /* apply AFE settings */
669 gm_phy_write(hw, port, 17, eee_afe[i].val);
670 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
671 }
672
673 /* End Workaround for OptimaEEE */
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
675
676 /* Enable 10Base-Te (EEE) */
677 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
678 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
679 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
680 reg | PHY_M_10B_TE_ENABLE);
681 }
682 }
683
684 /* Enable phy interrupt on auto-negotiation complete (or link up) */
685 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
686 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
687 else
688 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
689}
690
691static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
692static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
693
694static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
695{
696 u32 reg1;
697
698 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
699 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
700 reg1 &= ~phy_power[port];
701
702 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
703 reg1 |= coma_mode[port];
704
705 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
706 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
707 sky2_pci_read32(hw, PCI_DEV_REG1);
708
709 if (hw->chip_id == CHIP_ID_YUKON_FE)
710 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
711 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713}
714
715static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
716{
717 u32 reg1;
718 u16 ctrl;
719
720 /* release GPHY Control reset */
721 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
722
723 /* release GMAC reset */
724 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
725
726 if (hw->flags & SKY2_HW_NEWER_PHY) {
727 /* select page 2 to access MAC control register */
728 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
729
730 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
731 /* allow GMII Power Down */
732 ctrl &= ~PHY_M_MAC_GMIF_PUP;
733 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
734
735 /* set page register back to 0 */
736 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
737 }
738
739 /* setup General Purpose Control Register */
740 gma_write16(hw, port, GM_GP_CTRL,
741 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
742 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
743 GM_GPCR_AU_SPD_DIS);
744
745 if (hw->chip_id != CHIP_ID_YUKON_EC) {
746 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
747 /* select page 2 to access MAC control register */
748 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
749
750 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
751 /* enable Power Down */
752 ctrl |= PHY_M_PC_POW_D_ENA;
753 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
754
755 /* set page register back to 0 */
756 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
757 }
758
759 /* set IEEE compatible Power Down Mode (dev. #4.99) */
760 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
761 }
762
763 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
764 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
765 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
766 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
767 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
768}
769
770/* configure IPG according to used link speed */
771static void sky2_set_ipg(struct sky2_port *sky2)
772{
773 u16 reg;
774
775 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
776 reg &= ~GM_SMOD_IPG_MSK;
777 if (sky2->speed > SPEED_100)
778 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
779 else
780 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
781 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
782}
783
784/* Enable Rx/Tx */
785static void sky2_enable_rx_tx(struct sky2_port *sky2)
786{
787 struct sky2_hw *hw = sky2->hw;
788 unsigned port = sky2->port;
789 u16 reg;
790
791 reg = gma_read16(hw, port, GM_GP_CTRL);
792 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
793 gma_write16(hw, port, GM_GP_CTRL, reg);
794}
795
796/* Force a renegotiation */
797static void sky2_phy_reinit(struct sky2_port *sky2)
798{
799 spin_lock_bh(&sky2->phy_lock);
800 sky2_phy_init(sky2->hw, sky2->port);
801 sky2_enable_rx_tx(sky2);
802 spin_unlock_bh(&sky2->phy_lock);
803}
804
805/* Put device in state to listen for Wake On Lan */
806static void sky2_wol_init(struct sky2_port *sky2)
807{
808 struct sky2_hw *hw = sky2->hw;
809 unsigned port = sky2->port;
810 enum flow_control save_mode;
811 u16 ctrl;
812
813 /* Bring hardware out of reset */
814 sky2_write16(hw, B0_CTST, CS_RST_CLR);
815 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
816
817 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
818 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
819
820 /* Force to 10/100
821 * sky2_reset will re-enable on resume
822 */
823 save_mode = sky2->flow_mode;
824 ctrl = sky2->advertising;
825
826 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
827 sky2->flow_mode = FC_NONE;
828
829 spin_lock_bh(&sky2->phy_lock);
830 sky2_phy_power_up(hw, port);
831 sky2_phy_init(hw, port);
832 spin_unlock_bh(&sky2->phy_lock);
833
834 sky2->flow_mode = save_mode;
835 sky2->advertising = ctrl;
836
837 /* Set GMAC to no flow control and auto update for speed/duplex */
838 gma_write16(hw, port, GM_GP_CTRL,
839 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
840 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
841
842 /* Set WOL address */
843 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
844 sky2->netdev->dev_addr, ETH_ALEN);
845
846 /* Turn on appropriate WOL control bits */
847 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
848 ctrl = 0;
849 if (sky2->wol & WAKE_PHY)
850 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
851 else
852 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
853
854 if (sky2->wol & WAKE_MAGIC)
855 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
856 else
857 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
858
859 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
860 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
861
862 /* Disable PiG firmware */
863 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
864
865 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
866 if (legacy_pme) {
867 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
868 reg1 |= PCI_Y2_PME_LEGACY;
869 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
870 }
871
872 /* block receiver */
873 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
874 sky2_read32(hw, B0_CTST);
875}
876
877static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
878{
879 struct net_device *dev = hw->dev[port];
880
881 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
882 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
883 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
884 /* Yukon-Extreme B0 and further Extreme devices */
885 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
886 } else if (dev->mtu > ETH_DATA_LEN) {
887 /* set Tx GMAC FIFO Almost Empty Threshold */
888 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
889 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
890
891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
892 } else
893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
894}
895
896static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
897{
898 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
899 u16 reg;
900 u32 rx_reg;
901 int i;
902 const u8 *addr = hw->dev[port]->dev_addr;
903
904 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
905 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
906
907 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
908
909 if (hw->chip_id == CHIP_ID_YUKON_XL &&
910 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
911 port == 1) {
912 /* WA DEV_472 -- looks like crossed wires on port 2 */
913 /* clear GMAC 1 Control reset */
914 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
915 do {
916 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
917 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
918 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
919 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
920 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
921 }
922
923 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
924
925 /* Enable Transmit FIFO Underrun */
926 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
927
928 spin_lock_bh(&sky2->phy_lock);
929 sky2_phy_power_up(hw, port);
930 sky2_phy_init(hw, port);
931 spin_unlock_bh(&sky2->phy_lock);
932
933 /* MIB clear */
934 reg = gma_read16(hw, port, GM_PHY_ADDR);
935 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
936
937 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
938 gma_read16(hw, port, i);
939 gma_write16(hw, port, GM_PHY_ADDR, reg);
940
941 /* transmit control */
942 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
943
944 /* receive control reg: unicast + multicast + no FCS */
945 gma_write16(hw, port, GM_RX_CTRL,
946 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
947
948 /* transmit flow control */
949 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
950
951 /* transmit parameter */
952 gma_write16(hw, port, GM_TX_PARAM,
953 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
954 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
955 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
956 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
957
958 /* serial mode register */
959 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
960 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
961
962 if (hw->dev[port]->mtu > ETH_DATA_LEN)
963 reg |= GM_SMOD_JUMBO_ENA;
964
965 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
966 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
967 reg |= GM_NEW_FLOW_CTRL;
968
969 gma_write16(hw, port, GM_SERIAL_MODE, reg);
970
971 /* virtual address for data */
972 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
973
974 /* physical address: used for pause frames */
975 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
976
977 /* ignore counter overflows */
978 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
979 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
980 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
981
982 /* Configure Rx MAC FIFO */
983 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
984 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
985 if (hw->chip_id == CHIP_ID_YUKON_EX ||
986 hw->chip_id == CHIP_ID_YUKON_FE_P)
987 rx_reg |= GMF_RX_OVER_ON;
988
989 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
990
991 if (hw->chip_id == CHIP_ID_YUKON_XL) {
992 /* Hardware errata - clear flush mask */
993 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
994 } else {
995 /* Flush Rx MAC FIFO on any flow control or error */
996 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
997 }
998
999 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1000 reg = RX_GMF_FL_THR_DEF + 1;
1001 /* Another magic mystery workaround from sk98lin */
1002 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1003 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1004 reg = 0x178;
1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1006
1007 /* Configure Tx MAC FIFO */
1008 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1009 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1010
1011 /* On chips without ram buffer, pause is controlled by MAC level */
1012 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1013 /* Pause threshold is scaled by 8 in bytes */
1014 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1015 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1016 reg = 1568 / 8;
1017 else
1018 reg = 1024 / 8;
1019 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1020 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1021
1022 sky2_set_tx_stfwd(hw, port);
1023 }
1024
1025 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1026 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1027 /* disable dynamic watermark */
1028 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1029 reg &= ~TX_DYN_WM_ENA;
1030 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1031 }
1032}
1033
1034/* Assign Ram Buffer allocation to queue */
1035static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1036{
1037 u32 end;
1038
1039 /* convert from K bytes to qwords used for hw register */
1040 start *= 1024/8;
1041 space *= 1024/8;
1042 end = start + space - 1;
1043
1044 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1045 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1046 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1047 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1048 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1049
1050 if (q == Q_R1 || q == Q_R2) {
1051 u32 tp = space - space/4;
1052
1053 /* On receive queue's set the thresholds
1054 * give receiver priority when > 3/4 full
1055 * send pause when down to 2K
1056 */
1057 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1058 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1059
1060 tp = space - 8192/8;
1061 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1062 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1063 } else {
1064 /* Enable store & forward on Tx queue's because
1065 * Tx FIFO is only 1K on Yukon
1066 */
1067 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1068 }
1069
1070 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1071 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1072}
1073
1074/* Setup Bus Memory Interface */
1075static void sky2_qset(struct sky2_hw *hw, u16 q)
1076{
1077 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1078 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1080 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1081}
1082
1083/* Setup prefetch unit registers. This is the interface between
1084 * hardware and driver list elements
1085 */
1086static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1087 dma_addr_t addr, u32 last)
1088{
1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1093 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1094 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1095
1096 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1097}
1098
1099static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1100{
1101 struct sky2_tx_le *le = sky2->tx_le + *slot;
1102
1103 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1104 le->ctrl = 0;
1105 return le;
1106}
1107
1108static void tx_init(struct sky2_port *sky2)
1109{
1110 struct sky2_tx_le *le;
1111
1112 sky2->tx_prod = sky2->tx_cons = 0;
1113 sky2->tx_tcpsum = 0;
1114 sky2->tx_last_mss = 0;
1115 netdev_reset_queue(sky2->netdev);
1116
1117 le = get_tx_le(sky2, &sky2->tx_prod);
1118 le->addr = 0;
1119 le->opcode = OP_ADDR64 | HW_OWNER;
1120 sky2->tx_last_upper = 0;
1121}
1122
1123/* Update chip's next pointer */
1124static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1125{
1126 /* Make sure write' to descriptors are complete before we tell hardware */
1127 wmb();
1128 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1129}
1130
1131
1132static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1133{
1134 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1135 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1136 le->ctrl = 0;
1137 return le;
1138}
1139
1140static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1141{
1142 unsigned size;
1143
1144 /* Space needed for frame data + headers rounded up */
1145 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1146
1147 /* Stopping point for hardware truncation */
1148 return (size - 8) / sizeof(u32);
1149}
1150
1151static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1152{
1153 struct rx_ring_info *re;
1154 unsigned size;
1155
1156 /* Space needed for frame data + headers rounded up */
1157 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1158
1159 sky2->rx_nfrags = size >> PAGE_SHIFT;
1160 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1161
1162 /* Compute residue after pages */
1163 size -= sky2->rx_nfrags << PAGE_SHIFT;
1164
1165 /* Optimize to handle small packets and headers */
1166 if (size < copybreak)
1167 size = copybreak;
1168 if (size < ETH_HLEN)
1169 size = ETH_HLEN;
1170
1171 return size;
1172}
1173
1174/* Build description to hardware for one receive segment */
1175static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1176 dma_addr_t map, unsigned len)
1177{
1178 struct sky2_rx_le *le;
1179
1180 if (sizeof(dma_addr_t) > sizeof(u32)) {
1181 le = sky2_next_rx(sky2);
1182 le->addr = cpu_to_le32(upper_32_bits(map));
1183 le->opcode = OP_ADDR64 | HW_OWNER;
1184 }
1185
1186 le = sky2_next_rx(sky2);
1187 le->addr = cpu_to_le32(lower_32_bits(map));
1188 le->length = cpu_to_le16(len);
1189 le->opcode = op | HW_OWNER;
1190}
1191
1192/* Build description to hardware for one possibly fragmented skb */
1193static void sky2_rx_submit(struct sky2_port *sky2,
1194 const struct rx_ring_info *re)
1195{
1196 int i;
1197
1198 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1199
1200 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1201 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1202}
1203
1204
1205static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1206 unsigned size)
1207{
1208 struct sk_buff *skb = re->skb;
1209 int i;
1210
1211 re->data_addr = dma_map_single(&pdev->dev, skb->data, size,
1212 DMA_FROM_DEVICE);
1213 if (dma_mapping_error(&pdev->dev, re->data_addr))
1214 goto mapping_error;
1215
1216 dma_unmap_len_set(re, data_size, size);
1217
1218 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1219 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1220
1221 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1222 skb_frag_size(frag),
1223 DMA_FROM_DEVICE);
1224
1225 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1226 goto map_page_error;
1227 }
1228 return 0;
1229
1230map_page_error:
1231 while (--i >= 0) {
1232 dma_unmap_page(&pdev->dev, re->frag_addr[i],
1233 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1234 DMA_FROM_DEVICE);
1235 }
1236
1237 dma_unmap_single(&pdev->dev, re->data_addr,
1238 dma_unmap_len(re, data_size), DMA_FROM_DEVICE);
1239
1240mapping_error:
1241 if (net_ratelimit())
1242 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1243 skb->dev->name);
1244 return -EIO;
1245}
1246
1247static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1248{
1249 struct sk_buff *skb = re->skb;
1250 int i;
1251
1252 dma_unmap_single(&pdev->dev, re->data_addr,
1253 dma_unmap_len(re, data_size), DMA_FROM_DEVICE);
1254
1255 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1256 dma_unmap_page(&pdev->dev, re->frag_addr[i],
1257 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1258 DMA_FROM_DEVICE);
1259}
1260
1261/* Tell chip where to start receive checksum.
1262 * Actually has two checksums, but set both same to avoid possible byte
1263 * order problems.
1264 */
1265static void rx_set_checksum(struct sky2_port *sky2)
1266{
1267 struct sky2_rx_le *le = sky2_next_rx(sky2);
1268
1269 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1270 le->ctrl = 0;
1271 le->opcode = OP_TCPSTART | HW_OWNER;
1272
1273 sky2_write32(sky2->hw,
1274 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1275 (sky2->netdev->features & NETIF_F_RXCSUM)
1276 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1277}
1278
1279/* Enable/disable receive hash calculation (RSS) */
1280static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1281{
1282 struct sky2_port *sky2 = netdev_priv(dev);
1283 struct sky2_hw *hw = sky2->hw;
1284 int i, nkeys = 4;
1285
1286 /* Supports IPv6 and other modes */
1287 if (hw->flags & SKY2_HW_NEW_LE) {
1288 nkeys = 10;
1289 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1290 }
1291
1292 /* Program RSS initial values */
1293 if (features & NETIF_F_RXHASH) {
1294 u32 rss_key[10];
1295
1296 netdev_rss_key_fill(rss_key, sizeof(rss_key));
1297 for (i = 0; i < nkeys; i++)
1298 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1299 rss_key[i]);
1300
1301 /* Need to turn on (undocumented) flag to make hashing work */
1302 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1303 RX_STFW_ENA);
1304
1305 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1306 BMU_ENA_RX_RSS_HASH);
1307 } else
1308 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1309 BMU_DIS_RX_RSS_HASH);
1310}
1311
1312/*
1313 * The RX Stop command will not work for Yukon-2 if the BMU does not
1314 * reach the end of packet and since we can't make sure that we have
1315 * incoming data, we must reset the BMU while it is not doing a DMA
1316 * transfer. Since it is possible that the RX path is still active,
1317 * the RX RAM buffer will be stopped first, so any possible incoming
1318 * data will not trigger a DMA. After the RAM buffer is stopped, the
1319 * BMU is polled until any DMA in progress is ended and only then it
1320 * will be reset.
1321 */
1322static void sky2_rx_stop(struct sky2_port *sky2)
1323{
1324 struct sky2_hw *hw = sky2->hw;
1325 unsigned rxq = rxqaddr[sky2->port];
1326 int i;
1327
1328 /* disable the RAM Buffer receive queue */
1329 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1330
1331 for (i = 0; i < 0xffff; i++)
1332 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1333 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1334 goto stopped;
1335
1336 netdev_warn(sky2->netdev, "receiver stop failed\n");
1337stopped:
1338 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1339
1340 /* reset the Rx prefetch unit */
1341 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1342}
1343
1344/* Clean out receive buffer area, assumes receiver hardware stopped */
1345static void sky2_rx_clean(struct sky2_port *sky2)
1346{
1347 unsigned i;
1348
1349 if (sky2->rx_le)
1350 memset(sky2->rx_le, 0, RX_LE_BYTES);
1351
1352 for (i = 0; i < sky2->rx_pending; i++) {
1353 struct rx_ring_info *re = sky2->rx_ring + i;
1354
1355 if (re->skb) {
1356 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1357 kfree_skb(re->skb);
1358 re->skb = NULL;
1359 }
1360 }
1361}
1362
1363/* Basic MII support */
1364static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1365{
1366 struct mii_ioctl_data *data = if_mii(ifr);
1367 struct sky2_port *sky2 = netdev_priv(dev);
1368 struct sky2_hw *hw = sky2->hw;
1369 int err = -EOPNOTSUPP;
1370
1371 if (!netif_running(dev))
1372 return -ENODEV; /* Phy still in reset */
1373
1374 switch (cmd) {
1375 case SIOCGMIIPHY:
1376 data->phy_id = PHY_ADDR_MARV;
1377
1378 fallthrough;
1379 case SIOCGMIIREG: {
1380 u16 val = 0;
1381
1382 spin_lock_bh(&sky2->phy_lock);
1383 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1384 spin_unlock_bh(&sky2->phy_lock);
1385
1386 data->val_out = val;
1387 break;
1388 }
1389
1390 case SIOCSMIIREG:
1391 spin_lock_bh(&sky2->phy_lock);
1392 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1393 data->val_in);
1394 spin_unlock_bh(&sky2->phy_lock);
1395 break;
1396 }
1397 return err;
1398}
1399
1400#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1401
1402static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1403{
1404 struct sky2_port *sky2 = netdev_priv(dev);
1405 struct sky2_hw *hw = sky2->hw;
1406 u16 port = sky2->port;
1407
1408 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1409 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1410 RX_VLAN_STRIP_ON);
1411 else
1412 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1413 RX_VLAN_STRIP_OFF);
1414
1415 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1416 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1417 TX_VLAN_TAG_ON);
1418
1419 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1420 } else {
1421 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1422 TX_VLAN_TAG_OFF);
1423
1424 /* Can't do transmit offload of vlan without hw vlan */
1425 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1426 }
1427}
1428
1429/* Amount of required worst case padding in rx buffer */
1430static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1431{
1432 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1433}
1434
1435/*
1436 * Allocate an skb for receiving. If the MTU is large enough
1437 * make the skb non-linear with a fragment list of pages.
1438 */
1439static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1440{
1441 struct sk_buff *skb;
1442 int i;
1443
1444 skb = __netdev_alloc_skb(sky2->netdev,
1445 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1446 gfp);
1447 if (!skb)
1448 goto nomem;
1449
1450 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1451 unsigned char *start;
1452 /*
1453 * Workaround for a bug in FIFO that cause hang
1454 * if the FIFO if the receive buffer is not 64 byte aligned.
1455 * The buffer returned from netdev_alloc_skb is
1456 * aligned except if slab debugging is enabled.
1457 */
1458 start = PTR_ALIGN(skb->data, 8);
1459 skb_reserve(skb, start - skb->data);
1460 } else
1461 skb_reserve(skb, NET_IP_ALIGN);
1462
1463 for (i = 0; i < sky2->rx_nfrags; i++) {
1464 struct page *page = alloc_page(gfp);
1465
1466 if (!page)
1467 goto free_partial;
1468 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1469 }
1470
1471 return skb;
1472free_partial:
1473 kfree_skb(skb);
1474nomem:
1475 return NULL;
1476}
1477
1478static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1479{
1480 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1481}
1482
1483static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1484{
1485 struct sky2_hw *hw = sky2->hw;
1486 unsigned i;
1487
1488 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1489
1490 /* Fill Rx ring */
1491 for (i = 0; i < sky2->rx_pending; i++) {
1492 struct rx_ring_info *re = sky2->rx_ring + i;
1493
1494 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1495 if (!re->skb)
1496 return -ENOMEM;
1497
1498 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1499 dev_kfree_skb(re->skb);
1500 re->skb = NULL;
1501 return -ENOMEM;
1502 }
1503 }
1504 return 0;
1505}
1506
1507/*
1508 * Setup receiver buffer pool.
1509 * Normal case this ends up creating one list element for skb
1510 * in the receive ring. Worst case if using large MTU and each
1511 * allocation falls on a different 64 bit region, that results
1512 * in 6 list elements per ring entry.
1513 * One element is used for checksum enable/disable, and one
1514 * extra to avoid wrap.
1515 */
1516static void sky2_rx_start(struct sky2_port *sky2)
1517{
1518 struct sky2_hw *hw = sky2->hw;
1519 struct rx_ring_info *re;
1520 unsigned rxq = rxqaddr[sky2->port];
1521 unsigned i, thresh;
1522
1523 sky2->rx_put = sky2->rx_next = 0;
1524 sky2_qset(hw, rxq);
1525
1526 /* On PCI express lowering the watermark gives better performance */
1527 if (pci_is_pcie(hw->pdev))
1528 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1529
1530 /* These chips have no ram buffer?
1531 * MAC Rx RAM Read is controlled by hardware
1532 */
1533 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1534 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1535 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1536
1537 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1538
1539 if (!(hw->flags & SKY2_HW_NEW_LE))
1540 rx_set_checksum(sky2);
1541
1542 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1543 rx_set_rss(sky2->netdev, sky2->netdev->features);
1544
1545 /* submit Rx ring */
1546 for (i = 0; i < sky2->rx_pending; i++) {
1547 re = sky2->rx_ring + i;
1548 sky2_rx_submit(sky2, re);
1549 }
1550
1551 /*
1552 * The receiver hangs if it receives frames larger than the
1553 * packet buffer. As a workaround, truncate oversize frames, but
1554 * the register is limited to 9 bits, so if you do frames > 2052
1555 * you better get the MTU right!
1556 */
1557 thresh = sky2_get_rx_threshold(sky2);
1558 if (thresh > 0x1ff)
1559 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1560 else {
1561 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1562 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1563 }
1564
1565 /* Tell chip about available buffers */
1566 sky2_rx_update(sky2, rxq);
1567
1568 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1569 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1570 /*
1571 * Disable flushing of non ASF packets;
1572 * must be done after initializing the BMUs;
1573 * drivers without ASF support should do this too, otherwise
1574 * it may happen that they cannot run on ASF devices;
1575 * remember that the MAC FIFO isn't reset during initialization.
1576 */
1577 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1578 }
1579
1580 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1581 /* Enable RX Home Address & Routing Header checksum fix */
1582 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1583 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1584
1585 /* Enable TX Home Address & Routing Header checksum fix */
1586 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1587 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1588 }
1589}
1590
1591static int sky2_alloc_buffers(struct sky2_port *sky2)
1592{
1593 struct sky2_hw *hw = sky2->hw;
1594
1595 /* must be power of 2 */
1596 sky2->tx_le = dma_alloc_coherent(&hw->pdev->dev,
1597 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1598 &sky2->tx_le_map, GFP_KERNEL);
1599 if (!sky2->tx_le)
1600 goto nomem;
1601
1602 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1603 GFP_KERNEL);
1604 if (!sky2->tx_ring)
1605 goto nomem;
1606
1607 sky2->rx_le = dma_alloc_coherent(&hw->pdev->dev, RX_LE_BYTES,
1608 &sky2->rx_le_map, GFP_KERNEL);
1609 if (!sky2->rx_le)
1610 goto nomem;
1611
1612 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1613 GFP_KERNEL);
1614 if (!sky2->rx_ring)
1615 goto nomem;
1616
1617 return sky2_alloc_rx_skbs(sky2);
1618nomem:
1619 return -ENOMEM;
1620}
1621
1622static void sky2_free_buffers(struct sky2_port *sky2)
1623{
1624 struct sky2_hw *hw = sky2->hw;
1625
1626 sky2_rx_clean(sky2);
1627
1628 if (sky2->rx_le) {
1629 dma_free_coherent(&hw->pdev->dev, RX_LE_BYTES, sky2->rx_le,
1630 sky2->rx_le_map);
1631 sky2->rx_le = NULL;
1632 }
1633 if (sky2->tx_le) {
1634 dma_free_coherent(&hw->pdev->dev,
1635 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1636 sky2->tx_le, sky2->tx_le_map);
1637 sky2->tx_le = NULL;
1638 }
1639 kfree(sky2->tx_ring);
1640 kfree(sky2->rx_ring);
1641
1642 sky2->tx_ring = NULL;
1643 sky2->rx_ring = NULL;
1644}
1645
1646static void sky2_hw_up(struct sky2_port *sky2)
1647{
1648 struct sky2_hw *hw = sky2->hw;
1649 unsigned port = sky2->port;
1650 u32 ramsize;
1651 int cap;
1652 struct net_device *otherdev = hw->dev[sky2->port^1];
1653
1654 tx_init(sky2);
1655
1656 /*
1657 * On dual port PCI-X card, there is an problem where status
1658 * can be received out of order due to split transactions
1659 */
1660 if (otherdev && netif_running(otherdev) &&
1661 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1662 u16 cmd;
1663
1664 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1665 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1666 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1667 }
1668
1669 sky2_mac_init(hw, port);
1670
1671 /* Register is number of 4K blocks on internal RAM buffer. */
1672 ramsize = sky2_read8(hw, B2_E_0) * 4;
1673 if (ramsize > 0) {
1674 u32 rxspace;
1675
1676 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1677 if (ramsize < 16)
1678 rxspace = ramsize / 2;
1679 else
1680 rxspace = 8 + (2*(ramsize - 16))/3;
1681
1682 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1683 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1684
1685 /* Make sure SyncQ is disabled */
1686 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1687 RB_RST_SET);
1688 }
1689
1690 sky2_qset(hw, txqaddr[port]);
1691
1692 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1693 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1694 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1695
1696 /* Set almost empty threshold */
1697 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1698 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1699 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1700
1701 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1702 sky2->tx_ring_size - 1);
1703
1704 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1705 netdev_update_features(sky2->netdev);
1706
1707 sky2_rx_start(sky2);
1708}
1709
1710/* Setup device IRQ and enable napi to process */
1711static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1712{
1713 struct pci_dev *pdev = hw->pdev;
1714 int err;
1715
1716 err = request_irq(pdev->irq, sky2_intr,
1717 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1718 name, hw);
1719 if (err)
1720 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1721 else {
1722 hw->flags |= SKY2_HW_IRQ_SETUP;
1723
1724 napi_enable(&hw->napi);
1725 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1726 sky2_read32(hw, B0_IMSK);
1727 }
1728
1729 return err;
1730}
1731
1732
1733/* Bring up network interface. */
1734static int sky2_open(struct net_device *dev)
1735{
1736 struct sky2_port *sky2 = netdev_priv(dev);
1737 struct sky2_hw *hw = sky2->hw;
1738 unsigned port = sky2->port;
1739 u32 imask;
1740 int err;
1741
1742 netif_carrier_off(dev);
1743
1744 err = sky2_alloc_buffers(sky2);
1745 if (err)
1746 goto err_out;
1747
1748 /* With single port, IRQ is setup when device is brought up */
1749 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1750 goto err_out;
1751
1752 sky2_hw_up(sky2);
1753
1754 /* Enable interrupts from phy/mac for port */
1755 imask = sky2_read32(hw, B0_IMSK);
1756
1757 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1758 hw->chip_id == CHIP_ID_YUKON_PRM ||
1759 hw->chip_id == CHIP_ID_YUKON_OP_2)
1760 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1761
1762 imask |= portirq_msk[port];
1763 sky2_write32(hw, B0_IMSK, imask);
1764 sky2_read32(hw, B0_IMSK);
1765
1766 netif_info(sky2, ifup, dev, "enabling interface\n");
1767
1768 return 0;
1769
1770err_out:
1771 sky2_free_buffers(sky2);
1772 return err;
1773}
1774
1775/* Modular subtraction in ring */
1776static inline int tx_inuse(const struct sky2_port *sky2)
1777{
1778 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1779}
1780
1781/* Number of list elements available for next tx */
1782static inline int tx_avail(const struct sky2_port *sky2)
1783{
1784 return sky2->tx_pending - tx_inuse(sky2);
1785}
1786
1787/* Estimate of number of transmit list elements required */
1788static unsigned tx_le_req(const struct sk_buff *skb)
1789{
1790 unsigned count;
1791
1792 count = (skb_shinfo(skb)->nr_frags + 1)
1793 * (sizeof(dma_addr_t) / sizeof(u32));
1794
1795 if (skb_is_gso(skb))
1796 ++count;
1797 else if (sizeof(dma_addr_t) == sizeof(u32))
1798 ++count; /* possible vlan */
1799
1800 if (skb->ip_summed == CHECKSUM_PARTIAL)
1801 ++count;
1802
1803 return count;
1804}
1805
1806static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1807{
1808 if (re->flags & TX_MAP_SINGLE)
1809 dma_unmap_single(&pdev->dev, dma_unmap_addr(re, mapaddr),
1810 dma_unmap_len(re, maplen), DMA_TO_DEVICE);
1811 else if (re->flags & TX_MAP_PAGE)
1812 dma_unmap_page(&pdev->dev, dma_unmap_addr(re, mapaddr),
1813 dma_unmap_len(re, maplen), DMA_TO_DEVICE);
1814 re->flags = 0;
1815}
1816
1817/*
1818 * Put one packet in ring for transmit.
1819 * A single packet can generate multiple list elements, and
1820 * the number of ring elements will probably be less than the number
1821 * of list elements used.
1822 */
1823static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1824 struct net_device *dev)
1825{
1826 struct sky2_port *sky2 = netdev_priv(dev);
1827 struct sky2_hw *hw = sky2->hw;
1828 struct sky2_tx_le *le = NULL;
1829 struct tx_ring_info *re;
1830 unsigned i, len;
1831 dma_addr_t mapping;
1832 u32 upper;
1833 u16 slot;
1834 u16 mss;
1835 u8 ctrl;
1836
1837 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1838 return NETDEV_TX_BUSY;
1839
1840 len = skb_headlen(skb);
1841 mapping = dma_map_single(&hw->pdev->dev, skb->data, len,
1842 DMA_TO_DEVICE);
1843
1844 if (dma_mapping_error(&hw->pdev->dev, mapping))
1845 goto mapping_error;
1846
1847 slot = sky2->tx_prod;
1848 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1849 "tx queued, slot %u, len %d\n", slot, skb->len);
1850
1851 /* Send high bits if needed */
1852 upper = upper_32_bits(mapping);
1853 if (upper != sky2->tx_last_upper) {
1854 le = get_tx_le(sky2, &slot);
1855 le->addr = cpu_to_le32(upper);
1856 sky2->tx_last_upper = upper;
1857 le->opcode = OP_ADDR64 | HW_OWNER;
1858 }
1859
1860 /* Check for TCP Segmentation Offload */
1861 mss = skb_shinfo(skb)->gso_size;
1862 if (mss != 0) {
1863
1864 if (!(hw->flags & SKY2_HW_NEW_LE))
1865 mss += skb_tcp_all_headers(skb);
1866
1867 if (mss != sky2->tx_last_mss) {
1868 le = get_tx_le(sky2, &slot);
1869 le->addr = cpu_to_le32(mss);
1870
1871 if (hw->flags & SKY2_HW_NEW_LE)
1872 le->opcode = OP_MSS | HW_OWNER;
1873 else
1874 le->opcode = OP_LRGLEN | HW_OWNER;
1875 sky2->tx_last_mss = mss;
1876 }
1877 }
1878
1879 ctrl = 0;
1880
1881 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1882 if (skb_vlan_tag_present(skb)) {
1883 if (!le) {
1884 le = get_tx_le(sky2, &slot);
1885 le->addr = 0;
1886 le->opcode = OP_VLAN|HW_OWNER;
1887 } else
1888 le->opcode |= OP_VLAN;
1889 le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1890 ctrl |= INS_VLAN;
1891 }
1892
1893 /* Handle TCP checksum offload */
1894 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1895 /* On Yukon EX (some versions) encoding change. */
1896 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1897 ctrl |= CALSUM; /* auto checksum */
1898 else {
1899 const unsigned offset = skb_transport_offset(skb);
1900 u32 tcpsum;
1901
1902 tcpsum = offset << 16; /* sum start */
1903 tcpsum |= offset + skb->csum_offset; /* sum write */
1904
1905 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1906 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1907 ctrl |= UDPTCP;
1908
1909 if (tcpsum != sky2->tx_tcpsum) {
1910 sky2->tx_tcpsum = tcpsum;
1911
1912 le = get_tx_le(sky2, &slot);
1913 le->addr = cpu_to_le32(tcpsum);
1914 le->length = 0; /* initial checksum value */
1915 le->ctrl = 1; /* one packet */
1916 le->opcode = OP_TCPLISW | HW_OWNER;
1917 }
1918 }
1919 }
1920
1921 re = sky2->tx_ring + slot;
1922 re->flags = TX_MAP_SINGLE;
1923 dma_unmap_addr_set(re, mapaddr, mapping);
1924 dma_unmap_len_set(re, maplen, len);
1925
1926 le = get_tx_le(sky2, &slot);
1927 le->addr = cpu_to_le32(lower_32_bits(mapping));
1928 le->length = cpu_to_le16(len);
1929 le->ctrl = ctrl;
1930 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1931
1932
1933 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1934 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1935
1936 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1937 skb_frag_size(frag), DMA_TO_DEVICE);
1938
1939 if (dma_mapping_error(&hw->pdev->dev, mapping))
1940 goto mapping_unwind;
1941
1942 upper = upper_32_bits(mapping);
1943 if (upper != sky2->tx_last_upper) {
1944 le = get_tx_le(sky2, &slot);
1945 le->addr = cpu_to_le32(upper);
1946 sky2->tx_last_upper = upper;
1947 le->opcode = OP_ADDR64 | HW_OWNER;
1948 }
1949
1950 re = sky2->tx_ring + slot;
1951 re->flags = TX_MAP_PAGE;
1952 dma_unmap_addr_set(re, mapaddr, mapping);
1953 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1954
1955 le = get_tx_le(sky2, &slot);
1956 le->addr = cpu_to_le32(lower_32_bits(mapping));
1957 le->length = cpu_to_le16(skb_frag_size(frag));
1958 le->ctrl = ctrl;
1959 le->opcode = OP_BUFFER | HW_OWNER;
1960 }
1961
1962 re->skb = skb;
1963 le->ctrl |= EOP;
1964
1965 sky2->tx_prod = slot;
1966
1967 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1968 netif_stop_queue(dev);
1969
1970 netdev_sent_queue(dev, skb->len);
1971 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1972
1973 return NETDEV_TX_OK;
1974
1975mapping_unwind:
1976 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1977 re = sky2->tx_ring + i;
1978
1979 sky2_tx_unmap(hw->pdev, re);
1980 }
1981
1982mapping_error:
1983 if (net_ratelimit())
1984 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1985 dev_kfree_skb_any(skb);
1986 return NETDEV_TX_OK;
1987}
1988
1989/*
1990 * Free ring elements from starting at tx_cons until "done"
1991 *
1992 * NB:
1993 * 1. The hardware will tell us about partial completion of multi-part
1994 * buffers so make sure not to free skb to early.
1995 * 2. This may run in parallel start_xmit because the it only
1996 * looks at the tail of the queue of FIFO (tx_cons), not
1997 * the head (tx_prod)
1998 */
1999static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2000{
2001 struct net_device *dev = sky2->netdev;
2002 u16 idx;
2003 unsigned int bytes_compl = 0, pkts_compl = 0;
2004
2005 BUG_ON(done >= sky2->tx_ring_size);
2006
2007 for (idx = sky2->tx_cons; idx != done;
2008 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2009 struct tx_ring_info *re = sky2->tx_ring + idx;
2010 struct sk_buff *skb = re->skb;
2011
2012 sky2_tx_unmap(sky2->hw->pdev, re);
2013
2014 if (skb) {
2015 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2016 "tx done %u\n", idx);
2017
2018 pkts_compl++;
2019 bytes_compl += skb->len;
2020
2021 re->skb = NULL;
2022 dev_kfree_skb_any(skb);
2023
2024 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2025 }
2026 }
2027
2028 sky2->tx_cons = idx;
2029 smp_mb();
2030
2031 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2032
2033 u64_stats_update_begin(&sky2->tx_stats.syncp);
2034 sky2->tx_stats.packets += pkts_compl;
2035 sky2->tx_stats.bytes += bytes_compl;
2036 u64_stats_update_end(&sky2->tx_stats.syncp);
2037}
2038
2039static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2040{
2041 /* Disable Force Sync bit and Enable Alloc bit */
2042 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2043 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2044
2045 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2046 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2047 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2048
2049 /* Reset the PCI FIFO of the async Tx queue */
2050 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2051 BMU_RST_SET | BMU_FIFO_RST);
2052
2053 /* Reset the Tx prefetch units */
2054 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2055 PREF_UNIT_RST_SET);
2056
2057 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2058 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2059
2060 sky2_read32(hw, B0_CTST);
2061}
2062
2063static void sky2_hw_down(struct sky2_port *sky2)
2064{
2065 struct sky2_hw *hw = sky2->hw;
2066 unsigned port = sky2->port;
2067 u16 ctrl;
2068
2069 /* Force flow control off */
2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2071
2072 /* Stop transmitter */
2073 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2074 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2075
2076 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2077 RB_RST_SET | RB_DIS_OP_MD);
2078
2079 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2080 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2081 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2082
2083 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2084
2085 /* Workaround shared GMAC reset */
2086 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2087 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2088 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2089
2090 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2091
2092 /* Force any delayed status interrupt and NAPI */
2093 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2094 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2095 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2096 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2097
2098 sky2_rx_stop(sky2);
2099
2100 spin_lock_bh(&sky2->phy_lock);
2101 sky2_phy_power_down(hw, port);
2102 spin_unlock_bh(&sky2->phy_lock);
2103
2104 sky2_tx_reset(hw, port);
2105
2106 /* Free any pending frames stuck in HW queue */
2107 sky2_tx_complete(sky2, sky2->tx_prod);
2108}
2109
2110/* Network shutdown */
2111static int sky2_close(struct net_device *dev)
2112{
2113 struct sky2_port *sky2 = netdev_priv(dev);
2114 struct sky2_hw *hw = sky2->hw;
2115
2116 /* Never really got started! */
2117 if (!sky2->tx_le)
2118 return 0;
2119
2120 netif_info(sky2, ifdown, dev, "disabling interface\n");
2121
2122 if (hw->ports == 1) {
2123 sky2_write32(hw, B0_IMSK, 0);
2124 sky2_read32(hw, B0_IMSK);
2125
2126 napi_disable(&hw->napi);
2127 free_irq(hw->pdev->irq, hw);
2128 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2129 } else {
2130 u32 imask;
2131
2132 /* Disable port IRQ */
2133 imask = sky2_read32(hw, B0_IMSK);
2134 imask &= ~portirq_msk[sky2->port];
2135 sky2_write32(hw, B0_IMSK, imask);
2136 sky2_read32(hw, B0_IMSK);
2137
2138 synchronize_irq(hw->pdev->irq);
2139 napi_synchronize(&hw->napi);
2140 }
2141
2142 sky2_hw_down(sky2);
2143
2144 sky2_free_buffers(sky2);
2145
2146 return 0;
2147}
2148
2149static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2150{
2151 if (hw->flags & SKY2_HW_FIBRE_PHY)
2152 return SPEED_1000;
2153
2154 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2155 if (aux & PHY_M_PS_SPEED_100)
2156 return SPEED_100;
2157 else
2158 return SPEED_10;
2159 }
2160
2161 switch (aux & PHY_M_PS_SPEED_MSK) {
2162 case PHY_M_PS_SPEED_1000:
2163 return SPEED_1000;
2164 case PHY_M_PS_SPEED_100:
2165 return SPEED_100;
2166 default:
2167 return SPEED_10;
2168 }
2169}
2170
2171static void sky2_link_up(struct sky2_port *sky2)
2172{
2173 struct sky2_hw *hw = sky2->hw;
2174 unsigned port = sky2->port;
2175 static const char *fc_name[] = {
2176 [FC_NONE] = "none",
2177 [FC_TX] = "tx",
2178 [FC_RX] = "rx",
2179 [FC_BOTH] = "both",
2180 };
2181
2182 sky2_set_ipg(sky2);
2183
2184 sky2_enable_rx_tx(sky2);
2185
2186 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2187
2188 netif_carrier_on(sky2->netdev);
2189
2190 mod_timer(&hw->watchdog_timer, jiffies + 1);
2191
2192 /* Turn on link LED */
2193 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2194 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2195
2196 netif_info(sky2, link, sky2->netdev,
2197 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2198 sky2->speed,
2199 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2200 fc_name[sky2->flow_status]);
2201}
2202
2203static void sky2_link_down(struct sky2_port *sky2)
2204{
2205 struct sky2_hw *hw = sky2->hw;
2206 unsigned port = sky2->port;
2207 u16 reg;
2208
2209 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2210
2211 reg = gma_read16(hw, port, GM_GP_CTRL);
2212 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2213 gma_write16(hw, port, GM_GP_CTRL, reg);
2214
2215 netif_carrier_off(sky2->netdev);
2216
2217 /* Turn off link LED */
2218 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2219
2220 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2221
2222 sky2_phy_init(hw, port);
2223}
2224
2225static enum flow_control sky2_flow(int rx, int tx)
2226{
2227 if (rx)
2228 return tx ? FC_BOTH : FC_RX;
2229 else
2230 return tx ? FC_TX : FC_NONE;
2231}
2232
2233static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2234{
2235 struct sky2_hw *hw = sky2->hw;
2236 unsigned port = sky2->port;
2237 u16 advert, lpa;
2238
2239 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2240 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2241 if (lpa & PHY_M_AN_RF) {
2242 netdev_err(sky2->netdev, "remote fault\n");
2243 return -1;
2244 }
2245
2246 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2247 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2248 return -1;
2249 }
2250
2251 sky2->speed = sky2_phy_speed(hw, aux);
2252 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2253
2254 /* Since the pause result bits seem to in different positions on
2255 * different chips. look at registers.
2256 */
2257 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2258 /* Shift for bits in fiber PHY */
2259 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2260 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2261
2262 if (advert & ADVERTISE_1000XPAUSE)
2263 advert |= ADVERTISE_PAUSE_CAP;
2264 if (advert & ADVERTISE_1000XPSE_ASYM)
2265 advert |= ADVERTISE_PAUSE_ASYM;
2266 if (lpa & LPA_1000XPAUSE)
2267 lpa |= LPA_PAUSE_CAP;
2268 if (lpa & LPA_1000XPAUSE_ASYM)
2269 lpa |= LPA_PAUSE_ASYM;
2270 }
2271
2272 sky2->flow_status = FC_NONE;
2273 if (advert & ADVERTISE_PAUSE_CAP) {
2274 if (lpa & LPA_PAUSE_CAP)
2275 sky2->flow_status = FC_BOTH;
2276 else if (advert & ADVERTISE_PAUSE_ASYM)
2277 sky2->flow_status = FC_RX;
2278 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2279 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2280 sky2->flow_status = FC_TX;
2281 }
2282
2283 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2284 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2285 sky2->flow_status = FC_NONE;
2286
2287 if (sky2->flow_status & FC_TX)
2288 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2289 else
2290 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2291
2292 return 0;
2293}
2294
2295/* Interrupt from PHY */
2296static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2297{
2298 struct net_device *dev = hw->dev[port];
2299 struct sky2_port *sky2 = netdev_priv(dev);
2300 u16 istatus, phystat;
2301
2302 if (!netif_running(dev))
2303 return;
2304
2305 spin_lock(&sky2->phy_lock);
2306 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2307 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2308
2309 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2310 istatus, phystat);
2311
2312 if (istatus & PHY_M_IS_AN_COMPL) {
2313 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2314 !netif_carrier_ok(dev))
2315 sky2_link_up(sky2);
2316 goto out;
2317 }
2318
2319 if (istatus & PHY_M_IS_LSP_CHANGE)
2320 sky2->speed = sky2_phy_speed(hw, phystat);
2321
2322 if (istatus & PHY_M_IS_DUP_CHANGE)
2323 sky2->duplex =
2324 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2325
2326 if (istatus & PHY_M_IS_LST_CHANGE) {
2327 if (phystat & PHY_M_PS_LINK_UP)
2328 sky2_link_up(sky2);
2329 else
2330 sky2_link_down(sky2);
2331 }
2332out:
2333 spin_unlock(&sky2->phy_lock);
2334}
2335
2336/* Special quick link interrupt (Yukon-2 Optima only) */
2337static void sky2_qlink_intr(struct sky2_hw *hw)
2338{
2339 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2340 u32 imask;
2341 u16 phy;
2342
2343 /* disable irq */
2344 imask = sky2_read32(hw, B0_IMSK);
2345 imask &= ~Y2_IS_PHY_QLNK;
2346 sky2_write32(hw, B0_IMSK, imask);
2347
2348 /* reset PHY Link Detect */
2349 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2350 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2351 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2353
2354 sky2_link_up(sky2);
2355}
2356
2357/* Transmit timeout is only called if we are running, carrier is up
2358 * and tx queue is full (stopped).
2359 */
2360static void sky2_tx_timeout(struct net_device *dev, unsigned int txqueue)
2361{
2362 struct sky2_port *sky2 = netdev_priv(dev);
2363 struct sky2_hw *hw = sky2->hw;
2364
2365 netif_err(sky2, timer, dev, "tx timeout\n");
2366
2367 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2368 sky2->tx_cons, sky2->tx_prod,
2369 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2370 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2371
2372 /* can't restart safely under softirq */
2373 schedule_work(&hw->restart_work);
2374}
2375
2376static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2377{
2378 struct sky2_port *sky2 = netdev_priv(dev);
2379 struct sky2_hw *hw = sky2->hw;
2380 unsigned port = sky2->port;
2381 int err;
2382 u16 ctl, mode;
2383 u32 imask;
2384
2385 if (!netif_running(dev)) {
2386 dev->mtu = new_mtu;
2387 netdev_update_features(dev);
2388 return 0;
2389 }
2390
2391 imask = sky2_read32(hw, B0_IMSK);
2392 sky2_write32(hw, B0_IMSK, 0);
2393 sky2_read32(hw, B0_IMSK);
2394
2395 netif_trans_update(dev); /* prevent tx timeout */
2396 napi_disable(&hw->napi);
2397 netif_tx_disable(dev);
2398
2399 synchronize_irq(hw->pdev->irq);
2400
2401 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2402 sky2_set_tx_stfwd(hw, port);
2403
2404 ctl = gma_read16(hw, port, GM_GP_CTRL);
2405 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2406 sky2_rx_stop(sky2);
2407 sky2_rx_clean(sky2);
2408
2409 dev->mtu = new_mtu;
2410 netdev_update_features(dev);
2411
2412 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2413 if (sky2->speed > SPEED_100)
2414 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2415 else
2416 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2417
2418 if (dev->mtu > ETH_DATA_LEN)
2419 mode |= GM_SMOD_JUMBO_ENA;
2420
2421 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2422
2423 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2424
2425 err = sky2_alloc_rx_skbs(sky2);
2426 if (!err)
2427 sky2_rx_start(sky2);
2428 else
2429 sky2_rx_clean(sky2);
2430 sky2_write32(hw, B0_IMSK, imask);
2431
2432 sky2_read32(hw, B0_Y2_SP_LISR);
2433 napi_enable(&hw->napi);
2434
2435 if (err)
2436 dev_close(dev);
2437 else {
2438 gma_write16(hw, port, GM_GP_CTRL, ctl);
2439
2440 netif_wake_queue(dev);
2441 }
2442
2443 return err;
2444}
2445
2446static inline bool needs_copy(const struct rx_ring_info *re,
2447 unsigned length)
2448{
2449#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2450 /* Some architectures need the IP header to be aligned */
2451 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2452 return true;
2453#endif
2454 return length < copybreak;
2455}
2456
2457/* For small just reuse existing skb for next receive */
2458static struct sk_buff *receive_copy(struct sky2_port *sky2,
2459 const struct rx_ring_info *re,
2460 unsigned length)
2461{
2462 struct sk_buff *skb;
2463
2464 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2465 if (likely(skb)) {
2466 dma_sync_single_for_cpu(&sky2->hw->pdev->dev, re->data_addr,
2467 length, DMA_FROM_DEVICE);
2468 skb_copy_from_linear_data(re->skb, skb->data, length);
2469 skb->ip_summed = re->skb->ip_summed;
2470 skb->csum = re->skb->csum;
2471 skb_copy_hash(skb, re->skb);
2472 __vlan_hwaccel_copy_tag(skb, re->skb);
2473
2474 dma_sync_single_for_device(&sky2->hw->pdev->dev,
2475 re->data_addr, length,
2476 DMA_FROM_DEVICE);
2477 __vlan_hwaccel_clear_tag(re->skb);
2478 skb_clear_hash(re->skb);
2479 re->skb->ip_summed = CHECKSUM_NONE;
2480 skb_put(skb, length);
2481 }
2482 return skb;
2483}
2484
2485/* Adjust length of skb with fragments to match received data */
2486static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2487 unsigned int length)
2488{
2489 int i, num_frags;
2490 unsigned int size;
2491
2492 /* put header into skb */
2493 size = min(length, hdr_space);
2494 skb->tail += size;
2495 skb->len += size;
2496 length -= size;
2497
2498 num_frags = skb_shinfo(skb)->nr_frags;
2499 for (i = 0; i < num_frags; i++) {
2500 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2501
2502 if (length == 0) {
2503 /* don't need this page */
2504 __skb_frag_unref(frag, false);
2505 --skb_shinfo(skb)->nr_frags;
2506 } else {
2507 size = min(length, (unsigned) PAGE_SIZE);
2508
2509 skb_frag_size_set(frag, size);
2510 skb->data_len += size;
2511 skb->truesize += PAGE_SIZE;
2512 skb->len += size;
2513 length -= size;
2514 }
2515 }
2516}
2517
2518/* Normal packet - take skb from ring element and put in a new one */
2519static struct sk_buff *receive_new(struct sky2_port *sky2,
2520 struct rx_ring_info *re,
2521 unsigned int length)
2522{
2523 struct sk_buff *skb;
2524 struct rx_ring_info nre;
2525 unsigned hdr_space = sky2->rx_data_size;
2526
2527 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2528 if (unlikely(!nre.skb))
2529 goto nobuf;
2530
2531 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2532 goto nomap;
2533
2534 skb = re->skb;
2535 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2536 prefetch(skb->data);
2537 *re = nre;
2538
2539 if (skb_shinfo(skb)->nr_frags)
2540 skb_put_frags(skb, hdr_space, length);
2541 else
2542 skb_put(skb, length);
2543 return skb;
2544
2545nomap:
2546 dev_kfree_skb(nre.skb);
2547nobuf:
2548 return NULL;
2549}
2550
2551/*
2552 * Receive one packet.
2553 * For larger packets, get new buffer.
2554 */
2555static struct sk_buff *sky2_receive(struct net_device *dev,
2556 u16 length, u32 status)
2557{
2558 struct sky2_port *sky2 = netdev_priv(dev);
2559 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2560 struct sk_buff *skb = NULL;
2561 u16 count = (status & GMR_FS_LEN) >> 16;
2562
2563 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2564 "rx slot %u status 0x%x len %d\n",
2565 sky2->rx_next, status, length);
2566
2567 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2568 prefetch(sky2->rx_ring + sky2->rx_next);
2569
2570 if (skb_vlan_tag_present(re->skb))
2571 count -= VLAN_HLEN; /* Account for vlan tag */
2572
2573 /* This chip has hardware problems that generates bogus status.
2574 * So do only marginal checking and expect higher level protocols
2575 * to handle crap frames.
2576 */
2577 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2578 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2579 length != count)
2580 goto okay;
2581
2582 if (status & GMR_FS_ANY_ERR)
2583 goto error;
2584
2585 if (!(status & GMR_FS_RX_OK))
2586 goto resubmit;
2587
2588 /* if length reported by DMA does not match PHY, packet was truncated */
2589 if (length != count)
2590 goto error;
2591
2592okay:
2593 if (needs_copy(re, length))
2594 skb = receive_copy(sky2, re, length);
2595 else
2596 skb = receive_new(sky2, re, length);
2597
2598 dev->stats.rx_dropped += (skb == NULL);
2599
2600resubmit:
2601 sky2_rx_submit(sky2, re);
2602
2603 return skb;
2604
2605error:
2606 ++dev->stats.rx_errors;
2607
2608 if (net_ratelimit())
2609 netif_info(sky2, rx_err, dev,
2610 "rx error, status 0x%x length %d\n", status, length);
2611
2612 goto resubmit;
2613}
2614
2615/* Transmit complete */
2616static inline void sky2_tx_done(struct net_device *dev, u16 last)
2617{
2618 struct sky2_port *sky2 = netdev_priv(dev);
2619
2620 if (netif_running(dev)) {
2621 sky2_tx_complete(sky2, last);
2622
2623 /* Wake unless it's detached, and called e.g. from sky2_close() */
2624 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2625 netif_wake_queue(dev);
2626 }
2627}
2628
2629static inline void sky2_skb_rx(const struct sky2_port *sky2,
2630 struct sk_buff *skb)
2631{
2632 if (skb->ip_summed == CHECKSUM_NONE)
2633 netif_receive_skb(skb);
2634 else
2635 napi_gro_receive(&sky2->hw->napi, skb);
2636}
2637
2638static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2639 unsigned packets, unsigned bytes)
2640{
2641 struct net_device *dev = hw->dev[port];
2642 struct sky2_port *sky2 = netdev_priv(dev);
2643
2644 if (packets == 0)
2645 return;
2646
2647 u64_stats_update_begin(&sky2->rx_stats.syncp);
2648 sky2->rx_stats.packets += packets;
2649 sky2->rx_stats.bytes += bytes;
2650 u64_stats_update_end(&sky2->rx_stats.syncp);
2651
2652 sky2->last_rx = jiffies;
2653 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2654}
2655
2656static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2657{
2658 /* If this happens then driver assuming wrong format for chip type */
2659 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2660
2661 /* Both checksum counters are programmed to start at
2662 * the same offset, so unless there is a problem they
2663 * should match. This failure is an early indication that
2664 * hardware receive checksumming won't work.
2665 */
2666 if (likely((u16)(status >> 16) == (u16)status)) {
2667 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2668 skb->ip_summed = CHECKSUM_COMPLETE;
2669 skb->csum = le16_to_cpu(status);
2670 } else {
2671 dev_notice(&sky2->hw->pdev->dev,
2672 "%s: receive checksum problem (status = %#x)\n",
2673 sky2->netdev->name, status);
2674
2675 /* Disable checksum offload
2676 * It will be reenabled on next ndo_set_features, but if it's
2677 * really broken, will get disabled again
2678 */
2679 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2680 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2681 BMU_DIS_RX_CHKSUM);
2682 }
2683}
2684
2685static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2686{
2687 struct sk_buff *skb;
2688
2689 skb = sky2->rx_ring[sky2->rx_next].skb;
2690 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2691}
2692
2693static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2694{
2695 struct sk_buff *skb;
2696
2697 skb = sky2->rx_ring[sky2->rx_next].skb;
2698 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2699}
2700
2701/* Process status response ring */
2702static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2703{
2704 int work_done = 0;
2705 unsigned int total_bytes[2] = { 0 };
2706 unsigned int total_packets[2] = { 0 };
2707
2708 if (to_do <= 0)
2709 return work_done;
2710
2711 rmb();
2712 do {
2713 struct sky2_port *sky2;
2714 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2715 unsigned port;
2716 struct net_device *dev;
2717 struct sk_buff *skb;
2718 u32 status;
2719 u16 length;
2720 u8 opcode = le->opcode;
2721
2722 if (!(opcode & HW_OWNER))
2723 break;
2724
2725 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2726
2727 port = le->css & CSS_LINK_BIT;
2728 dev = hw->dev[port];
2729 sky2 = netdev_priv(dev);
2730 length = le16_to_cpu(le->length);
2731 status = le32_to_cpu(le->status);
2732
2733 le->opcode = 0;
2734 switch (opcode & ~HW_OWNER) {
2735 case OP_RXSTAT:
2736 total_packets[port]++;
2737 total_bytes[port] += length;
2738
2739 skb = sky2_receive(dev, length, status);
2740 if (!skb)
2741 break;
2742
2743 /* This chip reports checksum status differently */
2744 if (hw->flags & SKY2_HW_NEW_LE) {
2745 if ((dev->features & NETIF_F_RXCSUM) &&
2746 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2747 (le->css & CSS_TCPUDPCSOK))
2748 skb->ip_summed = CHECKSUM_UNNECESSARY;
2749 else
2750 skb->ip_summed = CHECKSUM_NONE;
2751 }
2752
2753 skb->protocol = eth_type_trans(skb, dev);
2754 sky2_skb_rx(sky2, skb);
2755
2756 /* Stop after net poll weight */
2757 if (++work_done >= to_do)
2758 goto exit_loop;
2759 break;
2760
2761 case OP_RXVLAN:
2762 sky2_rx_tag(sky2, length);
2763 break;
2764
2765 case OP_RXCHKSVLAN:
2766 sky2_rx_tag(sky2, length);
2767 fallthrough;
2768 case OP_RXCHKS:
2769 if (likely(dev->features & NETIF_F_RXCSUM))
2770 sky2_rx_checksum(sky2, status);
2771 break;
2772
2773 case OP_RSS_HASH:
2774 sky2_rx_hash(sky2, status);
2775 break;
2776
2777 case OP_TXINDEXLE:
2778 /* TX index reports status for both ports */
2779 sky2_tx_done(hw->dev[0], status & 0xfff);
2780 if (hw->dev[1])
2781 sky2_tx_done(hw->dev[1],
2782 ((status >> 24) & 0xff)
2783 | (u16)(length & 0xf) << 8);
2784 break;
2785
2786 default:
2787 if (net_ratelimit())
2788 pr_warn("unknown status opcode 0x%x\n", opcode);
2789 }
2790 } while (hw->st_idx != idx);
2791
2792 /* Fully processed status ring so clear irq */
2793 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2794
2795exit_loop:
2796 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2797 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2798
2799 return work_done;
2800}
2801
2802static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2803{
2804 struct net_device *dev = hw->dev[port];
2805
2806 if (net_ratelimit())
2807 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2808
2809 if (status & Y2_IS_PAR_RD1) {
2810 if (net_ratelimit())
2811 netdev_err(dev, "ram data read parity error\n");
2812 /* Clear IRQ */
2813 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2814 }
2815
2816 if (status & Y2_IS_PAR_WR1) {
2817 if (net_ratelimit())
2818 netdev_err(dev, "ram data write parity error\n");
2819
2820 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2821 }
2822
2823 if (status & Y2_IS_PAR_MAC1) {
2824 if (net_ratelimit())
2825 netdev_err(dev, "MAC parity error\n");
2826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2827 }
2828
2829 if (status & Y2_IS_PAR_RX1) {
2830 if (net_ratelimit())
2831 netdev_err(dev, "RX parity error\n");
2832 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2833 }
2834
2835 if (status & Y2_IS_TCP_TXA1) {
2836 if (net_ratelimit())
2837 netdev_err(dev, "TCP segmentation error\n");
2838 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2839 }
2840}
2841
2842static void sky2_hw_intr(struct sky2_hw *hw)
2843{
2844 struct pci_dev *pdev = hw->pdev;
2845 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2846 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2847
2848 status &= hwmsk;
2849
2850 if (status & Y2_IS_TIST_OV)
2851 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2852
2853 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2854 u16 pci_err;
2855
2856 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2857 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2858 if (net_ratelimit())
2859 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2860 pci_err);
2861
2862 sky2_pci_write16(hw, PCI_STATUS,
2863 pci_err | PCI_STATUS_ERROR_BITS);
2864 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2865 }
2866
2867 if (status & Y2_IS_PCI_EXP) {
2868 /* PCI-Express uncorrectable Error occurred */
2869 u32 err;
2870
2871 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2872 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2873 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2874 0xfffffffful);
2875 if (net_ratelimit())
2876 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2877
2878 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2879 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2880 }
2881
2882 if (status & Y2_HWE_L1_MASK)
2883 sky2_hw_error(hw, 0, status);
2884 status >>= 8;
2885 if (status & Y2_HWE_L1_MASK)
2886 sky2_hw_error(hw, 1, status);
2887}
2888
2889static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2890{
2891 struct net_device *dev = hw->dev[port];
2892 struct sky2_port *sky2 = netdev_priv(dev);
2893 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2894
2895 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2896
2897 if (status & GM_IS_RX_CO_OV)
2898 gma_read16(hw, port, GM_RX_IRQ_SRC);
2899
2900 if (status & GM_IS_TX_CO_OV)
2901 gma_read16(hw, port, GM_TX_IRQ_SRC);
2902
2903 if (status & GM_IS_RX_FF_OR) {
2904 ++dev->stats.rx_fifo_errors;
2905 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2906 }
2907
2908 if (status & GM_IS_TX_FF_UR) {
2909 ++dev->stats.tx_fifo_errors;
2910 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2911 }
2912}
2913
2914/* This should never happen it is a bug. */
2915static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2916{
2917 struct net_device *dev = hw->dev[port];
2918 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2919
2920 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2921 dev->name, (unsigned) q, (unsigned) idx,
2922 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2923
2924 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2925}
2926
2927static int sky2_rx_hung(struct net_device *dev)
2928{
2929 struct sky2_port *sky2 = netdev_priv(dev);
2930 struct sky2_hw *hw = sky2->hw;
2931 unsigned port = sky2->port;
2932 unsigned rxq = rxqaddr[port];
2933 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2934 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2935 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2936 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2937
2938 /* If idle and MAC or PCI is stuck */
2939 if (sky2->check.last == sky2->last_rx &&
2940 ((mac_rp == sky2->check.mac_rp &&
2941 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2942 /* Check if the PCI RX hang */
2943 (fifo_rp == sky2->check.fifo_rp &&
2944 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2945 netdev_printk(KERN_DEBUG, dev,
2946 "hung mac %d:%d fifo %d (%d:%d)\n",
2947 mac_lev, mac_rp, fifo_lev,
2948 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2949 return 1;
2950 } else {
2951 sky2->check.last = sky2->last_rx;
2952 sky2->check.mac_rp = mac_rp;
2953 sky2->check.mac_lev = mac_lev;
2954 sky2->check.fifo_rp = fifo_rp;
2955 sky2->check.fifo_lev = fifo_lev;
2956 return 0;
2957 }
2958}
2959
2960static void sky2_watchdog(struct timer_list *t)
2961{
2962 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer);
2963
2964 /* Check for lost IRQ once a second */
2965 if (sky2_read32(hw, B0_ISRC)) {
2966 napi_schedule(&hw->napi);
2967 } else {
2968 int i, active = 0;
2969
2970 for (i = 0; i < hw->ports; i++) {
2971 struct net_device *dev = hw->dev[i];
2972 if (!netif_running(dev))
2973 continue;
2974 ++active;
2975
2976 /* For chips with Rx FIFO, check if stuck */
2977 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2978 sky2_rx_hung(dev)) {
2979 netdev_info(dev, "receiver hang detected\n");
2980 schedule_work(&hw->restart_work);
2981 return;
2982 }
2983 }
2984
2985 if (active == 0)
2986 return;
2987 }
2988
2989 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2990}
2991
2992/* Hardware/software error handling */
2993static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2994{
2995 if (net_ratelimit())
2996 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2997
2998 if (status & Y2_IS_HW_ERR)
2999 sky2_hw_intr(hw);
3000
3001 if (status & Y2_IS_IRQ_MAC1)
3002 sky2_mac_intr(hw, 0);
3003
3004 if (status & Y2_IS_IRQ_MAC2)
3005 sky2_mac_intr(hw, 1);
3006
3007 if (status & Y2_IS_CHK_RX1)
3008 sky2_le_error(hw, 0, Q_R1);
3009
3010 if (status & Y2_IS_CHK_RX2)
3011 sky2_le_error(hw, 1, Q_R2);
3012
3013 if (status & Y2_IS_CHK_TXA1)
3014 sky2_le_error(hw, 0, Q_XA1);
3015
3016 if (status & Y2_IS_CHK_TXA2)
3017 sky2_le_error(hw, 1, Q_XA2);
3018}
3019
3020static int sky2_poll(struct napi_struct *napi, int work_limit)
3021{
3022 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3023 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3024 int work_done = 0;
3025 u16 idx;
3026
3027 if (unlikely(status & Y2_IS_ERROR))
3028 sky2_err_intr(hw, status);
3029
3030 if (status & Y2_IS_IRQ_PHY1)
3031 sky2_phy_intr(hw, 0);
3032
3033 if (status & Y2_IS_IRQ_PHY2)
3034 sky2_phy_intr(hw, 1);
3035
3036 if (status & Y2_IS_PHY_QLNK)
3037 sky2_qlink_intr(hw);
3038
3039 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3040 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3041
3042 if (work_done >= work_limit)
3043 goto done;
3044 }
3045
3046 napi_complete_done(napi, work_done);
3047 sky2_read32(hw, B0_Y2_SP_LISR);
3048done:
3049
3050 return work_done;
3051}
3052
3053static irqreturn_t sky2_intr(int irq, void *dev_id)
3054{
3055 struct sky2_hw *hw = dev_id;
3056 u32 status;
3057
3058 /* Reading this mask interrupts as side effect */
3059 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3060 if (status == 0 || status == ~0) {
3061 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3062 return IRQ_NONE;
3063 }
3064
3065 prefetch(&hw->st_le[hw->st_idx]);
3066
3067 napi_schedule(&hw->napi);
3068
3069 return IRQ_HANDLED;
3070}
3071
3072#ifdef CONFIG_NET_POLL_CONTROLLER
3073static void sky2_netpoll(struct net_device *dev)
3074{
3075 struct sky2_port *sky2 = netdev_priv(dev);
3076
3077 napi_schedule(&sky2->hw->napi);
3078}
3079#endif
3080
3081/* Chip internal frequency for clock calculations */
3082static u32 sky2_mhz(const struct sky2_hw *hw)
3083{
3084 switch (hw->chip_id) {
3085 case CHIP_ID_YUKON_EC:
3086 case CHIP_ID_YUKON_EC_U:
3087 case CHIP_ID_YUKON_EX:
3088 case CHIP_ID_YUKON_SUPR:
3089 case CHIP_ID_YUKON_UL_2:
3090 case CHIP_ID_YUKON_OPT:
3091 case CHIP_ID_YUKON_PRM:
3092 case CHIP_ID_YUKON_OP_2:
3093 return 125;
3094
3095 case CHIP_ID_YUKON_FE:
3096 return 100;
3097
3098 case CHIP_ID_YUKON_FE_P:
3099 return 50;
3100
3101 case CHIP_ID_YUKON_XL:
3102 return 156;
3103
3104 default:
3105 BUG();
3106 }
3107}
3108
3109static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3110{
3111 return sky2_mhz(hw) * us;
3112}
3113
3114static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3115{
3116 return clk / sky2_mhz(hw);
3117}
3118
3119
3120static int sky2_init(struct sky2_hw *hw)
3121{
3122 u8 t8;
3123
3124 /* Enable all clocks and check for bad PCI access */
3125 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3126
3127 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3128
3129 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3130 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3131
3132 switch (hw->chip_id) {
3133 case CHIP_ID_YUKON_XL:
3134 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3135 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3136 hw->flags |= SKY2_HW_RSS_BROKEN;
3137 break;
3138
3139 case CHIP_ID_YUKON_EC_U:
3140 hw->flags = SKY2_HW_GIGABIT
3141 | SKY2_HW_NEWER_PHY
3142 | SKY2_HW_ADV_POWER_CTL;
3143 break;
3144
3145 case CHIP_ID_YUKON_EX:
3146 hw->flags = SKY2_HW_GIGABIT
3147 | SKY2_HW_NEWER_PHY
3148 | SKY2_HW_NEW_LE
3149 | SKY2_HW_ADV_POWER_CTL
3150 | SKY2_HW_RSS_CHKSUM;
3151
3152 /* New transmit checksum */
3153 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3154 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3155 break;
3156
3157 case CHIP_ID_YUKON_EC:
3158 /* This rev is really old, and requires untested workarounds */
3159 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3160 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3161 return -EOPNOTSUPP;
3162 }
3163 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3164 break;
3165
3166 case CHIP_ID_YUKON_FE:
3167 hw->flags = SKY2_HW_RSS_BROKEN;
3168 break;
3169
3170 case CHIP_ID_YUKON_FE_P:
3171 hw->flags = SKY2_HW_NEWER_PHY
3172 | SKY2_HW_NEW_LE
3173 | SKY2_HW_AUTO_TX_SUM
3174 | SKY2_HW_ADV_POWER_CTL;
3175
3176 /* The workaround for status conflicts VLAN tag detection. */
3177 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3178 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3179 break;
3180
3181 case CHIP_ID_YUKON_SUPR:
3182 hw->flags = SKY2_HW_GIGABIT
3183 | SKY2_HW_NEWER_PHY
3184 | SKY2_HW_NEW_LE
3185 | SKY2_HW_AUTO_TX_SUM
3186 | SKY2_HW_ADV_POWER_CTL;
3187
3188 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3189 hw->flags |= SKY2_HW_RSS_CHKSUM;
3190 break;
3191
3192 case CHIP_ID_YUKON_UL_2:
3193 hw->flags = SKY2_HW_GIGABIT
3194 | SKY2_HW_ADV_POWER_CTL;
3195 break;
3196
3197 case CHIP_ID_YUKON_OPT:
3198 case CHIP_ID_YUKON_PRM:
3199 case CHIP_ID_YUKON_OP_2:
3200 hw->flags = SKY2_HW_GIGABIT
3201 | SKY2_HW_NEW_LE
3202 | SKY2_HW_ADV_POWER_CTL;
3203 break;
3204
3205 default:
3206 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3207 hw->chip_id);
3208 return -EOPNOTSUPP;
3209 }
3210
3211 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3212 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3213 hw->flags |= SKY2_HW_FIBRE_PHY;
3214
3215 hw->ports = 1;
3216 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3217 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3218 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3219 ++hw->ports;
3220 }
3221
3222 if (sky2_read8(hw, B2_E_0))
3223 hw->flags |= SKY2_HW_RAM_BUFFER;
3224
3225 return 0;
3226}
3227
3228static void sky2_reset(struct sky2_hw *hw)
3229{
3230 struct pci_dev *pdev = hw->pdev;
3231 u16 status;
3232 int i;
3233 u32 hwe_mask = Y2_HWE_ALL_MASK;
3234
3235 /* disable ASF */
3236 if (hw->chip_id == CHIP_ID_YUKON_EX
3237 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3238 sky2_write32(hw, CPU_WDOG, 0);
3239 status = sky2_read16(hw, HCU_CCSR);
3240 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3241 HCU_CCSR_UC_STATE_MSK);
3242 /*
3243 * CPU clock divider shouldn't be used because
3244 * - ASF firmware may malfunction
3245 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3246 */
3247 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3248 sky2_write16(hw, HCU_CCSR, status);
3249 sky2_write32(hw, CPU_WDOG, 0);
3250 } else
3251 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3252 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3253
3254 /* do a SW reset */
3255 sky2_write8(hw, B0_CTST, CS_RST_SET);
3256 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3257
3258 /* allow writes to PCI config */
3259 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3260
3261 /* clear PCI errors, if any */
3262 status = sky2_pci_read16(hw, PCI_STATUS);
3263 status |= PCI_STATUS_ERROR_BITS;
3264 sky2_pci_write16(hw, PCI_STATUS, status);
3265
3266 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3267
3268 if (pci_is_pcie(pdev)) {
3269 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3270 0xfffffffful);
3271
3272 /* If error bit is stuck on ignore it */
3273 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3274 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3275 else
3276 hwe_mask |= Y2_IS_PCI_EXP;
3277 }
3278
3279 sky2_power_on(hw);
3280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3281
3282 for (i = 0; i < hw->ports; i++) {
3283 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3284 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3285
3286 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3287 hw->chip_id == CHIP_ID_YUKON_SUPR)
3288 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3289 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3290 | GMC_BYP_RETR_ON);
3291
3292 }
3293
3294 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3295 /* enable MACSec clock gating */
3296 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3297 }
3298
3299 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3300 hw->chip_id == CHIP_ID_YUKON_PRM ||
3301 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3302 u16 reg;
3303
3304 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3305 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3306 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3307
3308 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3309 reg = 10;
3310
3311 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3312 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3313 } else {
3314 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3315 reg = 3;
3316 }
3317
3318 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3319 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3320
3321 /* reset PHY Link Detect */
3322 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3323 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3324
3325 /* check if PSMv2 was running before */
3326 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3327 if (reg & PCI_EXP_LNKCTL_ASPMC)
3328 /* restore the PCIe Link Control register */
3329 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3330 reg);
3331
3332 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3333 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3334 /* change PHY Interrupt polarity to low active */
3335 reg = sky2_read16(hw, GPHY_CTRL);
3336 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3337
3338 /* adapt HW for low active PHY Interrupt */
3339 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3340 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3341 }
3342
3343 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3344
3345 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3346 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3347 }
3348
3349 /* Clear I2C IRQ noise */
3350 sky2_write32(hw, B2_I2C_IRQ, 1);
3351
3352 /* turn off hardware timer (unused) */
3353 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3354 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3355
3356 /* Turn off descriptor polling */
3357 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3358
3359 /* Turn off receive timestamp */
3360 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3361 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3362
3363 /* enable the Tx Arbiters */
3364 for (i = 0; i < hw->ports; i++)
3365 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3366
3367 /* Initialize ram interface */
3368 for (i = 0; i < hw->ports; i++) {
3369 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3370
3371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3372 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3374 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3383 }
3384
3385 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3386
3387 for (i = 0; i < hw->ports; i++)
3388 sky2_gmac_reset(hw, i);
3389
3390 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3391 hw->st_idx = 0;
3392
3393 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3394 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3395
3396 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3397 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3398
3399 /* Set the list last index */
3400 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3401
3402 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3403 sky2_write8(hw, STAT_FIFO_WM, 16);
3404
3405 /* set Status-FIFO ISR watermark */
3406 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3407 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3408 else
3409 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3410
3411 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3412 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3413 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3414
3415 /* enable status unit */
3416 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3417
3418 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3419 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3420 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3421}
3422
3423/* Take device down (offline).
3424 * Equivalent to doing dev_stop() but this does not
3425 * inform upper layers of the transition.
3426 */
3427static void sky2_detach(struct net_device *dev)
3428{
3429 if (netif_running(dev)) {
3430 netif_tx_lock(dev);
3431 netif_device_detach(dev); /* stop txq */
3432 netif_tx_unlock(dev);
3433 sky2_close(dev);
3434 }
3435}
3436
3437/* Bring device back after doing sky2_detach */
3438static int sky2_reattach(struct net_device *dev)
3439{
3440 int err = 0;
3441
3442 if (netif_running(dev)) {
3443 err = sky2_open(dev);
3444 if (err) {
3445 netdev_info(dev, "could not restart %d\n", err);
3446 dev_close(dev);
3447 } else {
3448 netif_device_attach(dev);
3449 sky2_set_multicast(dev);
3450 }
3451 }
3452
3453 return err;
3454}
3455
3456static void sky2_all_down(struct sky2_hw *hw)
3457{
3458 int i;
3459
3460 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3461 sky2_write32(hw, B0_IMSK, 0);
3462 sky2_read32(hw, B0_IMSK);
3463
3464 synchronize_irq(hw->pdev->irq);
3465 napi_disable(&hw->napi);
3466 }
3467
3468 for (i = 0; i < hw->ports; i++) {
3469 struct net_device *dev = hw->dev[i];
3470 struct sky2_port *sky2 = netdev_priv(dev);
3471
3472 if (!netif_running(dev))
3473 continue;
3474
3475 netif_carrier_off(dev);
3476 netif_tx_disable(dev);
3477 sky2_hw_down(sky2);
3478 }
3479}
3480
3481static void sky2_all_up(struct sky2_hw *hw)
3482{
3483 u32 imask = Y2_IS_BASE;
3484 int i;
3485
3486 for (i = 0; i < hw->ports; i++) {
3487 struct net_device *dev = hw->dev[i];
3488 struct sky2_port *sky2 = netdev_priv(dev);
3489
3490 if (!netif_running(dev))
3491 continue;
3492
3493 sky2_hw_up(sky2);
3494 sky2_set_multicast(dev);
3495 imask |= portirq_msk[i];
3496 netif_wake_queue(dev);
3497 }
3498
3499 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3500 sky2_write32(hw, B0_IMSK, imask);
3501 sky2_read32(hw, B0_IMSK);
3502 sky2_read32(hw, B0_Y2_SP_LISR);
3503 napi_enable(&hw->napi);
3504 }
3505}
3506
3507static void sky2_restart(struct work_struct *work)
3508{
3509 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3510
3511 rtnl_lock();
3512
3513 sky2_all_down(hw);
3514 sky2_reset(hw);
3515 sky2_all_up(hw);
3516
3517 rtnl_unlock();
3518}
3519
3520static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3521{
3522 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3523}
3524
3525static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3526{
3527 const struct sky2_port *sky2 = netdev_priv(dev);
3528
3529 wol->supported = sky2_wol_supported(sky2->hw);
3530 wol->wolopts = sky2->wol;
3531}
3532
3533static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3534{
3535 struct sky2_port *sky2 = netdev_priv(dev);
3536 struct sky2_hw *hw = sky2->hw;
3537 bool enable_wakeup = false;
3538 int i;
3539
3540 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3541 !device_can_wakeup(&hw->pdev->dev))
3542 return -EOPNOTSUPP;
3543
3544 sky2->wol = wol->wolopts;
3545
3546 for (i = 0; i < hw->ports; i++) {
3547 struct net_device *dev = hw->dev[i];
3548 struct sky2_port *sky2 = netdev_priv(dev);
3549
3550 if (sky2->wol)
3551 enable_wakeup = true;
3552 }
3553 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3554
3555 return 0;
3556}
3557
3558static u32 sky2_supported_modes(const struct sky2_hw *hw)
3559{
3560 if (sky2_is_copper(hw)) {
3561 u32 modes = SUPPORTED_10baseT_Half
3562 | SUPPORTED_10baseT_Full
3563 | SUPPORTED_100baseT_Half
3564 | SUPPORTED_100baseT_Full;
3565
3566 if (hw->flags & SKY2_HW_GIGABIT)
3567 modes |= SUPPORTED_1000baseT_Half
3568 | SUPPORTED_1000baseT_Full;
3569 return modes;
3570 } else
3571 return SUPPORTED_1000baseT_Half
3572 | SUPPORTED_1000baseT_Full;
3573}
3574
3575static int sky2_get_link_ksettings(struct net_device *dev,
3576 struct ethtool_link_ksettings *cmd)
3577{
3578 struct sky2_port *sky2 = netdev_priv(dev);
3579 struct sky2_hw *hw = sky2->hw;
3580 u32 supported, advertising;
3581
3582 supported = sky2_supported_modes(hw);
3583 cmd->base.phy_address = PHY_ADDR_MARV;
3584 if (sky2_is_copper(hw)) {
3585 cmd->base.port = PORT_TP;
3586 cmd->base.speed = sky2->speed;
3587 supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3588 } else {
3589 cmd->base.speed = SPEED_1000;
3590 cmd->base.port = PORT_FIBRE;
3591 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3592 }
3593
3594 advertising = sky2->advertising;
3595 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3596 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3597 cmd->base.duplex = sky2->duplex;
3598
3599 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3600 supported);
3601 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3602 advertising);
3603
3604 return 0;
3605}
3606
3607static int sky2_set_link_ksettings(struct net_device *dev,
3608 const struct ethtool_link_ksettings *cmd)
3609{
3610 struct sky2_port *sky2 = netdev_priv(dev);
3611 const struct sky2_hw *hw = sky2->hw;
3612 u32 supported = sky2_supported_modes(hw);
3613 u32 new_advertising;
3614
3615 ethtool_convert_link_mode_to_legacy_u32(&new_advertising,
3616 cmd->link_modes.advertising);
3617
3618 if (cmd->base.autoneg == AUTONEG_ENABLE) {
3619 if (new_advertising & ~supported)
3620 return -EINVAL;
3621
3622 if (sky2_is_copper(hw))
3623 sky2->advertising = new_advertising |
3624 ADVERTISED_TP |
3625 ADVERTISED_Autoneg;
3626 else
3627 sky2->advertising = new_advertising |
3628 ADVERTISED_FIBRE |
3629 ADVERTISED_Autoneg;
3630
3631 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3632 sky2->duplex = -1;
3633 sky2->speed = -1;
3634 } else {
3635 u32 setting;
3636 u32 speed = cmd->base.speed;
3637
3638 switch (speed) {
3639 case SPEED_1000:
3640 if (cmd->base.duplex == DUPLEX_FULL)
3641 setting = SUPPORTED_1000baseT_Full;
3642 else if (cmd->base.duplex == DUPLEX_HALF)
3643 setting = SUPPORTED_1000baseT_Half;
3644 else
3645 return -EINVAL;
3646 break;
3647 case SPEED_100:
3648 if (cmd->base.duplex == DUPLEX_FULL)
3649 setting = SUPPORTED_100baseT_Full;
3650 else if (cmd->base.duplex == DUPLEX_HALF)
3651 setting = SUPPORTED_100baseT_Half;
3652 else
3653 return -EINVAL;
3654 break;
3655
3656 case SPEED_10:
3657 if (cmd->base.duplex == DUPLEX_FULL)
3658 setting = SUPPORTED_10baseT_Full;
3659 else if (cmd->base.duplex == DUPLEX_HALF)
3660 setting = SUPPORTED_10baseT_Half;
3661 else
3662 return -EINVAL;
3663 break;
3664 default:
3665 return -EINVAL;
3666 }
3667
3668 if ((setting & supported) == 0)
3669 return -EINVAL;
3670
3671 sky2->speed = speed;
3672 sky2->duplex = cmd->base.duplex;
3673 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3674 }
3675
3676 if (netif_running(dev)) {
3677 sky2_phy_reinit(sky2);
3678 sky2_set_multicast(dev);
3679 }
3680
3681 return 0;
3682}
3683
3684static void sky2_get_drvinfo(struct net_device *dev,
3685 struct ethtool_drvinfo *info)
3686{
3687 struct sky2_port *sky2 = netdev_priv(dev);
3688
3689 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
3690 strscpy(info->version, DRV_VERSION, sizeof(info->version));
3691 strscpy(info->bus_info, pci_name(sky2->hw->pdev),
3692 sizeof(info->bus_info));
3693}
3694
3695static const struct sky2_stat {
3696 char name[ETH_GSTRING_LEN];
3697 u16 offset;
3698} sky2_stats[] = {
3699 { "tx_bytes", GM_TXO_OK_HI },
3700 { "rx_bytes", GM_RXO_OK_HI },
3701 { "tx_broadcast", GM_TXF_BC_OK },
3702 { "rx_broadcast", GM_RXF_BC_OK },
3703 { "tx_multicast", GM_TXF_MC_OK },
3704 { "rx_multicast", GM_RXF_MC_OK },
3705 { "tx_unicast", GM_TXF_UC_OK },
3706 { "rx_unicast", GM_RXF_UC_OK },
3707 { "tx_mac_pause", GM_TXF_MPAUSE },
3708 { "rx_mac_pause", GM_RXF_MPAUSE },
3709 { "collisions", GM_TXF_COL },
3710 { "late_collision",GM_TXF_LAT_COL },
3711 { "aborted", GM_TXF_ABO_COL },
3712 { "single_collisions", GM_TXF_SNG_COL },
3713 { "multi_collisions", GM_TXF_MUL_COL },
3714
3715 { "rx_short", GM_RXF_SHT },
3716 { "rx_runt", GM_RXE_FRAG },
3717 { "rx_64_byte_packets", GM_RXF_64B },
3718 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3719 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3720 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3721 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3722 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3723 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3724 { "rx_too_long", GM_RXF_LNG_ERR },
3725 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3726 { "rx_jabber", GM_RXF_JAB_PKT },
3727 { "rx_fcs_error", GM_RXF_FCS_ERR },
3728
3729 { "tx_64_byte_packets", GM_TXF_64B },
3730 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3731 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3732 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3733 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3734 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3735 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3736 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3737};
3738
3739static u32 sky2_get_msglevel(struct net_device *netdev)
3740{
3741 struct sky2_port *sky2 = netdev_priv(netdev);
3742 return sky2->msg_enable;
3743}
3744
3745static int sky2_nway_reset(struct net_device *dev)
3746{
3747 struct sky2_port *sky2 = netdev_priv(dev);
3748
3749 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3750 return -EINVAL;
3751
3752 sky2_phy_reinit(sky2);
3753 sky2_set_multicast(dev);
3754
3755 return 0;
3756}
3757
3758static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3759{
3760 struct sky2_hw *hw = sky2->hw;
3761 unsigned port = sky2->port;
3762 int i;
3763
3764 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3765 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3766
3767 for (i = 2; i < count; i++)
3768 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3769}
3770
3771static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3772{
3773 struct sky2_port *sky2 = netdev_priv(netdev);
3774 sky2->msg_enable = value;
3775}
3776
3777static int sky2_get_sset_count(struct net_device *dev, int sset)
3778{
3779 switch (sset) {
3780 case ETH_SS_STATS:
3781 return ARRAY_SIZE(sky2_stats);
3782 default:
3783 return -EOPNOTSUPP;
3784 }
3785}
3786
3787static void sky2_get_ethtool_stats(struct net_device *dev,
3788 struct ethtool_stats *stats, u64 * data)
3789{
3790 struct sky2_port *sky2 = netdev_priv(dev);
3791
3792 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3793}
3794
3795static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3796{
3797 int i;
3798
3799 switch (stringset) {
3800 case ETH_SS_STATS:
3801 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3802 memcpy(data + i * ETH_GSTRING_LEN,
3803 sky2_stats[i].name, ETH_GSTRING_LEN);
3804 break;
3805 }
3806}
3807
3808static int sky2_set_mac_address(struct net_device *dev, void *p)
3809{
3810 struct sky2_port *sky2 = netdev_priv(dev);
3811 struct sky2_hw *hw = sky2->hw;
3812 unsigned port = sky2->port;
3813 const struct sockaddr *addr = p;
3814
3815 if (!is_valid_ether_addr(addr->sa_data))
3816 return -EADDRNOTAVAIL;
3817
3818 eth_hw_addr_set(dev, addr->sa_data);
3819 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3820 dev->dev_addr, ETH_ALEN);
3821 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3822 dev->dev_addr, ETH_ALEN);
3823
3824 /* virtual address for data */
3825 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3826
3827 /* physical address: used for pause frames */
3828 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3829
3830 return 0;
3831}
3832
3833static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3834{
3835 u32 bit;
3836
3837 bit = ether_crc(ETH_ALEN, addr) & 63;
3838 filter[bit >> 3] |= 1 << (bit & 7);
3839}
3840
3841static void sky2_set_multicast(struct net_device *dev)
3842{
3843 struct sky2_port *sky2 = netdev_priv(dev);
3844 struct sky2_hw *hw = sky2->hw;
3845 unsigned port = sky2->port;
3846 struct netdev_hw_addr *ha;
3847 u16 reg;
3848 u8 filter[8];
3849 int rx_pause;
3850 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3851
3852 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3853 memset(filter, 0, sizeof(filter));
3854
3855 reg = gma_read16(hw, port, GM_RX_CTRL);
3856 reg |= GM_RXCR_UCF_ENA;
3857
3858 if (dev->flags & IFF_PROMISC) /* promiscuous */
3859 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3860 else if (dev->flags & IFF_ALLMULTI)
3861 memset(filter, 0xff, sizeof(filter));
3862 else if (netdev_mc_empty(dev) && !rx_pause)
3863 reg &= ~GM_RXCR_MCF_ENA;
3864 else {
3865 reg |= GM_RXCR_MCF_ENA;
3866
3867 if (rx_pause)
3868 sky2_add_filter(filter, pause_mc_addr);
3869
3870 netdev_for_each_mc_addr(ha, dev)
3871 sky2_add_filter(filter, ha->addr);
3872 }
3873
3874 gma_write16(hw, port, GM_MC_ADDR_H1,
3875 (u16) filter[0] | ((u16) filter[1] << 8));
3876 gma_write16(hw, port, GM_MC_ADDR_H2,
3877 (u16) filter[2] | ((u16) filter[3] << 8));
3878 gma_write16(hw, port, GM_MC_ADDR_H3,
3879 (u16) filter[4] | ((u16) filter[5] << 8));
3880 gma_write16(hw, port, GM_MC_ADDR_H4,
3881 (u16) filter[6] | ((u16) filter[7] << 8));
3882
3883 gma_write16(hw, port, GM_RX_CTRL, reg);
3884}
3885
3886static void sky2_get_stats(struct net_device *dev,
3887 struct rtnl_link_stats64 *stats)
3888{
3889 struct sky2_port *sky2 = netdev_priv(dev);
3890 struct sky2_hw *hw = sky2->hw;
3891 unsigned port = sky2->port;
3892 unsigned int start;
3893 u64 _bytes, _packets;
3894
3895 do {
3896 start = u64_stats_fetch_begin(&sky2->rx_stats.syncp);
3897 _bytes = sky2->rx_stats.bytes;
3898 _packets = sky2->rx_stats.packets;
3899 } while (u64_stats_fetch_retry(&sky2->rx_stats.syncp, start));
3900
3901 stats->rx_packets = _packets;
3902 stats->rx_bytes = _bytes;
3903
3904 do {
3905 start = u64_stats_fetch_begin(&sky2->tx_stats.syncp);
3906 _bytes = sky2->tx_stats.bytes;
3907 _packets = sky2->tx_stats.packets;
3908 } while (u64_stats_fetch_retry(&sky2->tx_stats.syncp, start));
3909
3910 stats->tx_packets = _packets;
3911 stats->tx_bytes = _bytes;
3912
3913 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3914 + get_stats32(hw, port, GM_RXF_BC_OK);
3915
3916 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3917
3918 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3919 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3920 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3921 + get_stats32(hw, port, GM_RXE_FRAG);
3922 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3923
3924 stats->rx_dropped = dev->stats.rx_dropped;
3925 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3926 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3927}
3928
3929/* Can have one global because blinking is controlled by
3930 * ethtool and that is always under RTNL mutex
3931 */
3932static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3933{
3934 struct sky2_hw *hw = sky2->hw;
3935 unsigned port = sky2->port;
3936
3937 spin_lock_bh(&sky2->phy_lock);
3938 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3939 hw->chip_id == CHIP_ID_YUKON_EX ||
3940 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3941 u16 pg;
3942 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3943 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3944
3945 switch (mode) {
3946 case MO_LED_OFF:
3947 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3948 PHY_M_LEDC_LOS_CTRL(8) |
3949 PHY_M_LEDC_INIT_CTRL(8) |
3950 PHY_M_LEDC_STA1_CTRL(8) |
3951 PHY_M_LEDC_STA0_CTRL(8));
3952 break;
3953 case MO_LED_ON:
3954 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3955 PHY_M_LEDC_LOS_CTRL(9) |
3956 PHY_M_LEDC_INIT_CTRL(9) |
3957 PHY_M_LEDC_STA1_CTRL(9) |
3958 PHY_M_LEDC_STA0_CTRL(9));
3959 break;
3960 case MO_LED_BLINK:
3961 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3962 PHY_M_LEDC_LOS_CTRL(0xa) |
3963 PHY_M_LEDC_INIT_CTRL(0xa) |
3964 PHY_M_LEDC_STA1_CTRL(0xa) |
3965 PHY_M_LEDC_STA0_CTRL(0xa));
3966 break;
3967 case MO_LED_NORM:
3968 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3969 PHY_M_LEDC_LOS_CTRL(1) |
3970 PHY_M_LEDC_INIT_CTRL(8) |
3971 PHY_M_LEDC_STA1_CTRL(7) |
3972 PHY_M_LEDC_STA0_CTRL(7));
3973 }
3974
3975 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3976 } else
3977 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3978 PHY_M_LED_MO_DUP(mode) |
3979 PHY_M_LED_MO_10(mode) |
3980 PHY_M_LED_MO_100(mode) |
3981 PHY_M_LED_MO_1000(mode) |
3982 PHY_M_LED_MO_RX(mode) |
3983 PHY_M_LED_MO_TX(mode));
3984
3985 spin_unlock_bh(&sky2->phy_lock);
3986}
3987
3988/* blink LED's for finding board */
3989static int sky2_set_phys_id(struct net_device *dev,
3990 enum ethtool_phys_id_state state)
3991{
3992 struct sky2_port *sky2 = netdev_priv(dev);
3993
3994 switch (state) {
3995 case ETHTOOL_ID_ACTIVE:
3996 return 1; /* cycle on/off once per second */
3997 case ETHTOOL_ID_INACTIVE:
3998 sky2_led(sky2, MO_LED_NORM);
3999 break;
4000 case ETHTOOL_ID_ON:
4001 sky2_led(sky2, MO_LED_ON);
4002 break;
4003 case ETHTOOL_ID_OFF:
4004 sky2_led(sky2, MO_LED_OFF);
4005 break;
4006 }
4007
4008 return 0;
4009}
4010
4011static void sky2_get_pauseparam(struct net_device *dev,
4012 struct ethtool_pauseparam *ecmd)
4013{
4014 struct sky2_port *sky2 = netdev_priv(dev);
4015
4016 switch (sky2->flow_mode) {
4017 case FC_NONE:
4018 ecmd->tx_pause = ecmd->rx_pause = 0;
4019 break;
4020 case FC_TX:
4021 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4022 break;
4023 case FC_RX:
4024 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4025 break;
4026 case FC_BOTH:
4027 ecmd->tx_pause = ecmd->rx_pause = 1;
4028 }
4029
4030 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4031 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4032}
4033
4034static int sky2_set_pauseparam(struct net_device *dev,
4035 struct ethtool_pauseparam *ecmd)
4036{
4037 struct sky2_port *sky2 = netdev_priv(dev);
4038
4039 if (ecmd->autoneg == AUTONEG_ENABLE)
4040 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4041 else
4042 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4043
4044 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4045
4046 if (netif_running(dev))
4047 sky2_phy_reinit(sky2);
4048
4049 return 0;
4050}
4051
4052static int sky2_get_coalesce(struct net_device *dev,
4053 struct ethtool_coalesce *ecmd,
4054 struct kernel_ethtool_coalesce *kernel_coal,
4055 struct netlink_ext_ack *extack)
4056{
4057 struct sky2_port *sky2 = netdev_priv(dev);
4058 struct sky2_hw *hw = sky2->hw;
4059
4060 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4061 ecmd->tx_coalesce_usecs = 0;
4062 else {
4063 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4064 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4065 }
4066 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4067
4068 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4069 ecmd->rx_coalesce_usecs = 0;
4070 else {
4071 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4072 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4073 }
4074 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4075
4076 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4077 ecmd->rx_coalesce_usecs_irq = 0;
4078 else {
4079 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4080 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4081 }
4082
4083 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4084
4085 return 0;
4086}
4087
4088/* Note: this affect both ports */
4089static int sky2_set_coalesce(struct net_device *dev,
4090 struct ethtool_coalesce *ecmd,
4091 struct kernel_ethtool_coalesce *kernel_coal,
4092 struct netlink_ext_ack *extack)
4093{
4094 struct sky2_port *sky2 = netdev_priv(dev);
4095 struct sky2_hw *hw = sky2->hw;
4096 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4097
4098 if (ecmd->tx_coalesce_usecs > tmax ||
4099 ecmd->rx_coalesce_usecs > tmax ||
4100 ecmd->rx_coalesce_usecs_irq > tmax)
4101 return -EINVAL;
4102
4103 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4104 return -EINVAL;
4105 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4106 return -EINVAL;
4107 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4108 return -EINVAL;
4109
4110 if (ecmd->tx_coalesce_usecs == 0)
4111 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4112 else {
4113 sky2_write32(hw, STAT_TX_TIMER_INI,
4114 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4115 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4116 }
4117 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4118
4119 if (ecmd->rx_coalesce_usecs == 0)
4120 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4121 else {
4122 sky2_write32(hw, STAT_LEV_TIMER_INI,
4123 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4124 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4125 }
4126 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4127
4128 if (ecmd->rx_coalesce_usecs_irq == 0)
4129 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4130 else {
4131 sky2_write32(hw, STAT_ISR_TIMER_INI,
4132 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4133 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4134 }
4135 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4136 return 0;
4137}
4138
4139/*
4140 * Hardware is limited to min of 128 and max of 2048 for ring size
4141 * and rounded up to next power of two
4142 * to avoid division in modulus calculation
4143 */
4144static unsigned long roundup_ring_size(unsigned long pending)
4145{
4146 return max(128ul, roundup_pow_of_two(pending+1));
4147}
4148
4149static void sky2_get_ringparam(struct net_device *dev,
4150 struct ethtool_ringparam *ering,
4151 struct kernel_ethtool_ringparam *kernel_ering,
4152 struct netlink_ext_ack *extack)
4153{
4154 struct sky2_port *sky2 = netdev_priv(dev);
4155
4156 ering->rx_max_pending = RX_MAX_PENDING;
4157 ering->tx_max_pending = TX_MAX_PENDING;
4158
4159 ering->rx_pending = sky2->rx_pending;
4160 ering->tx_pending = sky2->tx_pending;
4161}
4162
4163static int sky2_set_ringparam(struct net_device *dev,
4164 struct ethtool_ringparam *ering,
4165 struct kernel_ethtool_ringparam *kernel_ering,
4166 struct netlink_ext_ack *extack)
4167{
4168 struct sky2_port *sky2 = netdev_priv(dev);
4169
4170 if (ering->rx_pending > RX_MAX_PENDING ||
4171 ering->rx_pending < 8 ||
4172 ering->tx_pending < TX_MIN_PENDING ||
4173 ering->tx_pending > TX_MAX_PENDING)
4174 return -EINVAL;
4175
4176 sky2_detach(dev);
4177
4178 sky2->rx_pending = ering->rx_pending;
4179 sky2->tx_pending = ering->tx_pending;
4180 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4181
4182 return sky2_reattach(dev);
4183}
4184
4185static int sky2_get_regs_len(struct net_device *dev)
4186{
4187 return 0x4000;
4188}
4189
4190static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4191{
4192 /* This complicated switch statement is to make sure and
4193 * only access regions that are unreserved.
4194 * Some blocks are only valid on dual port cards.
4195 */
4196 switch (b) {
4197 /* second port */
4198 case 5: /* Tx Arbiter 2 */
4199 case 9: /* RX2 */
4200 case 14 ... 15: /* TX2 */
4201 case 17: case 19: /* Ram Buffer 2 */
4202 case 22 ... 23: /* Tx Ram Buffer 2 */
4203 case 25: /* Rx MAC Fifo 1 */
4204 case 27: /* Tx MAC Fifo 2 */
4205 case 31: /* GPHY 2 */
4206 case 40 ... 47: /* Pattern Ram 2 */
4207 case 52: case 54: /* TCP Segmentation 2 */
4208 case 112 ... 116: /* GMAC 2 */
4209 return hw->ports > 1;
4210
4211 case 0: /* Control */
4212 case 2: /* Mac address */
4213 case 4: /* Tx Arbiter 1 */
4214 case 7: /* PCI express reg */
4215 case 8: /* RX1 */
4216 case 12 ... 13: /* TX1 */
4217 case 16: case 18:/* Rx Ram Buffer 1 */
4218 case 20 ... 21: /* Tx Ram Buffer 1 */
4219 case 24: /* Rx MAC Fifo 1 */
4220 case 26: /* Tx MAC Fifo 1 */
4221 case 28 ... 29: /* Descriptor and status unit */
4222 case 30: /* GPHY 1*/
4223 case 32 ... 39: /* Pattern Ram 1 */
4224 case 48: case 50: /* TCP Segmentation 1 */
4225 case 56 ... 60: /* PCI space */
4226 case 80 ... 84: /* GMAC 1 */
4227 return 1;
4228
4229 default:
4230 return 0;
4231 }
4232}
4233
4234/*
4235 * Returns copy of control register region
4236 * Note: ethtool_get_regs always provides full size (16k) buffer
4237 */
4238static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4239 void *p)
4240{
4241 const struct sky2_port *sky2 = netdev_priv(dev);
4242 const void __iomem *io = sky2->hw->regs;
4243 unsigned int b;
4244
4245 regs->version = 1;
4246
4247 for (b = 0; b < 128; b++) {
4248 /* skip poisonous diagnostic ram region in block 3 */
4249 if (b == 3)
4250 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4251 else if (sky2_reg_access_ok(sky2->hw, b))
4252 memcpy_fromio(p, io, 128);
4253 else
4254 memset(p, 0, 128);
4255
4256 p += 128;
4257 io += 128;
4258 }
4259}
4260
4261static int sky2_get_eeprom_len(struct net_device *dev)
4262{
4263 struct sky2_port *sky2 = netdev_priv(dev);
4264 struct sky2_hw *hw = sky2->hw;
4265 u16 reg2;
4266
4267 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4268 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4269}
4270
4271static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4272 u8 *data)
4273{
4274 struct sky2_port *sky2 = netdev_priv(dev);
4275 int rc;
4276
4277 eeprom->magic = SKY2_EEPROM_MAGIC;
4278 rc = pci_read_vpd_any(sky2->hw->pdev, eeprom->offset, eeprom->len,
4279 data);
4280 if (rc < 0)
4281 return rc;
4282
4283 eeprom->len = rc;
4284
4285 return 0;
4286}
4287
4288static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4289 u8 *data)
4290{
4291 struct sky2_port *sky2 = netdev_priv(dev);
4292 int rc;
4293
4294 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4295 return -EINVAL;
4296
4297 rc = pci_write_vpd_any(sky2->hw->pdev, eeprom->offset, eeprom->len,
4298 data);
4299
4300 return rc < 0 ? rc : 0;
4301}
4302
4303static netdev_features_t sky2_fix_features(struct net_device *dev,
4304 netdev_features_t features)
4305{
4306 const struct sky2_port *sky2 = netdev_priv(dev);
4307 const struct sky2_hw *hw = sky2->hw;
4308
4309 /* In order to do Jumbo packets on these chips, need to turn off the
4310 * transmit store/forward. Therefore checksum offload won't work.
4311 */
4312 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4313 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4314 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4315 }
4316
4317 /* Some hardware requires receive checksum for RSS to work. */
4318 if ( (features & NETIF_F_RXHASH) &&
4319 !(features & NETIF_F_RXCSUM) &&
4320 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4321 netdev_info(dev, "receive hashing forces receive checksum\n");
4322 features |= NETIF_F_RXCSUM;
4323 }
4324
4325 return features;
4326}
4327
4328static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4329{
4330 struct sky2_port *sky2 = netdev_priv(dev);
4331 netdev_features_t changed = dev->features ^ features;
4332
4333 if ((changed & NETIF_F_RXCSUM) &&
4334 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4335 sky2_write32(sky2->hw,
4336 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4337 (features & NETIF_F_RXCSUM)
4338 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4339 }
4340
4341 if (changed & NETIF_F_RXHASH)
4342 rx_set_rss(dev, features);
4343
4344 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4345 sky2_vlan_mode(dev, features);
4346
4347 return 0;
4348}
4349
4350static const struct ethtool_ops sky2_ethtool_ops = {
4351 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4352 ETHTOOL_COALESCE_MAX_FRAMES |
4353 ETHTOOL_COALESCE_RX_USECS_IRQ |
4354 ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ,
4355 .get_drvinfo = sky2_get_drvinfo,
4356 .get_wol = sky2_get_wol,
4357 .set_wol = sky2_set_wol,
4358 .get_msglevel = sky2_get_msglevel,
4359 .set_msglevel = sky2_set_msglevel,
4360 .nway_reset = sky2_nway_reset,
4361 .get_regs_len = sky2_get_regs_len,
4362 .get_regs = sky2_get_regs,
4363 .get_link = ethtool_op_get_link,
4364 .get_eeprom_len = sky2_get_eeprom_len,
4365 .get_eeprom = sky2_get_eeprom,
4366 .set_eeprom = sky2_set_eeprom,
4367 .get_strings = sky2_get_strings,
4368 .get_coalesce = sky2_get_coalesce,
4369 .set_coalesce = sky2_set_coalesce,
4370 .get_ringparam = sky2_get_ringparam,
4371 .set_ringparam = sky2_set_ringparam,
4372 .get_pauseparam = sky2_get_pauseparam,
4373 .set_pauseparam = sky2_set_pauseparam,
4374 .set_phys_id = sky2_set_phys_id,
4375 .get_sset_count = sky2_get_sset_count,
4376 .get_ethtool_stats = sky2_get_ethtool_stats,
4377 .get_link_ksettings = sky2_get_link_ksettings,
4378 .set_link_ksettings = sky2_set_link_ksettings,
4379};
4380
4381#ifdef CONFIG_SKY2_DEBUG
4382
4383static struct dentry *sky2_debug;
4384
4385static int sky2_debug_show(struct seq_file *seq, void *v)
4386{
4387 struct net_device *dev = seq->private;
4388 const struct sky2_port *sky2 = netdev_priv(dev);
4389 struct sky2_hw *hw = sky2->hw;
4390 unsigned port = sky2->port;
4391 unsigned idx, last;
4392 int sop;
4393
4394 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
4395 sky2_read32(hw, B0_ISRC),
4396 sky2_read32(hw, B0_IMSK),
4397 sky2_read32(hw, B0_Y2_SP_ICR));
4398
4399 if (!netif_running(dev)) {
4400 seq_puts(seq, "network not running\n");
4401 return 0;
4402 }
4403
4404 napi_disable(&hw->napi);
4405 last = sky2_read16(hw, STAT_PUT_IDX);
4406
4407 seq_printf(seq, "Status ring %u\n", hw->st_size);
4408 if (hw->st_idx == last)
4409 seq_puts(seq, "Status ring (empty)\n");
4410 else {
4411 seq_puts(seq, "Status ring\n");
4412 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4413 idx = RING_NEXT(idx, hw->st_size)) {
4414 const struct sky2_status_le *le = hw->st_le + idx;
4415 seq_printf(seq, "[%d] %#x %d %#x\n",
4416 idx, le->opcode, le->length, le->status);
4417 }
4418 seq_puts(seq, "\n");
4419 }
4420
4421 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4422 sky2->tx_cons, sky2->tx_prod,
4423 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4424 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4425
4426 /* Dump contents of tx ring */
4427 sop = 1;
4428 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4429 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4430 const struct sky2_tx_le *le = sky2->tx_le + idx;
4431 u32 a = le32_to_cpu(le->addr);
4432
4433 if (sop)
4434 seq_printf(seq, "%u:", idx);
4435 sop = 0;
4436
4437 switch (le->opcode & ~HW_OWNER) {
4438 case OP_ADDR64:
4439 seq_printf(seq, " %#x:", a);
4440 break;
4441 case OP_LRGLEN:
4442 seq_printf(seq, " mtu=%d", a);
4443 break;
4444 case OP_VLAN:
4445 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4446 break;
4447 case OP_TCPLISW:
4448 seq_printf(seq, " csum=%#x", a);
4449 break;
4450 case OP_LARGESEND:
4451 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4452 break;
4453 case OP_PACKET:
4454 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4455 break;
4456 case OP_BUFFER:
4457 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4458 break;
4459 default:
4460 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4461 a, le16_to_cpu(le->length));
4462 }
4463
4464 if (le->ctrl & EOP) {
4465 seq_putc(seq, '\n');
4466 sop = 1;
4467 }
4468 }
4469
4470 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4471 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4472 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4473 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4474
4475 sky2_read32(hw, B0_Y2_SP_LISR);
4476 napi_enable(&hw->napi);
4477 return 0;
4478}
4479DEFINE_SHOW_ATTRIBUTE(sky2_debug);
4480
4481/*
4482 * Use network device events to create/remove/rename
4483 * debugfs file entries
4484 */
4485static int sky2_device_event(struct notifier_block *unused,
4486 unsigned long event, void *ptr)
4487{
4488 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4489 struct sky2_port *sky2 = netdev_priv(dev);
4490
4491 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4492 return NOTIFY_DONE;
4493
4494 switch (event) {
4495 case NETDEV_CHANGENAME:
4496 if (sky2->debugfs) {
4497 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4498 sky2_debug, dev->name);
4499 }
4500 break;
4501
4502 case NETDEV_GOING_DOWN:
4503 if (sky2->debugfs) {
4504 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4505 debugfs_remove(sky2->debugfs);
4506 sky2->debugfs = NULL;
4507 }
4508 break;
4509
4510 case NETDEV_UP:
4511 sky2->debugfs = debugfs_create_file(dev->name, 0444,
4512 sky2_debug, dev,
4513 &sky2_debug_fops);
4514 if (IS_ERR(sky2->debugfs))
4515 sky2->debugfs = NULL;
4516 }
4517
4518 return NOTIFY_DONE;
4519}
4520
4521static struct notifier_block sky2_notifier = {
4522 .notifier_call = sky2_device_event,
4523};
4524
4525
4526static __init void sky2_debug_init(void)
4527{
4528 struct dentry *ent;
4529
4530 ent = debugfs_create_dir("sky2", NULL);
4531 if (IS_ERR(ent))
4532 return;
4533
4534 sky2_debug = ent;
4535 register_netdevice_notifier(&sky2_notifier);
4536}
4537
4538static __exit void sky2_debug_cleanup(void)
4539{
4540 if (sky2_debug) {
4541 unregister_netdevice_notifier(&sky2_notifier);
4542 debugfs_remove(sky2_debug);
4543 sky2_debug = NULL;
4544 }
4545}
4546
4547#else
4548#define sky2_debug_init()
4549#define sky2_debug_cleanup()
4550#endif
4551
4552/* Two copies of network device operations to handle special case of
4553 * not allowing netpoll on second port
4554 */
4555static const struct net_device_ops sky2_netdev_ops[2] = {
4556 {
4557 .ndo_open = sky2_open,
4558 .ndo_stop = sky2_close,
4559 .ndo_start_xmit = sky2_xmit_frame,
4560 .ndo_eth_ioctl = sky2_ioctl,
4561 .ndo_validate_addr = eth_validate_addr,
4562 .ndo_set_mac_address = sky2_set_mac_address,
4563 .ndo_set_rx_mode = sky2_set_multicast,
4564 .ndo_change_mtu = sky2_change_mtu,
4565 .ndo_fix_features = sky2_fix_features,
4566 .ndo_set_features = sky2_set_features,
4567 .ndo_tx_timeout = sky2_tx_timeout,
4568 .ndo_get_stats64 = sky2_get_stats,
4569#ifdef CONFIG_NET_POLL_CONTROLLER
4570 .ndo_poll_controller = sky2_netpoll,
4571#endif
4572 },
4573 {
4574 .ndo_open = sky2_open,
4575 .ndo_stop = sky2_close,
4576 .ndo_start_xmit = sky2_xmit_frame,
4577 .ndo_eth_ioctl = sky2_ioctl,
4578 .ndo_validate_addr = eth_validate_addr,
4579 .ndo_set_mac_address = sky2_set_mac_address,
4580 .ndo_set_rx_mode = sky2_set_multicast,
4581 .ndo_change_mtu = sky2_change_mtu,
4582 .ndo_fix_features = sky2_fix_features,
4583 .ndo_set_features = sky2_set_features,
4584 .ndo_tx_timeout = sky2_tx_timeout,
4585 .ndo_get_stats64 = sky2_get_stats,
4586 },
4587};
4588
4589/* Initialize network device */
4590static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4591 int highmem, int wol)
4592{
4593 struct sky2_port *sky2;
4594 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4595 int ret;
4596
4597 if (!dev)
4598 return NULL;
4599
4600 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4601 dev->irq = hw->pdev->irq;
4602 dev->ethtool_ops = &sky2_ethtool_ops;
4603 dev->watchdog_timeo = TX_WATCHDOG;
4604 dev->netdev_ops = &sky2_netdev_ops[port];
4605
4606 sky2 = netdev_priv(dev);
4607 sky2->netdev = dev;
4608 sky2->hw = hw;
4609 sky2->msg_enable = netif_msg_init(debug, default_msg);
4610
4611 u64_stats_init(&sky2->tx_stats.syncp);
4612 u64_stats_init(&sky2->rx_stats.syncp);
4613
4614 /* Auto speed and flow control */
4615 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4616 if (hw->chip_id != CHIP_ID_YUKON_XL)
4617 dev->hw_features |= NETIF_F_RXCSUM;
4618
4619 sky2->flow_mode = FC_BOTH;
4620
4621 sky2->duplex = -1;
4622 sky2->speed = -1;
4623 sky2->advertising = sky2_supported_modes(hw);
4624 sky2->wol = wol;
4625
4626 spin_lock_init(&sky2->phy_lock);
4627
4628 sky2->tx_pending = TX_DEF_PENDING;
4629 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4630 sky2->rx_pending = RX_DEF_PENDING;
4631
4632 hw->dev[port] = dev;
4633
4634 sky2->port = port;
4635
4636 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4637
4638 if (highmem)
4639 dev->features |= NETIF_F_HIGHDMA;
4640
4641 /* Enable receive hashing unless hardware is known broken */
4642 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4643 dev->hw_features |= NETIF_F_RXHASH;
4644
4645 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4646 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4647 NETIF_F_HW_VLAN_CTAG_RX;
4648 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4649 }
4650
4651 dev->features |= dev->hw_features;
4652
4653 /* MTU range: 60 - 1500 or 9000 */
4654 dev->min_mtu = ETH_ZLEN;
4655 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4656 hw->chip_id == CHIP_ID_YUKON_FE_P)
4657 dev->max_mtu = ETH_DATA_LEN;
4658 else
4659 dev->max_mtu = ETH_JUMBO_MTU;
4660
4661 /* try to get mac address in the following order:
4662 * 1) from device tree data
4663 * 2) from internal registers set by bootloader
4664 */
4665 ret = of_get_ethdev_address(hw->pdev->dev.of_node, dev);
4666 if (ret) {
4667 u8 addr[ETH_ALEN];
4668
4669 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4670 eth_hw_addr_set(dev, addr);
4671 }
4672
4673 /* if the address is invalid, use a random value */
4674 if (!is_valid_ether_addr(dev->dev_addr)) {
4675 struct sockaddr sa = { AF_UNSPEC };
4676
4677 dev_warn(&hw->pdev->dev, "Invalid MAC address, defaulting to random\n");
4678 eth_hw_addr_random(dev);
4679 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
4680 if (sky2_set_mac_address(dev, &sa))
4681 dev_warn(&hw->pdev->dev, "Failed to set MAC address.\n");
4682 }
4683
4684 return dev;
4685}
4686
4687static void sky2_show_addr(struct net_device *dev)
4688{
4689 const struct sky2_port *sky2 = netdev_priv(dev);
4690
4691 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4692}
4693
4694/* Handle software interrupt used during MSI test */
4695static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4696{
4697 struct sky2_hw *hw = dev_id;
4698 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4699
4700 if (status == 0)
4701 return IRQ_NONE;
4702
4703 if (status & Y2_IS_IRQ_SW) {
4704 hw->flags |= SKY2_HW_USE_MSI;
4705 wake_up(&hw->msi_wait);
4706 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4707 }
4708 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4709
4710 return IRQ_HANDLED;
4711}
4712
4713/* Test interrupt path by forcing a software IRQ */
4714static int sky2_test_msi(struct sky2_hw *hw)
4715{
4716 struct pci_dev *pdev = hw->pdev;
4717 int err;
4718
4719 init_waitqueue_head(&hw->msi_wait);
4720
4721 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4722 if (err) {
4723 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4724 return err;
4725 }
4726
4727 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4728
4729 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4730 sky2_read8(hw, B0_CTST);
4731
4732 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4733
4734 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4735 /* MSI test failed, go back to INTx mode */
4736 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4737 "switching to INTx mode.\n");
4738
4739 err = -EOPNOTSUPP;
4740 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4741 }
4742
4743 sky2_write32(hw, B0_IMSK, 0);
4744 sky2_read32(hw, B0_IMSK);
4745
4746 free_irq(pdev->irq, hw);
4747
4748 return err;
4749}
4750
4751/* This driver supports yukon2 chipset only */
4752static const char *sky2_name(u8 chipid, char *buf, int sz)
4753{
4754 static const char *const name[] = {
4755 "XL", /* 0xb3 */
4756 "EC Ultra", /* 0xb4 */
4757 "Extreme", /* 0xb5 */
4758 "EC", /* 0xb6 */
4759 "FE", /* 0xb7 */
4760 "FE+", /* 0xb8 */
4761 "Supreme", /* 0xb9 */
4762 "UL 2", /* 0xba */
4763 "Unknown", /* 0xbb */
4764 "Optima", /* 0xbc */
4765 "OptimaEEE", /* 0xbd */
4766 "Optima 2", /* 0xbe */
4767 };
4768
4769 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4770 snprintf(buf, sz, "%s", name[chipid - CHIP_ID_YUKON_XL]);
4771 else
4772 snprintf(buf, sz, "(chip %#x)", chipid);
4773 return buf;
4774}
4775
4776static const struct dmi_system_id msi_blacklist[] = {
4777 {
4778 .ident = "Dell Inspiron 1545",
4779 .matches = {
4780 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
4781 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"),
4782 },
4783 },
4784 {
4785 .ident = "Gateway P-79",
4786 .matches = {
4787 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"),
4788 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"),
4789 },
4790 },
4791 {
4792 .ident = "ASUS P5W DH Deluxe",
4793 .matches = {
4794 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTEK COMPUTER INC"),
4795 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
4796 },
4797 },
4798 {
4799 .ident = "ASUS P6T",
4800 .matches = {
4801 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4802 DMI_MATCH(DMI_BOARD_NAME, "P6T"),
4803 },
4804 },
4805 {
4806 .ident = "ASUS P6X",
4807 .matches = {
4808 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4809 DMI_MATCH(DMI_BOARD_NAME, "P6X"),
4810 },
4811 },
4812 {}
4813};
4814
4815static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4816{
4817 struct net_device *dev, *dev1;
4818 struct sky2_hw *hw;
4819 int err, using_dac = 0, wol_default;
4820 u32 reg;
4821 char buf1[16];
4822
4823 err = pci_enable_device(pdev);
4824 if (err) {
4825 dev_err(&pdev->dev, "cannot enable PCI device\n");
4826 goto err_out;
4827 }
4828
4829 /* Get configuration information
4830 * Note: only regular PCI config access once to test for HW issues
4831 * other PCI access through shared memory for speed and to
4832 * avoid MMCONFIG problems.
4833 */
4834 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4835 if (err) {
4836 dev_err(&pdev->dev, "PCI read config failed\n");
4837 goto err_out_disable;
4838 }
4839
4840 if (~reg == 0) {
4841 dev_err(&pdev->dev, "PCI configuration read error\n");
4842 err = -EIO;
4843 goto err_out_disable;
4844 }
4845
4846 err = pci_request_regions(pdev, DRV_NAME);
4847 if (err) {
4848 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4849 goto err_out_disable;
4850 }
4851
4852 pci_set_master(pdev);
4853
4854 if (sizeof(dma_addr_t) > sizeof(u32) &&
4855 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
4856 using_dac = 1;
4857 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
4858 if (err < 0) {
4859 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4860 "for consistent allocations\n");
4861 goto err_out_free_regions;
4862 }
4863 } else {
4864 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
4865 if (err) {
4866 dev_err(&pdev->dev, "no usable DMA configuration\n");
4867 goto err_out_free_regions;
4868 }
4869 }
4870
4871
4872#ifdef __BIG_ENDIAN
4873 /* The sk98lin vendor driver uses hardware byte swapping but
4874 * this driver uses software swapping.
4875 */
4876 reg &= ~PCI_REV_DESC;
4877 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4878 if (err) {
4879 dev_err(&pdev->dev, "PCI write config failed\n");
4880 goto err_out_free_regions;
4881 }
4882#endif
4883
4884 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4885
4886 err = -ENOMEM;
4887
4888 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4889 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4890 if (!hw)
4891 goto err_out_free_regions;
4892
4893 hw->pdev = pdev;
4894 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4895
4896 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
4897 if (!hw->regs) {
4898 dev_err(&pdev->dev, "cannot map device registers\n");
4899 goto err_out_free_hw;
4900 }
4901
4902 err = sky2_init(hw);
4903 if (err)
4904 goto err_out_iounmap;
4905
4906 /* ring for status responses */
4907 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4908 hw->st_le = dma_alloc_coherent(&pdev->dev,
4909 hw->st_size * sizeof(struct sky2_status_le),
4910 &hw->st_dma, GFP_KERNEL);
4911 if (!hw->st_le) {
4912 err = -ENOMEM;
4913 goto err_out_reset;
4914 }
4915
4916 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4917 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4918
4919 sky2_reset(hw);
4920
4921 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4922 if (!dev) {
4923 err = -ENOMEM;
4924 goto err_out_free_pci;
4925 }
4926
4927 if (disable_msi == -1)
4928 disable_msi = !!dmi_check_system(msi_blacklist);
4929
4930 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4931 err = sky2_test_msi(hw);
4932 if (err) {
4933 pci_disable_msi(pdev);
4934 if (err != -EOPNOTSUPP)
4935 goto err_out_free_netdev;
4936 }
4937 }
4938
4939 netif_napi_add(dev, &hw->napi, sky2_poll);
4940
4941 err = register_netdev(dev);
4942 if (err) {
4943 dev_err(&pdev->dev, "cannot register net device\n");
4944 goto err_out_free_netdev;
4945 }
4946
4947 netif_carrier_off(dev);
4948
4949 sky2_show_addr(dev);
4950
4951 if (hw->ports > 1) {
4952 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4953 if (!dev1) {
4954 err = -ENOMEM;
4955 goto err_out_unregister;
4956 }
4957
4958 err = register_netdev(dev1);
4959 if (err) {
4960 dev_err(&pdev->dev, "cannot register second net device\n");
4961 goto err_out_free_dev1;
4962 }
4963
4964 err = sky2_setup_irq(hw, hw->irq_name);
4965 if (err)
4966 goto err_out_unregister_dev1;
4967
4968 sky2_show_addr(dev1);
4969 }
4970
4971 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
4972 INIT_WORK(&hw->restart_work, sky2_restart);
4973
4974 pci_set_drvdata(pdev, hw);
4975 pdev->d3hot_delay = 300;
4976
4977 return 0;
4978
4979err_out_unregister_dev1:
4980 unregister_netdev(dev1);
4981err_out_free_dev1:
4982 free_netdev(dev1);
4983err_out_unregister:
4984 unregister_netdev(dev);
4985err_out_free_netdev:
4986 if (hw->flags & SKY2_HW_USE_MSI)
4987 pci_disable_msi(pdev);
4988 free_netdev(dev);
4989err_out_free_pci:
4990 dma_free_coherent(&pdev->dev,
4991 hw->st_size * sizeof(struct sky2_status_le),
4992 hw->st_le, hw->st_dma);
4993err_out_reset:
4994 sky2_write8(hw, B0_CTST, CS_RST_SET);
4995err_out_iounmap:
4996 iounmap(hw->regs);
4997err_out_free_hw:
4998 kfree(hw);
4999err_out_free_regions:
5000 pci_release_regions(pdev);
5001err_out_disable:
5002 pci_disable_device(pdev);
5003err_out:
5004 return err;
5005}
5006
5007static void sky2_remove(struct pci_dev *pdev)
5008{
5009 struct sky2_hw *hw = pci_get_drvdata(pdev);
5010 int i;
5011
5012 if (!hw)
5013 return;
5014
5015 timer_shutdown_sync(&hw->watchdog_timer);
5016 cancel_work_sync(&hw->restart_work);
5017
5018 for (i = hw->ports-1; i >= 0; --i)
5019 unregister_netdev(hw->dev[i]);
5020
5021 sky2_write32(hw, B0_IMSK, 0);
5022 sky2_read32(hw, B0_IMSK);
5023
5024 sky2_power_aux(hw);
5025
5026 sky2_write8(hw, B0_CTST, CS_RST_SET);
5027 sky2_read8(hw, B0_CTST);
5028
5029 if (hw->ports > 1) {
5030 napi_disable(&hw->napi);
5031 free_irq(pdev->irq, hw);
5032 }
5033
5034 if (hw->flags & SKY2_HW_USE_MSI)
5035 pci_disable_msi(pdev);
5036 dma_free_coherent(&pdev->dev,
5037 hw->st_size * sizeof(struct sky2_status_le),
5038 hw->st_le, hw->st_dma);
5039 pci_release_regions(pdev);
5040 pci_disable_device(pdev);
5041
5042 for (i = hw->ports-1; i >= 0; --i)
5043 free_netdev(hw->dev[i]);
5044
5045 iounmap(hw->regs);
5046 kfree(hw);
5047}
5048
5049static int sky2_suspend(struct device *dev)
5050{
5051 struct sky2_hw *hw = dev_get_drvdata(dev);
5052 int i;
5053
5054 if (!hw)
5055 return 0;
5056
5057 del_timer_sync(&hw->watchdog_timer);
5058 cancel_work_sync(&hw->restart_work);
5059
5060 rtnl_lock();
5061
5062 sky2_all_down(hw);
5063 for (i = 0; i < hw->ports; i++) {
5064 struct net_device *dev = hw->dev[i];
5065 struct sky2_port *sky2 = netdev_priv(dev);
5066
5067 if (sky2->wol)
5068 sky2_wol_init(sky2);
5069 }
5070
5071 sky2_power_aux(hw);
5072 rtnl_unlock();
5073
5074 return 0;
5075}
5076
5077#ifdef CONFIG_PM_SLEEP
5078static int sky2_resume(struct device *dev)
5079{
5080 struct pci_dev *pdev = to_pci_dev(dev);
5081 struct sky2_hw *hw = pci_get_drvdata(pdev);
5082 int err;
5083
5084 if (!hw)
5085 return 0;
5086
5087 /* Re-enable all clocks */
5088 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5089 if (err) {
5090 dev_err(&pdev->dev, "PCI write config failed\n");
5091 goto out;
5092 }
5093
5094 rtnl_lock();
5095 sky2_reset(hw);
5096 sky2_all_up(hw);
5097 rtnl_unlock();
5098
5099 return 0;
5100out:
5101
5102 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5103 pci_disable_device(pdev);
5104 return err;
5105}
5106
5107static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5108#define SKY2_PM_OPS (&sky2_pm_ops)
5109
5110#else
5111
5112#define SKY2_PM_OPS NULL
5113#endif
5114
5115static void sky2_shutdown(struct pci_dev *pdev)
5116{
5117 struct sky2_hw *hw = pci_get_drvdata(pdev);
5118 int port;
5119
5120 for (port = 0; port < hw->ports; port++) {
5121 struct net_device *ndev = hw->dev[port];
5122
5123 rtnl_lock();
5124 if (netif_running(ndev)) {
5125 dev_close(ndev);
5126 netif_device_detach(ndev);
5127 }
5128 rtnl_unlock();
5129 }
5130 sky2_suspend(&pdev->dev);
5131 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5132 pci_set_power_state(pdev, PCI_D3hot);
5133}
5134
5135static struct pci_driver sky2_driver = {
5136 .name = DRV_NAME,
5137 .id_table = sky2_id_table,
5138 .probe = sky2_probe,
5139 .remove = sky2_remove,
5140 .shutdown = sky2_shutdown,
5141 .driver.pm = SKY2_PM_OPS,
5142};
5143
5144static int __init sky2_init_module(void)
5145{
5146 pr_info("driver version " DRV_VERSION "\n");
5147
5148 sky2_debug_init();
5149 return pci_register_driver(&sky2_driver);
5150}
5151
5152static void __exit sky2_cleanup_module(void)
5153{
5154 pci_unregister_driver(&sky2_driver);
5155 sky2_debug_cleanup();
5156}
5157
5158module_init(sky2_init_module);
5159module_exit(sky2_cleanup_module);
5160
5161MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5162MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5163MODULE_LICENSE("GPL");
5164MODULE_VERSION(DRV_VERSION);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * New driver for Marvell Yukon 2 chipset.
4 * Based on earlier sk98lin, and skge driver.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/crc32.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/netdevice.h>
19#include <linux/dma-mapping.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/ip.h>
25#include <linux/slab.h>
26#include <net/ip.h>
27#include <linux/tcp.h>
28#include <linux/in.h>
29#include <linux/delay.h>
30#include <linux/workqueue.h>
31#include <linux/if_vlan.h>
32#include <linux/prefetch.h>
33#include <linux/debugfs.h>
34#include <linux/mii.h>
35#include <linux/of_device.h>
36#include <linux/of_net.h>
37#include <linux/dmi.h>
38
39#include <asm/irq.h>
40
41#include "sky2.h"
42
43#define DRV_NAME "sky2"
44#define DRV_VERSION "1.30"
45
46/*
47 * The Yukon II chipset takes 64 bit command blocks (called list elements)
48 * that are organized into three (receive, transmit, status) different rings
49 * similar to Tigon3.
50 */
51
52#define RX_LE_SIZE 1024
53#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
54#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
55#define RX_DEF_PENDING RX_MAX_PENDING
56
57/* This is the worst case number of transmit list elements for a single skb:
58 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
59#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
60#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
61#define TX_MAX_PENDING 1024
62#define TX_DEF_PENDING 63
63
64#define TX_WATCHDOG (5 * HZ)
65#define NAPI_WEIGHT 64
66#define PHY_RETRIES 1000
67
68#define SKY2_EEPROM_MAGIC 0x9955aabb
69
70#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
71
72static const u32 default_msg =
73 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
74 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
75 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
76
77static int debug = -1; /* defaults above */
78module_param(debug, int, 0);
79MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
80
81static int copybreak __read_mostly = 128;
82module_param(copybreak, int, 0);
83MODULE_PARM_DESC(copybreak, "Receive copy threshold");
84
85static int disable_msi = -1;
86module_param(disable_msi, int, 0);
87MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
88
89static int legacy_pme = 0;
90module_param(legacy_pme, int, 0);
91MODULE_PARM_DESC(legacy_pme, "Legacy power management");
92
93static const struct pci_device_id sky2_id_table[] = {
94 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
95 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
97 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
100 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
136 { 0 }
137};
138
139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
145
146static void sky2_set_multicast(struct net_device *dev);
147static irqreturn_t sky2_intr(int irq, void *dev_id);
148
149/* Access to PHY via serial interconnect */
150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
159 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
160 if (ctrl == 0xffff)
161 goto io_error;
162
163 if (!(ctrl & GM_SMI_CT_BUSY))
164 return 0;
165
166 udelay(10);
167 }
168
169 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
170 return -ETIMEDOUT;
171
172io_error:
173 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
174 return -EIO;
175}
176
177static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
178{
179 int i;
180
181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
183
184 for (i = 0; i < PHY_RETRIES; i++) {
185 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
186 if (ctrl == 0xffff)
187 goto io_error;
188
189 if (ctrl & GM_SMI_CT_RD_VAL) {
190 *val = gma_read16(hw, port, GM_SMI_DATA);
191 return 0;
192 }
193
194 udelay(10);
195 }
196
197 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
198 return -ETIMEDOUT;
199io_error:
200 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
201 return -EIO;
202}
203
204static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
205{
206 u16 v = 0;
207 __gm_phy_read(hw, port, reg, &v);
208 return v;
209}
210
211
212static void sky2_power_on(struct sky2_hw *hw)
213{
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw, B0_POWER_CTRL,
216 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
217
218 /* disable Core Clock Division, */
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
220
221 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
222 /* enable bits are inverted */
223 sky2_write8(hw, B2_Y2_CLK_GATE,
224 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
225 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
226 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
227 else
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229
230 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
231 u32 reg;
232
233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234
235 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
236 /* set all bits to 0 except bits 15..12 and 8 */
237 reg &= P_ASPM_CONTROL_MSK;
238 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
239
240 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
241 /* set all bits to 0 except bits 28 & 27 */
242 reg &= P_CTL_TIM_VMAIN_AV_MSK;
243 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
244
245 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
246
247 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
248
249 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
250 reg = sky2_read32(hw, B2_GP_IO);
251 reg |= GLB_GPIO_STAT_RACE_DIS;
252 sky2_write32(hw, B2_GP_IO, reg);
253
254 sky2_read32(hw, B2_GP_IO);
255 }
256
257 /* Turn on "driver loaded" LED */
258 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
259}
260
261static void sky2_power_aux(struct sky2_hw *hw)
262{
263 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
264 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
265 else
266 /* enable bits are inverted */
267 sky2_write8(hw, B2_Y2_CLK_GATE,
268 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
269 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
270 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
271
272 /* switch power to VAUX if supported and PME from D3cold */
273 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
274 pci_pme_capable(hw->pdev, PCI_D3cold))
275 sky2_write8(hw, B0_POWER_CTRL,
276 (PC_VAUX_ENA | PC_VCC_ENA |
277 PC_VAUX_ON | PC_VCC_OFF));
278
279 /* turn off "driver loaded LED" */
280 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
281}
282
283static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
284{
285 u16 reg;
286
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289
290 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
291 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
292 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
293 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
294
295 reg = gma_read16(hw, port, GM_RX_CTRL);
296 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
297 gma_write16(hw, port, GM_RX_CTRL, reg);
298}
299
300/* flow control to advertise bits */
301static const u16 copper_fc_adv[] = {
302 [FC_NONE] = 0,
303 [FC_TX] = PHY_M_AN_ASP,
304 [FC_RX] = PHY_M_AN_PC,
305 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
306};
307
308/* flow control to advertise bits when using 1000BaseX */
309static const u16 fiber_fc_adv[] = {
310 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
311 [FC_TX] = PHY_M_P_ASYM_MD_X,
312 [FC_RX] = PHY_M_P_SYM_MD_X,
313 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
314};
315
316/* flow control to GMA disable bits */
317static const u16 gm_fc_disable[] = {
318 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
319 [FC_TX] = GM_GPCR_FC_RX_DIS,
320 [FC_RX] = GM_GPCR_FC_TX_DIS,
321 [FC_BOTH] = 0,
322};
323
324
325static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
326{
327 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
328 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
329
330 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
331 !(hw->flags & SKY2_HW_NEWER_PHY)) {
332 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
333
334 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
335 PHY_M_EC_MAC_S_MSK);
336 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
337
338 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
339 if (hw->chip_id == CHIP_ID_YUKON_EC)
340 /* set downshift counter to 3x and enable downshift */
341 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
342 else
343 /* set master & slave downshift counter to 1x */
344 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
345
346 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
347 }
348
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
350 if (sky2_is_copper(hw)) {
351 if (!(hw->flags & SKY2_HW_GIGABIT)) {
352 /* enable automatic crossover */
353 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
354
355 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
356 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
357 u16 spec;
358
359 /* Enable Class A driver for FE+ A0 */
360 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
361 spec |= PHY_M_FESC_SEL_CL_A;
362 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
363 }
364 } else {
365 /* disable energy detect */
366 ctrl &= ~PHY_M_PC_EN_DET_MSK;
367
368 /* enable automatic crossover */
369 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
370
371 /* downshift on PHY 88E1112 and 88E1149 is changed */
372 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
373 (hw->flags & SKY2_HW_NEWER_PHY)) {
374 /* set downshift counter to 3x and enable downshift */
375 ctrl &= ~PHY_M_PC_DSC_MSK;
376 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
377 }
378 }
379 } else {
380 /* workaround for deviation #4.88 (CRC errors) */
381 /* disable Automatic Crossover */
382
383 ctrl &= ~PHY_M_PC_MDIX_MSK;
384 }
385
386 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
387
388 /* special setup for PHY 88E1112 Fiber */
389 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
390 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
391
392 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
393 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
394 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
395 ctrl &= ~PHY_M_MAC_MD_MSK;
396 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
398
399 if (hw->pmd_type == 'P') {
400 /* select page 1 to access Fiber registers */
401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
402
403 /* for SFP-module set SIGDET polarity to low */
404 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
405 ctrl |= PHY_M_FIB_SIGD_POL;
406 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
407 }
408
409 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
410 }
411
412 ctrl = PHY_CT_RESET;
413 ct1000 = 0;
414 adv = PHY_AN_CSMA;
415 reg = 0;
416
417 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
418 if (sky2_is_copper(hw)) {
419 if (sky2->advertising & ADVERTISED_1000baseT_Full)
420 ct1000 |= PHY_M_1000C_AFD;
421 if (sky2->advertising & ADVERTISED_1000baseT_Half)
422 ct1000 |= PHY_M_1000C_AHD;
423 if (sky2->advertising & ADVERTISED_100baseT_Full)
424 adv |= PHY_M_AN_100_FD;
425 if (sky2->advertising & ADVERTISED_100baseT_Half)
426 adv |= PHY_M_AN_100_HD;
427 if (sky2->advertising & ADVERTISED_10baseT_Full)
428 adv |= PHY_M_AN_10_FD;
429 if (sky2->advertising & ADVERTISED_10baseT_Half)
430 adv |= PHY_M_AN_10_HD;
431
432 } else { /* special defines for FIBER (88E1040S only) */
433 if (sky2->advertising & ADVERTISED_1000baseT_Full)
434 adv |= PHY_M_AN_1000X_AFD;
435 if (sky2->advertising & ADVERTISED_1000baseT_Half)
436 adv |= PHY_M_AN_1000X_AHD;
437 }
438
439 /* Restart Auto-negotiation */
440 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
441 } else {
442 /* forced speed/duplex settings */
443 ct1000 = PHY_M_1000C_MSE;
444
445 /* Disable auto update for duplex flow control and duplex */
446 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
447
448 switch (sky2->speed) {
449 case SPEED_1000:
450 ctrl |= PHY_CT_SP1000;
451 reg |= GM_GPCR_SPEED_1000;
452 break;
453 case SPEED_100:
454 ctrl |= PHY_CT_SP100;
455 reg |= GM_GPCR_SPEED_100;
456 break;
457 }
458
459 if (sky2->duplex == DUPLEX_FULL) {
460 reg |= GM_GPCR_DUP_FULL;
461 ctrl |= PHY_CT_DUP_MD;
462 } else if (sky2->speed < SPEED_1000)
463 sky2->flow_mode = FC_NONE;
464 }
465
466 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
467 if (sky2_is_copper(hw))
468 adv |= copper_fc_adv[sky2->flow_mode];
469 else
470 adv |= fiber_fc_adv[sky2->flow_mode];
471 } else {
472 reg |= GM_GPCR_AU_FCT_DIS;
473 reg |= gm_fc_disable[sky2->flow_mode];
474
475 /* Forward pause packets to GMAC? */
476 if (sky2->flow_mode & FC_RX)
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
478 else
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
480 }
481
482 gma_write16(hw, port, GM_GP_CTRL, reg);
483
484 if (hw->flags & SKY2_HW_GIGABIT)
485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
486
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
489
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
492 ledover = 0;
493
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
498
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
500
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
512
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
516
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
521
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
523 break;
524
525 case CHIP_ID_YUKON_XL:
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
537
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
546
547 /* restore page register */
548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
549 break;
550
551 case CHIP_ID_YUKON_EC_U:
552 case CHIP_ID_YUKON_EX:
553 case CHIP_ID_YUKON_SUPR:
554 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
555
556 /* select page 3 to access LED control register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
558
559 /* set LED Function Control register */
560 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
561 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
562 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
563 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
564 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
565
566 /* set Blink Rate in LED Timer Control Register */
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
568 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
569 /* restore page register */
570 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
571 break;
572
573 default:
574 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
575 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
576
577 /* turn off the Rx LED (LED_RX) */
578 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
579 }
580
581 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
582 /* apply fixes in PHY AFE */
583 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
584
585 /* increase differential signal amplitude in 10BASE-T */
586 gm_phy_write(hw, port, 0x18, 0xaa99);
587 gm_phy_write(hw, port, 0x17, 0x2011);
588
589 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
590 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xa204);
592 gm_phy_write(hw, port, 0x17, 0x2002);
593 }
594
595 /* set page register to 0 */
596 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
597 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
598 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
599 /* apply workaround for integrated resistors calibration */
600 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
601 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
602 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
603 /* apply fixes in PHY AFE */
604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
605
606 /* apply RDAC termination workaround */
607 gm_phy_write(hw, port, 24, 0x2800);
608 gm_phy_write(hw, port, 23, 0x2001);
609
610 /* set page register back to 0 */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
612 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
613 hw->chip_id < CHIP_ID_YUKON_SUPR) {
614 /* no effect on Yukon-XL */
615 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
616
617 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
618 sky2->speed == SPEED_100) {
619 /* turn on 100 Mbps LED (LED_LINK100) */
620 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
621 }
622
623 if (ledover)
624 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
625
626 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
627 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
628 int i;
629 /* This a phy register setup workaround copied from vendor driver. */
630 static const struct {
631 u16 reg, val;
632 } eee_afe[] = {
633 { 0x156, 0x58ce },
634 { 0x153, 0x99eb },
635 { 0x141, 0x8064 },
636 /* { 0x155, 0x130b },*/
637 { 0x000, 0x0000 },
638 { 0x151, 0x8433 },
639 { 0x14b, 0x8c44 },
640 { 0x14c, 0x0f90 },
641 { 0x14f, 0x39aa },
642 /* { 0x154, 0x2f39 },*/
643 { 0x14d, 0xba33 },
644 { 0x144, 0x0048 },
645 { 0x152, 0x2010 },
646 /* { 0x158, 0x1223 },*/
647 { 0x140, 0x4444 },
648 { 0x154, 0x2f3b },
649 { 0x158, 0xb203 },
650 { 0x157, 0x2029 },
651 };
652
653 /* Start Workaround for OptimaEEE Rev.Z0 */
654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
655
656 gm_phy_write(hw, port, 1, 0x4099);
657 gm_phy_write(hw, port, 3, 0x1120);
658 gm_phy_write(hw, port, 11, 0x113c);
659 gm_phy_write(hw, port, 14, 0x8100);
660 gm_phy_write(hw, port, 15, 0x112a);
661 gm_phy_write(hw, port, 17, 0x1008);
662
663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
664 gm_phy_write(hw, port, 1, 0x20b0);
665
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
667
668 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
669 /* apply AFE settings */
670 gm_phy_write(hw, port, 17, eee_afe[i].val);
671 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
672 }
673
674 /* End Workaround for OptimaEEE */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
676
677 /* Enable 10Base-Te (EEE) */
678 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
679 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
680 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
681 reg | PHY_M_10B_TE_ENABLE);
682 }
683 }
684
685 /* Enable phy interrupt on auto-negotiation complete (or link up) */
686 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
687 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
688 else
689 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
690}
691
692static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
693static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
694
695static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
696{
697 u32 reg1;
698
699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
700 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
701 reg1 &= ~phy_power[port];
702
703 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
704 reg1 |= coma_mode[port];
705
706 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
707 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
708 sky2_pci_read32(hw, PCI_DEV_REG1);
709
710 if (hw->chip_id == CHIP_ID_YUKON_FE)
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
712 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
713 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
714}
715
716static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
717{
718 u32 reg1;
719 u16 ctrl;
720
721 /* release GPHY Control reset */
722 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
723
724 /* release GMAC reset */
725 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
726
727 if (hw->flags & SKY2_HW_NEWER_PHY) {
728 /* select page 2 to access MAC control register */
729 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
730
731 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
732 /* allow GMII Power Down */
733 ctrl &= ~PHY_M_MAC_GMIF_PUP;
734 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
735
736 /* set page register back to 0 */
737 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
738 }
739
740 /* setup General Purpose Control Register */
741 gma_write16(hw, port, GM_GP_CTRL,
742 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
743 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
744 GM_GPCR_AU_SPD_DIS);
745
746 if (hw->chip_id != CHIP_ID_YUKON_EC) {
747 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
748 /* select page 2 to access MAC control register */
749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
750
751 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
752 /* enable Power Down */
753 ctrl |= PHY_M_PC_POW_D_ENA;
754 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
755
756 /* set page register back to 0 */
757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
758 }
759
760 /* set IEEE compatible Power Down Mode (dev. #4.99) */
761 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
762 }
763
764 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
765 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
766 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
767 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
769}
770
771/* configure IPG according to used link speed */
772static void sky2_set_ipg(struct sky2_port *sky2)
773{
774 u16 reg;
775
776 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
777 reg &= ~GM_SMOD_IPG_MSK;
778 if (sky2->speed > SPEED_100)
779 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
780 else
781 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
782 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
783}
784
785/* Enable Rx/Tx */
786static void sky2_enable_rx_tx(struct sky2_port *sky2)
787{
788 struct sky2_hw *hw = sky2->hw;
789 unsigned port = sky2->port;
790 u16 reg;
791
792 reg = gma_read16(hw, port, GM_GP_CTRL);
793 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
794 gma_write16(hw, port, GM_GP_CTRL, reg);
795}
796
797/* Force a renegotiation */
798static void sky2_phy_reinit(struct sky2_port *sky2)
799{
800 spin_lock_bh(&sky2->phy_lock);
801 sky2_phy_init(sky2->hw, sky2->port);
802 sky2_enable_rx_tx(sky2);
803 spin_unlock_bh(&sky2->phy_lock);
804}
805
806/* Put device in state to listen for Wake On Lan */
807static void sky2_wol_init(struct sky2_port *sky2)
808{
809 struct sky2_hw *hw = sky2->hw;
810 unsigned port = sky2->port;
811 enum flow_control save_mode;
812 u16 ctrl;
813
814 /* Bring hardware out of reset */
815 sky2_write16(hw, B0_CTST, CS_RST_CLR);
816 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
817
818 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
820
821 /* Force to 10/100
822 * sky2_reset will re-enable on resume
823 */
824 save_mode = sky2->flow_mode;
825 ctrl = sky2->advertising;
826
827 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
828 sky2->flow_mode = FC_NONE;
829
830 spin_lock_bh(&sky2->phy_lock);
831 sky2_phy_power_up(hw, port);
832 sky2_phy_init(hw, port);
833 spin_unlock_bh(&sky2->phy_lock);
834
835 sky2->flow_mode = save_mode;
836 sky2->advertising = ctrl;
837
838 /* Set GMAC to no flow control and auto update for speed/duplex */
839 gma_write16(hw, port, GM_GP_CTRL,
840 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
841 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
842
843 /* Set WOL address */
844 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
845 sky2->netdev->dev_addr, ETH_ALEN);
846
847 /* Turn on appropriate WOL control bits */
848 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
849 ctrl = 0;
850 if (sky2->wol & WAKE_PHY)
851 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
852 else
853 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
854
855 if (sky2->wol & WAKE_MAGIC)
856 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
857 else
858 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
859
860 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
861 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
862
863 /* Disable PiG firmware */
864 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
865
866 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
867 if (legacy_pme) {
868 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
869 reg1 |= PCI_Y2_PME_LEGACY;
870 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
871 }
872
873 /* block receiver */
874 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
875 sky2_read32(hw, B0_CTST);
876}
877
878static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
879{
880 struct net_device *dev = hw->dev[port];
881
882 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
883 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
884 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
885 /* Yukon-Extreme B0 and further Extreme devices */
886 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
887 } else if (dev->mtu > ETH_DATA_LEN) {
888 /* set Tx GMAC FIFO Almost Empty Threshold */
889 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
890 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
891
892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
893 } else
894 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
895}
896
897static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
898{
899 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
900 u16 reg;
901 u32 rx_reg;
902 int i;
903 const u8 *addr = hw->dev[port]->dev_addr;
904
905 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
907
908 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
909
910 if (hw->chip_id == CHIP_ID_YUKON_XL &&
911 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
912 port == 1) {
913 /* WA DEV_472 -- looks like crossed wires on port 2 */
914 /* clear GMAC 1 Control reset */
915 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
916 do {
917 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
918 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
919 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
920 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
921 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
922 }
923
924 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
925
926 /* Enable Transmit FIFO Underrun */
927 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
928
929 spin_lock_bh(&sky2->phy_lock);
930 sky2_phy_power_up(hw, port);
931 sky2_phy_init(hw, port);
932 spin_unlock_bh(&sky2->phy_lock);
933
934 /* MIB clear */
935 reg = gma_read16(hw, port, GM_PHY_ADDR);
936 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
937
938 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
939 gma_read16(hw, port, i);
940 gma_write16(hw, port, GM_PHY_ADDR, reg);
941
942 /* transmit control */
943 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
944
945 /* receive control reg: unicast + multicast + no FCS */
946 gma_write16(hw, port, GM_RX_CTRL,
947 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
948
949 /* transmit flow control */
950 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
951
952 /* transmit parameter */
953 gma_write16(hw, port, GM_TX_PARAM,
954 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
955 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
956 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
957 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
958
959 /* serial mode register */
960 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
961 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
962
963 if (hw->dev[port]->mtu > ETH_DATA_LEN)
964 reg |= GM_SMOD_JUMBO_ENA;
965
966 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
967 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
968 reg |= GM_NEW_FLOW_CTRL;
969
970 gma_write16(hw, port, GM_SERIAL_MODE, reg);
971
972 /* virtual address for data */
973 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
974
975 /* physical address: used for pause frames */
976 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
977
978 /* ignore counter overflows */
979 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
980 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
981 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
982
983 /* Configure Rx MAC FIFO */
984 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
985 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
986 if (hw->chip_id == CHIP_ID_YUKON_EX ||
987 hw->chip_id == CHIP_ID_YUKON_FE_P)
988 rx_reg |= GMF_RX_OVER_ON;
989
990 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
991
992 if (hw->chip_id == CHIP_ID_YUKON_XL) {
993 /* Hardware errata - clear flush mask */
994 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
995 } else {
996 /* Flush Rx MAC FIFO on any flow control or error */
997 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
998 }
999
1000 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1001 reg = RX_GMF_FL_THR_DEF + 1;
1002 /* Another magic mystery workaround from sk98lin */
1003 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1004 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1005 reg = 0x178;
1006 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1007
1008 /* Configure Tx MAC FIFO */
1009 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1010 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1011
1012 /* On chips without ram buffer, pause is controlled by MAC level */
1013 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1014 /* Pause threshold is scaled by 8 in bytes */
1015 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1016 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1017 reg = 1568 / 8;
1018 else
1019 reg = 1024 / 8;
1020 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1021 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1022
1023 sky2_set_tx_stfwd(hw, port);
1024 }
1025
1026 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1027 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1028 /* disable dynamic watermark */
1029 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1030 reg &= ~TX_DYN_WM_ENA;
1031 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1032 }
1033}
1034
1035/* Assign Ram Buffer allocation to queue */
1036static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1037{
1038 u32 end;
1039
1040 /* convert from K bytes to qwords used for hw register */
1041 start *= 1024/8;
1042 space *= 1024/8;
1043 end = start + space - 1;
1044
1045 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1046 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1047 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1048 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1049 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1050
1051 if (q == Q_R1 || q == Q_R2) {
1052 u32 tp = space - space/4;
1053
1054 /* On receive queue's set the thresholds
1055 * give receiver priority when > 3/4 full
1056 * send pause when down to 2K
1057 */
1058 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1060
1061 tp = space - 8192/8;
1062 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1063 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1064 } else {
1065 /* Enable store & forward on Tx queue's because
1066 * Tx FIFO is only 1K on Yukon
1067 */
1068 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1069 }
1070
1071 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1072 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1073}
1074
1075/* Setup Bus Memory Interface */
1076static void sky2_qset(struct sky2_hw *hw, u16 q)
1077{
1078 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1081 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1082}
1083
1084/* Setup prefetch unit registers. This is the interface between
1085 * hardware and driver list elements
1086 */
1087static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1088 dma_addr_t addr, u32 last)
1089{
1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1093 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1094 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1095 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1096
1097 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1098}
1099
1100static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1101{
1102 struct sky2_tx_le *le = sky2->tx_le + *slot;
1103
1104 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1105 le->ctrl = 0;
1106 return le;
1107}
1108
1109static void tx_init(struct sky2_port *sky2)
1110{
1111 struct sky2_tx_le *le;
1112
1113 sky2->tx_prod = sky2->tx_cons = 0;
1114 sky2->tx_tcpsum = 0;
1115 sky2->tx_last_mss = 0;
1116 netdev_reset_queue(sky2->netdev);
1117
1118 le = get_tx_le(sky2, &sky2->tx_prod);
1119 le->addr = 0;
1120 le->opcode = OP_ADDR64 | HW_OWNER;
1121 sky2->tx_last_upper = 0;
1122}
1123
1124/* Update chip's next pointer */
1125static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1126{
1127 /* Make sure write' to descriptors are complete before we tell hardware */
1128 wmb();
1129 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1130}
1131
1132
1133static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1134{
1135 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1136 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1137 le->ctrl = 0;
1138 return le;
1139}
1140
1141static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1142{
1143 unsigned size;
1144
1145 /* Space needed for frame data + headers rounded up */
1146 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1147
1148 /* Stopping point for hardware truncation */
1149 return (size - 8) / sizeof(u32);
1150}
1151
1152static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1153{
1154 struct rx_ring_info *re;
1155 unsigned size;
1156
1157 /* Space needed for frame data + headers rounded up */
1158 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1159
1160 sky2->rx_nfrags = size >> PAGE_SHIFT;
1161 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1162
1163 /* Compute residue after pages */
1164 size -= sky2->rx_nfrags << PAGE_SHIFT;
1165
1166 /* Optimize to handle small packets and headers */
1167 if (size < copybreak)
1168 size = copybreak;
1169 if (size < ETH_HLEN)
1170 size = ETH_HLEN;
1171
1172 return size;
1173}
1174
1175/* Build description to hardware for one receive segment */
1176static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1177 dma_addr_t map, unsigned len)
1178{
1179 struct sky2_rx_le *le;
1180
1181 if (sizeof(dma_addr_t) > sizeof(u32)) {
1182 le = sky2_next_rx(sky2);
1183 le->addr = cpu_to_le32(upper_32_bits(map));
1184 le->opcode = OP_ADDR64 | HW_OWNER;
1185 }
1186
1187 le = sky2_next_rx(sky2);
1188 le->addr = cpu_to_le32(lower_32_bits(map));
1189 le->length = cpu_to_le16(len);
1190 le->opcode = op | HW_OWNER;
1191}
1192
1193/* Build description to hardware for one possibly fragmented skb */
1194static void sky2_rx_submit(struct sky2_port *sky2,
1195 const struct rx_ring_info *re)
1196{
1197 int i;
1198
1199 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1200
1201 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1202 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1203}
1204
1205
1206static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1207 unsigned size)
1208{
1209 struct sk_buff *skb = re->skb;
1210 int i;
1211
1212 re->data_addr = dma_map_single(&pdev->dev, skb->data, size,
1213 DMA_FROM_DEVICE);
1214 if (dma_mapping_error(&pdev->dev, re->data_addr))
1215 goto mapping_error;
1216
1217 dma_unmap_len_set(re, data_size, size);
1218
1219 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1220 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1221
1222 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1223 skb_frag_size(frag),
1224 DMA_FROM_DEVICE);
1225
1226 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1227 goto map_page_error;
1228 }
1229 return 0;
1230
1231map_page_error:
1232 while (--i >= 0) {
1233 dma_unmap_page(&pdev->dev, re->frag_addr[i],
1234 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1235 DMA_FROM_DEVICE);
1236 }
1237
1238 dma_unmap_single(&pdev->dev, re->data_addr,
1239 dma_unmap_len(re, data_size), DMA_FROM_DEVICE);
1240
1241mapping_error:
1242 if (net_ratelimit())
1243 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1244 skb->dev->name);
1245 return -EIO;
1246}
1247
1248static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1249{
1250 struct sk_buff *skb = re->skb;
1251 int i;
1252
1253 dma_unmap_single(&pdev->dev, re->data_addr,
1254 dma_unmap_len(re, data_size), DMA_FROM_DEVICE);
1255
1256 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1257 dma_unmap_page(&pdev->dev, re->frag_addr[i],
1258 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1259 DMA_FROM_DEVICE);
1260}
1261
1262/* Tell chip where to start receive checksum.
1263 * Actually has two checksums, but set both same to avoid possible byte
1264 * order problems.
1265 */
1266static void rx_set_checksum(struct sky2_port *sky2)
1267{
1268 struct sky2_rx_le *le = sky2_next_rx(sky2);
1269
1270 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1271 le->ctrl = 0;
1272 le->opcode = OP_TCPSTART | HW_OWNER;
1273
1274 sky2_write32(sky2->hw,
1275 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1276 (sky2->netdev->features & NETIF_F_RXCSUM)
1277 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1278}
1279
1280/* Enable/disable receive hash calculation (RSS) */
1281static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1282{
1283 struct sky2_port *sky2 = netdev_priv(dev);
1284 struct sky2_hw *hw = sky2->hw;
1285 int i, nkeys = 4;
1286
1287 /* Supports IPv6 and other modes */
1288 if (hw->flags & SKY2_HW_NEW_LE) {
1289 nkeys = 10;
1290 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1291 }
1292
1293 /* Program RSS initial values */
1294 if (features & NETIF_F_RXHASH) {
1295 u32 rss_key[10];
1296
1297 netdev_rss_key_fill(rss_key, sizeof(rss_key));
1298 for (i = 0; i < nkeys; i++)
1299 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1300 rss_key[i]);
1301
1302 /* Need to turn on (undocumented) flag to make hashing work */
1303 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1304 RX_STFW_ENA);
1305
1306 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1307 BMU_ENA_RX_RSS_HASH);
1308 } else
1309 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1310 BMU_DIS_RX_RSS_HASH);
1311}
1312
1313/*
1314 * The RX Stop command will not work for Yukon-2 if the BMU does not
1315 * reach the end of packet and since we can't make sure that we have
1316 * incoming data, we must reset the BMU while it is not doing a DMA
1317 * transfer. Since it is possible that the RX path is still active,
1318 * the RX RAM buffer will be stopped first, so any possible incoming
1319 * data will not trigger a DMA. After the RAM buffer is stopped, the
1320 * BMU is polled until any DMA in progress is ended and only then it
1321 * will be reset.
1322 */
1323static void sky2_rx_stop(struct sky2_port *sky2)
1324{
1325 struct sky2_hw *hw = sky2->hw;
1326 unsigned rxq = rxqaddr[sky2->port];
1327 int i;
1328
1329 /* disable the RAM Buffer receive queue */
1330 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1331
1332 for (i = 0; i < 0xffff; i++)
1333 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1334 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1335 goto stopped;
1336
1337 netdev_warn(sky2->netdev, "receiver stop failed\n");
1338stopped:
1339 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1340
1341 /* reset the Rx prefetch unit */
1342 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1343}
1344
1345/* Clean out receive buffer area, assumes receiver hardware stopped */
1346static void sky2_rx_clean(struct sky2_port *sky2)
1347{
1348 unsigned i;
1349
1350 if (sky2->rx_le)
1351 memset(sky2->rx_le, 0, RX_LE_BYTES);
1352
1353 for (i = 0; i < sky2->rx_pending; i++) {
1354 struct rx_ring_info *re = sky2->rx_ring + i;
1355
1356 if (re->skb) {
1357 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1358 kfree_skb(re->skb);
1359 re->skb = NULL;
1360 }
1361 }
1362}
1363
1364/* Basic MII support */
1365static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1366{
1367 struct mii_ioctl_data *data = if_mii(ifr);
1368 struct sky2_port *sky2 = netdev_priv(dev);
1369 struct sky2_hw *hw = sky2->hw;
1370 int err = -EOPNOTSUPP;
1371
1372 if (!netif_running(dev))
1373 return -ENODEV; /* Phy still in reset */
1374
1375 switch (cmd) {
1376 case SIOCGMIIPHY:
1377 data->phy_id = PHY_ADDR_MARV;
1378
1379 fallthrough;
1380 case SIOCGMIIREG: {
1381 u16 val = 0;
1382
1383 spin_lock_bh(&sky2->phy_lock);
1384 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1385 spin_unlock_bh(&sky2->phy_lock);
1386
1387 data->val_out = val;
1388 break;
1389 }
1390
1391 case SIOCSMIIREG:
1392 spin_lock_bh(&sky2->phy_lock);
1393 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1394 data->val_in);
1395 spin_unlock_bh(&sky2->phy_lock);
1396 break;
1397 }
1398 return err;
1399}
1400
1401#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1402
1403static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1404{
1405 struct sky2_port *sky2 = netdev_priv(dev);
1406 struct sky2_hw *hw = sky2->hw;
1407 u16 port = sky2->port;
1408
1409 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1410 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1411 RX_VLAN_STRIP_ON);
1412 else
1413 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1414 RX_VLAN_STRIP_OFF);
1415
1416 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1417 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1418 TX_VLAN_TAG_ON);
1419
1420 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1421 } else {
1422 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1423 TX_VLAN_TAG_OFF);
1424
1425 /* Can't do transmit offload of vlan without hw vlan */
1426 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1427 }
1428}
1429
1430/* Amount of required worst case padding in rx buffer */
1431static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1432{
1433 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1434}
1435
1436/*
1437 * Allocate an skb for receiving. If the MTU is large enough
1438 * make the skb non-linear with a fragment list of pages.
1439 */
1440static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1441{
1442 struct sk_buff *skb;
1443 int i;
1444
1445 skb = __netdev_alloc_skb(sky2->netdev,
1446 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1447 gfp);
1448 if (!skb)
1449 goto nomem;
1450
1451 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1452 unsigned char *start;
1453 /*
1454 * Workaround for a bug in FIFO that cause hang
1455 * if the FIFO if the receive buffer is not 64 byte aligned.
1456 * The buffer returned from netdev_alloc_skb is
1457 * aligned except if slab debugging is enabled.
1458 */
1459 start = PTR_ALIGN(skb->data, 8);
1460 skb_reserve(skb, start - skb->data);
1461 } else
1462 skb_reserve(skb, NET_IP_ALIGN);
1463
1464 for (i = 0; i < sky2->rx_nfrags; i++) {
1465 struct page *page = alloc_page(gfp);
1466
1467 if (!page)
1468 goto free_partial;
1469 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1470 }
1471
1472 return skb;
1473free_partial:
1474 kfree_skb(skb);
1475nomem:
1476 return NULL;
1477}
1478
1479static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1480{
1481 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1482}
1483
1484static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1485{
1486 struct sky2_hw *hw = sky2->hw;
1487 unsigned i;
1488
1489 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1490
1491 /* Fill Rx ring */
1492 for (i = 0; i < sky2->rx_pending; i++) {
1493 struct rx_ring_info *re = sky2->rx_ring + i;
1494
1495 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1496 if (!re->skb)
1497 return -ENOMEM;
1498
1499 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1500 dev_kfree_skb(re->skb);
1501 re->skb = NULL;
1502 return -ENOMEM;
1503 }
1504 }
1505 return 0;
1506}
1507
1508/*
1509 * Setup receiver buffer pool.
1510 * Normal case this ends up creating one list element for skb
1511 * in the receive ring. Worst case if using large MTU and each
1512 * allocation falls on a different 64 bit region, that results
1513 * in 6 list elements per ring entry.
1514 * One element is used for checksum enable/disable, and one
1515 * extra to avoid wrap.
1516 */
1517static void sky2_rx_start(struct sky2_port *sky2)
1518{
1519 struct sky2_hw *hw = sky2->hw;
1520 struct rx_ring_info *re;
1521 unsigned rxq = rxqaddr[sky2->port];
1522 unsigned i, thresh;
1523
1524 sky2->rx_put = sky2->rx_next = 0;
1525 sky2_qset(hw, rxq);
1526
1527 /* On PCI express lowering the watermark gives better performance */
1528 if (pci_is_pcie(hw->pdev))
1529 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1530
1531 /* These chips have no ram buffer?
1532 * MAC Rx RAM Read is controlled by hardware */
1533 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1534 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1535 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1536
1537 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1538
1539 if (!(hw->flags & SKY2_HW_NEW_LE))
1540 rx_set_checksum(sky2);
1541
1542 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1543 rx_set_rss(sky2->netdev, sky2->netdev->features);
1544
1545 /* submit Rx ring */
1546 for (i = 0; i < sky2->rx_pending; i++) {
1547 re = sky2->rx_ring + i;
1548 sky2_rx_submit(sky2, re);
1549 }
1550
1551 /*
1552 * The receiver hangs if it receives frames larger than the
1553 * packet buffer. As a workaround, truncate oversize frames, but
1554 * the register is limited to 9 bits, so if you do frames > 2052
1555 * you better get the MTU right!
1556 */
1557 thresh = sky2_get_rx_threshold(sky2);
1558 if (thresh > 0x1ff)
1559 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1560 else {
1561 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1562 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1563 }
1564
1565 /* Tell chip about available buffers */
1566 sky2_rx_update(sky2, rxq);
1567
1568 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1569 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1570 /*
1571 * Disable flushing of non ASF packets;
1572 * must be done after initializing the BMUs;
1573 * drivers without ASF support should do this too, otherwise
1574 * it may happen that they cannot run on ASF devices;
1575 * remember that the MAC FIFO isn't reset during initialization.
1576 */
1577 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1578 }
1579
1580 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1581 /* Enable RX Home Address & Routing Header checksum fix */
1582 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1583 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1584
1585 /* Enable TX Home Address & Routing Header checksum fix */
1586 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1587 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1588 }
1589}
1590
1591static int sky2_alloc_buffers(struct sky2_port *sky2)
1592{
1593 struct sky2_hw *hw = sky2->hw;
1594
1595 /* must be power of 2 */
1596 sky2->tx_le = dma_alloc_coherent(&hw->pdev->dev,
1597 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1598 &sky2->tx_le_map, GFP_KERNEL);
1599 if (!sky2->tx_le)
1600 goto nomem;
1601
1602 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1603 GFP_KERNEL);
1604 if (!sky2->tx_ring)
1605 goto nomem;
1606
1607 sky2->rx_le = dma_alloc_coherent(&hw->pdev->dev, RX_LE_BYTES,
1608 &sky2->rx_le_map, GFP_KERNEL);
1609 if (!sky2->rx_le)
1610 goto nomem;
1611
1612 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1613 GFP_KERNEL);
1614 if (!sky2->rx_ring)
1615 goto nomem;
1616
1617 return sky2_alloc_rx_skbs(sky2);
1618nomem:
1619 return -ENOMEM;
1620}
1621
1622static void sky2_free_buffers(struct sky2_port *sky2)
1623{
1624 struct sky2_hw *hw = sky2->hw;
1625
1626 sky2_rx_clean(sky2);
1627
1628 if (sky2->rx_le) {
1629 dma_free_coherent(&hw->pdev->dev, RX_LE_BYTES, sky2->rx_le,
1630 sky2->rx_le_map);
1631 sky2->rx_le = NULL;
1632 }
1633 if (sky2->tx_le) {
1634 dma_free_coherent(&hw->pdev->dev,
1635 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1636 sky2->tx_le, sky2->tx_le_map);
1637 sky2->tx_le = NULL;
1638 }
1639 kfree(sky2->tx_ring);
1640 kfree(sky2->rx_ring);
1641
1642 sky2->tx_ring = NULL;
1643 sky2->rx_ring = NULL;
1644}
1645
1646static void sky2_hw_up(struct sky2_port *sky2)
1647{
1648 struct sky2_hw *hw = sky2->hw;
1649 unsigned port = sky2->port;
1650 u32 ramsize;
1651 int cap;
1652 struct net_device *otherdev = hw->dev[sky2->port^1];
1653
1654 tx_init(sky2);
1655
1656 /*
1657 * On dual port PCI-X card, there is an problem where status
1658 * can be received out of order due to split transactions
1659 */
1660 if (otherdev && netif_running(otherdev) &&
1661 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1662 u16 cmd;
1663
1664 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1665 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1666 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1667 }
1668
1669 sky2_mac_init(hw, port);
1670
1671 /* Register is number of 4K blocks on internal RAM buffer. */
1672 ramsize = sky2_read8(hw, B2_E_0) * 4;
1673 if (ramsize > 0) {
1674 u32 rxspace;
1675
1676 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1677 if (ramsize < 16)
1678 rxspace = ramsize / 2;
1679 else
1680 rxspace = 8 + (2*(ramsize - 16))/3;
1681
1682 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1683 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1684
1685 /* Make sure SyncQ is disabled */
1686 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1687 RB_RST_SET);
1688 }
1689
1690 sky2_qset(hw, txqaddr[port]);
1691
1692 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1693 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1694 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1695
1696 /* Set almost empty threshold */
1697 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1698 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1699 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1700
1701 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1702 sky2->tx_ring_size - 1);
1703
1704 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1705 netdev_update_features(sky2->netdev);
1706
1707 sky2_rx_start(sky2);
1708}
1709
1710/* Setup device IRQ and enable napi to process */
1711static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1712{
1713 struct pci_dev *pdev = hw->pdev;
1714 int err;
1715
1716 err = request_irq(pdev->irq, sky2_intr,
1717 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1718 name, hw);
1719 if (err)
1720 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1721 else {
1722 hw->flags |= SKY2_HW_IRQ_SETUP;
1723
1724 napi_enable(&hw->napi);
1725 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1726 sky2_read32(hw, B0_IMSK);
1727 }
1728
1729 return err;
1730}
1731
1732
1733/* Bring up network interface. */
1734static int sky2_open(struct net_device *dev)
1735{
1736 struct sky2_port *sky2 = netdev_priv(dev);
1737 struct sky2_hw *hw = sky2->hw;
1738 unsigned port = sky2->port;
1739 u32 imask;
1740 int err;
1741
1742 netif_carrier_off(dev);
1743
1744 err = sky2_alloc_buffers(sky2);
1745 if (err)
1746 goto err_out;
1747
1748 /* With single port, IRQ is setup when device is brought up */
1749 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1750 goto err_out;
1751
1752 sky2_hw_up(sky2);
1753
1754 /* Enable interrupts from phy/mac for port */
1755 imask = sky2_read32(hw, B0_IMSK);
1756
1757 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1758 hw->chip_id == CHIP_ID_YUKON_PRM ||
1759 hw->chip_id == CHIP_ID_YUKON_OP_2)
1760 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1761
1762 imask |= portirq_msk[port];
1763 sky2_write32(hw, B0_IMSK, imask);
1764 sky2_read32(hw, B0_IMSK);
1765
1766 netif_info(sky2, ifup, dev, "enabling interface\n");
1767
1768 return 0;
1769
1770err_out:
1771 sky2_free_buffers(sky2);
1772 return err;
1773}
1774
1775/* Modular subtraction in ring */
1776static inline int tx_inuse(const struct sky2_port *sky2)
1777{
1778 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1779}
1780
1781/* Number of list elements available for next tx */
1782static inline int tx_avail(const struct sky2_port *sky2)
1783{
1784 return sky2->tx_pending - tx_inuse(sky2);
1785}
1786
1787/* Estimate of number of transmit list elements required */
1788static unsigned tx_le_req(const struct sk_buff *skb)
1789{
1790 unsigned count;
1791
1792 count = (skb_shinfo(skb)->nr_frags + 1)
1793 * (sizeof(dma_addr_t) / sizeof(u32));
1794
1795 if (skb_is_gso(skb))
1796 ++count;
1797 else if (sizeof(dma_addr_t) == sizeof(u32))
1798 ++count; /* possible vlan */
1799
1800 if (skb->ip_summed == CHECKSUM_PARTIAL)
1801 ++count;
1802
1803 return count;
1804}
1805
1806static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1807{
1808 if (re->flags & TX_MAP_SINGLE)
1809 dma_unmap_single(&pdev->dev, dma_unmap_addr(re, mapaddr),
1810 dma_unmap_len(re, maplen), DMA_TO_DEVICE);
1811 else if (re->flags & TX_MAP_PAGE)
1812 dma_unmap_page(&pdev->dev, dma_unmap_addr(re, mapaddr),
1813 dma_unmap_len(re, maplen), DMA_TO_DEVICE);
1814 re->flags = 0;
1815}
1816
1817/*
1818 * Put one packet in ring for transmit.
1819 * A single packet can generate multiple list elements, and
1820 * the number of ring elements will probably be less than the number
1821 * of list elements used.
1822 */
1823static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1824 struct net_device *dev)
1825{
1826 struct sky2_port *sky2 = netdev_priv(dev);
1827 struct sky2_hw *hw = sky2->hw;
1828 struct sky2_tx_le *le = NULL;
1829 struct tx_ring_info *re;
1830 unsigned i, len;
1831 dma_addr_t mapping;
1832 u32 upper;
1833 u16 slot;
1834 u16 mss;
1835 u8 ctrl;
1836
1837 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1838 return NETDEV_TX_BUSY;
1839
1840 len = skb_headlen(skb);
1841 mapping = dma_map_single(&hw->pdev->dev, skb->data, len,
1842 DMA_TO_DEVICE);
1843
1844 if (dma_mapping_error(&hw->pdev->dev, mapping))
1845 goto mapping_error;
1846
1847 slot = sky2->tx_prod;
1848 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1849 "tx queued, slot %u, len %d\n", slot, skb->len);
1850
1851 /* Send high bits if needed */
1852 upper = upper_32_bits(mapping);
1853 if (upper != sky2->tx_last_upper) {
1854 le = get_tx_le(sky2, &slot);
1855 le->addr = cpu_to_le32(upper);
1856 sky2->tx_last_upper = upper;
1857 le->opcode = OP_ADDR64 | HW_OWNER;
1858 }
1859
1860 /* Check for TCP Segmentation Offload */
1861 mss = skb_shinfo(skb)->gso_size;
1862 if (mss != 0) {
1863
1864 if (!(hw->flags & SKY2_HW_NEW_LE))
1865 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1866
1867 if (mss != sky2->tx_last_mss) {
1868 le = get_tx_le(sky2, &slot);
1869 le->addr = cpu_to_le32(mss);
1870
1871 if (hw->flags & SKY2_HW_NEW_LE)
1872 le->opcode = OP_MSS | HW_OWNER;
1873 else
1874 le->opcode = OP_LRGLEN | HW_OWNER;
1875 sky2->tx_last_mss = mss;
1876 }
1877 }
1878
1879 ctrl = 0;
1880
1881 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1882 if (skb_vlan_tag_present(skb)) {
1883 if (!le) {
1884 le = get_tx_le(sky2, &slot);
1885 le->addr = 0;
1886 le->opcode = OP_VLAN|HW_OWNER;
1887 } else
1888 le->opcode |= OP_VLAN;
1889 le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1890 ctrl |= INS_VLAN;
1891 }
1892
1893 /* Handle TCP checksum offload */
1894 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1895 /* On Yukon EX (some versions) encoding change. */
1896 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1897 ctrl |= CALSUM; /* auto checksum */
1898 else {
1899 const unsigned offset = skb_transport_offset(skb);
1900 u32 tcpsum;
1901
1902 tcpsum = offset << 16; /* sum start */
1903 tcpsum |= offset + skb->csum_offset; /* sum write */
1904
1905 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1906 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1907 ctrl |= UDPTCP;
1908
1909 if (tcpsum != sky2->tx_tcpsum) {
1910 sky2->tx_tcpsum = tcpsum;
1911
1912 le = get_tx_le(sky2, &slot);
1913 le->addr = cpu_to_le32(tcpsum);
1914 le->length = 0; /* initial checksum value */
1915 le->ctrl = 1; /* one packet */
1916 le->opcode = OP_TCPLISW | HW_OWNER;
1917 }
1918 }
1919 }
1920
1921 re = sky2->tx_ring + slot;
1922 re->flags = TX_MAP_SINGLE;
1923 dma_unmap_addr_set(re, mapaddr, mapping);
1924 dma_unmap_len_set(re, maplen, len);
1925
1926 le = get_tx_le(sky2, &slot);
1927 le->addr = cpu_to_le32(lower_32_bits(mapping));
1928 le->length = cpu_to_le16(len);
1929 le->ctrl = ctrl;
1930 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1931
1932
1933 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1934 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1935
1936 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1937 skb_frag_size(frag), DMA_TO_DEVICE);
1938
1939 if (dma_mapping_error(&hw->pdev->dev, mapping))
1940 goto mapping_unwind;
1941
1942 upper = upper_32_bits(mapping);
1943 if (upper != sky2->tx_last_upper) {
1944 le = get_tx_le(sky2, &slot);
1945 le->addr = cpu_to_le32(upper);
1946 sky2->tx_last_upper = upper;
1947 le->opcode = OP_ADDR64 | HW_OWNER;
1948 }
1949
1950 re = sky2->tx_ring + slot;
1951 re->flags = TX_MAP_PAGE;
1952 dma_unmap_addr_set(re, mapaddr, mapping);
1953 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1954
1955 le = get_tx_le(sky2, &slot);
1956 le->addr = cpu_to_le32(lower_32_bits(mapping));
1957 le->length = cpu_to_le16(skb_frag_size(frag));
1958 le->ctrl = ctrl;
1959 le->opcode = OP_BUFFER | HW_OWNER;
1960 }
1961
1962 re->skb = skb;
1963 le->ctrl |= EOP;
1964
1965 sky2->tx_prod = slot;
1966
1967 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1968 netif_stop_queue(dev);
1969
1970 netdev_sent_queue(dev, skb->len);
1971 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1972
1973 return NETDEV_TX_OK;
1974
1975mapping_unwind:
1976 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1977 re = sky2->tx_ring + i;
1978
1979 sky2_tx_unmap(hw->pdev, re);
1980 }
1981
1982mapping_error:
1983 if (net_ratelimit())
1984 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1985 dev_kfree_skb_any(skb);
1986 return NETDEV_TX_OK;
1987}
1988
1989/*
1990 * Free ring elements from starting at tx_cons until "done"
1991 *
1992 * NB:
1993 * 1. The hardware will tell us about partial completion of multi-part
1994 * buffers so make sure not to free skb to early.
1995 * 2. This may run in parallel start_xmit because the it only
1996 * looks at the tail of the queue of FIFO (tx_cons), not
1997 * the head (tx_prod)
1998 */
1999static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2000{
2001 struct net_device *dev = sky2->netdev;
2002 u16 idx;
2003 unsigned int bytes_compl = 0, pkts_compl = 0;
2004
2005 BUG_ON(done >= sky2->tx_ring_size);
2006
2007 for (idx = sky2->tx_cons; idx != done;
2008 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2009 struct tx_ring_info *re = sky2->tx_ring + idx;
2010 struct sk_buff *skb = re->skb;
2011
2012 sky2_tx_unmap(sky2->hw->pdev, re);
2013
2014 if (skb) {
2015 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2016 "tx done %u\n", idx);
2017
2018 pkts_compl++;
2019 bytes_compl += skb->len;
2020
2021 re->skb = NULL;
2022 dev_kfree_skb_any(skb);
2023
2024 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2025 }
2026 }
2027
2028 sky2->tx_cons = idx;
2029 smp_mb();
2030
2031 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2032
2033 u64_stats_update_begin(&sky2->tx_stats.syncp);
2034 sky2->tx_stats.packets += pkts_compl;
2035 sky2->tx_stats.bytes += bytes_compl;
2036 u64_stats_update_end(&sky2->tx_stats.syncp);
2037}
2038
2039static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2040{
2041 /* Disable Force Sync bit and Enable Alloc bit */
2042 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2043 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2044
2045 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2046 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2047 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2048
2049 /* Reset the PCI FIFO of the async Tx queue */
2050 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2051 BMU_RST_SET | BMU_FIFO_RST);
2052
2053 /* Reset the Tx prefetch units */
2054 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2055 PREF_UNIT_RST_SET);
2056
2057 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2058 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2059
2060 sky2_read32(hw, B0_CTST);
2061}
2062
2063static void sky2_hw_down(struct sky2_port *sky2)
2064{
2065 struct sky2_hw *hw = sky2->hw;
2066 unsigned port = sky2->port;
2067 u16 ctrl;
2068
2069 /* Force flow control off */
2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2071
2072 /* Stop transmitter */
2073 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2074 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2075
2076 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2077 RB_RST_SET | RB_DIS_OP_MD);
2078
2079 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2080 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2081 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2082
2083 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2084
2085 /* Workaround shared GMAC reset */
2086 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2087 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2088 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2089
2090 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2091
2092 /* Force any delayed status interrupt and NAPI */
2093 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2094 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2095 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2096 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2097
2098 sky2_rx_stop(sky2);
2099
2100 spin_lock_bh(&sky2->phy_lock);
2101 sky2_phy_power_down(hw, port);
2102 spin_unlock_bh(&sky2->phy_lock);
2103
2104 sky2_tx_reset(hw, port);
2105
2106 /* Free any pending frames stuck in HW queue */
2107 sky2_tx_complete(sky2, sky2->tx_prod);
2108}
2109
2110/* Network shutdown */
2111static int sky2_close(struct net_device *dev)
2112{
2113 struct sky2_port *sky2 = netdev_priv(dev);
2114 struct sky2_hw *hw = sky2->hw;
2115
2116 /* Never really got started! */
2117 if (!sky2->tx_le)
2118 return 0;
2119
2120 netif_info(sky2, ifdown, dev, "disabling interface\n");
2121
2122 if (hw->ports == 1) {
2123 sky2_write32(hw, B0_IMSK, 0);
2124 sky2_read32(hw, B0_IMSK);
2125
2126 napi_disable(&hw->napi);
2127 free_irq(hw->pdev->irq, hw);
2128 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2129 } else {
2130 u32 imask;
2131
2132 /* Disable port IRQ */
2133 imask = sky2_read32(hw, B0_IMSK);
2134 imask &= ~portirq_msk[sky2->port];
2135 sky2_write32(hw, B0_IMSK, imask);
2136 sky2_read32(hw, B0_IMSK);
2137
2138 synchronize_irq(hw->pdev->irq);
2139 napi_synchronize(&hw->napi);
2140 }
2141
2142 sky2_hw_down(sky2);
2143
2144 sky2_free_buffers(sky2);
2145
2146 return 0;
2147}
2148
2149static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2150{
2151 if (hw->flags & SKY2_HW_FIBRE_PHY)
2152 return SPEED_1000;
2153
2154 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2155 if (aux & PHY_M_PS_SPEED_100)
2156 return SPEED_100;
2157 else
2158 return SPEED_10;
2159 }
2160
2161 switch (aux & PHY_M_PS_SPEED_MSK) {
2162 case PHY_M_PS_SPEED_1000:
2163 return SPEED_1000;
2164 case PHY_M_PS_SPEED_100:
2165 return SPEED_100;
2166 default:
2167 return SPEED_10;
2168 }
2169}
2170
2171static void sky2_link_up(struct sky2_port *sky2)
2172{
2173 struct sky2_hw *hw = sky2->hw;
2174 unsigned port = sky2->port;
2175 static const char *fc_name[] = {
2176 [FC_NONE] = "none",
2177 [FC_TX] = "tx",
2178 [FC_RX] = "rx",
2179 [FC_BOTH] = "both",
2180 };
2181
2182 sky2_set_ipg(sky2);
2183
2184 sky2_enable_rx_tx(sky2);
2185
2186 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2187
2188 netif_carrier_on(sky2->netdev);
2189
2190 mod_timer(&hw->watchdog_timer, jiffies + 1);
2191
2192 /* Turn on link LED */
2193 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2194 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2195
2196 netif_info(sky2, link, sky2->netdev,
2197 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2198 sky2->speed,
2199 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2200 fc_name[sky2->flow_status]);
2201}
2202
2203static void sky2_link_down(struct sky2_port *sky2)
2204{
2205 struct sky2_hw *hw = sky2->hw;
2206 unsigned port = sky2->port;
2207 u16 reg;
2208
2209 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2210
2211 reg = gma_read16(hw, port, GM_GP_CTRL);
2212 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2213 gma_write16(hw, port, GM_GP_CTRL, reg);
2214
2215 netif_carrier_off(sky2->netdev);
2216
2217 /* Turn off link LED */
2218 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2219
2220 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2221
2222 sky2_phy_init(hw, port);
2223}
2224
2225static enum flow_control sky2_flow(int rx, int tx)
2226{
2227 if (rx)
2228 return tx ? FC_BOTH : FC_RX;
2229 else
2230 return tx ? FC_TX : FC_NONE;
2231}
2232
2233static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2234{
2235 struct sky2_hw *hw = sky2->hw;
2236 unsigned port = sky2->port;
2237 u16 advert, lpa;
2238
2239 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2240 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2241 if (lpa & PHY_M_AN_RF) {
2242 netdev_err(sky2->netdev, "remote fault\n");
2243 return -1;
2244 }
2245
2246 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2247 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2248 return -1;
2249 }
2250
2251 sky2->speed = sky2_phy_speed(hw, aux);
2252 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2253
2254 /* Since the pause result bits seem to in different positions on
2255 * different chips. look at registers.
2256 */
2257 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2258 /* Shift for bits in fiber PHY */
2259 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2260 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2261
2262 if (advert & ADVERTISE_1000XPAUSE)
2263 advert |= ADVERTISE_PAUSE_CAP;
2264 if (advert & ADVERTISE_1000XPSE_ASYM)
2265 advert |= ADVERTISE_PAUSE_ASYM;
2266 if (lpa & LPA_1000XPAUSE)
2267 lpa |= LPA_PAUSE_CAP;
2268 if (lpa & LPA_1000XPAUSE_ASYM)
2269 lpa |= LPA_PAUSE_ASYM;
2270 }
2271
2272 sky2->flow_status = FC_NONE;
2273 if (advert & ADVERTISE_PAUSE_CAP) {
2274 if (lpa & LPA_PAUSE_CAP)
2275 sky2->flow_status = FC_BOTH;
2276 else if (advert & ADVERTISE_PAUSE_ASYM)
2277 sky2->flow_status = FC_RX;
2278 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2279 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2280 sky2->flow_status = FC_TX;
2281 }
2282
2283 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2284 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2285 sky2->flow_status = FC_NONE;
2286
2287 if (sky2->flow_status & FC_TX)
2288 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2289 else
2290 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2291
2292 return 0;
2293}
2294
2295/* Interrupt from PHY */
2296static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2297{
2298 struct net_device *dev = hw->dev[port];
2299 struct sky2_port *sky2 = netdev_priv(dev);
2300 u16 istatus, phystat;
2301
2302 if (!netif_running(dev))
2303 return;
2304
2305 spin_lock(&sky2->phy_lock);
2306 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2307 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2308
2309 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2310 istatus, phystat);
2311
2312 if (istatus & PHY_M_IS_AN_COMPL) {
2313 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2314 !netif_carrier_ok(dev))
2315 sky2_link_up(sky2);
2316 goto out;
2317 }
2318
2319 if (istatus & PHY_M_IS_LSP_CHANGE)
2320 sky2->speed = sky2_phy_speed(hw, phystat);
2321
2322 if (istatus & PHY_M_IS_DUP_CHANGE)
2323 sky2->duplex =
2324 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2325
2326 if (istatus & PHY_M_IS_LST_CHANGE) {
2327 if (phystat & PHY_M_PS_LINK_UP)
2328 sky2_link_up(sky2);
2329 else
2330 sky2_link_down(sky2);
2331 }
2332out:
2333 spin_unlock(&sky2->phy_lock);
2334}
2335
2336/* Special quick link interrupt (Yukon-2 Optima only) */
2337static void sky2_qlink_intr(struct sky2_hw *hw)
2338{
2339 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2340 u32 imask;
2341 u16 phy;
2342
2343 /* disable irq */
2344 imask = sky2_read32(hw, B0_IMSK);
2345 imask &= ~Y2_IS_PHY_QLNK;
2346 sky2_write32(hw, B0_IMSK, imask);
2347
2348 /* reset PHY Link Detect */
2349 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2350 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2351 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2353
2354 sky2_link_up(sky2);
2355}
2356
2357/* Transmit timeout is only called if we are running, carrier is up
2358 * and tx queue is full (stopped).
2359 */
2360static void sky2_tx_timeout(struct net_device *dev, unsigned int txqueue)
2361{
2362 struct sky2_port *sky2 = netdev_priv(dev);
2363 struct sky2_hw *hw = sky2->hw;
2364
2365 netif_err(sky2, timer, dev, "tx timeout\n");
2366
2367 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2368 sky2->tx_cons, sky2->tx_prod,
2369 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2370 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2371
2372 /* can't restart safely under softirq */
2373 schedule_work(&hw->restart_work);
2374}
2375
2376static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2377{
2378 struct sky2_port *sky2 = netdev_priv(dev);
2379 struct sky2_hw *hw = sky2->hw;
2380 unsigned port = sky2->port;
2381 int err;
2382 u16 ctl, mode;
2383 u32 imask;
2384
2385 if (!netif_running(dev)) {
2386 dev->mtu = new_mtu;
2387 netdev_update_features(dev);
2388 return 0;
2389 }
2390
2391 imask = sky2_read32(hw, B0_IMSK);
2392 sky2_write32(hw, B0_IMSK, 0);
2393 sky2_read32(hw, B0_IMSK);
2394
2395 netif_trans_update(dev); /* prevent tx timeout */
2396 napi_disable(&hw->napi);
2397 netif_tx_disable(dev);
2398
2399 synchronize_irq(hw->pdev->irq);
2400
2401 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2402 sky2_set_tx_stfwd(hw, port);
2403
2404 ctl = gma_read16(hw, port, GM_GP_CTRL);
2405 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2406 sky2_rx_stop(sky2);
2407 sky2_rx_clean(sky2);
2408
2409 dev->mtu = new_mtu;
2410 netdev_update_features(dev);
2411
2412 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2413 if (sky2->speed > SPEED_100)
2414 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2415 else
2416 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2417
2418 if (dev->mtu > ETH_DATA_LEN)
2419 mode |= GM_SMOD_JUMBO_ENA;
2420
2421 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2422
2423 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2424
2425 err = sky2_alloc_rx_skbs(sky2);
2426 if (!err)
2427 sky2_rx_start(sky2);
2428 else
2429 sky2_rx_clean(sky2);
2430 sky2_write32(hw, B0_IMSK, imask);
2431
2432 sky2_read32(hw, B0_Y2_SP_LISR);
2433 napi_enable(&hw->napi);
2434
2435 if (err)
2436 dev_close(dev);
2437 else {
2438 gma_write16(hw, port, GM_GP_CTRL, ctl);
2439
2440 netif_wake_queue(dev);
2441 }
2442
2443 return err;
2444}
2445
2446static inline bool needs_copy(const struct rx_ring_info *re,
2447 unsigned length)
2448{
2449#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2450 /* Some architectures need the IP header to be aligned */
2451 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2452 return true;
2453#endif
2454 return length < copybreak;
2455}
2456
2457/* For small just reuse existing skb for next receive */
2458static struct sk_buff *receive_copy(struct sky2_port *sky2,
2459 const struct rx_ring_info *re,
2460 unsigned length)
2461{
2462 struct sk_buff *skb;
2463
2464 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2465 if (likely(skb)) {
2466 dma_sync_single_for_cpu(&sky2->hw->pdev->dev, re->data_addr,
2467 length, DMA_FROM_DEVICE);
2468 skb_copy_from_linear_data(re->skb, skb->data, length);
2469 skb->ip_summed = re->skb->ip_summed;
2470 skb->csum = re->skb->csum;
2471 skb_copy_hash(skb, re->skb);
2472 __vlan_hwaccel_copy_tag(skb, re->skb);
2473
2474 dma_sync_single_for_device(&sky2->hw->pdev->dev,
2475 re->data_addr, length,
2476 DMA_FROM_DEVICE);
2477 __vlan_hwaccel_clear_tag(re->skb);
2478 skb_clear_hash(re->skb);
2479 re->skb->ip_summed = CHECKSUM_NONE;
2480 skb_put(skb, length);
2481 }
2482 return skb;
2483}
2484
2485/* Adjust length of skb with fragments to match received data */
2486static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2487 unsigned int length)
2488{
2489 int i, num_frags;
2490 unsigned int size;
2491
2492 /* put header into skb */
2493 size = min(length, hdr_space);
2494 skb->tail += size;
2495 skb->len += size;
2496 length -= size;
2497
2498 num_frags = skb_shinfo(skb)->nr_frags;
2499 for (i = 0; i < num_frags; i++) {
2500 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2501
2502 if (length == 0) {
2503 /* don't need this page */
2504 __skb_frag_unref(frag);
2505 --skb_shinfo(skb)->nr_frags;
2506 } else {
2507 size = min(length, (unsigned) PAGE_SIZE);
2508
2509 skb_frag_size_set(frag, size);
2510 skb->data_len += size;
2511 skb->truesize += PAGE_SIZE;
2512 skb->len += size;
2513 length -= size;
2514 }
2515 }
2516}
2517
2518/* Normal packet - take skb from ring element and put in a new one */
2519static struct sk_buff *receive_new(struct sky2_port *sky2,
2520 struct rx_ring_info *re,
2521 unsigned int length)
2522{
2523 struct sk_buff *skb;
2524 struct rx_ring_info nre;
2525 unsigned hdr_space = sky2->rx_data_size;
2526
2527 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2528 if (unlikely(!nre.skb))
2529 goto nobuf;
2530
2531 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2532 goto nomap;
2533
2534 skb = re->skb;
2535 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2536 prefetch(skb->data);
2537 *re = nre;
2538
2539 if (skb_shinfo(skb)->nr_frags)
2540 skb_put_frags(skb, hdr_space, length);
2541 else
2542 skb_put(skb, length);
2543 return skb;
2544
2545nomap:
2546 dev_kfree_skb(nre.skb);
2547nobuf:
2548 return NULL;
2549}
2550
2551/*
2552 * Receive one packet.
2553 * For larger packets, get new buffer.
2554 */
2555static struct sk_buff *sky2_receive(struct net_device *dev,
2556 u16 length, u32 status)
2557{
2558 struct sky2_port *sky2 = netdev_priv(dev);
2559 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2560 struct sk_buff *skb = NULL;
2561 u16 count = (status & GMR_FS_LEN) >> 16;
2562
2563 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2564 "rx slot %u status 0x%x len %d\n",
2565 sky2->rx_next, status, length);
2566
2567 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2568 prefetch(sky2->rx_ring + sky2->rx_next);
2569
2570 if (skb_vlan_tag_present(re->skb))
2571 count -= VLAN_HLEN; /* Account for vlan tag */
2572
2573 /* This chip has hardware problems that generates bogus status.
2574 * So do only marginal checking and expect higher level protocols
2575 * to handle crap frames.
2576 */
2577 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2578 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2579 length != count)
2580 goto okay;
2581
2582 if (status & GMR_FS_ANY_ERR)
2583 goto error;
2584
2585 if (!(status & GMR_FS_RX_OK))
2586 goto resubmit;
2587
2588 /* if length reported by DMA does not match PHY, packet was truncated */
2589 if (length != count)
2590 goto error;
2591
2592okay:
2593 if (needs_copy(re, length))
2594 skb = receive_copy(sky2, re, length);
2595 else
2596 skb = receive_new(sky2, re, length);
2597
2598 dev->stats.rx_dropped += (skb == NULL);
2599
2600resubmit:
2601 sky2_rx_submit(sky2, re);
2602
2603 return skb;
2604
2605error:
2606 ++dev->stats.rx_errors;
2607
2608 if (net_ratelimit())
2609 netif_info(sky2, rx_err, dev,
2610 "rx error, status 0x%x length %d\n", status, length);
2611
2612 goto resubmit;
2613}
2614
2615/* Transmit complete */
2616static inline void sky2_tx_done(struct net_device *dev, u16 last)
2617{
2618 struct sky2_port *sky2 = netdev_priv(dev);
2619
2620 if (netif_running(dev)) {
2621 sky2_tx_complete(sky2, last);
2622
2623 /* Wake unless it's detached, and called e.g. from sky2_close() */
2624 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2625 netif_wake_queue(dev);
2626 }
2627}
2628
2629static inline void sky2_skb_rx(const struct sky2_port *sky2,
2630 struct sk_buff *skb)
2631{
2632 if (skb->ip_summed == CHECKSUM_NONE)
2633 netif_receive_skb(skb);
2634 else
2635 napi_gro_receive(&sky2->hw->napi, skb);
2636}
2637
2638static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2639 unsigned packets, unsigned bytes)
2640{
2641 struct net_device *dev = hw->dev[port];
2642 struct sky2_port *sky2 = netdev_priv(dev);
2643
2644 if (packets == 0)
2645 return;
2646
2647 u64_stats_update_begin(&sky2->rx_stats.syncp);
2648 sky2->rx_stats.packets += packets;
2649 sky2->rx_stats.bytes += bytes;
2650 u64_stats_update_end(&sky2->rx_stats.syncp);
2651
2652 sky2->last_rx = jiffies;
2653 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2654}
2655
2656static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2657{
2658 /* If this happens then driver assuming wrong format for chip type */
2659 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2660
2661 /* Both checksum counters are programmed to start at
2662 * the same offset, so unless there is a problem they
2663 * should match. This failure is an early indication that
2664 * hardware receive checksumming won't work.
2665 */
2666 if (likely((u16)(status >> 16) == (u16)status)) {
2667 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2668 skb->ip_summed = CHECKSUM_COMPLETE;
2669 skb->csum = le16_to_cpu(status);
2670 } else {
2671 dev_notice(&sky2->hw->pdev->dev,
2672 "%s: receive checksum problem (status = %#x)\n",
2673 sky2->netdev->name, status);
2674
2675 /* Disable checksum offload
2676 * It will be reenabled on next ndo_set_features, but if it's
2677 * really broken, will get disabled again
2678 */
2679 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2680 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2681 BMU_DIS_RX_CHKSUM);
2682 }
2683}
2684
2685static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2686{
2687 struct sk_buff *skb;
2688
2689 skb = sky2->rx_ring[sky2->rx_next].skb;
2690 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2691}
2692
2693static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2694{
2695 struct sk_buff *skb;
2696
2697 skb = sky2->rx_ring[sky2->rx_next].skb;
2698 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2699}
2700
2701/* Process status response ring */
2702static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2703{
2704 int work_done = 0;
2705 unsigned int total_bytes[2] = { 0 };
2706 unsigned int total_packets[2] = { 0 };
2707
2708 if (to_do <= 0)
2709 return work_done;
2710
2711 rmb();
2712 do {
2713 struct sky2_port *sky2;
2714 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2715 unsigned port;
2716 struct net_device *dev;
2717 struct sk_buff *skb;
2718 u32 status;
2719 u16 length;
2720 u8 opcode = le->opcode;
2721
2722 if (!(opcode & HW_OWNER))
2723 break;
2724
2725 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2726
2727 port = le->css & CSS_LINK_BIT;
2728 dev = hw->dev[port];
2729 sky2 = netdev_priv(dev);
2730 length = le16_to_cpu(le->length);
2731 status = le32_to_cpu(le->status);
2732
2733 le->opcode = 0;
2734 switch (opcode & ~HW_OWNER) {
2735 case OP_RXSTAT:
2736 total_packets[port]++;
2737 total_bytes[port] += length;
2738
2739 skb = sky2_receive(dev, length, status);
2740 if (!skb)
2741 break;
2742
2743 /* This chip reports checksum status differently */
2744 if (hw->flags & SKY2_HW_NEW_LE) {
2745 if ((dev->features & NETIF_F_RXCSUM) &&
2746 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2747 (le->css & CSS_TCPUDPCSOK))
2748 skb->ip_summed = CHECKSUM_UNNECESSARY;
2749 else
2750 skb->ip_summed = CHECKSUM_NONE;
2751 }
2752
2753 skb->protocol = eth_type_trans(skb, dev);
2754 sky2_skb_rx(sky2, skb);
2755
2756 /* Stop after net poll weight */
2757 if (++work_done >= to_do)
2758 goto exit_loop;
2759 break;
2760
2761 case OP_RXVLAN:
2762 sky2_rx_tag(sky2, length);
2763 break;
2764
2765 case OP_RXCHKSVLAN:
2766 sky2_rx_tag(sky2, length);
2767 fallthrough;
2768 case OP_RXCHKS:
2769 if (likely(dev->features & NETIF_F_RXCSUM))
2770 sky2_rx_checksum(sky2, status);
2771 break;
2772
2773 case OP_RSS_HASH:
2774 sky2_rx_hash(sky2, status);
2775 break;
2776
2777 case OP_TXINDEXLE:
2778 /* TX index reports status for both ports */
2779 sky2_tx_done(hw->dev[0], status & 0xfff);
2780 if (hw->dev[1])
2781 sky2_tx_done(hw->dev[1],
2782 ((status >> 24) & 0xff)
2783 | (u16)(length & 0xf) << 8);
2784 break;
2785
2786 default:
2787 if (net_ratelimit())
2788 pr_warn("unknown status opcode 0x%x\n", opcode);
2789 }
2790 } while (hw->st_idx != idx);
2791
2792 /* Fully processed status ring so clear irq */
2793 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2794
2795exit_loop:
2796 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2797 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2798
2799 return work_done;
2800}
2801
2802static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2803{
2804 struct net_device *dev = hw->dev[port];
2805
2806 if (net_ratelimit())
2807 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2808
2809 if (status & Y2_IS_PAR_RD1) {
2810 if (net_ratelimit())
2811 netdev_err(dev, "ram data read parity error\n");
2812 /* Clear IRQ */
2813 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2814 }
2815
2816 if (status & Y2_IS_PAR_WR1) {
2817 if (net_ratelimit())
2818 netdev_err(dev, "ram data write parity error\n");
2819
2820 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2821 }
2822
2823 if (status & Y2_IS_PAR_MAC1) {
2824 if (net_ratelimit())
2825 netdev_err(dev, "MAC parity error\n");
2826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2827 }
2828
2829 if (status & Y2_IS_PAR_RX1) {
2830 if (net_ratelimit())
2831 netdev_err(dev, "RX parity error\n");
2832 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2833 }
2834
2835 if (status & Y2_IS_TCP_TXA1) {
2836 if (net_ratelimit())
2837 netdev_err(dev, "TCP segmentation error\n");
2838 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2839 }
2840}
2841
2842static void sky2_hw_intr(struct sky2_hw *hw)
2843{
2844 struct pci_dev *pdev = hw->pdev;
2845 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2846 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2847
2848 status &= hwmsk;
2849
2850 if (status & Y2_IS_TIST_OV)
2851 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2852
2853 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2854 u16 pci_err;
2855
2856 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2857 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2858 if (net_ratelimit())
2859 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2860 pci_err);
2861
2862 sky2_pci_write16(hw, PCI_STATUS,
2863 pci_err | PCI_STATUS_ERROR_BITS);
2864 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2865 }
2866
2867 if (status & Y2_IS_PCI_EXP) {
2868 /* PCI-Express uncorrectable Error occurred */
2869 u32 err;
2870
2871 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2872 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2873 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2874 0xfffffffful);
2875 if (net_ratelimit())
2876 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2877
2878 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2879 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2880 }
2881
2882 if (status & Y2_HWE_L1_MASK)
2883 sky2_hw_error(hw, 0, status);
2884 status >>= 8;
2885 if (status & Y2_HWE_L1_MASK)
2886 sky2_hw_error(hw, 1, status);
2887}
2888
2889static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2890{
2891 struct net_device *dev = hw->dev[port];
2892 struct sky2_port *sky2 = netdev_priv(dev);
2893 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2894
2895 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2896
2897 if (status & GM_IS_RX_CO_OV)
2898 gma_read16(hw, port, GM_RX_IRQ_SRC);
2899
2900 if (status & GM_IS_TX_CO_OV)
2901 gma_read16(hw, port, GM_TX_IRQ_SRC);
2902
2903 if (status & GM_IS_RX_FF_OR) {
2904 ++dev->stats.rx_fifo_errors;
2905 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2906 }
2907
2908 if (status & GM_IS_TX_FF_UR) {
2909 ++dev->stats.tx_fifo_errors;
2910 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2911 }
2912}
2913
2914/* This should never happen it is a bug. */
2915static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2916{
2917 struct net_device *dev = hw->dev[port];
2918 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2919
2920 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2921 dev->name, (unsigned) q, (unsigned) idx,
2922 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2923
2924 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2925}
2926
2927static int sky2_rx_hung(struct net_device *dev)
2928{
2929 struct sky2_port *sky2 = netdev_priv(dev);
2930 struct sky2_hw *hw = sky2->hw;
2931 unsigned port = sky2->port;
2932 unsigned rxq = rxqaddr[port];
2933 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2934 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2935 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2936 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2937
2938 /* If idle and MAC or PCI is stuck */
2939 if (sky2->check.last == sky2->last_rx &&
2940 ((mac_rp == sky2->check.mac_rp &&
2941 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2942 /* Check if the PCI RX hang */
2943 (fifo_rp == sky2->check.fifo_rp &&
2944 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2945 netdev_printk(KERN_DEBUG, dev,
2946 "hung mac %d:%d fifo %d (%d:%d)\n",
2947 mac_lev, mac_rp, fifo_lev,
2948 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2949 return 1;
2950 } else {
2951 sky2->check.last = sky2->last_rx;
2952 sky2->check.mac_rp = mac_rp;
2953 sky2->check.mac_lev = mac_lev;
2954 sky2->check.fifo_rp = fifo_rp;
2955 sky2->check.fifo_lev = fifo_lev;
2956 return 0;
2957 }
2958}
2959
2960static void sky2_watchdog(struct timer_list *t)
2961{
2962 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer);
2963
2964 /* Check for lost IRQ once a second */
2965 if (sky2_read32(hw, B0_ISRC)) {
2966 napi_schedule(&hw->napi);
2967 } else {
2968 int i, active = 0;
2969
2970 for (i = 0; i < hw->ports; i++) {
2971 struct net_device *dev = hw->dev[i];
2972 if (!netif_running(dev))
2973 continue;
2974 ++active;
2975
2976 /* For chips with Rx FIFO, check if stuck */
2977 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2978 sky2_rx_hung(dev)) {
2979 netdev_info(dev, "receiver hang detected\n");
2980 schedule_work(&hw->restart_work);
2981 return;
2982 }
2983 }
2984
2985 if (active == 0)
2986 return;
2987 }
2988
2989 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2990}
2991
2992/* Hardware/software error handling */
2993static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2994{
2995 if (net_ratelimit())
2996 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2997
2998 if (status & Y2_IS_HW_ERR)
2999 sky2_hw_intr(hw);
3000
3001 if (status & Y2_IS_IRQ_MAC1)
3002 sky2_mac_intr(hw, 0);
3003
3004 if (status & Y2_IS_IRQ_MAC2)
3005 sky2_mac_intr(hw, 1);
3006
3007 if (status & Y2_IS_CHK_RX1)
3008 sky2_le_error(hw, 0, Q_R1);
3009
3010 if (status & Y2_IS_CHK_RX2)
3011 sky2_le_error(hw, 1, Q_R2);
3012
3013 if (status & Y2_IS_CHK_TXA1)
3014 sky2_le_error(hw, 0, Q_XA1);
3015
3016 if (status & Y2_IS_CHK_TXA2)
3017 sky2_le_error(hw, 1, Q_XA2);
3018}
3019
3020static int sky2_poll(struct napi_struct *napi, int work_limit)
3021{
3022 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3023 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3024 int work_done = 0;
3025 u16 idx;
3026
3027 if (unlikely(status & Y2_IS_ERROR))
3028 sky2_err_intr(hw, status);
3029
3030 if (status & Y2_IS_IRQ_PHY1)
3031 sky2_phy_intr(hw, 0);
3032
3033 if (status & Y2_IS_IRQ_PHY2)
3034 sky2_phy_intr(hw, 1);
3035
3036 if (status & Y2_IS_PHY_QLNK)
3037 sky2_qlink_intr(hw);
3038
3039 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3040 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3041
3042 if (work_done >= work_limit)
3043 goto done;
3044 }
3045
3046 napi_complete_done(napi, work_done);
3047 sky2_read32(hw, B0_Y2_SP_LISR);
3048done:
3049
3050 return work_done;
3051}
3052
3053static irqreturn_t sky2_intr(int irq, void *dev_id)
3054{
3055 struct sky2_hw *hw = dev_id;
3056 u32 status;
3057
3058 /* Reading this mask interrupts as side effect */
3059 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3060 if (status == 0 || status == ~0) {
3061 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3062 return IRQ_NONE;
3063 }
3064
3065 prefetch(&hw->st_le[hw->st_idx]);
3066
3067 napi_schedule(&hw->napi);
3068
3069 return IRQ_HANDLED;
3070}
3071
3072#ifdef CONFIG_NET_POLL_CONTROLLER
3073static void sky2_netpoll(struct net_device *dev)
3074{
3075 struct sky2_port *sky2 = netdev_priv(dev);
3076
3077 napi_schedule(&sky2->hw->napi);
3078}
3079#endif
3080
3081/* Chip internal frequency for clock calculations */
3082static u32 sky2_mhz(const struct sky2_hw *hw)
3083{
3084 switch (hw->chip_id) {
3085 case CHIP_ID_YUKON_EC:
3086 case CHIP_ID_YUKON_EC_U:
3087 case CHIP_ID_YUKON_EX:
3088 case CHIP_ID_YUKON_SUPR:
3089 case CHIP_ID_YUKON_UL_2:
3090 case CHIP_ID_YUKON_OPT:
3091 case CHIP_ID_YUKON_PRM:
3092 case CHIP_ID_YUKON_OP_2:
3093 return 125;
3094
3095 case CHIP_ID_YUKON_FE:
3096 return 100;
3097
3098 case CHIP_ID_YUKON_FE_P:
3099 return 50;
3100
3101 case CHIP_ID_YUKON_XL:
3102 return 156;
3103
3104 default:
3105 BUG();
3106 }
3107}
3108
3109static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3110{
3111 return sky2_mhz(hw) * us;
3112}
3113
3114static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3115{
3116 return clk / sky2_mhz(hw);
3117}
3118
3119
3120static int sky2_init(struct sky2_hw *hw)
3121{
3122 u8 t8;
3123
3124 /* Enable all clocks and check for bad PCI access */
3125 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3126
3127 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3128
3129 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3130 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3131
3132 switch (hw->chip_id) {
3133 case CHIP_ID_YUKON_XL:
3134 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3135 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3136 hw->flags |= SKY2_HW_RSS_BROKEN;
3137 break;
3138
3139 case CHIP_ID_YUKON_EC_U:
3140 hw->flags = SKY2_HW_GIGABIT
3141 | SKY2_HW_NEWER_PHY
3142 | SKY2_HW_ADV_POWER_CTL;
3143 break;
3144
3145 case CHIP_ID_YUKON_EX:
3146 hw->flags = SKY2_HW_GIGABIT
3147 | SKY2_HW_NEWER_PHY
3148 | SKY2_HW_NEW_LE
3149 | SKY2_HW_ADV_POWER_CTL
3150 | SKY2_HW_RSS_CHKSUM;
3151
3152 /* New transmit checksum */
3153 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3154 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3155 break;
3156
3157 case CHIP_ID_YUKON_EC:
3158 /* This rev is really old, and requires untested workarounds */
3159 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3160 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3161 return -EOPNOTSUPP;
3162 }
3163 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3164 break;
3165
3166 case CHIP_ID_YUKON_FE:
3167 hw->flags = SKY2_HW_RSS_BROKEN;
3168 break;
3169
3170 case CHIP_ID_YUKON_FE_P:
3171 hw->flags = SKY2_HW_NEWER_PHY
3172 | SKY2_HW_NEW_LE
3173 | SKY2_HW_AUTO_TX_SUM
3174 | SKY2_HW_ADV_POWER_CTL;
3175
3176 /* The workaround for status conflicts VLAN tag detection. */
3177 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3178 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3179 break;
3180
3181 case CHIP_ID_YUKON_SUPR:
3182 hw->flags = SKY2_HW_GIGABIT
3183 | SKY2_HW_NEWER_PHY
3184 | SKY2_HW_NEW_LE
3185 | SKY2_HW_AUTO_TX_SUM
3186 | SKY2_HW_ADV_POWER_CTL;
3187
3188 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3189 hw->flags |= SKY2_HW_RSS_CHKSUM;
3190 break;
3191
3192 case CHIP_ID_YUKON_UL_2:
3193 hw->flags = SKY2_HW_GIGABIT
3194 | SKY2_HW_ADV_POWER_CTL;
3195 break;
3196
3197 case CHIP_ID_YUKON_OPT:
3198 case CHIP_ID_YUKON_PRM:
3199 case CHIP_ID_YUKON_OP_2:
3200 hw->flags = SKY2_HW_GIGABIT
3201 | SKY2_HW_NEW_LE
3202 | SKY2_HW_ADV_POWER_CTL;
3203 break;
3204
3205 default:
3206 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3207 hw->chip_id);
3208 return -EOPNOTSUPP;
3209 }
3210
3211 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3212 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3213 hw->flags |= SKY2_HW_FIBRE_PHY;
3214
3215 hw->ports = 1;
3216 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3217 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3218 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3219 ++hw->ports;
3220 }
3221
3222 if (sky2_read8(hw, B2_E_0))
3223 hw->flags |= SKY2_HW_RAM_BUFFER;
3224
3225 return 0;
3226}
3227
3228static void sky2_reset(struct sky2_hw *hw)
3229{
3230 struct pci_dev *pdev = hw->pdev;
3231 u16 status;
3232 int i;
3233 u32 hwe_mask = Y2_HWE_ALL_MASK;
3234
3235 /* disable ASF */
3236 if (hw->chip_id == CHIP_ID_YUKON_EX
3237 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3238 sky2_write32(hw, CPU_WDOG, 0);
3239 status = sky2_read16(hw, HCU_CCSR);
3240 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3241 HCU_CCSR_UC_STATE_MSK);
3242 /*
3243 * CPU clock divider shouldn't be used because
3244 * - ASF firmware may malfunction
3245 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3246 */
3247 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3248 sky2_write16(hw, HCU_CCSR, status);
3249 sky2_write32(hw, CPU_WDOG, 0);
3250 } else
3251 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3252 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3253
3254 /* do a SW reset */
3255 sky2_write8(hw, B0_CTST, CS_RST_SET);
3256 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3257
3258 /* allow writes to PCI config */
3259 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3260
3261 /* clear PCI errors, if any */
3262 status = sky2_pci_read16(hw, PCI_STATUS);
3263 status |= PCI_STATUS_ERROR_BITS;
3264 sky2_pci_write16(hw, PCI_STATUS, status);
3265
3266 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3267
3268 if (pci_is_pcie(pdev)) {
3269 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3270 0xfffffffful);
3271
3272 /* If error bit is stuck on ignore it */
3273 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3274 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3275 else
3276 hwe_mask |= Y2_IS_PCI_EXP;
3277 }
3278
3279 sky2_power_on(hw);
3280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3281
3282 for (i = 0; i < hw->ports; i++) {
3283 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3284 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3285
3286 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3287 hw->chip_id == CHIP_ID_YUKON_SUPR)
3288 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3289 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3290 | GMC_BYP_RETR_ON);
3291
3292 }
3293
3294 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3295 /* enable MACSec clock gating */
3296 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3297 }
3298
3299 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3300 hw->chip_id == CHIP_ID_YUKON_PRM ||
3301 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3302 u16 reg;
3303
3304 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3305 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3306 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3307
3308 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3309 reg = 10;
3310
3311 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3312 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3313 } else {
3314 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3315 reg = 3;
3316 }
3317
3318 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3319 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3320
3321 /* reset PHY Link Detect */
3322 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3323 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3324
3325 /* check if PSMv2 was running before */
3326 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3327 if (reg & PCI_EXP_LNKCTL_ASPMC)
3328 /* restore the PCIe Link Control register */
3329 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3330 reg);
3331
3332 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3333 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3334 /* change PHY Interrupt polarity to low active */
3335 reg = sky2_read16(hw, GPHY_CTRL);
3336 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3337
3338 /* adapt HW for low active PHY Interrupt */
3339 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3340 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3341 }
3342
3343 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3344
3345 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3346 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3347 }
3348
3349 /* Clear I2C IRQ noise */
3350 sky2_write32(hw, B2_I2C_IRQ, 1);
3351
3352 /* turn off hardware timer (unused) */
3353 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3354 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3355
3356 /* Turn off descriptor polling */
3357 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3358
3359 /* Turn off receive timestamp */
3360 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3361 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3362
3363 /* enable the Tx Arbiters */
3364 for (i = 0; i < hw->ports; i++)
3365 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3366
3367 /* Initialize ram interface */
3368 for (i = 0; i < hw->ports; i++) {
3369 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3370
3371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3372 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3374 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3383 }
3384
3385 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3386
3387 for (i = 0; i < hw->ports; i++)
3388 sky2_gmac_reset(hw, i);
3389
3390 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3391 hw->st_idx = 0;
3392
3393 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3394 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3395
3396 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3397 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3398
3399 /* Set the list last index */
3400 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3401
3402 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3403 sky2_write8(hw, STAT_FIFO_WM, 16);
3404
3405 /* set Status-FIFO ISR watermark */
3406 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3407 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3408 else
3409 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3410
3411 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3412 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3413 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3414
3415 /* enable status unit */
3416 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3417
3418 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3419 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3420 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3421}
3422
3423/* Take device down (offline).
3424 * Equivalent to doing dev_stop() but this does not
3425 * inform upper layers of the transition.
3426 */
3427static void sky2_detach(struct net_device *dev)
3428{
3429 if (netif_running(dev)) {
3430 netif_tx_lock(dev);
3431 netif_device_detach(dev); /* stop txq */
3432 netif_tx_unlock(dev);
3433 sky2_close(dev);
3434 }
3435}
3436
3437/* Bring device back after doing sky2_detach */
3438static int sky2_reattach(struct net_device *dev)
3439{
3440 int err = 0;
3441
3442 if (netif_running(dev)) {
3443 err = sky2_open(dev);
3444 if (err) {
3445 netdev_info(dev, "could not restart %d\n", err);
3446 dev_close(dev);
3447 } else {
3448 netif_device_attach(dev);
3449 sky2_set_multicast(dev);
3450 }
3451 }
3452
3453 return err;
3454}
3455
3456static void sky2_all_down(struct sky2_hw *hw)
3457{
3458 int i;
3459
3460 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3461 sky2_write32(hw, B0_IMSK, 0);
3462 sky2_read32(hw, B0_IMSK);
3463
3464 synchronize_irq(hw->pdev->irq);
3465 napi_disable(&hw->napi);
3466 }
3467
3468 for (i = 0; i < hw->ports; i++) {
3469 struct net_device *dev = hw->dev[i];
3470 struct sky2_port *sky2 = netdev_priv(dev);
3471
3472 if (!netif_running(dev))
3473 continue;
3474
3475 netif_carrier_off(dev);
3476 netif_tx_disable(dev);
3477 sky2_hw_down(sky2);
3478 }
3479}
3480
3481static void sky2_all_up(struct sky2_hw *hw)
3482{
3483 u32 imask = Y2_IS_BASE;
3484 int i;
3485
3486 for (i = 0; i < hw->ports; i++) {
3487 struct net_device *dev = hw->dev[i];
3488 struct sky2_port *sky2 = netdev_priv(dev);
3489
3490 if (!netif_running(dev))
3491 continue;
3492
3493 sky2_hw_up(sky2);
3494 sky2_set_multicast(dev);
3495 imask |= portirq_msk[i];
3496 netif_wake_queue(dev);
3497 }
3498
3499 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3500 sky2_write32(hw, B0_IMSK, imask);
3501 sky2_read32(hw, B0_IMSK);
3502 sky2_read32(hw, B0_Y2_SP_LISR);
3503 napi_enable(&hw->napi);
3504 }
3505}
3506
3507static void sky2_restart(struct work_struct *work)
3508{
3509 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3510
3511 rtnl_lock();
3512
3513 sky2_all_down(hw);
3514 sky2_reset(hw);
3515 sky2_all_up(hw);
3516
3517 rtnl_unlock();
3518}
3519
3520static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3521{
3522 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3523}
3524
3525static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3526{
3527 const struct sky2_port *sky2 = netdev_priv(dev);
3528
3529 wol->supported = sky2_wol_supported(sky2->hw);
3530 wol->wolopts = sky2->wol;
3531}
3532
3533static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3534{
3535 struct sky2_port *sky2 = netdev_priv(dev);
3536 struct sky2_hw *hw = sky2->hw;
3537 bool enable_wakeup = false;
3538 int i;
3539
3540 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3541 !device_can_wakeup(&hw->pdev->dev))
3542 return -EOPNOTSUPP;
3543
3544 sky2->wol = wol->wolopts;
3545
3546 for (i = 0; i < hw->ports; i++) {
3547 struct net_device *dev = hw->dev[i];
3548 struct sky2_port *sky2 = netdev_priv(dev);
3549
3550 if (sky2->wol)
3551 enable_wakeup = true;
3552 }
3553 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3554
3555 return 0;
3556}
3557
3558static u32 sky2_supported_modes(const struct sky2_hw *hw)
3559{
3560 if (sky2_is_copper(hw)) {
3561 u32 modes = SUPPORTED_10baseT_Half
3562 | SUPPORTED_10baseT_Full
3563 | SUPPORTED_100baseT_Half
3564 | SUPPORTED_100baseT_Full;
3565
3566 if (hw->flags & SKY2_HW_GIGABIT)
3567 modes |= SUPPORTED_1000baseT_Half
3568 | SUPPORTED_1000baseT_Full;
3569 return modes;
3570 } else
3571 return SUPPORTED_1000baseT_Half
3572 | SUPPORTED_1000baseT_Full;
3573}
3574
3575static int sky2_get_link_ksettings(struct net_device *dev,
3576 struct ethtool_link_ksettings *cmd)
3577{
3578 struct sky2_port *sky2 = netdev_priv(dev);
3579 struct sky2_hw *hw = sky2->hw;
3580 u32 supported, advertising;
3581
3582 supported = sky2_supported_modes(hw);
3583 cmd->base.phy_address = PHY_ADDR_MARV;
3584 if (sky2_is_copper(hw)) {
3585 cmd->base.port = PORT_TP;
3586 cmd->base.speed = sky2->speed;
3587 supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3588 } else {
3589 cmd->base.speed = SPEED_1000;
3590 cmd->base.port = PORT_FIBRE;
3591 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3592 }
3593
3594 advertising = sky2->advertising;
3595 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3596 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3597 cmd->base.duplex = sky2->duplex;
3598
3599 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3600 supported);
3601 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3602 advertising);
3603
3604 return 0;
3605}
3606
3607static int sky2_set_link_ksettings(struct net_device *dev,
3608 const struct ethtool_link_ksettings *cmd)
3609{
3610 struct sky2_port *sky2 = netdev_priv(dev);
3611 const struct sky2_hw *hw = sky2->hw;
3612 u32 supported = sky2_supported_modes(hw);
3613 u32 new_advertising;
3614
3615 ethtool_convert_link_mode_to_legacy_u32(&new_advertising,
3616 cmd->link_modes.advertising);
3617
3618 if (cmd->base.autoneg == AUTONEG_ENABLE) {
3619 if (new_advertising & ~supported)
3620 return -EINVAL;
3621
3622 if (sky2_is_copper(hw))
3623 sky2->advertising = new_advertising |
3624 ADVERTISED_TP |
3625 ADVERTISED_Autoneg;
3626 else
3627 sky2->advertising = new_advertising |
3628 ADVERTISED_FIBRE |
3629 ADVERTISED_Autoneg;
3630
3631 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3632 sky2->duplex = -1;
3633 sky2->speed = -1;
3634 } else {
3635 u32 setting;
3636 u32 speed = cmd->base.speed;
3637
3638 switch (speed) {
3639 case SPEED_1000:
3640 if (cmd->base.duplex == DUPLEX_FULL)
3641 setting = SUPPORTED_1000baseT_Full;
3642 else if (cmd->base.duplex == DUPLEX_HALF)
3643 setting = SUPPORTED_1000baseT_Half;
3644 else
3645 return -EINVAL;
3646 break;
3647 case SPEED_100:
3648 if (cmd->base.duplex == DUPLEX_FULL)
3649 setting = SUPPORTED_100baseT_Full;
3650 else if (cmd->base.duplex == DUPLEX_HALF)
3651 setting = SUPPORTED_100baseT_Half;
3652 else
3653 return -EINVAL;
3654 break;
3655
3656 case SPEED_10:
3657 if (cmd->base.duplex == DUPLEX_FULL)
3658 setting = SUPPORTED_10baseT_Full;
3659 else if (cmd->base.duplex == DUPLEX_HALF)
3660 setting = SUPPORTED_10baseT_Half;
3661 else
3662 return -EINVAL;
3663 break;
3664 default:
3665 return -EINVAL;
3666 }
3667
3668 if ((setting & supported) == 0)
3669 return -EINVAL;
3670
3671 sky2->speed = speed;
3672 sky2->duplex = cmd->base.duplex;
3673 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3674 }
3675
3676 if (netif_running(dev)) {
3677 sky2_phy_reinit(sky2);
3678 sky2_set_multicast(dev);
3679 }
3680
3681 return 0;
3682}
3683
3684static void sky2_get_drvinfo(struct net_device *dev,
3685 struct ethtool_drvinfo *info)
3686{
3687 struct sky2_port *sky2 = netdev_priv(dev);
3688
3689 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3690 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3691 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3692 sizeof(info->bus_info));
3693}
3694
3695static const struct sky2_stat {
3696 char name[ETH_GSTRING_LEN];
3697 u16 offset;
3698} sky2_stats[] = {
3699 { "tx_bytes", GM_TXO_OK_HI },
3700 { "rx_bytes", GM_RXO_OK_HI },
3701 { "tx_broadcast", GM_TXF_BC_OK },
3702 { "rx_broadcast", GM_RXF_BC_OK },
3703 { "tx_multicast", GM_TXF_MC_OK },
3704 { "rx_multicast", GM_RXF_MC_OK },
3705 { "tx_unicast", GM_TXF_UC_OK },
3706 { "rx_unicast", GM_RXF_UC_OK },
3707 { "tx_mac_pause", GM_TXF_MPAUSE },
3708 { "rx_mac_pause", GM_RXF_MPAUSE },
3709 { "collisions", GM_TXF_COL },
3710 { "late_collision",GM_TXF_LAT_COL },
3711 { "aborted", GM_TXF_ABO_COL },
3712 { "single_collisions", GM_TXF_SNG_COL },
3713 { "multi_collisions", GM_TXF_MUL_COL },
3714
3715 { "rx_short", GM_RXF_SHT },
3716 { "rx_runt", GM_RXE_FRAG },
3717 { "rx_64_byte_packets", GM_RXF_64B },
3718 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3719 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3720 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3721 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3722 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3723 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3724 { "rx_too_long", GM_RXF_LNG_ERR },
3725 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3726 { "rx_jabber", GM_RXF_JAB_PKT },
3727 { "rx_fcs_error", GM_RXF_FCS_ERR },
3728
3729 { "tx_64_byte_packets", GM_TXF_64B },
3730 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3731 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3732 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3733 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3734 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3735 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3736 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3737};
3738
3739static u32 sky2_get_msglevel(struct net_device *netdev)
3740{
3741 struct sky2_port *sky2 = netdev_priv(netdev);
3742 return sky2->msg_enable;
3743}
3744
3745static int sky2_nway_reset(struct net_device *dev)
3746{
3747 struct sky2_port *sky2 = netdev_priv(dev);
3748
3749 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3750 return -EINVAL;
3751
3752 sky2_phy_reinit(sky2);
3753 sky2_set_multicast(dev);
3754
3755 return 0;
3756}
3757
3758static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3759{
3760 struct sky2_hw *hw = sky2->hw;
3761 unsigned port = sky2->port;
3762 int i;
3763
3764 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3765 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3766
3767 for (i = 2; i < count; i++)
3768 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3769}
3770
3771static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3772{
3773 struct sky2_port *sky2 = netdev_priv(netdev);
3774 sky2->msg_enable = value;
3775}
3776
3777static int sky2_get_sset_count(struct net_device *dev, int sset)
3778{
3779 switch (sset) {
3780 case ETH_SS_STATS:
3781 return ARRAY_SIZE(sky2_stats);
3782 default:
3783 return -EOPNOTSUPP;
3784 }
3785}
3786
3787static void sky2_get_ethtool_stats(struct net_device *dev,
3788 struct ethtool_stats *stats, u64 * data)
3789{
3790 struct sky2_port *sky2 = netdev_priv(dev);
3791
3792 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3793}
3794
3795static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3796{
3797 int i;
3798
3799 switch (stringset) {
3800 case ETH_SS_STATS:
3801 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3802 memcpy(data + i * ETH_GSTRING_LEN,
3803 sky2_stats[i].name, ETH_GSTRING_LEN);
3804 break;
3805 }
3806}
3807
3808static int sky2_set_mac_address(struct net_device *dev, void *p)
3809{
3810 struct sky2_port *sky2 = netdev_priv(dev);
3811 struct sky2_hw *hw = sky2->hw;
3812 unsigned port = sky2->port;
3813 const struct sockaddr *addr = p;
3814
3815 if (!is_valid_ether_addr(addr->sa_data))
3816 return -EADDRNOTAVAIL;
3817
3818 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3819 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3820 dev->dev_addr, ETH_ALEN);
3821 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3822 dev->dev_addr, ETH_ALEN);
3823
3824 /* virtual address for data */
3825 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3826
3827 /* physical address: used for pause frames */
3828 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3829
3830 return 0;
3831}
3832
3833static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3834{
3835 u32 bit;
3836
3837 bit = ether_crc(ETH_ALEN, addr) & 63;
3838 filter[bit >> 3] |= 1 << (bit & 7);
3839}
3840
3841static void sky2_set_multicast(struct net_device *dev)
3842{
3843 struct sky2_port *sky2 = netdev_priv(dev);
3844 struct sky2_hw *hw = sky2->hw;
3845 unsigned port = sky2->port;
3846 struct netdev_hw_addr *ha;
3847 u16 reg;
3848 u8 filter[8];
3849 int rx_pause;
3850 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3851
3852 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3853 memset(filter, 0, sizeof(filter));
3854
3855 reg = gma_read16(hw, port, GM_RX_CTRL);
3856 reg |= GM_RXCR_UCF_ENA;
3857
3858 if (dev->flags & IFF_PROMISC) /* promiscuous */
3859 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3860 else if (dev->flags & IFF_ALLMULTI)
3861 memset(filter, 0xff, sizeof(filter));
3862 else if (netdev_mc_empty(dev) && !rx_pause)
3863 reg &= ~GM_RXCR_MCF_ENA;
3864 else {
3865 reg |= GM_RXCR_MCF_ENA;
3866
3867 if (rx_pause)
3868 sky2_add_filter(filter, pause_mc_addr);
3869
3870 netdev_for_each_mc_addr(ha, dev)
3871 sky2_add_filter(filter, ha->addr);
3872 }
3873
3874 gma_write16(hw, port, GM_MC_ADDR_H1,
3875 (u16) filter[0] | ((u16) filter[1] << 8));
3876 gma_write16(hw, port, GM_MC_ADDR_H2,
3877 (u16) filter[2] | ((u16) filter[3] << 8));
3878 gma_write16(hw, port, GM_MC_ADDR_H3,
3879 (u16) filter[4] | ((u16) filter[5] << 8));
3880 gma_write16(hw, port, GM_MC_ADDR_H4,
3881 (u16) filter[6] | ((u16) filter[7] << 8));
3882
3883 gma_write16(hw, port, GM_RX_CTRL, reg);
3884}
3885
3886static void sky2_get_stats(struct net_device *dev,
3887 struct rtnl_link_stats64 *stats)
3888{
3889 struct sky2_port *sky2 = netdev_priv(dev);
3890 struct sky2_hw *hw = sky2->hw;
3891 unsigned port = sky2->port;
3892 unsigned int start;
3893 u64 _bytes, _packets;
3894
3895 do {
3896 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp);
3897 _bytes = sky2->rx_stats.bytes;
3898 _packets = sky2->rx_stats.packets;
3899 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start));
3900
3901 stats->rx_packets = _packets;
3902 stats->rx_bytes = _bytes;
3903
3904 do {
3905 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp);
3906 _bytes = sky2->tx_stats.bytes;
3907 _packets = sky2->tx_stats.packets;
3908 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start));
3909
3910 stats->tx_packets = _packets;
3911 stats->tx_bytes = _bytes;
3912
3913 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3914 + get_stats32(hw, port, GM_RXF_BC_OK);
3915
3916 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3917
3918 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3919 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3920 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3921 + get_stats32(hw, port, GM_RXE_FRAG);
3922 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3923
3924 stats->rx_dropped = dev->stats.rx_dropped;
3925 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3926 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3927}
3928
3929/* Can have one global because blinking is controlled by
3930 * ethtool and that is always under RTNL mutex
3931 */
3932static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3933{
3934 struct sky2_hw *hw = sky2->hw;
3935 unsigned port = sky2->port;
3936
3937 spin_lock_bh(&sky2->phy_lock);
3938 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3939 hw->chip_id == CHIP_ID_YUKON_EX ||
3940 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3941 u16 pg;
3942 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3943 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3944
3945 switch (mode) {
3946 case MO_LED_OFF:
3947 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3948 PHY_M_LEDC_LOS_CTRL(8) |
3949 PHY_M_LEDC_INIT_CTRL(8) |
3950 PHY_M_LEDC_STA1_CTRL(8) |
3951 PHY_M_LEDC_STA0_CTRL(8));
3952 break;
3953 case MO_LED_ON:
3954 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3955 PHY_M_LEDC_LOS_CTRL(9) |
3956 PHY_M_LEDC_INIT_CTRL(9) |
3957 PHY_M_LEDC_STA1_CTRL(9) |
3958 PHY_M_LEDC_STA0_CTRL(9));
3959 break;
3960 case MO_LED_BLINK:
3961 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3962 PHY_M_LEDC_LOS_CTRL(0xa) |
3963 PHY_M_LEDC_INIT_CTRL(0xa) |
3964 PHY_M_LEDC_STA1_CTRL(0xa) |
3965 PHY_M_LEDC_STA0_CTRL(0xa));
3966 break;
3967 case MO_LED_NORM:
3968 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3969 PHY_M_LEDC_LOS_CTRL(1) |
3970 PHY_M_LEDC_INIT_CTRL(8) |
3971 PHY_M_LEDC_STA1_CTRL(7) |
3972 PHY_M_LEDC_STA0_CTRL(7));
3973 }
3974
3975 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3976 } else
3977 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3978 PHY_M_LED_MO_DUP(mode) |
3979 PHY_M_LED_MO_10(mode) |
3980 PHY_M_LED_MO_100(mode) |
3981 PHY_M_LED_MO_1000(mode) |
3982 PHY_M_LED_MO_RX(mode) |
3983 PHY_M_LED_MO_TX(mode));
3984
3985 spin_unlock_bh(&sky2->phy_lock);
3986}
3987
3988/* blink LED's for finding board */
3989static int sky2_set_phys_id(struct net_device *dev,
3990 enum ethtool_phys_id_state state)
3991{
3992 struct sky2_port *sky2 = netdev_priv(dev);
3993
3994 switch (state) {
3995 case ETHTOOL_ID_ACTIVE:
3996 return 1; /* cycle on/off once per second */
3997 case ETHTOOL_ID_INACTIVE:
3998 sky2_led(sky2, MO_LED_NORM);
3999 break;
4000 case ETHTOOL_ID_ON:
4001 sky2_led(sky2, MO_LED_ON);
4002 break;
4003 case ETHTOOL_ID_OFF:
4004 sky2_led(sky2, MO_LED_OFF);
4005 break;
4006 }
4007
4008 return 0;
4009}
4010
4011static void sky2_get_pauseparam(struct net_device *dev,
4012 struct ethtool_pauseparam *ecmd)
4013{
4014 struct sky2_port *sky2 = netdev_priv(dev);
4015
4016 switch (sky2->flow_mode) {
4017 case FC_NONE:
4018 ecmd->tx_pause = ecmd->rx_pause = 0;
4019 break;
4020 case FC_TX:
4021 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4022 break;
4023 case FC_RX:
4024 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4025 break;
4026 case FC_BOTH:
4027 ecmd->tx_pause = ecmd->rx_pause = 1;
4028 }
4029
4030 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4031 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4032}
4033
4034static int sky2_set_pauseparam(struct net_device *dev,
4035 struct ethtool_pauseparam *ecmd)
4036{
4037 struct sky2_port *sky2 = netdev_priv(dev);
4038
4039 if (ecmd->autoneg == AUTONEG_ENABLE)
4040 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4041 else
4042 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4043
4044 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4045
4046 if (netif_running(dev))
4047 sky2_phy_reinit(sky2);
4048
4049 return 0;
4050}
4051
4052static int sky2_get_coalesce(struct net_device *dev,
4053 struct ethtool_coalesce *ecmd)
4054{
4055 struct sky2_port *sky2 = netdev_priv(dev);
4056 struct sky2_hw *hw = sky2->hw;
4057
4058 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4059 ecmd->tx_coalesce_usecs = 0;
4060 else {
4061 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4062 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4063 }
4064 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4065
4066 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4067 ecmd->rx_coalesce_usecs = 0;
4068 else {
4069 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4070 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4071 }
4072 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4073
4074 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4075 ecmd->rx_coalesce_usecs_irq = 0;
4076 else {
4077 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4078 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4079 }
4080
4081 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4082
4083 return 0;
4084}
4085
4086/* Note: this affect both ports */
4087static int sky2_set_coalesce(struct net_device *dev,
4088 struct ethtool_coalesce *ecmd)
4089{
4090 struct sky2_port *sky2 = netdev_priv(dev);
4091 struct sky2_hw *hw = sky2->hw;
4092 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4093
4094 if (ecmd->tx_coalesce_usecs > tmax ||
4095 ecmd->rx_coalesce_usecs > tmax ||
4096 ecmd->rx_coalesce_usecs_irq > tmax)
4097 return -EINVAL;
4098
4099 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4100 return -EINVAL;
4101 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4102 return -EINVAL;
4103 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4104 return -EINVAL;
4105
4106 if (ecmd->tx_coalesce_usecs == 0)
4107 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4108 else {
4109 sky2_write32(hw, STAT_TX_TIMER_INI,
4110 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4111 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4112 }
4113 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4114
4115 if (ecmd->rx_coalesce_usecs == 0)
4116 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4117 else {
4118 sky2_write32(hw, STAT_LEV_TIMER_INI,
4119 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4120 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4121 }
4122 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4123
4124 if (ecmd->rx_coalesce_usecs_irq == 0)
4125 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4126 else {
4127 sky2_write32(hw, STAT_ISR_TIMER_INI,
4128 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4129 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4130 }
4131 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4132 return 0;
4133}
4134
4135/*
4136 * Hardware is limited to min of 128 and max of 2048 for ring size
4137 * and rounded up to next power of two
4138 * to avoid division in modulus calclation
4139 */
4140static unsigned long roundup_ring_size(unsigned long pending)
4141{
4142 return max(128ul, roundup_pow_of_two(pending+1));
4143}
4144
4145static void sky2_get_ringparam(struct net_device *dev,
4146 struct ethtool_ringparam *ering)
4147{
4148 struct sky2_port *sky2 = netdev_priv(dev);
4149
4150 ering->rx_max_pending = RX_MAX_PENDING;
4151 ering->tx_max_pending = TX_MAX_PENDING;
4152
4153 ering->rx_pending = sky2->rx_pending;
4154 ering->tx_pending = sky2->tx_pending;
4155}
4156
4157static int sky2_set_ringparam(struct net_device *dev,
4158 struct ethtool_ringparam *ering)
4159{
4160 struct sky2_port *sky2 = netdev_priv(dev);
4161
4162 if (ering->rx_pending > RX_MAX_PENDING ||
4163 ering->rx_pending < 8 ||
4164 ering->tx_pending < TX_MIN_PENDING ||
4165 ering->tx_pending > TX_MAX_PENDING)
4166 return -EINVAL;
4167
4168 sky2_detach(dev);
4169
4170 sky2->rx_pending = ering->rx_pending;
4171 sky2->tx_pending = ering->tx_pending;
4172 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4173
4174 return sky2_reattach(dev);
4175}
4176
4177static int sky2_get_regs_len(struct net_device *dev)
4178{
4179 return 0x4000;
4180}
4181
4182static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4183{
4184 /* This complicated switch statement is to make sure and
4185 * only access regions that are unreserved.
4186 * Some blocks are only valid on dual port cards.
4187 */
4188 switch (b) {
4189 /* second port */
4190 case 5: /* Tx Arbiter 2 */
4191 case 9: /* RX2 */
4192 case 14 ... 15: /* TX2 */
4193 case 17: case 19: /* Ram Buffer 2 */
4194 case 22 ... 23: /* Tx Ram Buffer 2 */
4195 case 25: /* Rx MAC Fifo 1 */
4196 case 27: /* Tx MAC Fifo 2 */
4197 case 31: /* GPHY 2 */
4198 case 40 ... 47: /* Pattern Ram 2 */
4199 case 52: case 54: /* TCP Segmentation 2 */
4200 case 112 ... 116: /* GMAC 2 */
4201 return hw->ports > 1;
4202
4203 case 0: /* Control */
4204 case 2: /* Mac address */
4205 case 4: /* Tx Arbiter 1 */
4206 case 7: /* PCI express reg */
4207 case 8: /* RX1 */
4208 case 12 ... 13: /* TX1 */
4209 case 16: case 18:/* Rx Ram Buffer 1 */
4210 case 20 ... 21: /* Tx Ram Buffer 1 */
4211 case 24: /* Rx MAC Fifo 1 */
4212 case 26: /* Tx MAC Fifo 1 */
4213 case 28 ... 29: /* Descriptor and status unit */
4214 case 30: /* GPHY 1*/
4215 case 32 ... 39: /* Pattern Ram 1 */
4216 case 48: case 50: /* TCP Segmentation 1 */
4217 case 56 ... 60: /* PCI space */
4218 case 80 ... 84: /* GMAC 1 */
4219 return 1;
4220
4221 default:
4222 return 0;
4223 }
4224}
4225
4226/*
4227 * Returns copy of control register region
4228 * Note: ethtool_get_regs always provides full size (16k) buffer
4229 */
4230static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4231 void *p)
4232{
4233 const struct sky2_port *sky2 = netdev_priv(dev);
4234 const void __iomem *io = sky2->hw->regs;
4235 unsigned int b;
4236
4237 regs->version = 1;
4238
4239 for (b = 0; b < 128; b++) {
4240 /* skip poisonous diagnostic ram region in block 3 */
4241 if (b == 3)
4242 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4243 else if (sky2_reg_access_ok(sky2->hw, b))
4244 memcpy_fromio(p, io, 128);
4245 else
4246 memset(p, 0, 128);
4247
4248 p += 128;
4249 io += 128;
4250 }
4251}
4252
4253static int sky2_get_eeprom_len(struct net_device *dev)
4254{
4255 struct sky2_port *sky2 = netdev_priv(dev);
4256 struct sky2_hw *hw = sky2->hw;
4257 u16 reg2;
4258
4259 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4260 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4261}
4262
4263static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4264{
4265 unsigned long start = jiffies;
4266
4267 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4268 /* Can take up to 10.6 ms for write */
4269 if (time_after(jiffies, start + HZ/4)) {
4270 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4271 return -ETIMEDOUT;
4272 }
4273 msleep(1);
4274 }
4275
4276 return 0;
4277}
4278
4279static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4280 u16 offset, size_t length)
4281{
4282 int rc = 0;
4283
4284 while (length > 0) {
4285 u32 val;
4286
4287 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4288 rc = sky2_vpd_wait(hw, cap, 0);
4289 if (rc)
4290 break;
4291
4292 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4293
4294 memcpy(data, &val, min(sizeof(val), length));
4295 offset += sizeof(u32);
4296 data += sizeof(u32);
4297 length -= sizeof(u32);
4298 }
4299
4300 return rc;
4301}
4302
4303static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4304 u16 offset, unsigned int length)
4305{
4306 unsigned int i;
4307 int rc = 0;
4308
4309 for (i = 0; i < length; i += sizeof(u32)) {
4310 u32 val = *(u32 *)(data + i);
4311
4312 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4313 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4314
4315 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4316 if (rc)
4317 break;
4318 }
4319 return rc;
4320}
4321
4322static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4323 u8 *data)
4324{
4325 struct sky2_port *sky2 = netdev_priv(dev);
4326 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4327
4328 if (!cap)
4329 return -EINVAL;
4330
4331 eeprom->magic = SKY2_EEPROM_MAGIC;
4332
4333 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4334}
4335
4336static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4337 u8 *data)
4338{
4339 struct sky2_port *sky2 = netdev_priv(dev);
4340 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4341
4342 if (!cap)
4343 return -EINVAL;
4344
4345 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4346 return -EINVAL;
4347
4348 /* Partial writes not supported */
4349 if ((eeprom->offset & 3) || (eeprom->len & 3))
4350 return -EINVAL;
4351
4352 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4353}
4354
4355static netdev_features_t sky2_fix_features(struct net_device *dev,
4356 netdev_features_t features)
4357{
4358 const struct sky2_port *sky2 = netdev_priv(dev);
4359 const struct sky2_hw *hw = sky2->hw;
4360
4361 /* In order to do Jumbo packets on these chips, need to turn off the
4362 * transmit store/forward. Therefore checksum offload won't work.
4363 */
4364 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4365 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4366 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4367 }
4368
4369 /* Some hardware requires receive checksum for RSS to work. */
4370 if ( (features & NETIF_F_RXHASH) &&
4371 !(features & NETIF_F_RXCSUM) &&
4372 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4373 netdev_info(dev, "receive hashing forces receive checksum\n");
4374 features |= NETIF_F_RXCSUM;
4375 }
4376
4377 return features;
4378}
4379
4380static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4381{
4382 struct sky2_port *sky2 = netdev_priv(dev);
4383 netdev_features_t changed = dev->features ^ features;
4384
4385 if ((changed & NETIF_F_RXCSUM) &&
4386 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4387 sky2_write32(sky2->hw,
4388 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4389 (features & NETIF_F_RXCSUM)
4390 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4391 }
4392
4393 if (changed & NETIF_F_RXHASH)
4394 rx_set_rss(dev, features);
4395
4396 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4397 sky2_vlan_mode(dev, features);
4398
4399 return 0;
4400}
4401
4402static const struct ethtool_ops sky2_ethtool_ops = {
4403 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4404 ETHTOOL_COALESCE_MAX_FRAMES |
4405 ETHTOOL_COALESCE_RX_USECS_IRQ |
4406 ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ,
4407 .get_drvinfo = sky2_get_drvinfo,
4408 .get_wol = sky2_get_wol,
4409 .set_wol = sky2_set_wol,
4410 .get_msglevel = sky2_get_msglevel,
4411 .set_msglevel = sky2_set_msglevel,
4412 .nway_reset = sky2_nway_reset,
4413 .get_regs_len = sky2_get_regs_len,
4414 .get_regs = sky2_get_regs,
4415 .get_link = ethtool_op_get_link,
4416 .get_eeprom_len = sky2_get_eeprom_len,
4417 .get_eeprom = sky2_get_eeprom,
4418 .set_eeprom = sky2_set_eeprom,
4419 .get_strings = sky2_get_strings,
4420 .get_coalesce = sky2_get_coalesce,
4421 .set_coalesce = sky2_set_coalesce,
4422 .get_ringparam = sky2_get_ringparam,
4423 .set_ringparam = sky2_set_ringparam,
4424 .get_pauseparam = sky2_get_pauseparam,
4425 .set_pauseparam = sky2_set_pauseparam,
4426 .set_phys_id = sky2_set_phys_id,
4427 .get_sset_count = sky2_get_sset_count,
4428 .get_ethtool_stats = sky2_get_ethtool_stats,
4429 .get_link_ksettings = sky2_get_link_ksettings,
4430 .set_link_ksettings = sky2_set_link_ksettings,
4431};
4432
4433#ifdef CONFIG_SKY2_DEBUG
4434
4435static struct dentry *sky2_debug;
4436
4437
4438/*
4439 * Read and parse the first part of Vital Product Data
4440 */
4441#define VPD_SIZE 128
4442#define VPD_MAGIC 0x82
4443
4444static const struct vpd_tag {
4445 char tag[2];
4446 char *label;
4447} vpd_tags[] = {
4448 { "PN", "Part Number" },
4449 { "EC", "Engineering Level" },
4450 { "MN", "Manufacturer" },
4451 { "SN", "Serial Number" },
4452 { "YA", "Asset Tag" },
4453 { "VL", "First Error Log Message" },
4454 { "VF", "Second Error Log Message" },
4455 { "VB", "Boot Agent ROM Configuration" },
4456 { "VE", "EFI UNDI Configuration" },
4457};
4458
4459static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4460{
4461 size_t vpd_size;
4462 loff_t offs;
4463 u8 len;
4464 unsigned char *buf;
4465 u16 reg2;
4466
4467 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4468 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4469
4470 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4471 buf = kmalloc(vpd_size, GFP_KERNEL);
4472 if (!buf) {
4473 seq_puts(seq, "no memory!\n");
4474 return;
4475 }
4476
4477 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4478 seq_puts(seq, "VPD read failed\n");
4479 goto out;
4480 }
4481
4482 if (buf[0] != VPD_MAGIC) {
4483 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4484 goto out;
4485 }
4486 len = buf[1];
4487 if (len == 0 || len > vpd_size - 4) {
4488 seq_printf(seq, "Invalid id length: %d\n", len);
4489 goto out;
4490 }
4491
4492 seq_printf(seq, "%.*s\n", len, buf + 3);
4493 offs = len + 3;
4494
4495 while (offs < vpd_size - 4) {
4496 int i;
4497
4498 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4499 break;
4500 len = buf[offs + 2];
4501 if (offs + len + 3 >= vpd_size)
4502 break;
4503
4504 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4505 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4506 seq_printf(seq, " %s: %.*s\n",
4507 vpd_tags[i].label, len, buf + offs + 3);
4508 break;
4509 }
4510 }
4511 offs += len + 3;
4512 }
4513out:
4514 kfree(buf);
4515}
4516
4517static int sky2_debug_show(struct seq_file *seq, void *v)
4518{
4519 struct net_device *dev = seq->private;
4520 const struct sky2_port *sky2 = netdev_priv(dev);
4521 struct sky2_hw *hw = sky2->hw;
4522 unsigned port = sky2->port;
4523 unsigned idx, last;
4524 int sop;
4525
4526 sky2_show_vpd(seq, hw);
4527
4528 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4529 sky2_read32(hw, B0_ISRC),
4530 sky2_read32(hw, B0_IMSK),
4531 sky2_read32(hw, B0_Y2_SP_ICR));
4532
4533 if (!netif_running(dev)) {
4534 seq_puts(seq, "network not running\n");
4535 return 0;
4536 }
4537
4538 napi_disable(&hw->napi);
4539 last = sky2_read16(hw, STAT_PUT_IDX);
4540
4541 seq_printf(seq, "Status ring %u\n", hw->st_size);
4542 if (hw->st_idx == last)
4543 seq_puts(seq, "Status ring (empty)\n");
4544 else {
4545 seq_puts(seq, "Status ring\n");
4546 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4547 idx = RING_NEXT(idx, hw->st_size)) {
4548 const struct sky2_status_le *le = hw->st_le + idx;
4549 seq_printf(seq, "[%d] %#x %d %#x\n",
4550 idx, le->opcode, le->length, le->status);
4551 }
4552 seq_puts(seq, "\n");
4553 }
4554
4555 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4556 sky2->tx_cons, sky2->tx_prod,
4557 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4558 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4559
4560 /* Dump contents of tx ring */
4561 sop = 1;
4562 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4563 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4564 const struct sky2_tx_le *le = sky2->tx_le + idx;
4565 u32 a = le32_to_cpu(le->addr);
4566
4567 if (sop)
4568 seq_printf(seq, "%u:", idx);
4569 sop = 0;
4570
4571 switch (le->opcode & ~HW_OWNER) {
4572 case OP_ADDR64:
4573 seq_printf(seq, " %#x:", a);
4574 break;
4575 case OP_LRGLEN:
4576 seq_printf(seq, " mtu=%d", a);
4577 break;
4578 case OP_VLAN:
4579 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4580 break;
4581 case OP_TCPLISW:
4582 seq_printf(seq, " csum=%#x", a);
4583 break;
4584 case OP_LARGESEND:
4585 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4586 break;
4587 case OP_PACKET:
4588 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4589 break;
4590 case OP_BUFFER:
4591 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4592 break;
4593 default:
4594 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4595 a, le16_to_cpu(le->length));
4596 }
4597
4598 if (le->ctrl & EOP) {
4599 seq_putc(seq, '\n');
4600 sop = 1;
4601 }
4602 }
4603
4604 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4605 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4606 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4607 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4608
4609 sky2_read32(hw, B0_Y2_SP_LISR);
4610 napi_enable(&hw->napi);
4611 return 0;
4612}
4613DEFINE_SHOW_ATTRIBUTE(sky2_debug);
4614
4615/*
4616 * Use network device events to create/remove/rename
4617 * debugfs file entries
4618 */
4619static int sky2_device_event(struct notifier_block *unused,
4620 unsigned long event, void *ptr)
4621{
4622 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4623 struct sky2_port *sky2 = netdev_priv(dev);
4624
4625 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4626 return NOTIFY_DONE;
4627
4628 switch (event) {
4629 case NETDEV_CHANGENAME:
4630 if (sky2->debugfs) {
4631 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4632 sky2_debug, dev->name);
4633 }
4634 break;
4635
4636 case NETDEV_GOING_DOWN:
4637 if (sky2->debugfs) {
4638 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4639 debugfs_remove(sky2->debugfs);
4640 sky2->debugfs = NULL;
4641 }
4642 break;
4643
4644 case NETDEV_UP:
4645 sky2->debugfs = debugfs_create_file(dev->name, 0444,
4646 sky2_debug, dev,
4647 &sky2_debug_fops);
4648 if (IS_ERR(sky2->debugfs))
4649 sky2->debugfs = NULL;
4650 }
4651
4652 return NOTIFY_DONE;
4653}
4654
4655static struct notifier_block sky2_notifier = {
4656 .notifier_call = sky2_device_event,
4657};
4658
4659
4660static __init void sky2_debug_init(void)
4661{
4662 struct dentry *ent;
4663
4664 ent = debugfs_create_dir("sky2", NULL);
4665 if (!ent || IS_ERR(ent))
4666 return;
4667
4668 sky2_debug = ent;
4669 register_netdevice_notifier(&sky2_notifier);
4670}
4671
4672static __exit void sky2_debug_cleanup(void)
4673{
4674 if (sky2_debug) {
4675 unregister_netdevice_notifier(&sky2_notifier);
4676 debugfs_remove(sky2_debug);
4677 sky2_debug = NULL;
4678 }
4679}
4680
4681#else
4682#define sky2_debug_init()
4683#define sky2_debug_cleanup()
4684#endif
4685
4686/* Two copies of network device operations to handle special case of
4687 not allowing netpoll on second port */
4688static const struct net_device_ops sky2_netdev_ops[2] = {
4689 {
4690 .ndo_open = sky2_open,
4691 .ndo_stop = sky2_close,
4692 .ndo_start_xmit = sky2_xmit_frame,
4693 .ndo_do_ioctl = sky2_ioctl,
4694 .ndo_validate_addr = eth_validate_addr,
4695 .ndo_set_mac_address = sky2_set_mac_address,
4696 .ndo_set_rx_mode = sky2_set_multicast,
4697 .ndo_change_mtu = sky2_change_mtu,
4698 .ndo_fix_features = sky2_fix_features,
4699 .ndo_set_features = sky2_set_features,
4700 .ndo_tx_timeout = sky2_tx_timeout,
4701 .ndo_get_stats64 = sky2_get_stats,
4702#ifdef CONFIG_NET_POLL_CONTROLLER
4703 .ndo_poll_controller = sky2_netpoll,
4704#endif
4705 },
4706 {
4707 .ndo_open = sky2_open,
4708 .ndo_stop = sky2_close,
4709 .ndo_start_xmit = sky2_xmit_frame,
4710 .ndo_do_ioctl = sky2_ioctl,
4711 .ndo_validate_addr = eth_validate_addr,
4712 .ndo_set_mac_address = sky2_set_mac_address,
4713 .ndo_set_rx_mode = sky2_set_multicast,
4714 .ndo_change_mtu = sky2_change_mtu,
4715 .ndo_fix_features = sky2_fix_features,
4716 .ndo_set_features = sky2_set_features,
4717 .ndo_tx_timeout = sky2_tx_timeout,
4718 .ndo_get_stats64 = sky2_get_stats,
4719 },
4720};
4721
4722/* Initialize network device */
4723static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4724 int highmem, int wol)
4725{
4726 struct sky2_port *sky2;
4727 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4728 const void *iap;
4729
4730 if (!dev)
4731 return NULL;
4732
4733 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4734 dev->irq = hw->pdev->irq;
4735 dev->ethtool_ops = &sky2_ethtool_ops;
4736 dev->watchdog_timeo = TX_WATCHDOG;
4737 dev->netdev_ops = &sky2_netdev_ops[port];
4738
4739 sky2 = netdev_priv(dev);
4740 sky2->netdev = dev;
4741 sky2->hw = hw;
4742 sky2->msg_enable = netif_msg_init(debug, default_msg);
4743
4744 u64_stats_init(&sky2->tx_stats.syncp);
4745 u64_stats_init(&sky2->rx_stats.syncp);
4746
4747 /* Auto speed and flow control */
4748 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4749 if (hw->chip_id != CHIP_ID_YUKON_XL)
4750 dev->hw_features |= NETIF_F_RXCSUM;
4751
4752 sky2->flow_mode = FC_BOTH;
4753
4754 sky2->duplex = -1;
4755 sky2->speed = -1;
4756 sky2->advertising = sky2_supported_modes(hw);
4757 sky2->wol = wol;
4758
4759 spin_lock_init(&sky2->phy_lock);
4760
4761 sky2->tx_pending = TX_DEF_PENDING;
4762 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4763 sky2->rx_pending = RX_DEF_PENDING;
4764
4765 hw->dev[port] = dev;
4766
4767 sky2->port = port;
4768
4769 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4770
4771 if (highmem)
4772 dev->features |= NETIF_F_HIGHDMA;
4773
4774 /* Enable receive hashing unless hardware is known broken */
4775 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4776 dev->hw_features |= NETIF_F_RXHASH;
4777
4778 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4779 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4780 NETIF_F_HW_VLAN_CTAG_RX;
4781 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4782 }
4783
4784 dev->features |= dev->hw_features;
4785
4786 /* MTU range: 60 - 1500 or 9000 */
4787 dev->min_mtu = ETH_ZLEN;
4788 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4789 hw->chip_id == CHIP_ID_YUKON_FE_P)
4790 dev->max_mtu = ETH_DATA_LEN;
4791 else
4792 dev->max_mtu = ETH_JUMBO_MTU;
4793
4794 /* try to get mac address in the following order:
4795 * 1) from device tree data
4796 * 2) from internal registers set by bootloader
4797 */
4798 iap = of_get_mac_address(hw->pdev->dev.of_node);
4799 if (!IS_ERR(iap))
4800 ether_addr_copy(dev->dev_addr, iap);
4801 else
4802 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
4803 ETH_ALEN);
4804
4805 /* if the address is invalid, use a random value */
4806 if (!is_valid_ether_addr(dev->dev_addr)) {
4807 struct sockaddr sa = { AF_UNSPEC };
4808
4809 netdev_warn(dev,
4810 "Invalid MAC address, defaulting to random\n");
4811 eth_hw_addr_random(dev);
4812 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
4813 if (sky2_set_mac_address(dev, &sa))
4814 netdev_warn(dev, "Failed to set MAC address.\n");
4815 }
4816
4817 return dev;
4818}
4819
4820static void sky2_show_addr(struct net_device *dev)
4821{
4822 const struct sky2_port *sky2 = netdev_priv(dev);
4823
4824 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4825}
4826
4827/* Handle software interrupt used during MSI test */
4828static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4829{
4830 struct sky2_hw *hw = dev_id;
4831 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4832
4833 if (status == 0)
4834 return IRQ_NONE;
4835
4836 if (status & Y2_IS_IRQ_SW) {
4837 hw->flags |= SKY2_HW_USE_MSI;
4838 wake_up(&hw->msi_wait);
4839 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4840 }
4841 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4842
4843 return IRQ_HANDLED;
4844}
4845
4846/* Test interrupt path by forcing a a software IRQ */
4847static int sky2_test_msi(struct sky2_hw *hw)
4848{
4849 struct pci_dev *pdev = hw->pdev;
4850 int err;
4851
4852 init_waitqueue_head(&hw->msi_wait);
4853
4854 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4855 if (err) {
4856 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4857 return err;
4858 }
4859
4860 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4861
4862 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4863 sky2_read8(hw, B0_CTST);
4864
4865 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4866
4867 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4868 /* MSI test failed, go back to INTx mode */
4869 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4870 "switching to INTx mode.\n");
4871
4872 err = -EOPNOTSUPP;
4873 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4874 }
4875
4876 sky2_write32(hw, B0_IMSK, 0);
4877 sky2_read32(hw, B0_IMSK);
4878
4879 free_irq(pdev->irq, hw);
4880
4881 return err;
4882}
4883
4884/* This driver supports yukon2 chipset only */
4885static const char *sky2_name(u8 chipid, char *buf, int sz)
4886{
4887 const char *name[] = {
4888 "XL", /* 0xb3 */
4889 "EC Ultra", /* 0xb4 */
4890 "Extreme", /* 0xb5 */
4891 "EC", /* 0xb6 */
4892 "FE", /* 0xb7 */
4893 "FE+", /* 0xb8 */
4894 "Supreme", /* 0xb9 */
4895 "UL 2", /* 0xba */
4896 "Unknown", /* 0xbb */
4897 "Optima", /* 0xbc */
4898 "OptimaEEE", /* 0xbd */
4899 "Optima 2", /* 0xbe */
4900 };
4901
4902 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4903 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4904 else
4905 snprintf(buf, sz, "(chip %#x)", chipid);
4906 return buf;
4907}
4908
4909static const struct dmi_system_id msi_blacklist[] = {
4910 {
4911 .ident = "Dell Inspiron 1545",
4912 .matches = {
4913 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
4914 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"),
4915 },
4916 },
4917 {
4918 .ident = "Gateway P-79",
4919 .matches = {
4920 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"),
4921 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"),
4922 },
4923 },
4924 {
4925 .ident = "ASUS P5W DH Deluxe",
4926 .matches = {
4927 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTEK COMPUTER INC"),
4928 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
4929 },
4930 },
4931 {
4932 .ident = "ASUS P6T",
4933 .matches = {
4934 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4935 DMI_MATCH(DMI_BOARD_NAME, "P6T"),
4936 },
4937 },
4938 {
4939 .ident = "ASUS P6X",
4940 .matches = {
4941 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4942 DMI_MATCH(DMI_BOARD_NAME, "P6X"),
4943 },
4944 },
4945 {}
4946};
4947
4948static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4949{
4950 struct net_device *dev, *dev1;
4951 struct sky2_hw *hw;
4952 int err, using_dac = 0, wol_default;
4953 u32 reg;
4954 char buf1[16];
4955
4956 err = pci_enable_device(pdev);
4957 if (err) {
4958 dev_err(&pdev->dev, "cannot enable PCI device\n");
4959 goto err_out;
4960 }
4961
4962 /* Get configuration information
4963 * Note: only regular PCI config access once to test for HW issues
4964 * other PCI access through shared memory for speed and to
4965 * avoid MMCONFIG problems.
4966 */
4967 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4968 if (err) {
4969 dev_err(&pdev->dev, "PCI read config failed\n");
4970 goto err_out_disable;
4971 }
4972
4973 if (~reg == 0) {
4974 dev_err(&pdev->dev, "PCI configuration read error\n");
4975 err = -EIO;
4976 goto err_out_disable;
4977 }
4978
4979 err = pci_request_regions(pdev, DRV_NAME);
4980 if (err) {
4981 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4982 goto err_out_disable;
4983 }
4984
4985 pci_set_master(pdev);
4986
4987 if (sizeof(dma_addr_t) > sizeof(u32) &&
4988 !(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))) {
4989 using_dac = 1;
4990 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
4991 if (err < 0) {
4992 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4993 "for consistent allocations\n");
4994 goto err_out_free_regions;
4995 }
4996 } else {
4997 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
4998 if (err) {
4999 dev_err(&pdev->dev, "no usable DMA configuration\n");
5000 goto err_out_free_regions;
5001 }
5002 }
5003
5004
5005#ifdef __BIG_ENDIAN
5006 /* The sk98lin vendor driver uses hardware byte swapping but
5007 * this driver uses software swapping.
5008 */
5009 reg &= ~PCI_REV_DESC;
5010 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
5011 if (err) {
5012 dev_err(&pdev->dev, "PCI write config failed\n");
5013 goto err_out_free_regions;
5014 }
5015#endif
5016
5017 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
5018
5019 err = -ENOMEM;
5020
5021 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
5022 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
5023 if (!hw)
5024 goto err_out_free_regions;
5025
5026 hw->pdev = pdev;
5027 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
5028
5029 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
5030 if (!hw->regs) {
5031 dev_err(&pdev->dev, "cannot map device registers\n");
5032 goto err_out_free_hw;
5033 }
5034
5035 err = sky2_init(hw);
5036 if (err)
5037 goto err_out_iounmap;
5038
5039 /* ring for status responses */
5040 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
5041 hw->st_le = dma_alloc_coherent(&pdev->dev,
5042 hw->st_size * sizeof(struct sky2_status_le),
5043 &hw->st_dma, GFP_KERNEL);
5044 if (!hw->st_le) {
5045 err = -ENOMEM;
5046 goto err_out_reset;
5047 }
5048
5049 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
5050 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
5051
5052 sky2_reset(hw);
5053
5054 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
5055 if (!dev) {
5056 err = -ENOMEM;
5057 goto err_out_free_pci;
5058 }
5059
5060 if (disable_msi == -1)
5061 disable_msi = !!dmi_check_system(msi_blacklist);
5062
5063 if (!disable_msi && pci_enable_msi(pdev) == 0) {
5064 err = sky2_test_msi(hw);
5065 if (err) {
5066 pci_disable_msi(pdev);
5067 if (err != -EOPNOTSUPP)
5068 goto err_out_free_netdev;
5069 }
5070 }
5071
5072 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5073
5074 err = register_netdev(dev);
5075 if (err) {
5076 dev_err(&pdev->dev, "cannot register net device\n");
5077 goto err_out_free_netdev;
5078 }
5079
5080 netif_carrier_off(dev);
5081
5082 sky2_show_addr(dev);
5083
5084 if (hw->ports > 1) {
5085 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5086 if (!dev1) {
5087 err = -ENOMEM;
5088 goto err_out_unregister;
5089 }
5090
5091 err = register_netdev(dev1);
5092 if (err) {
5093 dev_err(&pdev->dev, "cannot register second net device\n");
5094 goto err_out_free_dev1;
5095 }
5096
5097 err = sky2_setup_irq(hw, hw->irq_name);
5098 if (err)
5099 goto err_out_unregister_dev1;
5100
5101 sky2_show_addr(dev1);
5102 }
5103
5104 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
5105 INIT_WORK(&hw->restart_work, sky2_restart);
5106
5107 pci_set_drvdata(pdev, hw);
5108 pdev->d3_delay = 300;
5109
5110 return 0;
5111
5112err_out_unregister_dev1:
5113 unregister_netdev(dev1);
5114err_out_free_dev1:
5115 free_netdev(dev1);
5116err_out_unregister:
5117 unregister_netdev(dev);
5118err_out_free_netdev:
5119 if (hw->flags & SKY2_HW_USE_MSI)
5120 pci_disable_msi(pdev);
5121 free_netdev(dev);
5122err_out_free_pci:
5123 dma_free_coherent(&pdev->dev,
5124 hw->st_size * sizeof(struct sky2_status_le),
5125 hw->st_le, hw->st_dma);
5126err_out_reset:
5127 sky2_write8(hw, B0_CTST, CS_RST_SET);
5128err_out_iounmap:
5129 iounmap(hw->regs);
5130err_out_free_hw:
5131 kfree(hw);
5132err_out_free_regions:
5133 pci_release_regions(pdev);
5134err_out_disable:
5135 pci_disable_device(pdev);
5136err_out:
5137 return err;
5138}
5139
5140static void sky2_remove(struct pci_dev *pdev)
5141{
5142 struct sky2_hw *hw = pci_get_drvdata(pdev);
5143 int i;
5144
5145 if (!hw)
5146 return;
5147
5148 del_timer_sync(&hw->watchdog_timer);
5149 cancel_work_sync(&hw->restart_work);
5150
5151 for (i = hw->ports-1; i >= 0; --i)
5152 unregister_netdev(hw->dev[i]);
5153
5154 sky2_write32(hw, B0_IMSK, 0);
5155 sky2_read32(hw, B0_IMSK);
5156
5157 sky2_power_aux(hw);
5158
5159 sky2_write8(hw, B0_CTST, CS_RST_SET);
5160 sky2_read8(hw, B0_CTST);
5161
5162 if (hw->ports > 1) {
5163 napi_disable(&hw->napi);
5164 free_irq(pdev->irq, hw);
5165 }
5166
5167 if (hw->flags & SKY2_HW_USE_MSI)
5168 pci_disable_msi(pdev);
5169 dma_free_coherent(&pdev->dev,
5170 hw->st_size * sizeof(struct sky2_status_le),
5171 hw->st_le, hw->st_dma);
5172 pci_release_regions(pdev);
5173 pci_disable_device(pdev);
5174
5175 for (i = hw->ports-1; i >= 0; --i)
5176 free_netdev(hw->dev[i]);
5177
5178 iounmap(hw->regs);
5179 kfree(hw);
5180}
5181
5182static int sky2_suspend(struct device *dev)
5183{
5184 struct sky2_hw *hw = dev_get_drvdata(dev);
5185 int i;
5186
5187 if (!hw)
5188 return 0;
5189
5190 del_timer_sync(&hw->watchdog_timer);
5191 cancel_work_sync(&hw->restart_work);
5192
5193 rtnl_lock();
5194
5195 sky2_all_down(hw);
5196 for (i = 0; i < hw->ports; i++) {
5197 struct net_device *dev = hw->dev[i];
5198 struct sky2_port *sky2 = netdev_priv(dev);
5199
5200 if (sky2->wol)
5201 sky2_wol_init(sky2);
5202 }
5203
5204 sky2_power_aux(hw);
5205 rtnl_unlock();
5206
5207 return 0;
5208}
5209
5210#ifdef CONFIG_PM_SLEEP
5211static int sky2_resume(struct device *dev)
5212{
5213 struct pci_dev *pdev = to_pci_dev(dev);
5214 struct sky2_hw *hw = pci_get_drvdata(pdev);
5215 int err;
5216
5217 if (!hw)
5218 return 0;
5219
5220 /* Re-enable all clocks */
5221 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5222 if (err) {
5223 dev_err(&pdev->dev, "PCI write config failed\n");
5224 goto out;
5225 }
5226
5227 rtnl_lock();
5228 sky2_reset(hw);
5229 sky2_all_up(hw);
5230 rtnl_unlock();
5231
5232 return 0;
5233out:
5234
5235 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5236 pci_disable_device(pdev);
5237 return err;
5238}
5239
5240static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5241#define SKY2_PM_OPS (&sky2_pm_ops)
5242
5243#else
5244
5245#define SKY2_PM_OPS NULL
5246#endif
5247
5248static void sky2_shutdown(struct pci_dev *pdev)
5249{
5250 struct sky2_hw *hw = pci_get_drvdata(pdev);
5251 int port;
5252
5253 for (port = 0; port < hw->ports; port++) {
5254 struct net_device *ndev = hw->dev[port];
5255
5256 rtnl_lock();
5257 if (netif_running(ndev)) {
5258 dev_close(ndev);
5259 netif_device_detach(ndev);
5260 }
5261 rtnl_unlock();
5262 }
5263 sky2_suspend(&pdev->dev);
5264 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5265 pci_set_power_state(pdev, PCI_D3hot);
5266}
5267
5268static struct pci_driver sky2_driver = {
5269 .name = DRV_NAME,
5270 .id_table = sky2_id_table,
5271 .probe = sky2_probe,
5272 .remove = sky2_remove,
5273 .shutdown = sky2_shutdown,
5274 .driver.pm = SKY2_PM_OPS,
5275};
5276
5277static int __init sky2_init_module(void)
5278{
5279 pr_info("driver version " DRV_VERSION "\n");
5280
5281 sky2_debug_init();
5282 return pci_register_driver(&sky2_driver);
5283}
5284
5285static void __exit sky2_cleanup_module(void)
5286{
5287 pci_unregister_driver(&sky2_driver);
5288 sky2_debug_cleanup();
5289}
5290
5291module_init(sky2_init_module);
5292module_exit(sky2_cleanup_module);
5293
5294MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5295MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5296MODULE_LICENSE("GPL");
5297MODULE_VERSION(DRV_VERSION);