Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7#ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H
8#define __LINUX_MTD_SPI_NOR_INTERNAL_H
9
10#include "sfdp.h"
11
12#define SPI_NOR_MAX_ID_LEN 6
13/*
14 * 256 bytes is a sane default for most older flashes. Newer flashes will
15 * have the page size defined within their SFDP tables.
16 */
17#define SPI_NOR_DEFAULT_PAGE_SIZE 256
18#define SPI_NOR_DEFAULT_N_BANKS 1
19#define SPI_NOR_DEFAULT_SECTOR_SIZE SZ_64K
20
21/* Standard SPI NOR flash operations. */
22#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \
23 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \
24 SPI_MEM_OP_ADDR(naddr, 0, 0), \
25 SPI_MEM_OP_DUMMY(ndummy, 0), \
26 SPI_MEM_OP_DATA_IN(len, buf, 0))
27
28#define SPI_NOR_WREN_OP \
29 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), \
30 SPI_MEM_OP_NO_ADDR, \
31 SPI_MEM_OP_NO_DUMMY, \
32 SPI_MEM_OP_NO_DATA)
33
34#define SPI_NOR_WRDI_OP \
35 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), \
36 SPI_MEM_OP_NO_ADDR, \
37 SPI_MEM_OP_NO_DUMMY, \
38 SPI_MEM_OP_NO_DATA)
39
40#define SPI_NOR_RDSR_OP(buf) \
41 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \
42 SPI_MEM_OP_NO_ADDR, \
43 SPI_MEM_OP_NO_DUMMY, \
44 SPI_MEM_OP_DATA_IN(1, buf, 0))
45
46#define SPI_NOR_WRSR_OP(buf, len) \
47 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \
48 SPI_MEM_OP_NO_ADDR, \
49 SPI_MEM_OP_NO_DUMMY, \
50 SPI_MEM_OP_DATA_OUT(len, buf, 0))
51
52#define SPI_NOR_RDSR2_OP(buf) \
53 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \
54 SPI_MEM_OP_NO_ADDR, \
55 SPI_MEM_OP_NO_DUMMY, \
56 SPI_MEM_OP_DATA_OUT(1, buf, 0))
57
58#define SPI_NOR_WRSR2_OP(buf) \
59 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \
60 SPI_MEM_OP_NO_ADDR, \
61 SPI_MEM_OP_NO_DUMMY, \
62 SPI_MEM_OP_DATA_OUT(1, buf, 0))
63
64#define SPI_NOR_RDCR_OP(buf) \
65 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \
66 SPI_MEM_OP_NO_ADDR, \
67 SPI_MEM_OP_NO_DUMMY, \
68 SPI_MEM_OP_DATA_IN(1, buf, 0))
69
70#define SPI_NOR_EN4B_EX4B_OP(enable) \
71 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \
72 SPI_MEM_OP_NO_ADDR, \
73 SPI_MEM_OP_NO_DUMMY, \
74 SPI_MEM_OP_NO_DATA)
75
76#define SPI_NOR_BRWR_OP(buf) \
77 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), \
78 SPI_MEM_OP_NO_ADDR, \
79 SPI_MEM_OP_NO_DUMMY, \
80 SPI_MEM_OP_DATA_OUT(1, buf, 0))
81
82#define SPI_NOR_GBULK_OP \
83 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), \
84 SPI_MEM_OP_NO_ADDR, \
85 SPI_MEM_OP_NO_DUMMY, \
86 SPI_MEM_OP_NO_DATA)
87
88#define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice) \
89 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
90 SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0), \
91 SPI_MEM_OP_NO_DUMMY, \
92 SPI_MEM_OP_NO_DATA)
93
94#define SPI_NOR_SECTOR_ERASE_OP(opcode, addr_nbytes, addr) \
95 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
96 SPI_MEM_OP_ADDR(addr_nbytes, addr, 0), \
97 SPI_MEM_OP_NO_DUMMY, \
98 SPI_MEM_OP_NO_DATA)
99
100#define SPI_NOR_READ_OP(opcode) \
101 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
102 SPI_MEM_OP_ADDR(3, 0, 0), \
103 SPI_MEM_OP_DUMMY(1, 0), \
104 SPI_MEM_OP_DATA_IN(2, NULL, 0))
105
106#define SPI_NOR_PP_OP(opcode) \
107 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
108 SPI_MEM_OP_ADDR(3, 0, 0), \
109 SPI_MEM_OP_NO_DUMMY, \
110 SPI_MEM_OP_DATA_OUT(2, NULL, 0))
111
112#define SPINOR_SRSTEN_OP \
113 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), \
114 SPI_MEM_OP_NO_DUMMY, \
115 SPI_MEM_OP_NO_ADDR, \
116 SPI_MEM_OP_NO_DATA)
117
118#define SPINOR_SRST_OP \
119 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), \
120 SPI_MEM_OP_NO_DUMMY, \
121 SPI_MEM_OP_NO_ADDR, \
122 SPI_MEM_OP_NO_DATA)
123
124/* Keep these in sync with the list in debugfs.c */
125enum spi_nor_option_flags {
126 SNOR_F_HAS_SR_TB = BIT(0),
127 SNOR_F_NO_OP_CHIP_ERASE = BIT(1),
128 SNOR_F_BROKEN_RESET = BIT(2),
129 SNOR_F_4B_OPCODES = BIT(3),
130 SNOR_F_HAS_4BAIT = BIT(4),
131 SNOR_F_HAS_LOCK = BIT(5),
132 SNOR_F_HAS_16BIT_SR = BIT(6),
133 SNOR_F_NO_READ_CR = BIT(7),
134 SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
135 SNOR_F_HAS_4BIT_BP = BIT(9),
136 SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
137 SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
138 SNOR_F_SOFT_RESET = BIT(12),
139 SNOR_F_SWP_IS_VOLATILE = BIT(13),
140 SNOR_F_RWW = BIT(14),
141 SNOR_F_ECC = BIT(15),
142 SNOR_F_NO_WP = BIT(16),
143};
144
145struct spi_nor_read_command {
146 u8 num_mode_clocks;
147 u8 num_wait_states;
148 u8 opcode;
149 enum spi_nor_protocol proto;
150};
151
152struct spi_nor_pp_command {
153 u8 opcode;
154 enum spi_nor_protocol proto;
155};
156
157enum spi_nor_read_command_index {
158 SNOR_CMD_READ,
159 SNOR_CMD_READ_FAST,
160 SNOR_CMD_READ_1_1_1_DTR,
161
162 /* Dual SPI */
163 SNOR_CMD_READ_1_1_2,
164 SNOR_CMD_READ_1_2_2,
165 SNOR_CMD_READ_2_2_2,
166 SNOR_CMD_READ_1_2_2_DTR,
167
168 /* Quad SPI */
169 SNOR_CMD_READ_1_1_4,
170 SNOR_CMD_READ_1_4_4,
171 SNOR_CMD_READ_4_4_4,
172 SNOR_CMD_READ_1_4_4_DTR,
173
174 /* Octal SPI */
175 SNOR_CMD_READ_1_1_8,
176 SNOR_CMD_READ_1_8_8,
177 SNOR_CMD_READ_8_8_8,
178 SNOR_CMD_READ_1_8_8_DTR,
179 SNOR_CMD_READ_8_8_8_DTR,
180
181 SNOR_CMD_READ_MAX
182};
183
184enum spi_nor_pp_command_index {
185 SNOR_CMD_PP,
186
187 /* Quad SPI */
188 SNOR_CMD_PP_1_1_4,
189 SNOR_CMD_PP_1_4_4,
190 SNOR_CMD_PP_4_4_4,
191
192 /* Octal SPI */
193 SNOR_CMD_PP_1_1_8,
194 SNOR_CMD_PP_1_8_8,
195 SNOR_CMD_PP_8_8_8,
196 SNOR_CMD_PP_8_8_8_DTR,
197
198 SNOR_CMD_PP_MAX
199};
200
201/**
202 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
203 * @size: the size of the sector/block erased by the erase type.
204 * JEDEC JESD216B imposes erase sizes to be a power of 2.
205 * @size_shift: @size is a power of 2, the shift is stored in
206 * @size_shift.
207 * @size_mask: the size mask based on @size_shift.
208 * @opcode: the SPI command op code to erase the sector/block.
209 * @idx: Erase Type index as sorted in the Basic Flash Parameter
210 * Table. It will be used to synchronize the supported
211 * Erase Types with the ones identified in the SFDP
212 * optional tables.
213 */
214struct spi_nor_erase_type {
215 u32 size;
216 u32 size_shift;
217 u32 size_mask;
218 u8 opcode;
219 u8 idx;
220};
221
222/**
223 * struct spi_nor_erase_command - Used for non-uniform erases
224 * The structure is used to describe a list of erase commands to be executed
225 * once we validate that the erase can be performed. The elements in the list
226 * are run-length encoded.
227 * @list: for inclusion into the list of erase commands.
228 * @count: how many times the same erase command should be
229 * consecutively used.
230 * @size: the size of the sector/block erased by the command.
231 * @opcode: the SPI command op code to erase the sector/block.
232 */
233struct spi_nor_erase_command {
234 struct list_head list;
235 u32 count;
236 u32 size;
237 u8 opcode;
238};
239
240/**
241 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
242 * @offset: the offset in the data array of erase region start.
243 * LSB bits are used as a bitmask encoding flags to
244 * determine if this region is overlaid, if this region is
245 * the last in the SPI NOR flash memory and to indicate
246 * all the supported erase commands inside this region.
247 * The erase types are sorted in ascending order with the
248 * smallest Erase Type size being at BIT(0).
249 * @size: the size of the region in bytes.
250 */
251struct spi_nor_erase_region {
252 u64 offset;
253 u64 size;
254};
255
256#define SNOR_ERASE_TYPE_MAX 4
257#define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
258
259#define SNOR_LAST_REGION BIT(4)
260#define SNOR_OVERLAID_REGION BIT(5)
261
262#define SNOR_ERASE_FLAGS_MAX 6
263#define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
264
265/**
266 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
267 * @regions: array of erase regions. The regions are consecutive in
268 * address space. Walking through the regions is done
269 * incrementally.
270 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
271 * sector size (legacy implementation).
272 * @erase_type: an array of erase types shared by all the regions.
273 * The erase types are sorted in ascending order, with the
274 * smallest Erase Type size being the first member in the
275 * erase_type array.
276 * @uniform_erase_type: bitmask encoding erase types that can erase the
277 * entire memory. This member is completed at init by
278 * uniform and non-uniform SPI NOR flash memories if they
279 * support at least one erase type that can erase the
280 * entire memory.
281 */
282struct spi_nor_erase_map {
283 struct spi_nor_erase_region *regions;
284 struct spi_nor_erase_region uniform_region;
285 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
286 u8 uniform_erase_type;
287};
288
289/**
290 * struct spi_nor_locking_ops - SPI NOR locking methods
291 * @lock: lock a region of the SPI NOR.
292 * @unlock: unlock a region of the SPI NOR.
293 * @is_locked: check if a region of the SPI NOR is completely locked
294 */
295struct spi_nor_locking_ops {
296 int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len);
297 int (*unlock)(struct spi_nor *nor, loff_t ofs, u64 len);
298 int (*is_locked)(struct spi_nor *nor, loff_t ofs, u64 len);
299};
300
301/**
302 * struct spi_nor_otp_organization - Structure to describe the SPI NOR OTP regions
303 * @len: size of one OTP region in bytes.
304 * @base: start address of the OTP area.
305 * @offset: offset between consecutive OTP regions if there are more
306 * than one.
307 * @n_regions: number of individual OTP regions.
308 */
309struct spi_nor_otp_organization {
310 size_t len;
311 loff_t base;
312 loff_t offset;
313 unsigned int n_regions;
314};
315
316/**
317 * struct spi_nor_otp_ops - SPI NOR OTP methods
318 * @read: read from the SPI NOR OTP area.
319 * @write: write to the SPI NOR OTP area.
320 * @lock: lock an OTP region.
321 * @erase: erase an OTP region.
322 * @is_locked: check if an OTP region of the SPI NOR is locked.
323 */
324struct spi_nor_otp_ops {
325 int (*read)(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf);
326 int (*write)(struct spi_nor *nor, loff_t addr, size_t len,
327 const u8 *buf);
328 int (*lock)(struct spi_nor *nor, unsigned int region);
329 int (*erase)(struct spi_nor *nor, loff_t addr);
330 int (*is_locked)(struct spi_nor *nor, unsigned int region);
331};
332
333/**
334 * struct spi_nor_otp - SPI NOR OTP grouping structure
335 * @org: OTP region organization
336 * @ops: OTP access ops
337 */
338struct spi_nor_otp {
339 const struct spi_nor_otp_organization *org;
340 const struct spi_nor_otp_ops *ops;
341};
342
343/**
344 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
345 * Includes legacy flash parameters and settings that can be overwritten
346 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
347 * Serial Flash Discoverable Parameters (SFDP) tables.
348 *
349 * @bank_size: the flash memory bank density in bytes.
350 * @size: the total flash memory density in bytes.
351 * @writesize Minimal writable flash unit size. Defaults to 1. Set to
352 * ECC unit size for ECC-ed flashes.
353 * @page_size: the page size of the SPI NOR flash memory.
354 * @addr_nbytes: number of address bytes to send.
355 * @addr_mode_nbytes: number of address bytes of current address mode. Useful
356 * when the flash operates with 4B opcodes but needs the
357 * internal address mode for opcodes that don't have a 4B
358 * opcode correspondent.
359 * @rdsr_dummy: dummy cycles needed for Read Status Register command
360 * in octal DTR mode.
361 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
362 * command in octal DTR mode.
363 * @n_banks: number of banks.
364 * @n_dice: number of dice in the flash memory.
365 * @die_erase_opcode: die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.
366 * @vreg_offset: volatile register offset for each die.
367 * @hwcaps: describes the read and page program hardware
368 * capabilities.
369 * @reads: read capabilities ordered by priority: the higher index
370 * in the array, the higher priority.
371 * @page_programs: page program capabilities ordered by priority: the
372 * higher index in the array, the higher priority.
373 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
374 * Table.
375 * @otp: SPI NOR OTP info.
376 * @set_octal_dtr: enables or disables SPI NOR octal DTR mode.
377 * @quad_enable: enables SPI NOR quad mode.
378 * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
379 * @convert_addr: converts an absolute address into something the flash
380 * will understand. Particularly useful when pagesize is
381 * not a power-of-2.
382 * @setup: (optional) configures the SPI NOR memory. Useful for
383 * SPI NOR flashes that have peculiarities to the SPI NOR
384 * standard e.g. different opcodes, specific address
385 * calculation, page size, etc.
386 * @ready: (optional) flashes might use a different mechanism
387 * than reading the status register to indicate they
388 * are ready for a new command
389 * @locking_ops: SPI NOR locking methods.
390 * @priv: flash's private data.
391 */
392struct spi_nor_flash_parameter {
393 u64 bank_size;
394 u64 size;
395 u32 writesize;
396 u32 page_size;
397 u8 addr_nbytes;
398 u8 addr_mode_nbytes;
399 u8 rdsr_dummy;
400 u8 rdsr_addr_nbytes;
401 u8 n_banks;
402 u8 n_dice;
403 u8 die_erase_opcode;
404 u32 *vreg_offset;
405
406 struct spi_nor_hwcaps hwcaps;
407 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
408 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
409
410 struct spi_nor_erase_map erase_map;
411 struct spi_nor_otp otp;
412
413 int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
414 int (*quad_enable)(struct spi_nor *nor);
415 int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
416 u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
417 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
418 int (*ready)(struct spi_nor *nor);
419
420 const struct spi_nor_locking_ops *locking_ops;
421 void *priv;
422};
423
424/**
425 * struct spi_nor_fixups - SPI NOR fixup hooks
426 * @default_init: called after default flash parameters init. Used to tweak
427 * flash parameters when information provided by the flash_info
428 * table is incomplete or wrong.
429 * @post_bfpt: called after the BFPT table has been parsed
430 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
431 * that do not support RDSFDP). Typically used to tweak various
432 * parameters that could not be extracted by other means (i.e.
433 * when information provided by the SFDP/flash_info tables are
434 * incomplete or wrong).
435 * @late_init: used to initialize flash parameters that are not declared in the
436 * JESD216 SFDP standard, or where SFDP tables not defined at all.
437 * Will replace the default_init() hook.
438 *
439 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
440 * table is broken or not available.
441 */
442struct spi_nor_fixups {
443 void (*default_init)(struct spi_nor *nor);
444 int (*post_bfpt)(struct spi_nor *nor,
445 const struct sfdp_parameter_header *bfpt_header,
446 const struct sfdp_bfpt *bfpt);
447 int (*post_sfdp)(struct spi_nor *nor);
448 int (*late_init)(struct spi_nor *nor);
449};
450
451/**
452 * struct spi_nor_id - SPI NOR flash ID.
453 *
454 * @bytes: the bytes returned by the flash when issuing command 9F. Typically,
455 * the first byte is the manufacturer ID code (see JEP106) and the next
456 * two bytes are a flash part specific ID.
457 * @len: the number of bytes of ID.
458 */
459struct spi_nor_id {
460 const u8 *bytes;
461 u8 len;
462};
463
464/**
465 * struct flash_info - SPI NOR flash_info entry.
466 * @id: pointer to struct spi_nor_id or NULL, which means "no ID" (mostly
467 * older chips).
468 * @name: (obsolete) the name of the flash. Do not set it for new additions.
469 * @size: the size of the flash in bytes.
470 * @sector_size: (optional) the size listed here is what works with
471 * SPINOR_OP_SE, which isn't necessarily called a "sector" by
472 * the vendor. Defaults to 64k.
473 * @n_banks: (optional) the number of banks. Defaults to 1.
474 * @page_size: (optional) the flash's page size. Defaults to 256.
475 * @addr_nbytes: number of address bytes to send.
476 *
477 * @flags: flags that indicate support that is not defined by the
478 * JESD216 standard in its SFDP tables. Flag meanings:
479 * SPI_NOR_HAS_LOCK: flash supports lock/unlock via SR
480 * SPI_NOR_HAS_TB: flash SR has Top/Bottom (TB) protect bit. Must be
481 * used with SPI_NOR_HAS_LOCK.
482 * SPI_NOR_TB_SR_BIT6: Top/Bottom (TB) is bit 6 of status register.
483 * Must be used with SPI_NOR_HAS_TB.
484 * SPI_NOR_4BIT_BP: flash SR has 4 bit fields (BP0-3) for block
485 * protection.
486 * SPI_NOR_BP3_SR_BIT6: BP3 is bit 6 of status register. Must be used with
487 * SPI_NOR_4BIT_BP.
488 * SPI_NOR_SWP_IS_VOLATILE: flash has volatile software write protection bits.
489 * Usually these will power-up in a write-protected
490 * state.
491 * SPI_NOR_NO_ERASE: no erase command needed.
492 * SPI_NOR_NO_FR: can't do fastread.
493 * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
494 * SPI_NOR_RWW: flash supports reads while write.
495 *
496 * @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
497 * Used when SFDP tables are not defined in the flash. These
498 * flags are used together with the SPI_NOR_SKIP_SFDP flag.
499 * SPI_NOR_SKIP_SFDP: skip parsing of SFDP tables.
500 * SECT_4K: SPINOR_OP_BE_4K works uniformly.
501 * SPI_NOR_DUAL_READ: flash supports Dual Read.
502 * SPI_NOR_QUAD_READ: flash supports Quad Read.
503 * SPI_NOR_OCTAL_READ: flash supports Octal Read.
504 * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
505 * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
506 *
507 * @fixup_flags: flags that indicate support that can be discovered via SFDP
508 * ideally, but can not be discovered for this particular flash
509 * because the SFDP table that indicates this support is not
510 * defined by the flash. In case the table for this support is
511 * defined but has wrong values, one should instead use a
512 * post_sfdp() hook to set the SNOR_F equivalent flag.
513 *
514 * SPI_NOR_4B_OPCODES: use dedicated 4byte address op codes to support
515 * memory size above 128Mib.
516 * SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode
517 * via a volatile bit.
518 * @mfr_flags: manufacturer private flags. Used in the manufacturer fixup
519 * hooks to differentiate support between flashes of the same
520 * manufacturer.
521 * @otp_org: flash's OTP organization.
522 * @fixups: part specific fixup hooks.
523 */
524struct flash_info {
525 char *name;
526 const struct spi_nor_id *id;
527 size_t size;
528 unsigned sector_size;
529 u16 page_size;
530 u8 n_banks;
531 u8 addr_nbytes;
532
533 u16 flags;
534#define SPI_NOR_HAS_LOCK BIT(0)
535#define SPI_NOR_HAS_TB BIT(1)
536#define SPI_NOR_TB_SR_BIT6 BIT(2)
537#define SPI_NOR_4BIT_BP BIT(3)
538#define SPI_NOR_BP3_SR_BIT6 BIT(4)
539#define SPI_NOR_SWP_IS_VOLATILE BIT(5)
540#define SPI_NOR_NO_ERASE BIT(6)
541#define SPI_NOR_NO_FR BIT(7)
542#define SPI_NOR_QUAD_PP BIT(8)
543#define SPI_NOR_RWW BIT(9)
544
545 u8 no_sfdp_flags;
546#define SPI_NOR_SKIP_SFDP BIT(0)
547#define SECT_4K BIT(1)
548#define SPI_NOR_DUAL_READ BIT(3)
549#define SPI_NOR_QUAD_READ BIT(4)
550#define SPI_NOR_OCTAL_READ BIT(5)
551#define SPI_NOR_OCTAL_DTR_READ BIT(6)
552#define SPI_NOR_OCTAL_DTR_PP BIT(7)
553
554 u8 fixup_flags;
555#define SPI_NOR_4B_OPCODES BIT(0)
556#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1)
557
558 u8 mfr_flags;
559
560 const struct spi_nor_otp_organization *otp;
561 const struct spi_nor_fixups *fixups;
562};
563
564#define SNOR_ID(...) \
565 (&(const struct spi_nor_id){ \
566 .bytes = (const u8[]){ __VA_ARGS__ }, \
567 .len = sizeof((u8[]){ __VA_ARGS__ }), \
568 })
569
570#define SNOR_OTP(_len, _n_regions, _base, _offset) \
571 (&(const struct spi_nor_otp_organization){ \
572 .len = (_len), \
573 .base = (_base), \
574 .offset = (_offset), \
575 .n_regions = (_n_regions), \
576 })
577
578/**
579 * struct spi_nor_manufacturer - SPI NOR manufacturer object
580 * @name: manufacturer name
581 * @parts: array of parts supported by this manufacturer
582 * @nparts: number of entries in the parts array
583 * @fixups: hooks called at various points in time during spi_nor_scan()
584 */
585struct spi_nor_manufacturer {
586 const char *name;
587 const struct flash_info *parts;
588 unsigned int nparts;
589 const struct spi_nor_fixups *fixups;
590};
591
592/**
593 * struct sfdp - SFDP data
594 * @num_dwords: number of entries in the dwords array
595 * @dwords: array of double words of the SFDP data
596 */
597struct sfdp {
598 size_t num_dwords;
599 u32 *dwords;
600};
601
602/* Manufacturer drivers. */
603extern const struct spi_nor_manufacturer spi_nor_atmel;
604extern const struct spi_nor_manufacturer spi_nor_eon;
605extern const struct spi_nor_manufacturer spi_nor_esmt;
606extern const struct spi_nor_manufacturer spi_nor_everspin;
607extern const struct spi_nor_manufacturer spi_nor_gigadevice;
608extern const struct spi_nor_manufacturer spi_nor_intel;
609extern const struct spi_nor_manufacturer spi_nor_issi;
610extern const struct spi_nor_manufacturer spi_nor_macronix;
611extern const struct spi_nor_manufacturer spi_nor_micron;
612extern const struct spi_nor_manufacturer spi_nor_st;
613extern const struct spi_nor_manufacturer spi_nor_spansion;
614extern const struct spi_nor_manufacturer spi_nor_sst;
615extern const struct spi_nor_manufacturer spi_nor_winbond;
616extern const struct spi_nor_manufacturer spi_nor_xilinx;
617extern const struct spi_nor_manufacturer spi_nor_xmc;
618
619extern const struct attribute_group *spi_nor_sysfs_groups[];
620
621void spi_nor_spimem_setup_op(const struct spi_nor *nor,
622 struct spi_mem_op *op,
623 const enum spi_nor_protocol proto);
624int spi_nor_write_enable(struct spi_nor *nor);
625int spi_nor_write_disable(struct spi_nor *nor);
626int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable);
627int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor,
628 bool enable);
629int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable);
630int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
631int spi_nor_wait_till_ready(struct spi_nor *nor);
632int spi_nor_global_block_unlock(struct spi_nor *nor);
633int spi_nor_prep_and_lock(struct spi_nor *nor);
634void spi_nor_unlock_and_unprep(struct spi_nor *nor);
635int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
636int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
637int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
638int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
639 enum spi_nor_protocol reg_proto);
640int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
641int spi_nor_sr_ready(struct spi_nor *nor);
642int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
643int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
644int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
645int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
646
647ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
648 u8 *buf);
649ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
650 const u8 *buf);
651int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
652 enum spi_nor_protocol proto);
653int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
654 enum spi_nor_protocol proto);
655int spi_nor_erase_sector(struct spi_nor *nor, u32 addr);
656
657int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf);
658int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
659 const u8 *buf);
660int spi_nor_otp_erase_secr(struct spi_nor *nor, loff_t addr);
661int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region);
662int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region);
663
664int spi_nor_hwcaps_read2cmd(u32 hwcaps);
665int spi_nor_hwcaps_pp2cmd(u32 hwcaps);
666u8 spi_nor_convert_3to4_read(u8 opcode);
667void spi_nor_set_read_settings(struct spi_nor_read_command *read,
668 u8 num_mode_clocks,
669 u8 num_wait_states,
670 u8 opcode,
671 enum spi_nor_protocol proto);
672void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
673 enum spi_nor_protocol proto);
674
675void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
676 u8 opcode);
677void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase);
678struct spi_nor_erase_region *
679spi_nor_region_next(struct spi_nor_erase_region *region);
680void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
681 u8 erase_mask, u64 flash_size);
682
683int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
684 const struct sfdp_parameter_header *bfpt_header,
685 const struct sfdp_bfpt *bfpt);
686
687void spi_nor_init_default_locking_ops(struct spi_nor *nor);
688void spi_nor_try_unlock_all(struct spi_nor *nor);
689void spi_nor_set_mtd_locking_ops(struct spi_nor *nor);
690void spi_nor_set_mtd_otp_ops(struct spi_nor *nor);
691
692int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
693 u8 *buf, size_t len);
694int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
695 const u8 *buf, size_t len);
696
697int spi_nor_check_sfdp_signature(struct spi_nor *nor);
698int spi_nor_parse_sfdp(struct spi_nor *nor);
699
700static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
701{
702 return container_of(mtd, struct spi_nor, mtd);
703}
704
705/**
706 * spi_nor_needs_sfdp() - returns true if SFDP parsing is used for this flash.
707 *
708 * Return: true if SFDP parsing is needed
709 */
710static inline bool spi_nor_needs_sfdp(const struct spi_nor *nor)
711{
712 /*
713 * The flash size is one property parsed by the SFDP. We use it as an
714 * indicator whether we need SFDP parsing for a particular flash. I.e.
715 * non-legacy flash entries in flash_info will have a size of zero iff
716 * SFDP should be used.
717 */
718 return !nor->info->size;
719}
720
721#ifdef CONFIG_DEBUG_FS
722void spi_nor_debugfs_register(struct spi_nor *nor);
723void spi_nor_debugfs_shutdown(void);
724#else
725static inline void spi_nor_debugfs_register(struct spi_nor *nor) {}
726static inline void spi_nor_debugfs_shutdown(void) {}
727#endif
728
729#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7#ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H
8#define __LINUX_MTD_SPI_NOR_INTERNAL_H
9
10#include "sfdp.h"
11
12#define SPI_NOR_MAX_ID_LEN 6
13
14enum spi_nor_option_flags {
15 SNOR_F_USE_FSR = BIT(0),
16 SNOR_F_HAS_SR_TB = BIT(1),
17 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
18 SNOR_F_READY_XSR_RDY = BIT(3),
19 SNOR_F_USE_CLSR = BIT(4),
20 SNOR_F_BROKEN_RESET = BIT(5),
21 SNOR_F_4B_OPCODES = BIT(6),
22 SNOR_F_HAS_4BAIT = BIT(7),
23 SNOR_F_HAS_LOCK = BIT(8),
24 SNOR_F_HAS_16BIT_SR = BIT(9),
25 SNOR_F_NO_READ_CR = BIT(10),
26 SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
27 SNOR_F_HAS_4BIT_BP = BIT(12),
28 SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
29};
30
31struct spi_nor_read_command {
32 u8 num_mode_clocks;
33 u8 num_wait_states;
34 u8 opcode;
35 enum spi_nor_protocol proto;
36};
37
38struct spi_nor_pp_command {
39 u8 opcode;
40 enum spi_nor_protocol proto;
41};
42
43enum spi_nor_read_command_index {
44 SNOR_CMD_READ,
45 SNOR_CMD_READ_FAST,
46 SNOR_CMD_READ_1_1_1_DTR,
47
48 /* Dual SPI */
49 SNOR_CMD_READ_1_1_2,
50 SNOR_CMD_READ_1_2_2,
51 SNOR_CMD_READ_2_2_2,
52 SNOR_CMD_READ_1_2_2_DTR,
53
54 /* Quad SPI */
55 SNOR_CMD_READ_1_1_4,
56 SNOR_CMD_READ_1_4_4,
57 SNOR_CMD_READ_4_4_4,
58 SNOR_CMD_READ_1_4_4_DTR,
59
60 /* Octal SPI */
61 SNOR_CMD_READ_1_1_8,
62 SNOR_CMD_READ_1_8_8,
63 SNOR_CMD_READ_8_8_8,
64 SNOR_CMD_READ_1_8_8_DTR,
65
66 SNOR_CMD_READ_MAX
67};
68
69enum spi_nor_pp_command_index {
70 SNOR_CMD_PP,
71
72 /* Quad SPI */
73 SNOR_CMD_PP_1_1_4,
74 SNOR_CMD_PP_1_4_4,
75 SNOR_CMD_PP_4_4_4,
76
77 /* Octal SPI */
78 SNOR_CMD_PP_1_1_8,
79 SNOR_CMD_PP_1_8_8,
80 SNOR_CMD_PP_8_8_8,
81
82 SNOR_CMD_PP_MAX
83};
84
85/**
86 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
87 * @size: the size of the sector/block erased by the erase type.
88 * JEDEC JESD216B imposes erase sizes to be a power of 2.
89 * @size_shift: @size is a power of 2, the shift is stored in
90 * @size_shift.
91 * @size_mask: the size mask based on @size_shift.
92 * @opcode: the SPI command op code to erase the sector/block.
93 * @idx: Erase Type index as sorted in the Basic Flash Parameter
94 * Table. It will be used to synchronize the supported
95 * Erase Types with the ones identified in the SFDP
96 * optional tables.
97 */
98struct spi_nor_erase_type {
99 u32 size;
100 u32 size_shift;
101 u32 size_mask;
102 u8 opcode;
103 u8 idx;
104};
105
106/**
107 * struct spi_nor_erase_command - Used for non-uniform erases
108 * The structure is used to describe a list of erase commands to be executed
109 * once we validate that the erase can be performed. The elements in the list
110 * are run-length encoded.
111 * @list: for inclusion into the list of erase commands.
112 * @count: how many times the same erase command should be
113 * consecutively used.
114 * @size: the size of the sector/block erased by the command.
115 * @opcode: the SPI command op code to erase the sector/block.
116 */
117struct spi_nor_erase_command {
118 struct list_head list;
119 u32 count;
120 u32 size;
121 u8 opcode;
122};
123
124/**
125 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
126 * @offset: the offset in the data array of erase region start.
127 * LSB bits are used as a bitmask encoding flags to
128 * determine if this region is overlaid, if this region is
129 * the last in the SPI NOR flash memory and to indicate
130 * all the supported erase commands inside this region.
131 * The erase types are sorted in ascending order with the
132 * smallest Erase Type size being at BIT(0).
133 * @size: the size of the region in bytes.
134 */
135struct spi_nor_erase_region {
136 u64 offset;
137 u64 size;
138};
139
140#define SNOR_ERASE_TYPE_MAX 4
141#define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
142
143#define SNOR_LAST_REGION BIT(4)
144#define SNOR_OVERLAID_REGION BIT(5)
145
146#define SNOR_ERASE_FLAGS_MAX 6
147#define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
148
149/**
150 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
151 * @regions: array of erase regions. The regions are consecutive in
152 * address space. Walking through the regions is done
153 * incrementally.
154 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
155 * sector size (legacy implementation).
156 * @erase_type: an array of erase types shared by all the regions.
157 * The erase types are sorted in ascending order, with the
158 * smallest Erase Type size being the first member in the
159 * erase_type array.
160 * @uniform_erase_type: bitmask encoding erase types that can erase the
161 * entire memory. This member is completed at init by
162 * uniform and non-uniform SPI NOR flash memories if they
163 * support at least one erase type that can erase the
164 * entire memory.
165 */
166struct spi_nor_erase_map {
167 struct spi_nor_erase_region *regions;
168 struct spi_nor_erase_region uniform_region;
169 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
170 u8 uniform_erase_type;
171};
172
173/**
174 * struct spi_nor_locking_ops - SPI NOR locking methods
175 * @lock: lock a region of the SPI NOR.
176 * @unlock: unlock a region of the SPI NOR.
177 * @is_locked: check if a region of the SPI NOR is completely locked
178 */
179struct spi_nor_locking_ops {
180 int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
181 int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
182 int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
183};
184
185/**
186 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
187 * Includes legacy flash parameters and settings that can be overwritten
188 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
189 * Serial Flash Discoverable Parameters (SFDP) tables.
190 *
191 * @size: the flash memory density in bytes.
192 * @page_size: the page size of the SPI NOR flash memory.
193 * @hwcaps: describes the read and page program hardware
194 * capabilities.
195 * @reads: read capabilities ordered by priority: the higher index
196 * in the array, the higher priority.
197 * @page_programs: page program capabilities ordered by priority: the
198 * higher index in the array, the higher priority.
199 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
200 * Table.
201 * @quad_enable: enables SPI NOR quad mode.
202 * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
203 * @convert_addr: converts an absolute address into something the flash
204 * will understand. Particularly useful when pagesize is
205 * not a power-of-2.
206 * @setup: configures the SPI NOR memory. Useful for SPI NOR
207 * flashes that have peculiarities to the SPI NOR standard
208 * e.g. different opcodes, specific address calculation,
209 * page size, etc.
210 * @locking_ops: SPI NOR locking methods.
211 */
212struct spi_nor_flash_parameter {
213 u64 size;
214 u32 page_size;
215
216 struct spi_nor_hwcaps hwcaps;
217 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
218 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
219
220 struct spi_nor_erase_map erase_map;
221
222 int (*quad_enable)(struct spi_nor *nor);
223 int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
224 u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
225 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
226
227 const struct spi_nor_locking_ops *locking_ops;
228};
229
230/**
231 * struct spi_nor_fixups - SPI NOR fixup hooks
232 * @default_init: called after default flash parameters init. Used to tweak
233 * flash parameters when information provided by the flash_info
234 * table is incomplete or wrong.
235 * @post_bfpt: called after the BFPT table has been parsed
236 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
237 * that do not support RDSFDP). Typically used to tweak various
238 * parameters that could not be extracted by other means (i.e.
239 * when information provided by the SFDP/flash_info tables are
240 * incomplete or wrong).
241 *
242 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
243 * table is broken or not available.
244 */
245struct spi_nor_fixups {
246 void (*default_init)(struct spi_nor *nor);
247 int (*post_bfpt)(struct spi_nor *nor,
248 const struct sfdp_parameter_header *bfpt_header,
249 const struct sfdp_bfpt *bfpt,
250 struct spi_nor_flash_parameter *params);
251 void (*post_sfdp)(struct spi_nor *nor);
252};
253
254struct flash_info {
255 char *name;
256
257 /*
258 * This array stores the ID bytes.
259 * The first three bytes are the JEDIC ID.
260 * JEDEC ID zero means "no ID" (mostly older chips).
261 */
262 u8 id[SPI_NOR_MAX_ID_LEN];
263 u8 id_len;
264
265 /* The size listed here is what works with SPINOR_OP_SE, which isn't
266 * necessarily called a "sector" by the vendor.
267 */
268 unsigned sector_size;
269 u16 n_sectors;
270
271 u16 page_size;
272 u16 addr_width;
273
274 u32 flags;
275#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
276#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
277#define SST_WRITE BIT(2) /* use SST byte programming */
278#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
279#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
280#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
281#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
282#define USE_FSR BIT(7) /* use flag status register */
283#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
284#define SPI_NOR_HAS_TB BIT(9) /*
285 * Flash SR has Top/Bottom (TB) protect
286 * bit. Must be used with
287 * SPI_NOR_HAS_LOCK.
288 */
289#define SPI_NOR_XSR_RDY BIT(10) /*
290 * S3AN flashes have specific opcode to
291 * read the status register.
292 */
293#define SPI_NOR_4B_OPCODES BIT(11) /*
294 * Use dedicated 4byte address op codes
295 * to support memory size above 128Mib.
296 */
297#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
298#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
299#define USE_CLSR BIT(14) /* use CLSR command */
300#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
301#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
302 * Top/Bottom (TB) is bit 6 of
303 * status register. Must be used with
304 * SPI_NOR_HAS_TB.
305 */
306#define SPI_NOR_4BIT_BP BIT(17) /*
307 * Flash SR has 4 bit fields (BP0-3)
308 * for block protection.
309 */
310#define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
311 * BP3 is bit 6 of status register.
312 * Must be used with SPI_NOR_4BIT_BP.
313 */
314
315 /* Part specific fixup hooks. */
316 const struct spi_nor_fixups *fixups;
317};
318
319/* Used when the "_ext_id" is two bytes at most */
320#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
321 .id = { \
322 ((_jedec_id) >> 16) & 0xff, \
323 ((_jedec_id) >> 8) & 0xff, \
324 (_jedec_id) & 0xff, \
325 ((_ext_id) >> 8) & 0xff, \
326 (_ext_id) & 0xff, \
327 }, \
328 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
329 .sector_size = (_sector_size), \
330 .n_sectors = (_n_sectors), \
331 .page_size = 256, \
332 .flags = (_flags),
333
334#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
335 .id = { \
336 ((_jedec_id) >> 16) & 0xff, \
337 ((_jedec_id) >> 8) & 0xff, \
338 (_jedec_id) & 0xff, \
339 ((_ext_id) >> 16) & 0xff, \
340 ((_ext_id) >> 8) & 0xff, \
341 (_ext_id) & 0xff, \
342 }, \
343 .id_len = 6, \
344 .sector_size = (_sector_size), \
345 .n_sectors = (_n_sectors), \
346 .page_size = 256, \
347 .flags = (_flags),
348
349#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
350 .sector_size = (_sector_size), \
351 .n_sectors = (_n_sectors), \
352 .page_size = (_page_size), \
353 .addr_width = (_addr_width), \
354 .flags = (_flags),
355
356#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
357 .id = { \
358 ((_jedec_id) >> 16) & 0xff, \
359 ((_jedec_id) >> 8) & 0xff, \
360 (_jedec_id) & 0xff \
361 }, \
362 .id_len = 3, \
363 .sector_size = (8*_page_size), \
364 .n_sectors = (_n_sectors), \
365 .page_size = _page_size, \
366 .addr_width = 3, \
367 .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
368
369/**
370 * struct spi_nor_manufacturer - SPI NOR manufacturer object
371 * @name: manufacturer name
372 * @parts: array of parts supported by this manufacturer
373 * @nparts: number of entries in the parts array
374 * @fixups: hooks called at various points in time during spi_nor_scan()
375 */
376struct spi_nor_manufacturer {
377 const char *name;
378 const struct flash_info *parts;
379 unsigned int nparts;
380 const struct spi_nor_fixups *fixups;
381};
382
383/* Manufacturer drivers. */
384extern const struct spi_nor_manufacturer spi_nor_atmel;
385extern const struct spi_nor_manufacturer spi_nor_catalyst;
386extern const struct spi_nor_manufacturer spi_nor_eon;
387extern const struct spi_nor_manufacturer spi_nor_esmt;
388extern const struct spi_nor_manufacturer spi_nor_everspin;
389extern const struct spi_nor_manufacturer spi_nor_fujitsu;
390extern const struct spi_nor_manufacturer spi_nor_gigadevice;
391extern const struct spi_nor_manufacturer spi_nor_intel;
392extern const struct spi_nor_manufacturer spi_nor_issi;
393extern const struct spi_nor_manufacturer spi_nor_macronix;
394extern const struct spi_nor_manufacturer spi_nor_micron;
395extern const struct spi_nor_manufacturer spi_nor_st;
396extern const struct spi_nor_manufacturer spi_nor_spansion;
397extern const struct spi_nor_manufacturer spi_nor_sst;
398extern const struct spi_nor_manufacturer spi_nor_winbond;
399extern const struct spi_nor_manufacturer spi_nor_xilinx;
400extern const struct spi_nor_manufacturer spi_nor_xmc;
401
402int spi_nor_write_enable(struct spi_nor *nor);
403int spi_nor_write_disable(struct spi_nor *nor);
404int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
405int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
406int spi_nor_wait_till_ready(struct spi_nor *nor);
407int spi_nor_lock_and_prep(struct spi_nor *nor);
408void spi_nor_unlock_and_unprep(struct spi_nor *nor);
409int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
410int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
411int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
412
413int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
414ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
415 u8 *buf);
416ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
417 const u8 *buf);
418
419int spi_nor_hwcaps_read2cmd(u32 hwcaps);
420u8 spi_nor_convert_3to4_read(u8 opcode);
421void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
422 enum spi_nor_protocol proto);
423
424void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
425 u8 opcode);
426struct spi_nor_erase_region *
427spi_nor_region_next(struct spi_nor_erase_region *region);
428void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
429 u8 erase_mask, u64 flash_size);
430
431int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
432 const struct sfdp_parameter_header *bfpt_header,
433 const struct sfdp_bfpt *bfpt,
434 struct spi_nor_flash_parameter *params);
435
436static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd)
437{
438 return mtd->priv;
439}
440
441#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */