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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51
52static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
53
54void sdhci_dumpregs(struct sdhci_host *host)
55{
56 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
57
58 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
61 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
79 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
92 sdhci_readl(host, SDHCI_RESPONSE),
93 sdhci_readl(host, SDHCI_RESPONSE + 4));
94 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE + 8),
96 sdhci_readl(host, SDHCI_RESPONSE + 12));
97 SDHCI_DUMP("Host ctl2: 0x%08x\n",
98 sdhci_readw(host, SDHCI_HOST_CONTROL2));
99
100 if (host->flags & SDHCI_USE_ADMA) {
101 if (host->flags & SDHCI_USE_64_BIT_DMA) {
102 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
103 sdhci_readl(host, SDHCI_ADMA_ERROR),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
106 } else {
107 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
108 sdhci_readl(host, SDHCI_ADMA_ERROR),
109 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
110 }
111 }
112
113 if (host->ops->dump_vendor_regs)
114 host->ops->dump_vendor_regs(host);
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127{
128 u16 ctrl2;
129
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return;
133
134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
136}
137
138/*
139 * This can be called before sdhci_add_host() by Vendor's host controller
140 * driver to enable v4 mode if supported.
141 */
142void sdhci_enable_v4_mode(struct sdhci_host *host)
143{
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
146}
147EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
148
149static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
150{
151 return cmd->data || cmd->flags & MMC_RSP_BUSY;
152}
153
154static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
155{
156 u32 present;
157
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
160 return;
161
162 if (enable) {
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
167 SDHCI_INT_CARD_INSERT;
168 } else {
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
170 }
171
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
174}
175
176static void sdhci_enable_card_detection(struct sdhci_host *host)
177{
178 sdhci_set_card_detection(host, true);
179}
180
181static void sdhci_disable_card_detection(struct sdhci_host *host)
182{
183 sdhci_set_card_detection(host, false);
184}
185
186static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187{
188 if (host->bus_on)
189 return;
190 host->bus_on = true;
191 pm_runtime_get_noresume(mmc_dev(host->mmc));
192}
193
194static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
195{
196 if (!host->bus_on)
197 return;
198 host->bus_on = false;
199 pm_runtime_put_noidle(mmc_dev(host->mmc));
200}
201
202void sdhci_reset(struct sdhci_host *host, u8 mask)
203{
204 ktime_t timeout;
205
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
207
208 if (mask & SDHCI_RESET_ALL) {
209 host->clock = 0;
210 /* Reset-all turns off SD Bus Power */
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
213 }
214
215 /* Wait max 100 ms */
216 timeout = ktime_add_ms(ktime_get(), 100);
217
218 /* hw clears the bit when it's done */
219 while (1) {
220 bool timedout = ktime_after(ktime_get(), timeout);
221
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
223 break;
224 if (timedout) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
228 sdhci_dumpregs(host);
229 return;
230 }
231 udelay(10);
232 }
233}
234EXPORT_SYMBOL_GPL(sdhci_reset);
235
236static bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
237{
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
239 struct mmc_host *mmc = host->mmc;
240
241 if (!mmc->ops->get_cd(mmc))
242 return false;
243 }
244
245 host->ops->reset(host, mask);
246
247 return true;
248}
249
250static void sdhci_reset_for_all(struct sdhci_host *host)
251{
252 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
253 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
254 if (host->ops->enable_dma)
255 host->ops->enable_dma(host);
256 }
257 /* Resetting the controller clears many */
258 host->preset_enabled = false;
259 }
260}
261
262enum sdhci_reset_reason {
263 SDHCI_RESET_FOR_INIT,
264 SDHCI_RESET_FOR_REQUEST_ERROR,
265 SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
266 SDHCI_RESET_FOR_TUNING_ABORT,
267 SDHCI_RESET_FOR_CARD_REMOVED,
268 SDHCI_RESET_FOR_CQE_RECOVERY,
269};
270
271static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
272{
273 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
274 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
275 return;
276 }
277
278 switch (reason) {
279 case SDHCI_RESET_FOR_INIT:
280 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
281 break;
282 case SDHCI_RESET_FOR_REQUEST_ERROR:
283 case SDHCI_RESET_FOR_TUNING_ABORT:
284 case SDHCI_RESET_FOR_CARD_REMOVED:
285 case SDHCI_RESET_FOR_CQE_RECOVERY:
286 sdhci_do_reset(host, SDHCI_RESET_CMD);
287 sdhci_do_reset(host, SDHCI_RESET_DATA);
288 break;
289 case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
291 break;
292 }
293}
294
295#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
296
297static void sdhci_set_default_irqs(struct sdhci_host *host)
298{
299 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
300 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
301 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
302 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
303 SDHCI_INT_RESPONSE;
304
305 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
306 host->tuning_mode == SDHCI_TUNING_MODE_3)
307 host->ier |= SDHCI_INT_RETUNE;
308
309 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
310 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
311}
312
313static void sdhci_config_dma(struct sdhci_host *host)
314{
315 u8 ctrl;
316 u16 ctrl2;
317
318 if (host->version < SDHCI_SPEC_200)
319 return;
320
321 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
322
323 /*
324 * Always adjust the DMA selection as some controllers
325 * (e.g. JMicron) can't do PIO properly when the selection
326 * is ADMA.
327 */
328 ctrl &= ~SDHCI_CTRL_DMA_MASK;
329 if (!(host->flags & SDHCI_REQ_USE_DMA))
330 goto out;
331
332 /* Note if DMA Select is zero then SDMA is selected */
333 if (host->flags & SDHCI_USE_ADMA)
334 ctrl |= SDHCI_CTRL_ADMA32;
335
336 if (host->flags & SDHCI_USE_64_BIT_DMA) {
337 /*
338 * If v4 mode, all supported DMA can be 64-bit addressing if
339 * controller supports 64-bit system address, otherwise only
340 * ADMA can support 64-bit addressing.
341 */
342 if (host->v4_mode) {
343 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
344 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
345 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
346 } else if (host->flags & SDHCI_USE_ADMA) {
347 /*
348 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
349 * set SDHCI_CTRL_ADMA64.
350 */
351 ctrl |= SDHCI_CTRL_ADMA64;
352 }
353 }
354
355out:
356 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
357}
358
359static void sdhci_init(struct sdhci_host *host, int soft)
360{
361 struct mmc_host *mmc = host->mmc;
362 unsigned long flags;
363
364 if (soft)
365 sdhci_reset_for(host, INIT);
366 else
367 sdhci_reset_for_all(host);
368
369 if (host->v4_mode)
370 sdhci_do_enable_v4_mode(host);
371
372 spin_lock_irqsave(&host->lock, flags);
373 sdhci_set_default_irqs(host);
374 spin_unlock_irqrestore(&host->lock, flags);
375
376 host->cqe_on = false;
377
378 if (soft) {
379 /* force clock reconfiguration */
380 host->clock = 0;
381 host->reinit_uhs = true;
382 mmc->ops->set_ios(mmc, &mmc->ios);
383 }
384}
385
386static void sdhci_reinit(struct sdhci_host *host)
387{
388 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
389
390 sdhci_init(host, 0);
391 sdhci_enable_card_detection(host);
392
393 /*
394 * A change to the card detect bits indicates a change in present state,
395 * refer sdhci_set_card_detection(). A card detect interrupt might have
396 * been missed while the host controller was being reset, so trigger a
397 * rescan to check.
398 */
399 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
400 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
401}
402
403static void __sdhci_led_activate(struct sdhci_host *host)
404{
405 u8 ctrl;
406
407 if (host->quirks & SDHCI_QUIRK_NO_LED)
408 return;
409
410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
411 ctrl |= SDHCI_CTRL_LED;
412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
413}
414
415static void __sdhci_led_deactivate(struct sdhci_host *host)
416{
417 u8 ctrl;
418
419 if (host->quirks & SDHCI_QUIRK_NO_LED)
420 return;
421
422 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
423 ctrl &= ~SDHCI_CTRL_LED;
424 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
425}
426
427#if IS_REACHABLE(CONFIG_LEDS_CLASS)
428static void sdhci_led_control(struct led_classdev *led,
429 enum led_brightness brightness)
430{
431 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
432 unsigned long flags;
433
434 spin_lock_irqsave(&host->lock, flags);
435
436 if (host->runtime_suspended)
437 goto out;
438
439 if (brightness == LED_OFF)
440 __sdhci_led_deactivate(host);
441 else
442 __sdhci_led_activate(host);
443out:
444 spin_unlock_irqrestore(&host->lock, flags);
445}
446
447static int sdhci_led_register(struct sdhci_host *host)
448{
449 struct mmc_host *mmc = host->mmc;
450
451 if (host->quirks & SDHCI_QUIRK_NO_LED)
452 return 0;
453
454 snprintf(host->led_name, sizeof(host->led_name),
455 "%s::", mmc_hostname(mmc));
456
457 host->led.name = host->led_name;
458 host->led.brightness = LED_OFF;
459 host->led.default_trigger = mmc_hostname(mmc);
460 host->led.brightness_set = sdhci_led_control;
461
462 return led_classdev_register(mmc_dev(mmc), &host->led);
463}
464
465static void sdhci_led_unregister(struct sdhci_host *host)
466{
467 if (host->quirks & SDHCI_QUIRK_NO_LED)
468 return;
469
470 led_classdev_unregister(&host->led);
471}
472
473static inline void sdhci_led_activate(struct sdhci_host *host)
474{
475}
476
477static inline void sdhci_led_deactivate(struct sdhci_host *host)
478{
479}
480
481#else
482
483static inline int sdhci_led_register(struct sdhci_host *host)
484{
485 return 0;
486}
487
488static inline void sdhci_led_unregister(struct sdhci_host *host)
489{
490}
491
492static inline void sdhci_led_activate(struct sdhci_host *host)
493{
494 __sdhci_led_activate(host);
495}
496
497static inline void sdhci_led_deactivate(struct sdhci_host *host)
498{
499 __sdhci_led_deactivate(host);
500}
501
502#endif
503
504static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
505 unsigned long timeout)
506{
507 if (sdhci_data_line_cmd(mrq->cmd))
508 mod_timer(&host->data_timer, timeout);
509 else
510 mod_timer(&host->timer, timeout);
511}
512
513static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
514{
515 if (sdhci_data_line_cmd(mrq->cmd))
516 del_timer(&host->data_timer);
517 else
518 del_timer(&host->timer);
519}
520
521static inline bool sdhci_has_requests(struct sdhci_host *host)
522{
523 return host->cmd || host->data_cmd;
524}
525
526/*****************************************************************************\
527 * *
528 * Core functions *
529 * *
530\*****************************************************************************/
531
532static void sdhci_read_block_pio(struct sdhci_host *host)
533{
534 size_t blksize, len, chunk;
535 u32 scratch;
536 u8 *buf;
537
538 DBG("PIO reading\n");
539
540 blksize = host->data->blksz;
541 chunk = 0;
542
543 while (blksize) {
544 BUG_ON(!sg_miter_next(&host->sg_miter));
545
546 len = min(host->sg_miter.length, blksize);
547
548 blksize -= len;
549 host->sg_miter.consumed = len;
550
551 buf = host->sg_miter.addr;
552
553 while (len) {
554 if (chunk == 0) {
555 scratch = sdhci_readl(host, SDHCI_BUFFER);
556 chunk = 4;
557 }
558
559 *buf = scratch & 0xFF;
560
561 buf++;
562 scratch >>= 8;
563 chunk--;
564 len--;
565 }
566 }
567
568 sg_miter_stop(&host->sg_miter);
569}
570
571static void sdhci_write_block_pio(struct sdhci_host *host)
572{
573 size_t blksize, len, chunk;
574 u32 scratch;
575 u8 *buf;
576
577 DBG("PIO writing\n");
578
579 blksize = host->data->blksz;
580 chunk = 0;
581 scratch = 0;
582
583 while (blksize) {
584 BUG_ON(!sg_miter_next(&host->sg_miter));
585
586 len = min(host->sg_miter.length, blksize);
587
588 blksize -= len;
589 host->sg_miter.consumed = len;
590
591 buf = host->sg_miter.addr;
592
593 while (len) {
594 scratch |= (u32)*buf << (chunk * 8);
595
596 buf++;
597 chunk++;
598 len--;
599
600 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
601 sdhci_writel(host, scratch, SDHCI_BUFFER);
602 chunk = 0;
603 scratch = 0;
604 }
605 }
606 }
607
608 sg_miter_stop(&host->sg_miter);
609}
610
611static void sdhci_transfer_pio(struct sdhci_host *host)
612{
613 u32 mask;
614
615 if (host->blocks == 0)
616 return;
617
618 if (host->data->flags & MMC_DATA_READ)
619 mask = SDHCI_DATA_AVAILABLE;
620 else
621 mask = SDHCI_SPACE_AVAILABLE;
622
623 /*
624 * Some controllers (JMicron JMB38x) mess up the buffer bits
625 * for transfers < 4 bytes. As long as it is just one block,
626 * we can ignore the bits.
627 */
628 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
629 (host->data->blocks == 1))
630 mask = ~0;
631
632 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
633 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
634 udelay(100);
635
636 if (host->data->flags & MMC_DATA_READ)
637 sdhci_read_block_pio(host);
638 else
639 sdhci_write_block_pio(host);
640
641 host->blocks--;
642 if (host->blocks == 0)
643 break;
644 }
645
646 DBG("PIO transfer complete.\n");
647}
648
649static int sdhci_pre_dma_transfer(struct sdhci_host *host,
650 struct mmc_data *data, int cookie)
651{
652 int sg_count;
653
654 /*
655 * If the data buffers are already mapped, return the previous
656 * dma_map_sg() result.
657 */
658 if (data->host_cookie == COOKIE_PRE_MAPPED)
659 return data->sg_count;
660
661 /* Bounce write requests to the bounce buffer */
662 if (host->bounce_buffer) {
663 unsigned int length = data->blksz * data->blocks;
664
665 if (length > host->bounce_buffer_size) {
666 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
667 mmc_hostname(host->mmc), length,
668 host->bounce_buffer_size);
669 return -EIO;
670 }
671 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
672 /* Copy the data to the bounce buffer */
673 if (host->ops->copy_to_bounce_buffer) {
674 host->ops->copy_to_bounce_buffer(host,
675 data, length);
676 } else {
677 sg_copy_to_buffer(data->sg, data->sg_len,
678 host->bounce_buffer, length);
679 }
680 }
681 /* Switch ownership to the DMA */
682 dma_sync_single_for_device(mmc_dev(host->mmc),
683 host->bounce_addr,
684 host->bounce_buffer_size,
685 mmc_get_dma_dir(data));
686 /* Just a dummy value */
687 sg_count = 1;
688 } else {
689 /* Just access the data directly from memory */
690 sg_count = dma_map_sg(mmc_dev(host->mmc),
691 data->sg, data->sg_len,
692 mmc_get_dma_dir(data));
693 }
694
695 if (sg_count == 0)
696 return -ENOSPC;
697
698 data->sg_count = sg_count;
699 data->host_cookie = cookie;
700
701 return sg_count;
702}
703
704static char *sdhci_kmap_atomic(struct scatterlist *sg)
705{
706 return kmap_local_page(sg_page(sg)) + sg->offset;
707}
708
709static void sdhci_kunmap_atomic(void *buffer)
710{
711 kunmap_local(buffer);
712}
713
714void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
715 dma_addr_t addr, int len, unsigned int cmd)
716{
717 struct sdhci_adma2_64_desc *dma_desc = *desc;
718
719 /* 32-bit and 64-bit descriptors have these members in same position */
720 dma_desc->cmd = cpu_to_le16(cmd);
721 dma_desc->len = cpu_to_le16(len);
722 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
723
724 if (host->flags & SDHCI_USE_64_BIT_DMA)
725 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
726
727 *desc += host->desc_sz;
728}
729EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
730
731static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
732 void **desc, dma_addr_t addr,
733 int len, unsigned int cmd)
734{
735 if (host->ops->adma_write_desc)
736 host->ops->adma_write_desc(host, desc, addr, len, cmd);
737 else
738 sdhci_adma_write_desc(host, desc, addr, len, cmd);
739}
740
741static void sdhci_adma_mark_end(void *desc)
742{
743 struct sdhci_adma2_64_desc *dma_desc = desc;
744
745 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
746 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
747}
748
749static void sdhci_adma_table_pre(struct sdhci_host *host,
750 struct mmc_data *data, int sg_count)
751{
752 struct scatterlist *sg;
753 dma_addr_t addr, align_addr;
754 void *desc, *align;
755 char *buffer;
756 int len, offset, i;
757
758 /*
759 * The spec does not specify endianness of descriptor table.
760 * We currently guess that it is LE.
761 */
762
763 host->sg_count = sg_count;
764
765 desc = host->adma_table;
766 align = host->align_buffer;
767
768 align_addr = host->align_addr;
769
770 for_each_sg(data->sg, sg, host->sg_count, i) {
771 addr = sg_dma_address(sg);
772 len = sg_dma_len(sg);
773
774 /*
775 * The SDHCI specification states that ADMA addresses must
776 * be 32-bit aligned. If they aren't, then we use a bounce
777 * buffer for the (up to three) bytes that screw up the
778 * alignment.
779 */
780 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
781 SDHCI_ADMA2_MASK;
782 if (offset) {
783 if (data->flags & MMC_DATA_WRITE) {
784 buffer = sdhci_kmap_atomic(sg);
785 memcpy(align, buffer, offset);
786 sdhci_kunmap_atomic(buffer);
787 }
788
789 /* tran, valid */
790 __sdhci_adma_write_desc(host, &desc, align_addr,
791 offset, ADMA2_TRAN_VALID);
792
793 BUG_ON(offset > 65536);
794
795 align += SDHCI_ADMA2_ALIGN;
796 align_addr += SDHCI_ADMA2_ALIGN;
797
798 addr += offset;
799 len -= offset;
800 }
801
802 /*
803 * The block layer forces a minimum segment size of PAGE_SIZE,
804 * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
805 * multiple descriptors, noting that the ADMA table is sized
806 * for 4KiB chunks anyway, so it will be big enough.
807 */
808 while (len > host->max_adma) {
809 int n = 32 * 1024; /* 32KiB*/
810
811 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
812 addr += n;
813 len -= n;
814 }
815
816 /* tran, valid */
817 if (len)
818 __sdhci_adma_write_desc(host, &desc, addr, len,
819 ADMA2_TRAN_VALID);
820
821 /*
822 * If this triggers then we have a calculation bug
823 * somewhere. :/
824 */
825 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
826 }
827
828 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
829 /* Mark the last descriptor as the terminating descriptor */
830 if (desc != host->adma_table) {
831 desc -= host->desc_sz;
832 sdhci_adma_mark_end(desc);
833 }
834 } else {
835 /* Add a terminating entry - nop, end, valid */
836 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
837 }
838}
839
840static void sdhci_adma_table_post(struct sdhci_host *host,
841 struct mmc_data *data)
842{
843 struct scatterlist *sg;
844 int i, size;
845 void *align;
846 char *buffer;
847
848 if (data->flags & MMC_DATA_READ) {
849 bool has_unaligned = false;
850
851 /* Do a quick scan of the SG list for any unaligned mappings */
852 for_each_sg(data->sg, sg, host->sg_count, i)
853 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
854 has_unaligned = true;
855 break;
856 }
857
858 if (has_unaligned) {
859 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
860 data->sg_len, DMA_FROM_DEVICE);
861
862 align = host->align_buffer;
863
864 for_each_sg(data->sg, sg, host->sg_count, i) {
865 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
866 size = SDHCI_ADMA2_ALIGN -
867 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
868
869 buffer = sdhci_kmap_atomic(sg);
870 memcpy(buffer, align, size);
871 sdhci_kunmap_atomic(buffer);
872
873 align += SDHCI_ADMA2_ALIGN;
874 }
875 }
876 }
877 }
878}
879
880static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
881{
882 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
883 if (host->flags & SDHCI_USE_64_BIT_DMA)
884 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
885}
886
887static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
888{
889 if (host->bounce_buffer)
890 return host->bounce_addr;
891 else
892 return sg_dma_address(host->data->sg);
893}
894
895static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
896{
897 if (host->v4_mode)
898 sdhci_set_adma_addr(host, addr);
899 else
900 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
901}
902
903static unsigned int sdhci_target_timeout(struct sdhci_host *host,
904 struct mmc_command *cmd,
905 struct mmc_data *data)
906{
907 unsigned int target_timeout;
908
909 /* timeout in us */
910 if (!data) {
911 target_timeout = cmd->busy_timeout * 1000;
912 } else {
913 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
914 if (host->clock && data->timeout_clks) {
915 unsigned long long val;
916
917 /*
918 * data->timeout_clks is in units of clock cycles.
919 * host->clock is in Hz. target_timeout is in us.
920 * Hence, us = 1000000 * cycles / Hz. Round up.
921 */
922 val = 1000000ULL * data->timeout_clks;
923 if (do_div(val, host->clock))
924 target_timeout++;
925 target_timeout += val;
926 }
927 }
928
929 return target_timeout;
930}
931
932static void sdhci_calc_sw_timeout(struct sdhci_host *host,
933 struct mmc_command *cmd)
934{
935 struct mmc_data *data = cmd->data;
936 struct mmc_host *mmc = host->mmc;
937 struct mmc_ios *ios = &mmc->ios;
938 unsigned char bus_width = 1 << ios->bus_width;
939 unsigned int blksz;
940 unsigned int freq;
941 u64 target_timeout;
942 u64 transfer_time;
943
944 target_timeout = sdhci_target_timeout(host, cmd, data);
945 target_timeout *= NSEC_PER_USEC;
946
947 if (data) {
948 blksz = data->blksz;
949 freq = mmc->actual_clock ? : host->clock;
950 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
951 do_div(transfer_time, freq);
952 /* multiply by '2' to account for any unknowns */
953 transfer_time = transfer_time * 2;
954 /* calculate timeout for the entire data */
955 host->data_timeout = data->blocks * target_timeout +
956 transfer_time;
957 } else {
958 host->data_timeout = target_timeout;
959 }
960
961 if (host->data_timeout)
962 host->data_timeout += MMC_CMD_TRANSFER_TIME;
963}
964
965static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
966 bool *too_big)
967{
968 u8 count;
969 struct mmc_data *data;
970 unsigned target_timeout, current_timeout;
971
972 *too_big = false;
973
974 /*
975 * If the host controller provides us with an incorrect timeout
976 * value, just skip the check and use the maximum. The hardware may take
977 * longer to time out, but that's much better than having a too-short
978 * timeout value.
979 */
980 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
981 return host->max_timeout_count;
982
983 /* Unspecified command, assume max */
984 if (cmd == NULL)
985 return host->max_timeout_count;
986
987 data = cmd->data;
988 /* Unspecified timeout, assume max */
989 if (!data && !cmd->busy_timeout)
990 return host->max_timeout_count;
991
992 /* timeout in us */
993 target_timeout = sdhci_target_timeout(host, cmd, data);
994
995 /*
996 * Figure out needed cycles.
997 * We do this in steps in order to fit inside a 32 bit int.
998 * The first step is the minimum timeout, which will have a
999 * minimum resolution of 6 bits:
1000 * (1) 2^13*1000 > 2^22,
1001 * (2) host->timeout_clk < 2^16
1002 * =>
1003 * (1) / (2) > 2^6
1004 */
1005 count = 0;
1006 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1007 while (current_timeout < target_timeout) {
1008 count++;
1009 current_timeout <<= 1;
1010 if (count > host->max_timeout_count) {
1011 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1012 DBG("Too large timeout 0x%x requested for CMD%d!\n",
1013 count, cmd->opcode);
1014 count = host->max_timeout_count;
1015 *too_big = true;
1016 break;
1017 }
1018 }
1019
1020 return count;
1021}
1022
1023static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1024{
1025 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1026 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1027
1028 if (host->flags & SDHCI_REQ_USE_DMA)
1029 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1030 else
1031 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1032
1033 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1034 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1035 else
1036 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1037
1038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1040}
1041
1042void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1043{
1044 if (enable)
1045 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1046 else
1047 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1048 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1049 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1050}
1051EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1052
1053void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1054{
1055 bool too_big = false;
1056 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1057
1058 if (too_big &&
1059 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1060 sdhci_calc_sw_timeout(host, cmd);
1061 sdhci_set_data_timeout_irq(host, false);
1062 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1063 sdhci_set_data_timeout_irq(host, true);
1064 }
1065
1066 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1067}
1068EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1069
1070static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1071{
1072 if (host->ops->set_timeout)
1073 host->ops->set_timeout(host, cmd);
1074 else
1075 __sdhci_set_timeout(host, cmd);
1076}
1077
1078static void sdhci_initialize_data(struct sdhci_host *host,
1079 struct mmc_data *data)
1080{
1081 WARN_ON(host->data);
1082
1083 /* Sanity checks */
1084 BUG_ON(data->blksz * data->blocks > 524288);
1085 BUG_ON(data->blksz > host->mmc->max_blk_size);
1086 BUG_ON(data->blocks > 65535);
1087
1088 host->data = data;
1089 host->data_early = 0;
1090 host->data->bytes_xfered = 0;
1091}
1092
1093static inline void sdhci_set_block_info(struct sdhci_host *host,
1094 struct mmc_data *data)
1095{
1096 /* Set the DMA boundary value and block size */
1097 sdhci_writew(host,
1098 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1099 SDHCI_BLOCK_SIZE);
1100 /*
1101 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1102 * can be supported, in that case 16-bit block count register must be 0.
1103 */
1104 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1105 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1106 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1107 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1108 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1109 } else {
1110 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1111 }
1112}
1113
1114static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1115{
1116 struct mmc_data *data = cmd->data;
1117
1118 sdhci_initialize_data(host, data);
1119
1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1121 struct scatterlist *sg;
1122 unsigned int length_mask, offset_mask;
1123 int i;
1124
1125 host->flags |= SDHCI_REQ_USE_DMA;
1126
1127 /*
1128 * FIXME: This doesn't account for merging when mapping the
1129 * scatterlist.
1130 *
1131 * The assumption here being that alignment and lengths are
1132 * the same after DMA mapping to device address space.
1133 */
1134 length_mask = 0;
1135 offset_mask = 0;
1136 if (host->flags & SDHCI_USE_ADMA) {
1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1138 length_mask = 3;
1139 /*
1140 * As we use up to 3 byte chunks to work
1141 * around alignment problems, we need to
1142 * check the offset as well.
1143 */
1144 offset_mask = 3;
1145 }
1146 } else {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1148 length_mask = 3;
1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1150 offset_mask = 3;
1151 }
1152
1153 if (unlikely(length_mask | offset_mask)) {
1154 for_each_sg(data->sg, sg, data->sg_len, i) {
1155 if (sg->length & length_mask) {
1156 DBG("Reverting to PIO because of transfer size (%d)\n",
1157 sg->length);
1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1159 break;
1160 }
1161 if (sg->offset & offset_mask) {
1162 DBG("Reverting to PIO because of bad alignment\n");
1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1164 break;
1165 }
1166 }
1167 }
1168 }
1169
1170 sdhci_config_dma(host);
1171
1172 if (host->flags & SDHCI_REQ_USE_DMA) {
1173 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1174
1175 if (sg_cnt <= 0) {
1176 /*
1177 * This only happens when someone fed
1178 * us an invalid request.
1179 */
1180 WARN_ON(1);
1181 host->flags &= ~SDHCI_REQ_USE_DMA;
1182 } else if (host->flags & SDHCI_USE_ADMA) {
1183 sdhci_adma_table_pre(host, data, sg_cnt);
1184 sdhci_set_adma_addr(host, host->adma_addr);
1185 } else {
1186 WARN_ON(sg_cnt != 1);
1187 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1188 }
1189 }
1190
1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1192 int flags;
1193
1194 flags = SG_MITER_ATOMIC;
1195 if (host->data->flags & MMC_DATA_READ)
1196 flags |= SG_MITER_TO_SG;
1197 else
1198 flags |= SG_MITER_FROM_SG;
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200 host->blocks = data->blocks;
1201 }
1202
1203 sdhci_set_transfer_irqs(host);
1204
1205 sdhci_set_block_info(host, data);
1206}
1207
1208#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1209
1210static int sdhci_external_dma_init(struct sdhci_host *host)
1211{
1212 int ret = 0;
1213 struct mmc_host *mmc = host->mmc;
1214
1215 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1216 if (IS_ERR(host->tx_chan)) {
1217 ret = PTR_ERR(host->tx_chan);
1218 if (ret != -EPROBE_DEFER)
1219 pr_warn("Failed to request TX DMA channel.\n");
1220 host->tx_chan = NULL;
1221 return ret;
1222 }
1223
1224 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1225 if (IS_ERR(host->rx_chan)) {
1226 if (host->tx_chan) {
1227 dma_release_channel(host->tx_chan);
1228 host->tx_chan = NULL;
1229 }
1230
1231 ret = PTR_ERR(host->rx_chan);
1232 if (ret != -EPROBE_DEFER)
1233 pr_warn("Failed to request RX DMA channel.\n");
1234 host->rx_chan = NULL;
1235 }
1236
1237 return ret;
1238}
1239
1240static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1241 struct mmc_data *data)
1242{
1243 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1244}
1245
1246static int sdhci_external_dma_setup(struct sdhci_host *host,
1247 struct mmc_command *cmd)
1248{
1249 int ret, i;
1250 enum dma_transfer_direction dir;
1251 struct dma_async_tx_descriptor *desc;
1252 struct mmc_data *data = cmd->data;
1253 struct dma_chan *chan;
1254 struct dma_slave_config cfg;
1255 dma_cookie_t cookie;
1256 int sg_cnt;
1257
1258 if (!host->mapbase)
1259 return -EINVAL;
1260
1261 memset(&cfg, 0, sizeof(cfg));
1262 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1263 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1264 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1265 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1266 cfg.src_maxburst = data->blksz / 4;
1267 cfg.dst_maxburst = data->blksz / 4;
1268
1269 /* Sanity check: all the SG entries must be aligned by block size. */
1270 for (i = 0; i < data->sg_len; i++) {
1271 if ((data->sg + i)->length % data->blksz)
1272 return -EINVAL;
1273 }
1274
1275 chan = sdhci_external_dma_channel(host, data);
1276
1277 ret = dmaengine_slave_config(chan, &cfg);
1278 if (ret)
1279 return ret;
1280
1281 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1282 if (sg_cnt <= 0)
1283 return -EINVAL;
1284
1285 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1286 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1287 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1288 if (!desc)
1289 return -EINVAL;
1290
1291 desc->callback = NULL;
1292 desc->callback_param = NULL;
1293
1294 cookie = dmaengine_submit(desc);
1295 if (dma_submit_error(cookie))
1296 ret = cookie;
1297
1298 return ret;
1299}
1300
1301static void sdhci_external_dma_release(struct sdhci_host *host)
1302{
1303 if (host->tx_chan) {
1304 dma_release_channel(host->tx_chan);
1305 host->tx_chan = NULL;
1306 }
1307
1308 if (host->rx_chan) {
1309 dma_release_channel(host->rx_chan);
1310 host->rx_chan = NULL;
1311 }
1312
1313 sdhci_switch_external_dma(host, false);
1314}
1315
1316static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1317 struct mmc_command *cmd)
1318{
1319 struct mmc_data *data = cmd->data;
1320
1321 sdhci_initialize_data(host, data);
1322
1323 host->flags |= SDHCI_REQ_USE_DMA;
1324 sdhci_set_transfer_irqs(host);
1325
1326 sdhci_set_block_info(host, data);
1327}
1328
1329static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1330 struct mmc_command *cmd)
1331{
1332 if (!sdhci_external_dma_setup(host, cmd)) {
1333 __sdhci_external_dma_prepare_data(host, cmd);
1334 } else {
1335 sdhci_external_dma_release(host);
1336 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1337 mmc_hostname(host->mmc));
1338 sdhci_prepare_data(host, cmd);
1339 }
1340}
1341
1342static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1343 struct mmc_command *cmd)
1344{
1345 struct dma_chan *chan;
1346
1347 if (!cmd->data)
1348 return;
1349
1350 chan = sdhci_external_dma_channel(host, cmd->data);
1351 if (chan)
1352 dma_async_issue_pending(chan);
1353}
1354
1355#else
1356
1357static inline int sdhci_external_dma_init(struct sdhci_host *host)
1358{
1359 return -EOPNOTSUPP;
1360}
1361
1362static inline void sdhci_external_dma_release(struct sdhci_host *host)
1363{
1364}
1365
1366static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1367 struct mmc_command *cmd)
1368{
1369 /* This should never happen */
1370 WARN_ON_ONCE(1);
1371}
1372
1373static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1374 struct mmc_command *cmd)
1375{
1376}
1377
1378static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1379 struct mmc_data *data)
1380{
1381 return NULL;
1382}
1383
1384#endif
1385
1386void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1387{
1388 host->use_external_dma = en;
1389}
1390EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1391
1392static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1393 struct mmc_request *mrq)
1394{
1395 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1396 !mrq->cap_cmd_during_tfr;
1397}
1398
1399static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1400 struct mmc_request *mrq)
1401{
1402 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1403}
1404
1405static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1406 struct mmc_request *mrq)
1407{
1408 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1409}
1410
1411static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1412 struct mmc_command *cmd,
1413 u16 *mode)
1414{
1415 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1416 (cmd->opcode != SD_IO_RW_EXTENDED);
1417 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1418 u16 ctrl2;
1419
1420 /*
1421 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1422 * Select' is recommended rather than use of 'Auto CMD12
1423 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1424 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1425 */
1426 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1427 (use_cmd12 || use_cmd23)) {
1428 *mode |= SDHCI_TRNS_AUTO_SEL;
1429
1430 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1431 if (use_cmd23)
1432 ctrl2 |= SDHCI_CMD23_ENABLE;
1433 else
1434 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1435 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1436
1437 return;
1438 }
1439
1440 /*
1441 * If we are sending CMD23, CMD12 never gets sent
1442 * on successful completion (so no Auto-CMD12).
1443 */
1444 if (use_cmd12)
1445 *mode |= SDHCI_TRNS_AUTO_CMD12;
1446 else if (use_cmd23)
1447 *mode |= SDHCI_TRNS_AUTO_CMD23;
1448}
1449
1450static void sdhci_set_transfer_mode(struct sdhci_host *host,
1451 struct mmc_command *cmd)
1452{
1453 u16 mode = 0;
1454 struct mmc_data *data = cmd->data;
1455
1456 if (data == NULL) {
1457 if (host->quirks2 &
1458 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1459 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1460 if (!mmc_op_tuning(cmd->opcode))
1461 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1462 } else {
1463 /* clear Auto CMD settings for no data CMDs */
1464 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1465 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1466 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1467 }
1468 return;
1469 }
1470
1471 WARN_ON(!host->data);
1472
1473 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1474 mode = SDHCI_TRNS_BLK_CNT_EN;
1475
1476 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1477 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1478 sdhci_auto_cmd_select(host, cmd, &mode);
1479 if (sdhci_auto_cmd23(host, cmd->mrq))
1480 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1481 }
1482
1483 if (data->flags & MMC_DATA_READ)
1484 mode |= SDHCI_TRNS_READ;
1485 if (host->flags & SDHCI_REQ_USE_DMA)
1486 mode |= SDHCI_TRNS_DMA;
1487
1488 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1489}
1490
1491static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1492{
1493 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1494 ((mrq->cmd && mrq->cmd->error) ||
1495 (mrq->sbc && mrq->sbc->error) ||
1496 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1497 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1498}
1499
1500static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1501{
1502 int i;
1503
1504 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1505 if (host->mrqs_done[i] == mrq) {
1506 WARN_ON(1);
1507 return;
1508 }
1509 }
1510
1511 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1512 if (!host->mrqs_done[i]) {
1513 host->mrqs_done[i] = mrq;
1514 break;
1515 }
1516 }
1517
1518 WARN_ON(i >= SDHCI_MAX_MRQS);
1519}
1520
1521static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1522{
1523 if (host->cmd && host->cmd->mrq == mrq)
1524 host->cmd = NULL;
1525
1526 if (host->data_cmd && host->data_cmd->mrq == mrq)
1527 host->data_cmd = NULL;
1528
1529 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1530 host->deferred_cmd = NULL;
1531
1532 if (host->data && host->data->mrq == mrq)
1533 host->data = NULL;
1534
1535 if (sdhci_needs_reset(host, mrq))
1536 host->pending_reset = true;
1537
1538 sdhci_set_mrq_done(host, mrq);
1539
1540 sdhci_del_timer(host, mrq);
1541
1542 if (!sdhci_has_requests(host))
1543 sdhci_led_deactivate(host);
1544}
1545
1546static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1547{
1548 __sdhci_finish_mrq(host, mrq);
1549
1550 queue_work(host->complete_wq, &host->complete_work);
1551}
1552
1553static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1554{
1555 struct mmc_command *data_cmd = host->data_cmd;
1556 struct mmc_data *data = host->data;
1557
1558 host->data = NULL;
1559 host->data_cmd = NULL;
1560
1561 /*
1562 * The controller needs a reset of internal state machines upon error
1563 * conditions.
1564 */
1565 if (data->error) {
1566 if (!host->cmd || host->cmd == data_cmd)
1567 sdhci_reset_for(host, REQUEST_ERROR);
1568 else
1569 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
1570 }
1571
1572 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1573 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1574 sdhci_adma_table_post(host, data);
1575
1576 /*
1577 * The specification states that the block count register must
1578 * be updated, but it does not specify at what point in the
1579 * data flow. That makes the register entirely useless to read
1580 * back so we have to assume that nothing made it to the card
1581 * in the event of an error.
1582 */
1583 if (data->error)
1584 data->bytes_xfered = 0;
1585 else
1586 data->bytes_xfered = data->blksz * data->blocks;
1587
1588 /*
1589 * Need to send CMD12 if -
1590 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1591 * b) error in multiblock transfer
1592 */
1593 if (data->stop &&
1594 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1595 data->error)) {
1596 /*
1597 * 'cap_cmd_during_tfr' request must not use the command line
1598 * after mmc_command_done() has been called. It is upper layer's
1599 * responsibility to send the stop command if required.
1600 */
1601 if (data->mrq->cap_cmd_during_tfr) {
1602 __sdhci_finish_mrq(host, data->mrq);
1603 } else {
1604 /* Avoid triggering warning in sdhci_send_command() */
1605 host->cmd = NULL;
1606 if (!sdhci_send_command(host, data->stop)) {
1607 if (sw_data_timeout) {
1608 /*
1609 * This is anyway a sw data timeout, so
1610 * give up now.
1611 */
1612 data->stop->error = -EIO;
1613 __sdhci_finish_mrq(host, data->mrq);
1614 } else {
1615 WARN_ON(host->deferred_cmd);
1616 host->deferred_cmd = data->stop;
1617 }
1618 }
1619 }
1620 } else {
1621 __sdhci_finish_mrq(host, data->mrq);
1622 }
1623}
1624
1625static void sdhci_finish_data(struct sdhci_host *host)
1626{
1627 __sdhci_finish_data(host, false);
1628}
1629
1630static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1631{
1632 int flags;
1633 u32 mask;
1634 unsigned long timeout;
1635
1636 WARN_ON(host->cmd);
1637
1638 /* Initially, a command has no error */
1639 cmd->error = 0;
1640
1641 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1642 cmd->opcode == MMC_STOP_TRANSMISSION)
1643 cmd->flags |= MMC_RSP_BUSY;
1644
1645 mask = SDHCI_CMD_INHIBIT;
1646 if (sdhci_data_line_cmd(cmd))
1647 mask |= SDHCI_DATA_INHIBIT;
1648
1649 /* We shouldn't wait for data inihibit for stop commands, even
1650 though they might use busy signaling */
1651 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1652 mask &= ~SDHCI_DATA_INHIBIT;
1653
1654 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1655 return false;
1656
1657 host->cmd = cmd;
1658 host->data_timeout = 0;
1659 if (sdhci_data_line_cmd(cmd)) {
1660 WARN_ON(host->data_cmd);
1661 host->data_cmd = cmd;
1662 sdhci_set_timeout(host, cmd);
1663 }
1664
1665 if (cmd->data) {
1666 if (host->use_external_dma)
1667 sdhci_external_dma_prepare_data(host, cmd);
1668 else
1669 sdhci_prepare_data(host, cmd);
1670 }
1671
1672 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1673
1674 sdhci_set_transfer_mode(host, cmd);
1675
1676 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1677 WARN_ONCE(1, "Unsupported response type!\n");
1678 /*
1679 * This does not happen in practice because 136-bit response
1680 * commands never have busy waiting, so rather than complicate
1681 * the error path, just remove busy waiting and continue.
1682 */
1683 cmd->flags &= ~MMC_RSP_BUSY;
1684 }
1685
1686 if (!(cmd->flags & MMC_RSP_PRESENT))
1687 flags = SDHCI_CMD_RESP_NONE;
1688 else if (cmd->flags & MMC_RSP_136)
1689 flags = SDHCI_CMD_RESP_LONG;
1690 else if (cmd->flags & MMC_RSP_BUSY)
1691 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1692 else
1693 flags = SDHCI_CMD_RESP_SHORT;
1694
1695 if (cmd->flags & MMC_RSP_CRC)
1696 flags |= SDHCI_CMD_CRC;
1697 if (cmd->flags & MMC_RSP_OPCODE)
1698 flags |= SDHCI_CMD_INDEX;
1699
1700 /* CMD19 is special in that the Data Present Select should be set */
1701 if (cmd->data || mmc_op_tuning(cmd->opcode))
1702 flags |= SDHCI_CMD_DATA;
1703
1704 timeout = jiffies;
1705 if (host->data_timeout)
1706 timeout += nsecs_to_jiffies(host->data_timeout);
1707 else if (!cmd->data && cmd->busy_timeout > 9000)
1708 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1709 else
1710 timeout += 10 * HZ;
1711 sdhci_mod_timer(host, cmd->mrq, timeout);
1712
1713 if (host->use_external_dma)
1714 sdhci_external_dma_pre_transfer(host, cmd);
1715
1716 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1717
1718 return true;
1719}
1720
1721static bool sdhci_present_error(struct sdhci_host *host,
1722 struct mmc_command *cmd, bool present)
1723{
1724 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1725 cmd->error = -ENOMEDIUM;
1726 return true;
1727 }
1728
1729 return false;
1730}
1731
1732static bool sdhci_send_command_retry(struct sdhci_host *host,
1733 struct mmc_command *cmd,
1734 unsigned long flags)
1735 __releases(host->lock)
1736 __acquires(host->lock)
1737{
1738 struct mmc_command *deferred_cmd = host->deferred_cmd;
1739 int timeout = 10; /* Approx. 10 ms */
1740 bool present;
1741
1742 while (!sdhci_send_command(host, cmd)) {
1743 if (!timeout--) {
1744 pr_err("%s: Controller never released inhibit bit(s).\n",
1745 mmc_hostname(host->mmc));
1746 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1747 sdhci_dumpregs(host);
1748 cmd->error = -EIO;
1749 return false;
1750 }
1751
1752 spin_unlock_irqrestore(&host->lock, flags);
1753
1754 usleep_range(1000, 1250);
1755
1756 present = host->mmc->ops->get_cd(host->mmc);
1757
1758 spin_lock_irqsave(&host->lock, flags);
1759
1760 /* A deferred command might disappear, handle that */
1761 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1762 return true;
1763
1764 if (sdhci_present_error(host, cmd, present))
1765 return false;
1766 }
1767
1768 if (cmd == host->deferred_cmd)
1769 host->deferred_cmd = NULL;
1770
1771 return true;
1772}
1773
1774static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1775{
1776 int i, reg;
1777
1778 for (i = 0; i < 4; i++) {
1779 reg = SDHCI_RESPONSE + (3 - i) * 4;
1780 cmd->resp[i] = sdhci_readl(host, reg);
1781 }
1782
1783 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1784 return;
1785
1786 /* CRC is stripped so we need to do some shifting */
1787 for (i = 0; i < 4; i++) {
1788 cmd->resp[i] <<= 8;
1789 if (i != 3)
1790 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1791 }
1792}
1793
1794static void sdhci_finish_command(struct sdhci_host *host)
1795{
1796 struct mmc_command *cmd = host->cmd;
1797
1798 host->cmd = NULL;
1799
1800 if (cmd->flags & MMC_RSP_PRESENT) {
1801 if (cmd->flags & MMC_RSP_136) {
1802 sdhci_read_rsp_136(host, cmd);
1803 } else {
1804 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1805 }
1806 }
1807
1808 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1809 mmc_command_done(host->mmc, cmd->mrq);
1810
1811 /*
1812 * The host can send and interrupt when the busy state has
1813 * ended, allowing us to wait without wasting CPU cycles.
1814 * The busy signal uses DAT0 so this is similar to waiting
1815 * for data to complete.
1816 *
1817 * Note: The 1.0 specification is a bit ambiguous about this
1818 * feature so there might be some problems with older
1819 * controllers.
1820 */
1821 if (cmd->flags & MMC_RSP_BUSY) {
1822 if (cmd->data) {
1823 DBG("Cannot wait for busy signal when also doing a data transfer");
1824 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1825 cmd == host->data_cmd) {
1826 /* Command complete before busy is ended */
1827 return;
1828 }
1829 }
1830
1831 /* Finished CMD23, now send actual command. */
1832 if (cmd == cmd->mrq->sbc) {
1833 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1834 WARN_ON(host->deferred_cmd);
1835 host->deferred_cmd = cmd->mrq->cmd;
1836 }
1837 } else {
1838
1839 /* Processed actual command. */
1840 if (host->data && host->data_early)
1841 sdhci_finish_data(host);
1842
1843 if (!cmd->data)
1844 __sdhci_finish_mrq(host, cmd->mrq);
1845 }
1846}
1847
1848static u16 sdhci_get_preset_value(struct sdhci_host *host)
1849{
1850 u16 preset = 0;
1851
1852 switch (host->timing) {
1853 case MMC_TIMING_MMC_HS:
1854 case MMC_TIMING_SD_HS:
1855 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1856 break;
1857 case MMC_TIMING_UHS_SDR12:
1858 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1859 break;
1860 case MMC_TIMING_UHS_SDR25:
1861 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1862 break;
1863 case MMC_TIMING_UHS_SDR50:
1864 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1865 break;
1866 case MMC_TIMING_UHS_SDR104:
1867 case MMC_TIMING_MMC_HS200:
1868 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1869 break;
1870 case MMC_TIMING_UHS_DDR50:
1871 case MMC_TIMING_MMC_DDR52:
1872 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1873 break;
1874 case MMC_TIMING_MMC_HS400:
1875 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1876 break;
1877 default:
1878 pr_warn("%s: Invalid UHS-I mode selected\n",
1879 mmc_hostname(host->mmc));
1880 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1881 break;
1882 }
1883 return preset;
1884}
1885
1886u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1887 unsigned int *actual_clock)
1888{
1889 int div = 0; /* Initialized for compiler warning */
1890 int real_div = div, clk_mul = 1;
1891 u16 clk = 0;
1892 bool switch_base_clk = false;
1893
1894 if (host->version >= SDHCI_SPEC_300) {
1895 if (host->preset_enabled) {
1896 u16 pre_val;
1897
1898 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1899 pre_val = sdhci_get_preset_value(host);
1900 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1901 if (host->clk_mul &&
1902 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1903 clk = SDHCI_PROG_CLOCK_MODE;
1904 real_div = div + 1;
1905 clk_mul = host->clk_mul;
1906 } else {
1907 real_div = max_t(int, 1, div << 1);
1908 }
1909 goto clock_set;
1910 }
1911
1912 /*
1913 * Check if the Host Controller supports Programmable Clock
1914 * Mode.
1915 */
1916 if (host->clk_mul) {
1917 for (div = 1; div <= 1024; div++) {
1918 if ((host->max_clk * host->clk_mul / div)
1919 <= clock)
1920 break;
1921 }
1922 if ((host->max_clk * host->clk_mul / div) <= clock) {
1923 /*
1924 * Set Programmable Clock Mode in the Clock
1925 * Control register.
1926 */
1927 clk = SDHCI_PROG_CLOCK_MODE;
1928 real_div = div;
1929 clk_mul = host->clk_mul;
1930 div--;
1931 } else {
1932 /*
1933 * Divisor can be too small to reach clock
1934 * speed requirement. Then use the base clock.
1935 */
1936 switch_base_clk = true;
1937 }
1938 }
1939
1940 if (!host->clk_mul || switch_base_clk) {
1941 /* Version 3.00 divisors must be a multiple of 2. */
1942 if (host->max_clk <= clock)
1943 div = 1;
1944 else {
1945 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1946 div += 2) {
1947 if ((host->max_clk / div) <= clock)
1948 break;
1949 }
1950 }
1951 real_div = div;
1952 div >>= 1;
1953 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1954 && !div && host->max_clk <= 25000000)
1955 div = 1;
1956 }
1957 } else {
1958 /* Version 2.00 divisors must be a power of 2. */
1959 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1960 if ((host->max_clk / div) <= clock)
1961 break;
1962 }
1963 real_div = div;
1964 div >>= 1;
1965 }
1966
1967clock_set:
1968 if (real_div)
1969 *actual_clock = (host->max_clk * clk_mul) / real_div;
1970 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1971 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1972 << SDHCI_DIVIDER_HI_SHIFT;
1973
1974 return clk;
1975}
1976EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1977
1978void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1979{
1980 ktime_t timeout;
1981
1982 clk |= SDHCI_CLOCK_INT_EN;
1983 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1984
1985 /* Wait max 150 ms */
1986 timeout = ktime_add_ms(ktime_get(), 150);
1987 while (1) {
1988 bool timedout = ktime_after(ktime_get(), timeout);
1989
1990 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1991 if (clk & SDHCI_CLOCK_INT_STABLE)
1992 break;
1993 if (timedout) {
1994 pr_err("%s: Internal clock never stabilised.\n",
1995 mmc_hostname(host->mmc));
1996 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1997 sdhci_dumpregs(host);
1998 return;
1999 }
2000 udelay(10);
2001 }
2002
2003 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2004 clk |= SDHCI_CLOCK_PLL_EN;
2005 clk &= ~SDHCI_CLOCK_INT_STABLE;
2006 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2007
2008 /* Wait max 150 ms */
2009 timeout = ktime_add_ms(ktime_get(), 150);
2010 while (1) {
2011 bool timedout = ktime_after(ktime_get(), timeout);
2012
2013 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2014 if (clk & SDHCI_CLOCK_INT_STABLE)
2015 break;
2016 if (timedout) {
2017 pr_err("%s: PLL clock never stabilised.\n",
2018 mmc_hostname(host->mmc));
2019 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2020 sdhci_dumpregs(host);
2021 return;
2022 }
2023 udelay(10);
2024 }
2025 }
2026
2027 clk |= SDHCI_CLOCK_CARD_EN;
2028 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2029}
2030EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2031
2032void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2033{
2034 u16 clk;
2035
2036 host->mmc->actual_clock = 0;
2037
2038 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2039
2040 if (clock == 0)
2041 return;
2042
2043 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2044 sdhci_enable_clk(host, clk);
2045}
2046EXPORT_SYMBOL_GPL(sdhci_set_clock);
2047
2048static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2049 unsigned short vdd)
2050{
2051 struct mmc_host *mmc = host->mmc;
2052
2053 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2054
2055 if (mode != MMC_POWER_OFF)
2056 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2057 else
2058 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2059}
2060
2061void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2062 unsigned short vdd)
2063{
2064 u8 pwr = 0;
2065
2066 if (mode != MMC_POWER_OFF) {
2067 switch (1 << vdd) {
2068 case MMC_VDD_165_195:
2069 /*
2070 * Without a regulator, SDHCI does not support 2.0v
2071 * so we only get here if the driver deliberately
2072 * added the 2.0v range to ocr_avail. Map it to 1.8v
2073 * for the purpose of turning on the power.
2074 */
2075 case MMC_VDD_20_21:
2076 pwr = SDHCI_POWER_180;
2077 break;
2078 case MMC_VDD_29_30:
2079 case MMC_VDD_30_31:
2080 pwr = SDHCI_POWER_300;
2081 break;
2082 case MMC_VDD_32_33:
2083 case MMC_VDD_33_34:
2084 /*
2085 * 3.4 ~ 3.6V are valid only for those platforms where it's
2086 * known that the voltage range is supported by hardware.
2087 */
2088 case MMC_VDD_34_35:
2089 case MMC_VDD_35_36:
2090 pwr = SDHCI_POWER_330;
2091 break;
2092 default:
2093 WARN(1, "%s: Invalid vdd %#x\n",
2094 mmc_hostname(host->mmc), vdd);
2095 break;
2096 }
2097 }
2098
2099 if (host->pwr == pwr)
2100 return;
2101
2102 host->pwr = pwr;
2103
2104 if (pwr == 0) {
2105 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2106 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2107 sdhci_runtime_pm_bus_off(host);
2108 } else {
2109 /*
2110 * Spec says that we should clear the power reg before setting
2111 * a new value. Some controllers don't seem to like this though.
2112 */
2113 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2114 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2115
2116 /*
2117 * At least the Marvell CaFe chip gets confused if we set the
2118 * voltage and set turn on power at the same time, so set the
2119 * voltage first.
2120 */
2121 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2122 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2123
2124 pwr |= SDHCI_POWER_ON;
2125
2126 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2127
2128 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2129 sdhci_runtime_pm_bus_on(host);
2130
2131 /*
2132 * Some controllers need an extra 10ms delay of 10ms before
2133 * they can apply clock after applying power
2134 */
2135 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2136 mdelay(10);
2137 }
2138}
2139EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2140
2141void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2142 unsigned short vdd)
2143{
2144 if (IS_ERR(host->mmc->supply.vmmc))
2145 sdhci_set_power_noreg(host, mode, vdd);
2146 else
2147 sdhci_set_power_reg(host, mode, vdd);
2148}
2149EXPORT_SYMBOL_GPL(sdhci_set_power);
2150
2151/*
2152 * Some controllers need to configure a valid bus voltage on their power
2153 * register regardless of whether an external regulator is taking care of power
2154 * supply. This helper function takes care of it if set as the controller's
2155 * sdhci_ops.set_power callback.
2156 */
2157void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2158 unsigned char mode,
2159 unsigned short vdd)
2160{
2161 if (!IS_ERR(host->mmc->supply.vmmc)) {
2162 struct mmc_host *mmc = host->mmc;
2163
2164 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2165 }
2166 sdhci_set_power_noreg(host, mode, vdd);
2167}
2168EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2169
2170/*****************************************************************************\
2171 * *
2172 * MMC callbacks *
2173 * *
2174\*****************************************************************************/
2175
2176void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2177{
2178 struct sdhci_host *host = mmc_priv(mmc);
2179 struct mmc_command *cmd;
2180 unsigned long flags;
2181 bool present;
2182
2183 /* Firstly check card presence */
2184 present = mmc->ops->get_cd(mmc);
2185
2186 spin_lock_irqsave(&host->lock, flags);
2187
2188 sdhci_led_activate(host);
2189
2190 if (sdhci_present_error(host, mrq->cmd, present))
2191 goto out_finish;
2192
2193 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2194
2195 if (!sdhci_send_command_retry(host, cmd, flags))
2196 goto out_finish;
2197
2198 spin_unlock_irqrestore(&host->lock, flags);
2199
2200 return;
2201
2202out_finish:
2203 sdhci_finish_mrq(host, mrq);
2204 spin_unlock_irqrestore(&host->lock, flags);
2205}
2206EXPORT_SYMBOL_GPL(sdhci_request);
2207
2208int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2209{
2210 struct sdhci_host *host = mmc_priv(mmc);
2211 struct mmc_command *cmd;
2212 unsigned long flags;
2213 int ret = 0;
2214
2215 spin_lock_irqsave(&host->lock, flags);
2216
2217 if (sdhci_present_error(host, mrq->cmd, true)) {
2218 sdhci_finish_mrq(host, mrq);
2219 goto out_finish;
2220 }
2221
2222 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2223
2224 /*
2225 * The HSQ may send a command in interrupt context without polling
2226 * the busy signaling, which means we should return BUSY if controller
2227 * has not released inhibit bits to allow HSQ trying to send request
2228 * again in non-atomic context. So we should not finish this request
2229 * here.
2230 */
2231 if (!sdhci_send_command(host, cmd))
2232 ret = -EBUSY;
2233 else
2234 sdhci_led_activate(host);
2235
2236out_finish:
2237 spin_unlock_irqrestore(&host->lock, flags);
2238 return ret;
2239}
2240EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2241
2242void sdhci_set_bus_width(struct sdhci_host *host, int width)
2243{
2244 u8 ctrl;
2245
2246 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2247 if (width == MMC_BUS_WIDTH_8) {
2248 ctrl &= ~SDHCI_CTRL_4BITBUS;
2249 ctrl |= SDHCI_CTRL_8BITBUS;
2250 } else {
2251 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2252 ctrl &= ~SDHCI_CTRL_8BITBUS;
2253 if (width == MMC_BUS_WIDTH_4)
2254 ctrl |= SDHCI_CTRL_4BITBUS;
2255 else
2256 ctrl &= ~SDHCI_CTRL_4BITBUS;
2257 }
2258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2259}
2260EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2261
2262void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2263{
2264 u16 ctrl_2;
2265
2266 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2267 /* Select Bus Speed Mode for host */
2268 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2269 if ((timing == MMC_TIMING_MMC_HS200) ||
2270 (timing == MMC_TIMING_UHS_SDR104))
2271 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2272 else if (timing == MMC_TIMING_UHS_SDR12)
2273 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2274 else if (timing == MMC_TIMING_UHS_SDR25)
2275 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2276 else if (timing == MMC_TIMING_UHS_SDR50)
2277 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2278 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2279 (timing == MMC_TIMING_MMC_DDR52))
2280 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2281 else if (timing == MMC_TIMING_MMC_HS400)
2282 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2283 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2284}
2285EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2286
2287static bool sdhci_timing_has_preset(unsigned char timing)
2288{
2289 switch (timing) {
2290 case MMC_TIMING_UHS_SDR12:
2291 case MMC_TIMING_UHS_SDR25:
2292 case MMC_TIMING_UHS_SDR50:
2293 case MMC_TIMING_UHS_SDR104:
2294 case MMC_TIMING_UHS_DDR50:
2295 case MMC_TIMING_MMC_DDR52:
2296 return true;
2297 }
2298 return false;
2299}
2300
2301static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2302{
2303 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2304 sdhci_timing_has_preset(timing);
2305}
2306
2307static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2308{
2309 /*
2310 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
2311 * Frequency. Check if preset values need to be enabled, or the Driver
2312 * Strength needs updating. Note, clock changes are handled separately.
2313 */
2314 return !host->preset_enabled &&
2315 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2316}
2317
2318void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2319{
2320 struct sdhci_host *host = mmc_priv(mmc);
2321 bool reinit_uhs = host->reinit_uhs;
2322 bool turning_on_clk = false;
2323 u8 ctrl;
2324
2325 host->reinit_uhs = false;
2326
2327 if (ios->power_mode == MMC_POWER_UNDEFINED)
2328 return;
2329
2330 if (host->flags & SDHCI_DEVICE_DEAD) {
2331 if (!IS_ERR(mmc->supply.vmmc) &&
2332 ios->power_mode == MMC_POWER_OFF)
2333 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2334 return;
2335 }
2336
2337 /*
2338 * Reset the chip on each power off.
2339 * Should clear out any weird states.
2340 */
2341 if (ios->power_mode == MMC_POWER_OFF) {
2342 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2343 sdhci_reinit(host);
2344 }
2345
2346 if (host->version >= SDHCI_SPEC_300 &&
2347 (ios->power_mode == MMC_POWER_UP) &&
2348 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2349 sdhci_enable_preset_value(host, false);
2350
2351 if (!ios->clock || ios->clock != host->clock) {
2352 turning_on_clk = ios->clock && !host->clock;
2353
2354 host->ops->set_clock(host, ios->clock);
2355 host->clock = ios->clock;
2356
2357 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2358 host->clock) {
2359 host->timeout_clk = mmc->actual_clock ?
2360 mmc->actual_clock / 1000 :
2361 host->clock / 1000;
2362 mmc->max_busy_timeout =
2363 host->ops->get_max_timeout_count ?
2364 host->ops->get_max_timeout_count(host) :
2365 1 << 27;
2366 mmc->max_busy_timeout /= host->timeout_clk;
2367 }
2368 }
2369
2370 if (host->ops->set_power)
2371 host->ops->set_power(host, ios->power_mode, ios->vdd);
2372 else
2373 sdhci_set_power(host, ios->power_mode, ios->vdd);
2374
2375 if (host->ops->platform_send_init_74_clocks)
2376 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2377
2378 host->ops->set_bus_width(host, ios->bus_width);
2379
2380 /*
2381 * Special case to avoid multiple clock changes during voltage
2382 * switching.
2383 */
2384 if (!reinit_uhs &&
2385 turning_on_clk &&
2386 host->timing == ios->timing &&
2387 host->version >= SDHCI_SPEC_300 &&
2388 !sdhci_presetable_values_change(host, ios))
2389 return;
2390
2391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2392
2393 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2394 if (ios->timing == MMC_TIMING_SD_HS ||
2395 ios->timing == MMC_TIMING_MMC_HS ||
2396 ios->timing == MMC_TIMING_MMC_HS400 ||
2397 ios->timing == MMC_TIMING_MMC_HS200 ||
2398 ios->timing == MMC_TIMING_MMC_DDR52 ||
2399 ios->timing == MMC_TIMING_UHS_SDR50 ||
2400 ios->timing == MMC_TIMING_UHS_SDR104 ||
2401 ios->timing == MMC_TIMING_UHS_DDR50 ||
2402 ios->timing == MMC_TIMING_UHS_SDR25)
2403 ctrl |= SDHCI_CTRL_HISPD;
2404 else
2405 ctrl &= ~SDHCI_CTRL_HISPD;
2406 }
2407
2408 if (host->version >= SDHCI_SPEC_300) {
2409 u16 clk, ctrl_2;
2410
2411 /*
2412 * According to SDHCI Spec v3.00, if the Preset Value
2413 * Enable in the Host Control 2 register is set, we
2414 * need to reset SD Clock Enable before changing High
2415 * Speed Enable to avoid generating clock glitches.
2416 */
2417 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2418 if (clk & SDHCI_CLOCK_CARD_EN) {
2419 clk &= ~SDHCI_CLOCK_CARD_EN;
2420 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2421 }
2422
2423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2424
2425 if (!host->preset_enabled) {
2426 /*
2427 * We only need to set Driver Strength if the
2428 * preset value enable is not set.
2429 */
2430 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2431 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2432 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2433 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2434 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2435 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2436 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2437 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2438 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2439 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2440 else {
2441 pr_warn("%s: invalid driver type, default to driver type B\n",
2442 mmc_hostname(mmc));
2443 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2444 }
2445
2446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2447 host->drv_type = ios->drv_type;
2448 }
2449
2450 host->ops->set_uhs_signaling(host, ios->timing);
2451 host->timing = ios->timing;
2452
2453 if (sdhci_preset_needed(host, ios->timing)) {
2454 u16 preset;
2455
2456 sdhci_enable_preset_value(host, true);
2457 preset = sdhci_get_preset_value(host);
2458 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2459 preset);
2460 host->drv_type = ios->drv_type;
2461 }
2462
2463 /* Re-enable SD Clock */
2464 host->ops->set_clock(host, host->clock);
2465 } else
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2467}
2468EXPORT_SYMBOL_GPL(sdhci_set_ios);
2469
2470static int sdhci_get_cd(struct mmc_host *mmc)
2471{
2472 struct sdhci_host *host = mmc_priv(mmc);
2473 int gpio_cd = mmc_gpio_get_cd(mmc);
2474
2475 if (host->flags & SDHCI_DEVICE_DEAD)
2476 return 0;
2477
2478 /* If nonremovable, assume that the card is always present. */
2479 if (!mmc_card_is_removable(mmc))
2480 return 1;
2481
2482 /*
2483 * Try slot gpio detect, if defined it take precedence
2484 * over build in controller functionality
2485 */
2486 if (gpio_cd >= 0)
2487 return !!gpio_cd;
2488
2489 /* If polling, assume that the card is always present. */
2490 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2491 return 1;
2492
2493 /* Host native card detect */
2494 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2495}
2496
2497int sdhci_get_cd_nogpio(struct mmc_host *mmc)
2498{
2499 struct sdhci_host *host = mmc_priv(mmc);
2500 unsigned long flags;
2501 int ret = 0;
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->flags & SDHCI_DEVICE_DEAD)
2506 goto out;
2507
2508 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2509out:
2510 spin_unlock_irqrestore(&host->lock, flags);
2511
2512 return ret;
2513}
2514EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
2515
2516static int sdhci_check_ro(struct sdhci_host *host)
2517{
2518 unsigned long flags;
2519 int is_readonly;
2520
2521 spin_lock_irqsave(&host->lock, flags);
2522
2523 if (host->flags & SDHCI_DEVICE_DEAD)
2524 is_readonly = 0;
2525 else if (host->ops->get_ro)
2526 is_readonly = host->ops->get_ro(host);
2527 else if (mmc_can_gpio_ro(host->mmc))
2528 is_readonly = mmc_gpio_get_ro(host->mmc);
2529 else
2530 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2531 & SDHCI_WRITE_PROTECT);
2532
2533 spin_unlock_irqrestore(&host->lock, flags);
2534
2535 /* This quirk needs to be replaced by a callback-function later */
2536 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2537 !is_readonly : is_readonly;
2538}
2539
2540#define SAMPLE_COUNT 5
2541
2542static int sdhci_get_ro(struct mmc_host *mmc)
2543{
2544 struct sdhci_host *host = mmc_priv(mmc);
2545 int i, ro_count;
2546
2547 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2548 return sdhci_check_ro(host);
2549
2550 ro_count = 0;
2551 for (i = 0; i < SAMPLE_COUNT; i++) {
2552 if (sdhci_check_ro(host)) {
2553 if (++ro_count > SAMPLE_COUNT / 2)
2554 return 1;
2555 }
2556 msleep(30);
2557 }
2558 return 0;
2559}
2560
2561static void sdhci_hw_reset(struct mmc_host *mmc)
2562{
2563 struct sdhci_host *host = mmc_priv(mmc);
2564
2565 if (host->ops && host->ops->hw_reset)
2566 host->ops->hw_reset(host);
2567}
2568
2569static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2570{
2571 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2572 if (enable)
2573 host->ier |= SDHCI_INT_CARD_INT;
2574 else
2575 host->ier &= ~SDHCI_INT_CARD_INT;
2576
2577 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2578 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2579 }
2580}
2581
2582void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2583{
2584 struct sdhci_host *host = mmc_priv(mmc);
2585 unsigned long flags;
2586
2587 if (enable)
2588 pm_runtime_get_noresume(mmc_dev(mmc));
2589
2590 spin_lock_irqsave(&host->lock, flags);
2591 sdhci_enable_sdio_irq_nolock(host, enable);
2592 spin_unlock_irqrestore(&host->lock, flags);
2593
2594 if (!enable)
2595 pm_runtime_put_noidle(mmc_dev(mmc));
2596}
2597EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2598
2599static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2600{
2601 struct sdhci_host *host = mmc_priv(mmc);
2602 unsigned long flags;
2603
2604 spin_lock_irqsave(&host->lock, flags);
2605 sdhci_enable_sdio_irq_nolock(host, true);
2606 spin_unlock_irqrestore(&host->lock, flags);
2607}
2608
2609int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2610 struct mmc_ios *ios)
2611{
2612 struct sdhci_host *host = mmc_priv(mmc);
2613 u16 ctrl;
2614 int ret;
2615
2616 /*
2617 * Signal Voltage Switching is only applicable for Host Controllers
2618 * v3.00 and above.
2619 */
2620 if (host->version < SDHCI_SPEC_300)
2621 return 0;
2622
2623 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2624
2625 switch (ios->signal_voltage) {
2626 case MMC_SIGNAL_VOLTAGE_330:
2627 if (!(host->flags & SDHCI_SIGNALING_330))
2628 return -EINVAL;
2629 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2630 ctrl &= ~SDHCI_CTRL_VDD_180;
2631 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2632
2633 if (!IS_ERR(mmc->supply.vqmmc)) {
2634 ret = mmc_regulator_set_vqmmc(mmc, ios);
2635 if (ret < 0) {
2636 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2637 mmc_hostname(mmc));
2638 return -EIO;
2639 }
2640 }
2641 /* Wait for 5ms */
2642 usleep_range(5000, 5500);
2643
2644 /* 3.3V regulator output should be stable within 5 ms */
2645 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2646 if (!(ctrl & SDHCI_CTRL_VDD_180))
2647 return 0;
2648
2649 pr_warn("%s: 3.3V regulator output did not become stable\n",
2650 mmc_hostname(mmc));
2651
2652 return -EAGAIN;
2653 case MMC_SIGNAL_VOLTAGE_180:
2654 if (!(host->flags & SDHCI_SIGNALING_180))
2655 return -EINVAL;
2656 if (!IS_ERR(mmc->supply.vqmmc)) {
2657 ret = mmc_regulator_set_vqmmc(mmc, ios);
2658 if (ret < 0) {
2659 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2660 mmc_hostname(mmc));
2661 return -EIO;
2662 }
2663 }
2664
2665 /*
2666 * Enable 1.8V Signal Enable in the Host Control2
2667 * register
2668 */
2669 ctrl |= SDHCI_CTRL_VDD_180;
2670 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2671
2672 /* Some controller need to do more when switching */
2673 if (host->ops->voltage_switch)
2674 host->ops->voltage_switch(host);
2675
2676 /* 1.8V regulator output should be stable within 5 ms */
2677 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2678 if (ctrl & SDHCI_CTRL_VDD_180)
2679 return 0;
2680
2681 pr_warn("%s: 1.8V regulator output did not become stable\n",
2682 mmc_hostname(mmc));
2683
2684 return -EAGAIN;
2685 case MMC_SIGNAL_VOLTAGE_120:
2686 if (!(host->flags & SDHCI_SIGNALING_120))
2687 return -EINVAL;
2688 if (!IS_ERR(mmc->supply.vqmmc)) {
2689 ret = mmc_regulator_set_vqmmc(mmc, ios);
2690 if (ret < 0) {
2691 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2692 mmc_hostname(mmc));
2693 return -EIO;
2694 }
2695 }
2696 return 0;
2697 default:
2698 /* No signal voltage switch required */
2699 return 0;
2700 }
2701}
2702EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2703
2704static int sdhci_card_busy(struct mmc_host *mmc)
2705{
2706 struct sdhci_host *host = mmc_priv(mmc);
2707 u32 present_state;
2708
2709 /* Check whether DAT[0] is 0 */
2710 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2711
2712 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2713}
2714
2715static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2716{
2717 struct sdhci_host *host = mmc_priv(mmc);
2718 unsigned long flags;
2719
2720 spin_lock_irqsave(&host->lock, flags);
2721 host->flags |= SDHCI_HS400_TUNING;
2722 spin_unlock_irqrestore(&host->lock, flags);
2723
2724 return 0;
2725}
2726
2727void sdhci_start_tuning(struct sdhci_host *host)
2728{
2729 u16 ctrl;
2730
2731 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2732 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2733 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2734 ctrl |= SDHCI_CTRL_TUNED_CLK;
2735 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2736
2737 /*
2738 * As per the Host Controller spec v3.00, tuning command
2739 * generates Buffer Read Ready interrupt, so enable that.
2740 *
2741 * Note: The spec clearly says that when tuning sequence
2742 * is being performed, the controller does not generate
2743 * interrupts other than Buffer Read Ready interrupt. But
2744 * to make sure we don't hit a controller bug, we _only_
2745 * enable Buffer Read Ready interrupt here.
2746 */
2747 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2748 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2749}
2750EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2751
2752void sdhci_end_tuning(struct sdhci_host *host)
2753{
2754 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2755 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2756}
2757EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2758
2759void sdhci_reset_tuning(struct sdhci_host *host)
2760{
2761 u16 ctrl;
2762
2763 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2764 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2765 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2767}
2768EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2769
2770void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2771{
2772 sdhci_reset_tuning(host);
2773
2774 sdhci_reset_for(host, TUNING_ABORT);
2775
2776 sdhci_end_tuning(host);
2777
2778 mmc_send_abort_tuning(host->mmc, opcode);
2779}
2780EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2781
2782/*
2783 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2784 * tuning command does not have a data payload (or rather the hardware does it
2785 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2786 * interrupt setup is different to other commands and there is no timeout
2787 * interrupt so special handling is needed.
2788 */
2789void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2790{
2791 struct mmc_host *mmc = host->mmc;
2792 struct mmc_command cmd = {};
2793 struct mmc_request mrq = {};
2794 unsigned long flags;
2795 u32 b = host->sdma_boundary;
2796
2797 spin_lock_irqsave(&host->lock, flags);
2798
2799 cmd.opcode = opcode;
2800 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2801 cmd.mrq = &mrq;
2802
2803 mrq.cmd = &cmd;
2804 /*
2805 * In response to CMD19, the card sends 64 bytes of tuning
2806 * block to the Host Controller. So we set the block size
2807 * to 64 here.
2808 */
2809 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2810 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2811 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2812 else
2813 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2814
2815 /*
2816 * The tuning block is sent by the card to the host controller.
2817 * So we set the TRNS_READ bit in the Transfer Mode register.
2818 * This also takes care of setting DMA Enable and Multi Block
2819 * Select in the same register to 0.
2820 */
2821 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2822
2823 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2824 spin_unlock_irqrestore(&host->lock, flags);
2825 host->tuning_done = 0;
2826 return;
2827 }
2828
2829 host->cmd = NULL;
2830
2831 sdhci_del_timer(host, &mrq);
2832
2833 host->tuning_done = 0;
2834
2835 spin_unlock_irqrestore(&host->lock, flags);
2836
2837 /* Wait for Buffer Read Ready interrupt */
2838 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2839 msecs_to_jiffies(50));
2840
2841}
2842EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2843
2844int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2845{
2846 int i;
2847
2848 /*
2849 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2850 * of loops reaches tuning loop count.
2851 */
2852 for (i = 0; i < host->tuning_loop_count; i++) {
2853 u16 ctrl;
2854
2855 sdhci_send_tuning(host, opcode);
2856
2857 if (!host->tuning_done) {
2858 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2859 mmc_hostname(host->mmc));
2860 sdhci_abort_tuning(host, opcode);
2861 return -ETIMEDOUT;
2862 }
2863
2864 /* Spec does not require a delay between tuning cycles */
2865 if (host->tuning_delay > 0)
2866 mdelay(host->tuning_delay);
2867
2868 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2869 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2870 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2871 return 0; /* Success! */
2872 break;
2873 }
2874
2875 }
2876
2877 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2878 mmc_hostname(host->mmc));
2879 sdhci_reset_tuning(host);
2880 return -EAGAIN;
2881}
2882EXPORT_SYMBOL_GPL(__sdhci_execute_tuning);
2883
2884int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2885{
2886 struct sdhci_host *host = mmc_priv(mmc);
2887 int err = 0;
2888 unsigned int tuning_count = 0;
2889 bool hs400_tuning;
2890
2891 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2892
2893 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2894 tuning_count = host->tuning_count;
2895
2896 /*
2897 * The Host Controller needs tuning in case of SDR104 and DDR50
2898 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2899 * the Capabilities register.
2900 * If the Host Controller supports the HS200 mode then the
2901 * tuning function has to be executed.
2902 */
2903 switch (host->timing) {
2904 /* HS400 tuning is done in HS200 mode */
2905 case MMC_TIMING_MMC_HS400:
2906 err = -EINVAL;
2907 goto out;
2908
2909 case MMC_TIMING_MMC_HS200:
2910 /*
2911 * Periodic re-tuning for HS400 is not expected to be needed, so
2912 * disable it here.
2913 */
2914 if (hs400_tuning)
2915 tuning_count = 0;
2916 break;
2917
2918 case MMC_TIMING_UHS_SDR104:
2919 case MMC_TIMING_UHS_DDR50:
2920 break;
2921
2922 case MMC_TIMING_UHS_SDR50:
2923 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2924 break;
2925 fallthrough;
2926
2927 default:
2928 goto out;
2929 }
2930
2931 if (host->ops->platform_execute_tuning) {
2932 err = host->ops->platform_execute_tuning(host, opcode);
2933 goto out;
2934 }
2935
2936 mmc->retune_period = tuning_count;
2937
2938 if (host->tuning_delay < 0)
2939 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2940
2941 sdhci_start_tuning(host);
2942
2943 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2944
2945 sdhci_end_tuning(host);
2946out:
2947 host->flags &= ~SDHCI_HS400_TUNING;
2948
2949 return err;
2950}
2951EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2952
2953static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2954{
2955 /* Host Controller v3.00 defines preset value registers */
2956 if (host->version < SDHCI_SPEC_300)
2957 return;
2958
2959 /*
2960 * We only enable or disable Preset Value if they are not already
2961 * enabled or disabled respectively. Otherwise, we bail out.
2962 */
2963 if (host->preset_enabled != enable) {
2964 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2965
2966 if (enable)
2967 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2968 else
2969 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2970
2971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2972
2973 if (enable)
2974 host->flags |= SDHCI_PV_ENABLED;
2975 else
2976 host->flags &= ~SDHCI_PV_ENABLED;
2977
2978 host->preset_enabled = enable;
2979 }
2980}
2981
2982static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2983 int err)
2984{
2985 struct mmc_data *data = mrq->data;
2986
2987 if (data->host_cookie != COOKIE_UNMAPPED)
2988 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
2989 mmc_get_dma_dir(data));
2990
2991 data->host_cookie = COOKIE_UNMAPPED;
2992}
2993
2994static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2995{
2996 struct sdhci_host *host = mmc_priv(mmc);
2997
2998 mrq->data->host_cookie = COOKIE_UNMAPPED;
2999
3000 /*
3001 * No pre-mapping in the pre hook if we're using the bounce buffer,
3002 * for that we would need two bounce buffers since one buffer is
3003 * in flight when this is getting called.
3004 */
3005 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
3006 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
3007}
3008
3009static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3010{
3011 if (host->data_cmd) {
3012 host->data_cmd->error = err;
3013 sdhci_finish_mrq(host, host->data_cmd->mrq);
3014 }
3015
3016 if (host->cmd) {
3017 host->cmd->error = err;
3018 sdhci_finish_mrq(host, host->cmd->mrq);
3019 }
3020}
3021
3022static void sdhci_card_event(struct mmc_host *mmc)
3023{
3024 struct sdhci_host *host = mmc_priv(mmc);
3025 unsigned long flags;
3026 int present;
3027
3028 /* First check if client has provided their own card event */
3029 if (host->ops->card_event)
3030 host->ops->card_event(host);
3031
3032 present = mmc->ops->get_cd(mmc);
3033
3034 spin_lock_irqsave(&host->lock, flags);
3035
3036 /* Check sdhci_has_requests() first in case we are runtime suspended */
3037 if (sdhci_has_requests(host) && !present) {
3038 pr_err("%s: Card removed during transfer!\n",
3039 mmc_hostname(mmc));
3040 pr_err("%s: Resetting controller.\n",
3041 mmc_hostname(mmc));
3042
3043 sdhci_reset_for(host, CARD_REMOVED);
3044
3045 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3046 }
3047
3048 spin_unlock_irqrestore(&host->lock, flags);
3049}
3050
3051static const struct mmc_host_ops sdhci_ops = {
3052 .request = sdhci_request,
3053 .post_req = sdhci_post_req,
3054 .pre_req = sdhci_pre_req,
3055 .set_ios = sdhci_set_ios,
3056 .get_cd = sdhci_get_cd,
3057 .get_ro = sdhci_get_ro,
3058 .card_hw_reset = sdhci_hw_reset,
3059 .enable_sdio_irq = sdhci_enable_sdio_irq,
3060 .ack_sdio_irq = sdhci_ack_sdio_irq,
3061 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
3062 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
3063 .execute_tuning = sdhci_execute_tuning,
3064 .card_event = sdhci_card_event,
3065 .card_busy = sdhci_card_busy,
3066};
3067
3068/*****************************************************************************\
3069 * *
3070 * Request done *
3071 * *
3072\*****************************************************************************/
3073
3074static bool sdhci_request_done(struct sdhci_host *host)
3075{
3076 unsigned long flags;
3077 struct mmc_request *mrq;
3078 int i;
3079
3080 spin_lock_irqsave(&host->lock, flags);
3081
3082 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3083 mrq = host->mrqs_done[i];
3084 if (mrq)
3085 break;
3086 }
3087
3088 if (!mrq) {
3089 spin_unlock_irqrestore(&host->lock, flags);
3090 return true;
3091 }
3092
3093 /*
3094 * The controller needs a reset of internal state machines
3095 * upon error conditions.
3096 */
3097 if (sdhci_needs_reset(host, mrq)) {
3098 /*
3099 * Do not finish until command and data lines are available for
3100 * reset. Note there can only be one other mrq, so it cannot
3101 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3102 * would both be null.
3103 */
3104 if (host->cmd || host->data_cmd) {
3105 spin_unlock_irqrestore(&host->lock, flags);
3106 return true;
3107 }
3108
3109 /* Some controllers need this kick or reset won't work here */
3110 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3111 /* This is to force an update */
3112 host->ops->set_clock(host, host->clock);
3113
3114 sdhci_reset_for(host, REQUEST_ERROR);
3115
3116 host->pending_reset = false;
3117 }
3118
3119 /*
3120 * Always unmap the data buffers if they were mapped by
3121 * sdhci_prepare_data() whenever we finish with a request.
3122 * This avoids leaking DMA mappings on error.
3123 */
3124 if (host->flags & SDHCI_REQ_USE_DMA) {
3125 struct mmc_data *data = mrq->data;
3126
3127 if (host->use_external_dma && data &&
3128 (mrq->cmd->error || data->error)) {
3129 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3130
3131 host->mrqs_done[i] = NULL;
3132 spin_unlock_irqrestore(&host->lock, flags);
3133 dmaengine_terminate_sync(chan);
3134 spin_lock_irqsave(&host->lock, flags);
3135 sdhci_set_mrq_done(host, mrq);
3136 }
3137
3138 if (data && data->host_cookie == COOKIE_MAPPED) {
3139 if (host->bounce_buffer) {
3140 /*
3141 * On reads, copy the bounced data into the
3142 * sglist
3143 */
3144 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3145 unsigned int length = data->bytes_xfered;
3146
3147 if (length > host->bounce_buffer_size) {
3148 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3149 mmc_hostname(host->mmc),
3150 host->bounce_buffer_size,
3151 data->bytes_xfered);
3152 /* Cap it down and continue */
3153 length = host->bounce_buffer_size;
3154 }
3155 dma_sync_single_for_cpu(
3156 mmc_dev(host->mmc),
3157 host->bounce_addr,
3158 host->bounce_buffer_size,
3159 DMA_FROM_DEVICE);
3160 sg_copy_from_buffer(data->sg,
3161 data->sg_len,
3162 host->bounce_buffer,
3163 length);
3164 } else {
3165 /* No copying, just switch ownership */
3166 dma_sync_single_for_cpu(
3167 mmc_dev(host->mmc),
3168 host->bounce_addr,
3169 host->bounce_buffer_size,
3170 mmc_get_dma_dir(data));
3171 }
3172 } else {
3173 /* Unmap the raw data */
3174 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3175 data->sg_len,
3176 mmc_get_dma_dir(data));
3177 }
3178 data->host_cookie = COOKIE_UNMAPPED;
3179 }
3180 }
3181
3182 host->mrqs_done[i] = NULL;
3183
3184 spin_unlock_irqrestore(&host->lock, flags);
3185
3186 if (host->ops->request_done)
3187 host->ops->request_done(host, mrq);
3188 else
3189 mmc_request_done(host->mmc, mrq);
3190
3191 return false;
3192}
3193
3194static void sdhci_complete_work(struct work_struct *work)
3195{
3196 struct sdhci_host *host = container_of(work, struct sdhci_host,
3197 complete_work);
3198
3199 while (!sdhci_request_done(host))
3200 ;
3201}
3202
3203static void sdhci_timeout_timer(struct timer_list *t)
3204{
3205 struct sdhci_host *host;
3206 unsigned long flags;
3207
3208 host = from_timer(host, t, timer);
3209
3210 spin_lock_irqsave(&host->lock, flags);
3211
3212 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3213 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3214 mmc_hostname(host->mmc));
3215 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3216 sdhci_dumpregs(host);
3217
3218 host->cmd->error = -ETIMEDOUT;
3219 sdhci_finish_mrq(host, host->cmd->mrq);
3220 }
3221
3222 spin_unlock_irqrestore(&host->lock, flags);
3223}
3224
3225static void sdhci_timeout_data_timer(struct timer_list *t)
3226{
3227 struct sdhci_host *host;
3228 unsigned long flags;
3229
3230 host = from_timer(host, t, data_timer);
3231
3232 spin_lock_irqsave(&host->lock, flags);
3233
3234 if (host->data || host->data_cmd ||
3235 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3236 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3237 mmc_hostname(host->mmc));
3238 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3239 sdhci_dumpregs(host);
3240
3241 if (host->data) {
3242 host->data->error = -ETIMEDOUT;
3243 __sdhci_finish_data(host, true);
3244 queue_work(host->complete_wq, &host->complete_work);
3245 } else if (host->data_cmd) {
3246 host->data_cmd->error = -ETIMEDOUT;
3247 sdhci_finish_mrq(host, host->data_cmd->mrq);
3248 } else {
3249 host->cmd->error = -ETIMEDOUT;
3250 sdhci_finish_mrq(host, host->cmd->mrq);
3251 }
3252 }
3253
3254 spin_unlock_irqrestore(&host->lock, flags);
3255}
3256
3257/*****************************************************************************\
3258 * *
3259 * Interrupt handling *
3260 * *
3261\*****************************************************************************/
3262
3263static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3264{
3265 /* Handle auto-CMD12 error */
3266 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3267 struct mmc_request *mrq = host->data_cmd->mrq;
3268 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3269 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3270 SDHCI_INT_DATA_TIMEOUT :
3271 SDHCI_INT_DATA_CRC;
3272
3273 /* Treat auto-CMD12 error the same as data error */
3274 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3275 *intmask_p |= data_err_bit;
3276 return;
3277 }
3278 }
3279
3280 if (!host->cmd) {
3281 /*
3282 * SDHCI recovers from errors by resetting the cmd and data
3283 * circuits. Until that is done, there very well might be more
3284 * interrupts, so ignore them in that case.
3285 */
3286 if (host->pending_reset)
3287 return;
3288 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3289 mmc_hostname(host->mmc), (unsigned)intmask);
3290 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3291 sdhci_dumpregs(host);
3292 return;
3293 }
3294
3295 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3296 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3297 if (intmask & SDHCI_INT_TIMEOUT) {
3298 host->cmd->error = -ETIMEDOUT;
3299 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3300 } else {
3301 host->cmd->error = -EILSEQ;
3302 if (!mmc_op_tuning(host->cmd->opcode))
3303 sdhci_err_stats_inc(host, CMD_CRC);
3304 }
3305 /* Treat data command CRC error the same as data CRC error */
3306 if (host->cmd->data &&
3307 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3308 SDHCI_INT_CRC) {
3309 host->cmd = NULL;
3310 *intmask_p |= SDHCI_INT_DATA_CRC;
3311 return;
3312 }
3313
3314 __sdhci_finish_mrq(host, host->cmd->mrq);
3315 return;
3316 }
3317
3318 /* Handle auto-CMD23 error */
3319 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3320 struct mmc_request *mrq = host->cmd->mrq;
3321 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3322 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3323 -ETIMEDOUT :
3324 -EILSEQ;
3325
3326 sdhci_err_stats_inc(host, AUTO_CMD);
3327
3328 if (sdhci_auto_cmd23(host, mrq)) {
3329 mrq->sbc->error = err;
3330 __sdhci_finish_mrq(host, mrq);
3331 return;
3332 }
3333 }
3334
3335 if (intmask & SDHCI_INT_RESPONSE)
3336 sdhci_finish_command(host);
3337}
3338
3339static void sdhci_adma_show_error(struct sdhci_host *host)
3340{
3341 void *desc = host->adma_table;
3342 dma_addr_t dma = host->adma_addr;
3343
3344 sdhci_dumpregs(host);
3345
3346 while (true) {
3347 struct sdhci_adma2_64_desc *dma_desc = desc;
3348
3349 if (host->flags & SDHCI_USE_64_BIT_DMA)
3350 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3351 (unsigned long long)dma,
3352 le32_to_cpu(dma_desc->addr_hi),
3353 le32_to_cpu(dma_desc->addr_lo),
3354 le16_to_cpu(dma_desc->len),
3355 le16_to_cpu(dma_desc->cmd));
3356 else
3357 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3358 (unsigned long long)dma,
3359 le32_to_cpu(dma_desc->addr_lo),
3360 le16_to_cpu(dma_desc->len),
3361 le16_to_cpu(dma_desc->cmd));
3362
3363 desc += host->desc_sz;
3364 dma += host->desc_sz;
3365
3366 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3367 break;
3368 }
3369}
3370
3371static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3372{
3373 /*
3374 * CMD19 generates _only_ Buffer Read Ready interrupt if
3375 * use sdhci_send_tuning.
3376 * Need to exclude this case: PIO mode and use mmc_send_tuning,
3377 * If not, sdhci_transfer_pio will never be called, make the
3378 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3379 */
3380 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3381 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
3382 host->tuning_done = 1;
3383 wake_up(&host->buf_ready_int);
3384 return;
3385 }
3386 }
3387
3388 if (!host->data) {
3389 struct mmc_command *data_cmd = host->data_cmd;
3390
3391 /*
3392 * The "data complete" interrupt is also used to
3393 * indicate that a busy state has ended. See comment
3394 * above in sdhci_cmd_irq().
3395 */
3396 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3397 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3398 host->data_cmd = NULL;
3399 data_cmd->error = -ETIMEDOUT;
3400 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3401 __sdhci_finish_mrq(host, data_cmd->mrq);
3402 return;
3403 }
3404 if (intmask & SDHCI_INT_DATA_END) {
3405 host->data_cmd = NULL;
3406 /*
3407 * Some cards handle busy-end interrupt
3408 * before the command completed, so make
3409 * sure we do things in the proper order.
3410 */
3411 if (host->cmd == data_cmd)
3412 return;
3413
3414 __sdhci_finish_mrq(host, data_cmd->mrq);
3415 return;
3416 }
3417 }
3418
3419 /*
3420 * SDHCI recovers from errors by resetting the cmd and data
3421 * circuits. Until that is done, there very well might be more
3422 * interrupts, so ignore them in that case.
3423 */
3424 if (host->pending_reset)
3425 return;
3426
3427 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3428 mmc_hostname(host->mmc), (unsigned)intmask);
3429 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3430 sdhci_dumpregs(host);
3431
3432 return;
3433 }
3434
3435 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3436 host->data->error = -ETIMEDOUT;
3437 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3438 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3439 host->data->error = -EILSEQ;
3440 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3441 sdhci_err_stats_inc(host, DAT_CRC);
3442 } else if ((intmask & SDHCI_INT_DATA_CRC) &&
3443 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3444 != MMC_BUS_TEST_R) {
3445 host->data->error = -EILSEQ;
3446 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3447 sdhci_err_stats_inc(host, DAT_CRC);
3448 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3449 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3450 intmask);
3451 sdhci_adma_show_error(host);
3452 sdhci_err_stats_inc(host, ADMA);
3453 host->data->error = -EIO;
3454 if (host->ops->adma_workaround)
3455 host->ops->adma_workaround(host, intmask);
3456 }
3457
3458 if (host->data->error)
3459 sdhci_finish_data(host);
3460 else {
3461 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3462 sdhci_transfer_pio(host);
3463
3464 /*
3465 * We currently don't do anything fancy with DMA
3466 * boundaries, but as we can't disable the feature
3467 * we need to at least restart the transfer.
3468 *
3469 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3470 * should return a valid address to continue from, but as
3471 * some controllers are faulty, don't trust them.
3472 */
3473 if (intmask & SDHCI_INT_DMA_END) {
3474 dma_addr_t dmastart, dmanow;
3475
3476 dmastart = sdhci_sdma_address(host);
3477 dmanow = dmastart + host->data->bytes_xfered;
3478 /*
3479 * Force update to the next DMA block boundary.
3480 */
3481 dmanow = (dmanow &
3482 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3483 SDHCI_DEFAULT_BOUNDARY_SIZE;
3484 host->data->bytes_xfered = dmanow - dmastart;
3485 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3486 &dmastart, host->data->bytes_xfered, &dmanow);
3487 sdhci_set_sdma_addr(host, dmanow);
3488 }
3489
3490 if (intmask & SDHCI_INT_DATA_END) {
3491 if (host->cmd == host->data_cmd) {
3492 /*
3493 * Data managed to finish before the
3494 * command completed. Make sure we do
3495 * things in the proper order.
3496 */
3497 host->data_early = 1;
3498 } else {
3499 sdhci_finish_data(host);
3500 }
3501 }
3502 }
3503}
3504
3505static inline bool sdhci_defer_done(struct sdhci_host *host,
3506 struct mmc_request *mrq)
3507{
3508 struct mmc_data *data = mrq->data;
3509
3510 return host->pending_reset || host->always_defer_done ||
3511 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3512 data->host_cookie == COOKIE_MAPPED);
3513}
3514
3515static irqreturn_t sdhci_irq(int irq, void *dev_id)
3516{
3517 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3518 irqreturn_t result = IRQ_NONE;
3519 struct sdhci_host *host = dev_id;
3520 u32 intmask, mask, unexpected = 0;
3521 int max_loops = 16;
3522 int i;
3523
3524 spin_lock(&host->lock);
3525
3526 if (host->runtime_suspended) {
3527 spin_unlock(&host->lock);
3528 return IRQ_NONE;
3529 }
3530
3531 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3532 if (!intmask || intmask == 0xffffffff) {
3533 result = IRQ_NONE;
3534 goto out;
3535 }
3536
3537 do {
3538 DBG("IRQ status 0x%08x\n", intmask);
3539
3540 if (host->ops->irq) {
3541 intmask = host->ops->irq(host, intmask);
3542 if (!intmask)
3543 goto cont;
3544 }
3545
3546 /* Clear selected interrupts. */
3547 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3548 SDHCI_INT_BUS_POWER);
3549 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3550
3551 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3552 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3553 SDHCI_CARD_PRESENT;
3554
3555 /*
3556 * There is a observation on i.mx esdhc. INSERT
3557 * bit will be immediately set again when it gets
3558 * cleared, if a card is inserted. We have to mask
3559 * the irq to prevent interrupt storm which will
3560 * freeze the system. And the REMOVE gets the
3561 * same situation.
3562 *
3563 * More testing are needed here to ensure it works
3564 * for other platforms though.
3565 */
3566 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3567 SDHCI_INT_CARD_REMOVE);
3568 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3569 SDHCI_INT_CARD_INSERT;
3570 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3571 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3572
3573 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3574 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3575
3576 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3577 SDHCI_INT_CARD_REMOVE);
3578 result = IRQ_WAKE_THREAD;
3579 }
3580
3581 if (intmask & SDHCI_INT_CMD_MASK)
3582 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3583
3584 if (intmask & SDHCI_INT_DATA_MASK)
3585 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3586
3587 if (intmask & SDHCI_INT_BUS_POWER)
3588 pr_err("%s: Card is consuming too much power!\n",
3589 mmc_hostname(host->mmc));
3590
3591 if (intmask & SDHCI_INT_RETUNE)
3592 mmc_retune_needed(host->mmc);
3593
3594 if ((intmask & SDHCI_INT_CARD_INT) &&
3595 (host->ier & SDHCI_INT_CARD_INT)) {
3596 sdhci_enable_sdio_irq_nolock(host, false);
3597 sdio_signal_irq(host->mmc);
3598 }
3599
3600 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3601 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3602 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3603 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3604
3605 if (intmask) {
3606 unexpected |= intmask;
3607 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3608 }
3609cont:
3610 if (result == IRQ_NONE)
3611 result = IRQ_HANDLED;
3612
3613 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3614 } while (intmask && --max_loops);
3615
3616 /* Determine if mrqs can be completed immediately */
3617 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3618 struct mmc_request *mrq = host->mrqs_done[i];
3619
3620 if (!mrq)
3621 continue;
3622
3623 if (sdhci_defer_done(host, mrq)) {
3624 result = IRQ_WAKE_THREAD;
3625 } else {
3626 mrqs_done[i] = mrq;
3627 host->mrqs_done[i] = NULL;
3628 }
3629 }
3630out:
3631 if (host->deferred_cmd)
3632 result = IRQ_WAKE_THREAD;
3633
3634 spin_unlock(&host->lock);
3635
3636 /* Process mrqs ready for immediate completion */
3637 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3638 if (!mrqs_done[i])
3639 continue;
3640
3641 if (host->ops->request_done)
3642 host->ops->request_done(host, mrqs_done[i]);
3643 else
3644 mmc_request_done(host->mmc, mrqs_done[i]);
3645 }
3646
3647 if (unexpected) {
3648 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3649 mmc_hostname(host->mmc), unexpected);
3650 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3651 sdhci_dumpregs(host);
3652 }
3653
3654 return result;
3655}
3656
3657static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3658{
3659 struct sdhci_host *host = dev_id;
3660 struct mmc_command *cmd;
3661 unsigned long flags;
3662 u32 isr;
3663
3664 while (!sdhci_request_done(host))
3665 ;
3666
3667 spin_lock_irqsave(&host->lock, flags);
3668
3669 isr = host->thread_isr;
3670 host->thread_isr = 0;
3671
3672 cmd = host->deferred_cmd;
3673 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3674 sdhci_finish_mrq(host, cmd->mrq);
3675
3676 spin_unlock_irqrestore(&host->lock, flags);
3677
3678 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3679 struct mmc_host *mmc = host->mmc;
3680
3681 mmc->ops->card_event(mmc);
3682 mmc_detect_change(mmc, msecs_to_jiffies(200));
3683 }
3684
3685 return IRQ_HANDLED;
3686}
3687
3688/*****************************************************************************\
3689 * *
3690 * Suspend/resume *
3691 * *
3692\*****************************************************************************/
3693
3694#ifdef CONFIG_PM
3695
3696static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3697{
3698 return mmc_card_is_removable(host->mmc) &&
3699 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3700 !mmc_can_gpio_cd(host->mmc);
3701}
3702
3703/*
3704 * To enable wakeup events, the corresponding events have to be enabled in
3705 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3706 * Table' in the SD Host Controller Standard Specification.
3707 * It is useless to restore SDHCI_INT_ENABLE state in
3708 * sdhci_disable_irq_wakeups() since it will be set by
3709 * sdhci_enable_card_detection() or sdhci_init().
3710 */
3711static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3712{
3713 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3714 SDHCI_WAKE_ON_INT;
3715 u32 irq_val = 0;
3716 u8 wake_val = 0;
3717 u8 val;
3718
3719 if (sdhci_cd_irq_can_wakeup(host)) {
3720 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3721 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3722 }
3723
3724 if (mmc_card_wake_sdio_irq(host->mmc)) {
3725 wake_val |= SDHCI_WAKE_ON_INT;
3726 irq_val |= SDHCI_INT_CARD_INT;
3727 }
3728
3729 if (!irq_val)
3730 return false;
3731
3732 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3733 val &= ~mask;
3734 val |= wake_val;
3735 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3736
3737 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3738
3739 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3740
3741 return host->irq_wake_enabled;
3742}
3743
3744static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3745{
3746 u8 val;
3747 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3748 | SDHCI_WAKE_ON_INT;
3749
3750 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3751 val &= ~mask;
3752 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3753
3754 disable_irq_wake(host->irq);
3755
3756 host->irq_wake_enabled = false;
3757}
3758
3759int sdhci_suspend_host(struct sdhci_host *host)
3760{
3761 sdhci_disable_card_detection(host);
3762
3763 mmc_retune_timer_stop(host->mmc);
3764
3765 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3766 !sdhci_enable_irq_wakeups(host)) {
3767 host->ier = 0;
3768 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3769 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3770 free_irq(host->irq, host);
3771 }
3772
3773 return 0;
3774}
3775
3776EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3777
3778int sdhci_resume_host(struct sdhci_host *host)
3779{
3780 struct mmc_host *mmc = host->mmc;
3781 int ret = 0;
3782
3783 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3784 if (host->ops->enable_dma)
3785 host->ops->enable_dma(host);
3786 }
3787
3788 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3789 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3790 /* Card keeps power but host controller does not */
3791 sdhci_init(host, 0);
3792 host->pwr = 0;
3793 host->clock = 0;
3794 host->reinit_uhs = true;
3795 mmc->ops->set_ios(mmc, &mmc->ios);
3796 } else {
3797 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3798 }
3799
3800 if (host->irq_wake_enabled) {
3801 sdhci_disable_irq_wakeups(host);
3802 } else {
3803 ret = request_threaded_irq(host->irq, sdhci_irq,
3804 sdhci_thread_irq, IRQF_SHARED,
3805 mmc_hostname(mmc), host);
3806 if (ret)
3807 return ret;
3808 }
3809
3810 sdhci_enable_card_detection(host);
3811
3812 return ret;
3813}
3814
3815EXPORT_SYMBOL_GPL(sdhci_resume_host);
3816
3817int sdhci_runtime_suspend_host(struct sdhci_host *host)
3818{
3819 unsigned long flags;
3820
3821 mmc_retune_timer_stop(host->mmc);
3822
3823 spin_lock_irqsave(&host->lock, flags);
3824 host->ier &= SDHCI_INT_CARD_INT;
3825 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3826 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3827 spin_unlock_irqrestore(&host->lock, flags);
3828
3829 synchronize_hardirq(host->irq);
3830
3831 spin_lock_irqsave(&host->lock, flags);
3832 host->runtime_suspended = true;
3833 spin_unlock_irqrestore(&host->lock, flags);
3834
3835 return 0;
3836}
3837EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3838
3839int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3840{
3841 struct mmc_host *mmc = host->mmc;
3842 unsigned long flags;
3843 int host_flags = host->flags;
3844
3845 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3846 if (host->ops->enable_dma)
3847 host->ops->enable_dma(host);
3848 }
3849
3850 sdhci_init(host, soft_reset);
3851
3852 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3853 mmc->ios.power_mode != MMC_POWER_OFF) {
3854 /* Force clock and power re-program */
3855 host->pwr = 0;
3856 host->clock = 0;
3857 host->reinit_uhs = true;
3858 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3859 mmc->ops->set_ios(mmc, &mmc->ios);
3860
3861 if ((host_flags & SDHCI_PV_ENABLED) &&
3862 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3863 spin_lock_irqsave(&host->lock, flags);
3864 sdhci_enable_preset_value(host, true);
3865 spin_unlock_irqrestore(&host->lock, flags);
3866 }
3867
3868 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3869 mmc->ops->hs400_enhanced_strobe)
3870 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3871 }
3872
3873 spin_lock_irqsave(&host->lock, flags);
3874
3875 host->runtime_suspended = false;
3876
3877 /* Enable SDIO IRQ */
3878 if (sdio_irq_claimed(mmc))
3879 sdhci_enable_sdio_irq_nolock(host, true);
3880
3881 /* Enable Card Detection */
3882 sdhci_enable_card_detection(host);
3883
3884 spin_unlock_irqrestore(&host->lock, flags);
3885
3886 return 0;
3887}
3888EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3889
3890#endif /* CONFIG_PM */
3891
3892/*****************************************************************************\
3893 * *
3894 * Command Queue Engine (CQE) helpers *
3895 * *
3896\*****************************************************************************/
3897
3898void sdhci_cqe_enable(struct mmc_host *mmc)
3899{
3900 struct sdhci_host *host = mmc_priv(mmc);
3901 unsigned long flags;
3902 u8 ctrl;
3903
3904 spin_lock_irqsave(&host->lock, flags);
3905
3906 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3907 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3908 /*
3909 * Host from V4.10 supports ADMA3 DMA type.
3910 * ADMA3 performs integrated descriptor which is more suitable
3911 * for cmd queuing to fetch both command and transfer descriptors.
3912 */
3913 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3914 ctrl |= SDHCI_CTRL_ADMA3;
3915 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3916 ctrl |= SDHCI_CTRL_ADMA64;
3917 else
3918 ctrl |= SDHCI_CTRL_ADMA32;
3919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3920
3921 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3922 SDHCI_BLOCK_SIZE);
3923
3924 /* Set maximum timeout */
3925 sdhci_set_timeout(host, NULL);
3926
3927 host->ier = host->cqe_ier;
3928
3929 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3930 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3931
3932 host->cqe_on = true;
3933
3934 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3935 mmc_hostname(mmc), host->ier,
3936 sdhci_readl(host, SDHCI_INT_STATUS));
3937
3938 spin_unlock_irqrestore(&host->lock, flags);
3939}
3940EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3941
3942void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3943{
3944 struct sdhci_host *host = mmc_priv(mmc);
3945 unsigned long flags;
3946
3947 spin_lock_irqsave(&host->lock, flags);
3948
3949 sdhci_set_default_irqs(host);
3950
3951 host->cqe_on = false;
3952
3953 if (recovery)
3954 sdhci_reset_for(host, CQE_RECOVERY);
3955
3956 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3957 mmc_hostname(mmc), host->ier,
3958 sdhci_readl(host, SDHCI_INT_STATUS));
3959
3960 spin_unlock_irqrestore(&host->lock, flags);
3961}
3962EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3963
3964bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3965 int *data_error)
3966{
3967 u32 mask;
3968
3969 if (!host->cqe_on)
3970 return false;
3971
3972 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
3973 *cmd_error = -EILSEQ;
3974 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3975 sdhci_err_stats_inc(host, CMD_CRC);
3976 } else if (intmask & SDHCI_INT_TIMEOUT) {
3977 *cmd_error = -ETIMEDOUT;
3978 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3979 } else
3980 *cmd_error = 0;
3981
3982 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) {
3983 *data_error = -EILSEQ;
3984 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3985 sdhci_err_stats_inc(host, DAT_CRC);
3986 } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3987 *data_error = -ETIMEDOUT;
3988 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3989 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3990 *data_error = -EIO;
3991 sdhci_err_stats_inc(host, ADMA);
3992 } else
3993 *data_error = 0;
3994
3995 /* Clear selected interrupts. */
3996 mask = intmask & host->cqe_ier;
3997 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3998
3999 if (intmask & SDHCI_INT_BUS_POWER)
4000 pr_err("%s: Card is consuming too much power!\n",
4001 mmc_hostname(host->mmc));
4002
4003 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4004 if (intmask) {
4005 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4006 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
4007 mmc_hostname(host->mmc), intmask);
4008 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
4009 sdhci_dumpregs(host);
4010 }
4011
4012 return true;
4013}
4014EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
4015
4016/*****************************************************************************\
4017 * *
4018 * Device allocation/registration *
4019 * *
4020\*****************************************************************************/
4021
4022struct sdhci_host *sdhci_alloc_host(struct device *dev,
4023 size_t priv_size)
4024{
4025 struct mmc_host *mmc;
4026 struct sdhci_host *host;
4027
4028 WARN_ON(dev == NULL);
4029
4030 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
4031 if (!mmc)
4032 return ERR_PTR(-ENOMEM);
4033
4034 host = mmc_priv(mmc);
4035 host->mmc = mmc;
4036 host->mmc_host_ops = sdhci_ops;
4037 mmc->ops = &host->mmc_host_ops;
4038
4039 host->flags = SDHCI_SIGNALING_330;
4040
4041 host->cqe_ier = SDHCI_CQE_INT_MASK;
4042 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4043
4044 host->tuning_delay = -1;
4045 host->tuning_loop_count = MAX_TUNING_LOOP;
4046
4047 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4048
4049 /*
4050 * The DMA table descriptor count is calculated as the maximum
4051 * number of segments times 2, to allow for an alignment
4052 * descriptor for each segment, plus 1 for a nop end descriptor.
4053 */
4054 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4055 host->max_adma = 65536;
4056
4057 host->max_timeout_count = 0xE;
4058
4059 return host;
4060}
4061
4062EXPORT_SYMBOL_GPL(sdhci_alloc_host);
4063
4064static int sdhci_set_dma_mask(struct sdhci_host *host)
4065{
4066 struct mmc_host *mmc = host->mmc;
4067 struct device *dev = mmc_dev(mmc);
4068 int ret = -EINVAL;
4069
4070 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4071 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4072
4073 /* Try 64-bit mask if hardware is capable of it */
4074 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4075 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4076 if (ret) {
4077 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
4078 mmc_hostname(mmc));
4079 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4080 }
4081 }
4082
4083 /* 32-bit mask as default & fallback */
4084 if (ret) {
4085 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
4086 if (ret)
4087 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4088 mmc_hostname(mmc));
4089 }
4090
4091 return ret;
4092}
4093
4094void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4095 const u32 *caps, const u32 *caps1)
4096{
4097 u16 v;
4098 u64 dt_caps_mask = 0;
4099 u64 dt_caps = 0;
4100
4101 if (host->read_caps)
4102 return;
4103
4104 host->read_caps = true;
4105
4106 if (debug_quirks)
4107 host->quirks = debug_quirks;
4108
4109 if (debug_quirks2)
4110 host->quirks2 = debug_quirks2;
4111
4112 sdhci_reset_for_all(host);
4113
4114 if (host->v4_mode)
4115 sdhci_do_enable_v4_mode(host);
4116
4117 device_property_read_u64(mmc_dev(host->mmc),
4118 "sdhci-caps-mask", &dt_caps_mask);
4119 device_property_read_u64(mmc_dev(host->mmc),
4120 "sdhci-caps", &dt_caps);
4121
4122 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4123 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4124
4125 if (caps) {
4126 host->caps = *caps;
4127 } else {
4128 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4129 host->caps &= ~lower_32_bits(dt_caps_mask);
4130 host->caps |= lower_32_bits(dt_caps);
4131 }
4132
4133 if (host->version < SDHCI_SPEC_300)
4134 return;
4135
4136 if (caps1) {
4137 host->caps1 = *caps1;
4138 } else {
4139 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4140 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4141 host->caps1 |= upper_32_bits(dt_caps);
4142 }
4143}
4144EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4145
4146static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4147{
4148 struct mmc_host *mmc = host->mmc;
4149 unsigned int max_blocks;
4150 unsigned int bounce_size;
4151 int ret;
4152
4153 /*
4154 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4155 * has diminishing returns, this is probably because SD/MMC
4156 * cards are usually optimized to handle this size of requests.
4157 */
4158 bounce_size = SZ_64K;
4159 /*
4160 * Adjust downwards to maximum request size if this is less
4161 * than our segment size, else hammer down the maximum
4162 * request size to the maximum buffer size.
4163 */
4164 if (mmc->max_req_size < bounce_size)
4165 bounce_size = mmc->max_req_size;
4166 max_blocks = bounce_size / 512;
4167
4168 /*
4169 * When we just support one segment, we can get significant
4170 * speedups by the help of a bounce buffer to group scattered
4171 * reads/writes together.
4172 */
4173 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4174 bounce_size,
4175 GFP_KERNEL);
4176 if (!host->bounce_buffer) {
4177 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4178 mmc_hostname(mmc),
4179 bounce_size);
4180 /*
4181 * Exiting with zero here makes sure we proceed with
4182 * mmc->max_segs == 1.
4183 */
4184 return;
4185 }
4186
4187 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4188 host->bounce_buffer,
4189 bounce_size,
4190 DMA_BIDIRECTIONAL);
4191 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4192 if (ret) {
4193 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4194 host->bounce_buffer = NULL;
4195 /* Again fall back to max_segs == 1 */
4196 return;
4197 }
4198
4199 host->bounce_buffer_size = bounce_size;
4200
4201 /* Lie about this since we're bouncing */
4202 mmc->max_segs = max_blocks;
4203 mmc->max_seg_size = bounce_size;
4204 mmc->max_req_size = bounce_size;
4205
4206 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4207 mmc_hostname(mmc), max_blocks, bounce_size);
4208}
4209
4210static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4211{
4212 /*
4213 * According to SD Host Controller spec v4.10, bit[27] added from
4214 * version 4.10 in Capabilities Register is used as 64-bit System
4215 * Address support for V4 mode.
4216 */
4217 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4218 return host->caps & SDHCI_CAN_64BIT_V4;
4219
4220 return host->caps & SDHCI_CAN_64BIT;
4221}
4222
4223int sdhci_setup_host(struct sdhci_host *host)
4224{
4225 struct mmc_host *mmc;
4226 u32 max_current_caps;
4227 unsigned int ocr_avail;
4228 unsigned int override_timeout_clk;
4229 u32 max_clk;
4230 int ret = 0;
4231 bool enable_vqmmc = false;
4232
4233 WARN_ON(host == NULL);
4234 if (host == NULL)
4235 return -EINVAL;
4236
4237 mmc = host->mmc;
4238
4239 /*
4240 * If there are external regulators, get them. Note this must be done
4241 * early before resetting the host and reading the capabilities so that
4242 * the host can take the appropriate action if regulators are not
4243 * available.
4244 */
4245 if (!mmc->supply.vqmmc) {
4246 ret = mmc_regulator_get_supply(mmc);
4247 if (ret)
4248 return ret;
4249 enable_vqmmc = true;
4250 }
4251
4252 DBG("Version: 0x%08x | Present: 0x%08x\n",
4253 sdhci_readw(host, SDHCI_HOST_VERSION),
4254 sdhci_readl(host, SDHCI_PRESENT_STATE));
4255 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4256 sdhci_readl(host, SDHCI_CAPABILITIES),
4257 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4258
4259 sdhci_read_caps(host);
4260
4261 override_timeout_clk = host->timeout_clk;
4262
4263 if (host->version > SDHCI_SPEC_420) {
4264 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4265 mmc_hostname(mmc), host->version);
4266 }
4267
4268 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4269 host->flags |= SDHCI_USE_SDMA;
4270 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4271 DBG("Controller doesn't have SDMA capability\n");
4272 else
4273 host->flags |= SDHCI_USE_SDMA;
4274
4275 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4276 (host->flags & SDHCI_USE_SDMA)) {
4277 DBG("Disabling DMA as it is marked broken\n");
4278 host->flags &= ~SDHCI_USE_SDMA;
4279 }
4280
4281 if ((host->version >= SDHCI_SPEC_200) &&
4282 (host->caps & SDHCI_CAN_DO_ADMA2))
4283 host->flags |= SDHCI_USE_ADMA;
4284
4285 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4286 (host->flags & SDHCI_USE_ADMA)) {
4287 DBG("Disabling ADMA as it is marked broken\n");
4288 host->flags &= ~SDHCI_USE_ADMA;
4289 }
4290
4291 if (sdhci_can_64bit_dma(host))
4292 host->flags |= SDHCI_USE_64_BIT_DMA;
4293
4294 if (host->use_external_dma) {
4295 ret = sdhci_external_dma_init(host);
4296 if (ret == -EPROBE_DEFER)
4297 goto unreg;
4298 /*
4299 * Fall back to use the DMA/PIO integrated in standard SDHCI
4300 * instead of external DMA devices.
4301 */
4302 else if (ret)
4303 sdhci_switch_external_dma(host, false);
4304 /* Disable internal DMA sources */
4305 else
4306 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4307 }
4308
4309 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4310 if (host->ops->set_dma_mask)
4311 ret = host->ops->set_dma_mask(host);
4312 else
4313 ret = sdhci_set_dma_mask(host);
4314
4315 if (!ret && host->ops->enable_dma)
4316 ret = host->ops->enable_dma(host);
4317
4318 if (ret) {
4319 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4320 mmc_hostname(mmc));
4321 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4322
4323 ret = 0;
4324 }
4325 }
4326
4327 /* SDMA does not support 64-bit DMA if v4 mode not set */
4328 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4329 host->flags &= ~SDHCI_USE_SDMA;
4330
4331 if (host->flags & SDHCI_USE_ADMA) {
4332 dma_addr_t dma;
4333 void *buf;
4334
4335 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4336 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4337 else if (!host->alloc_desc_sz)
4338 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4339
4340 host->desc_sz = host->alloc_desc_sz;
4341 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4342
4343 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4344 /*
4345 * Use zalloc to zero the reserved high 32-bits of 128-bit
4346 * descriptors so that they never need to be written.
4347 */
4348 buf = dma_alloc_coherent(mmc_dev(mmc),
4349 host->align_buffer_sz + host->adma_table_sz,
4350 &dma, GFP_KERNEL);
4351 if (!buf) {
4352 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4353 mmc_hostname(mmc));
4354 host->flags &= ~SDHCI_USE_ADMA;
4355 } else if ((dma + host->align_buffer_sz) &
4356 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4357 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4358 mmc_hostname(mmc));
4359 host->flags &= ~SDHCI_USE_ADMA;
4360 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4361 host->adma_table_sz, buf, dma);
4362 } else {
4363 host->align_buffer = buf;
4364 host->align_addr = dma;
4365
4366 host->adma_table = buf + host->align_buffer_sz;
4367 host->adma_addr = dma + host->align_buffer_sz;
4368 }
4369 }
4370
4371 /*
4372 * If we use DMA, then it's up to the caller to set the DMA
4373 * mask, but PIO does not need the hw shim so we set a new
4374 * mask here in that case.
4375 */
4376 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4377 host->dma_mask = DMA_BIT_MASK(64);
4378 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4379 }
4380
4381 if (host->version >= SDHCI_SPEC_300)
4382 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4383 else
4384 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4385
4386 host->max_clk *= 1000000;
4387 if (host->max_clk == 0 || host->quirks &
4388 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4389 if (!host->ops->get_max_clock) {
4390 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4391 mmc_hostname(mmc));
4392 ret = -ENODEV;
4393 goto undma;
4394 }
4395 host->max_clk = host->ops->get_max_clock(host);
4396 }
4397
4398 /*
4399 * In case of Host Controller v3.00, find out whether clock
4400 * multiplier is supported.
4401 */
4402 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4403
4404 /*
4405 * In case the value in Clock Multiplier is 0, then programmable
4406 * clock mode is not supported, otherwise the actual clock
4407 * multiplier is one more than the value of Clock Multiplier
4408 * in the Capabilities Register.
4409 */
4410 if (host->clk_mul)
4411 host->clk_mul += 1;
4412
4413 /*
4414 * Set host parameters.
4415 */
4416 max_clk = host->max_clk;
4417
4418 if (host->ops->get_min_clock)
4419 mmc->f_min = host->ops->get_min_clock(host);
4420 else if (host->version >= SDHCI_SPEC_300) {
4421 if (host->clk_mul)
4422 max_clk = host->max_clk * host->clk_mul;
4423 /*
4424 * Divided Clock Mode minimum clock rate is always less than
4425 * Programmable Clock Mode minimum clock rate.
4426 */
4427 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4428 } else
4429 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4430
4431 if (!mmc->f_max || mmc->f_max > max_clk)
4432 mmc->f_max = max_clk;
4433
4434 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4435 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4436
4437 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4438 host->timeout_clk *= 1000;
4439
4440 if (host->timeout_clk == 0) {
4441 if (!host->ops->get_timeout_clock) {
4442 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4443 mmc_hostname(mmc));
4444 ret = -ENODEV;
4445 goto undma;
4446 }
4447
4448 host->timeout_clk =
4449 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4450 1000);
4451 }
4452
4453 if (override_timeout_clk)
4454 host->timeout_clk = override_timeout_clk;
4455
4456 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4457 host->ops->get_max_timeout_count(host) : 1 << 27;
4458 mmc->max_busy_timeout /= host->timeout_clk;
4459 }
4460
4461 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4462 !host->ops->get_max_timeout_count)
4463 mmc->max_busy_timeout = 0;
4464
4465 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4466 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4467
4468 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4469 host->flags |= SDHCI_AUTO_CMD12;
4470
4471 /*
4472 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4473 * For v4 mode, SDMA may use Auto-CMD23 as well.
4474 */
4475 if ((host->version >= SDHCI_SPEC_300) &&
4476 ((host->flags & SDHCI_USE_ADMA) ||
4477 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4478 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4479 host->flags |= SDHCI_AUTO_CMD23;
4480 DBG("Auto-CMD23 available\n");
4481 } else {
4482 DBG("Auto-CMD23 unavailable\n");
4483 }
4484
4485 /*
4486 * A controller may support 8-bit width, but the board itself
4487 * might not have the pins brought out. Boards that support
4488 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4489 * their platform code before calling sdhci_add_host(), and we
4490 * won't assume 8-bit width for hosts without that CAP.
4491 */
4492 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4493 mmc->caps |= MMC_CAP_4_BIT_DATA;
4494
4495 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4496 mmc->caps &= ~MMC_CAP_CMD23;
4497
4498 if (host->caps & SDHCI_CAN_DO_HISPD)
4499 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4500
4501 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4502 mmc_card_is_removable(mmc) &&
4503 mmc_gpio_get_cd(mmc) < 0)
4504 mmc->caps |= MMC_CAP_NEEDS_POLL;
4505
4506 if (!IS_ERR(mmc->supply.vqmmc)) {
4507 if (enable_vqmmc) {
4508 ret = regulator_enable(mmc->supply.vqmmc);
4509 host->sdhci_core_to_disable_vqmmc = !ret;
4510 }
4511
4512 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4513 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4514 1950000))
4515 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4516 SDHCI_SUPPORT_SDR50 |
4517 SDHCI_SUPPORT_DDR50);
4518
4519 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4520 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4521 3600000))
4522 host->flags &= ~SDHCI_SIGNALING_330;
4523
4524 if (ret) {
4525 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4526 mmc_hostname(mmc), ret);
4527 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4528 }
4529
4530 }
4531
4532 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4533 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4534 SDHCI_SUPPORT_DDR50);
4535 /*
4536 * The SDHCI controller in a SoC might support HS200/HS400
4537 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4538 * but if the board is modeled such that the IO lines are not
4539 * connected to 1.8v then HS200/HS400 cannot be supported.
4540 * Disable HS200/HS400 if the board does not have 1.8v connected
4541 * to the IO lines. (Applicable for other modes in 1.8v)
4542 */
4543 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4544 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4545 }
4546
4547 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4548 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4549 SDHCI_SUPPORT_DDR50))
4550 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4551
4552 /* SDR104 supports also implies SDR50 support */
4553 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4554 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4555 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4556 * field can be promoted to support HS200.
4557 */
4558 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4559 mmc->caps2 |= MMC_CAP2_HS200;
4560 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4561 mmc->caps |= MMC_CAP_UHS_SDR50;
4562 }
4563
4564 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4565 (host->caps1 & SDHCI_SUPPORT_HS400))
4566 mmc->caps2 |= MMC_CAP2_HS400;
4567
4568 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4569 (IS_ERR(mmc->supply.vqmmc) ||
4570 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4571 1300000)))
4572 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4573
4574 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4575 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4576 mmc->caps |= MMC_CAP_UHS_DDR50;
4577
4578 /* Does the host need tuning for SDR50? */
4579 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4580 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4581
4582 /* Driver Type(s) (A, C, D) supported by the host */
4583 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4584 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4585 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4586 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4587 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4588 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4589
4590 /* Initial value for re-tuning timer count */
4591 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4592 host->caps1);
4593
4594 /*
4595 * In case Re-tuning Timer is not disabled, the actual value of
4596 * re-tuning timer will be 2 ^ (n - 1).
4597 */
4598 if (host->tuning_count)
4599 host->tuning_count = 1 << (host->tuning_count - 1);
4600
4601 /* Re-tuning mode supported by the Host Controller */
4602 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4603
4604 ocr_avail = 0;
4605
4606 /*
4607 * According to SD Host Controller spec v3.00, if the Host System
4608 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4609 * the value is meaningful only if Voltage Support in the Capabilities
4610 * register is set. The actual current value is 4 times the register
4611 * value.
4612 */
4613 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4614 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4615 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4616 if (curr > 0) {
4617
4618 /* convert to SDHCI_MAX_CURRENT format */
4619 curr = curr/1000; /* convert to mA */
4620 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4621
4622 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4623 max_current_caps =
4624 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4625 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4626 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4627 }
4628 }
4629
4630 if (host->caps & SDHCI_CAN_VDD_330) {
4631 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4632
4633 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4634 max_current_caps) *
4635 SDHCI_MAX_CURRENT_MULTIPLIER;
4636 }
4637 if (host->caps & SDHCI_CAN_VDD_300) {
4638 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4639
4640 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4641 max_current_caps) *
4642 SDHCI_MAX_CURRENT_MULTIPLIER;
4643 }
4644 if (host->caps & SDHCI_CAN_VDD_180) {
4645 ocr_avail |= MMC_VDD_165_195;
4646
4647 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4648 max_current_caps) *
4649 SDHCI_MAX_CURRENT_MULTIPLIER;
4650 }
4651
4652 /* If OCR set by host, use it instead. */
4653 if (host->ocr_mask)
4654 ocr_avail = host->ocr_mask;
4655
4656 /* If OCR set by external regulators, give it highest prio. */
4657 if (mmc->ocr_avail)
4658 ocr_avail = mmc->ocr_avail;
4659
4660 mmc->ocr_avail = ocr_avail;
4661 mmc->ocr_avail_sdio = ocr_avail;
4662 if (host->ocr_avail_sdio)
4663 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4664 mmc->ocr_avail_sd = ocr_avail;
4665 if (host->ocr_avail_sd)
4666 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4667 else /* normal SD controllers don't support 1.8V */
4668 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4669 mmc->ocr_avail_mmc = ocr_avail;
4670 if (host->ocr_avail_mmc)
4671 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4672
4673 if (mmc->ocr_avail == 0) {
4674 pr_err("%s: Hardware doesn't report any support voltages.\n",
4675 mmc_hostname(mmc));
4676 ret = -ENODEV;
4677 goto unreg;
4678 }
4679
4680 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4681 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4682 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4683 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4684 host->flags |= SDHCI_SIGNALING_180;
4685
4686 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4687 host->flags |= SDHCI_SIGNALING_120;
4688
4689 spin_lock_init(&host->lock);
4690
4691 /*
4692 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4693 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4694 * is less anyway.
4695 */
4696 mmc->max_req_size = 524288;
4697
4698 /*
4699 * Maximum number of segments. Depends on if the hardware
4700 * can do scatter/gather or not.
4701 */
4702 if (host->flags & SDHCI_USE_ADMA) {
4703 mmc->max_segs = SDHCI_MAX_SEGS;
4704 } else if (host->flags & SDHCI_USE_SDMA) {
4705 mmc->max_segs = 1;
4706 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4707 dma_max_mapping_size(mmc_dev(mmc)));
4708 } else { /* PIO */
4709 mmc->max_segs = SDHCI_MAX_SEGS;
4710 }
4711
4712 /*
4713 * Maximum segment size. Could be one segment with the maximum number
4714 * of bytes. When doing hardware scatter/gather, each entry cannot
4715 * be larger than 64 KiB though.
4716 */
4717 if (host->flags & SDHCI_USE_ADMA) {
4718 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4719 host->max_adma = 65532; /* 32-bit alignment */
4720 mmc->max_seg_size = 65535;
4721 } else {
4722 mmc->max_seg_size = 65536;
4723 }
4724 } else {
4725 mmc->max_seg_size = mmc->max_req_size;
4726 }
4727
4728 /*
4729 * Maximum block size. This varies from controller to controller and
4730 * is specified in the capabilities register.
4731 */
4732 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4733 mmc->max_blk_size = 2;
4734 } else {
4735 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4736 SDHCI_MAX_BLOCK_SHIFT;
4737 if (mmc->max_blk_size >= 3) {
4738 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4739 mmc_hostname(mmc));
4740 mmc->max_blk_size = 0;
4741 }
4742 }
4743
4744 mmc->max_blk_size = 512 << mmc->max_blk_size;
4745
4746 /*
4747 * Maximum block count.
4748 */
4749 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4750
4751 if (mmc->max_segs == 1)
4752 /* This may alter mmc->*_blk_* parameters */
4753 sdhci_allocate_bounce_buffer(host);
4754
4755 return 0;
4756
4757unreg:
4758 if (host->sdhci_core_to_disable_vqmmc)
4759 regulator_disable(mmc->supply.vqmmc);
4760undma:
4761 if (host->align_buffer)
4762 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4763 host->adma_table_sz, host->align_buffer,
4764 host->align_addr);
4765 host->adma_table = NULL;
4766 host->align_buffer = NULL;
4767
4768 return ret;
4769}
4770EXPORT_SYMBOL_GPL(sdhci_setup_host);
4771
4772void sdhci_cleanup_host(struct sdhci_host *host)
4773{
4774 struct mmc_host *mmc = host->mmc;
4775
4776 if (host->sdhci_core_to_disable_vqmmc)
4777 regulator_disable(mmc->supply.vqmmc);
4778
4779 if (host->align_buffer)
4780 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4781 host->adma_table_sz, host->align_buffer,
4782 host->align_addr);
4783
4784 if (host->use_external_dma)
4785 sdhci_external_dma_release(host);
4786
4787 host->adma_table = NULL;
4788 host->align_buffer = NULL;
4789}
4790EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4791
4792int __sdhci_add_host(struct sdhci_host *host)
4793{
4794 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4795 struct mmc_host *mmc = host->mmc;
4796 int ret;
4797
4798 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4799 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4800 mmc->caps2 &= ~MMC_CAP2_CQE;
4801 mmc->cqe_ops = NULL;
4802 }
4803
4804 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4805 if (!host->complete_wq)
4806 return -ENOMEM;
4807
4808 INIT_WORK(&host->complete_work, sdhci_complete_work);
4809
4810 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4811 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4812
4813 init_waitqueue_head(&host->buf_ready_int);
4814
4815 sdhci_init(host, 0);
4816
4817 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4818 IRQF_SHARED, mmc_hostname(mmc), host);
4819 if (ret) {
4820 pr_err("%s: Failed to request IRQ %d: %d\n",
4821 mmc_hostname(mmc), host->irq, ret);
4822 goto unwq;
4823 }
4824
4825 ret = sdhci_led_register(host);
4826 if (ret) {
4827 pr_err("%s: Failed to register LED device: %d\n",
4828 mmc_hostname(mmc), ret);
4829 goto unirq;
4830 }
4831
4832 ret = mmc_add_host(mmc);
4833 if (ret)
4834 goto unled;
4835
4836 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4837 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4838 host->use_external_dma ? "External DMA" :
4839 (host->flags & SDHCI_USE_ADMA) ?
4840 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4841 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4842
4843 sdhci_enable_card_detection(host);
4844
4845 return 0;
4846
4847unled:
4848 sdhci_led_unregister(host);
4849unirq:
4850 sdhci_reset_for_all(host);
4851 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4852 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4853 free_irq(host->irq, host);
4854unwq:
4855 destroy_workqueue(host->complete_wq);
4856
4857 return ret;
4858}
4859EXPORT_SYMBOL_GPL(__sdhci_add_host);
4860
4861int sdhci_add_host(struct sdhci_host *host)
4862{
4863 int ret;
4864
4865 ret = sdhci_setup_host(host);
4866 if (ret)
4867 return ret;
4868
4869 ret = __sdhci_add_host(host);
4870 if (ret)
4871 goto cleanup;
4872
4873 return 0;
4874
4875cleanup:
4876 sdhci_cleanup_host(host);
4877
4878 return ret;
4879}
4880EXPORT_SYMBOL_GPL(sdhci_add_host);
4881
4882void sdhci_remove_host(struct sdhci_host *host, int dead)
4883{
4884 struct mmc_host *mmc = host->mmc;
4885 unsigned long flags;
4886
4887 if (dead) {
4888 spin_lock_irqsave(&host->lock, flags);
4889
4890 host->flags |= SDHCI_DEVICE_DEAD;
4891
4892 if (sdhci_has_requests(host)) {
4893 pr_err("%s: Controller removed during "
4894 " transfer!\n", mmc_hostname(mmc));
4895 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4896 }
4897
4898 spin_unlock_irqrestore(&host->lock, flags);
4899 }
4900
4901 sdhci_disable_card_detection(host);
4902
4903 mmc_remove_host(mmc);
4904
4905 sdhci_led_unregister(host);
4906
4907 if (!dead)
4908 sdhci_reset_for_all(host);
4909
4910 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4911 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4912 free_irq(host->irq, host);
4913
4914 del_timer_sync(&host->timer);
4915 del_timer_sync(&host->data_timer);
4916
4917 destroy_workqueue(host->complete_wq);
4918
4919 if (host->sdhci_core_to_disable_vqmmc)
4920 regulator_disable(mmc->supply.vqmmc);
4921
4922 if (host->align_buffer)
4923 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4924 host->adma_table_sz, host->align_buffer,
4925 host->align_addr);
4926
4927 if (host->use_external_dma)
4928 sdhci_external_dma_release(host);
4929
4930 host->adma_table = NULL;
4931 host->align_buffer = NULL;
4932}
4933
4934EXPORT_SYMBOL_GPL(sdhci_remove_host);
4935
4936void sdhci_free_host(struct sdhci_host *host)
4937{
4938 mmc_free_host(host->mmc);
4939}
4940
4941EXPORT_SYMBOL_GPL(sdhci_free_host);
4942
4943/*****************************************************************************\
4944 * *
4945 * Driver init/exit *
4946 * *
4947\*****************************************************************************/
4948
4949static int __init sdhci_drv_init(void)
4950{
4951 pr_info(DRIVER_NAME
4952 ": Secure Digital Host Controller Interface driver\n");
4953 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4954
4955 return 0;
4956}
4957
4958static void __exit sdhci_drv_exit(void)
4959{
4960}
4961
4962module_init(sdhci_drv_init);
4963module_exit(sdhci_drv_exit);
4964
4965module_param(debug_quirks, uint, 0444);
4966module_param(debug_quirks2, uint, 0444);
4967
4968MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4969MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4970MODULE_LICENSE("GPL");
4971
4972MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4973MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/swiotlb.h>
24#include <linux/regulator/consumer.h>
25#include <linux/pm_runtime.h>
26#include <linux/of.h>
27
28#include <linux/leds.h>
29
30#include <linux/mmc/mmc.h>
31#include <linux/mmc/host.h>
32#include <linux/mmc/card.h>
33#include <linux/mmc/sdio.h>
34#include <linux/mmc/slot-gpio.h>
35
36#include "sdhci.h"
37
38#define DRIVER_NAME "sdhci"
39
40#define DBG(f, x...) \
41 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
42
43#define SDHCI_DUMP(f, x...) \
44 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
45
46#define MAX_TUNING_LOOP 40
47
48static unsigned int debug_quirks = 0;
49static unsigned int debug_quirks2;
50
51static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
52
53static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
54
55void sdhci_dumpregs(struct sdhci_host *host)
56{
57 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
58
59 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
60 sdhci_readl(host, SDHCI_DMA_ADDRESS),
61 sdhci_readw(host, SDHCI_HOST_VERSION));
62 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
63 sdhci_readw(host, SDHCI_BLOCK_SIZE),
64 sdhci_readw(host, SDHCI_BLOCK_COUNT));
65 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
66 sdhci_readl(host, SDHCI_ARGUMENT),
67 sdhci_readw(host, SDHCI_TRANSFER_MODE));
68 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
69 sdhci_readl(host, SDHCI_PRESENT_STATE),
70 sdhci_readb(host, SDHCI_HOST_CONTROL));
71 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
72 sdhci_readb(host, SDHCI_POWER_CONTROL),
73 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
74 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
75 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
76 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
77 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
78 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
79 sdhci_readl(host, SDHCI_INT_STATUS));
80 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
81 sdhci_readl(host, SDHCI_INT_ENABLE),
82 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
83 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
84 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
85 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
86 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
87 sdhci_readl(host, SDHCI_CAPABILITIES),
88 sdhci_readl(host, SDHCI_CAPABILITIES_1));
89 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
90 sdhci_readw(host, SDHCI_COMMAND),
91 sdhci_readl(host, SDHCI_MAX_CURRENT));
92 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
93 sdhci_readl(host, SDHCI_RESPONSE),
94 sdhci_readl(host, SDHCI_RESPONSE + 4));
95 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
96 sdhci_readl(host, SDHCI_RESPONSE + 8),
97 sdhci_readl(host, SDHCI_RESPONSE + 12));
98 SDHCI_DUMP("Host ctl2: 0x%08x\n",
99 sdhci_readw(host, SDHCI_HOST_CONTROL2));
100
101 if (host->flags & SDHCI_USE_ADMA) {
102 if (host->flags & SDHCI_USE_64_BIT_DMA) {
103 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
104 sdhci_readl(host, SDHCI_ADMA_ERROR),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
106 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
107 } else {
108 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
109 sdhci_readl(host, SDHCI_ADMA_ERROR),
110 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
111 }
112 }
113
114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
116
117 SDHCI_DUMP("============================================\n");
118}
119EXPORT_SYMBOL_GPL(sdhci_dumpregs);
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
127static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
128{
129 u16 ctrl2;
130
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
132 if (ctrl2 & SDHCI_CTRL_V4_MODE)
133 return;
134
135 ctrl2 |= SDHCI_CTRL_V4_MODE;
136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
137}
138
139/*
140 * This can be called before sdhci_add_host() by Vendor's host controller
141 * driver to enable v4 mode if supported.
142 */
143void sdhci_enable_v4_mode(struct sdhci_host *host)
144{
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
147}
148EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
149
150static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
151{
152 return cmd->data || cmd->flags & MMC_RSP_BUSY;
153}
154
155static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
156{
157 u32 present;
158
159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
160 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
161 return;
162
163 if (enable) {
164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT;
166
167 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
168 SDHCI_INT_CARD_INSERT;
169 } else {
170 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
171 }
172
173 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
174 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
175}
176
177static void sdhci_enable_card_detection(struct sdhci_host *host)
178{
179 sdhci_set_card_detection(host, true);
180}
181
182static void sdhci_disable_card_detection(struct sdhci_host *host)
183{
184 sdhci_set_card_detection(host, false);
185}
186
187static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
188{
189 if (host->bus_on)
190 return;
191 host->bus_on = true;
192 pm_runtime_get_noresume(host->mmc->parent);
193}
194
195static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
196{
197 if (!host->bus_on)
198 return;
199 host->bus_on = false;
200 pm_runtime_put_noidle(host->mmc->parent);
201}
202
203void sdhci_reset(struct sdhci_host *host, u8 mask)
204{
205 ktime_t timeout;
206
207 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
208
209 if (mask & SDHCI_RESET_ALL) {
210 host->clock = 0;
211 /* Reset-all turns off SD Bus Power */
212 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
213 sdhci_runtime_pm_bus_off(host);
214 }
215
216 /* Wait max 100 ms */
217 timeout = ktime_add_ms(ktime_get(), 100);
218
219 /* hw clears the bit when it's done */
220 while (1) {
221 bool timedout = ktime_after(ktime_get(), timeout);
222
223 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
224 break;
225 if (timedout) {
226 pr_err("%s: Reset 0x%x never completed.\n",
227 mmc_hostname(host->mmc), (int)mask);
228 sdhci_dumpregs(host);
229 return;
230 }
231 udelay(10);
232 }
233}
234EXPORT_SYMBOL_GPL(sdhci_reset);
235
236static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
237{
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
239 struct mmc_host *mmc = host->mmc;
240
241 if (!mmc->ops->get_cd(mmc))
242 return;
243 }
244
245 host->ops->reset(host, mask);
246
247 if (mask & SDHCI_RESET_ALL) {
248 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
249 if (host->ops->enable_dma)
250 host->ops->enable_dma(host);
251 }
252
253 /* Resetting the controller clears many */
254 host->preset_enabled = false;
255 }
256}
257
258static void sdhci_set_default_irqs(struct sdhci_host *host)
259{
260 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
261 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
262 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
263 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
264 SDHCI_INT_RESPONSE;
265
266 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
267 host->tuning_mode == SDHCI_TUNING_MODE_3)
268 host->ier |= SDHCI_INT_RETUNE;
269
270 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
271 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
272}
273
274static void sdhci_config_dma(struct sdhci_host *host)
275{
276 u8 ctrl;
277 u16 ctrl2;
278
279 if (host->version < SDHCI_SPEC_200)
280 return;
281
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
283
284 /*
285 * Always adjust the DMA selection as some controllers
286 * (e.g. JMicron) can't do PIO properly when the selection
287 * is ADMA.
288 */
289 ctrl &= ~SDHCI_CTRL_DMA_MASK;
290 if (!(host->flags & SDHCI_REQ_USE_DMA))
291 goto out;
292
293 /* Note if DMA Select is zero then SDMA is selected */
294 if (host->flags & SDHCI_USE_ADMA)
295 ctrl |= SDHCI_CTRL_ADMA32;
296
297 if (host->flags & SDHCI_USE_64_BIT_DMA) {
298 /*
299 * If v4 mode, all supported DMA can be 64-bit addressing if
300 * controller supports 64-bit system address, otherwise only
301 * ADMA can support 64-bit addressing.
302 */
303 if (host->v4_mode) {
304 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
305 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
306 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
307 } else if (host->flags & SDHCI_USE_ADMA) {
308 /*
309 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
310 * set SDHCI_CTRL_ADMA64.
311 */
312 ctrl |= SDHCI_CTRL_ADMA64;
313 }
314 }
315
316out:
317 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
318}
319
320static void sdhci_init(struct sdhci_host *host, int soft)
321{
322 struct mmc_host *mmc = host->mmc;
323 unsigned long flags;
324
325 if (soft)
326 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
327 else
328 sdhci_do_reset(host, SDHCI_RESET_ALL);
329
330 if (host->v4_mode)
331 sdhci_do_enable_v4_mode(host);
332
333 spin_lock_irqsave(&host->lock, flags);
334 sdhci_set_default_irqs(host);
335 spin_unlock_irqrestore(&host->lock, flags);
336
337 host->cqe_on = false;
338
339 if (soft) {
340 /* force clock reconfiguration */
341 host->clock = 0;
342 mmc->ops->set_ios(mmc, &mmc->ios);
343 }
344}
345
346static void sdhci_reinit(struct sdhci_host *host)
347{
348 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
349
350 sdhci_init(host, 0);
351 sdhci_enable_card_detection(host);
352
353 /*
354 * A change to the card detect bits indicates a change in present state,
355 * refer sdhci_set_card_detection(). A card detect interrupt might have
356 * been missed while the host controller was being reset, so trigger a
357 * rescan to check.
358 */
359 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
360 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
361}
362
363static void __sdhci_led_activate(struct sdhci_host *host)
364{
365 u8 ctrl;
366
367 if (host->quirks & SDHCI_QUIRK_NO_LED)
368 return;
369
370 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
371 ctrl |= SDHCI_CTRL_LED;
372 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
373}
374
375static void __sdhci_led_deactivate(struct sdhci_host *host)
376{
377 u8 ctrl;
378
379 if (host->quirks & SDHCI_QUIRK_NO_LED)
380 return;
381
382 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
383 ctrl &= ~SDHCI_CTRL_LED;
384 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
385}
386
387#if IS_REACHABLE(CONFIG_LEDS_CLASS)
388static void sdhci_led_control(struct led_classdev *led,
389 enum led_brightness brightness)
390{
391 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
392 unsigned long flags;
393
394 spin_lock_irqsave(&host->lock, flags);
395
396 if (host->runtime_suspended)
397 goto out;
398
399 if (brightness == LED_OFF)
400 __sdhci_led_deactivate(host);
401 else
402 __sdhci_led_activate(host);
403out:
404 spin_unlock_irqrestore(&host->lock, flags);
405}
406
407static int sdhci_led_register(struct sdhci_host *host)
408{
409 struct mmc_host *mmc = host->mmc;
410
411 if (host->quirks & SDHCI_QUIRK_NO_LED)
412 return 0;
413
414 snprintf(host->led_name, sizeof(host->led_name),
415 "%s::", mmc_hostname(mmc));
416
417 host->led.name = host->led_name;
418 host->led.brightness = LED_OFF;
419 host->led.default_trigger = mmc_hostname(mmc);
420 host->led.brightness_set = sdhci_led_control;
421
422 return led_classdev_register(mmc_dev(mmc), &host->led);
423}
424
425static void sdhci_led_unregister(struct sdhci_host *host)
426{
427 if (host->quirks & SDHCI_QUIRK_NO_LED)
428 return;
429
430 led_classdev_unregister(&host->led);
431}
432
433static inline void sdhci_led_activate(struct sdhci_host *host)
434{
435}
436
437static inline void sdhci_led_deactivate(struct sdhci_host *host)
438{
439}
440
441#else
442
443static inline int sdhci_led_register(struct sdhci_host *host)
444{
445 return 0;
446}
447
448static inline void sdhci_led_unregister(struct sdhci_host *host)
449{
450}
451
452static inline void sdhci_led_activate(struct sdhci_host *host)
453{
454 __sdhci_led_activate(host);
455}
456
457static inline void sdhci_led_deactivate(struct sdhci_host *host)
458{
459 __sdhci_led_deactivate(host);
460}
461
462#endif
463
464static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
465 unsigned long timeout)
466{
467 if (sdhci_data_line_cmd(mrq->cmd))
468 mod_timer(&host->data_timer, timeout);
469 else
470 mod_timer(&host->timer, timeout);
471}
472
473static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
474{
475 if (sdhci_data_line_cmd(mrq->cmd))
476 del_timer(&host->data_timer);
477 else
478 del_timer(&host->timer);
479}
480
481static inline bool sdhci_has_requests(struct sdhci_host *host)
482{
483 return host->cmd || host->data_cmd;
484}
485
486/*****************************************************************************\
487 * *
488 * Core functions *
489 * *
490\*****************************************************************************/
491
492static void sdhci_read_block_pio(struct sdhci_host *host)
493{
494 unsigned long flags;
495 size_t blksize, len, chunk;
496 u32 scratch;
497 u8 *buf;
498
499 DBG("PIO reading\n");
500
501 blksize = host->data->blksz;
502 chunk = 0;
503
504 local_irq_save(flags);
505
506 while (blksize) {
507 BUG_ON(!sg_miter_next(&host->sg_miter));
508
509 len = min(host->sg_miter.length, blksize);
510
511 blksize -= len;
512 host->sg_miter.consumed = len;
513
514 buf = host->sg_miter.addr;
515
516 while (len) {
517 if (chunk == 0) {
518 scratch = sdhci_readl(host, SDHCI_BUFFER);
519 chunk = 4;
520 }
521
522 *buf = scratch & 0xFF;
523
524 buf++;
525 scratch >>= 8;
526 chunk--;
527 len--;
528 }
529 }
530
531 sg_miter_stop(&host->sg_miter);
532
533 local_irq_restore(flags);
534}
535
536static void sdhci_write_block_pio(struct sdhci_host *host)
537{
538 unsigned long flags;
539 size_t blksize, len, chunk;
540 u32 scratch;
541 u8 *buf;
542
543 DBG("PIO writing\n");
544
545 blksize = host->data->blksz;
546 chunk = 0;
547 scratch = 0;
548
549 local_irq_save(flags);
550
551 while (blksize) {
552 BUG_ON(!sg_miter_next(&host->sg_miter));
553
554 len = min(host->sg_miter.length, blksize);
555
556 blksize -= len;
557 host->sg_miter.consumed = len;
558
559 buf = host->sg_miter.addr;
560
561 while (len) {
562 scratch |= (u32)*buf << (chunk * 8);
563
564 buf++;
565 chunk++;
566 len--;
567
568 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
569 sdhci_writel(host, scratch, SDHCI_BUFFER);
570 chunk = 0;
571 scratch = 0;
572 }
573 }
574 }
575
576 sg_miter_stop(&host->sg_miter);
577
578 local_irq_restore(flags);
579}
580
581static void sdhci_transfer_pio(struct sdhci_host *host)
582{
583 u32 mask;
584
585 if (host->blocks == 0)
586 return;
587
588 if (host->data->flags & MMC_DATA_READ)
589 mask = SDHCI_DATA_AVAILABLE;
590 else
591 mask = SDHCI_SPACE_AVAILABLE;
592
593 /*
594 * Some controllers (JMicron JMB38x) mess up the buffer bits
595 * for transfers < 4 bytes. As long as it is just one block,
596 * we can ignore the bits.
597 */
598 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
599 (host->data->blocks == 1))
600 mask = ~0;
601
602 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
603 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
604 udelay(100);
605
606 if (host->data->flags & MMC_DATA_READ)
607 sdhci_read_block_pio(host);
608 else
609 sdhci_write_block_pio(host);
610
611 host->blocks--;
612 if (host->blocks == 0)
613 break;
614 }
615
616 DBG("PIO transfer complete.\n");
617}
618
619static int sdhci_pre_dma_transfer(struct sdhci_host *host,
620 struct mmc_data *data, int cookie)
621{
622 int sg_count;
623
624 /*
625 * If the data buffers are already mapped, return the previous
626 * dma_map_sg() result.
627 */
628 if (data->host_cookie == COOKIE_PRE_MAPPED)
629 return data->sg_count;
630
631 /* Bounce write requests to the bounce buffer */
632 if (host->bounce_buffer) {
633 unsigned int length = data->blksz * data->blocks;
634
635 if (length > host->bounce_buffer_size) {
636 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
637 mmc_hostname(host->mmc), length,
638 host->bounce_buffer_size);
639 return -EIO;
640 }
641 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
642 /* Copy the data to the bounce buffer */
643 if (host->ops->copy_to_bounce_buffer) {
644 host->ops->copy_to_bounce_buffer(host,
645 data, length);
646 } else {
647 sg_copy_to_buffer(data->sg, data->sg_len,
648 host->bounce_buffer, length);
649 }
650 }
651 /* Switch ownership to the DMA */
652 dma_sync_single_for_device(host->mmc->parent,
653 host->bounce_addr,
654 host->bounce_buffer_size,
655 mmc_get_dma_dir(data));
656 /* Just a dummy value */
657 sg_count = 1;
658 } else {
659 /* Just access the data directly from memory */
660 sg_count = dma_map_sg(mmc_dev(host->mmc),
661 data->sg, data->sg_len,
662 mmc_get_dma_dir(data));
663 }
664
665 if (sg_count == 0)
666 return -ENOSPC;
667
668 data->sg_count = sg_count;
669 data->host_cookie = cookie;
670
671 return sg_count;
672}
673
674static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
675{
676 local_irq_save(*flags);
677 return kmap_atomic(sg_page(sg)) + sg->offset;
678}
679
680static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
681{
682 kunmap_atomic(buffer);
683 local_irq_restore(*flags);
684}
685
686void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
687 dma_addr_t addr, int len, unsigned int cmd)
688{
689 struct sdhci_adma2_64_desc *dma_desc = *desc;
690
691 /* 32-bit and 64-bit descriptors have these members in same position */
692 dma_desc->cmd = cpu_to_le16(cmd);
693 dma_desc->len = cpu_to_le16(len);
694 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
695
696 if (host->flags & SDHCI_USE_64_BIT_DMA)
697 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
698
699 *desc += host->desc_sz;
700}
701EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
702
703static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
704 void **desc, dma_addr_t addr,
705 int len, unsigned int cmd)
706{
707 if (host->ops->adma_write_desc)
708 host->ops->adma_write_desc(host, desc, addr, len, cmd);
709 else
710 sdhci_adma_write_desc(host, desc, addr, len, cmd);
711}
712
713static void sdhci_adma_mark_end(void *desc)
714{
715 struct sdhci_adma2_64_desc *dma_desc = desc;
716
717 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
718 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
719}
720
721static void sdhci_adma_table_pre(struct sdhci_host *host,
722 struct mmc_data *data, int sg_count)
723{
724 struct scatterlist *sg;
725 unsigned long flags;
726 dma_addr_t addr, align_addr;
727 void *desc, *align;
728 char *buffer;
729 int len, offset, i;
730
731 /*
732 * The spec does not specify endianness of descriptor table.
733 * We currently guess that it is LE.
734 */
735
736 host->sg_count = sg_count;
737
738 desc = host->adma_table;
739 align = host->align_buffer;
740
741 align_addr = host->align_addr;
742
743 for_each_sg(data->sg, sg, host->sg_count, i) {
744 addr = sg_dma_address(sg);
745 len = sg_dma_len(sg);
746
747 /*
748 * The SDHCI specification states that ADMA addresses must
749 * be 32-bit aligned. If they aren't, then we use a bounce
750 * buffer for the (up to three) bytes that screw up the
751 * alignment.
752 */
753 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
754 SDHCI_ADMA2_MASK;
755 if (offset) {
756 if (data->flags & MMC_DATA_WRITE) {
757 buffer = sdhci_kmap_atomic(sg, &flags);
758 memcpy(align, buffer, offset);
759 sdhci_kunmap_atomic(buffer, &flags);
760 }
761
762 /* tran, valid */
763 __sdhci_adma_write_desc(host, &desc, align_addr,
764 offset, ADMA2_TRAN_VALID);
765
766 BUG_ON(offset > 65536);
767
768 align += SDHCI_ADMA2_ALIGN;
769 align_addr += SDHCI_ADMA2_ALIGN;
770
771 addr += offset;
772 len -= offset;
773 }
774
775 BUG_ON(len > 65536);
776
777 /* tran, valid */
778 if (len)
779 __sdhci_adma_write_desc(host, &desc, addr, len,
780 ADMA2_TRAN_VALID);
781
782 /*
783 * If this triggers then we have a calculation bug
784 * somewhere. :/
785 */
786 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
787 }
788
789 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
790 /* Mark the last descriptor as the terminating descriptor */
791 if (desc != host->adma_table) {
792 desc -= host->desc_sz;
793 sdhci_adma_mark_end(desc);
794 }
795 } else {
796 /* Add a terminating entry - nop, end, valid */
797 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
798 }
799}
800
801static void sdhci_adma_table_post(struct sdhci_host *host,
802 struct mmc_data *data)
803{
804 struct scatterlist *sg;
805 int i, size;
806 void *align;
807 char *buffer;
808 unsigned long flags;
809
810 if (data->flags & MMC_DATA_READ) {
811 bool has_unaligned = false;
812
813 /* Do a quick scan of the SG list for any unaligned mappings */
814 for_each_sg(data->sg, sg, host->sg_count, i)
815 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
816 has_unaligned = true;
817 break;
818 }
819
820 if (has_unaligned) {
821 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
822 data->sg_len, DMA_FROM_DEVICE);
823
824 align = host->align_buffer;
825
826 for_each_sg(data->sg, sg, host->sg_count, i) {
827 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
828 size = SDHCI_ADMA2_ALIGN -
829 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
830
831 buffer = sdhci_kmap_atomic(sg, &flags);
832 memcpy(buffer, align, size);
833 sdhci_kunmap_atomic(buffer, &flags);
834
835 align += SDHCI_ADMA2_ALIGN;
836 }
837 }
838 }
839 }
840}
841
842static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
843{
844 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
845 if (host->flags & SDHCI_USE_64_BIT_DMA)
846 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
847}
848
849static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
850{
851 if (host->bounce_buffer)
852 return host->bounce_addr;
853 else
854 return sg_dma_address(host->data->sg);
855}
856
857static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
858{
859 if (host->v4_mode)
860 sdhci_set_adma_addr(host, addr);
861 else
862 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
863}
864
865static unsigned int sdhci_target_timeout(struct sdhci_host *host,
866 struct mmc_command *cmd,
867 struct mmc_data *data)
868{
869 unsigned int target_timeout;
870
871 /* timeout in us */
872 if (!data) {
873 target_timeout = cmd->busy_timeout * 1000;
874 } else {
875 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
876 if (host->clock && data->timeout_clks) {
877 unsigned long long val;
878
879 /*
880 * data->timeout_clks is in units of clock cycles.
881 * host->clock is in Hz. target_timeout is in us.
882 * Hence, us = 1000000 * cycles / Hz. Round up.
883 */
884 val = 1000000ULL * data->timeout_clks;
885 if (do_div(val, host->clock))
886 target_timeout++;
887 target_timeout += val;
888 }
889 }
890
891 return target_timeout;
892}
893
894static void sdhci_calc_sw_timeout(struct sdhci_host *host,
895 struct mmc_command *cmd)
896{
897 struct mmc_data *data = cmd->data;
898 struct mmc_host *mmc = host->mmc;
899 struct mmc_ios *ios = &mmc->ios;
900 unsigned char bus_width = 1 << ios->bus_width;
901 unsigned int blksz;
902 unsigned int freq;
903 u64 target_timeout;
904 u64 transfer_time;
905
906 target_timeout = sdhci_target_timeout(host, cmd, data);
907 target_timeout *= NSEC_PER_USEC;
908
909 if (data) {
910 blksz = data->blksz;
911 freq = host->mmc->actual_clock ? : host->clock;
912 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
913 do_div(transfer_time, freq);
914 /* multiply by '2' to account for any unknowns */
915 transfer_time = transfer_time * 2;
916 /* calculate timeout for the entire data */
917 host->data_timeout = data->blocks * target_timeout +
918 transfer_time;
919 } else {
920 host->data_timeout = target_timeout;
921 }
922
923 if (host->data_timeout)
924 host->data_timeout += MMC_CMD_TRANSFER_TIME;
925}
926
927static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
928 bool *too_big)
929{
930 u8 count;
931 struct mmc_data *data;
932 unsigned target_timeout, current_timeout;
933
934 *too_big = true;
935
936 /*
937 * If the host controller provides us with an incorrect timeout
938 * value, just skip the check and use 0xE. The hardware may take
939 * longer to time out, but that's much better than having a too-short
940 * timeout value.
941 */
942 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
943 return 0xE;
944
945 /* Unspecified command, asume max */
946 if (cmd == NULL)
947 return 0xE;
948
949 data = cmd->data;
950 /* Unspecified timeout, assume max */
951 if (!data && !cmd->busy_timeout)
952 return 0xE;
953
954 /* timeout in us */
955 target_timeout = sdhci_target_timeout(host, cmd, data);
956
957 /*
958 * Figure out needed cycles.
959 * We do this in steps in order to fit inside a 32 bit int.
960 * The first step is the minimum timeout, which will have a
961 * minimum resolution of 6 bits:
962 * (1) 2^13*1000 > 2^22,
963 * (2) host->timeout_clk < 2^16
964 * =>
965 * (1) / (2) > 2^6
966 */
967 count = 0;
968 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
969 while (current_timeout < target_timeout) {
970 count++;
971 current_timeout <<= 1;
972 if (count >= 0xF)
973 break;
974 }
975
976 if (count >= 0xF) {
977 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
978 DBG("Too large timeout 0x%x requested for CMD%d!\n",
979 count, cmd->opcode);
980 count = 0xE;
981 } else {
982 *too_big = false;
983 }
984
985 return count;
986}
987
988static void sdhci_set_transfer_irqs(struct sdhci_host *host)
989{
990 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
991 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
992
993 if (host->flags & SDHCI_REQ_USE_DMA)
994 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
995 else
996 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
997
998 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
999 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1000 else
1001 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1002
1003 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1004 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1005}
1006
1007void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1008{
1009 if (enable)
1010 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1011 else
1012 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1013 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1014 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1015}
1016EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1017
1018void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1019{
1020 bool too_big = false;
1021 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1022
1023 if (too_big &&
1024 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1025 sdhci_calc_sw_timeout(host, cmd);
1026 sdhci_set_data_timeout_irq(host, false);
1027 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1028 sdhci_set_data_timeout_irq(host, true);
1029 }
1030
1031 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1032}
1033EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1034
1035static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1036{
1037 if (host->ops->set_timeout)
1038 host->ops->set_timeout(host, cmd);
1039 else
1040 __sdhci_set_timeout(host, cmd);
1041}
1042
1043static void sdhci_initialize_data(struct sdhci_host *host,
1044 struct mmc_data *data)
1045{
1046 WARN_ON(host->data);
1047
1048 /* Sanity checks */
1049 BUG_ON(data->blksz * data->blocks > 524288);
1050 BUG_ON(data->blksz > host->mmc->max_blk_size);
1051 BUG_ON(data->blocks > 65535);
1052
1053 host->data = data;
1054 host->data_early = 0;
1055 host->data->bytes_xfered = 0;
1056}
1057
1058static inline void sdhci_set_block_info(struct sdhci_host *host,
1059 struct mmc_data *data)
1060{
1061 /* Set the DMA boundary value and block size */
1062 sdhci_writew(host,
1063 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1064 SDHCI_BLOCK_SIZE);
1065 /*
1066 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1067 * can be supported, in that case 16-bit block count register must be 0.
1068 */
1069 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1070 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1071 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1072 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1073 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1074 } else {
1075 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1076 }
1077}
1078
1079static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1080{
1081 struct mmc_data *data = cmd->data;
1082
1083 sdhci_initialize_data(host, data);
1084
1085 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1086 struct scatterlist *sg;
1087 unsigned int length_mask, offset_mask;
1088 int i;
1089
1090 host->flags |= SDHCI_REQ_USE_DMA;
1091
1092 /*
1093 * FIXME: This doesn't account for merging when mapping the
1094 * scatterlist.
1095 *
1096 * The assumption here being that alignment and lengths are
1097 * the same after DMA mapping to device address space.
1098 */
1099 length_mask = 0;
1100 offset_mask = 0;
1101 if (host->flags & SDHCI_USE_ADMA) {
1102 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1103 length_mask = 3;
1104 /*
1105 * As we use up to 3 byte chunks to work
1106 * around alignment problems, we need to
1107 * check the offset as well.
1108 */
1109 offset_mask = 3;
1110 }
1111 } else {
1112 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1113 length_mask = 3;
1114 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1115 offset_mask = 3;
1116 }
1117
1118 if (unlikely(length_mask | offset_mask)) {
1119 for_each_sg(data->sg, sg, data->sg_len, i) {
1120 if (sg->length & length_mask) {
1121 DBG("Reverting to PIO because of transfer size (%d)\n",
1122 sg->length);
1123 host->flags &= ~SDHCI_REQ_USE_DMA;
1124 break;
1125 }
1126 if (sg->offset & offset_mask) {
1127 DBG("Reverting to PIO because of bad alignment\n");
1128 host->flags &= ~SDHCI_REQ_USE_DMA;
1129 break;
1130 }
1131 }
1132 }
1133 }
1134
1135 if (host->flags & SDHCI_REQ_USE_DMA) {
1136 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1137
1138 if (sg_cnt <= 0) {
1139 /*
1140 * This only happens when someone fed
1141 * us an invalid request.
1142 */
1143 WARN_ON(1);
1144 host->flags &= ~SDHCI_REQ_USE_DMA;
1145 } else if (host->flags & SDHCI_USE_ADMA) {
1146 sdhci_adma_table_pre(host, data, sg_cnt);
1147 sdhci_set_adma_addr(host, host->adma_addr);
1148 } else {
1149 WARN_ON(sg_cnt != 1);
1150 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1151 }
1152 }
1153
1154 sdhci_config_dma(host);
1155
1156 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1157 int flags;
1158
1159 flags = SG_MITER_ATOMIC;
1160 if (host->data->flags & MMC_DATA_READ)
1161 flags |= SG_MITER_TO_SG;
1162 else
1163 flags |= SG_MITER_FROM_SG;
1164 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1165 host->blocks = data->blocks;
1166 }
1167
1168 sdhci_set_transfer_irqs(host);
1169
1170 sdhci_set_block_info(host, data);
1171}
1172
1173#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1174
1175static int sdhci_external_dma_init(struct sdhci_host *host)
1176{
1177 int ret = 0;
1178 struct mmc_host *mmc = host->mmc;
1179
1180 host->tx_chan = dma_request_chan(mmc->parent, "tx");
1181 if (IS_ERR(host->tx_chan)) {
1182 ret = PTR_ERR(host->tx_chan);
1183 if (ret != -EPROBE_DEFER)
1184 pr_warn("Failed to request TX DMA channel.\n");
1185 host->tx_chan = NULL;
1186 return ret;
1187 }
1188
1189 host->rx_chan = dma_request_chan(mmc->parent, "rx");
1190 if (IS_ERR(host->rx_chan)) {
1191 if (host->tx_chan) {
1192 dma_release_channel(host->tx_chan);
1193 host->tx_chan = NULL;
1194 }
1195
1196 ret = PTR_ERR(host->rx_chan);
1197 if (ret != -EPROBE_DEFER)
1198 pr_warn("Failed to request RX DMA channel.\n");
1199 host->rx_chan = NULL;
1200 }
1201
1202 return ret;
1203}
1204
1205static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1206 struct mmc_data *data)
1207{
1208 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1209}
1210
1211static int sdhci_external_dma_setup(struct sdhci_host *host,
1212 struct mmc_command *cmd)
1213{
1214 int ret, i;
1215 enum dma_transfer_direction dir;
1216 struct dma_async_tx_descriptor *desc;
1217 struct mmc_data *data = cmd->data;
1218 struct dma_chan *chan;
1219 struct dma_slave_config cfg;
1220 dma_cookie_t cookie;
1221 int sg_cnt;
1222
1223 if (!host->mapbase)
1224 return -EINVAL;
1225
1226 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1227 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1228 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1229 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1230 cfg.src_maxburst = data->blksz / 4;
1231 cfg.dst_maxburst = data->blksz / 4;
1232
1233 /* Sanity check: all the SG entries must be aligned by block size. */
1234 for (i = 0; i < data->sg_len; i++) {
1235 if ((data->sg + i)->length % data->blksz)
1236 return -EINVAL;
1237 }
1238
1239 chan = sdhci_external_dma_channel(host, data);
1240
1241 ret = dmaengine_slave_config(chan, &cfg);
1242 if (ret)
1243 return ret;
1244
1245 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1246 if (sg_cnt <= 0)
1247 return -EINVAL;
1248
1249 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1250 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1251 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1252 if (!desc)
1253 return -EINVAL;
1254
1255 desc->callback = NULL;
1256 desc->callback_param = NULL;
1257
1258 cookie = dmaengine_submit(desc);
1259 if (dma_submit_error(cookie))
1260 ret = cookie;
1261
1262 return ret;
1263}
1264
1265static void sdhci_external_dma_release(struct sdhci_host *host)
1266{
1267 if (host->tx_chan) {
1268 dma_release_channel(host->tx_chan);
1269 host->tx_chan = NULL;
1270 }
1271
1272 if (host->rx_chan) {
1273 dma_release_channel(host->rx_chan);
1274 host->rx_chan = NULL;
1275 }
1276
1277 sdhci_switch_external_dma(host, false);
1278}
1279
1280static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1281 struct mmc_command *cmd)
1282{
1283 struct mmc_data *data = cmd->data;
1284
1285 sdhci_initialize_data(host, data);
1286
1287 host->flags |= SDHCI_REQ_USE_DMA;
1288 sdhci_set_transfer_irqs(host);
1289
1290 sdhci_set_block_info(host, data);
1291}
1292
1293static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1294 struct mmc_command *cmd)
1295{
1296 if (!sdhci_external_dma_setup(host, cmd)) {
1297 __sdhci_external_dma_prepare_data(host, cmd);
1298 } else {
1299 sdhci_external_dma_release(host);
1300 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1301 mmc_hostname(host->mmc));
1302 sdhci_prepare_data(host, cmd);
1303 }
1304}
1305
1306static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1307 struct mmc_command *cmd)
1308{
1309 struct dma_chan *chan;
1310
1311 if (!cmd->data)
1312 return;
1313
1314 chan = sdhci_external_dma_channel(host, cmd->data);
1315 if (chan)
1316 dma_async_issue_pending(chan);
1317}
1318
1319#else
1320
1321static inline int sdhci_external_dma_init(struct sdhci_host *host)
1322{
1323 return -EOPNOTSUPP;
1324}
1325
1326static inline void sdhci_external_dma_release(struct sdhci_host *host)
1327{
1328}
1329
1330static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1331 struct mmc_command *cmd)
1332{
1333 /* This should never happen */
1334 WARN_ON_ONCE(1);
1335}
1336
1337static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1338 struct mmc_command *cmd)
1339{
1340}
1341
1342static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1343 struct mmc_data *data)
1344{
1345 return NULL;
1346}
1347
1348#endif
1349
1350void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1351{
1352 host->use_external_dma = en;
1353}
1354EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1355
1356static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1357 struct mmc_request *mrq)
1358{
1359 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1360 !mrq->cap_cmd_during_tfr;
1361}
1362
1363static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1364 struct mmc_request *mrq)
1365{
1366 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1367}
1368
1369static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1370 struct mmc_request *mrq)
1371{
1372 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1373}
1374
1375static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1376 struct mmc_command *cmd,
1377 u16 *mode)
1378{
1379 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1380 (cmd->opcode != SD_IO_RW_EXTENDED);
1381 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1382 u16 ctrl2;
1383
1384 /*
1385 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1386 * Select' is recommended rather than use of 'Auto CMD12
1387 * Enable' or 'Auto CMD23 Enable'.
1388 */
1389 if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
1390 *mode |= SDHCI_TRNS_AUTO_SEL;
1391
1392 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1393 if (use_cmd23)
1394 ctrl2 |= SDHCI_CMD23_ENABLE;
1395 else
1396 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1397 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1398
1399 return;
1400 }
1401
1402 /*
1403 * If we are sending CMD23, CMD12 never gets sent
1404 * on successful completion (so no Auto-CMD12).
1405 */
1406 if (use_cmd12)
1407 *mode |= SDHCI_TRNS_AUTO_CMD12;
1408 else if (use_cmd23)
1409 *mode |= SDHCI_TRNS_AUTO_CMD23;
1410}
1411
1412static void sdhci_set_transfer_mode(struct sdhci_host *host,
1413 struct mmc_command *cmd)
1414{
1415 u16 mode = 0;
1416 struct mmc_data *data = cmd->data;
1417
1418 if (data == NULL) {
1419 if (host->quirks2 &
1420 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1421 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1422 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1423 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1424 } else {
1425 /* clear Auto CMD settings for no data CMDs */
1426 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1427 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1428 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1429 }
1430 return;
1431 }
1432
1433 WARN_ON(!host->data);
1434
1435 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1436 mode = SDHCI_TRNS_BLK_CNT_EN;
1437
1438 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1439 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1440 sdhci_auto_cmd_select(host, cmd, &mode);
1441 if (sdhci_auto_cmd23(host, cmd->mrq))
1442 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1443 }
1444
1445 if (data->flags & MMC_DATA_READ)
1446 mode |= SDHCI_TRNS_READ;
1447 if (host->flags & SDHCI_REQ_USE_DMA)
1448 mode |= SDHCI_TRNS_DMA;
1449
1450 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1451}
1452
1453static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1454{
1455 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1456 ((mrq->cmd && mrq->cmd->error) ||
1457 (mrq->sbc && mrq->sbc->error) ||
1458 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1459 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1460}
1461
1462static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1463{
1464 int i;
1465
1466 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1467 if (host->mrqs_done[i] == mrq) {
1468 WARN_ON(1);
1469 return;
1470 }
1471 }
1472
1473 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1474 if (!host->mrqs_done[i]) {
1475 host->mrqs_done[i] = mrq;
1476 break;
1477 }
1478 }
1479
1480 WARN_ON(i >= SDHCI_MAX_MRQS);
1481}
1482
1483static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1484{
1485 if (host->cmd && host->cmd->mrq == mrq)
1486 host->cmd = NULL;
1487
1488 if (host->data_cmd && host->data_cmd->mrq == mrq)
1489 host->data_cmd = NULL;
1490
1491 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1492 host->deferred_cmd = NULL;
1493
1494 if (host->data && host->data->mrq == mrq)
1495 host->data = NULL;
1496
1497 if (sdhci_needs_reset(host, mrq))
1498 host->pending_reset = true;
1499
1500 sdhci_set_mrq_done(host, mrq);
1501
1502 sdhci_del_timer(host, mrq);
1503
1504 if (!sdhci_has_requests(host))
1505 sdhci_led_deactivate(host);
1506}
1507
1508static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1509{
1510 __sdhci_finish_mrq(host, mrq);
1511
1512 queue_work(host->complete_wq, &host->complete_work);
1513}
1514
1515static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1516{
1517 struct mmc_command *data_cmd = host->data_cmd;
1518 struct mmc_data *data = host->data;
1519
1520 host->data = NULL;
1521 host->data_cmd = NULL;
1522
1523 /*
1524 * The controller needs a reset of internal state machines upon error
1525 * conditions.
1526 */
1527 if (data->error) {
1528 if (!host->cmd || host->cmd == data_cmd)
1529 sdhci_do_reset(host, SDHCI_RESET_CMD);
1530 sdhci_do_reset(host, SDHCI_RESET_DATA);
1531 }
1532
1533 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1534 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1535 sdhci_adma_table_post(host, data);
1536
1537 /*
1538 * The specification states that the block count register must
1539 * be updated, but it does not specify at what point in the
1540 * data flow. That makes the register entirely useless to read
1541 * back so we have to assume that nothing made it to the card
1542 * in the event of an error.
1543 */
1544 if (data->error)
1545 data->bytes_xfered = 0;
1546 else
1547 data->bytes_xfered = data->blksz * data->blocks;
1548
1549 /*
1550 * Need to send CMD12 if -
1551 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1552 * b) error in multiblock transfer
1553 */
1554 if (data->stop &&
1555 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1556 data->error)) {
1557 /*
1558 * 'cap_cmd_during_tfr' request must not use the command line
1559 * after mmc_command_done() has been called. It is upper layer's
1560 * responsibility to send the stop command if required.
1561 */
1562 if (data->mrq->cap_cmd_during_tfr) {
1563 __sdhci_finish_mrq(host, data->mrq);
1564 } else {
1565 /* Avoid triggering warning in sdhci_send_command() */
1566 host->cmd = NULL;
1567 if (!sdhci_send_command(host, data->stop)) {
1568 if (sw_data_timeout) {
1569 /*
1570 * This is anyway a sw data timeout, so
1571 * give up now.
1572 */
1573 data->stop->error = -EIO;
1574 __sdhci_finish_mrq(host, data->mrq);
1575 } else {
1576 WARN_ON(host->deferred_cmd);
1577 host->deferred_cmd = data->stop;
1578 }
1579 }
1580 }
1581 } else {
1582 __sdhci_finish_mrq(host, data->mrq);
1583 }
1584}
1585
1586static void sdhci_finish_data(struct sdhci_host *host)
1587{
1588 __sdhci_finish_data(host, false);
1589}
1590
1591static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1592{
1593 int flags;
1594 u32 mask;
1595 unsigned long timeout;
1596
1597 WARN_ON(host->cmd);
1598
1599 /* Initially, a command has no error */
1600 cmd->error = 0;
1601
1602 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1603 cmd->opcode == MMC_STOP_TRANSMISSION)
1604 cmd->flags |= MMC_RSP_BUSY;
1605
1606 mask = SDHCI_CMD_INHIBIT;
1607 if (sdhci_data_line_cmd(cmd))
1608 mask |= SDHCI_DATA_INHIBIT;
1609
1610 /* We shouldn't wait for data inihibit for stop commands, even
1611 though they might use busy signaling */
1612 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1613 mask &= ~SDHCI_DATA_INHIBIT;
1614
1615 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1616 return false;
1617
1618 host->cmd = cmd;
1619 host->data_timeout = 0;
1620 if (sdhci_data_line_cmd(cmd)) {
1621 WARN_ON(host->data_cmd);
1622 host->data_cmd = cmd;
1623 sdhci_set_timeout(host, cmd);
1624 }
1625
1626 if (cmd->data) {
1627 if (host->use_external_dma)
1628 sdhci_external_dma_prepare_data(host, cmd);
1629 else
1630 sdhci_prepare_data(host, cmd);
1631 }
1632
1633 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1634
1635 sdhci_set_transfer_mode(host, cmd);
1636
1637 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1638 WARN_ONCE(1, "Unsupported response type!\n");
1639 /*
1640 * This does not happen in practice because 136-bit response
1641 * commands never have busy waiting, so rather than complicate
1642 * the error path, just remove busy waiting and continue.
1643 */
1644 cmd->flags &= ~MMC_RSP_BUSY;
1645 }
1646
1647 if (!(cmd->flags & MMC_RSP_PRESENT))
1648 flags = SDHCI_CMD_RESP_NONE;
1649 else if (cmd->flags & MMC_RSP_136)
1650 flags = SDHCI_CMD_RESP_LONG;
1651 else if (cmd->flags & MMC_RSP_BUSY)
1652 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1653 else
1654 flags = SDHCI_CMD_RESP_SHORT;
1655
1656 if (cmd->flags & MMC_RSP_CRC)
1657 flags |= SDHCI_CMD_CRC;
1658 if (cmd->flags & MMC_RSP_OPCODE)
1659 flags |= SDHCI_CMD_INDEX;
1660
1661 /* CMD19 is special in that the Data Present Select should be set */
1662 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1663 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1664 flags |= SDHCI_CMD_DATA;
1665
1666 timeout = jiffies;
1667 if (host->data_timeout)
1668 timeout += nsecs_to_jiffies(host->data_timeout);
1669 else if (!cmd->data && cmd->busy_timeout > 9000)
1670 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1671 else
1672 timeout += 10 * HZ;
1673 sdhci_mod_timer(host, cmd->mrq, timeout);
1674
1675 if (host->use_external_dma)
1676 sdhci_external_dma_pre_transfer(host, cmd);
1677
1678 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1679
1680 return true;
1681}
1682
1683static bool sdhci_present_error(struct sdhci_host *host,
1684 struct mmc_command *cmd, bool present)
1685{
1686 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1687 cmd->error = -ENOMEDIUM;
1688 return true;
1689 }
1690
1691 return false;
1692}
1693
1694static bool sdhci_send_command_retry(struct sdhci_host *host,
1695 struct mmc_command *cmd,
1696 unsigned long flags)
1697 __releases(host->lock)
1698 __acquires(host->lock)
1699{
1700 struct mmc_command *deferred_cmd = host->deferred_cmd;
1701 int timeout = 10; /* Approx. 10 ms */
1702 bool present;
1703
1704 while (!sdhci_send_command(host, cmd)) {
1705 if (!timeout--) {
1706 pr_err("%s: Controller never released inhibit bit(s).\n",
1707 mmc_hostname(host->mmc));
1708 sdhci_dumpregs(host);
1709 cmd->error = -EIO;
1710 return false;
1711 }
1712
1713 spin_unlock_irqrestore(&host->lock, flags);
1714
1715 usleep_range(1000, 1250);
1716
1717 present = host->mmc->ops->get_cd(host->mmc);
1718
1719 spin_lock_irqsave(&host->lock, flags);
1720
1721 /* A deferred command might disappear, handle that */
1722 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1723 return true;
1724
1725 if (sdhci_present_error(host, cmd, present))
1726 return false;
1727 }
1728
1729 if (cmd == host->deferred_cmd)
1730 host->deferred_cmd = NULL;
1731
1732 return true;
1733}
1734
1735static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1736{
1737 int i, reg;
1738
1739 for (i = 0; i < 4; i++) {
1740 reg = SDHCI_RESPONSE + (3 - i) * 4;
1741 cmd->resp[i] = sdhci_readl(host, reg);
1742 }
1743
1744 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1745 return;
1746
1747 /* CRC is stripped so we need to do some shifting */
1748 for (i = 0; i < 4; i++) {
1749 cmd->resp[i] <<= 8;
1750 if (i != 3)
1751 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1752 }
1753}
1754
1755static void sdhci_finish_command(struct sdhci_host *host)
1756{
1757 struct mmc_command *cmd = host->cmd;
1758
1759 host->cmd = NULL;
1760
1761 if (cmd->flags & MMC_RSP_PRESENT) {
1762 if (cmd->flags & MMC_RSP_136) {
1763 sdhci_read_rsp_136(host, cmd);
1764 } else {
1765 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1766 }
1767 }
1768
1769 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1770 mmc_command_done(host->mmc, cmd->mrq);
1771
1772 /*
1773 * The host can send and interrupt when the busy state has
1774 * ended, allowing us to wait without wasting CPU cycles.
1775 * The busy signal uses DAT0 so this is similar to waiting
1776 * for data to complete.
1777 *
1778 * Note: The 1.0 specification is a bit ambiguous about this
1779 * feature so there might be some problems with older
1780 * controllers.
1781 */
1782 if (cmd->flags & MMC_RSP_BUSY) {
1783 if (cmd->data) {
1784 DBG("Cannot wait for busy signal when also doing a data transfer");
1785 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1786 cmd == host->data_cmd) {
1787 /* Command complete before busy is ended */
1788 return;
1789 }
1790 }
1791
1792 /* Finished CMD23, now send actual command. */
1793 if (cmd == cmd->mrq->sbc) {
1794 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1795 WARN_ON(host->deferred_cmd);
1796 host->deferred_cmd = cmd->mrq->cmd;
1797 }
1798 } else {
1799
1800 /* Processed actual command. */
1801 if (host->data && host->data_early)
1802 sdhci_finish_data(host);
1803
1804 if (!cmd->data)
1805 __sdhci_finish_mrq(host, cmd->mrq);
1806 }
1807}
1808
1809static u16 sdhci_get_preset_value(struct sdhci_host *host)
1810{
1811 u16 preset = 0;
1812
1813 switch (host->timing) {
1814 case MMC_TIMING_UHS_SDR12:
1815 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1816 break;
1817 case MMC_TIMING_UHS_SDR25:
1818 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1819 break;
1820 case MMC_TIMING_UHS_SDR50:
1821 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1822 break;
1823 case MMC_TIMING_UHS_SDR104:
1824 case MMC_TIMING_MMC_HS200:
1825 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1826 break;
1827 case MMC_TIMING_UHS_DDR50:
1828 case MMC_TIMING_MMC_DDR52:
1829 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1830 break;
1831 case MMC_TIMING_MMC_HS400:
1832 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1833 break;
1834 default:
1835 pr_warn("%s: Invalid UHS-I mode selected\n",
1836 mmc_hostname(host->mmc));
1837 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1838 break;
1839 }
1840 return preset;
1841}
1842
1843u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1844 unsigned int *actual_clock)
1845{
1846 int div = 0; /* Initialized for compiler warning */
1847 int real_div = div, clk_mul = 1;
1848 u16 clk = 0;
1849 bool switch_base_clk = false;
1850
1851 if (host->version >= SDHCI_SPEC_300) {
1852 if (host->preset_enabled) {
1853 u16 pre_val;
1854
1855 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1856 pre_val = sdhci_get_preset_value(host);
1857 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1858 if (host->clk_mul &&
1859 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1860 clk = SDHCI_PROG_CLOCK_MODE;
1861 real_div = div + 1;
1862 clk_mul = host->clk_mul;
1863 } else {
1864 real_div = max_t(int, 1, div << 1);
1865 }
1866 goto clock_set;
1867 }
1868
1869 /*
1870 * Check if the Host Controller supports Programmable Clock
1871 * Mode.
1872 */
1873 if (host->clk_mul) {
1874 for (div = 1; div <= 1024; div++) {
1875 if ((host->max_clk * host->clk_mul / div)
1876 <= clock)
1877 break;
1878 }
1879 if ((host->max_clk * host->clk_mul / div) <= clock) {
1880 /*
1881 * Set Programmable Clock Mode in the Clock
1882 * Control register.
1883 */
1884 clk = SDHCI_PROG_CLOCK_MODE;
1885 real_div = div;
1886 clk_mul = host->clk_mul;
1887 div--;
1888 } else {
1889 /*
1890 * Divisor can be too small to reach clock
1891 * speed requirement. Then use the base clock.
1892 */
1893 switch_base_clk = true;
1894 }
1895 }
1896
1897 if (!host->clk_mul || switch_base_clk) {
1898 /* Version 3.00 divisors must be a multiple of 2. */
1899 if (host->max_clk <= clock)
1900 div = 1;
1901 else {
1902 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1903 div += 2) {
1904 if ((host->max_clk / div) <= clock)
1905 break;
1906 }
1907 }
1908 real_div = div;
1909 div >>= 1;
1910 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1911 && !div && host->max_clk <= 25000000)
1912 div = 1;
1913 }
1914 } else {
1915 /* Version 2.00 divisors must be a power of 2. */
1916 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1917 if ((host->max_clk / div) <= clock)
1918 break;
1919 }
1920 real_div = div;
1921 div >>= 1;
1922 }
1923
1924clock_set:
1925 if (real_div)
1926 *actual_clock = (host->max_clk * clk_mul) / real_div;
1927 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1928 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1929 << SDHCI_DIVIDER_HI_SHIFT;
1930
1931 return clk;
1932}
1933EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1934
1935void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1936{
1937 ktime_t timeout;
1938
1939 clk |= SDHCI_CLOCK_INT_EN;
1940 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1941
1942 /* Wait max 150 ms */
1943 timeout = ktime_add_ms(ktime_get(), 150);
1944 while (1) {
1945 bool timedout = ktime_after(ktime_get(), timeout);
1946
1947 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1948 if (clk & SDHCI_CLOCK_INT_STABLE)
1949 break;
1950 if (timedout) {
1951 pr_err("%s: Internal clock never stabilised.\n",
1952 mmc_hostname(host->mmc));
1953 sdhci_dumpregs(host);
1954 return;
1955 }
1956 udelay(10);
1957 }
1958
1959 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1960 clk |= SDHCI_CLOCK_PLL_EN;
1961 clk &= ~SDHCI_CLOCK_INT_STABLE;
1962 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1963
1964 /* Wait max 150 ms */
1965 timeout = ktime_add_ms(ktime_get(), 150);
1966 while (1) {
1967 bool timedout = ktime_after(ktime_get(), timeout);
1968
1969 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1970 if (clk & SDHCI_CLOCK_INT_STABLE)
1971 break;
1972 if (timedout) {
1973 pr_err("%s: PLL clock never stabilised.\n",
1974 mmc_hostname(host->mmc));
1975 sdhci_dumpregs(host);
1976 return;
1977 }
1978 udelay(10);
1979 }
1980 }
1981
1982 clk |= SDHCI_CLOCK_CARD_EN;
1983 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1984}
1985EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1986
1987void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1988{
1989 u16 clk;
1990
1991 host->mmc->actual_clock = 0;
1992
1993 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1994
1995 if (clock == 0)
1996 return;
1997
1998 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1999 sdhci_enable_clk(host, clk);
2000}
2001EXPORT_SYMBOL_GPL(sdhci_set_clock);
2002
2003static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2004 unsigned short vdd)
2005{
2006 struct mmc_host *mmc = host->mmc;
2007
2008 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2009
2010 if (mode != MMC_POWER_OFF)
2011 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2012 else
2013 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2014}
2015
2016void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2017 unsigned short vdd)
2018{
2019 u8 pwr = 0;
2020
2021 if (mode != MMC_POWER_OFF) {
2022 switch (1 << vdd) {
2023 case MMC_VDD_165_195:
2024 /*
2025 * Without a regulator, SDHCI does not support 2.0v
2026 * so we only get here if the driver deliberately
2027 * added the 2.0v range to ocr_avail. Map it to 1.8v
2028 * for the purpose of turning on the power.
2029 */
2030 case MMC_VDD_20_21:
2031 pwr = SDHCI_POWER_180;
2032 break;
2033 case MMC_VDD_29_30:
2034 case MMC_VDD_30_31:
2035 pwr = SDHCI_POWER_300;
2036 break;
2037 case MMC_VDD_32_33:
2038 case MMC_VDD_33_34:
2039 pwr = SDHCI_POWER_330;
2040 break;
2041 default:
2042 WARN(1, "%s: Invalid vdd %#x\n",
2043 mmc_hostname(host->mmc), vdd);
2044 break;
2045 }
2046 }
2047
2048 if (host->pwr == pwr)
2049 return;
2050
2051 host->pwr = pwr;
2052
2053 if (pwr == 0) {
2054 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2055 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2056 sdhci_runtime_pm_bus_off(host);
2057 } else {
2058 /*
2059 * Spec says that we should clear the power reg before setting
2060 * a new value. Some controllers don't seem to like this though.
2061 */
2062 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2063 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2064
2065 /*
2066 * At least the Marvell CaFe chip gets confused if we set the
2067 * voltage and set turn on power at the same time, so set the
2068 * voltage first.
2069 */
2070 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2071 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2072
2073 pwr |= SDHCI_POWER_ON;
2074
2075 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2076
2077 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2078 sdhci_runtime_pm_bus_on(host);
2079
2080 /*
2081 * Some controllers need an extra 10ms delay of 10ms before
2082 * they can apply clock after applying power
2083 */
2084 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2085 mdelay(10);
2086 }
2087}
2088EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2089
2090void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2091 unsigned short vdd)
2092{
2093 if (IS_ERR(host->mmc->supply.vmmc))
2094 sdhci_set_power_noreg(host, mode, vdd);
2095 else
2096 sdhci_set_power_reg(host, mode, vdd);
2097}
2098EXPORT_SYMBOL_GPL(sdhci_set_power);
2099
2100/*
2101 * Some controllers need to configure a valid bus voltage on their power
2102 * register regardless of whether an external regulator is taking care of power
2103 * supply. This helper function takes care of it if set as the controller's
2104 * sdhci_ops.set_power callback.
2105 */
2106void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2107 unsigned char mode,
2108 unsigned short vdd)
2109{
2110 if (!IS_ERR(host->mmc->supply.vmmc)) {
2111 struct mmc_host *mmc = host->mmc;
2112
2113 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2114 }
2115 sdhci_set_power_noreg(host, mode, vdd);
2116}
2117EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2118
2119/*****************************************************************************\
2120 * *
2121 * MMC callbacks *
2122 * *
2123\*****************************************************************************/
2124
2125void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2126{
2127 struct sdhci_host *host = mmc_priv(mmc);
2128 struct mmc_command *cmd;
2129 unsigned long flags;
2130 bool present;
2131
2132 /* Firstly check card presence */
2133 present = mmc->ops->get_cd(mmc);
2134
2135 spin_lock_irqsave(&host->lock, flags);
2136
2137 sdhci_led_activate(host);
2138
2139 if (sdhci_present_error(host, mrq->cmd, present))
2140 goto out_finish;
2141
2142 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2143
2144 if (!sdhci_send_command_retry(host, cmd, flags))
2145 goto out_finish;
2146
2147 spin_unlock_irqrestore(&host->lock, flags);
2148
2149 return;
2150
2151out_finish:
2152 sdhci_finish_mrq(host, mrq);
2153 spin_unlock_irqrestore(&host->lock, flags);
2154}
2155EXPORT_SYMBOL_GPL(sdhci_request);
2156
2157int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2158{
2159 struct sdhci_host *host = mmc_priv(mmc);
2160 struct mmc_command *cmd;
2161 unsigned long flags;
2162 int ret = 0;
2163
2164 spin_lock_irqsave(&host->lock, flags);
2165
2166 if (sdhci_present_error(host, mrq->cmd, true)) {
2167 sdhci_finish_mrq(host, mrq);
2168 goto out_finish;
2169 }
2170
2171 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2172
2173 /*
2174 * The HSQ may send a command in interrupt context without polling
2175 * the busy signaling, which means we should return BUSY if controller
2176 * has not released inhibit bits to allow HSQ trying to send request
2177 * again in non-atomic context. So we should not finish this request
2178 * here.
2179 */
2180 if (!sdhci_send_command(host, cmd))
2181 ret = -EBUSY;
2182 else
2183 sdhci_led_activate(host);
2184
2185out_finish:
2186 spin_unlock_irqrestore(&host->lock, flags);
2187 return ret;
2188}
2189EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2190
2191void sdhci_set_bus_width(struct sdhci_host *host, int width)
2192{
2193 u8 ctrl;
2194
2195 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2196 if (width == MMC_BUS_WIDTH_8) {
2197 ctrl &= ~SDHCI_CTRL_4BITBUS;
2198 ctrl |= SDHCI_CTRL_8BITBUS;
2199 } else {
2200 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2201 ctrl &= ~SDHCI_CTRL_8BITBUS;
2202 if (width == MMC_BUS_WIDTH_4)
2203 ctrl |= SDHCI_CTRL_4BITBUS;
2204 else
2205 ctrl &= ~SDHCI_CTRL_4BITBUS;
2206 }
2207 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2208}
2209EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2210
2211void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2212{
2213 u16 ctrl_2;
2214
2215 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2216 /* Select Bus Speed Mode for host */
2217 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2218 if ((timing == MMC_TIMING_MMC_HS200) ||
2219 (timing == MMC_TIMING_UHS_SDR104))
2220 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2221 else if (timing == MMC_TIMING_UHS_SDR12)
2222 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2223 else if (timing == MMC_TIMING_UHS_SDR25)
2224 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2225 else if (timing == MMC_TIMING_UHS_SDR50)
2226 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2227 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2228 (timing == MMC_TIMING_MMC_DDR52))
2229 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2230 else if (timing == MMC_TIMING_MMC_HS400)
2231 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2232 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2233}
2234EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2235
2236void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2237{
2238 struct sdhci_host *host = mmc_priv(mmc);
2239 u8 ctrl;
2240
2241 if (ios->power_mode == MMC_POWER_UNDEFINED)
2242 return;
2243
2244 if (host->flags & SDHCI_DEVICE_DEAD) {
2245 if (!IS_ERR(mmc->supply.vmmc) &&
2246 ios->power_mode == MMC_POWER_OFF)
2247 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2248 return;
2249 }
2250
2251 /*
2252 * Reset the chip on each power off.
2253 * Should clear out any weird states.
2254 */
2255 if (ios->power_mode == MMC_POWER_OFF) {
2256 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2257 sdhci_reinit(host);
2258 }
2259
2260 if (host->version >= SDHCI_SPEC_300 &&
2261 (ios->power_mode == MMC_POWER_UP) &&
2262 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2263 sdhci_enable_preset_value(host, false);
2264
2265 if (!ios->clock || ios->clock != host->clock) {
2266 host->ops->set_clock(host, ios->clock);
2267 host->clock = ios->clock;
2268
2269 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2270 host->clock) {
2271 host->timeout_clk = host->mmc->actual_clock ?
2272 host->mmc->actual_clock / 1000 :
2273 host->clock / 1000;
2274 host->mmc->max_busy_timeout =
2275 host->ops->get_max_timeout_count ?
2276 host->ops->get_max_timeout_count(host) :
2277 1 << 27;
2278 host->mmc->max_busy_timeout /= host->timeout_clk;
2279 }
2280 }
2281
2282 if (host->ops->set_power)
2283 host->ops->set_power(host, ios->power_mode, ios->vdd);
2284 else
2285 sdhci_set_power(host, ios->power_mode, ios->vdd);
2286
2287 if (host->ops->platform_send_init_74_clocks)
2288 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2289
2290 host->ops->set_bus_width(host, ios->bus_width);
2291
2292 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2293
2294 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2295 if (ios->timing == MMC_TIMING_SD_HS ||
2296 ios->timing == MMC_TIMING_MMC_HS ||
2297 ios->timing == MMC_TIMING_MMC_HS400 ||
2298 ios->timing == MMC_TIMING_MMC_HS200 ||
2299 ios->timing == MMC_TIMING_MMC_DDR52 ||
2300 ios->timing == MMC_TIMING_UHS_SDR50 ||
2301 ios->timing == MMC_TIMING_UHS_SDR104 ||
2302 ios->timing == MMC_TIMING_UHS_DDR50 ||
2303 ios->timing == MMC_TIMING_UHS_SDR25)
2304 ctrl |= SDHCI_CTRL_HISPD;
2305 else
2306 ctrl &= ~SDHCI_CTRL_HISPD;
2307 }
2308
2309 if (host->version >= SDHCI_SPEC_300) {
2310 u16 clk, ctrl_2;
2311
2312 if (!host->preset_enabled) {
2313 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2314 /*
2315 * We only need to set Driver Strength if the
2316 * preset value enable is not set.
2317 */
2318 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2319 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2320 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2321 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2322 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2323 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2324 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2325 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2326 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2327 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2328 else {
2329 pr_warn("%s: invalid driver type, default to driver type B\n",
2330 mmc_hostname(mmc));
2331 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2332 }
2333
2334 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2335 } else {
2336 /*
2337 * According to SDHC Spec v3.00, if the Preset Value
2338 * Enable in the Host Control 2 register is set, we
2339 * need to reset SD Clock Enable before changing High
2340 * Speed Enable to avoid generating clock gliches.
2341 */
2342
2343 /* Reset SD Clock Enable */
2344 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2345 clk &= ~SDHCI_CLOCK_CARD_EN;
2346 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2347
2348 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2349
2350 /* Re-enable SD Clock */
2351 host->ops->set_clock(host, host->clock);
2352 }
2353
2354 /* Reset SD Clock Enable */
2355 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2356 clk &= ~SDHCI_CLOCK_CARD_EN;
2357 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2358
2359 host->ops->set_uhs_signaling(host, ios->timing);
2360 host->timing = ios->timing;
2361
2362 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2363 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2364 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2365 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2366 (ios->timing == MMC_TIMING_UHS_SDR104) ||
2367 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2368 (ios->timing == MMC_TIMING_MMC_DDR52))) {
2369 u16 preset;
2370
2371 sdhci_enable_preset_value(host, true);
2372 preset = sdhci_get_preset_value(host);
2373 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2374 preset);
2375 }
2376
2377 /* Re-enable SD Clock */
2378 host->ops->set_clock(host, host->clock);
2379 } else
2380 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2381
2382 /*
2383 * Some (ENE) controllers go apeshit on some ios operation,
2384 * signalling timeout and CRC errors even on CMD0. Resetting
2385 * it on each ios seems to solve the problem.
2386 */
2387 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2388 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2389}
2390EXPORT_SYMBOL_GPL(sdhci_set_ios);
2391
2392static int sdhci_get_cd(struct mmc_host *mmc)
2393{
2394 struct sdhci_host *host = mmc_priv(mmc);
2395 int gpio_cd = mmc_gpio_get_cd(mmc);
2396
2397 if (host->flags & SDHCI_DEVICE_DEAD)
2398 return 0;
2399
2400 /* If nonremovable, assume that the card is always present. */
2401 if (!mmc_card_is_removable(host->mmc))
2402 return 1;
2403
2404 /*
2405 * Try slot gpio detect, if defined it take precedence
2406 * over build in controller functionality
2407 */
2408 if (gpio_cd >= 0)
2409 return !!gpio_cd;
2410
2411 /* If polling, assume that the card is always present. */
2412 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2413 return 1;
2414
2415 /* Host native card detect */
2416 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2417}
2418
2419static int sdhci_check_ro(struct sdhci_host *host)
2420{
2421 unsigned long flags;
2422 int is_readonly;
2423
2424 spin_lock_irqsave(&host->lock, flags);
2425
2426 if (host->flags & SDHCI_DEVICE_DEAD)
2427 is_readonly = 0;
2428 else if (host->ops->get_ro)
2429 is_readonly = host->ops->get_ro(host);
2430 else if (mmc_can_gpio_ro(host->mmc))
2431 is_readonly = mmc_gpio_get_ro(host->mmc);
2432 else
2433 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2434 & SDHCI_WRITE_PROTECT);
2435
2436 spin_unlock_irqrestore(&host->lock, flags);
2437
2438 /* This quirk needs to be replaced by a callback-function later */
2439 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2440 !is_readonly : is_readonly;
2441}
2442
2443#define SAMPLE_COUNT 5
2444
2445static int sdhci_get_ro(struct mmc_host *mmc)
2446{
2447 struct sdhci_host *host = mmc_priv(mmc);
2448 int i, ro_count;
2449
2450 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2451 return sdhci_check_ro(host);
2452
2453 ro_count = 0;
2454 for (i = 0; i < SAMPLE_COUNT; i++) {
2455 if (sdhci_check_ro(host)) {
2456 if (++ro_count > SAMPLE_COUNT / 2)
2457 return 1;
2458 }
2459 msleep(30);
2460 }
2461 return 0;
2462}
2463
2464static void sdhci_hw_reset(struct mmc_host *mmc)
2465{
2466 struct sdhci_host *host = mmc_priv(mmc);
2467
2468 if (host->ops && host->ops->hw_reset)
2469 host->ops->hw_reset(host);
2470}
2471
2472static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2473{
2474 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2475 if (enable)
2476 host->ier |= SDHCI_INT_CARD_INT;
2477 else
2478 host->ier &= ~SDHCI_INT_CARD_INT;
2479
2480 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2481 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2482 }
2483}
2484
2485void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2486{
2487 struct sdhci_host *host = mmc_priv(mmc);
2488 unsigned long flags;
2489
2490 if (enable)
2491 pm_runtime_get_noresume(host->mmc->parent);
2492
2493 spin_lock_irqsave(&host->lock, flags);
2494 sdhci_enable_sdio_irq_nolock(host, enable);
2495 spin_unlock_irqrestore(&host->lock, flags);
2496
2497 if (!enable)
2498 pm_runtime_put_noidle(host->mmc->parent);
2499}
2500EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2501
2502static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2503{
2504 struct sdhci_host *host = mmc_priv(mmc);
2505 unsigned long flags;
2506
2507 spin_lock_irqsave(&host->lock, flags);
2508 sdhci_enable_sdio_irq_nolock(host, true);
2509 spin_unlock_irqrestore(&host->lock, flags);
2510}
2511
2512int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2513 struct mmc_ios *ios)
2514{
2515 struct sdhci_host *host = mmc_priv(mmc);
2516 u16 ctrl;
2517 int ret;
2518
2519 /*
2520 * Signal Voltage Switching is only applicable for Host Controllers
2521 * v3.00 and above.
2522 */
2523 if (host->version < SDHCI_SPEC_300)
2524 return 0;
2525
2526 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2527
2528 switch (ios->signal_voltage) {
2529 case MMC_SIGNAL_VOLTAGE_330:
2530 if (!(host->flags & SDHCI_SIGNALING_330))
2531 return -EINVAL;
2532 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2533 ctrl &= ~SDHCI_CTRL_VDD_180;
2534 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2535
2536 if (!IS_ERR(mmc->supply.vqmmc)) {
2537 ret = mmc_regulator_set_vqmmc(mmc, ios);
2538 if (ret < 0) {
2539 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2540 mmc_hostname(mmc));
2541 return -EIO;
2542 }
2543 }
2544 /* Wait for 5ms */
2545 usleep_range(5000, 5500);
2546
2547 /* 3.3V regulator output should be stable within 5 ms */
2548 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2549 if (!(ctrl & SDHCI_CTRL_VDD_180))
2550 return 0;
2551
2552 pr_warn("%s: 3.3V regulator output did not become stable\n",
2553 mmc_hostname(mmc));
2554
2555 return -EAGAIN;
2556 case MMC_SIGNAL_VOLTAGE_180:
2557 if (!(host->flags & SDHCI_SIGNALING_180))
2558 return -EINVAL;
2559 if (!IS_ERR(mmc->supply.vqmmc)) {
2560 ret = mmc_regulator_set_vqmmc(mmc, ios);
2561 if (ret < 0) {
2562 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2563 mmc_hostname(mmc));
2564 return -EIO;
2565 }
2566 }
2567
2568 /*
2569 * Enable 1.8V Signal Enable in the Host Control2
2570 * register
2571 */
2572 ctrl |= SDHCI_CTRL_VDD_180;
2573 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2574
2575 /* Some controller need to do more when switching */
2576 if (host->ops->voltage_switch)
2577 host->ops->voltage_switch(host);
2578
2579 /* 1.8V regulator output should be stable within 5 ms */
2580 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2581 if (ctrl & SDHCI_CTRL_VDD_180)
2582 return 0;
2583
2584 pr_warn("%s: 1.8V regulator output did not become stable\n",
2585 mmc_hostname(mmc));
2586
2587 return -EAGAIN;
2588 case MMC_SIGNAL_VOLTAGE_120:
2589 if (!(host->flags & SDHCI_SIGNALING_120))
2590 return -EINVAL;
2591 if (!IS_ERR(mmc->supply.vqmmc)) {
2592 ret = mmc_regulator_set_vqmmc(mmc, ios);
2593 if (ret < 0) {
2594 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2595 mmc_hostname(mmc));
2596 return -EIO;
2597 }
2598 }
2599 return 0;
2600 default:
2601 /* No signal voltage switch required */
2602 return 0;
2603 }
2604}
2605EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2606
2607static int sdhci_card_busy(struct mmc_host *mmc)
2608{
2609 struct sdhci_host *host = mmc_priv(mmc);
2610 u32 present_state;
2611
2612 /* Check whether DAT[0] is 0 */
2613 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2614
2615 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2616}
2617
2618static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2619{
2620 struct sdhci_host *host = mmc_priv(mmc);
2621 unsigned long flags;
2622
2623 spin_lock_irqsave(&host->lock, flags);
2624 host->flags |= SDHCI_HS400_TUNING;
2625 spin_unlock_irqrestore(&host->lock, flags);
2626
2627 return 0;
2628}
2629
2630void sdhci_start_tuning(struct sdhci_host *host)
2631{
2632 u16 ctrl;
2633
2634 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2635 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2636 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2637 ctrl |= SDHCI_CTRL_TUNED_CLK;
2638 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2639
2640 /*
2641 * As per the Host Controller spec v3.00, tuning command
2642 * generates Buffer Read Ready interrupt, so enable that.
2643 *
2644 * Note: The spec clearly says that when tuning sequence
2645 * is being performed, the controller does not generate
2646 * interrupts other than Buffer Read Ready interrupt. But
2647 * to make sure we don't hit a controller bug, we _only_
2648 * enable Buffer Read Ready interrupt here.
2649 */
2650 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2651 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2652}
2653EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2654
2655void sdhci_end_tuning(struct sdhci_host *host)
2656{
2657 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2658 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2659}
2660EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2661
2662void sdhci_reset_tuning(struct sdhci_host *host)
2663{
2664 u16 ctrl;
2665
2666 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2667 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2668 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2669 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2670}
2671EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2672
2673void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2674{
2675 sdhci_reset_tuning(host);
2676
2677 sdhci_do_reset(host, SDHCI_RESET_CMD);
2678 sdhci_do_reset(host, SDHCI_RESET_DATA);
2679
2680 sdhci_end_tuning(host);
2681
2682 mmc_abort_tuning(host->mmc, opcode);
2683}
2684EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2685
2686/*
2687 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2688 * tuning command does not have a data payload (or rather the hardware does it
2689 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2690 * interrupt setup is different to other commands and there is no timeout
2691 * interrupt so special handling is needed.
2692 */
2693void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2694{
2695 struct mmc_host *mmc = host->mmc;
2696 struct mmc_command cmd = {};
2697 struct mmc_request mrq = {};
2698 unsigned long flags;
2699 u32 b = host->sdma_boundary;
2700
2701 spin_lock_irqsave(&host->lock, flags);
2702
2703 cmd.opcode = opcode;
2704 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2705 cmd.mrq = &mrq;
2706
2707 mrq.cmd = &cmd;
2708 /*
2709 * In response to CMD19, the card sends 64 bytes of tuning
2710 * block to the Host Controller. So we set the block size
2711 * to 64 here.
2712 */
2713 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2714 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2715 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2716 else
2717 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2718
2719 /*
2720 * The tuning block is sent by the card to the host controller.
2721 * So we set the TRNS_READ bit in the Transfer Mode register.
2722 * This also takes care of setting DMA Enable and Multi Block
2723 * Select in the same register to 0.
2724 */
2725 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2726
2727 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2728 spin_unlock_irqrestore(&host->lock, flags);
2729 host->tuning_done = 0;
2730 return;
2731 }
2732
2733 host->cmd = NULL;
2734
2735 sdhci_del_timer(host, &mrq);
2736
2737 host->tuning_done = 0;
2738
2739 spin_unlock_irqrestore(&host->lock, flags);
2740
2741 /* Wait for Buffer Read Ready interrupt */
2742 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2743 msecs_to_jiffies(50));
2744
2745}
2746EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2747
2748static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2749{
2750 int i;
2751
2752 /*
2753 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2754 * of loops reaches tuning loop count.
2755 */
2756 for (i = 0; i < host->tuning_loop_count; i++) {
2757 u16 ctrl;
2758
2759 sdhci_send_tuning(host, opcode);
2760
2761 if (!host->tuning_done) {
2762 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2763 mmc_hostname(host->mmc));
2764 sdhci_abort_tuning(host, opcode);
2765 return -ETIMEDOUT;
2766 }
2767
2768 /* Spec does not require a delay between tuning cycles */
2769 if (host->tuning_delay > 0)
2770 mdelay(host->tuning_delay);
2771
2772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2773 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2774 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2775 return 0; /* Success! */
2776 break;
2777 }
2778
2779 }
2780
2781 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2782 mmc_hostname(host->mmc));
2783 sdhci_reset_tuning(host);
2784 return -EAGAIN;
2785}
2786
2787int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2788{
2789 struct sdhci_host *host = mmc_priv(mmc);
2790 int err = 0;
2791 unsigned int tuning_count = 0;
2792 bool hs400_tuning;
2793
2794 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2795
2796 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2797 tuning_count = host->tuning_count;
2798
2799 /*
2800 * The Host Controller needs tuning in case of SDR104 and DDR50
2801 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2802 * the Capabilities register.
2803 * If the Host Controller supports the HS200 mode then the
2804 * tuning function has to be executed.
2805 */
2806 switch (host->timing) {
2807 /* HS400 tuning is done in HS200 mode */
2808 case MMC_TIMING_MMC_HS400:
2809 err = -EINVAL;
2810 goto out;
2811
2812 case MMC_TIMING_MMC_HS200:
2813 /*
2814 * Periodic re-tuning for HS400 is not expected to be needed, so
2815 * disable it here.
2816 */
2817 if (hs400_tuning)
2818 tuning_count = 0;
2819 break;
2820
2821 case MMC_TIMING_UHS_SDR104:
2822 case MMC_TIMING_UHS_DDR50:
2823 break;
2824
2825 case MMC_TIMING_UHS_SDR50:
2826 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2827 break;
2828 fallthrough;
2829
2830 default:
2831 goto out;
2832 }
2833
2834 if (host->ops->platform_execute_tuning) {
2835 err = host->ops->platform_execute_tuning(host, opcode);
2836 goto out;
2837 }
2838
2839 host->mmc->retune_period = tuning_count;
2840
2841 if (host->tuning_delay < 0)
2842 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2843
2844 sdhci_start_tuning(host);
2845
2846 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2847
2848 sdhci_end_tuning(host);
2849out:
2850 host->flags &= ~SDHCI_HS400_TUNING;
2851
2852 return err;
2853}
2854EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2855
2856static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2857{
2858 /* Host Controller v3.00 defines preset value registers */
2859 if (host->version < SDHCI_SPEC_300)
2860 return;
2861
2862 /*
2863 * We only enable or disable Preset Value if they are not already
2864 * enabled or disabled respectively. Otherwise, we bail out.
2865 */
2866 if (host->preset_enabled != enable) {
2867 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2868
2869 if (enable)
2870 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2871 else
2872 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2873
2874 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2875
2876 if (enable)
2877 host->flags |= SDHCI_PV_ENABLED;
2878 else
2879 host->flags &= ~SDHCI_PV_ENABLED;
2880
2881 host->preset_enabled = enable;
2882 }
2883}
2884
2885static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2886 int err)
2887{
2888 struct sdhci_host *host = mmc_priv(mmc);
2889 struct mmc_data *data = mrq->data;
2890
2891 if (data->host_cookie != COOKIE_UNMAPPED)
2892 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2893 mmc_get_dma_dir(data));
2894
2895 data->host_cookie = COOKIE_UNMAPPED;
2896}
2897
2898static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2899{
2900 struct sdhci_host *host = mmc_priv(mmc);
2901
2902 mrq->data->host_cookie = COOKIE_UNMAPPED;
2903
2904 /*
2905 * No pre-mapping in the pre hook if we're using the bounce buffer,
2906 * for that we would need two bounce buffers since one buffer is
2907 * in flight when this is getting called.
2908 */
2909 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2910 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2911}
2912
2913static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2914{
2915 if (host->data_cmd) {
2916 host->data_cmd->error = err;
2917 sdhci_finish_mrq(host, host->data_cmd->mrq);
2918 }
2919
2920 if (host->cmd) {
2921 host->cmd->error = err;
2922 sdhci_finish_mrq(host, host->cmd->mrq);
2923 }
2924}
2925
2926static void sdhci_card_event(struct mmc_host *mmc)
2927{
2928 struct sdhci_host *host = mmc_priv(mmc);
2929 unsigned long flags;
2930 int present;
2931
2932 /* First check if client has provided their own card event */
2933 if (host->ops->card_event)
2934 host->ops->card_event(host);
2935
2936 present = mmc->ops->get_cd(mmc);
2937
2938 spin_lock_irqsave(&host->lock, flags);
2939
2940 /* Check sdhci_has_requests() first in case we are runtime suspended */
2941 if (sdhci_has_requests(host) && !present) {
2942 pr_err("%s: Card removed during transfer!\n",
2943 mmc_hostname(host->mmc));
2944 pr_err("%s: Resetting controller.\n",
2945 mmc_hostname(host->mmc));
2946
2947 sdhci_do_reset(host, SDHCI_RESET_CMD);
2948 sdhci_do_reset(host, SDHCI_RESET_DATA);
2949
2950 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2951 }
2952
2953 spin_unlock_irqrestore(&host->lock, flags);
2954}
2955
2956static const struct mmc_host_ops sdhci_ops = {
2957 .request = sdhci_request,
2958 .post_req = sdhci_post_req,
2959 .pre_req = sdhci_pre_req,
2960 .set_ios = sdhci_set_ios,
2961 .get_cd = sdhci_get_cd,
2962 .get_ro = sdhci_get_ro,
2963 .hw_reset = sdhci_hw_reset,
2964 .enable_sdio_irq = sdhci_enable_sdio_irq,
2965 .ack_sdio_irq = sdhci_ack_sdio_irq,
2966 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2967 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2968 .execute_tuning = sdhci_execute_tuning,
2969 .card_event = sdhci_card_event,
2970 .card_busy = sdhci_card_busy,
2971};
2972
2973/*****************************************************************************\
2974 * *
2975 * Request done *
2976 * *
2977\*****************************************************************************/
2978
2979static bool sdhci_request_done(struct sdhci_host *host)
2980{
2981 unsigned long flags;
2982 struct mmc_request *mrq;
2983 int i;
2984
2985 spin_lock_irqsave(&host->lock, flags);
2986
2987 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2988 mrq = host->mrqs_done[i];
2989 if (mrq)
2990 break;
2991 }
2992
2993 if (!mrq) {
2994 spin_unlock_irqrestore(&host->lock, flags);
2995 return true;
2996 }
2997
2998 /*
2999 * Always unmap the data buffers if they were mapped by
3000 * sdhci_prepare_data() whenever we finish with a request.
3001 * This avoids leaking DMA mappings on error.
3002 */
3003 if (host->flags & SDHCI_REQ_USE_DMA) {
3004 struct mmc_data *data = mrq->data;
3005
3006 if (host->use_external_dma && data &&
3007 (mrq->cmd->error || data->error)) {
3008 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3009
3010 host->mrqs_done[i] = NULL;
3011 spin_unlock_irqrestore(&host->lock, flags);
3012 dmaengine_terminate_sync(chan);
3013 spin_lock_irqsave(&host->lock, flags);
3014 sdhci_set_mrq_done(host, mrq);
3015 }
3016
3017 if (data && data->host_cookie == COOKIE_MAPPED) {
3018 if (host->bounce_buffer) {
3019 /*
3020 * On reads, copy the bounced data into the
3021 * sglist
3022 */
3023 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3024 unsigned int length = data->bytes_xfered;
3025
3026 if (length > host->bounce_buffer_size) {
3027 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3028 mmc_hostname(host->mmc),
3029 host->bounce_buffer_size,
3030 data->bytes_xfered);
3031 /* Cap it down and continue */
3032 length = host->bounce_buffer_size;
3033 }
3034 dma_sync_single_for_cpu(
3035 host->mmc->parent,
3036 host->bounce_addr,
3037 host->bounce_buffer_size,
3038 DMA_FROM_DEVICE);
3039 sg_copy_from_buffer(data->sg,
3040 data->sg_len,
3041 host->bounce_buffer,
3042 length);
3043 } else {
3044 /* No copying, just switch ownership */
3045 dma_sync_single_for_cpu(
3046 host->mmc->parent,
3047 host->bounce_addr,
3048 host->bounce_buffer_size,
3049 mmc_get_dma_dir(data));
3050 }
3051 } else {
3052 /* Unmap the raw data */
3053 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3054 data->sg_len,
3055 mmc_get_dma_dir(data));
3056 }
3057 data->host_cookie = COOKIE_UNMAPPED;
3058 }
3059 }
3060
3061 /*
3062 * The controller needs a reset of internal state machines
3063 * upon error conditions.
3064 */
3065 if (sdhci_needs_reset(host, mrq)) {
3066 /*
3067 * Do not finish until command and data lines are available for
3068 * reset. Note there can only be one other mrq, so it cannot
3069 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3070 * would both be null.
3071 */
3072 if (host->cmd || host->data_cmd) {
3073 spin_unlock_irqrestore(&host->lock, flags);
3074 return true;
3075 }
3076
3077 /* Some controllers need this kick or reset won't work here */
3078 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3079 /* This is to force an update */
3080 host->ops->set_clock(host, host->clock);
3081
3082 /* Spec says we should do both at the same time, but Ricoh
3083 controllers do not like that. */
3084 sdhci_do_reset(host, SDHCI_RESET_CMD);
3085 sdhci_do_reset(host, SDHCI_RESET_DATA);
3086
3087 host->pending_reset = false;
3088 }
3089
3090 host->mrqs_done[i] = NULL;
3091
3092 spin_unlock_irqrestore(&host->lock, flags);
3093
3094 if (host->ops->request_done)
3095 host->ops->request_done(host, mrq);
3096 else
3097 mmc_request_done(host->mmc, mrq);
3098
3099 return false;
3100}
3101
3102static void sdhci_complete_work(struct work_struct *work)
3103{
3104 struct sdhci_host *host = container_of(work, struct sdhci_host,
3105 complete_work);
3106
3107 while (!sdhci_request_done(host))
3108 ;
3109}
3110
3111static void sdhci_timeout_timer(struct timer_list *t)
3112{
3113 struct sdhci_host *host;
3114 unsigned long flags;
3115
3116 host = from_timer(host, t, timer);
3117
3118 spin_lock_irqsave(&host->lock, flags);
3119
3120 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3121 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3122 mmc_hostname(host->mmc));
3123 sdhci_dumpregs(host);
3124
3125 host->cmd->error = -ETIMEDOUT;
3126 sdhci_finish_mrq(host, host->cmd->mrq);
3127 }
3128
3129 spin_unlock_irqrestore(&host->lock, flags);
3130}
3131
3132static void sdhci_timeout_data_timer(struct timer_list *t)
3133{
3134 struct sdhci_host *host;
3135 unsigned long flags;
3136
3137 host = from_timer(host, t, data_timer);
3138
3139 spin_lock_irqsave(&host->lock, flags);
3140
3141 if (host->data || host->data_cmd ||
3142 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3143 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3144 mmc_hostname(host->mmc));
3145 sdhci_dumpregs(host);
3146
3147 if (host->data) {
3148 host->data->error = -ETIMEDOUT;
3149 __sdhci_finish_data(host, true);
3150 queue_work(host->complete_wq, &host->complete_work);
3151 } else if (host->data_cmd) {
3152 host->data_cmd->error = -ETIMEDOUT;
3153 sdhci_finish_mrq(host, host->data_cmd->mrq);
3154 } else {
3155 host->cmd->error = -ETIMEDOUT;
3156 sdhci_finish_mrq(host, host->cmd->mrq);
3157 }
3158 }
3159
3160 spin_unlock_irqrestore(&host->lock, flags);
3161}
3162
3163/*****************************************************************************\
3164 * *
3165 * Interrupt handling *
3166 * *
3167\*****************************************************************************/
3168
3169static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3170{
3171 /* Handle auto-CMD12 error */
3172 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3173 struct mmc_request *mrq = host->data_cmd->mrq;
3174 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3175 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3176 SDHCI_INT_DATA_TIMEOUT :
3177 SDHCI_INT_DATA_CRC;
3178
3179 /* Treat auto-CMD12 error the same as data error */
3180 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3181 *intmask_p |= data_err_bit;
3182 return;
3183 }
3184 }
3185
3186 if (!host->cmd) {
3187 /*
3188 * SDHCI recovers from errors by resetting the cmd and data
3189 * circuits. Until that is done, there very well might be more
3190 * interrupts, so ignore them in that case.
3191 */
3192 if (host->pending_reset)
3193 return;
3194 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3195 mmc_hostname(host->mmc), (unsigned)intmask);
3196 sdhci_dumpregs(host);
3197 return;
3198 }
3199
3200 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3201 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3202 if (intmask & SDHCI_INT_TIMEOUT)
3203 host->cmd->error = -ETIMEDOUT;
3204 else
3205 host->cmd->error = -EILSEQ;
3206
3207 /* Treat data command CRC error the same as data CRC error */
3208 if (host->cmd->data &&
3209 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3210 SDHCI_INT_CRC) {
3211 host->cmd = NULL;
3212 *intmask_p |= SDHCI_INT_DATA_CRC;
3213 return;
3214 }
3215
3216 __sdhci_finish_mrq(host, host->cmd->mrq);
3217 return;
3218 }
3219
3220 /* Handle auto-CMD23 error */
3221 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3222 struct mmc_request *mrq = host->cmd->mrq;
3223 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3224 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3225 -ETIMEDOUT :
3226 -EILSEQ;
3227
3228 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3229 mrq->sbc->error = err;
3230 __sdhci_finish_mrq(host, mrq);
3231 return;
3232 }
3233 }
3234
3235 if (intmask & SDHCI_INT_RESPONSE)
3236 sdhci_finish_command(host);
3237}
3238
3239static void sdhci_adma_show_error(struct sdhci_host *host)
3240{
3241 void *desc = host->adma_table;
3242 dma_addr_t dma = host->adma_addr;
3243
3244 sdhci_dumpregs(host);
3245
3246 while (true) {
3247 struct sdhci_adma2_64_desc *dma_desc = desc;
3248
3249 if (host->flags & SDHCI_USE_64_BIT_DMA)
3250 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3251 (unsigned long long)dma,
3252 le32_to_cpu(dma_desc->addr_hi),
3253 le32_to_cpu(dma_desc->addr_lo),
3254 le16_to_cpu(dma_desc->len),
3255 le16_to_cpu(dma_desc->cmd));
3256 else
3257 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3258 (unsigned long long)dma,
3259 le32_to_cpu(dma_desc->addr_lo),
3260 le16_to_cpu(dma_desc->len),
3261 le16_to_cpu(dma_desc->cmd));
3262
3263 desc += host->desc_sz;
3264 dma += host->desc_sz;
3265
3266 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3267 break;
3268 }
3269}
3270
3271static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3272{
3273 u32 command;
3274
3275 /* CMD19 generates _only_ Buffer Read Ready interrupt */
3276 if (intmask & SDHCI_INT_DATA_AVAIL) {
3277 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3278 if (command == MMC_SEND_TUNING_BLOCK ||
3279 command == MMC_SEND_TUNING_BLOCK_HS200) {
3280 host->tuning_done = 1;
3281 wake_up(&host->buf_ready_int);
3282 return;
3283 }
3284 }
3285
3286 if (!host->data) {
3287 struct mmc_command *data_cmd = host->data_cmd;
3288
3289 /*
3290 * The "data complete" interrupt is also used to
3291 * indicate that a busy state has ended. See comment
3292 * above in sdhci_cmd_irq().
3293 */
3294 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3295 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3296 host->data_cmd = NULL;
3297 data_cmd->error = -ETIMEDOUT;
3298 __sdhci_finish_mrq(host, data_cmd->mrq);
3299 return;
3300 }
3301 if (intmask & SDHCI_INT_DATA_END) {
3302 host->data_cmd = NULL;
3303 /*
3304 * Some cards handle busy-end interrupt
3305 * before the command completed, so make
3306 * sure we do things in the proper order.
3307 */
3308 if (host->cmd == data_cmd)
3309 return;
3310
3311 __sdhci_finish_mrq(host, data_cmd->mrq);
3312 return;
3313 }
3314 }
3315
3316 /*
3317 * SDHCI recovers from errors by resetting the cmd and data
3318 * circuits. Until that is done, there very well might be more
3319 * interrupts, so ignore them in that case.
3320 */
3321 if (host->pending_reset)
3322 return;
3323
3324 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3325 mmc_hostname(host->mmc), (unsigned)intmask);
3326 sdhci_dumpregs(host);
3327
3328 return;
3329 }
3330
3331 if (intmask & SDHCI_INT_DATA_TIMEOUT)
3332 host->data->error = -ETIMEDOUT;
3333 else if (intmask & SDHCI_INT_DATA_END_BIT)
3334 host->data->error = -EILSEQ;
3335 else if ((intmask & SDHCI_INT_DATA_CRC) &&
3336 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3337 != MMC_BUS_TEST_R)
3338 host->data->error = -EILSEQ;
3339 else if (intmask & SDHCI_INT_ADMA_ERROR) {
3340 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3341 intmask);
3342 sdhci_adma_show_error(host);
3343 host->data->error = -EIO;
3344 if (host->ops->adma_workaround)
3345 host->ops->adma_workaround(host, intmask);
3346 }
3347
3348 if (host->data->error)
3349 sdhci_finish_data(host);
3350 else {
3351 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3352 sdhci_transfer_pio(host);
3353
3354 /*
3355 * We currently don't do anything fancy with DMA
3356 * boundaries, but as we can't disable the feature
3357 * we need to at least restart the transfer.
3358 *
3359 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3360 * should return a valid address to continue from, but as
3361 * some controllers are faulty, don't trust them.
3362 */
3363 if (intmask & SDHCI_INT_DMA_END) {
3364 dma_addr_t dmastart, dmanow;
3365
3366 dmastart = sdhci_sdma_address(host);
3367 dmanow = dmastart + host->data->bytes_xfered;
3368 /*
3369 * Force update to the next DMA block boundary.
3370 */
3371 dmanow = (dmanow &
3372 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3373 SDHCI_DEFAULT_BOUNDARY_SIZE;
3374 host->data->bytes_xfered = dmanow - dmastart;
3375 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3376 &dmastart, host->data->bytes_xfered, &dmanow);
3377 sdhci_set_sdma_addr(host, dmanow);
3378 }
3379
3380 if (intmask & SDHCI_INT_DATA_END) {
3381 if (host->cmd == host->data_cmd) {
3382 /*
3383 * Data managed to finish before the
3384 * command completed. Make sure we do
3385 * things in the proper order.
3386 */
3387 host->data_early = 1;
3388 } else {
3389 sdhci_finish_data(host);
3390 }
3391 }
3392 }
3393}
3394
3395static inline bool sdhci_defer_done(struct sdhci_host *host,
3396 struct mmc_request *mrq)
3397{
3398 struct mmc_data *data = mrq->data;
3399
3400 return host->pending_reset || host->always_defer_done ||
3401 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3402 data->host_cookie == COOKIE_MAPPED);
3403}
3404
3405static irqreturn_t sdhci_irq(int irq, void *dev_id)
3406{
3407 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3408 irqreturn_t result = IRQ_NONE;
3409 struct sdhci_host *host = dev_id;
3410 u32 intmask, mask, unexpected = 0;
3411 int max_loops = 16;
3412 int i;
3413
3414 spin_lock(&host->lock);
3415
3416 if (host->runtime_suspended) {
3417 spin_unlock(&host->lock);
3418 return IRQ_NONE;
3419 }
3420
3421 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3422 if (!intmask || intmask == 0xffffffff) {
3423 result = IRQ_NONE;
3424 goto out;
3425 }
3426
3427 do {
3428 DBG("IRQ status 0x%08x\n", intmask);
3429
3430 if (host->ops->irq) {
3431 intmask = host->ops->irq(host, intmask);
3432 if (!intmask)
3433 goto cont;
3434 }
3435
3436 /* Clear selected interrupts. */
3437 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3438 SDHCI_INT_BUS_POWER);
3439 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3440
3441 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3442 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3443 SDHCI_CARD_PRESENT;
3444
3445 /*
3446 * There is a observation on i.mx esdhc. INSERT
3447 * bit will be immediately set again when it gets
3448 * cleared, if a card is inserted. We have to mask
3449 * the irq to prevent interrupt storm which will
3450 * freeze the system. And the REMOVE gets the
3451 * same situation.
3452 *
3453 * More testing are needed here to ensure it works
3454 * for other platforms though.
3455 */
3456 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3457 SDHCI_INT_CARD_REMOVE);
3458 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3459 SDHCI_INT_CARD_INSERT;
3460 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3461 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3462
3463 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3464 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3465
3466 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3467 SDHCI_INT_CARD_REMOVE);
3468 result = IRQ_WAKE_THREAD;
3469 }
3470
3471 if (intmask & SDHCI_INT_CMD_MASK)
3472 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3473
3474 if (intmask & SDHCI_INT_DATA_MASK)
3475 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3476
3477 if (intmask & SDHCI_INT_BUS_POWER)
3478 pr_err("%s: Card is consuming too much power!\n",
3479 mmc_hostname(host->mmc));
3480
3481 if (intmask & SDHCI_INT_RETUNE)
3482 mmc_retune_needed(host->mmc);
3483
3484 if ((intmask & SDHCI_INT_CARD_INT) &&
3485 (host->ier & SDHCI_INT_CARD_INT)) {
3486 sdhci_enable_sdio_irq_nolock(host, false);
3487 sdio_signal_irq(host->mmc);
3488 }
3489
3490 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3491 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3492 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3493 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3494
3495 if (intmask) {
3496 unexpected |= intmask;
3497 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3498 }
3499cont:
3500 if (result == IRQ_NONE)
3501 result = IRQ_HANDLED;
3502
3503 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3504 } while (intmask && --max_loops);
3505
3506 /* Determine if mrqs can be completed immediately */
3507 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3508 struct mmc_request *mrq = host->mrqs_done[i];
3509
3510 if (!mrq)
3511 continue;
3512
3513 if (sdhci_defer_done(host, mrq)) {
3514 result = IRQ_WAKE_THREAD;
3515 } else {
3516 mrqs_done[i] = mrq;
3517 host->mrqs_done[i] = NULL;
3518 }
3519 }
3520out:
3521 if (host->deferred_cmd)
3522 result = IRQ_WAKE_THREAD;
3523
3524 spin_unlock(&host->lock);
3525
3526 /* Process mrqs ready for immediate completion */
3527 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3528 if (!mrqs_done[i])
3529 continue;
3530
3531 if (host->ops->request_done)
3532 host->ops->request_done(host, mrqs_done[i]);
3533 else
3534 mmc_request_done(host->mmc, mrqs_done[i]);
3535 }
3536
3537 if (unexpected) {
3538 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3539 mmc_hostname(host->mmc), unexpected);
3540 sdhci_dumpregs(host);
3541 }
3542
3543 return result;
3544}
3545
3546static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3547{
3548 struct sdhci_host *host = dev_id;
3549 struct mmc_command *cmd;
3550 unsigned long flags;
3551 u32 isr;
3552
3553 while (!sdhci_request_done(host))
3554 ;
3555
3556 spin_lock_irqsave(&host->lock, flags);
3557
3558 isr = host->thread_isr;
3559 host->thread_isr = 0;
3560
3561 cmd = host->deferred_cmd;
3562 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3563 sdhci_finish_mrq(host, cmd->mrq);
3564
3565 spin_unlock_irqrestore(&host->lock, flags);
3566
3567 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3568 struct mmc_host *mmc = host->mmc;
3569
3570 mmc->ops->card_event(mmc);
3571 mmc_detect_change(mmc, msecs_to_jiffies(200));
3572 }
3573
3574 return IRQ_HANDLED;
3575}
3576
3577/*****************************************************************************\
3578 * *
3579 * Suspend/resume *
3580 * *
3581\*****************************************************************************/
3582
3583#ifdef CONFIG_PM
3584
3585static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3586{
3587 return mmc_card_is_removable(host->mmc) &&
3588 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3589 !mmc_can_gpio_cd(host->mmc);
3590}
3591
3592/*
3593 * To enable wakeup events, the corresponding events have to be enabled in
3594 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3595 * Table' in the SD Host Controller Standard Specification.
3596 * It is useless to restore SDHCI_INT_ENABLE state in
3597 * sdhci_disable_irq_wakeups() since it will be set by
3598 * sdhci_enable_card_detection() or sdhci_init().
3599 */
3600static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3601{
3602 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3603 SDHCI_WAKE_ON_INT;
3604 u32 irq_val = 0;
3605 u8 wake_val = 0;
3606 u8 val;
3607
3608 if (sdhci_cd_irq_can_wakeup(host)) {
3609 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3610 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3611 }
3612
3613 if (mmc_card_wake_sdio_irq(host->mmc)) {
3614 wake_val |= SDHCI_WAKE_ON_INT;
3615 irq_val |= SDHCI_INT_CARD_INT;
3616 }
3617
3618 if (!irq_val)
3619 return false;
3620
3621 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3622 val &= ~mask;
3623 val |= wake_val;
3624 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3625
3626 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3627
3628 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3629
3630 return host->irq_wake_enabled;
3631}
3632
3633static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3634{
3635 u8 val;
3636 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3637 | SDHCI_WAKE_ON_INT;
3638
3639 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3640 val &= ~mask;
3641 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3642
3643 disable_irq_wake(host->irq);
3644
3645 host->irq_wake_enabled = false;
3646}
3647
3648int sdhci_suspend_host(struct sdhci_host *host)
3649{
3650 sdhci_disable_card_detection(host);
3651
3652 mmc_retune_timer_stop(host->mmc);
3653
3654 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3655 !sdhci_enable_irq_wakeups(host)) {
3656 host->ier = 0;
3657 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3658 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3659 free_irq(host->irq, host);
3660 }
3661
3662 return 0;
3663}
3664
3665EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3666
3667int sdhci_resume_host(struct sdhci_host *host)
3668{
3669 struct mmc_host *mmc = host->mmc;
3670 int ret = 0;
3671
3672 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3673 if (host->ops->enable_dma)
3674 host->ops->enable_dma(host);
3675 }
3676
3677 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3678 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3679 /* Card keeps power but host controller does not */
3680 sdhci_init(host, 0);
3681 host->pwr = 0;
3682 host->clock = 0;
3683 mmc->ops->set_ios(mmc, &mmc->ios);
3684 } else {
3685 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3686 }
3687
3688 if (host->irq_wake_enabled) {
3689 sdhci_disable_irq_wakeups(host);
3690 } else {
3691 ret = request_threaded_irq(host->irq, sdhci_irq,
3692 sdhci_thread_irq, IRQF_SHARED,
3693 mmc_hostname(host->mmc), host);
3694 if (ret)
3695 return ret;
3696 }
3697
3698 sdhci_enable_card_detection(host);
3699
3700 return ret;
3701}
3702
3703EXPORT_SYMBOL_GPL(sdhci_resume_host);
3704
3705int sdhci_runtime_suspend_host(struct sdhci_host *host)
3706{
3707 unsigned long flags;
3708
3709 mmc_retune_timer_stop(host->mmc);
3710
3711 spin_lock_irqsave(&host->lock, flags);
3712 host->ier &= SDHCI_INT_CARD_INT;
3713 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3714 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3715 spin_unlock_irqrestore(&host->lock, flags);
3716
3717 synchronize_hardirq(host->irq);
3718
3719 spin_lock_irqsave(&host->lock, flags);
3720 host->runtime_suspended = true;
3721 spin_unlock_irqrestore(&host->lock, flags);
3722
3723 return 0;
3724}
3725EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3726
3727int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3728{
3729 struct mmc_host *mmc = host->mmc;
3730 unsigned long flags;
3731 int host_flags = host->flags;
3732
3733 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3734 if (host->ops->enable_dma)
3735 host->ops->enable_dma(host);
3736 }
3737
3738 sdhci_init(host, soft_reset);
3739
3740 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3741 mmc->ios.power_mode != MMC_POWER_OFF) {
3742 /* Force clock and power re-program */
3743 host->pwr = 0;
3744 host->clock = 0;
3745 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3746 mmc->ops->set_ios(mmc, &mmc->ios);
3747
3748 if ((host_flags & SDHCI_PV_ENABLED) &&
3749 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3750 spin_lock_irqsave(&host->lock, flags);
3751 sdhci_enable_preset_value(host, true);
3752 spin_unlock_irqrestore(&host->lock, flags);
3753 }
3754
3755 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3756 mmc->ops->hs400_enhanced_strobe)
3757 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3758 }
3759
3760 spin_lock_irqsave(&host->lock, flags);
3761
3762 host->runtime_suspended = false;
3763
3764 /* Enable SDIO IRQ */
3765 if (sdio_irq_claimed(mmc))
3766 sdhci_enable_sdio_irq_nolock(host, true);
3767
3768 /* Enable Card Detection */
3769 sdhci_enable_card_detection(host);
3770
3771 spin_unlock_irqrestore(&host->lock, flags);
3772
3773 return 0;
3774}
3775EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3776
3777#endif /* CONFIG_PM */
3778
3779/*****************************************************************************\
3780 * *
3781 * Command Queue Engine (CQE) helpers *
3782 * *
3783\*****************************************************************************/
3784
3785void sdhci_cqe_enable(struct mmc_host *mmc)
3786{
3787 struct sdhci_host *host = mmc_priv(mmc);
3788 unsigned long flags;
3789 u8 ctrl;
3790
3791 spin_lock_irqsave(&host->lock, flags);
3792
3793 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3794 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3795 /*
3796 * Host from V4.10 supports ADMA3 DMA type.
3797 * ADMA3 performs integrated descriptor which is more suitable
3798 * for cmd queuing to fetch both command and transfer descriptors.
3799 */
3800 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3801 ctrl |= SDHCI_CTRL_ADMA3;
3802 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3803 ctrl |= SDHCI_CTRL_ADMA64;
3804 else
3805 ctrl |= SDHCI_CTRL_ADMA32;
3806 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3807
3808 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3809 SDHCI_BLOCK_SIZE);
3810
3811 /* Set maximum timeout */
3812 sdhci_set_timeout(host, NULL);
3813
3814 host->ier = host->cqe_ier;
3815
3816 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3817 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3818
3819 host->cqe_on = true;
3820
3821 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3822 mmc_hostname(mmc), host->ier,
3823 sdhci_readl(host, SDHCI_INT_STATUS));
3824
3825 spin_unlock_irqrestore(&host->lock, flags);
3826}
3827EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3828
3829void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3830{
3831 struct sdhci_host *host = mmc_priv(mmc);
3832 unsigned long flags;
3833
3834 spin_lock_irqsave(&host->lock, flags);
3835
3836 sdhci_set_default_irqs(host);
3837
3838 host->cqe_on = false;
3839
3840 if (recovery) {
3841 sdhci_do_reset(host, SDHCI_RESET_CMD);
3842 sdhci_do_reset(host, SDHCI_RESET_DATA);
3843 }
3844
3845 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3846 mmc_hostname(mmc), host->ier,
3847 sdhci_readl(host, SDHCI_INT_STATUS));
3848
3849 spin_unlock_irqrestore(&host->lock, flags);
3850}
3851EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3852
3853bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3854 int *data_error)
3855{
3856 u32 mask;
3857
3858 if (!host->cqe_on)
3859 return false;
3860
3861 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3862 *cmd_error = -EILSEQ;
3863 else if (intmask & SDHCI_INT_TIMEOUT)
3864 *cmd_error = -ETIMEDOUT;
3865 else
3866 *cmd_error = 0;
3867
3868 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3869 *data_error = -EILSEQ;
3870 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3871 *data_error = -ETIMEDOUT;
3872 else if (intmask & SDHCI_INT_ADMA_ERROR)
3873 *data_error = -EIO;
3874 else
3875 *data_error = 0;
3876
3877 /* Clear selected interrupts. */
3878 mask = intmask & host->cqe_ier;
3879 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3880
3881 if (intmask & SDHCI_INT_BUS_POWER)
3882 pr_err("%s: Card is consuming too much power!\n",
3883 mmc_hostname(host->mmc));
3884
3885 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3886 if (intmask) {
3887 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3888 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3889 mmc_hostname(host->mmc), intmask);
3890 sdhci_dumpregs(host);
3891 }
3892
3893 return true;
3894}
3895EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3896
3897/*****************************************************************************\
3898 * *
3899 * Device allocation/registration *
3900 * *
3901\*****************************************************************************/
3902
3903struct sdhci_host *sdhci_alloc_host(struct device *dev,
3904 size_t priv_size)
3905{
3906 struct mmc_host *mmc;
3907 struct sdhci_host *host;
3908
3909 WARN_ON(dev == NULL);
3910
3911 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3912 if (!mmc)
3913 return ERR_PTR(-ENOMEM);
3914
3915 host = mmc_priv(mmc);
3916 host->mmc = mmc;
3917 host->mmc_host_ops = sdhci_ops;
3918 mmc->ops = &host->mmc_host_ops;
3919
3920 host->flags = SDHCI_SIGNALING_330;
3921
3922 host->cqe_ier = SDHCI_CQE_INT_MASK;
3923 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3924
3925 host->tuning_delay = -1;
3926 host->tuning_loop_count = MAX_TUNING_LOOP;
3927
3928 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3929
3930 /*
3931 * The DMA table descriptor count is calculated as the maximum
3932 * number of segments times 2, to allow for an alignment
3933 * descriptor for each segment, plus 1 for a nop end descriptor.
3934 */
3935 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3936
3937 return host;
3938}
3939
3940EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3941
3942static int sdhci_set_dma_mask(struct sdhci_host *host)
3943{
3944 struct mmc_host *mmc = host->mmc;
3945 struct device *dev = mmc_dev(mmc);
3946 int ret = -EINVAL;
3947
3948 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3949 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3950
3951 /* Try 64-bit mask if hardware is capable of it */
3952 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3953 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3954 if (ret) {
3955 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3956 mmc_hostname(mmc));
3957 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3958 }
3959 }
3960
3961 /* 32-bit mask as default & fallback */
3962 if (ret) {
3963 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3964 if (ret)
3965 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3966 mmc_hostname(mmc));
3967 }
3968
3969 return ret;
3970}
3971
3972void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3973 const u32 *caps, const u32 *caps1)
3974{
3975 u16 v;
3976 u64 dt_caps_mask = 0;
3977 u64 dt_caps = 0;
3978
3979 if (host->read_caps)
3980 return;
3981
3982 host->read_caps = true;
3983
3984 if (debug_quirks)
3985 host->quirks = debug_quirks;
3986
3987 if (debug_quirks2)
3988 host->quirks2 = debug_quirks2;
3989
3990 sdhci_do_reset(host, SDHCI_RESET_ALL);
3991
3992 if (host->v4_mode)
3993 sdhci_do_enable_v4_mode(host);
3994
3995 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3996 "sdhci-caps-mask", &dt_caps_mask);
3997 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3998 "sdhci-caps", &dt_caps);
3999
4000 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4001 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4002
4003 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4004 return;
4005
4006 if (caps) {
4007 host->caps = *caps;
4008 } else {
4009 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4010 host->caps &= ~lower_32_bits(dt_caps_mask);
4011 host->caps |= lower_32_bits(dt_caps);
4012 }
4013
4014 if (host->version < SDHCI_SPEC_300)
4015 return;
4016
4017 if (caps1) {
4018 host->caps1 = *caps1;
4019 } else {
4020 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4021 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4022 host->caps1 |= upper_32_bits(dt_caps);
4023 }
4024}
4025EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4026
4027static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4028{
4029 struct mmc_host *mmc = host->mmc;
4030 unsigned int max_blocks;
4031 unsigned int bounce_size;
4032 int ret;
4033
4034 /*
4035 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4036 * has diminishing returns, this is probably because SD/MMC
4037 * cards are usually optimized to handle this size of requests.
4038 */
4039 bounce_size = SZ_64K;
4040 /*
4041 * Adjust downwards to maximum request size if this is less
4042 * than our segment size, else hammer down the maximum
4043 * request size to the maximum buffer size.
4044 */
4045 if (mmc->max_req_size < bounce_size)
4046 bounce_size = mmc->max_req_size;
4047 max_blocks = bounce_size / 512;
4048
4049 /*
4050 * When we just support one segment, we can get significant
4051 * speedups by the help of a bounce buffer to group scattered
4052 * reads/writes together.
4053 */
4054 host->bounce_buffer = devm_kmalloc(mmc->parent,
4055 bounce_size,
4056 GFP_KERNEL);
4057 if (!host->bounce_buffer) {
4058 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4059 mmc_hostname(mmc),
4060 bounce_size);
4061 /*
4062 * Exiting with zero here makes sure we proceed with
4063 * mmc->max_segs == 1.
4064 */
4065 return;
4066 }
4067
4068 host->bounce_addr = dma_map_single(mmc->parent,
4069 host->bounce_buffer,
4070 bounce_size,
4071 DMA_BIDIRECTIONAL);
4072 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
4073 if (ret)
4074 /* Again fall back to max_segs == 1 */
4075 return;
4076 host->bounce_buffer_size = bounce_size;
4077
4078 /* Lie about this since we're bouncing */
4079 mmc->max_segs = max_blocks;
4080 mmc->max_seg_size = bounce_size;
4081 mmc->max_req_size = bounce_size;
4082
4083 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4084 mmc_hostname(mmc), max_blocks, bounce_size);
4085}
4086
4087static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4088{
4089 /*
4090 * According to SD Host Controller spec v4.10, bit[27] added from
4091 * version 4.10 in Capabilities Register is used as 64-bit System
4092 * Address support for V4 mode.
4093 */
4094 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4095 return host->caps & SDHCI_CAN_64BIT_V4;
4096
4097 return host->caps & SDHCI_CAN_64BIT;
4098}
4099
4100int sdhci_setup_host(struct sdhci_host *host)
4101{
4102 struct mmc_host *mmc;
4103 u32 max_current_caps;
4104 unsigned int ocr_avail;
4105 unsigned int override_timeout_clk;
4106 u32 max_clk;
4107 int ret = 0;
4108 bool enable_vqmmc = false;
4109
4110 WARN_ON(host == NULL);
4111 if (host == NULL)
4112 return -EINVAL;
4113
4114 mmc = host->mmc;
4115
4116 /*
4117 * If there are external regulators, get them. Note this must be done
4118 * early before resetting the host and reading the capabilities so that
4119 * the host can take the appropriate action if regulators are not
4120 * available.
4121 */
4122 if (!mmc->supply.vqmmc) {
4123 ret = mmc_regulator_get_supply(mmc);
4124 if (ret)
4125 return ret;
4126 enable_vqmmc = true;
4127 }
4128
4129 DBG("Version: 0x%08x | Present: 0x%08x\n",
4130 sdhci_readw(host, SDHCI_HOST_VERSION),
4131 sdhci_readl(host, SDHCI_PRESENT_STATE));
4132 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4133 sdhci_readl(host, SDHCI_CAPABILITIES),
4134 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4135
4136 sdhci_read_caps(host);
4137
4138 override_timeout_clk = host->timeout_clk;
4139
4140 if (host->version > SDHCI_SPEC_420) {
4141 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4142 mmc_hostname(mmc), host->version);
4143 }
4144
4145 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4146 host->flags |= SDHCI_USE_SDMA;
4147 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4148 DBG("Controller doesn't have SDMA capability\n");
4149 else
4150 host->flags |= SDHCI_USE_SDMA;
4151
4152 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4153 (host->flags & SDHCI_USE_SDMA)) {
4154 DBG("Disabling DMA as it is marked broken\n");
4155 host->flags &= ~SDHCI_USE_SDMA;
4156 }
4157
4158 if ((host->version >= SDHCI_SPEC_200) &&
4159 (host->caps & SDHCI_CAN_DO_ADMA2))
4160 host->flags |= SDHCI_USE_ADMA;
4161
4162 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4163 (host->flags & SDHCI_USE_ADMA)) {
4164 DBG("Disabling ADMA as it is marked broken\n");
4165 host->flags &= ~SDHCI_USE_ADMA;
4166 }
4167
4168 if (sdhci_can_64bit_dma(host))
4169 host->flags |= SDHCI_USE_64_BIT_DMA;
4170
4171 if (host->use_external_dma) {
4172 ret = sdhci_external_dma_init(host);
4173 if (ret == -EPROBE_DEFER)
4174 goto unreg;
4175 /*
4176 * Fall back to use the DMA/PIO integrated in standard SDHCI
4177 * instead of external DMA devices.
4178 */
4179 else if (ret)
4180 sdhci_switch_external_dma(host, false);
4181 /* Disable internal DMA sources */
4182 else
4183 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4184 }
4185
4186 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4187 if (host->ops->set_dma_mask)
4188 ret = host->ops->set_dma_mask(host);
4189 else
4190 ret = sdhci_set_dma_mask(host);
4191
4192 if (!ret && host->ops->enable_dma)
4193 ret = host->ops->enable_dma(host);
4194
4195 if (ret) {
4196 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4197 mmc_hostname(mmc));
4198 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4199
4200 ret = 0;
4201 }
4202 }
4203
4204 /* SDMA does not support 64-bit DMA if v4 mode not set */
4205 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4206 host->flags &= ~SDHCI_USE_SDMA;
4207
4208 if (host->flags & SDHCI_USE_ADMA) {
4209 dma_addr_t dma;
4210 void *buf;
4211
4212 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4213 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4214 else if (!host->alloc_desc_sz)
4215 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4216
4217 host->desc_sz = host->alloc_desc_sz;
4218 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4219
4220 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4221 /*
4222 * Use zalloc to zero the reserved high 32-bits of 128-bit
4223 * descriptors so that they never need to be written.
4224 */
4225 buf = dma_alloc_coherent(mmc_dev(mmc),
4226 host->align_buffer_sz + host->adma_table_sz,
4227 &dma, GFP_KERNEL);
4228 if (!buf) {
4229 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4230 mmc_hostname(mmc));
4231 host->flags &= ~SDHCI_USE_ADMA;
4232 } else if ((dma + host->align_buffer_sz) &
4233 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4234 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4235 mmc_hostname(mmc));
4236 host->flags &= ~SDHCI_USE_ADMA;
4237 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4238 host->adma_table_sz, buf, dma);
4239 } else {
4240 host->align_buffer = buf;
4241 host->align_addr = dma;
4242
4243 host->adma_table = buf + host->align_buffer_sz;
4244 host->adma_addr = dma + host->align_buffer_sz;
4245 }
4246 }
4247
4248 /*
4249 * If we use DMA, then it's up to the caller to set the DMA
4250 * mask, but PIO does not need the hw shim so we set a new
4251 * mask here in that case.
4252 */
4253 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4254 host->dma_mask = DMA_BIT_MASK(64);
4255 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4256 }
4257
4258 if (host->version >= SDHCI_SPEC_300)
4259 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4260 else
4261 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4262
4263 host->max_clk *= 1000000;
4264 if (host->max_clk == 0 || host->quirks &
4265 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4266 if (!host->ops->get_max_clock) {
4267 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4268 mmc_hostname(mmc));
4269 ret = -ENODEV;
4270 goto undma;
4271 }
4272 host->max_clk = host->ops->get_max_clock(host);
4273 }
4274
4275 /*
4276 * In case of Host Controller v3.00, find out whether clock
4277 * multiplier is supported.
4278 */
4279 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4280
4281 /*
4282 * In case the value in Clock Multiplier is 0, then programmable
4283 * clock mode is not supported, otherwise the actual clock
4284 * multiplier is one more than the value of Clock Multiplier
4285 * in the Capabilities Register.
4286 */
4287 if (host->clk_mul)
4288 host->clk_mul += 1;
4289
4290 /*
4291 * Set host parameters.
4292 */
4293 max_clk = host->max_clk;
4294
4295 if (host->ops->get_min_clock)
4296 mmc->f_min = host->ops->get_min_clock(host);
4297 else if (host->version >= SDHCI_SPEC_300) {
4298 if (host->clk_mul)
4299 max_clk = host->max_clk * host->clk_mul;
4300 /*
4301 * Divided Clock Mode minimum clock rate is always less than
4302 * Programmable Clock Mode minimum clock rate.
4303 */
4304 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4305 } else
4306 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4307
4308 if (!mmc->f_max || mmc->f_max > max_clk)
4309 mmc->f_max = max_clk;
4310
4311 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4312 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4313
4314 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4315 host->timeout_clk *= 1000;
4316
4317 if (host->timeout_clk == 0) {
4318 if (!host->ops->get_timeout_clock) {
4319 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4320 mmc_hostname(mmc));
4321 ret = -ENODEV;
4322 goto undma;
4323 }
4324
4325 host->timeout_clk =
4326 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4327 1000);
4328 }
4329
4330 if (override_timeout_clk)
4331 host->timeout_clk = override_timeout_clk;
4332
4333 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4334 host->ops->get_max_timeout_count(host) : 1 << 27;
4335 mmc->max_busy_timeout /= host->timeout_clk;
4336 }
4337
4338 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4339 !host->ops->get_max_timeout_count)
4340 mmc->max_busy_timeout = 0;
4341
4342 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4343 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4344
4345 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4346 host->flags |= SDHCI_AUTO_CMD12;
4347
4348 /*
4349 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4350 * For v4 mode, SDMA may use Auto-CMD23 as well.
4351 */
4352 if ((host->version >= SDHCI_SPEC_300) &&
4353 ((host->flags & SDHCI_USE_ADMA) ||
4354 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4355 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4356 host->flags |= SDHCI_AUTO_CMD23;
4357 DBG("Auto-CMD23 available\n");
4358 } else {
4359 DBG("Auto-CMD23 unavailable\n");
4360 }
4361
4362 /*
4363 * A controller may support 8-bit width, but the board itself
4364 * might not have the pins brought out. Boards that support
4365 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4366 * their platform code before calling sdhci_add_host(), and we
4367 * won't assume 8-bit width for hosts without that CAP.
4368 */
4369 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4370 mmc->caps |= MMC_CAP_4_BIT_DATA;
4371
4372 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4373 mmc->caps &= ~MMC_CAP_CMD23;
4374
4375 if (host->caps & SDHCI_CAN_DO_HISPD)
4376 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4377
4378 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4379 mmc_card_is_removable(mmc) &&
4380 mmc_gpio_get_cd(host->mmc) < 0)
4381 mmc->caps |= MMC_CAP_NEEDS_POLL;
4382
4383 if (!IS_ERR(mmc->supply.vqmmc)) {
4384 if (enable_vqmmc) {
4385 ret = regulator_enable(mmc->supply.vqmmc);
4386 host->sdhci_core_to_disable_vqmmc = !ret;
4387 }
4388
4389 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4390 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4391 1950000))
4392 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4393 SDHCI_SUPPORT_SDR50 |
4394 SDHCI_SUPPORT_DDR50);
4395
4396 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4397 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4398 3600000))
4399 host->flags &= ~SDHCI_SIGNALING_330;
4400
4401 if (ret) {
4402 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4403 mmc_hostname(mmc), ret);
4404 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4405 }
4406
4407 }
4408
4409 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4410 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4411 SDHCI_SUPPORT_DDR50);
4412 /*
4413 * The SDHCI controller in a SoC might support HS200/HS400
4414 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4415 * but if the board is modeled such that the IO lines are not
4416 * connected to 1.8v then HS200/HS400 cannot be supported.
4417 * Disable HS200/HS400 if the board does not have 1.8v connected
4418 * to the IO lines. (Applicable for other modes in 1.8v)
4419 */
4420 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4421 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4422 }
4423
4424 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4425 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4426 SDHCI_SUPPORT_DDR50))
4427 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4428
4429 /* SDR104 supports also implies SDR50 support */
4430 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4431 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4432 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4433 * field can be promoted to support HS200.
4434 */
4435 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4436 mmc->caps2 |= MMC_CAP2_HS200;
4437 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4438 mmc->caps |= MMC_CAP_UHS_SDR50;
4439 }
4440
4441 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4442 (host->caps1 & SDHCI_SUPPORT_HS400))
4443 mmc->caps2 |= MMC_CAP2_HS400;
4444
4445 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4446 (IS_ERR(mmc->supply.vqmmc) ||
4447 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4448 1300000)))
4449 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4450
4451 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4452 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4453 mmc->caps |= MMC_CAP_UHS_DDR50;
4454
4455 /* Does the host need tuning for SDR50? */
4456 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4457 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4458
4459 /* Driver Type(s) (A, C, D) supported by the host */
4460 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4461 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4462 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4463 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4464 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4465 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4466
4467 /* Initial value for re-tuning timer count */
4468 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4469 host->caps1);
4470
4471 /*
4472 * In case Re-tuning Timer is not disabled, the actual value of
4473 * re-tuning timer will be 2 ^ (n - 1).
4474 */
4475 if (host->tuning_count)
4476 host->tuning_count = 1 << (host->tuning_count - 1);
4477
4478 /* Re-tuning mode supported by the Host Controller */
4479 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4480
4481 ocr_avail = 0;
4482
4483 /*
4484 * According to SD Host Controller spec v3.00, if the Host System
4485 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4486 * the value is meaningful only if Voltage Support in the Capabilities
4487 * register is set. The actual current value is 4 times the register
4488 * value.
4489 */
4490 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4491 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4492 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4493 if (curr > 0) {
4494
4495 /* convert to SDHCI_MAX_CURRENT format */
4496 curr = curr/1000; /* convert to mA */
4497 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4498
4499 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4500 max_current_caps =
4501 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4502 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4503 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4504 }
4505 }
4506
4507 if (host->caps & SDHCI_CAN_VDD_330) {
4508 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4509
4510 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4511 max_current_caps) *
4512 SDHCI_MAX_CURRENT_MULTIPLIER;
4513 }
4514 if (host->caps & SDHCI_CAN_VDD_300) {
4515 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4516
4517 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4518 max_current_caps) *
4519 SDHCI_MAX_CURRENT_MULTIPLIER;
4520 }
4521 if (host->caps & SDHCI_CAN_VDD_180) {
4522 ocr_avail |= MMC_VDD_165_195;
4523
4524 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4525 max_current_caps) *
4526 SDHCI_MAX_CURRENT_MULTIPLIER;
4527 }
4528
4529 /* If OCR set by host, use it instead. */
4530 if (host->ocr_mask)
4531 ocr_avail = host->ocr_mask;
4532
4533 /* If OCR set by external regulators, give it highest prio. */
4534 if (mmc->ocr_avail)
4535 ocr_avail = mmc->ocr_avail;
4536
4537 mmc->ocr_avail = ocr_avail;
4538 mmc->ocr_avail_sdio = ocr_avail;
4539 if (host->ocr_avail_sdio)
4540 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4541 mmc->ocr_avail_sd = ocr_avail;
4542 if (host->ocr_avail_sd)
4543 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4544 else /* normal SD controllers don't support 1.8V */
4545 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4546 mmc->ocr_avail_mmc = ocr_avail;
4547 if (host->ocr_avail_mmc)
4548 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4549
4550 if (mmc->ocr_avail == 0) {
4551 pr_err("%s: Hardware doesn't report any support voltages.\n",
4552 mmc_hostname(mmc));
4553 ret = -ENODEV;
4554 goto unreg;
4555 }
4556
4557 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4558 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4559 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4560 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4561 host->flags |= SDHCI_SIGNALING_180;
4562
4563 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4564 host->flags |= SDHCI_SIGNALING_120;
4565
4566 spin_lock_init(&host->lock);
4567
4568 /*
4569 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4570 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4571 * is less anyway.
4572 */
4573 mmc->max_req_size = 524288;
4574
4575 /*
4576 * Maximum number of segments. Depends on if the hardware
4577 * can do scatter/gather or not.
4578 */
4579 if (host->flags & SDHCI_USE_ADMA) {
4580 mmc->max_segs = SDHCI_MAX_SEGS;
4581 } else if (host->flags & SDHCI_USE_SDMA) {
4582 mmc->max_segs = 1;
4583 if (swiotlb_max_segment()) {
4584 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4585 IO_TLB_SEGSIZE;
4586 mmc->max_req_size = min(mmc->max_req_size,
4587 max_req_size);
4588 }
4589 } else { /* PIO */
4590 mmc->max_segs = SDHCI_MAX_SEGS;
4591 }
4592
4593 /*
4594 * Maximum segment size. Could be one segment with the maximum number
4595 * of bytes. When doing hardware scatter/gather, each entry cannot
4596 * be larger than 64 KiB though.
4597 */
4598 if (host->flags & SDHCI_USE_ADMA) {
4599 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4600 mmc->max_seg_size = 65535;
4601 else
4602 mmc->max_seg_size = 65536;
4603 } else {
4604 mmc->max_seg_size = mmc->max_req_size;
4605 }
4606
4607 /*
4608 * Maximum block size. This varies from controller to controller and
4609 * is specified in the capabilities register.
4610 */
4611 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4612 mmc->max_blk_size = 2;
4613 } else {
4614 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4615 SDHCI_MAX_BLOCK_SHIFT;
4616 if (mmc->max_blk_size >= 3) {
4617 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4618 mmc_hostname(mmc));
4619 mmc->max_blk_size = 0;
4620 }
4621 }
4622
4623 mmc->max_blk_size = 512 << mmc->max_blk_size;
4624
4625 /*
4626 * Maximum block count.
4627 */
4628 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4629
4630 if (mmc->max_segs == 1)
4631 /* This may alter mmc->*_blk_* parameters */
4632 sdhci_allocate_bounce_buffer(host);
4633
4634 return 0;
4635
4636unreg:
4637 if (host->sdhci_core_to_disable_vqmmc)
4638 regulator_disable(mmc->supply.vqmmc);
4639undma:
4640 if (host->align_buffer)
4641 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4642 host->adma_table_sz, host->align_buffer,
4643 host->align_addr);
4644 host->adma_table = NULL;
4645 host->align_buffer = NULL;
4646
4647 return ret;
4648}
4649EXPORT_SYMBOL_GPL(sdhci_setup_host);
4650
4651void sdhci_cleanup_host(struct sdhci_host *host)
4652{
4653 struct mmc_host *mmc = host->mmc;
4654
4655 if (host->sdhci_core_to_disable_vqmmc)
4656 regulator_disable(mmc->supply.vqmmc);
4657
4658 if (host->align_buffer)
4659 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4660 host->adma_table_sz, host->align_buffer,
4661 host->align_addr);
4662
4663 if (host->use_external_dma)
4664 sdhci_external_dma_release(host);
4665
4666 host->adma_table = NULL;
4667 host->align_buffer = NULL;
4668}
4669EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4670
4671int __sdhci_add_host(struct sdhci_host *host)
4672{
4673 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4674 struct mmc_host *mmc = host->mmc;
4675 int ret;
4676
4677 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4678 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4679 mmc->caps2 &= ~MMC_CAP2_CQE;
4680 mmc->cqe_ops = NULL;
4681 }
4682
4683 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4684 if (!host->complete_wq)
4685 return -ENOMEM;
4686
4687 INIT_WORK(&host->complete_work, sdhci_complete_work);
4688
4689 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4690 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4691
4692 init_waitqueue_head(&host->buf_ready_int);
4693
4694 sdhci_init(host, 0);
4695
4696 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4697 IRQF_SHARED, mmc_hostname(mmc), host);
4698 if (ret) {
4699 pr_err("%s: Failed to request IRQ %d: %d\n",
4700 mmc_hostname(mmc), host->irq, ret);
4701 goto unwq;
4702 }
4703
4704 ret = sdhci_led_register(host);
4705 if (ret) {
4706 pr_err("%s: Failed to register LED device: %d\n",
4707 mmc_hostname(mmc), ret);
4708 goto unirq;
4709 }
4710
4711 ret = mmc_add_host(mmc);
4712 if (ret)
4713 goto unled;
4714
4715 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4716 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4717 host->use_external_dma ? "External DMA" :
4718 (host->flags & SDHCI_USE_ADMA) ?
4719 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4720 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4721
4722 sdhci_enable_card_detection(host);
4723
4724 return 0;
4725
4726unled:
4727 sdhci_led_unregister(host);
4728unirq:
4729 sdhci_do_reset(host, SDHCI_RESET_ALL);
4730 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4731 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4732 free_irq(host->irq, host);
4733unwq:
4734 destroy_workqueue(host->complete_wq);
4735
4736 return ret;
4737}
4738EXPORT_SYMBOL_GPL(__sdhci_add_host);
4739
4740int sdhci_add_host(struct sdhci_host *host)
4741{
4742 int ret;
4743
4744 ret = sdhci_setup_host(host);
4745 if (ret)
4746 return ret;
4747
4748 ret = __sdhci_add_host(host);
4749 if (ret)
4750 goto cleanup;
4751
4752 return 0;
4753
4754cleanup:
4755 sdhci_cleanup_host(host);
4756
4757 return ret;
4758}
4759EXPORT_SYMBOL_GPL(sdhci_add_host);
4760
4761void sdhci_remove_host(struct sdhci_host *host, int dead)
4762{
4763 struct mmc_host *mmc = host->mmc;
4764 unsigned long flags;
4765
4766 if (dead) {
4767 spin_lock_irqsave(&host->lock, flags);
4768
4769 host->flags |= SDHCI_DEVICE_DEAD;
4770
4771 if (sdhci_has_requests(host)) {
4772 pr_err("%s: Controller removed during "
4773 " transfer!\n", mmc_hostname(mmc));
4774 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4775 }
4776
4777 spin_unlock_irqrestore(&host->lock, flags);
4778 }
4779
4780 sdhci_disable_card_detection(host);
4781
4782 mmc_remove_host(mmc);
4783
4784 sdhci_led_unregister(host);
4785
4786 if (!dead)
4787 sdhci_do_reset(host, SDHCI_RESET_ALL);
4788
4789 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4790 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4791 free_irq(host->irq, host);
4792
4793 del_timer_sync(&host->timer);
4794 del_timer_sync(&host->data_timer);
4795
4796 destroy_workqueue(host->complete_wq);
4797
4798 if (host->sdhci_core_to_disable_vqmmc)
4799 regulator_disable(mmc->supply.vqmmc);
4800
4801 if (host->align_buffer)
4802 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4803 host->adma_table_sz, host->align_buffer,
4804 host->align_addr);
4805
4806 if (host->use_external_dma)
4807 sdhci_external_dma_release(host);
4808
4809 host->adma_table = NULL;
4810 host->align_buffer = NULL;
4811}
4812
4813EXPORT_SYMBOL_GPL(sdhci_remove_host);
4814
4815void sdhci_free_host(struct sdhci_host *host)
4816{
4817 mmc_free_host(host->mmc);
4818}
4819
4820EXPORT_SYMBOL_GPL(sdhci_free_host);
4821
4822/*****************************************************************************\
4823 * *
4824 * Driver init/exit *
4825 * *
4826\*****************************************************************************/
4827
4828static int __init sdhci_drv_init(void)
4829{
4830 pr_info(DRIVER_NAME
4831 ": Secure Digital Host Controller Interface driver\n");
4832 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4833
4834 return 0;
4835}
4836
4837static void __exit sdhci_drv_exit(void)
4838{
4839}
4840
4841module_init(sdhci_drv_init);
4842module_exit(sdhci_drv_exit);
4843
4844module_param(debug_quirks, uint, 0444);
4845module_param(debug_quirks2, uint, 0444);
4846
4847MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4848MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4849MODULE_LICENSE("GPL");
4850
4851MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4852MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");