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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
42MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
43MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
44
45/* address block */
46#define smnMP1_FIRMWARE_FLAGS 0x3010024
47
48static int psp_v12_0_init_microcode(struct psp_context *psp)
49{
50 struct amdgpu_device *adev = psp->adev;
51 char ucode_prefix[30];
52 int err = 0;
53 DRM_DEBUG("\n");
54
55 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
56
57 err = psp_init_asd_microcode(psp, ucode_prefix);
58 if (err)
59 return err;
60
61 err = psp_init_ta_microcode(psp, ucode_prefix);
62 if (err)
63 return err;
64
65 /* only supported on renoir */
66 if (!(adev->apu_flags & AMD_APU_IS_RENOIR))
67 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
68
69 return 0;
70}
71
72static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
73{
74 int ret;
75 uint32_t psp_gfxdrv_command_reg = 0;
76 struct amdgpu_device *adev = psp->adev;
77 uint32_t sol_reg;
78
79 /* Check sOS sign of life register to confirm sys driver and sOS
80 * are already been loaded.
81 */
82 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
83 if (sol_reg)
84 return 0;
85
86 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
87 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
88 0x80000000, 0x80000000, false);
89 if (ret)
90 return ret;
91
92 /* Copy PSP System Driver binary to memory */
93 psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
94
95 /* Provide the sys driver to bootloader */
96 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
97 (uint32_t)(psp->fw_pri_mc_addr >> 20));
98 psp_gfxdrv_command_reg = 1 << 16;
99 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
100 psp_gfxdrv_command_reg);
101
102 /* there might be handshake issue with hardware which needs delay */
103 mdelay(20);
104
105 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
106 0x80000000, 0x80000000, false);
107
108 return ret;
109}
110
111static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
112{
113 int ret;
114 unsigned int psp_gfxdrv_command_reg = 0;
115 struct amdgpu_device *adev = psp->adev;
116 uint32_t sol_reg;
117
118 /* Check sOS sign of life register to confirm sys driver and sOS
119 * are already been loaded.
120 */
121 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
122 if (sol_reg)
123 return 0;
124
125 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
126 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
127 0x80000000, 0x80000000, false);
128 if (ret)
129 return ret;
130
131 /* Copy Secure OS binary to PSP memory */
132 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
133
134 /* Provide the PSP secure OS to bootloader */
135 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
136 (uint32_t)(psp->fw_pri_mc_addr >> 20));
137 psp_gfxdrv_command_reg = 2 << 16;
138 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
139 psp_gfxdrv_command_reg);
140
141 /* there might be handshake issue with hardware which needs delay */
142 mdelay(20);
143 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
144 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
145 0, true);
146
147 return ret;
148}
149
150static void psp_v12_0_reroute_ih(struct psp_context *psp)
151{
152 struct amdgpu_device *adev = psp->adev;
153 uint32_t tmp;
154
155 /* Change IH ring for VMC */
156 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
157 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
158 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
159
160 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
161 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
162 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
163
164 mdelay(20);
165 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
166 0x80000000, 0x8000FFFF, false);
167
168 /* Change IH ring for UMC */
169 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
170 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
171
172 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
173 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
174 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
175
176 mdelay(20);
177 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
178 0x80000000, 0x8000FFFF, false);
179}
180
181static int psp_v12_0_ring_create(struct psp_context *psp,
182 enum psp_ring_type ring_type)
183{
184 int ret = 0;
185 unsigned int psp_ring_reg = 0;
186 struct psp_ring *ring = &psp->km_ring;
187 struct amdgpu_device *adev = psp->adev;
188
189 psp_v12_0_reroute_ih(psp);
190
191 if (amdgpu_sriov_vf(psp->adev)) {
192 /* Write low address of the ring to C2PMSG_102 */
193 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
194 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
195 /* Write high address of the ring to C2PMSG_103 */
196 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
197 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
198
199 /* Write the ring initialization command to C2PMSG_101 */
200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
201 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
202
203 /* there might be handshake issue with hardware which needs delay */
204 mdelay(20);
205
206 /* Wait for response flag (bit 31) in C2PMSG_101 */
207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
208 0x80000000, 0x8000FFFF, false);
209
210 } else {
211 /* Write low address of the ring to C2PMSG_69 */
212 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
214 /* Write high address of the ring to C2PMSG_70 */
215 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
216 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
217 /* Write size of ring to C2PMSG_71 */
218 psp_ring_reg = ring->ring_size;
219 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
220 /* Write the ring initialization command to C2PMSG_64 */
221 psp_ring_reg = ring_type;
222 psp_ring_reg = psp_ring_reg << 16;
223 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
224
225 /* there might be handshake issue with hardware which needs delay */
226 mdelay(20);
227
228 /* Wait for response flag (bit 31) in C2PMSG_64 */
229 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
230 0x80000000, 0x8000FFFF, false);
231 }
232
233 return ret;
234}
235
236static int psp_v12_0_ring_stop(struct psp_context *psp,
237 enum psp_ring_type ring_type)
238{
239 int ret = 0;
240 struct amdgpu_device *adev = psp->adev;
241
242 /* Write the ring destroy command*/
243 if (amdgpu_sriov_vf(adev))
244 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
245 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
246 else
247 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
248 GFX_CTRL_CMD_ID_DESTROY_RINGS);
249
250 /* there might be handshake issue with hardware which needs delay */
251 mdelay(20);
252
253 /* Wait for response flag (bit 31) */
254 if (amdgpu_sriov_vf(adev))
255 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
256 0x80000000, 0x80000000, false);
257 else
258 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
259 0x80000000, 0x80000000, false);
260
261 return ret;
262}
263
264static int psp_v12_0_ring_destroy(struct psp_context *psp,
265 enum psp_ring_type ring_type)
266{
267 int ret = 0;
268 struct psp_ring *ring = &psp->km_ring;
269 struct amdgpu_device *adev = psp->adev;
270
271 ret = psp_v12_0_ring_stop(psp, ring_type);
272 if (ret)
273 DRM_ERROR("Fail to stop psp ring\n");
274
275 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
276 &ring->ring_mem_mc_addr,
277 (void **)&ring->ring_mem);
278
279 return ret;
280}
281
282static int psp_v12_0_mode1_reset(struct psp_context *psp)
283{
284 int ret;
285 uint32_t offset;
286 struct amdgpu_device *adev = psp->adev;
287
288 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
289
290 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
291
292 if (ret) {
293 DRM_INFO("psp is not working correctly before mode1 reset!\n");
294 return -EINVAL;
295 }
296
297 /*send the mode 1 reset command*/
298 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
299
300 msleep(500);
301
302 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
303
304 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
305
306 if (ret) {
307 DRM_INFO("psp mode 1 reset failed!\n");
308 return -EINVAL;
309 }
310
311 DRM_INFO("psp mode1 reset succeed \n");
312
313 return 0;
314}
315
316static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
317{
318 uint32_t data;
319 struct amdgpu_device *adev = psp->adev;
320
321 if (amdgpu_sriov_vf(adev))
322 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
323 else
324 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
325
326 return data;
327}
328
329static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
330{
331 struct amdgpu_device *adev = psp->adev;
332
333 if (amdgpu_sriov_vf(adev)) {
334 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
335 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
336 } else
337 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
338}
339
340static const struct psp_funcs psp_v12_0_funcs = {
341 .init_microcode = psp_v12_0_init_microcode,
342 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
343 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
344 .ring_create = psp_v12_0_ring_create,
345 .ring_stop = psp_v12_0_ring_stop,
346 .ring_destroy = psp_v12_0_ring_destroy,
347 .mode1_reset = psp_v12_0_mode1_reset,
348 .ring_get_wptr = psp_v12_0_ring_get_wptr,
349 .ring_set_wptr = psp_v12_0_ring_set_wptr,
350};
351
352void psp_v12_0_set_psp_funcs(struct psp_context *psp)
353{
354 psp->funcs = &psp_v12_0_funcs;
355}
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41/* address block */
42#define smnMP1_FIRMWARE_FLAGS 0x3010024
43
44static int psp_v12_0_init_microcode(struct psp_context *psp)
45{
46 struct amdgpu_device *adev = psp->adev;
47 const char *chip_name;
48 int err = 0;
49
50 switch (adev->asic_type) {
51 case CHIP_RENOIR:
52 chip_name = "renoir";
53 break;
54 default:
55 BUG();
56 }
57
58 err = psp_init_asd_microcode(psp, chip_name);
59 return err;
60}
61
62static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
63{
64 int ret;
65 uint32_t psp_gfxdrv_command_reg = 0;
66 struct amdgpu_device *adev = psp->adev;
67 uint32_t sol_reg;
68
69 /* Check sOS sign of life register to confirm sys driver and sOS
70 * are already been loaded.
71 */
72 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
73 if (sol_reg)
74 return 0;
75
76 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
77 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
78 0x80000000, 0x80000000, false);
79 if (ret)
80 return ret;
81
82 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
83
84 /* Copy PSP System Driver binary to memory */
85 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
86
87 /* Provide the sys driver to bootloader */
88 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
89 (uint32_t)(psp->fw_pri_mc_addr >> 20));
90 psp_gfxdrv_command_reg = 1 << 16;
91 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
92 psp_gfxdrv_command_reg);
93
94 /* there might be handshake issue with hardware which needs delay */
95 mdelay(20);
96
97 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
98 0x80000000, 0x80000000, false);
99
100 return ret;
101}
102
103static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
104{
105 int ret;
106 unsigned int psp_gfxdrv_command_reg = 0;
107 struct amdgpu_device *adev = psp->adev;
108 uint32_t sol_reg;
109
110 /* Check sOS sign of life register to confirm sys driver and sOS
111 * are already been loaded.
112 */
113 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
114 if (sol_reg)
115 return 0;
116
117 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
118 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
119 0x80000000, 0x80000000, false);
120 if (ret)
121 return ret;
122
123 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
124
125 /* Copy Secure OS binary to PSP memory */
126 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
127
128 /* Provide the PSP secure OS to bootloader */
129 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
130 (uint32_t)(psp->fw_pri_mc_addr >> 20));
131 psp_gfxdrv_command_reg = 2 << 16;
132 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
133 psp_gfxdrv_command_reg);
134
135 /* there might be handshake issue with hardware which needs delay */
136 mdelay(20);
137 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
138 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
139 0, true);
140
141 return ret;
142}
143
144static void psp_v12_0_reroute_ih(struct psp_context *psp)
145{
146 struct amdgpu_device *adev = psp->adev;
147 uint32_t tmp;
148
149 /* Change IH ring for VMC */
150 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
151 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
152 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
153
154 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
155 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
156 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
157
158 mdelay(20);
159 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
160 0x80000000, 0x8000FFFF, false);
161
162 /* Change IH ring for UMC */
163 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
164 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
165
166 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
167 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
168 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
169
170 mdelay(20);
171 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
172 0x80000000, 0x8000FFFF, false);
173}
174
175static int psp_v12_0_ring_init(struct psp_context *psp,
176 enum psp_ring_type ring_type)
177{
178 int ret = 0;
179 struct psp_ring *ring;
180 struct amdgpu_device *adev = psp->adev;
181
182 psp_v12_0_reroute_ih(psp);
183
184 ring = &psp->km_ring;
185
186 ring->ring_type = ring_type;
187
188 /* allocate 4k Page of Local Frame Buffer memory for ring */
189 ring->ring_size = 0x1000;
190 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
191 AMDGPU_GEM_DOMAIN_VRAM,
192 &adev->firmware.rbuf,
193 &ring->ring_mem_mc_addr,
194 (void **)&ring->ring_mem);
195 if (ret) {
196 ring->ring_size = 0;
197 return ret;
198 }
199
200 return 0;
201}
202
203static int psp_v12_0_ring_create(struct psp_context *psp,
204 enum psp_ring_type ring_type)
205{
206 int ret = 0;
207 unsigned int psp_ring_reg = 0;
208 struct psp_ring *ring = &psp->km_ring;
209 struct amdgpu_device *adev = psp->adev;
210
211 if (amdgpu_sriov_vf(psp->adev)) {
212 /* Write low address of the ring to C2PMSG_102 */
213 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
215 /* Write high address of the ring to C2PMSG_103 */
216 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
217 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
218
219 /* Write the ring initialization command to C2PMSG_101 */
220 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
221 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
222
223 /* there might be handshake issue with hardware which needs delay */
224 mdelay(20);
225
226 /* Wait for response flag (bit 31) in C2PMSG_101 */
227 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
228 0x80000000, 0x8000FFFF, false);
229
230 } else {
231 /* Write low address of the ring to C2PMSG_69 */
232 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
233 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
234 /* Write high address of the ring to C2PMSG_70 */
235 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
236 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
237 /* Write size of ring to C2PMSG_71 */
238 psp_ring_reg = ring->ring_size;
239 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
240 /* Write the ring initialization command to C2PMSG_64 */
241 psp_ring_reg = ring_type;
242 psp_ring_reg = psp_ring_reg << 16;
243 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
244
245 /* there might be handshake issue with hardware which needs delay */
246 mdelay(20);
247
248 /* Wait for response flag (bit 31) in C2PMSG_64 */
249 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
250 0x80000000, 0x8000FFFF, false);
251 }
252
253 return ret;
254}
255
256static int psp_v12_0_ring_stop(struct psp_context *psp,
257 enum psp_ring_type ring_type)
258{
259 int ret = 0;
260 struct amdgpu_device *adev = psp->adev;
261
262 /* Write the ring destroy command*/
263 if (amdgpu_sriov_vf(adev))
264 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
265 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
266 else
267 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
268 GFX_CTRL_CMD_ID_DESTROY_RINGS);
269
270 /* there might be handshake issue with hardware which needs delay */
271 mdelay(20);
272
273 /* Wait for response flag (bit 31) */
274 if (amdgpu_sriov_vf(adev))
275 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
276 0x80000000, 0x80000000, false);
277 else
278 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
279 0x80000000, 0x80000000, false);
280
281 return ret;
282}
283
284static int psp_v12_0_ring_destroy(struct psp_context *psp,
285 enum psp_ring_type ring_type)
286{
287 int ret = 0;
288 struct psp_ring *ring = &psp->km_ring;
289 struct amdgpu_device *adev = psp->adev;
290
291 ret = psp_v12_0_ring_stop(psp, ring_type);
292 if (ret)
293 DRM_ERROR("Fail to stop psp ring\n");
294
295 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
296 &ring->ring_mem_mc_addr,
297 (void **)&ring->ring_mem);
298
299 return ret;
300}
301
302static int psp_v12_0_mode1_reset(struct psp_context *psp)
303{
304 int ret;
305 uint32_t offset;
306 struct amdgpu_device *adev = psp->adev;
307
308 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
309
310 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
311
312 if (ret) {
313 DRM_INFO("psp is not working correctly before mode1 reset!\n");
314 return -EINVAL;
315 }
316
317 /*send the mode 1 reset command*/
318 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
319
320 msleep(500);
321
322 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
323
324 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
325
326 if (ret) {
327 DRM_INFO("psp mode 1 reset failed!\n");
328 return -EINVAL;
329 }
330
331 DRM_INFO("psp mode1 reset succeed \n");
332
333 return 0;
334}
335
336static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
337{
338 uint32_t data;
339 struct amdgpu_device *adev = psp->adev;
340
341 if (amdgpu_sriov_vf(adev))
342 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
343 else
344 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
345
346 return data;
347}
348
349static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
350{
351 struct amdgpu_device *adev = psp->adev;
352
353 if (amdgpu_sriov_vf(adev)) {
354 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
355 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
356 } else
357 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
358}
359
360static const struct psp_funcs psp_v12_0_funcs = {
361 .init_microcode = psp_v12_0_init_microcode,
362 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
363 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
364 .ring_init = psp_v12_0_ring_init,
365 .ring_create = psp_v12_0_ring_create,
366 .ring_stop = psp_v12_0_ring_stop,
367 .ring_destroy = psp_v12_0_ring_destroy,
368 .mode1_reset = psp_v12_0_mode1_reset,
369 .ring_get_wptr = psp_v12_0_ring_get_wptr,
370 .ring_set_wptr = psp_v12_0_ring_set_wptr,
371};
372
373void psp_v12_0_set_psp_funcs(struct psp_context *psp)
374{
375 psp->funcs = &psp_v12_0_funcs;
376}