Loading...
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_edid.h>
25#include <drm/drm_fourcc.h>
26#include <drm/drm_modeset_helper.h>
27#include <drm/drm_modeset_helper_vtables.h>
28#include <drm/drm_vblank.h>
29
30#include "amdgpu.h"
31#include "amdgpu_pm.h"
32#include "amdgpu_i2c.h"
33#include "cikd.h"
34#include "atom.h"
35#include "amdgpu_atombios.h"
36#include "atombios_crtc.h"
37#include "atombios_encoders.h"
38#include "amdgpu_pll.h"
39#include "amdgpu_connectors.h"
40#include "amdgpu_display.h"
41#include "dce_v8_0.h"
42
43#include "dce/dce_8_0_d.h"
44#include "dce/dce_8_0_sh_mask.h"
45
46#include "gca/gfx_7_2_enum.h"
47
48#include "gmc/gmc_7_1_d.h"
49#include "gmc/gmc_7_1_sh_mask.h"
50
51#include "oss/oss_2_0_d.h"
52#include "oss/oss_2_0_sh_mask.h"
53
54static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
55static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56
57static const u32 crtc_offsets[6] = {
58 CRTC0_REGISTER_OFFSET,
59 CRTC1_REGISTER_OFFSET,
60 CRTC2_REGISTER_OFFSET,
61 CRTC3_REGISTER_OFFSET,
62 CRTC4_REGISTER_OFFSET,
63 CRTC5_REGISTER_OFFSET
64};
65
66static const u32 hpd_offsets[] = {
67 HPD0_REGISTER_OFFSET,
68 HPD1_REGISTER_OFFSET,
69 HPD2_REGISTER_OFFSET,
70 HPD3_REGISTER_OFFSET,
71 HPD4_REGISTER_OFFSET,
72 HPD5_REGISTER_OFFSET
73};
74
75static const uint32_t dig_offsets[] = {
76 CRTC0_REGISTER_OFFSET,
77 CRTC1_REGISTER_OFFSET,
78 CRTC2_REGISTER_OFFSET,
79 CRTC3_REGISTER_OFFSET,
80 CRTC4_REGISTER_OFFSET,
81 CRTC5_REGISTER_OFFSET,
82 (0x13830 - 0x7030) >> 2,
83};
84
85static const struct {
86 uint32_t reg;
87 uint32_t vblank;
88 uint32_t vline;
89 uint32_t hpd;
90
91} interrupt_status_offsets[6] = { {
92 .reg = mmDISP_INTERRUPT_STATUS,
93 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
116}, {
117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
119 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
121} };
122
123static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
124 u32 block_offset, u32 reg)
125{
126 unsigned long flags;
127 u32 r;
128
129 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
130 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
131 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
132 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
133
134 return r;
135}
136
137static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
138 u32 block_offset, u32 reg, u32 v)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
144 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
145 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
146}
147
148static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
149{
150 if (crtc >= adev->mode_info.num_crtc)
151 return 0;
152 else
153 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
154}
155
156static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
157{
158 unsigned i;
159
160 /* Enable pflip interrupts */
161 for (i = 0; i < adev->mode_info.num_crtc; i++)
162 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
163}
164
165static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
166{
167 unsigned i;
168
169 /* Disable pflip interrupts */
170 for (i = 0; i < adev->mode_info.num_crtc; i++)
171 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
172}
173
174/**
175 * dce_v8_0_page_flip - pageflip callback.
176 *
177 * @adev: amdgpu_device pointer
178 * @crtc_id: crtc to cleanup pageflip on
179 * @crtc_base: new address of the crtc (GPU MC address)
180 * @async: asynchronous flip
181 *
182 * Triggers the actual pageflip by updating the primary
183 * surface base address.
184 */
185static void dce_v8_0_page_flip(struct amdgpu_device *adev,
186 int crtc_id, u64 crtc_base, bool async)
187{
188 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
189 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
190
191 /* flip at hsync for async, default is vsync */
192 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
193 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
194 /* update pitch */
195 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
196 fb->pitches[0] / fb->format->cpp[0]);
197 /* update the primary scanout addresses */
198 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
199 upper_32_bits(crtc_base));
200 /* writing to the low address triggers the update */
201 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
202 lower_32_bits(crtc_base));
203 /* post the write */
204 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
205}
206
207static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
208 u32 *vbl, u32 *position)
209{
210 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
211 return -EINVAL;
212
213 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
214 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
215
216 return 0;
217}
218
219/**
220 * dce_v8_0_hpd_sense - hpd sense callback.
221 *
222 * @adev: amdgpu_device pointer
223 * @hpd: hpd (hotplug detect) pin
224 *
225 * Checks if a digital monitor is connected (evergreen+).
226 * Returns true if connected, false if not connected.
227 */
228static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
229 enum amdgpu_hpd_id hpd)
230{
231 bool connected = false;
232
233 if (hpd >= adev->mode_info.num_hpd)
234 return connected;
235
236 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
237 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
238 connected = true;
239
240 return connected;
241}
242
243/**
244 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
245 *
246 * @adev: amdgpu_device pointer
247 * @hpd: hpd (hotplug detect) pin
248 *
249 * Set the polarity of the hpd pin (evergreen+).
250 */
251static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
252 enum amdgpu_hpd_id hpd)
253{
254 u32 tmp;
255 bool connected = dce_v8_0_hpd_sense(adev, hpd);
256
257 if (hpd >= adev->mode_info.num_hpd)
258 return;
259
260 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
261 if (connected)
262 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
263 else
264 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
265 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
266}
267
268/**
269 * dce_v8_0_hpd_init - hpd setup callback.
270 *
271 * @adev: amdgpu_device pointer
272 *
273 * Setup the hpd pins used by the card (evergreen+).
274 * Enable the pin, set the polarity, and enable the hpd interrupts.
275 */
276static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
277{
278 struct drm_device *dev = adev_to_drm(adev);
279 struct drm_connector *connector;
280 struct drm_connector_list_iter iter;
281 u32 tmp;
282
283 drm_connector_list_iter_begin(dev, &iter);
284 drm_for_each_connector_iter(connector, &iter) {
285 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
286
287 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
288 continue;
289
290 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
291 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
292 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
293
294 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
295 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
296 /* don't try to enable hpd on eDP or LVDS avoid breaking the
297 * aux dp channel on imac and help (but not completely fix)
298 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
299 * also avoid interrupt storms during dpms.
300 */
301 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
302 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
303 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
304 continue;
305 }
306
307 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
308 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
309 }
310 drm_connector_list_iter_end(&iter);
311}
312
313/**
314 * dce_v8_0_hpd_fini - hpd tear down callback.
315 *
316 * @adev: amdgpu_device pointer
317 *
318 * Tear down the hpd pins used by the card (evergreen+).
319 * Disable the hpd interrupts.
320 */
321static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
322{
323 struct drm_device *dev = adev_to_drm(adev);
324 struct drm_connector *connector;
325 struct drm_connector_list_iter iter;
326 u32 tmp;
327
328 drm_connector_list_iter_begin(dev, &iter);
329 drm_for_each_connector_iter(connector, &iter) {
330 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
331
332 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
333 continue;
334
335 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
336 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
337 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
338
339 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
340 }
341 drm_connector_list_iter_end(&iter);
342}
343
344static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
345{
346 return mmDC_GPIO_HPD_A;
347}
348
349static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
350{
351 u32 crtc_hung = 0;
352 u32 crtc_status[6];
353 u32 i, j, tmp;
354
355 for (i = 0; i < adev->mode_info.num_crtc; i++) {
356 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
357 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
358 crtc_hung |= (1 << i);
359 }
360 }
361
362 for (j = 0; j < 10; j++) {
363 for (i = 0; i < adev->mode_info.num_crtc; i++) {
364 if (crtc_hung & (1 << i)) {
365 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
366 if (tmp != crtc_status[i])
367 crtc_hung &= ~(1 << i);
368 }
369 }
370 if (crtc_hung == 0)
371 return false;
372 udelay(100);
373 }
374
375 return true;
376}
377
378static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
379 bool render)
380{
381 u32 tmp;
382
383 /* Lockout access through VGA aperture*/
384 tmp = RREG32(mmVGA_HDP_CONTROL);
385 if (render)
386 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
387 else
388 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
389 WREG32(mmVGA_HDP_CONTROL, tmp);
390
391 /* disable VGA render */
392 tmp = RREG32(mmVGA_RENDER_CONTROL);
393 if (render)
394 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
395 else
396 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
397 WREG32(mmVGA_RENDER_CONTROL, tmp);
398}
399
400static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
401{
402 int num_crtc = 0;
403
404 switch (adev->asic_type) {
405 case CHIP_BONAIRE:
406 case CHIP_HAWAII:
407 num_crtc = 6;
408 break;
409 case CHIP_KAVERI:
410 num_crtc = 4;
411 break;
412 case CHIP_KABINI:
413 case CHIP_MULLINS:
414 num_crtc = 2;
415 break;
416 default:
417 num_crtc = 0;
418 }
419 return num_crtc;
420}
421
422void dce_v8_0_disable_dce(struct amdgpu_device *adev)
423{
424 /*Disable VGA render and enabled crtc, if has DCE engine*/
425 if (amdgpu_atombios_has_dce_engine_info(adev)) {
426 u32 tmp;
427 int crtc_enabled, i;
428
429 dce_v8_0_set_vga_render_state(adev, false);
430
431 /*Disable crtc*/
432 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
433 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
434 CRTC_CONTROL, CRTC_MASTER_EN);
435 if (crtc_enabled) {
436 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
437 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
438 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
439 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
440 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
441 }
442 }
443 }
444}
445
446static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
447{
448 struct drm_device *dev = encoder->dev;
449 struct amdgpu_device *adev = drm_to_adev(dev);
450 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
451 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
452 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
453 int bpc = 0;
454 u32 tmp = 0;
455 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
456
457 if (connector) {
458 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
459 bpc = amdgpu_connector_get_monitor_bpc(connector);
460 dither = amdgpu_connector->dither;
461 }
462
463 /* LVDS/eDP FMT is set up by atom */
464 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
465 return;
466
467 /* not needed for analog */
468 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
469 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
470 return;
471
472 if (bpc == 0)
473 return;
474
475 switch (bpc) {
476 case 6:
477 if (dither == AMDGPU_FMT_DITHER_ENABLE)
478 /* XXX sort out optimal dither settings */
479 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
480 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
481 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
482 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
483 else
484 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
485 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
486 break;
487 case 8:
488 if (dither == AMDGPU_FMT_DITHER_ENABLE)
489 /* XXX sort out optimal dither settings */
490 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
491 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
492 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
493 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
494 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
495 else
496 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
497 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
498 break;
499 case 10:
500 if (dither == AMDGPU_FMT_DITHER_ENABLE)
501 /* XXX sort out optimal dither settings */
502 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
503 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
504 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
505 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
506 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
507 else
508 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
509 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
510 break;
511 default:
512 /* not needed */
513 break;
514 }
515
516 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
517}
518
519
520/* display watermark setup */
521/**
522 * dce_v8_0_line_buffer_adjust - Set up the line buffer
523 *
524 * @adev: amdgpu_device pointer
525 * @amdgpu_crtc: the selected display controller
526 * @mode: the current display mode on the selected display
527 * controller
528 *
529 * Setup up the line buffer allocation for
530 * the selected display controller (CIK).
531 * Returns the line buffer size in pixels.
532 */
533static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
534 struct amdgpu_crtc *amdgpu_crtc,
535 struct drm_display_mode *mode)
536{
537 u32 tmp, buffer_alloc, i;
538 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
539 /*
540 * Line Buffer Setup
541 * There are 6 line buffers, one for each display controllers.
542 * There are 3 partitions per LB. Select the number of partitions
543 * to enable based on the display width. For display widths larger
544 * than 4096, you need use to use 2 display controllers and combine
545 * them using the stereo blender.
546 */
547 if (amdgpu_crtc->base.enabled && mode) {
548 if (mode->crtc_hdisplay < 1920) {
549 tmp = 1;
550 buffer_alloc = 2;
551 } else if (mode->crtc_hdisplay < 2560) {
552 tmp = 2;
553 buffer_alloc = 2;
554 } else if (mode->crtc_hdisplay < 4096) {
555 tmp = 0;
556 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
557 } else {
558 DRM_DEBUG_KMS("Mode too big for LB!\n");
559 tmp = 0;
560 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
561 }
562 } else {
563 tmp = 1;
564 buffer_alloc = 0;
565 }
566
567 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
568 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
569 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
570
571 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
572 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
573 for (i = 0; i < adev->usec_timeout; i++) {
574 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
575 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
576 break;
577 udelay(1);
578 }
579
580 if (amdgpu_crtc->base.enabled && mode) {
581 switch (tmp) {
582 case 0:
583 default:
584 return 4096 * 2;
585 case 1:
586 return 1920 * 2;
587 case 2:
588 return 2560 * 2;
589 }
590 }
591
592 /* controller not enabled, so no lb used */
593 return 0;
594}
595
596/**
597 * cik_get_number_of_dram_channels - get the number of dram channels
598 *
599 * @adev: amdgpu_device pointer
600 *
601 * Look up the number of video ram channels (CIK).
602 * Used for display watermark bandwidth calculations
603 * Returns the number of dram channels
604 */
605static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
606{
607 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
608
609 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
610 case 0:
611 default:
612 return 1;
613 case 1:
614 return 2;
615 case 2:
616 return 4;
617 case 3:
618 return 8;
619 case 4:
620 return 3;
621 case 5:
622 return 6;
623 case 6:
624 return 10;
625 case 7:
626 return 12;
627 case 8:
628 return 16;
629 }
630}
631
632struct dce8_wm_params {
633 u32 dram_channels; /* number of dram channels */
634 u32 yclk; /* bandwidth per dram data pin in kHz */
635 u32 sclk; /* engine clock in kHz */
636 u32 disp_clk; /* display clock in kHz */
637 u32 src_width; /* viewport width */
638 u32 active_time; /* active display time in ns */
639 u32 blank_time; /* blank time in ns */
640 bool interlaced; /* mode is interlaced */
641 fixed20_12 vsc; /* vertical scale ratio */
642 u32 num_heads; /* number of active crtcs */
643 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
644 u32 lb_size; /* line buffer allocated to pipe */
645 u32 vtaps; /* vertical scaler taps */
646};
647
648/**
649 * dce_v8_0_dram_bandwidth - get the dram bandwidth
650 *
651 * @wm: watermark calculation data
652 *
653 * Calculate the raw dram bandwidth (CIK).
654 * Used for display watermark bandwidth calculations
655 * Returns the dram bandwidth in MBytes/s
656 */
657static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
658{
659 /* Calculate raw DRAM Bandwidth */
660 fixed20_12 dram_efficiency; /* 0.7 */
661 fixed20_12 yclk, dram_channels, bandwidth;
662 fixed20_12 a;
663
664 a.full = dfixed_const(1000);
665 yclk.full = dfixed_const(wm->yclk);
666 yclk.full = dfixed_div(yclk, a);
667 dram_channels.full = dfixed_const(wm->dram_channels * 4);
668 a.full = dfixed_const(10);
669 dram_efficiency.full = dfixed_const(7);
670 dram_efficiency.full = dfixed_div(dram_efficiency, a);
671 bandwidth.full = dfixed_mul(dram_channels, yclk);
672 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
673
674 return dfixed_trunc(bandwidth);
675}
676
677/**
678 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
679 *
680 * @wm: watermark calculation data
681 *
682 * Calculate the dram bandwidth used for display (CIK).
683 * Used for display watermark bandwidth calculations
684 * Returns the dram bandwidth for display in MBytes/s
685 */
686static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
687{
688 /* Calculate DRAM Bandwidth and the part allocated to display. */
689 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
690 fixed20_12 yclk, dram_channels, bandwidth;
691 fixed20_12 a;
692
693 a.full = dfixed_const(1000);
694 yclk.full = dfixed_const(wm->yclk);
695 yclk.full = dfixed_div(yclk, a);
696 dram_channels.full = dfixed_const(wm->dram_channels * 4);
697 a.full = dfixed_const(10);
698 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
699 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
700 bandwidth.full = dfixed_mul(dram_channels, yclk);
701 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
702
703 return dfixed_trunc(bandwidth);
704}
705
706/**
707 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
708 *
709 * @wm: watermark calculation data
710 *
711 * Calculate the data return bandwidth used for display (CIK).
712 * Used for display watermark bandwidth calculations
713 * Returns the data return bandwidth in MBytes/s
714 */
715static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
716{
717 /* Calculate the display Data return Bandwidth */
718 fixed20_12 return_efficiency; /* 0.8 */
719 fixed20_12 sclk, bandwidth;
720 fixed20_12 a;
721
722 a.full = dfixed_const(1000);
723 sclk.full = dfixed_const(wm->sclk);
724 sclk.full = dfixed_div(sclk, a);
725 a.full = dfixed_const(10);
726 return_efficiency.full = dfixed_const(8);
727 return_efficiency.full = dfixed_div(return_efficiency, a);
728 a.full = dfixed_const(32);
729 bandwidth.full = dfixed_mul(a, sclk);
730 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
731
732 return dfixed_trunc(bandwidth);
733}
734
735/**
736 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
737 *
738 * @wm: watermark calculation data
739 *
740 * Calculate the dmif bandwidth used for display (CIK).
741 * Used for display watermark bandwidth calculations
742 * Returns the dmif bandwidth in MBytes/s
743 */
744static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
745{
746 /* Calculate the DMIF Request Bandwidth */
747 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
748 fixed20_12 disp_clk, bandwidth;
749 fixed20_12 a, b;
750
751 a.full = dfixed_const(1000);
752 disp_clk.full = dfixed_const(wm->disp_clk);
753 disp_clk.full = dfixed_div(disp_clk, a);
754 a.full = dfixed_const(32);
755 b.full = dfixed_mul(a, disp_clk);
756
757 a.full = dfixed_const(10);
758 disp_clk_request_efficiency.full = dfixed_const(8);
759 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
760
761 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
762
763 return dfixed_trunc(bandwidth);
764}
765
766/**
767 * dce_v8_0_available_bandwidth - get the min available bandwidth
768 *
769 * @wm: watermark calculation data
770 *
771 * Calculate the min available bandwidth used for display (CIK).
772 * Used for display watermark bandwidth calculations
773 * Returns the min available bandwidth in MBytes/s
774 */
775static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
776{
777 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
778 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
779 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
780 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
781
782 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
783}
784
785/**
786 * dce_v8_0_average_bandwidth - get the average available bandwidth
787 *
788 * @wm: watermark calculation data
789 *
790 * Calculate the average available bandwidth used for display (CIK).
791 * Used for display watermark bandwidth calculations
792 * Returns the average available bandwidth in MBytes/s
793 */
794static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
795{
796 /* Calculate the display mode Average Bandwidth
797 * DisplayMode should contain the source and destination dimensions,
798 * timing, etc.
799 */
800 fixed20_12 bpp;
801 fixed20_12 line_time;
802 fixed20_12 src_width;
803 fixed20_12 bandwidth;
804 fixed20_12 a;
805
806 a.full = dfixed_const(1000);
807 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
808 line_time.full = dfixed_div(line_time, a);
809 bpp.full = dfixed_const(wm->bytes_per_pixel);
810 src_width.full = dfixed_const(wm->src_width);
811 bandwidth.full = dfixed_mul(src_width, bpp);
812 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
813 bandwidth.full = dfixed_div(bandwidth, line_time);
814
815 return dfixed_trunc(bandwidth);
816}
817
818/**
819 * dce_v8_0_latency_watermark - get the latency watermark
820 *
821 * @wm: watermark calculation data
822 *
823 * Calculate the latency watermark (CIK).
824 * Used for display watermark bandwidth calculations
825 * Returns the latency watermark in ns
826 */
827static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
828{
829 /* First calculate the latency in ns */
830 u32 mc_latency = 2000; /* 2000 ns. */
831 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
832 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
833 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
834 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
835 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
836 (wm->num_heads * cursor_line_pair_return_time);
837 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
838 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
839 u32 tmp, dmif_size = 12288;
840 fixed20_12 a, b, c;
841
842 if (wm->num_heads == 0)
843 return 0;
844
845 a.full = dfixed_const(2);
846 b.full = dfixed_const(1);
847 if ((wm->vsc.full > a.full) ||
848 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
849 (wm->vtaps >= 5) ||
850 ((wm->vsc.full >= a.full) && wm->interlaced))
851 max_src_lines_per_dst_line = 4;
852 else
853 max_src_lines_per_dst_line = 2;
854
855 a.full = dfixed_const(available_bandwidth);
856 b.full = dfixed_const(wm->num_heads);
857 a.full = dfixed_div(a, b);
858 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
859 tmp = min(dfixed_trunc(a), tmp);
860
861 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
862
863 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
864 b.full = dfixed_const(1000);
865 c.full = dfixed_const(lb_fill_bw);
866 b.full = dfixed_div(c, b);
867 a.full = dfixed_div(a, b);
868 line_fill_time = dfixed_trunc(a);
869
870 if (line_fill_time < wm->active_time)
871 return latency;
872 else
873 return latency + (line_fill_time - wm->active_time);
874
875}
876
877/**
878 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
879 * average and available dram bandwidth
880 *
881 * @wm: watermark calculation data
882 *
883 * Check if the display average bandwidth fits in the display
884 * dram bandwidth (CIK).
885 * Used for display watermark bandwidth calculations
886 * Returns true if the display fits, false if not.
887 */
888static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
889{
890 if (dce_v8_0_average_bandwidth(wm) <=
891 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
892 return true;
893 else
894 return false;
895}
896
897/**
898 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
899 * average and available bandwidth
900 *
901 * @wm: watermark calculation data
902 *
903 * Check if the display average bandwidth fits in the display
904 * available bandwidth (CIK).
905 * Used for display watermark bandwidth calculations
906 * Returns true if the display fits, false if not.
907 */
908static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
909{
910 if (dce_v8_0_average_bandwidth(wm) <=
911 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
912 return true;
913 else
914 return false;
915}
916
917/**
918 * dce_v8_0_check_latency_hiding - check latency hiding
919 *
920 * @wm: watermark calculation data
921 *
922 * Check latency hiding (CIK).
923 * Used for display watermark bandwidth calculations
924 * Returns true if the display fits, false if not.
925 */
926static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
927{
928 u32 lb_partitions = wm->lb_size / wm->src_width;
929 u32 line_time = wm->active_time + wm->blank_time;
930 u32 latency_tolerant_lines;
931 u32 latency_hiding;
932 fixed20_12 a;
933
934 a.full = dfixed_const(1);
935 if (wm->vsc.full > a.full)
936 latency_tolerant_lines = 1;
937 else {
938 if (lb_partitions <= (wm->vtaps + 1))
939 latency_tolerant_lines = 1;
940 else
941 latency_tolerant_lines = 2;
942 }
943
944 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
945
946 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
947 return true;
948 else
949 return false;
950}
951
952/**
953 * dce_v8_0_program_watermarks - program display watermarks
954 *
955 * @adev: amdgpu_device pointer
956 * @amdgpu_crtc: the selected display controller
957 * @lb_size: line buffer size
958 * @num_heads: number of display controllers in use
959 *
960 * Calculate and program the display watermarks for the
961 * selected display controller (CIK).
962 */
963static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
964 struct amdgpu_crtc *amdgpu_crtc,
965 u32 lb_size, u32 num_heads)
966{
967 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
968 struct dce8_wm_params wm_low, wm_high;
969 u32 active_time;
970 u32 line_time = 0;
971 u32 latency_watermark_a = 0, latency_watermark_b = 0;
972 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
973
974 if (amdgpu_crtc->base.enabled && num_heads && mode) {
975 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
976 (u32)mode->clock);
977 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
978 (u32)mode->clock);
979 line_time = min_t(u32, line_time, 65535);
980
981 /* watermark for high clocks */
982 if (adev->pm.dpm_enabled) {
983 wm_high.yclk =
984 amdgpu_dpm_get_mclk(adev, false) * 10;
985 wm_high.sclk =
986 amdgpu_dpm_get_sclk(adev, false) * 10;
987 } else {
988 wm_high.yclk = adev->pm.current_mclk * 10;
989 wm_high.sclk = adev->pm.current_sclk * 10;
990 }
991
992 wm_high.disp_clk = mode->clock;
993 wm_high.src_width = mode->crtc_hdisplay;
994 wm_high.active_time = active_time;
995 wm_high.blank_time = line_time - wm_high.active_time;
996 wm_high.interlaced = false;
997 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
998 wm_high.interlaced = true;
999 wm_high.vsc = amdgpu_crtc->vsc;
1000 wm_high.vtaps = 1;
1001 if (amdgpu_crtc->rmx_type != RMX_OFF)
1002 wm_high.vtaps = 2;
1003 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1004 wm_high.lb_size = lb_size;
1005 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1006 wm_high.num_heads = num_heads;
1007
1008 /* set for high clocks */
1009 latency_watermark_a = min_t(u32, dce_v8_0_latency_watermark(&wm_high), 65535);
1010
1011 /* possibly force display priority to high */
1012 /* should really do this at mode validation time... */
1013 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1014 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1015 !dce_v8_0_check_latency_hiding(&wm_high) ||
1016 (adev->mode_info.disp_priority == 2)) {
1017 DRM_DEBUG_KMS("force priority to high\n");
1018 }
1019
1020 /* watermark for low clocks */
1021 if (adev->pm.dpm_enabled) {
1022 wm_low.yclk =
1023 amdgpu_dpm_get_mclk(adev, true) * 10;
1024 wm_low.sclk =
1025 amdgpu_dpm_get_sclk(adev, true) * 10;
1026 } else {
1027 wm_low.yclk = adev->pm.current_mclk * 10;
1028 wm_low.sclk = adev->pm.current_sclk * 10;
1029 }
1030
1031 wm_low.disp_clk = mode->clock;
1032 wm_low.src_width = mode->crtc_hdisplay;
1033 wm_low.active_time = active_time;
1034 wm_low.blank_time = line_time - wm_low.active_time;
1035 wm_low.interlaced = false;
1036 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1037 wm_low.interlaced = true;
1038 wm_low.vsc = amdgpu_crtc->vsc;
1039 wm_low.vtaps = 1;
1040 if (amdgpu_crtc->rmx_type != RMX_OFF)
1041 wm_low.vtaps = 2;
1042 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1043 wm_low.lb_size = lb_size;
1044 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1045 wm_low.num_heads = num_heads;
1046
1047 /* set for low clocks */
1048 latency_watermark_b = min_t(u32, dce_v8_0_latency_watermark(&wm_low), 65535);
1049
1050 /* possibly force display priority to high */
1051 /* should really do this at mode validation time... */
1052 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1053 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1054 !dce_v8_0_check_latency_hiding(&wm_low) ||
1055 (adev->mode_info.disp_priority == 2)) {
1056 DRM_DEBUG_KMS("force priority to high\n");
1057 }
1058 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1059 }
1060
1061 /* select wm A */
1062 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1063 tmp = wm_mask;
1064 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1065 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1066 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1067 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1068 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1069 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1070 /* select wm B */
1071 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1072 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1073 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1074 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1075 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1076 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1077 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1078 /* restore original selection */
1079 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1080
1081 /* save values for DPM */
1082 amdgpu_crtc->line_time = line_time;
1083 amdgpu_crtc->wm_high = latency_watermark_a;
1084 amdgpu_crtc->wm_low = latency_watermark_b;
1085 /* Save number of lines the linebuffer leads before the scanout */
1086 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1087}
1088
1089/**
1090 * dce_v8_0_bandwidth_update - program display watermarks
1091 *
1092 * @adev: amdgpu_device pointer
1093 *
1094 * Calculate and program the display watermarks and line
1095 * buffer allocation (CIK).
1096 */
1097static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1098{
1099 struct drm_display_mode *mode = NULL;
1100 u32 num_heads = 0, lb_size;
1101 int i;
1102
1103 amdgpu_display_update_priority(adev);
1104
1105 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1106 if (adev->mode_info.crtcs[i]->base.enabled)
1107 num_heads++;
1108 }
1109 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1110 mode = &adev->mode_info.crtcs[i]->base.mode;
1111 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1112 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1113 lb_size, num_heads);
1114 }
1115}
1116
1117static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1118{
1119 int i;
1120 u32 offset, tmp;
1121
1122 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1123 offset = adev->mode_info.audio.pin[i].offset;
1124 tmp = RREG32_AUDIO_ENDPT(offset,
1125 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1126 if (((tmp &
1127 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1128 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1129 adev->mode_info.audio.pin[i].connected = false;
1130 else
1131 adev->mode_info.audio.pin[i].connected = true;
1132 }
1133}
1134
1135static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1136{
1137 int i;
1138
1139 dce_v8_0_audio_get_connected_pins(adev);
1140
1141 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1142 if (adev->mode_info.audio.pin[i].connected)
1143 return &adev->mode_info.audio.pin[i];
1144 }
1145 DRM_ERROR("No connected audio pins found!\n");
1146 return NULL;
1147}
1148
1149static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1150{
1151 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1152 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1153 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1154 u32 offset;
1155
1156 if (!dig || !dig->afmt || !dig->afmt->pin)
1157 return;
1158
1159 offset = dig->afmt->offset;
1160
1161 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1162 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1163}
1164
1165static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1166 struct drm_display_mode *mode)
1167{
1168 struct drm_device *dev = encoder->dev;
1169 struct amdgpu_device *adev = drm_to_adev(dev);
1170 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1171 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1172 struct drm_connector *connector;
1173 struct drm_connector_list_iter iter;
1174 struct amdgpu_connector *amdgpu_connector = NULL;
1175 u32 tmp = 0, offset;
1176
1177 if (!dig || !dig->afmt || !dig->afmt->pin)
1178 return;
1179
1180 offset = dig->afmt->pin->offset;
1181
1182 drm_connector_list_iter_begin(dev, &iter);
1183 drm_for_each_connector_iter(connector, &iter) {
1184 if (connector->encoder == encoder) {
1185 amdgpu_connector = to_amdgpu_connector(connector);
1186 break;
1187 }
1188 }
1189 drm_connector_list_iter_end(&iter);
1190
1191 if (!amdgpu_connector) {
1192 DRM_ERROR("Couldn't find encoder's connector\n");
1193 return;
1194 }
1195
1196 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1197 if (connector->latency_present[1])
1198 tmp =
1199 (connector->video_latency[1] <<
1200 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1201 (connector->audio_latency[1] <<
1202 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1203 else
1204 tmp =
1205 (0 <<
1206 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1207 (0 <<
1208 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1209 } else {
1210 if (connector->latency_present[0])
1211 tmp =
1212 (connector->video_latency[0] <<
1213 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1214 (connector->audio_latency[0] <<
1215 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1216 else
1217 tmp =
1218 (0 <<
1219 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1220 (0 <<
1221 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1222
1223 }
1224 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1225}
1226
1227static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1228{
1229 struct drm_device *dev = encoder->dev;
1230 struct amdgpu_device *adev = drm_to_adev(dev);
1231 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1232 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1233 struct drm_connector *connector;
1234 struct drm_connector_list_iter iter;
1235 struct amdgpu_connector *amdgpu_connector = NULL;
1236 u32 offset, tmp;
1237 u8 *sadb = NULL;
1238 int sad_count;
1239
1240 if (!dig || !dig->afmt || !dig->afmt->pin)
1241 return;
1242
1243 offset = dig->afmt->pin->offset;
1244
1245 drm_connector_list_iter_begin(dev, &iter);
1246 drm_for_each_connector_iter(connector, &iter) {
1247 if (connector->encoder == encoder) {
1248 amdgpu_connector = to_amdgpu_connector(connector);
1249 break;
1250 }
1251 }
1252 drm_connector_list_iter_end(&iter);
1253
1254 if (!amdgpu_connector) {
1255 DRM_ERROR("Couldn't find encoder's connector\n");
1256 return;
1257 }
1258
1259 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1260 if (sad_count < 0) {
1261 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1262 sad_count = 0;
1263 }
1264
1265 /* program the speaker allocation */
1266 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1267 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1268 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1269 /* set HDMI mode */
1270 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1271 if (sad_count)
1272 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1273 else
1274 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1275 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1276
1277 kfree(sadb);
1278}
1279
1280static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1281{
1282 struct drm_device *dev = encoder->dev;
1283 struct amdgpu_device *adev = drm_to_adev(dev);
1284 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1285 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1286 u32 offset;
1287 struct drm_connector *connector;
1288 struct drm_connector_list_iter iter;
1289 struct amdgpu_connector *amdgpu_connector = NULL;
1290 struct cea_sad *sads;
1291 int i, sad_count;
1292
1293 static const u16 eld_reg_to_type[][2] = {
1294 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1295 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1296 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1297 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1298 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1299 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1300 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1301 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1302 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1303 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1304 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1305 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1306 };
1307
1308 if (!dig || !dig->afmt || !dig->afmt->pin)
1309 return;
1310
1311 offset = dig->afmt->pin->offset;
1312
1313 drm_connector_list_iter_begin(dev, &iter);
1314 drm_for_each_connector_iter(connector, &iter) {
1315 if (connector->encoder == encoder) {
1316 amdgpu_connector = to_amdgpu_connector(connector);
1317 break;
1318 }
1319 }
1320 drm_connector_list_iter_end(&iter);
1321
1322 if (!amdgpu_connector) {
1323 DRM_ERROR("Couldn't find encoder's connector\n");
1324 return;
1325 }
1326
1327 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1328 if (sad_count < 0)
1329 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1330 if (sad_count <= 0)
1331 return;
1332 BUG_ON(!sads);
1333
1334 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1335 u32 value = 0;
1336 u8 stereo_freqs = 0;
1337 int max_channels = -1;
1338 int j;
1339
1340 for (j = 0; j < sad_count; j++) {
1341 struct cea_sad *sad = &sads[j];
1342
1343 if (sad->format == eld_reg_to_type[i][1]) {
1344 if (sad->channels > max_channels) {
1345 value = (sad->channels <<
1346 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1347 (sad->byte2 <<
1348 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1349 (sad->freq <<
1350 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1351 max_channels = sad->channels;
1352 }
1353
1354 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1355 stereo_freqs |= sad->freq;
1356 else
1357 break;
1358 }
1359 }
1360
1361 value |= (stereo_freqs <<
1362 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1363
1364 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1365 }
1366
1367 kfree(sads);
1368}
1369
1370static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1371 struct amdgpu_audio_pin *pin,
1372 bool enable)
1373{
1374 if (!pin)
1375 return;
1376
1377 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1378 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1379}
1380
1381static const u32 pin_offsets[7] = {
1382 (0x1780 - 0x1780),
1383 (0x1786 - 0x1780),
1384 (0x178c - 0x1780),
1385 (0x1792 - 0x1780),
1386 (0x1798 - 0x1780),
1387 (0x179d - 0x1780),
1388 (0x17a4 - 0x1780),
1389};
1390
1391static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1392{
1393 int i;
1394
1395 if (!amdgpu_audio)
1396 return 0;
1397
1398 adev->mode_info.audio.enabled = true;
1399
1400 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1401 adev->mode_info.audio.num_pins = 7;
1402 else if ((adev->asic_type == CHIP_KABINI) ||
1403 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1404 adev->mode_info.audio.num_pins = 3;
1405 else if ((adev->asic_type == CHIP_BONAIRE) ||
1406 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1407 adev->mode_info.audio.num_pins = 7;
1408 else
1409 adev->mode_info.audio.num_pins = 3;
1410
1411 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1412 adev->mode_info.audio.pin[i].channels = -1;
1413 adev->mode_info.audio.pin[i].rate = -1;
1414 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1415 adev->mode_info.audio.pin[i].status_bits = 0;
1416 adev->mode_info.audio.pin[i].category_code = 0;
1417 adev->mode_info.audio.pin[i].connected = false;
1418 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1419 adev->mode_info.audio.pin[i].id = i;
1420 /* disable audio. it will be set up later */
1421 /* XXX remove once we switch to ip funcs */
1422 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1423 }
1424
1425 return 0;
1426}
1427
1428static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1429{
1430 int i;
1431
1432 if (!amdgpu_audio)
1433 return;
1434
1435 if (!adev->mode_info.audio.enabled)
1436 return;
1437
1438 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1439 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1440
1441 adev->mode_info.audio.enabled = false;
1442}
1443
1444/*
1445 * update the N and CTS parameters for a given pixel clock rate
1446 */
1447static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1448{
1449 struct drm_device *dev = encoder->dev;
1450 struct amdgpu_device *adev = drm_to_adev(dev);
1451 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1452 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1453 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1454 uint32_t offset = dig->afmt->offset;
1455
1456 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1457 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1458
1459 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1460 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1461
1462 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1463 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1464}
1465
1466/*
1467 * build a HDMI Video Info Frame
1468 */
1469static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1470 void *buffer, size_t size)
1471{
1472 struct drm_device *dev = encoder->dev;
1473 struct amdgpu_device *adev = drm_to_adev(dev);
1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476 uint32_t offset = dig->afmt->offset;
1477 uint8_t *frame = buffer + 3;
1478 uint8_t *header = buffer;
1479
1480 WREG32(mmAFMT_AVI_INFO0 + offset,
1481 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1482 WREG32(mmAFMT_AVI_INFO1 + offset,
1483 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1484 WREG32(mmAFMT_AVI_INFO2 + offset,
1485 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1486 WREG32(mmAFMT_AVI_INFO3 + offset,
1487 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1488}
1489
1490static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1491{
1492 struct drm_device *dev = encoder->dev;
1493 struct amdgpu_device *adev = drm_to_adev(dev);
1494 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1495 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1496 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1497 u32 dto_phase = 24 * 1000;
1498 u32 dto_modulo = clock;
1499
1500 if (!dig || !dig->afmt)
1501 return;
1502
1503 /* XXX two dtos; generally use dto0 for hdmi */
1504 /* Express [24MHz / target pixel clock] as an exact rational
1505 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1506 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1507 */
1508 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1509 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1510 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1511}
1512
1513/*
1514 * update the info frames with the data from the current display mode
1515 */
1516static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1517 struct drm_display_mode *mode)
1518{
1519 struct drm_device *dev = encoder->dev;
1520 struct amdgpu_device *adev = drm_to_adev(dev);
1521 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1522 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1523 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1524 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1525 struct hdmi_avi_infoframe frame;
1526 uint32_t offset, val;
1527 ssize_t err;
1528 int bpc = 8;
1529
1530 if (!dig || !dig->afmt)
1531 return;
1532
1533 /* Silent, r600_hdmi_enable will raise WARN for us */
1534 if (!dig->afmt->enabled)
1535 return;
1536
1537 offset = dig->afmt->offset;
1538
1539 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1540 if (encoder->crtc) {
1541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1542 bpc = amdgpu_crtc->bpc;
1543 }
1544
1545 /* disable audio prior to setting up hw */
1546 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1547 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1548
1549 dce_v8_0_audio_set_dto(encoder, mode->clock);
1550
1551 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1552 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1553
1554 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1555
1556 val = RREG32(mmHDMI_CONTROL + offset);
1557 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1558 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1559
1560 switch (bpc) {
1561 case 0:
1562 case 6:
1563 case 8:
1564 case 16:
1565 default:
1566 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1567 connector->name, bpc);
1568 break;
1569 case 10:
1570 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1571 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1572 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1573 connector->name);
1574 break;
1575 case 12:
1576 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1577 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1578 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1579 connector->name);
1580 break;
1581 }
1582
1583 WREG32(mmHDMI_CONTROL + offset, val);
1584
1585 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1586 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1587 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1588 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1589
1590 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1591 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1592 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1593
1594 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1595 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1596
1597 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1598 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1599
1600 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1601
1602 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1603 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1604 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1605
1606 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1607 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1608
1609 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1610
1611 if (bpc > 8)
1612 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1613 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1614 else
1615 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1616 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1617 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1618
1619 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1620
1621 WREG32(mmAFMT_60958_0 + offset,
1622 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1623
1624 WREG32(mmAFMT_60958_1 + offset,
1625 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1626
1627 WREG32(mmAFMT_60958_2 + offset,
1628 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1629 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1630 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1631 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1632 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1633 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1634
1635 dce_v8_0_audio_write_speaker_allocation(encoder);
1636
1637
1638 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1639 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1640
1641 dce_v8_0_afmt_audio_select_pin(encoder);
1642 dce_v8_0_audio_write_sad_regs(encoder);
1643 dce_v8_0_audio_write_latency_fields(encoder, mode);
1644
1645 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1646 if (err < 0) {
1647 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1648 return;
1649 }
1650
1651 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1652 if (err < 0) {
1653 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1654 return;
1655 }
1656
1657 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1658
1659 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1660 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1661 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1662
1663 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1664 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1665 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1666
1667 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1668 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1669
1670 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1671 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1672 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1673 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1674
1675 /* enable audio after setting up hw */
1676 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1677}
1678
1679static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1680{
1681 struct drm_device *dev = encoder->dev;
1682 struct amdgpu_device *adev = drm_to_adev(dev);
1683 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1684 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1685
1686 if (!dig || !dig->afmt)
1687 return;
1688
1689 /* Silent, r600_hdmi_enable will raise WARN for us */
1690 if (enable && dig->afmt->enabled)
1691 return;
1692 if (!enable && !dig->afmt->enabled)
1693 return;
1694
1695 if (!enable && dig->afmt->pin) {
1696 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1697 dig->afmt->pin = NULL;
1698 }
1699
1700 dig->afmt->enabled = enable;
1701
1702 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1703 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1704}
1705
1706static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1707{
1708 int i;
1709
1710 for (i = 0; i < adev->mode_info.num_dig; i++)
1711 adev->mode_info.afmt[i] = NULL;
1712
1713 /* DCE8 has audio blocks tied to DIG encoders */
1714 for (i = 0; i < adev->mode_info.num_dig; i++) {
1715 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1716 if (adev->mode_info.afmt[i]) {
1717 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1718 adev->mode_info.afmt[i]->id = i;
1719 } else {
1720 int j;
1721 for (j = 0; j < i; j++) {
1722 kfree(adev->mode_info.afmt[j]);
1723 adev->mode_info.afmt[j] = NULL;
1724 }
1725 return -ENOMEM;
1726 }
1727 }
1728 return 0;
1729}
1730
1731static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1732{
1733 int i;
1734
1735 for (i = 0; i < adev->mode_info.num_dig; i++) {
1736 kfree(adev->mode_info.afmt[i]);
1737 adev->mode_info.afmt[i] = NULL;
1738 }
1739}
1740
1741static const u32 vga_control_regs[6] = {
1742 mmD1VGA_CONTROL,
1743 mmD2VGA_CONTROL,
1744 mmD3VGA_CONTROL,
1745 mmD4VGA_CONTROL,
1746 mmD5VGA_CONTROL,
1747 mmD6VGA_CONTROL,
1748};
1749
1750static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1751{
1752 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1753 struct drm_device *dev = crtc->dev;
1754 struct amdgpu_device *adev = drm_to_adev(dev);
1755 u32 vga_control;
1756
1757 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1758 if (enable)
1759 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1760 else
1761 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1762}
1763
1764static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1765{
1766 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1767 struct drm_device *dev = crtc->dev;
1768 struct amdgpu_device *adev = drm_to_adev(dev);
1769
1770 if (enable)
1771 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1772 else
1773 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1774}
1775
1776static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1777 struct drm_framebuffer *fb,
1778 int x, int y, int atomic)
1779{
1780 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1781 struct drm_device *dev = crtc->dev;
1782 struct amdgpu_device *adev = drm_to_adev(dev);
1783 struct drm_framebuffer *target_fb;
1784 struct drm_gem_object *obj;
1785 struct amdgpu_bo *abo;
1786 uint64_t fb_location, tiling_flags;
1787 uint32_t fb_format, fb_pitch_pixels;
1788 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1789 u32 pipe_config;
1790 u32 viewport_w, viewport_h;
1791 int r;
1792 bool bypass_lut = false;
1793
1794 /* no fb bound */
1795 if (!atomic && !crtc->primary->fb) {
1796 DRM_DEBUG_KMS("No FB bound\n");
1797 return 0;
1798 }
1799
1800 if (atomic)
1801 target_fb = fb;
1802 else
1803 target_fb = crtc->primary->fb;
1804
1805 /* If atomic, assume fb object is pinned & idle & fenced and
1806 * just update base pointers
1807 */
1808 obj = target_fb->obj[0];
1809 abo = gem_to_amdgpu_bo(obj);
1810 r = amdgpu_bo_reserve(abo, false);
1811 if (unlikely(r != 0))
1812 return r;
1813
1814 if (!atomic) {
1815 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1816 if (unlikely(r != 0)) {
1817 amdgpu_bo_unreserve(abo);
1818 return -EINVAL;
1819 }
1820 }
1821 fb_location = amdgpu_bo_gpu_offset(abo);
1822
1823 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1824 amdgpu_bo_unreserve(abo);
1825
1826 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1827
1828 switch (target_fb->format->format) {
1829 case DRM_FORMAT_C8:
1830 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1831 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1832 break;
1833 case DRM_FORMAT_XRGB4444:
1834 case DRM_FORMAT_ARGB4444:
1835 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1836 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1837#ifdef __BIG_ENDIAN
1838 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1839#endif
1840 break;
1841 case DRM_FORMAT_XRGB1555:
1842 case DRM_FORMAT_ARGB1555:
1843 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1844 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1845#ifdef __BIG_ENDIAN
1846 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1847#endif
1848 break;
1849 case DRM_FORMAT_BGRX5551:
1850 case DRM_FORMAT_BGRA5551:
1851 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1852 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1853#ifdef __BIG_ENDIAN
1854 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1855#endif
1856 break;
1857 case DRM_FORMAT_RGB565:
1858 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1859 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1860#ifdef __BIG_ENDIAN
1861 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1862#endif
1863 break;
1864 case DRM_FORMAT_XRGB8888:
1865 case DRM_FORMAT_ARGB8888:
1866 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1867 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1868#ifdef __BIG_ENDIAN
1869 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1870#endif
1871 break;
1872 case DRM_FORMAT_XRGB2101010:
1873 case DRM_FORMAT_ARGB2101010:
1874 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1875 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1876#ifdef __BIG_ENDIAN
1877 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1878#endif
1879 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1880 bypass_lut = true;
1881 break;
1882 case DRM_FORMAT_BGRX1010102:
1883 case DRM_FORMAT_BGRA1010102:
1884 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1885 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1886#ifdef __BIG_ENDIAN
1887 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1888#endif
1889 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1890 bypass_lut = true;
1891 break;
1892 case DRM_FORMAT_XBGR8888:
1893 case DRM_FORMAT_ABGR8888:
1894 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1895 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1896 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1897 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1898#ifdef __BIG_ENDIAN
1899 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1900#endif
1901 break;
1902 default:
1903 DRM_ERROR("Unsupported screen format %p4cc\n",
1904 &target_fb->format->format);
1905 return -EINVAL;
1906 }
1907
1908 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1909 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1910
1911 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1912 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1913 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1914 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1915 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1916
1917 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1918 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1919 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1920 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1921 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1922 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1923 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1924 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1925 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1926 }
1927
1928 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1929
1930 dce_v8_0_vga_enable(crtc, false);
1931
1932 /* Make sure surface address is updated at vertical blank rather than
1933 * horizontal blank
1934 */
1935 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1936
1937 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1938 upper_32_bits(fb_location));
1939 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1940 upper_32_bits(fb_location));
1941 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1942 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1943 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1944 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1945 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1946 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1947
1948 /*
1949 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1950 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1951 * retain the full precision throughout the pipeline.
1952 */
1953 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1954 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1955 ~LUT_10BIT_BYPASS_EN);
1956
1957 if (bypass_lut)
1958 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1959
1960 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1961 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1962 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1963 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1964 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1965 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1966
1967 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1968 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1969
1970 dce_v8_0_grph_enable(crtc, true);
1971
1972 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1973 target_fb->height);
1974
1975 x &= ~3;
1976 y &= ~1;
1977 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1978 (x << 16) | y);
1979 viewport_w = crtc->mode.hdisplay;
1980 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1981 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1982 (viewport_w << 16) | viewport_h);
1983
1984 /* set pageflip to happen anywhere in vblank interval */
1985 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1986
1987 if (!atomic && fb && fb != crtc->primary->fb) {
1988 abo = gem_to_amdgpu_bo(fb->obj[0]);
1989 r = amdgpu_bo_reserve(abo, true);
1990 if (unlikely(r != 0))
1991 return r;
1992 amdgpu_bo_unpin(abo);
1993 amdgpu_bo_unreserve(abo);
1994 }
1995
1996 /* Bytes per pixel may have changed */
1997 dce_v8_0_bandwidth_update(adev);
1998
1999 return 0;
2000}
2001
2002static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2003 struct drm_display_mode *mode)
2004{
2005 struct drm_device *dev = crtc->dev;
2006 struct amdgpu_device *adev = drm_to_adev(dev);
2007 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2008
2009 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2010 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2011 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2012 else
2013 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2014}
2015
2016static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2017{
2018 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2019 struct drm_device *dev = crtc->dev;
2020 struct amdgpu_device *adev = drm_to_adev(dev);
2021 u16 *r, *g, *b;
2022 int i;
2023
2024 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2025
2026 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2027 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2028 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2029 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2030 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2031 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2032 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2033 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2034 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2035 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2036
2037 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2038
2039 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2040 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2041 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2042
2043 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2044 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2045 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2046
2047 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2048 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2049
2050 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2051 r = crtc->gamma_store;
2052 g = r + crtc->gamma_size;
2053 b = g + crtc->gamma_size;
2054 for (i = 0; i < 256; i++) {
2055 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2056 ((*r++ & 0xffc0) << 14) |
2057 ((*g++ & 0xffc0) << 4) |
2058 (*b++ >> 6));
2059 }
2060
2061 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2062 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2063 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2064 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2065 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2066 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2067 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2068 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2069 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2070 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2071 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2072 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2073 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2074 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2075 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2076 /* XXX this only needs to be programmed once per crtc at startup,
2077 * not sure where the best place for it is
2078 */
2079 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2080 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2081}
2082
2083static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2084{
2085 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2086 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2087
2088 switch (amdgpu_encoder->encoder_id) {
2089 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2090 if (dig->linkb)
2091 return 1;
2092 else
2093 return 0;
2094 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2095 if (dig->linkb)
2096 return 3;
2097 else
2098 return 2;
2099 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2100 if (dig->linkb)
2101 return 5;
2102 else
2103 return 4;
2104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2105 return 6;
2106 default:
2107 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2108 return 0;
2109 }
2110}
2111
2112/**
2113 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2114 *
2115 * @crtc: drm crtc
2116 *
2117 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2118 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2119 * monitors a dedicated PPLL must be used. If a particular board has
2120 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2121 * as there is no need to program the PLL itself. If we are not able to
2122 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2123 * avoid messing up an existing monitor.
2124 *
2125 * Asic specific PLL information
2126 *
2127 * DCE 8.x
2128 * KB/KV
2129 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2130 * CI
2131 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2132 *
2133 */
2134static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2135{
2136 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2137 struct drm_device *dev = crtc->dev;
2138 struct amdgpu_device *adev = drm_to_adev(dev);
2139 u32 pll_in_use;
2140 int pll;
2141
2142 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2143 if (adev->clock.dp_extclk)
2144 /* skip PPLL programming if using ext clock */
2145 return ATOM_PPLL_INVALID;
2146 else {
2147 /* use the same PPLL for all DP monitors */
2148 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2149 if (pll != ATOM_PPLL_INVALID)
2150 return pll;
2151 }
2152 } else {
2153 /* use the same PPLL for all monitors with the same clock */
2154 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2155 if (pll != ATOM_PPLL_INVALID)
2156 return pll;
2157 }
2158 /* otherwise, pick one of the plls */
2159 if ((adev->asic_type == CHIP_KABINI) ||
2160 (adev->asic_type == CHIP_MULLINS)) {
2161 /* KB/ML has PPLL1 and PPLL2 */
2162 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2163 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2164 return ATOM_PPLL2;
2165 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2166 return ATOM_PPLL1;
2167 DRM_ERROR("unable to allocate a PPLL\n");
2168 return ATOM_PPLL_INVALID;
2169 } else {
2170 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2171 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2172 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2173 return ATOM_PPLL2;
2174 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2175 return ATOM_PPLL1;
2176 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2177 return ATOM_PPLL0;
2178 DRM_ERROR("unable to allocate a PPLL\n");
2179 return ATOM_PPLL_INVALID;
2180 }
2181 return ATOM_PPLL_INVALID;
2182}
2183
2184static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2185{
2186 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2187 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2188 uint32_t cur_lock;
2189
2190 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2191 if (lock)
2192 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2193 else
2194 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2195 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2196}
2197
2198static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2199{
2200 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2201 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2202
2203 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2204 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2205 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2206}
2207
2208static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2209{
2210 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2211 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2212
2213 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2214 upper_32_bits(amdgpu_crtc->cursor_addr));
2215 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2216 lower_32_bits(amdgpu_crtc->cursor_addr));
2217
2218 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2219 CUR_CONTROL__CURSOR_EN_MASK |
2220 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2221 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2222}
2223
2224static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2225 int x, int y)
2226{
2227 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2228 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2229 int xorigin = 0, yorigin = 0;
2230
2231 amdgpu_crtc->cursor_x = x;
2232 amdgpu_crtc->cursor_y = y;
2233
2234 /* avivo cursor are offset into the total surface */
2235 x += crtc->x;
2236 y += crtc->y;
2237 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2238
2239 if (x < 0) {
2240 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2241 x = 0;
2242 }
2243 if (y < 0) {
2244 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2245 y = 0;
2246 }
2247
2248 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2249 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2250 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2251 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2252
2253 return 0;
2254}
2255
2256static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2257 int x, int y)
2258{
2259 int ret;
2260
2261 dce_v8_0_lock_cursor(crtc, true);
2262 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2263 dce_v8_0_lock_cursor(crtc, false);
2264
2265 return ret;
2266}
2267
2268static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2269 struct drm_file *file_priv,
2270 uint32_t handle,
2271 uint32_t width,
2272 uint32_t height,
2273 int32_t hot_x,
2274 int32_t hot_y)
2275{
2276 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277 struct drm_gem_object *obj;
2278 struct amdgpu_bo *aobj;
2279 int ret;
2280
2281 if (!handle) {
2282 /* turn off cursor */
2283 dce_v8_0_hide_cursor(crtc);
2284 obj = NULL;
2285 goto unpin;
2286 }
2287
2288 if ((width > amdgpu_crtc->max_cursor_width) ||
2289 (height > amdgpu_crtc->max_cursor_height)) {
2290 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2291 return -EINVAL;
2292 }
2293
2294 obj = drm_gem_object_lookup(file_priv, handle);
2295 if (!obj) {
2296 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2297 return -ENOENT;
2298 }
2299
2300 aobj = gem_to_amdgpu_bo(obj);
2301 ret = amdgpu_bo_reserve(aobj, false);
2302 if (ret != 0) {
2303 drm_gem_object_put(obj);
2304 return ret;
2305 }
2306
2307 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2308 amdgpu_bo_unreserve(aobj);
2309 if (ret) {
2310 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2311 drm_gem_object_put(obj);
2312 return ret;
2313 }
2314 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2315
2316 dce_v8_0_lock_cursor(crtc, true);
2317
2318 if (width != amdgpu_crtc->cursor_width ||
2319 height != amdgpu_crtc->cursor_height ||
2320 hot_x != amdgpu_crtc->cursor_hot_x ||
2321 hot_y != amdgpu_crtc->cursor_hot_y) {
2322 int x, y;
2323
2324 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2325 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2326
2327 dce_v8_0_cursor_move_locked(crtc, x, y);
2328
2329 amdgpu_crtc->cursor_width = width;
2330 amdgpu_crtc->cursor_height = height;
2331 amdgpu_crtc->cursor_hot_x = hot_x;
2332 amdgpu_crtc->cursor_hot_y = hot_y;
2333 }
2334
2335 dce_v8_0_show_cursor(crtc);
2336 dce_v8_0_lock_cursor(crtc, false);
2337
2338unpin:
2339 if (amdgpu_crtc->cursor_bo) {
2340 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2341 ret = amdgpu_bo_reserve(aobj, true);
2342 if (likely(ret == 0)) {
2343 amdgpu_bo_unpin(aobj);
2344 amdgpu_bo_unreserve(aobj);
2345 }
2346 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2347 }
2348
2349 amdgpu_crtc->cursor_bo = obj;
2350 return 0;
2351}
2352
2353static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2354{
2355 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2356
2357 if (amdgpu_crtc->cursor_bo) {
2358 dce_v8_0_lock_cursor(crtc, true);
2359
2360 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2361 amdgpu_crtc->cursor_y);
2362
2363 dce_v8_0_show_cursor(crtc);
2364
2365 dce_v8_0_lock_cursor(crtc, false);
2366 }
2367}
2368
2369static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2370 u16 *blue, uint32_t size,
2371 struct drm_modeset_acquire_ctx *ctx)
2372{
2373 dce_v8_0_crtc_load_lut(crtc);
2374
2375 return 0;
2376}
2377
2378static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2379{
2380 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2381
2382 drm_crtc_cleanup(crtc);
2383 kfree(amdgpu_crtc);
2384}
2385
2386static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2387 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2388 .cursor_move = dce_v8_0_crtc_cursor_move,
2389 .gamma_set = dce_v8_0_crtc_gamma_set,
2390 .set_config = amdgpu_display_crtc_set_config,
2391 .destroy = dce_v8_0_crtc_destroy,
2392 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2393 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2394 .enable_vblank = amdgpu_enable_vblank_kms,
2395 .disable_vblank = amdgpu_disable_vblank_kms,
2396 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2397};
2398
2399static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2400{
2401 struct drm_device *dev = crtc->dev;
2402 struct amdgpu_device *adev = drm_to_adev(dev);
2403 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2404 unsigned type;
2405
2406 switch (mode) {
2407 case DRM_MODE_DPMS_ON:
2408 amdgpu_crtc->enabled = true;
2409 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2410 dce_v8_0_vga_enable(crtc, true);
2411 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2412 dce_v8_0_vga_enable(crtc, false);
2413 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2414 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2415 amdgpu_crtc->crtc_id);
2416 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2417 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2418 drm_crtc_vblank_on(crtc);
2419 dce_v8_0_crtc_load_lut(crtc);
2420 break;
2421 case DRM_MODE_DPMS_STANDBY:
2422 case DRM_MODE_DPMS_SUSPEND:
2423 case DRM_MODE_DPMS_OFF:
2424 drm_crtc_vblank_off(crtc);
2425 if (amdgpu_crtc->enabled) {
2426 dce_v8_0_vga_enable(crtc, true);
2427 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2428 dce_v8_0_vga_enable(crtc, false);
2429 }
2430 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2431 amdgpu_crtc->enabled = false;
2432 break;
2433 }
2434 /* adjust pm to dpms */
2435 amdgpu_dpm_compute_clocks(adev);
2436}
2437
2438static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2439{
2440 /* disable crtc pair power gating before programming */
2441 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2442 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2443 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2444}
2445
2446static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2447{
2448 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2449 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2450}
2451
2452static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2453{
2454 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2455 struct drm_device *dev = crtc->dev;
2456 struct amdgpu_device *adev = drm_to_adev(dev);
2457 struct amdgpu_atom_ss ss;
2458 int i;
2459
2460 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2461 if (crtc->primary->fb) {
2462 int r;
2463 struct amdgpu_bo *abo;
2464
2465 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2466 r = amdgpu_bo_reserve(abo, true);
2467 if (unlikely(r))
2468 DRM_ERROR("failed to reserve abo before unpin\n");
2469 else {
2470 amdgpu_bo_unpin(abo);
2471 amdgpu_bo_unreserve(abo);
2472 }
2473 }
2474 /* disable the GRPH */
2475 dce_v8_0_grph_enable(crtc, false);
2476
2477 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2478
2479 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2480 if (adev->mode_info.crtcs[i] &&
2481 adev->mode_info.crtcs[i]->enabled &&
2482 i != amdgpu_crtc->crtc_id &&
2483 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2484 /* one other crtc is using this pll don't turn
2485 * off the pll
2486 */
2487 goto done;
2488 }
2489 }
2490
2491 switch (amdgpu_crtc->pll_id) {
2492 case ATOM_PPLL1:
2493 case ATOM_PPLL2:
2494 /* disable the ppll */
2495 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2496 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2497 break;
2498 case ATOM_PPLL0:
2499 /* disable the ppll */
2500 if ((adev->asic_type == CHIP_KAVERI) ||
2501 (adev->asic_type == CHIP_BONAIRE) ||
2502 (adev->asic_type == CHIP_HAWAII))
2503 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2504 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2505 break;
2506 default:
2507 break;
2508 }
2509done:
2510 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2511 amdgpu_crtc->adjusted_clock = 0;
2512 amdgpu_crtc->encoder = NULL;
2513 amdgpu_crtc->connector = NULL;
2514}
2515
2516static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2517 struct drm_display_mode *mode,
2518 struct drm_display_mode *adjusted_mode,
2519 int x, int y, struct drm_framebuffer *old_fb)
2520{
2521 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2522
2523 if (!amdgpu_crtc->adjusted_clock)
2524 return -EINVAL;
2525
2526 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2527 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2528 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2529 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2530 amdgpu_atombios_crtc_scaler_setup(crtc);
2531 dce_v8_0_cursor_reset(crtc);
2532 /* update the hw version fpr dpm */
2533 amdgpu_crtc->hw_mode = *adjusted_mode;
2534
2535 return 0;
2536}
2537
2538static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2539 const struct drm_display_mode *mode,
2540 struct drm_display_mode *adjusted_mode)
2541{
2542 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2543 struct drm_device *dev = crtc->dev;
2544 struct drm_encoder *encoder;
2545
2546 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2548 if (encoder->crtc == crtc) {
2549 amdgpu_crtc->encoder = encoder;
2550 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2551 break;
2552 }
2553 }
2554 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2555 amdgpu_crtc->encoder = NULL;
2556 amdgpu_crtc->connector = NULL;
2557 return false;
2558 }
2559 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2560 return false;
2561 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2562 return false;
2563 /* pick pll */
2564 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2565 /* if we can't get a PPLL for a non-DP encoder, fail */
2566 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2567 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2568 return false;
2569
2570 return true;
2571}
2572
2573static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2574 struct drm_framebuffer *old_fb)
2575{
2576 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2577}
2578
2579static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2580 struct drm_framebuffer *fb,
2581 int x, int y, enum mode_set_atomic state)
2582{
2583 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2584}
2585
2586static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2587 .dpms = dce_v8_0_crtc_dpms,
2588 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2589 .mode_set = dce_v8_0_crtc_mode_set,
2590 .mode_set_base = dce_v8_0_crtc_set_base,
2591 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2592 .prepare = dce_v8_0_crtc_prepare,
2593 .commit = dce_v8_0_crtc_commit,
2594 .disable = dce_v8_0_crtc_disable,
2595 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2596};
2597
2598static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2599{
2600 struct amdgpu_crtc *amdgpu_crtc;
2601
2602 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2603 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2604 if (amdgpu_crtc == NULL)
2605 return -ENOMEM;
2606
2607 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2608
2609 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2610 amdgpu_crtc->crtc_id = index;
2611 adev->mode_info.crtcs[index] = amdgpu_crtc;
2612
2613 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2614 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2615 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2616 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2617
2618 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2619
2620 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2621 amdgpu_crtc->adjusted_clock = 0;
2622 amdgpu_crtc->encoder = NULL;
2623 amdgpu_crtc->connector = NULL;
2624 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2625
2626 return 0;
2627}
2628
2629static int dce_v8_0_early_init(void *handle)
2630{
2631 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2632
2633 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2634 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2635
2636 dce_v8_0_set_display_funcs(adev);
2637
2638 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2639
2640 switch (adev->asic_type) {
2641 case CHIP_BONAIRE:
2642 case CHIP_HAWAII:
2643 adev->mode_info.num_hpd = 6;
2644 adev->mode_info.num_dig = 6;
2645 break;
2646 case CHIP_KAVERI:
2647 adev->mode_info.num_hpd = 6;
2648 adev->mode_info.num_dig = 7;
2649 break;
2650 case CHIP_KABINI:
2651 case CHIP_MULLINS:
2652 adev->mode_info.num_hpd = 6;
2653 adev->mode_info.num_dig = 6; /* ? */
2654 break;
2655 default:
2656 /* FIXME: not supported yet */
2657 return -EINVAL;
2658 }
2659
2660 dce_v8_0_set_irq_funcs(adev);
2661
2662 return 0;
2663}
2664
2665static int dce_v8_0_sw_init(void *handle)
2666{
2667 int r, i;
2668 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2669
2670 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2671 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2672 if (r)
2673 return r;
2674 }
2675
2676 for (i = 8; i < 20; i += 2) {
2677 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2678 if (r)
2679 return r;
2680 }
2681
2682 /* HPD hotplug */
2683 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2684 if (r)
2685 return r;
2686
2687 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2688
2689 adev_to_drm(adev)->mode_config.async_page_flip = true;
2690
2691 adev_to_drm(adev)->mode_config.max_width = 16384;
2692 adev_to_drm(adev)->mode_config.max_height = 16384;
2693
2694 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2695 if (adev->asic_type == CHIP_HAWAII)
2696 /* disable prefer shadow for now due to hibernation issues */
2697 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
2698 else
2699 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2700
2701 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2702
2703 r = amdgpu_display_modeset_create_props(adev);
2704 if (r)
2705 return r;
2706
2707 adev_to_drm(adev)->mode_config.max_width = 16384;
2708 adev_to_drm(adev)->mode_config.max_height = 16384;
2709
2710 /* allocate crtcs */
2711 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2712 r = dce_v8_0_crtc_init(adev, i);
2713 if (r)
2714 return r;
2715 }
2716
2717 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2718 amdgpu_display_print_display_setup(adev_to_drm(adev));
2719 else
2720 return -EINVAL;
2721
2722 /* setup afmt */
2723 r = dce_v8_0_afmt_init(adev);
2724 if (r)
2725 return r;
2726
2727 r = dce_v8_0_audio_init(adev);
2728 if (r)
2729 return r;
2730
2731 /* Disable vblank IRQs aggressively for power-saving */
2732 /* XXX: can this be enabled for DC? */
2733 adev_to_drm(adev)->vblank_disable_immediate = true;
2734
2735 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2736 if (r)
2737 return r;
2738
2739 /* Pre-DCE11 */
2740 INIT_DELAYED_WORK(&adev->hotplug_work,
2741 amdgpu_display_hotplug_work_func);
2742
2743 drm_kms_helper_poll_init(adev_to_drm(adev));
2744
2745 adev->mode_info.mode_config_initialized = true;
2746 return 0;
2747}
2748
2749static int dce_v8_0_sw_fini(void *handle)
2750{
2751 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2752
2753 kfree(adev->mode_info.bios_hardcoded_edid);
2754
2755 drm_kms_helper_poll_fini(adev_to_drm(adev));
2756
2757 dce_v8_0_audio_fini(adev);
2758
2759 dce_v8_0_afmt_fini(adev);
2760
2761 drm_mode_config_cleanup(adev_to_drm(adev));
2762 adev->mode_info.mode_config_initialized = false;
2763
2764 return 0;
2765}
2766
2767static int dce_v8_0_hw_init(void *handle)
2768{
2769 int i;
2770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2771
2772 /* disable vga render */
2773 dce_v8_0_set_vga_render_state(adev, false);
2774 /* init dig PHYs, disp eng pll */
2775 amdgpu_atombios_encoder_init_dig(adev);
2776 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2777
2778 /* initialize hpd */
2779 dce_v8_0_hpd_init(adev);
2780
2781 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2782 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2783 }
2784
2785 dce_v8_0_pageflip_interrupt_init(adev);
2786
2787 return 0;
2788}
2789
2790static int dce_v8_0_hw_fini(void *handle)
2791{
2792 int i;
2793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2794
2795 dce_v8_0_hpd_fini(adev);
2796
2797 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2798 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2799 }
2800
2801 dce_v8_0_pageflip_interrupt_fini(adev);
2802
2803 flush_delayed_work(&adev->hotplug_work);
2804
2805 return 0;
2806}
2807
2808static int dce_v8_0_suspend(void *handle)
2809{
2810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2811 int r;
2812
2813 r = amdgpu_display_suspend_helper(adev);
2814 if (r)
2815 return r;
2816
2817 adev->mode_info.bl_level =
2818 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2819
2820 return dce_v8_0_hw_fini(handle);
2821}
2822
2823static int dce_v8_0_resume(void *handle)
2824{
2825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2826 int ret;
2827
2828 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2829 adev->mode_info.bl_level);
2830
2831 ret = dce_v8_0_hw_init(handle);
2832
2833 /* turn on the BL */
2834 if (adev->mode_info.bl_encoder) {
2835 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2836 adev->mode_info.bl_encoder);
2837 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2838 bl_level);
2839 }
2840 if (ret)
2841 return ret;
2842
2843 return amdgpu_display_resume_helper(adev);
2844}
2845
2846static bool dce_v8_0_is_idle(void *handle)
2847{
2848 return true;
2849}
2850
2851static int dce_v8_0_wait_for_idle(void *handle)
2852{
2853 return 0;
2854}
2855
2856static int dce_v8_0_soft_reset(void *handle)
2857{
2858 u32 srbm_soft_reset = 0, tmp;
2859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2860
2861 if (dce_v8_0_is_display_hung(adev))
2862 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2863
2864 if (srbm_soft_reset) {
2865 tmp = RREG32(mmSRBM_SOFT_RESET);
2866 tmp |= srbm_soft_reset;
2867 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2868 WREG32(mmSRBM_SOFT_RESET, tmp);
2869 tmp = RREG32(mmSRBM_SOFT_RESET);
2870
2871 udelay(50);
2872
2873 tmp &= ~srbm_soft_reset;
2874 WREG32(mmSRBM_SOFT_RESET, tmp);
2875 tmp = RREG32(mmSRBM_SOFT_RESET);
2876
2877 /* Wait a little for things to settle down */
2878 udelay(50);
2879 }
2880 return 0;
2881}
2882
2883static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2884 int crtc,
2885 enum amdgpu_interrupt_state state)
2886{
2887 u32 reg_block, lb_interrupt_mask;
2888
2889 if (crtc >= adev->mode_info.num_crtc) {
2890 DRM_DEBUG("invalid crtc %d\n", crtc);
2891 return;
2892 }
2893
2894 switch (crtc) {
2895 case 0:
2896 reg_block = CRTC0_REGISTER_OFFSET;
2897 break;
2898 case 1:
2899 reg_block = CRTC1_REGISTER_OFFSET;
2900 break;
2901 case 2:
2902 reg_block = CRTC2_REGISTER_OFFSET;
2903 break;
2904 case 3:
2905 reg_block = CRTC3_REGISTER_OFFSET;
2906 break;
2907 case 4:
2908 reg_block = CRTC4_REGISTER_OFFSET;
2909 break;
2910 case 5:
2911 reg_block = CRTC5_REGISTER_OFFSET;
2912 break;
2913 default:
2914 DRM_DEBUG("invalid crtc %d\n", crtc);
2915 return;
2916 }
2917
2918 switch (state) {
2919 case AMDGPU_IRQ_STATE_DISABLE:
2920 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2921 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2922 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2923 break;
2924 case AMDGPU_IRQ_STATE_ENABLE:
2925 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2926 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2927 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2928 break;
2929 default:
2930 break;
2931 }
2932}
2933
2934static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2935 int crtc,
2936 enum amdgpu_interrupt_state state)
2937{
2938 u32 reg_block, lb_interrupt_mask;
2939
2940 if (crtc >= adev->mode_info.num_crtc) {
2941 DRM_DEBUG("invalid crtc %d\n", crtc);
2942 return;
2943 }
2944
2945 switch (crtc) {
2946 case 0:
2947 reg_block = CRTC0_REGISTER_OFFSET;
2948 break;
2949 case 1:
2950 reg_block = CRTC1_REGISTER_OFFSET;
2951 break;
2952 case 2:
2953 reg_block = CRTC2_REGISTER_OFFSET;
2954 break;
2955 case 3:
2956 reg_block = CRTC3_REGISTER_OFFSET;
2957 break;
2958 case 4:
2959 reg_block = CRTC4_REGISTER_OFFSET;
2960 break;
2961 case 5:
2962 reg_block = CRTC5_REGISTER_OFFSET;
2963 break;
2964 default:
2965 DRM_DEBUG("invalid crtc %d\n", crtc);
2966 return;
2967 }
2968
2969 switch (state) {
2970 case AMDGPU_IRQ_STATE_DISABLE:
2971 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2972 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2973 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2974 break;
2975 case AMDGPU_IRQ_STATE_ENABLE:
2976 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2977 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2978 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2979 break;
2980 default:
2981 break;
2982 }
2983}
2984
2985static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2986 struct amdgpu_irq_src *src,
2987 unsigned type,
2988 enum amdgpu_interrupt_state state)
2989{
2990 u32 dc_hpd_int_cntl;
2991
2992 if (type >= adev->mode_info.num_hpd) {
2993 DRM_DEBUG("invalid hdp %d\n", type);
2994 return 0;
2995 }
2996
2997 switch (state) {
2998 case AMDGPU_IRQ_STATE_DISABLE:
2999 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3000 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3001 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3002 break;
3003 case AMDGPU_IRQ_STATE_ENABLE:
3004 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3005 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3006 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3007 break;
3008 default:
3009 break;
3010 }
3011
3012 return 0;
3013}
3014
3015static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3016 struct amdgpu_irq_src *src,
3017 unsigned type,
3018 enum amdgpu_interrupt_state state)
3019{
3020 switch (type) {
3021 case AMDGPU_CRTC_IRQ_VBLANK1:
3022 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3023 break;
3024 case AMDGPU_CRTC_IRQ_VBLANK2:
3025 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3026 break;
3027 case AMDGPU_CRTC_IRQ_VBLANK3:
3028 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3029 break;
3030 case AMDGPU_CRTC_IRQ_VBLANK4:
3031 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3032 break;
3033 case AMDGPU_CRTC_IRQ_VBLANK5:
3034 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3035 break;
3036 case AMDGPU_CRTC_IRQ_VBLANK6:
3037 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3038 break;
3039 case AMDGPU_CRTC_IRQ_VLINE1:
3040 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3041 break;
3042 case AMDGPU_CRTC_IRQ_VLINE2:
3043 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3044 break;
3045 case AMDGPU_CRTC_IRQ_VLINE3:
3046 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3047 break;
3048 case AMDGPU_CRTC_IRQ_VLINE4:
3049 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3050 break;
3051 case AMDGPU_CRTC_IRQ_VLINE5:
3052 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3053 break;
3054 case AMDGPU_CRTC_IRQ_VLINE6:
3055 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3056 break;
3057 default:
3058 break;
3059 }
3060 return 0;
3061}
3062
3063static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3064 struct amdgpu_irq_src *source,
3065 struct amdgpu_iv_entry *entry)
3066{
3067 unsigned crtc = entry->src_id - 1;
3068 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3069 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3070 crtc);
3071
3072 switch (entry->src_data[0]) {
3073 case 0: /* vblank */
3074 if (disp_int & interrupt_status_offsets[crtc].vblank)
3075 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3076 else
3077 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3078
3079 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3080 drm_handle_vblank(adev_to_drm(adev), crtc);
3081 }
3082 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3083 break;
3084 case 1: /* vline */
3085 if (disp_int & interrupt_status_offsets[crtc].vline)
3086 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3087 else
3088 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3089
3090 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3091 break;
3092 default:
3093 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3094 break;
3095 }
3096
3097 return 0;
3098}
3099
3100static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3101 struct amdgpu_irq_src *src,
3102 unsigned type,
3103 enum amdgpu_interrupt_state state)
3104{
3105 u32 reg;
3106
3107 if (type >= adev->mode_info.num_crtc) {
3108 DRM_ERROR("invalid pageflip crtc %d\n", type);
3109 return -EINVAL;
3110 }
3111
3112 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3113 if (state == AMDGPU_IRQ_STATE_DISABLE)
3114 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3115 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3116 else
3117 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3118 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3119
3120 return 0;
3121}
3122
3123static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3124 struct amdgpu_irq_src *source,
3125 struct amdgpu_iv_entry *entry)
3126{
3127 unsigned long flags;
3128 unsigned crtc_id;
3129 struct amdgpu_crtc *amdgpu_crtc;
3130 struct amdgpu_flip_work *works;
3131
3132 crtc_id = (entry->src_id - 8) >> 1;
3133 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3134
3135 if (crtc_id >= adev->mode_info.num_crtc) {
3136 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3137 return -EINVAL;
3138 }
3139
3140 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3141 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3142 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3143 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3144
3145 /* IRQ could occur when in initial stage */
3146 if (amdgpu_crtc == NULL)
3147 return 0;
3148
3149 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3150 works = amdgpu_crtc->pflip_works;
3151 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3152 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3153 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3154 amdgpu_crtc->pflip_status,
3155 AMDGPU_FLIP_SUBMITTED);
3156 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3157 return 0;
3158 }
3159
3160 /* page flip completed. clean up */
3161 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3162 amdgpu_crtc->pflip_works = NULL;
3163
3164 /* wakeup usersapce */
3165 if (works->event)
3166 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3167
3168 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3169
3170 drm_crtc_vblank_put(&amdgpu_crtc->base);
3171 schedule_work(&works->unpin_work);
3172
3173 return 0;
3174}
3175
3176static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3177 struct amdgpu_irq_src *source,
3178 struct amdgpu_iv_entry *entry)
3179{
3180 uint32_t disp_int, mask, tmp;
3181 unsigned hpd;
3182
3183 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3184 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3185 return 0;
3186 }
3187
3188 hpd = entry->src_data[0];
3189 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3190 mask = interrupt_status_offsets[hpd].hpd;
3191
3192 if (disp_int & mask) {
3193 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3194 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3195 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3196 schedule_delayed_work(&adev->hotplug_work, 0);
3197 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3198 }
3199
3200 return 0;
3201
3202}
3203
3204static int dce_v8_0_set_clockgating_state(void *handle,
3205 enum amd_clockgating_state state)
3206{
3207 return 0;
3208}
3209
3210static int dce_v8_0_set_powergating_state(void *handle,
3211 enum amd_powergating_state state)
3212{
3213 return 0;
3214}
3215
3216static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3217 .name = "dce_v8_0",
3218 .early_init = dce_v8_0_early_init,
3219 .late_init = NULL,
3220 .sw_init = dce_v8_0_sw_init,
3221 .sw_fini = dce_v8_0_sw_fini,
3222 .hw_init = dce_v8_0_hw_init,
3223 .hw_fini = dce_v8_0_hw_fini,
3224 .suspend = dce_v8_0_suspend,
3225 .resume = dce_v8_0_resume,
3226 .is_idle = dce_v8_0_is_idle,
3227 .wait_for_idle = dce_v8_0_wait_for_idle,
3228 .soft_reset = dce_v8_0_soft_reset,
3229 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3230 .set_powergating_state = dce_v8_0_set_powergating_state,
3231};
3232
3233static void
3234dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3235 struct drm_display_mode *mode,
3236 struct drm_display_mode *adjusted_mode)
3237{
3238 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3239
3240 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3241
3242 /* need to call this here rather than in prepare() since we need some crtc info */
3243 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3244
3245 /* set scaler clears this on some chips */
3246 dce_v8_0_set_interleave(encoder->crtc, mode);
3247
3248 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3249 dce_v8_0_afmt_enable(encoder, true);
3250 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3251 }
3252}
3253
3254static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3255{
3256 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3257 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3258 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3259
3260 if ((amdgpu_encoder->active_device &
3261 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3262 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3263 ENCODER_OBJECT_ID_NONE)) {
3264 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3265 if (dig) {
3266 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3267 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3268 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3269 }
3270 }
3271
3272 amdgpu_atombios_scratch_regs_lock(adev, true);
3273
3274 if (connector) {
3275 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3276
3277 /* select the clock/data port if it uses a router */
3278 if (amdgpu_connector->router.cd_valid)
3279 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3280
3281 /* turn eDP panel on for mode set */
3282 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3283 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3284 ATOM_TRANSMITTER_ACTION_POWER_ON);
3285 }
3286
3287 /* this is needed for the pll/ss setup to work correctly in some cases */
3288 amdgpu_atombios_encoder_set_crtc_source(encoder);
3289 /* set up the FMT blocks */
3290 dce_v8_0_program_fmt(encoder);
3291}
3292
3293static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3294{
3295 struct drm_device *dev = encoder->dev;
3296 struct amdgpu_device *adev = drm_to_adev(dev);
3297
3298 /* need to call this here as we need the crtc set up */
3299 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3300 amdgpu_atombios_scratch_regs_lock(adev, false);
3301}
3302
3303static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3304{
3305 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3306 struct amdgpu_encoder_atom_dig *dig;
3307
3308 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3309
3310 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3311 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3312 dce_v8_0_afmt_enable(encoder, false);
3313 dig = amdgpu_encoder->enc_priv;
3314 dig->dig_encoder = -1;
3315 }
3316 amdgpu_encoder->active_device = 0;
3317}
3318
3319/* these are handled by the primary encoders */
3320static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3321{
3322
3323}
3324
3325static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3326{
3327
3328}
3329
3330static void
3331dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3332 struct drm_display_mode *mode,
3333 struct drm_display_mode *adjusted_mode)
3334{
3335
3336}
3337
3338static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3339{
3340
3341}
3342
3343static void
3344dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3345{
3346
3347}
3348
3349static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3350 .dpms = dce_v8_0_ext_dpms,
3351 .prepare = dce_v8_0_ext_prepare,
3352 .mode_set = dce_v8_0_ext_mode_set,
3353 .commit = dce_v8_0_ext_commit,
3354 .disable = dce_v8_0_ext_disable,
3355 /* no detect for TMDS/LVDS yet */
3356};
3357
3358static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3359 .dpms = amdgpu_atombios_encoder_dpms,
3360 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3361 .prepare = dce_v8_0_encoder_prepare,
3362 .mode_set = dce_v8_0_encoder_mode_set,
3363 .commit = dce_v8_0_encoder_commit,
3364 .disable = dce_v8_0_encoder_disable,
3365 .detect = amdgpu_atombios_encoder_dig_detect,
3366};
3367
3368static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3369 .dpms = amdgpu_atombios_encoder_dpms,
3370 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3371 .prepare = dce_v8_0_encoder_prepare,
3372 .mode_set = dce_v8_0_encoder_mode_set,
3373 .commit = dce_v8_0_encoder_commit,
3374 .detect = amdgpu_atombios_encoder_dac_detect,
3375};
3376
3377static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3378{
3379 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3380 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3381 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3382 kfree(amdgpu_encoder->enc_priv);
3383 drm_encoder_cleanup(encoder);
3384 kfree(amdgpu_encoder);
3385}
3386
3387static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3388 .destroy = dce_v8_0_encoder_destroy,
3389};
3390
3391static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3392 uint32_t encoder_enum,
3393 uint32_t supported_device,
3394 u16 caps)
3395{
3396 struct drm_device *dev = adev_to_drm(adev);
3397 struct drm_encoder *encoder;
3398 struct amdgpu_encoder *amdgpu_encoder;
3399
3400 /* see if we already added it */
3401 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3402 amdgpu_encoder = to_amdgpu_encoder(encoder);
3403 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3404 amdgpu_encoder->devices |= supported_device;
3405 return;
3406 }
3407
3408 }
3409
3410 /* add a new one */
3411 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3412 if (!amdgpu_encoder)
3413 return;
3414
3415 encoder = &amdgpu_encoder->base;
3416 switch (adev->mode_info.num_crtc) {
3417 case 1:
3418 encoder->possible_crtcs = 0x1;
3419 break;
3420 case 2:
3421 default:
3422 encoder->possible_crtcs = 0x3;
3423 break;
3424 case 4:
3425 encoder->possible_crtcs = 0xf;
3426 break;
3427 case 6:
3428 encoder->possible_crtcs = 0x3f;
3429 break;
3430 }
3431
3432 amdgpu_encoder->enc_priv = NULL;
3433
3434 amdgpu_encoder->encoder_enum = encoder_enum;
3435 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3436 amdgpu_encoder->devices = supported_device;
3437 amdgpu_encoder->rmx_type = RMX_OFF;
3438 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3439 amdgpu_encoder->is_ext_encoder = false;
3440 amdgpu_encoder->caps = caps;
3441
3442 switch (amdgpu_encoder->encoder_id) {
3443 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3444 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3445 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3446 DRM_MODE_ENCODER_DAC, NULL);
3447 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3448 break;
3449 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3450 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3451 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3452 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3453 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3454 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3455 amdgpu_encoder->rmx_type = RMX_FULL;
3456 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3457 DRM_MODE_ENCODER_LVDS, NULL);
3458 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3459 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3460 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3461 DRM_MODE_ENCODER_DAC, NULL);
3462 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3463 } else {
3464 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3465 DRM_MODE_ENCODER_TMDS, NULL);
3466 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3467 }
3468 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3469 break;
3470 case ENCODER_OBJECT_ID_SI170B:
3471 case ENCODER_OBJECT_ID_CH7303:
3472 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3473 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3474 case ENCODER_OBJECT_ID_TITFP513:
3475 case ENCODER_OBJECT_ID_VT1623:
3476 case ENCODER_OBJECT_ID_HDMI_SI1930:
3477 case ENCODER_OBJECT_ID_TRAVIS:
3478 case ENCODER_OBJECT_ID_NUTMEG:
3479 /* these are handled by the primary encoders */
3480 amdgpu_encoder->is_ext_encoder = true;
3481 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3482 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3483 DRM_MODE_ENCODER_LVDS, NULL);
3484 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3485 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3486 DRM_MODE_ENCODER_DAC, NULL);
3487 else
3488 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3489 DRM_MODE_ENCODER_TMDS, NULL);
3490 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3491 break;
3492 }
3493}
3494
3495static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3496 .bandwidth_update = &dce_v8_0_bandwidth_update,
3497 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3498 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3499 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3500 .hpd_sense = &dce_v8_0_hpd_sense,
3501 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3502 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3503 .page_flip = &dce_v8_0_page_flip,
3504 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3505 .add_encoder = &dce_v8_0_encoder_add,
3506 .add_connector = &amdgpu_connector_add,
3507};
3508
3509static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3510{
3511 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3512}
3513
3514static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3515 .set = dce_v8_0_set_crtc_interrupt_state,
3516 .process = dce_v8_0_crtc_irq,
3517};
3518
3519static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3520 .set = dce_v8_0_set_pageflip_interrupt_state,
3521 .process = dce_v8_0_pageflip_irq,
3522};
3523
3524static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3525 .set = dce_v8_0_set_hpd_interrupt_state,
3526 .process = dce_v8_0_hpd_irq,
3527};
3528
3529static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3530{
3531 if (adev->mode_info.num_crtc > 0)
3532 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3533 else
3534 adev->crtc_irq.num_types = 0;
3535 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3536
3537 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3538 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3539
3540 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3541 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3542}
3543
3544const struct amdgpu_ip_block_version dce_v8_0_ip_block = {
3545 .type = AMD_IP_BLOCK_TYPE_DCE,
3546 .major = 8,
3547 .minor = 0,
3548 .rev = 0,
3549 .funcs = &dce_v8_0_ip_funcs,
3550};
3551
3552const struct amdgpu_ip_block_version dce_v8_1_ip_block = {
3553 .type = AMD_IP_BLOCK_TYPE_DCE,
3554 .major = 8,
3555 .minor = 1,
3556 .rev = 0,
3557 .funcs = &dce_v8_0_ip_funcs,
3558};
3559
3560const struct amdgpu_ip_block_version dce_v8_2_ip_block = {
3561 .type = AMD_IP_BLOCK_TYPE_DCE,
3562 .major = 8,
3563 .minor = 2,
3564 .rev = 0,
3565 .funcs = &dce_v8_0_ip_funcs,
3566};
3567
3568const struct amdgpu_ip_block_version dce_v8_3_ip_block = {
3569 .type = AMD_IP_BLOCK_TYPE_DCE,
3570 .major = 8,
3571 .minor = 3,
3572 .rev = 0,
3573 .funcs = &dce_v8_0_ip_funcs,
3574};
3575
3576const struct amdgpu_ip_block_version dce_v8_5_ip_block = {
3577 .type = AMD_IP_BLOCK_TYPE_DCE,
3578 .major = 8,
3579 .minor = 5,
3580 .rev = 0,
3581 .funcs = &dce_v8_0_ip_funcs,
3582};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fourcc.h>
25#include <drm/drm_vblank.h>
26
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_i2c.h"
30#include "cikd.h"
31#include "atom.h"
32#include "amdgpu_atombios.h"
33#include "atombios_crtc.h"
34#include "atombios_encoders.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37#include "amdgpu_display.h"
38#include "dce_v8_0.h"
39
40#include "dce/dce_8_0_d.h"
41#include "dce/dce_8_0_sh_mask.h"
42
43#include "gca/gfx_7_2_enum.h"
44
45#include "gmc/gmc_7_1_d.h"
46#include "gmc/gmc_7_1_sh_mask.h"
47
48#include "oss/oss_2_0_d.h"
49#include "oss/oss_2_0_sh_mask.h"
50
51static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
52static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
53
54static const u32 crtc_offsets[6] =
55{
56 CRTC0_REGISTER_OFFSET,
57 CRTC1_REGISTER_OFFSET,
58 CRTC2_REGISTER_OFFSET,
59 CRTC3_REGISTER_OFFSET,
60 CRTC4_REGISTER_OFFSET,
61 CRTC5_REGISTER_OFFSET
62};
63
64static const u32 hpd_offsets[] =
65{
66 HPD0_REGISTER_OFFSET,
67 HPD1_REGISTER_OFFSET,
68 HPD2_REGISTER_OFFSET,
69 HPD3_REGISTER_OFFSET,
70 HPD4_REGISTER_OFFSET,
71 HPD5_REGISTER_OFFSET
72};
73
74static const uint32_t dig_offsets[] = {
75 CRTC0_REGISTER_OFFSET,
76 CRTC1_REGISTER_OFFSET,
77 CRTC2_REGISTER_OFFSET,
78 CRTC3_REGISTER_OFFSET,
79 CRTC4_REGISTER_OFFSET,
80 CRTC5_REGISTER_OFFSET,
81 (0x13830 - 0x7030) >> 2,
82};
83
84static const struct {
85 uint32_t reg;
86 uint32_t vblank;
87 uint32_t vline;
88 uint32_t hpd;
89
90} interrupt_status_offsets[6] = { {
91 .reg = mmDISP_INTERRUPT_STATUS,
92 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105}, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110}, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115}, {
116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120} };
121
122static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
123 u32 block_offset, u32 reg)
124{
125 unsigned long flags;
126 u32 r;
127
128 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
129 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
130 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
131 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
132
133 return r;
134}
135
136static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
137 u32 block_offset, u32 reg, u32 v)
138{
139 unsigned long flags;
140
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
145}
146
147static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
148{
149 if (crtc >= adev->mode_info.num_crtc)
150 return 0;
151 else
152 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
153}
154
155static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
156{
157 unsigned i;
158
159 /* Enable pflip interrupts */
160 for (i = 0; i < adev->mode_info.num_crtc; i++)
161 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
162}
163
164static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
165{
166 unsigned i;
167
168 /* Disable pflip interrupts */
169 for (i = 0; i < adev->mode_info.num_crtc; i++)
170 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
171}
172
173/**
174 * dce_v8_0_page_flip - pageflip callback.
175 *
176 * @adev: amdgpu_device pointer
177 * @crtc_id: crtc to cleanup pageflip on
178 * @crtc_base: new address of the crtc (GPU MC address)
179 *
180 * Triggers the actual pageflip by updating the primary
181 * surface base address.
182 */
183static void dce_v8_0_page_flip(struct amdgpu_device *adev,
184 int crtc_id, u64 crtc_base, bool async)
185{
186 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
187 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
188
189 /* flip at hsync for async, default is vsync */
190 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
191 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
192 /* update pitch */
193 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
194 fb->pitches[0] / fb->format->cpp[0]);
195 /* update the primary scanout addresses */
196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
197 upper_32_bits(crtc_base));
198 /* writing to the low address triggers the update */
199 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
200 lower_32_bits(crtc_base));
201 /* post the write */
202 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
203}
204
205static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
206 u32 *vbl, u32 *position)
207{
208 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
209 return -EINVAL;
210
211 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
212 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
213
214 return 0;
215}
216
217/**
218 * dce_v8_0_hpd_sense - hpd sense callback.
219 *
220 * @adev: amdgpu_device pointer
221 * @hpd: hpd (hotplug detect) pin
222 *
223 * Checks if a digital monitor is connected (evergreen+).
224 * Returns true if connected, false if not connected.
225 */
226static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
227 enum amdgpu_hpd_id hpd)
228{
229 bool connected = false;
230
231 if (hpd >= adev->mode_info.num_hpd)
232 return connected;
233
234 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
235 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
236 connected = true;
237
238 return connected;
239}
240
241/**
242 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
243 *
244 * @adev: amdgpu_device pointer
245 * @hpd: hpd (hotplug detect) pin
246 *
247 * Set the polarity of the hpd pin (evergreen+).
248 */
249static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
250 enum amdgpu_hpd_id hpd)
251{
252 u32 tmp;
253 bool connected = dce_v8_0_hpd_sense(adev, hpd);
254
255 if (hpd >= adev->mode_info.num_hpd)
256 return;
257
258 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
259 if (connected)
260 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
261 else
262 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
263 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
264}
265
266/**
267 * dce_v8_0_hpd_init - hpd setup callback.
268 *
269 * @adev: amdgpu_device pointer
270 *
271 * Setup the hpd pins used by the card (evergreen+).
272 * Enable the pin, set the polarity, and enable the hpd interrupts.
273 */
274static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
275{
276 struct drm_device *dev = adev->ddev;
277 struct drm_connector *connector;
278 struct drm_connector_list_iter iter;
279 u32 tmp;
280
281 drm_connector_list_iter_begin(dev, &iter);
282 drm_for_each_connector_iter(connector, &iter) {
283 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
284
285 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
286 continue;
287
288 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
289 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
290 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
291
292 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
293 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
294 /* don't try to enable hpd on eDP or LVDS avoid breaking the
295 * aux dp channel on imac and help (but not completely fix)
296 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
297 * also avoid interrupt storms during dpms.
298 */
299 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
300 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
301 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
302 continue;
303 }
304
305 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
306 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
307 }
308 drm_connector_list_iter_end(&iter);
309}
310
311/**
312 * dce_v8_0_hpd_fini - hpd tear down callback.
313 *
314 * @adev: amdgpu_device pointer
315 *
316 * Tear down the hpd pins used by the card (evergreen+).
317 * Disable the hpd interrupts.
318 */
319static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
320{
321 struct drm_device *dev = adev->ddev;
322 struct drm_connector *connector;
323 struct drm_connector_list_iter iter;
324 u32 tmp;
325
326 drm_connector_list_iter_begin(dev, &iter);
327 drm_for_each_connector_iter(connector, &iter) {
328 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
329
330 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
331 continue;
332
333 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
334 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
335 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
336
337 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
338 }
339 drm_connector_list_iter_end(&iter);
340}
341
342static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
343{
344 return mmDC_GPIO_HPD_A;
345}
346
347static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
348{
349 u32 crtc_hung = 0;
350 u32 crtc_status[6];
351 u32 i, j, tmp;
352
353 for (i = 0; i < adev->mode_info.num_crtc; i++) {
354 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
355 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
356 crtc_hung |= (1 << i);
357 }
358 }
359
360 for (j = 0; j < 10; j++) {
361 for (i = 0; i < adev->mode_info.num_crtc; i++) {
362 if (crtc_hung & (1 << i)) {
363 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
364 if (tmp != crtc_status[i])
365 crtc_hung &= ~(1 << i);
366 }
367 }
368 if (crtc_hung == 0)
369 return false;
370 udelay(100);
371 }
372
373 return true;
374}
375
376static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
377 bool render)
378{
379 u32 tmp;
380
381 /* Lockout access through VGA aperture*/
382 tmp = RREG32(mmVGA_HDP_CONTROL);
383 if (render)
384 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
385 else
386 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
387 WREG32(mmVGA_HDP_CONTROL, tmp);
388
389 /* disable VGA render */
390 tmp = RREG32(mmVGA_RENDER_CONTROL);
391 if (render)
392 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
393 else
394 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
395 WREG32(mmVGA_RENDER_CONTROL, tmp);
396}
397
398static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
399{
400 int num_crtc = 0;
401
402 switch (adev->asic_type) {
403 case CHIP_BONAIRE:
404 case CHIP_HAWAII:
405 num_crtc = 6;
406 break;
407 case CHIP_KAVERI:
408 num_crtc = 4;
409 break;
410 case CHIP_KABINI:
411 case CHIP_MULLINS:
412 num_crtc = 2;
413 break;
414 default:
415 num_crtc = 0;
416 }
417 return num_crtc;
418}
419
420void dce_v8_0_disable_dce(struct amdgpu_device *adev)
421{
422 /*Disable VGA render and enabled crtc, if has DCE engine*/
423 if (amdgpu_atombios_has_dce_engine_info(adev)) {
424 u32 tmp;
425 int crtc_enabled, i;
426
427 dce_v8_0_set_vga_render_state(adev, false);
428
429 /*Disable crtc*/
430 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
431 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
432 CRTC_CONTROL, CRTC_MASTER_EN);
433 if (crtc_enabled) {
434 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
435 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
436 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
437 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
438 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
439 }
440 }
441 }
442}
443
444static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
445{
446 struct drm_device *dev = encoder->dev;
447 struct amdgpu_device *adev = dev->dev_private;
448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
449 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
450 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
451 int bpc = 0;
452 u32 tmp = 0;
453 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
454
455 if (connector) {
456 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
457 bpc = amdgpu_connector_get_monitor_bpc(connector);
458 dither = amdgpu_connector->dither;
459 }
460
461 /* LVDS/eDP FMT is set up by atom */
462 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
463 return;
464
465 /* not needed for analog */
466 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
467 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
468 return;
469
470 if (bpc == 0)
471 return;
472
473 switch (bpc) {
474 case 6:
475 if (dither == AMDGPU_FMT_DITHER_ENABLE)
476 /* XXX sort out optimal dither settings */
477 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
478 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
479 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
480 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
481 else
482 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
483 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
484 break;
485 case 8:
486 if (dither == AMDGPU_FMT_DITHER_ENABLE)
487 /* XXX sort out optimal dither settings */
488 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
489 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
490 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
491 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
492 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
493 else
494 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
495 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
496 break;
497 case 10:
498 if (dither == AMDGPU_FMT_DITHER_ENABLE)
499 /* XXX sort out optimal dither settings */
500 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
501 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
502 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
503 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
504 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
505 else
506 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
507 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
508 break;
509 default:
510 /* not needed */
511 break;
512 }
513
514 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
515}
516
517
518/* display watermark setup */
519/**
520 * dce_v8_0_line_buffer_adjust - Set up the line buffer
521 *
522 * @adev: amdgpu_device pointer
523 * @amdgpu_crtc: the selected display controller
524 * @mode: the current display mode on the selected display
525 * controller
526 *
527 * Setup up the line buffer allocation for
528 * the selected display controller (CIK).
529 * Returns the line buffer size in pixels.
530 */
531static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
532 struct amdgpu_crtc *amdgpu_crtc,
533 struct drm_display_mode *mode)
534{
535 u32 tmp, buffer_alloc, i;
536 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
537 /*
538 * Line Buffer Setup
539 * There are 6 line buffers, one for each display controllers.
540 * There are 3 partitions per LB. Select the number of partitions
541 * to enable based on the display width. For display widths larger
542 * than 4096, you need use to use 2 display controllers and combine
543 * them using the stereo blender.
544 */
545 if (amdgpu_crtc->base.enabled && mode) {
546 if (mode->crtc_hdisplay < 1920) {
547 tmp = 1;
548 buffer_alloc = 2;
549 } else if (mode->crtc_hdisplay < 2560) {
550 tmp = 2;
551 buffer_alloc = 2;
552 } else if (mode->crtc_hdisplay < 4096) {
553 tmp = 0;
554 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
555 } else {
556 DRM_DEBUG_KMS("Mode too big for LB!\n");
557 tmp = 0;
558 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
559 }
560 } else {
561 tmp = 1;
562 buffer_alloc = 0;
563 }
564
565 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
566 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
567 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
568
569 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
570 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
571 for (i = 0; i < adev->usec_timeout; i++) {
572 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
573 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
574 break;
575 udelay(1);
576 }
577
578 if (amdgpu_crtc->base.enabled && mode) {
579 switch (tmp) {
580 case 0:
581 default:
582 return 4096 * 2;
583 case 1:
584 return 1920 * 2;
585 case 2:
586 return 2560 * 2;
587 }
588 }
589
590 /* controller not enabled, so no lb used */
591 return 0;
592}
593
594/**
595 * cik_get_number_of_dram_channels - get the number of dram channels
596 *
597 * @adev: amdgpu_device pointer
598 *
599 * Look up the number of video ram channels (CIK).
600 * Used for display watermark bandwidth calculations
601 * Returns the number of dram channels
602 */
603static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
604{
605 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
606
607 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
608 case 0:
609 default:
610 return 1;
611 case 1:
612 return 2;
613 case 2:
614 return 4;
615 case 3:
616 return 8;
617 case 4:
618 return 3;
619 case 5:
620 return 6;
621 case 6:
622 return 10;
623 case 7:
624 return 12;
625 case 8:
626 return 16;
627 }
628}
629
630struct dce8_wm_params {
631 u32 dram_channels; /* number of dram channels */
632 u32 yclk; /* bandwidth per dram data pin in kHz */
633 u32 sclk; /* engine clock in kHz */
634 u32 disp_clk; /* display clock in kHz */
635 u32 src_width; /* viewport width */
636 u32 active_time; /* active display time in ns */
637 u32 blank_time; /* blank time in ns */
638 bool interlaced; /* mode is interlaced */
639 fixed20_12 vsc; /* vertical scale ratio */
640 u32 num_heads; /* number of active crtcs */
641 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
642 u32 lb_size; /* line buffer allocated to pipe */
643 u32 vtaps; /* vertical scaler taps */
644};
645
646/**
647 * dce_v8_0_dram_bandwidth - get the dram bandwidth
648 *
649 * @wm: watermark calculation data
650 *
651 * Calculate the raw dram bandwidth (CIK).
652 * Used for display watermark bandwidth calculations
653 * Returns the dram bandwidth in MBytes/s
654 */
655static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
656{
657 /* Calculate raw DRAM Bandwidth */
658 fixed20_12 dram_efficiency; /* 0.7 */
659 fixed20_12 yclk, dram_channels, bandwidth;
660 fixed20_12 a;
661
662 a.full = dfixed_const(1000);
663 yclk.full = dfixed_const(wm->yclk);
664 yclk.full = dfixed_div(yclk, a);
665 dram_channels.full = dfixed_const(wm->dram_channels * 4);
666 a.full = dfixed_const(10);
667 dram_efficiency.full = dfixed_const(7);
668 dram_efficiency.full = dfixed_div(dram_efficiency, a);
669 bandwidth.full = dfixed_mul(dram_channels, yclk);
670 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
671
672 return dfixed_trunc(bandwidth);
673}
674
675/**
676 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
677 *
678 * @wm: watermark calculation data
679 *
680 * Calculate the dram bandwidth used for display (CIK).
681 * Used for display watermark bandwidth calculations
682 * Returns the dram bandwidth for display in MBytes/s
683 */
684static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
685{
686 /* Calculate DRAM Bandwidth and the part allocated to display. */
687 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
688 fixed20_12 yclk, dram_channels, bandwidth;
689 fixed20_12 a;
690
691 a.full = dfixed_const(1000);
692 yclk.full = dfixed_const(wm->yclk);
693 yclk.full = dfixed_div(yclk, a);
694 dram_channels.full = dfixed_const(wm->dram_channels * 4);
695 a.full = dfixed_const(10);
696 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
697 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
698 bandwidth.full = dfixed_mul(dram_channels, yclk);
699 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
700
701 return dfixed_trunc(bandwidth);
702}
703
704/**
705 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
706 *
707 * @wm: watermark calculation data
708 *
709 * Calculate the data return bandwidth used for display (CIK).
710 * Used for display watermark bandwidth calculations
711 * Returns the data return bandwidth in MBytes/s
712 */
713static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
714{
715 /* Calculate the display Data return Bandwidth */
716 fixed20_12 return_efficiency; /* 0.8 */
717 fixed20_12 sclk, bandwidth;
718 fixed20_12 a;
719
720 a.full = dfixed_const(1000);
721 sclk.full = dfixed_const(wm->sclk);
722 sclk.full = dfixed_div(sclk, a);
723 a.full = dfixed_const(10);
724 return_efficiency.full = dfixed_const(8);
725 return_efficiency.full = dfixed_div(return_efficiency, a);
726 a.full = dfixed_const(32);
727 bandwidth.full = dfixed_mul(a, sclk);
728 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
729
730 return dfixed_trunc(bandwidth);
731}
732
733/**
734 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
735 *
736 * @wm: watermark calculation data
737 *
738 * Calculate the dmif bandwidth used for display (CIK).
739 * Used for display watermark bandwidth calculations
740 * Returns the dmif bandwidth in MBytes/s
741 */
742static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
743{
744 /* Calculate the DMIF Request Bandwidth */
745 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
746 fixed20_12 disp_clk, bandwidth;
747 fixed20_12 a, b;
748
749 a.full = dfixed_const(1000);
750 disp_clk.full = dfixed_const(wm->disp_clk);
751 disp_clk.full = dfixed_div(disp_clk, a);
752 a.full = dfixed_const(32);
753 b.full = dfixed_mul(a, disp_clk);
754
755 a.full = dfixed_const(10);
756 disp_clk_request_efficiency.full = dfixed_const(8);
757 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
758
759 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
760
761 return dfixed_trunc(bandwidth);
762}
763
764/**
765 * dce_v8_0_available_bandwidth - get the min available bandwidth
766 *
767 * @wm: watermark calculation data
768 *
769 * Calculate the min available bandwidth used for display (CIK).
770 * Used for display watermark bandwidth calculations
771 * Returns the min available bandwidth in MBytes/s
772 */
773static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
774{
775 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
776 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
777 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
778 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
779
780 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
781}
782
783/**
784 * dce_v8_0_average_bandwidth - get the average available bandwidth
785 *
786 * @wm: watermark calculation data
787 *
788 * Calculate the average available bandwidth used for display (CIK).
789 * Used for display watermark bandwidth calculations
790 * Returns the average available bandwidth in MBytes/s
791 */
792static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
793{
794 /* Calculate the display mode Average Bandwidth
795 * DisplayMode should contain the source and destination dimensions,
796 * timing, etc.
797 */
798 fixed20_12 bpp;
799 fixed20_12 line_time;
800 fixed20_12 src_width;
801 fixed20_12 bandwidth;
802 fixed20_12 a;
803
804 a.full = dfixed_const(1000);
805 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
806 line_time.full = dfixed_div(line_time, a);
807 bpp.full = dfixed_const(wm->bytes_per_pixel);
808 src_width.full = dfixed_const(wm->src_width);
809 bandwidth.full = dfixed_mul(src_width, bpp);
810 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
811 bandwidth.full = dfixed_div(bandwidth, line_time);
812
813 return dfixed_trunc(bandwidth);
814}
815
816/**
817 * dce_v8_0_latency_watermark - get the latency watermark
818 *
819 * @wm: watermark calculation data
820 *
821 * Calculate the latency watermark (CIK).
822 * Used for display watermark bandwidth calculations
823 * Returns the latency watermark in ns
824 */
825static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
826{
827 /* First calculate the latency in ns */
828 u32 mc_latency = 2000; /* 2000 ns. */
829 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
830 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
831 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
832 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
833 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
834 (wm->num_heads * cursor_line_pair_return_time);
835 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
836 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
837 u32 tmp, dmif_size = 12288;
838 fixed20_12 a, b, c;
839
840 if (wm->num_heads == 0)
841 return 0;
842
843 a.full = dfixed_const(2);
844 b.full = dfixed_const(1);
845 if ((wm->vsc.full > a.full) ||
846 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
847 (wm->vtaps >= 5) ||
848 ((wm->vsc.full >= a.full) && wm->interlaced))
849 max_src_lines_per_dst_line = 4;
850 else
851 max_src_lines_per_dst_line = 2;
852
853 a.full = dfixed_const(available_bandwidth);
854 b.full = dfixed_const(wm->num_heads);
855 a.full = dfixed_div(a, b);
856 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
857 tmp = min(dfixed_trunc(a), tmp);
858
859 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
860
861 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
862 b.full = dfixed_const(1000);
863 c.full = dfixed_const(lb_fill_bw);
864 b.full = dfixed_div(c, b);
865 a.full = dfixed_div(a, b);
866 line_fill_time = dfixed_trunc(a);
867
868 if (line_fill_time < wm->active_time)
869 return latency;
870 else
871 return latency + (line_fill_time - wm->active_time);
872
873}
874
875/**
876 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
877 * average and available dram bandwidth
878 *
879 * @wm: watermark calculation data
880 *
881 * Check if the display average bandwidth fits in the display
882 * dram bandwidth (CIK).
883 * Used for display watermark bandwidth calculations
884 * Returns true if the display fits, false if not.
885 */
886static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
887{
888 if (dce_v8_0_average_bandwidth(wm) <=
889 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
890 return true;
891 else
892 return false;
893}
894
895/**
896 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
897 * average and available bandwidth
898 *
899 * @wm: watermark calculation data
900 *
901 * Check if the display average bandwidth fits in the display
902 * available bandwidth (CIK).
903 * Used for display watermark bandwidth calculations
904 * Returns true if the display fits, false if not.
905 */
906static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
907{
908 if (dce_v8_0_average_bandwidth(wm) <=
909 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
910 return true;
911 else
912 return false;
913}
914
915/**
916 * dce_v8_0_check_latency_hiding - check latency hiding
917 *
918 * @wm: watermark calculation data
919 *
920 * Check latency hiding (CIK).
921 * Used for display watermark bandwidth calculations
922 * Returns true if the display fits, false if not.
923 */
924static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
925{
926 u32 lb_partitions = wm->lb_size / wm->src_width;
927 u32 line_time = wm->active_time + wm->blank_time;
928 u32 latency_tolerant_lines;
929 u32 latency_hiding;
930 fixed20_12 a;
931
932 a.full = dfixed_const(1);
933 if (wm->vsc.full > a.full)
934 latency_tolerant_lines = 1;
935 else {
936 if (lb_partitions <= (wm->vtaps + 1))
937 latency_tolerant_lines = 1;
938 else
939 latency_tolerant_lines = 2;
940 }
941
942 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
943
944 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
945 return true;
946 else
947 return false;
948}
949
950/**
951 * dce_v8_0_program_watermarks - program display watermarks
952 *
953 * @adev: amdgpu_device pointer
954 * @amdgpu_crtc: the selected display controller
955 * @lb_size: line buffer size
956 * @num_heads: number of display controllers in use
957 *
958 * Calculate and program the display watermarks for the
959 * selected display controller (CIK).
960 */
961static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
962 struct amdgpu_crtc *amdgpu_crtc,
963 u32 lb_size, u32 num_heads)
964{
965 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
966 struct dce8_wm_params wm_low, wm_high;
967 u32 active_time;
968 u32 line_time = 0;
969 u32 latency_watermark_a = 0, latency_watermark_b = 0;
970 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
971
972 if (amdgpu_crtc->base.enabled && num_heads && mode) {
973 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
974 (u32)mode->clock);
975 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
976 (u32)mode->clock);
977 line_time = min(line_time, (u32)65535);
978
979 /* watermark for high clocks */
980 if (adev->pm.dpm_enabled) {
981 wm_high.yclk =
982 amdgpu_dpm_get_mclk(adev, false) * 10;
983 wm_high.sclk =
984 amdgpu_dpm_get_sclk(adev, false) * 10;
985 } else {
986 wm_high.yclk = adev->pm.current_mclk * 10;
987 wm_high.sclk = adev->pm.current_sclk * 10;
988 }
989
990 wm_high.disp_clk = mode->clock;
991 wm_high.src_width = mode->crtc_hdisplay;
992 wm_high.active_time = active_time;
993 wm_high.blank_time = line_time - wm_high.active_time;
994 wm_high.interlaced = false;
995 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
996 wm_high.interlaced = true;
997 wm_high.vsc = amdgpu_crtc->vsc;
998 wm_high.vtaps = 1;
999 if (amdgpu_crtc->rmx_type != RMX_OFF)
1000 wm_high.vtaps = 2;
1001 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1002 wm_high.lb_size = lb_size;
1003 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1004 wm_high.num_heads = num_heads;
1005
1006 /* set for high clocks */
1007 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1008
1009 /* possibly force display priority to high */
1010 /* should really do this at mode validation time... */
1011 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1012 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1013 !dce_v8_0_check_latency_hiding(&wm_high) ||
1014 (adev->mode_info.disp_priority == 2)) {
1015 DRM_DEBUG_KMS("force priority to high\n");
1016 }
1017
1018 /* watermark for low clocks */
1019 if (adev->pm.dpm_enabled) {
1020 wm_low.yclk =
1021 amdgpu_dpm_get_mclk(adev, true) * 10;
1022 wm_low.sclk =
1023 amdgpu_dpm_get_sclk(adev, true) * 10;
1024 } else {
1025 wm_low.yclk = adev->pm.current_mclk * 10;
1026 wm_low.sclk = adev->pm.current_sclk * 10;
1027 }
1028
1029 wm_low.disp_clk = mode->clock;
1030 wm_low.src_width = mode->crtc_hdisplay;
1031 wm_low.active_time = active_time;
1032 wm_low.blank_time = line_time - wm_low.active_time;
1033 wm_low.interlaced = false;
1034 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1035 wm_low.interlaced = true;
1036 wm_low.vsc = amdgpu_crtc->vsc;
1037 wm_low.vtaps = 1;
1038 if (amdgpu_crtc->rmx_type != RMX_OFF)
1039 wm_low.vtaps = 2;
1040 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1041 wm_low.lb_size = lb_size;
1042 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1043 wm_low.num_heads = num_heads;
1044
1045 /* set for low clocks */
1046 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1047
1048 /* possibly force display priority to high */
1049 /* should really do this at mode validation time... */
1050 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1051 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1052 !dce_v8_0_check_latency_hiding(&wm_low) ||
1053 (adev->mode_info.disp_priority == 2)) {
1054 DRM_DEBUG_KMS("force priority to high\n");
1055 }
1056 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1057 }
1058
1059 /* select wm A */
1060 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1061 tmp = wm_mask;
1062 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1063 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1064 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1065 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1066 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1067 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1068 /* select wm B */
1069 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1070 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1071 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1072 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1073 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1074 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1075 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1076 /* restore original selection */
1077 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1078
1079 /* save values for DPM */
1080 amdgpu_crtc->line_time = line_time;
1081 amdgpu_crtc->wm_high = latency_watermark_a;
1082 amdgpu_crtc->wm_low = latency_watermark_b;
1083 /* Save number of lines the linebuffer leads before the scanout */
1084 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1085}
1086
1087/**
1088 * dce_v8_0_bandwidth_update - program display watermarks
1089 *
1090 * @adev: amdgpu_device pointer
1091 *
1092 * Calculate and program the display watermarks and line
1093 * buffer allocation (CIK).
1094 */
1095static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1096{
1097 struct drm_display_mode *mode = NULL;
1098 u32 num_heads = 0, lb_size;
1099 int i;
1100
1101 amdgpu_display_update_priority(adev);
1102
1103 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1104 if (adev->mode_info.crtcs[i]->base.enabled)
1105 num_heads++;
1106 }
1107 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1108 mode = &adev->mode_info.crtcs[i]->base.mode;
1109 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1110 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1111 lb_size, num_heads);
1112 }
1113}
1114
1115static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1116{
1117 int i;
1118 u32 offset, tmp;
1119
1120 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1121 offset = adev->mode_info.audio.pin[i].offset;
1122 tmp = RREG32_AUDIO_ENDPT(offset,
1123 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1124 if (((tmp &
1125 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1126 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1127 adev->mode_info.audio.pin[i].connected = false;
1128 else
1129 adev->mode_info.audio.pin[i].connected = true;
1130 }
1131}
1132
1133static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1134{
1135 int i;
1136
1137 dce_v8_0_audio_get_connected_pins(adev);
1138
1139 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1140 if (adev->mode_info.audio.pin[i].connected)
1141 return &adev->mode_info.audio.pin[i];
1142 }
1143 DRM_ERROR("No connected audio pins found!\n");
1144 return NULL;
1145}
1146
1147static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1148{
1149 struct amdgpu_device *adev = encoder->dev->dev_private;
1150 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1151 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1152 u32 offset;
1153
1154 if (!dig || !dig->afmt || !dig->afmt->pin)
1155 return;
1156
1157 offset = dig->afmt->offset;
1158
1159 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1160 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1161}
1162
1163static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1164 struct drm_display_mode *mode)
1165{
1166 struct drm_device *dev = encoder->dev;
1167 struct amdgpu_device *adev = dev->dev_private;
1168 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1169 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1170 struct drm_connector *connector;
1171 struct drm_connector_list_iter iter;
1172 struct amdgpu_connector *amdgpu_connector = NULL;
1173 u32 tmp = 0, offset;
1174
1175 if (!dig || !dig->afmt || !dig->afmt->pin)
1176 return;
1177
1178 offset = dig->afmt->pin->offset;
1179
1180 drm_connector_list_iter_begin(dev, &iter);
1181 drm_for_each_connector_iter(connector, &iter) {
1182 if (connector->encoder == encoder) {
1183 amdgpu_connector = to_amdgpu_connector(connector);
1184 break;
1185 }
1186 }
1187 drm_connector_list_iter_end(&iter);
1188
1189 if (!amdgpu_connector) {
1190 DRM_ERROR("Couldn't find encoder's connector\n");
1191 return;
1192 }
1193
1194 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1195 if (connector->latency_present[1])
1196 tmp =
1197 (connector->video_latency[1] <<
1198 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1199 (connector->audio_latency[1] <<
1200 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1201 else
1202 tmp =
1203 (0 <<
1204 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1205 (0 <<
1206 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1207 } else {
1208 if (connector->latency_present[0])
1209 tmp =
1210 (connector->video_latency[0] <<
1211 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1212 (connector->audio_latency[0] <<
1213 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1214 else
1215 tmp =
1216 (0 <<
1217 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1218 (0 <<
1219 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1220
1221 }
1222 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1223}
1224
1225static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1226{
1227 struct drm_device *dev = encoder->dev;
1228 struct amdgpu_device *adev = dev->dev_private;
1229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1231 struct drm_connector *connector;
1232 struct drm_connector_list_iter iter;
1233 struct amdgpu_connector *amdgpu_connector = NULL;
1234 u32 offset, tmp;
1235 u8 *sadb = NULL;
1236 int sad_count;
1237
1238 if (!dig || !dig->afmt || !dig->afmt->pin)
1239 return;
1240
1241 offset = dig->afmt->pin->offset;
1242
1243 drm_connector_list_iter_begin(dev, &iter);
1244 drm_for_each_connector_iter(connector, &iter) {
1245 if (connector->encoder == encoder) {
1246 amdgpu_connector = to_amdgpu_connector(connector);
1247 break;
1248 }
1249 }
1250 drm_connector_list_iter_end(&iter);
1251
1252 if (!amdgpu_connector) {
1253 DRM_ERROR("Couldn't find encoder's connector\n");
1254 return;
1255 }
1256
1257 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1258 if (sad_count < 0) {
1259 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1260 sad_count = 0;
1261 }
1262
1263 /* program the speaker allocation */
1264 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1265 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1266 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1267 /* set HDMI mode */
1268 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1269 if (sad_count)
1270 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1271 else
1272 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1273 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1274
1275 kfree(sadb);
1276}
1277
1278static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1279{
1280 struct drm_device *dev = encoder->dev;
1281 struct amdgpu_device *adev = dev->dev_private;
1282 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1283 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1284 u32 offset;
1285 struct drm_connector *connector;
1286 struct drm_connector_list_iter iter;
1287 struct amdgpu_connector *amdgpu_connector = NULL;
1288 struct cea_sad *sads;
1289 int i, sad_count;
1290
1291 static const u16 eld_reg_to_type[][2] = {
1292 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1293 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1294 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1295 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1296 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1297 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1298 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1299 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1300 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1301 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1302 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1303 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1304 };
1305
1306 if (!dig || !dig->afmt || !dig->afmt->pin)
1307 return;
1308
1309 offset = dig->afmt->pin->offset;
1310
1311 drm_connector_list_iter_begin(dev, &iter);
1312 drm_for_each_connector_iter(connector, &iter) {
1313 if (connector->encoder == encoder) {
1314 amdgpu_connector = to_amdgpu_connector(connector);
1315 break;
1316 }
1317 }
1318 drm_connector_list_iter_end(&iter);
1319
1320 if (!amdgpu_connector) {
1321 DRM_ERROR("Couldn't find encoder's connector\n");
1322 return;
1323 }
1324
1325 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1326 if (sad_count < 0)
1327 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1328 if (sad_count <= 0)
1329 return;
1330 BUG_ON(!sads);
1331
1332 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1333 u32 value = 0;
1334 u8 stereo_freqs = 0;
1335 int max_channels = -1;
1336 int j;
1337
1338 for (j = 0; j < sad_count; j++) {
1339 struct cea_sad *sad = &sads[j];
1340
1341 if (sad->format == eld_reg_to_type[i][1]) {
1342 if (sad->channels > max_channels) {
1343 value = (sad->channels <<
1344 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1345 (sad->byte2 <<
1346 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1347 (sad->freq <<
1348 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1349 max_channels = sad->channels;
1350 }
1351
1352 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1353 stereo_freqs |= sad->freq;
1354 else
1355 break;
1356 }
1357 }
1358
1359 value |= (stereo_freqs <<
1360 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1361
1362 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1363 }
1364
1365 kfree(sads);
1366}
1367
1368static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1369 struct amdgpu_audio_pin *pin,
1370 bool enable)
1371{
1372 if (!pin)
1373 return;
1374
1375 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1376 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1377}
1378
1379static const u32 pin_offsets[7] =
1380{
1381 (0x1780 - 0x1780),
1382 (0x1786 - 0x1780),
1383 (0x178c - 0x1780),
1384 (0x1792 - 0x1780),
1385 (0x1798 - 0x1780),
1386 (0x179d - 0x1780),
1387 (0x17a4 - 0x1780),
1388};
1389
1390static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1391{
1392 int i;
1393
1394 if (!amdgpu_audio)
1395 return 0;
1396
1397 adev->mode_info.audio.enabled = true;
1398
1399 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1400 adev->mode_info.audio.num_pins = 7;
1401 else if ((adev->asic_type == CHIP_KABINI) ||
1402 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1403 adev->mode_info.audio.num_pins = 3;
1404 else if ((adev->asic_type == CHIP_BONAIRE) ||
1405 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1406 adev->mode_info.audio.num_pins = 7;
1407 else
1408 adev->mode_info.audio.num_pins = 3;
1409
1410 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1411 adev->mode_info.audio.pin[i].channels = -1;
1412 adev->mode_info.audio.pin[i].rate = -1;
1413 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1414 adev->mode_info.audio.pin[i].status_bits = 0;
1415 adev->mode_info.audio.pin[i].category_code = 0;
1416 adev->mode_info.audio.pin[i].connected = false;
1417 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1418 adev->mode_info.audio.pin[i].id = i;
1419 /* disable audio. it will be set up later */
1420 /* XXX remove once we switch to ip funcs */
1421 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1422 }
1423
1424 return 0;
1425}
1426
1427static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1428{
1429 int i;
1430
1431 if (!amdgpu_audio)
1432 return;
1433
1434 if (!adev->mode_info.audio.enabled)
1435 return;
1436
1437 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1438 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1439
1440 adev->mode_info.audio.enabled = false;
1441}
1442
1443/*
1444 * update the N and CTS parameters for a given pixel clock rate
1445 */
1446static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1447{
1448 struct drm_device *dev = encoder->dev;
1449 struct amdgpu_device *adev = dev->dev_private;
1450 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1451 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1452 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1453 uint32_t offset = dig->afmt->offset;
1454
1455 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1456 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1457
1458 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1459 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1460
1461 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1462 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1463}
1464
1465/*
1466 * build a HDMI Video Info Frame
1467 */
1468static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1469 void *buffer, size_t size)
1470{
1471 struct drm_device *dev = encoder->dev;
1472 struct amdgpu_device *adev = dev->dev_private;
1473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1475 uint32_t offset = dig->afmt->offset;
1476 uint8_t *frame = buffer + 3;
1477 uint8_t *header = buffer;
1478
1479 WREG32(mmAFMT_AVI_INFO0 + offset,
1480 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1481 WREG32(mmAFMT_AVI_INFO1 + offset,
1482 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1483 WREG32(mmAFMT_AVI_INFO2 + offset,
1484 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1485 WREG32(mmAFMT_AVI_INFO3 + offset,
1486 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1487}
1488
1489static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1490{
1491 struct drm_device *dev = encoder->dev;
1492 struct amdgpu_device *adev = dev->dev_private;
1493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1494 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1495 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1496 u32 dto_phase = 24 * 1000;
1497 u32 dto_modulo = clock;
1498
1499 if (!dig || !dig->afmt)
1500 return;
1501
1502 /* XXX two dtos; generally use dto0 for hdmi */
1503 /* Express [24MHz / target pixel clock] as an exact rational
1504 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1505 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1506 */
1507 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1508 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1509 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1510}
1511
1512/*
1513 * update the info frames with the data from the current display mode
1514 */
1515static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1516 struct drm_display_mode *mode)
1517{
1518 struct drm_device *dev = encoder->dev;
1519 struct amdgpu_device *adev = dev->dev_private;
1520 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1521 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1522 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1523 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1524 struct hdmi_avi_infoframe frame;
1525 uint32_t offset, val;
1526 ssize_t err;
1527 int bpc = 8;
1528
1529 if (!dig || !dig->afmt)
1530 return;
1531
1532 /* Silent, r600_hdmi_enable will raise WARN for us */
1533 if (!dig->afmt->enabled)
1534 return;
1535
1536 offset = dig->afmt->offset;
1537
1538 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1539 if (encoder->crtc) {
1540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1541 bpc = amdgpu_crtc->bpc;
1542 }
1543
1544 /* disable audio prior to setting up hw */
1545 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1546 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1547
1548 dce_v8_0_audio_set_dto(encoder, mode->clock);
1549
1550 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1551 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1552
1553 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1554
1555 val = RREG32(mmHDMI_CONTROL + offset);
1556 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1557 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1558
1559 switch (bpc) {
1560 case 0:
1561 case 6:
1562 case 8:
1563 case 16:
1564 default:
1565 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1566 connector->name, bpc);
1567 break;
1568 case 10:
1569 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1570 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1571 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1572 connector->name);
1573 break;
1574 case 12:
1575 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1576 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1577 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1578 connector->name);
1579 break;
1580 }
1581
1582 WREG32(mmHDMI_CONTROL + offset, val);
1583
1584 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1585 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1586 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1587 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1588
1589 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1590 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1591 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1592
1593 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1594 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1595
1596 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1597 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1598
1599 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1600
1601 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1602 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1603 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1604
1605 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1606 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1607
1608 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1609
1610 if (bpc > 8)
1611 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1612 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1613 else
1614 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1615 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1616 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1617
1618 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1619
1620 WREG32(mmAFMT_60958_0 + offset,
1621 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1622
1623 WREG32(mmAFMT_60958_1 + offset,
1624 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1625
1626 WREG32(mmAFMT_60958_2 + offset,
1627 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1628 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1629 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1630 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1631 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1632 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1633
1634 dce_v8_0_audio_write_speaker_allocation(encoder);
1635
1636
1637 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1638 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1639
1640 dce_v8_0_afmt_audio_select_pin(encoder);
1641 dce_v8_0_audio_write_sad_regs(encoder);
1642 dce_v8_0_audio_write_latency_fields(encoder, mode);
1643
1644 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1645 if (err < 0) {
1646 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1647 return;
1648 }
1649
1650 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1651 if (err < 0) {
1652 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1653 return;
1654 }
1655
1656 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1657
1658 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1659 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1660 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1661
1662 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1663 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1664 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1665
1666 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1667 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1668
1669 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1670 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1671 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1672 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1673
1674 /* enable audio after setting up hw */
1675 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1676}
1677
1678static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1679{
1680 struct drm_device *dev = encoder->dev;
1681 struct amdgpu_device *adev = dev->dev_private;
1682 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1683 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1684
1685 if (!dig || !dig->afmt)
1686 return;
1687
1688 /* Silent, r600_hdmi_enable will raise WARN for us */
1689 if (enable && dig->afmt->enabled)
1690 return;
1691 if (!enable && !dig->afmt->enabled)
1692 return;
1693
1694 if (!enable && dig->afmt->pin) {
1695 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1696 dig->afmt->pin = NULL;
1697 }
1698
1699 dig->afmt->enabled = enable;
1700
1701 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1702 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1703}
1704
1705static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1706{
1707 int i;
1708
1709 for (i = 0; i < adev->mode_info.num_dig; i++)
1710 adev->mode_info.afmt[i] = NULL;
1711
1712 /* DCE8 has audio blocks tied to DIG encoders */
1713 for (i = 0; i < adev->mode_info.num_dig; i++) {
1714 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1715 if (adev->mode_info.afmt[i]) {
1716 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1717 adev->mode_info.afmt[i]->id = i;
1718 } else {
1719 int j;
1720 for (j = 0; j < i; j++) {
1721 kfree(adev->mode_info.afmt[j]);
1722 adev->mode_info.afmt[j] = NULL;
1723 }
1724 return -ENOMEM;
1725 }
1726 }
1727 return 0;
1728}
1729
1730static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1731{
1732 int i;
1733
1734 for (i = 0; i < adev->mode_info.num_dig; i++) {
1735 kfree(adev->mode_info.afmt[i]);
1736 adev->mode_info.afmt[i] = NULL;
1737 }
1738}
1739
1740static const u32 vga_control_regs[6] =
1741{
1742 mmD1VGA_CONTROL,
1743 mmD2VGA_CONTROL,
1744 mmD3VGA_CONTROL,
1745 mmD4VGA_CONTROL,
1746 mmD5VGA_CONTROL,
1747 mmD6VGA_CONTROL,
1748};
1749
1750static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1751{
1752 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1753 struct drm_device *dev = crtc->dev;
1754 struct amdgpu_device *adev = dev->dev_private;
1755 u32 vga_control;
1756
1757 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1758 if (enable)
1759 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1760 else
1761 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1762}
1763
1764static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1765{
1766 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1767 struct drm_device *dev = crtc->dev;
1768 struct amdgpu_device *adev = dev->dev_private;
1769
1770 if (enable)
1771 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1772 else
1773 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1774}
1775
1776static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1777 struct drm_framebuffer *fb,
1778 int x, int y, int atomic)
1779{
1780 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1781 struct drm_device *dev = crtc->dev;
1782 struct amdgpu_device *adev = dev->dev_private;
1783 struct drm_framebuffer *target_fb;
1784 struct drm_gem_object *obj;
1785 struct amdgpu_bo *abo;
1786 uint64_t fb_location, tiling_flags;
1787 uint32_t fb_format, fb_pitch_pixels;
1788 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1789 u32 pipe_config;
1790 u32 viewport_w, viewport_h;
1791 int r;
1792 bool bypass_lut = false;
1793 struct drm_format_name_buf format_name;
1794
1795 /* no fb bound */
1796 if (!atomic && !crtc->primary->fb) {
1797 DRM_DEBUG_KMS("No FB bound\n");
1798 return 0;
1799 }
1800
1801 if (atomic)
1802 target_fb = fb;
1803 else
1804 target_fb = crtc->primary->fb;
1805
1806 /* If atomic, assume fb object is pinned & idle & fenced and
1807 * just update base pointers
1808 */
1809 obj = target_fb->obj[0];
1810 abo = gem_to_amdgpu_bo(obj);
1811 r = amdgpu_bo_reserve(abo, false);
1812 if (unlikely(r != 0))
1813 return r;
1814
1815 if (!atomic) {
1816 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1817 if (unlikely(r != 0)) {
1818 amdgpu_bo_unreserve(abo);
1819 return -EINVAL;
1820 }
1821 }
1822 fb_location = amdgpu_bo_gpu_offset(abo);
1823
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825 amdgpu_bo_unreserve(abo);
1826
1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1828
1829 switch (target_fb->format->format) {
1830 case DRM_FORMAT_C8:
1831 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1832 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1833 break;
1834 case DRM_FORMAT_XRGB4444:
1835 case DRM_FORMAT_ARGB4444:
1836 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1837 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1838#ifdef __BIG_ENDIAN
1839 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1840#endif
1841 break;
1842 case DRM_FORMAT_XRGB1555:
1843 case DRM_FORMAT_ARGB1555:
1844 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1845 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1846#ifdef __BIG_ENDIAN
1847 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1848#endif
1849 break;
1850 case DRM_FORMAT_BGRX5551:
1851 case DRM_FORMAT_BGRA5551:
1852 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1853 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1854#ifdef __BIG_ENDIAN
1855 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1856#endif
1857 break;
1858 case DRM_FORMAT_RGB565:
1859 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1860 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1861#ifdef __BIG_ENDIAN
1862 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1863#endif
1864 break;
1865 case DRM_FORMAT_XRGB8888:
1866 case DRM_FORMAT_ARGB8888:
1867 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1868 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1869#ifdef __BIG_ENDIAN
1870 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1871#endif
1872 break;
1873 case DRM_FORMAT_XRGB2101010:
1874 case DRM_FORMAT_ARGB2101010:
1875 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1876 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1877#ifdef __BIG_ENDIAN
1878 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1879#endif
1880 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1881 bypass_lut = true;
1882 break;
1883 case DRM_FORMAT_BGRX1010102:
1884 case DRM_FORMAT_BGRA1010102:
1885 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1886 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1887#ifdef __BIG_ENDIAN
1888 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1889#endif
1890 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1891 bypass_lut = true;
1892 break;
1893 case DRM_FORMAT_XBGR8888:
1894 case DRM_FORMAT_ABGR8888:
1895 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1896 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1897 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1898 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1899#ifdef __BIG_ENDIAN
1900 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1901#endif
1902 break;
1903 default:
1904 DRM_ERROR("Unsupported screen format %s\n",
1905 drm_get_format_name(target_fb->format->format, &format_name));
1906 return -EINVAL;
1907 }
1908
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1911
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1917
1918 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1919 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1920 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1921 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1922 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1923 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1924 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1926 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1927 }
1928
1929 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1930
1931 dce_v8_0_vga_enable(crtc, false);
1932
1933 /* Make sure surface address is updated at vertical blank rather than
1934 * horizontal blank
1935 */
1936 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1937
1938 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1939 upper_32_bits(fb_location));
1940 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1941 upper_32_bits(fb_location));
1942 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1943 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1944 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1945 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1946 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1947 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1948
1949 /*
1950 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1951 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1952 * retain the full precision throughout the pipeline.
1953 */
1954 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1955 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1956 ~LUT_10BIT_BYPASS_EN);
1957
1958 if (bypass_lut)
1959 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1960
1961 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1962 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1963 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1964 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1965 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1966 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1967
1968 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1969 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1970
1971 dce_v8_0_grph_enable(crtc, true);
1972
1973 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1974 target_fb->height);
1975
1976 x &= ~3;
1977 y &= ~1;
1978 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1979 (x << 16) | y);
1980 viewport_w = crtc->mode.hdisplay;
1981 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1982 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1983 (viewport_w << 16) | viewport_h);
1984
1985 /* set pageflip to happen anywhere in vblank interval */
1986 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1987
1988 if (!atomic && fb && fb != crtc->primary->fb) {
1989 abo = gem_to_amdgpu_bo(fb->obj[0]);
1990 r = amdgpu_bo_reserve(abo, true);
1991 if (unlikely(r != 0))
1992 return r;
1993 amdgpu_bo_unpin(abo);
1994 amdgpu_bo_unreserve(abo);
1995 }
1996
1997 /* Bytes per pixel may have changed */
1998 dce_v8_0_bandwidth_update(adev);
1999
2000 return 0;
2001}
2002
2003static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2004 struct drm_display_mode *mode)
2005{
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = dev->dev_private;
2008 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009
2010 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2011 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2012 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2013 else
2014 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2015}
2016
2017static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2018{
2019 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020 struct drm_device *dev = crtc->dev;
2021 struct amdgpu_device *adev = dev->dev_private;
2022 u16 *r, *g, *b;
2023 int i;
2024
2025 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2026
2027 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2028 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2029 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2030 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2031 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2032 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2033 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2034 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2035 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2036 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2037
2038 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2039
2040 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2041 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2042 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2043
2044 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2045 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2046 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2047
2048 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2049 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2050
2051 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2052 r = crtc->gamma_store;
2053 g = r + crtc->gamma_size;
2054 b = g + crtc->gamma_size;
2055 for (i = 0; i < 256; i++) {
2056 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2057 ((*r++ & 0xffc0) << 14) |
2058 ((*g++ & 0xffc0) << 4) |
2059 (*b++ >> 6));
2060 }
2061
2062 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2063 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2064 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2065 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2066 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2067 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2068 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2069 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2070 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2071 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2072 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2073 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2074 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2075 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2076 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2077 /* XXX this only needs to be programmed once per crtc at startup,
2078 * not sure where the best place for it is
2079 */
2080 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2081 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2082}
2083
2084static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2085{
2086 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2087 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2088
2089 switch (amdgpu_encoder->encoder_id) {
2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2091 if (dig->linkb)
2092 return 1;
2093 else
2094 return 0;
2095 break;
2096 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2097 if (dig->linkb)
2098 return 3;
2099 else
2100 return 2;
2101 break;
2102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2103 if (dig->linkb)
2104 return 5;
2105 else
2106 return 4;
2107 break;
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2109 return 6;
2110 break;
2111 default:
2112 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2113 return 0;
2114 }
2115}
2116
2117/**
2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2119 *
2120 * @crtc: drm crtc
2121 *
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2125 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2126 * as there is no need to program the PLL itself. If we are not able to
2127 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2128 * avoid messing up an existing monitor.
2129 *
2130 * Asic specific PLL information
2131 *
2132 * DCE 8.x
2133 * KB/KV
2134 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2135 * CI
2136 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2137 *
2138 */
2139static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2140{
2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142 struct drm_device *dev = crtc->dev;
2143 struct amdgpu_device *adev = dev->dev_private;
2144 u32 pll_in_use;
2145 int pll;
2146
2147 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2148 if (adev->clock.dp_extclk)
2149 /* skip PPLL programming if using ext clock */
2150 return ATOM_PPLL_INVALID;
2151 else {
2152 /* use the same PPLL for all DP monitors */
2153 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2154 if (pll != ATOM_PPLL_INVALID)
2155 return pll;
2156 }
2157 } else {
2158 /* use the same PPLL for all monitors with the same clock */
2159 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2160 if (pll != ATOM_PPLL_INVALID)
2161 return pll;
2162 }
2163 /* otherwise, pick one of the plls */
2164 if ((adev->asic_type == CHIP_KABINI) ||
2165 (adev->asic_type == CHIP_MULLINS)) {
2166 /* KB/ML has PPLL1 and PPLL2 */
2167 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2168 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2169 return ATOM_PPLL2;
2170 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2171 return ATOM_PPLL1;
2172 DRM_ERROR("unable to allocate a PPLL\n");
2173 return ATOM_PPLL_INVALID;
2174 } else {
2175 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2176 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2177 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2178 return ATOM_PPLL2;
2179 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2180 return ATOM_PPLL1;
2181 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2182 return ATOM_PPLL0;
2183 DRM_ERROR("unable to allocate a PPLL\n");
2184 return ATOM_PPLL_INVALID;
2185 }
2186 return ATOM_PPLL_INVALID;
2187}
2188
2189static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2190{
2191 struct amdgpu_device *adev = crtc->dev->dev_private;
2192 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2193 uint32_t cur_lock;
2194
2195 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2196 if (lock)
2197 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2198 else
2199 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2200 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2201}
2202
2203static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2204{
2205 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2206 struct amdgpu_device *adev = crtc->dev->dev_private;
2207
2208 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2209 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2210 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2211}
2212
2213static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2214{
2215 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2216 struct amdgpu_device *adev = crtc->dev->dev_private;
2217
2218 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2219 upper_32_bits(amdgpu_crtc->cursor_addr));
2220 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2221 lower_32_bits(amdgpu_crtc->cursor_addr));
2222
2223 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2224 CUR_CONTROL__CURSOR_EN_MASK |
2225 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2226 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2227}
2228
2229static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2230 int x, int y)
2231{
2232 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2233 struct amdgpu_device *adev = crtc->dev->dev_private;
2234 int xorigin = 0, yorigin = 0;
2235
2236 amdgpu_crtc->cursor_x = x;
2237 amdgpu_crtc->cursor_y = y;
2238
2239 /* avivo cursor are offset into the total surface */
2240 x += crtc->x;
2241 y += crtc->y;
2242 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2243
2244 if (x < 0) {
2245 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2246 x = 0;
2247 }
2248 if (y < 0) {
2249 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2250 y = 0;
2251 }
2252
2253 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2254 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2255 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2256 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2257
2258 return 0;
2259}
2260
2261static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2262 int x, int y)
2263{
2264 int ret;
2265
2266 dce_v8_0_lock_cursor(crtc, true);
2267 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2268 dce_v8_0_lock_cursor(crtc, false);
2269
2270 return ret;
2271}
2272
2273static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2274 struct drm_file *file_priv,
2275 uint32_t handle,
2276 uint32_t width,
2277 uint32_t height,
2278 int32_t hot_x,
2279 int32_t hot_y)
2280{
2281 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2282 struct drm_gem_object *obj;
2283 struct amdgpu_bo *aobj;
2284 int ret;
2285
2286 if (!handle) {
2287 /* turn off cursor */
2288 dce_v8_0_hide_cursor(crtc);
2289 obj = NULL;
2290 goto unpin;
2291 }
2292
2293 if ((width > amdgpu_crtc->max_cursor_width) ||
2294 (height > amdgpu_crtc->max_cursor_height)) {
2295 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2296 return -EINVAL;
2297 }
2298
2299 obj = drm_gem_object_lookup(file_priv, handle);
2300 if (!obj) {
2301 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2302 return -ENOENT;
2303 }
2304
2305 aobj = gem_to_amdgpu_bo(obj);
2306 ret = amdgpu_bo_reserve(aobj, false);
2307 if (ret != 0) {
2308 drm_gem_object_put(obj);
2309 return ret;
2310 }
2311
2312 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2313 amdgpu_bo_unreserve(aobj);
2314 if (ret) {
2315 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2316 drm_gem_object_put(obj);
2317 return ret;
2318 }
2319 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2320
2321 dce_v8_0_lock_cursor(crtc, true);
2322
2323 if (width != amdgpu_crtc->cursor_width ||
2324 height != amdgpu_crtc->cursor_height ||
2325 hot_x != amdgpu_crtc->cursor_hot_x ||
2326 hot_y != amdgpu_crtc->cursor_hot_y) {
2327 int x, y;
2328
2329 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2330 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2331
2332 dce_v8_0_cursor_move_locked(crtc, x, y);
2333
2334 amdgpu_crtc->cursor_width = width;
2335 amdgpu_crtc->cursor_height = height;
2336 amdgpu_crtc->cursor_hot_x = hot_x;
2337 amdgpu_crtc->cursor_hot_y = hot_y;
2338 }
2339
2340 dce_v8_0_show_cursor(crtc);
2341 dce_v8_0_lock_cursor(crtc, false);
2342
2343unpin:
2344 if (amdgpu_crtc->cursor_bo) {
2345 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2346 ret = amdgpu_bo_reserve(aobj, true);
2347 if (likely(ret == 0)) {
2348 amdgpu_bo_unpin(aobj);
2349 amdgpu_bo_unreserve(aobj);
2350 }
2351 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2352 }
2353
2354 amdgpu_crtc->cursor_bo = obj;
2355 return 0;
2356}
2357
2358static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2359{
2360 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2361
2362 if (amdgpu_crtc->cursor_bo) {
2363 dce_v8_0_lock_cursor(crtc, true);
2364
2365 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2366 amdgpu_crtc->cursor_y);
2367
2368 dce_v8_0_show_cursor(crtc);
2369
2370 dce_v8_0_lock_cursor(crtc, false);
2371 }
2372}
2373
2374static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2375 u16 *blue, uint32_t size,
2376 struct drm_modeset_acquire_ctx *ctx)
2377{
2378 dce_v8_0_crtc_load_lut(crtc);
2379
2380 return 0;
2381}
2382
2383static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2384{
2385 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386
2387 drm_crtc_cleanup(crtc);
2388 kfree(amdgpu_crtc);
2389}
2390
2391static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2392 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2393 .cursor_move = dce_v8_0_crtc_cursor_move,
2394 .gamma_set = dce_v8_0_crtc_gamma_set,
2395 .set_config = amdgpu_display_crtc_set_config,
2396 .destroy = dce_v8_0_crtc_destroy,
2397 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2398 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2399 .enable_vblank = amdgpu_enable_vblank_kms,
2400 .disable_vblank = amdgpu_disable_vblank_kms,
2401 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2402};
2403
2404static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct amdgpu_device *adev = dev->dev_private;
2408 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2409 unsigned type;
2410
2411 switch (mode) {
2412 case DRM_MODE_DPMS_ON:
2413 amdgpu_crtc->enabled = true;
2414 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2415 dce_v8_0_vga_enable(crtc, true);
2416 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2417 dce_v8_0_vga_enable(crtc, false);
2418 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2419 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2420 amdgpu_crtc->crtc_id);
2421 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2422 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2423 drm_crtc_vblank_on(crtc);
2424 dce_v8_0_crtc_load_lut(crtc);
2425 break;
2426 case DRM_MODE_DPMS_STANDBY:
2427 case DRM_MODE_DPMS_SUSPEND:
2428 case DRM_MODE_DPMS_OFF:
2429 drm_crtc_vblank_off(crtc);
2430 if (amdgpu_crtc->enabled) {
2431 dce_v8_0_vga_enable(crtc, true);
2432 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2433 dce_v8_0_vga_enable(crtc, false);
2434 }
2435 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2436 amdgpu_crtc->enabled = false;
2437 break;
2438 }
2439 /* adjust pm to dpms */
2440 amdgpu_pm_compute_clocks(adev);
2441}
2442
2443static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2444{
2445 /* disable crtc pair power gating before programming */
2446 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2447 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2448 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2449}
2450
2451static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2452{
2453 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2454 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2455}
2456
2457static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2458{
2459 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2460 struct drm_device *dev = crtc->dev;
2461 struct amdgpu_device *adev = dev->dev_private;
2462 struct amdgpu_atom_ss ss;
2463 int i;
2464
2465 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2466 if (crtc->primary->fb) {
2467 int r;
2468 struct amdgpu_bo *abo;
2469
2470 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2471 r = amdgpu_bo_reserve(abo, true);
2472 if (unlikely(r))
2473 DRM_ERROR("failed to reserve abo before unpin\n");
2474 else {
2475 amdgpu_bo_unpin(abo);
2476 amdgpu_bo_unreserve(abo);
2477 }
2478 }
2479 /* disable the GRPH */
2480 dce_v8_0_grph_enable(crtc, false);
2481
2482 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2483
2484 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2485 if (adev->mode_info.crtcs[i] &&
2486 adev->mode_info.crtcs[i]->enabled &&
2487 i != amdgpu_crtc->crtc_id &&
2488 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2489 /* one other crtc is using this pll don't turn
2490 * off the pll
2491 */
2492 goto done;
2493 }
2494 }
2495
2496 switch (amdgpu_crtc->pll_id) {
2497 case ATOM_PPLL1:
2498 case ATOM_PPLL2:
2499 /* disable the ppll */
2500 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2501 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2502 break;
2503 case ATOM_PPLL0:
2504 /* disable the ppll */
2505 if ((adev->asic_type == CHIP_KAVERI) ||
2506 (adev->asic_type == CHIP_BONAIRE) ||
2507 (adev->asic_type == CHIP_HAWAII))
2508 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2509 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2510 break;
2511 default:
2512 break;
2513 }
2514done:
2515 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2516 amdgpu_crtc->adjusted_clock = 0;
2517 amdgpu_crtc->encoder = NULL;
2518 amdgpu_crtc->connector = NULL;
2519}
2520
2521static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2522 struct drm_display_mode *mode,
2523 struct drm_display_mode *adjusted_mode,
2524 int x, int y, struct drm_framebuffer *old_fb)
2525{
2526 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2527
2528 if (!amdgpu_crtc->adjusted_clock)
2529 return -EINVAL;
2530
2531 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2532 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2533 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2534 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2535 amdgpu_atombios_crtc_scaler_setup(crtc);
2536 dce_v8_0_cursor_reset(crtc);
2537 /* update the hw version fpr dpm */
2538 amdgpu_crtc->hw_mode = *adjusted_mode;
2539
2540 return 0;
2541}
2542
2543static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2544 const struct drm_display_mode *mode,
2545 struct drm_display_mode *adjusted_mode)
2546{
2547 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2548 struct drm_device *dev = crtc->dev;
2549 struct drm_encoder *encoder;
2550
2551 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2552 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2553 if (encoder->crtc == crtc) {
2554 amdgpu_crtc->encoder = encoder;
2555 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2556 break;
2557 }
2558 }
2559 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2560 amdgpu_crtc->encoder = NULL;
2561 amdgpu_crtc->connector = NULL;
2562 return false;
2563 }
2564 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2565 return false;
2566 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2567 return false;
2568 /* pick pll */
2569 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2570 /* if we can't get a PPLL for a non-DP encoder, fail */
2571 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2572 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2573 return false;
2574
2575 return true;
2576}
2577
2578static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2579 struct drm_framebuffer *old_fb)
2580{
2581 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2582}
2583
2584static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2585 struct drm_framebuffer *fb,
2586 int x, int y, enum mode_set_atomic state)
2587{
2588 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2589}
2590
2591static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2592 .dpms = dce_v8_0_crtc_dpms,
2593 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2594 .mode_set = dce_v8_0_crtc_mode_set,
2595 .mode_set_base = dce_v8_0_crtc_set_base,
2596 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2597 .prepare = dce_v8_0_crtc_prepare,
2598 .commit = dce_v8_0_crtc_commit,
2599 .disable = dce_v8_0_crtc_disable,
2600 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2601};
2602
2603static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2604{
2605 struct amdgpu_crtc *amdgpu_crtc;
2606
2607 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2608 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2609 if (amdgpu_crtc == NULL)
2610 return -ENOMEM;
2611
2612 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2613
2614 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2615 amdgpu_crtc->crtc_id = index;
2616 adev->mode_info.crtcs[index] = amdgpu_crtc;
2617
2618 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2619 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2620 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2621 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2622
2623 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2624
2625 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2626 amdgpu_crtc->adjusted_clock = 0;
2627 amdgpu_crtc->encoder = NULL;
2628 amdgpu_crtc->connector = NULL;
2629 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2630
2631 return 0;
2632}
2633
2634static int dce_v8_0_early_init(void *handle)
2635{
2636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2637
2638 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2639 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2640
2641 dce_v8_0_set_display_funcs(adev);
2642
2643 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2644
2645 switch (adev->asic_type) {
2646 case CHIP_BONAIRE:
2647 case CHIP_HAWAII:
2648 adev->mode_info.num_hpd = 6;
2649 adev->mode_info.num_dig = 6;
2650 break;
2651 case CHIP_KAVERI:
2652 adev->mode_info.num_hpd = 6;
2653 adev->mode_info.num_dig = 7;
2654 break;
2655 case CHIP_KABINI:
2656 case CHIP_MULLINS:
2657 adev->mode_info.num_hpd = 6;
2658 adev->mode_info.num_dig = 6; /* ? */
2659 break;
2660 default:
2661 /* FIXME: not supported yet */
2662 return -EINVAL;
2663 }
2664
2665 dce_v8_0_set_irq_funcs(adev);
2666
2667 return 0;
2668}
2669
2670static int dce_v8_0_sw_init(void *handle)
2671{
2672 int r, i;
2673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2674
2675 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2676 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2677 if (r)
2678 return r;
2679 }
2680
2681 for (i = 8; i < 20; i += 2) {
2682 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2683 if (r)
2684 return r;
2685 }
2686
2687 /* HPD hotplug */
2688 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2689 if (r)
2690 return r;
2691
2692 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2693
2694 adev->ddev->mode_config.async_page_flip = true;
2695
2696 adev->ddev->mode_config.max_width = 16384;
2697 adev->ddev->mode_config.max_height = 16384;
2698
2699 adev->ddev->mode_config.preferred_depth = 24;
2700 adev->ddev->mode_config.prefer_shadow = 1;
2701
2702 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2703
2704 r = amdgpu_display_modeset_create_props(adev);
2705 if (r)
2706 return r;
2707
2708 adev->ddev->mode_config.max_width = 16384;
2709 adev->ddev->mode_config.max_height = 16384;
2710
2711 /* allocate crtcs */
2712 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2713 r = dce_v8_0_crtc_init(adev, i);
2714 if (r)
2715 return r;
2716 }
2717
2718 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2719 amdgpu_display_print_display_setup(adev->ddev);
2720 else
2721 return -EINVAL;
2722
2723 /* setup afmt */
2724 r = dce_v8_0_afmt_init(adev);
2725 if (r)
2726 return r;
2727
2728 r = dce_v8_0_audio_init(adev);
2729 if (r)
2730 return r;
2731
2732 drm_kms_helper_poll_init(adev->ddev);
2733
2734 adev->mode_info.mode_config_initialized = true;
2735 return 0;
2736}
2737
2738static int dce_v8_0_sw_fini(void *handle)
2739{
2740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2741
2742 kfree(adev->mode_info.bios_hardcoded_edid);
2743
2744 drm_kms_helper_poll_fini(adev->ddev);
2745
2746 dce_v8_0_audio_fini(adev);
2747
2748 dce_v8_0_afmt_fini(adev);
2749
2750 drm_mode_config_cleanup(adev->ddev);
2751 adev->mode_info.mode_config_initialized = false;
2752
2753 return 0;
2754}
2755
2756static int dce_v8_0_hw_init(void *handle)
2757{
2758 int i;
2759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2760
2761 /* disable vga render */
2762 dce_v8_0_set_vga_render_state(adev, false);
2763 /* init dig PHYs, disp eng pll */
2764 amdgpu_atombios_encoder_init_dig(adev);
2765 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2766
2767 /* initialize hpd */
2768 dce_v8_0_hpd_init(adev);
2769
2770 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2771 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2772 }
2773
2774 dce_v8_0_pageflip_interrupt_init(adev);
2775
2776 return 0;
2777}
2778
2779static int dce_v8_0_hw_fini(void *handle)
2780{
2781 int i;
2782 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2783
2784 dce_v8_0_hpd_fini(adev);
2785
2786 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2787 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2788 }
2789
2790 dce_v8_0_pageflip_interrupt_fini(adev);
2791
2792 return 0;
2793}
2794
2795static int dce_v8_0_suspend(void *handle)
2796{
2797 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2798
2799 adev->mode_info.bl_level =
2800 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2801
2802 return dce_v8_0_hw_fini(handle);
2803}
2804
2805static int dce_v8_0_resume(void *handle)
2806{
2807 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2808 int ret;
2809
2810 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2811 adev->mode_info.bl_level);
2812
2813 ret = dce_v8_0_hw_init(handle);
2814
2815 /* turn on the BL */
2816 if (adev->mode_info.bl_encoder) {
2817 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2818 adev->mode_info.bl_encoder);
2819 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2820 bl_level);
2821 }
2822
2823 return ret;
2824}
2825
2826static bool dce_v8_0_is_idle(void *handle)
2827{
2828 return true;
2829}
2830
2831static int dce_v8_0_wait_for_idle(void *handle)
2832{
2833 return 0;
2834}
2835
2836static int dce_v8_0_soft_reset(void *handle)
2837{
2838 u32 srbm_soft_reset = 0, tmp;
2839 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2840
2841 if (dce_v8_0_is_display_hung(adev))
2842 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2843
2844 if (srbm_soft_reset) {
2845 tmp = RREG32(mmSRBM_SOFT_RESET);
2846 tmp |= srbm_soft_reset;
2847 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2848 WREG32(mmSRBM_SOFT_RESET, tmp);
2849 tmp = RREG32(mmSRBM_SOFT_RESET);
2850
2851 udelay(50);
2852
2853 tmp &= ~srbm_soft_reset;
2854 WREG32(mmSRBM_SOFT_RESET, tmp);
2855 tmp = RREG32(mmSRBM_SOFT_RESET);
2856
2857 /* Wait a little for things to settle down */
2858 udelay(50);
2859 }
2860 return 0;
2861}
2862
2863static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2864 int crtc,
2865 enum amdgpu_interrupt_state state)
2866{
2867 u32 reg_block, lb_interrupt_mask;
2868
2869 if (crtc >= adev->mode_info.num_crtc) {
2870 DRM_DEBUG("invalid crtc %d\n", crtc);
2871 return;
2872 }
2873
2874 switch (crtc) {
2875 case 0:
2876 reg_block = CRTC0_REGISTER_OFFSET;
2877 break;
2878 case 1:
2879 reg_block = CRTC1_REGISTER_OFFSET;
2880 break;
2881 case 2:
2882 reg_block = CRTC2_REGISTER_OFFSET;
2883 break;
2884 case 3:
2885 reg_block = CRTC3_REGISTER_OFFSET;
2886 break;
2887 case 4:
2888 reg_block = CRTC4_REGISTER_OFFSET;
2889 break;
2890 case 5:
2891 reg_block = CRTC5_REGISTER_OFFSET;
2892 break;
2893 default:
2894 DRM_DEBUG("invalid crtc %d\n", crtc);
2895 return;
2896 }
2897
2898 switch (state) {
2899 case AMDGPU_IRQ_STATE_DISABLE:
2900 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2901 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2902 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2903 break;
2904 case AMDGPU_IRQ_STATE_ENABLE:
2905 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2906 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2907 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2908 break;
2909 default:
2910 break;
2911 }
2912}
2913
2914static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2915 int crtc,
2916 enum amdgpu_interrupt_state state)
2917{
2918 u32 reg_block, lb_interrupt_mask;
2919
2920 if (crtc >= adev->mode_info.num_crtc) {
2921 DRM_DEBUG("invalid crtc %d\n", crtc);
2922 return;
2923 }
2924
2925 switch (crtc) {
2926 case 0:
2927 reg_block = CRTC0_REGISTER_OFFSET;
2928 break;
2929 case 1:
2930 reg_block = CRTC1_REGISTER_OFFSET;
2931 break;
2932 case 2:
2933 reg_block = CRTC2_REGISTER_OFFSET;
2934 break;
2935 case 3:
2936 reg_block = CRTC3_REGISTER_OFFSET;
2937 break;
2938 case 4:
2939 reg_block = CRTC4_REGISTER_OFFSET;
2940 break;
2941 case 5:
2942 reg_block = CRTC5_REGISTER_OFFSET;
2943 break;
2944 default:
2945 DRM_DEBUG("invalid crtc %d\n", crtc);
2946 return;
2947 }
2948
2949 switch (state) {
2950 case AMDGPU_IRQ_STATE_DISABLE:
2951 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2952 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2953 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2954 break;
2955 case AMDGPU_IRQ_STATE_ENABLE:
2956 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2957 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2958 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2959 break;
2960 default:
2961 break;
2962 }
2963}
2964
2965static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2966 struct amdgpu_irq_src *src,
2967 unsigned type,
2968 enum amdgpu_interrupt_state state)
2969{
2970 u32 dc_hpd_int_cntl;
2971
2972 if (type >= adev->mode_info.num_hpd) {
2973 DRM_DEBUG("invalid hdp %d\n", type);
2974 return 0;
2975 }
2976
2977 switch (state) {
2978 case AMDGPU_IRQ_STATE_DISABLE:
2979 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2980 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2981 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2982 break;
2983 case AMDGPU_IRQ_STATE_ENABLE:
2984 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2985 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2986 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2987 break;
2988 default:
2989 break;
2990 }
2991
2992 return 0;
2993}
2994
2995static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2996 struct amdgpu_irq_src *src,
2997 unsigned type,
2998 enum amdgpu_interrupt_state state)
2999{
3000 switch (type) {
3001 case AMDGPU_CRTC_IRQ_VBLANK1:
3002 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3003 break;
3004 case AMDGPU_CRTC_IRQ_VBLANK2:
3005 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3006 break;
3007 case AMDGPU_CRTC_IRQ_VBLANK3:
3008 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3009 break;
3010 case AMDGPU_CRTC_IRQ_VBLANK4:
3011 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3012 break;
3013 case AMDGPU_CRTC_IRQ_VBLANK5:
3014 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3015 break;
3016 case AMDGPU_CRTC_IRQ_VBLANK6:
3017 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3018 break;
3019 case AMDGPU_CRTC_IRQ_VLINE1:
3020 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3021 break;
3022 case AMDGPU_CRTC_IRQ_VLINE2:
3023 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3024 break;
3025 case AMDGPU_CRTC_IRQ_VLINE3:
3026 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3027 break;
3028 case AMDGPU_CRTC_IRQ_VLINE4:
3029 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3030 break;
3031 case AMDGPU_CRTC_IRQ_VLINE5:
3032 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3033 break;
3034 case AMDGPU_CRTC_IRQ_VLINE6:
3035 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3036 break;
3037 default:
3038 break;
3039 }
3040 return 0;
3041}
3042
3043static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3044 struct amdgpu_irq_src *source,
3045 struct amdgpu_iv_entry *entry)
3046{
3047 unsigned crtc = entry->src_id - 1;
3048 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3049 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3050 crtc);
3051
3052 switch (entry->src_data[0]) {
3053 case 0: /* vblank */
3054 if (disp_int & interrupt_status_offsets[crtc].vblank)
3055 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3056 else
3057 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3058
3059 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3060 drm_handle_vblank(adev->ddev, crtc);
3061 }
3062 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3063 break;
3064 case 1: /* vline */
3065 if (disp_int & interrupt_status_offsets[crtc].vline)
3066 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3067 else
3068 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3069
3070 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3071 break;
3072 default:
3073 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3074 break;
3075 }
3076
3077 return 0;
3078}
3079
3080static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3081 struct amdgpu_irq_src *src,
3082 unsigned type,
3083 enum amdgpu_interrupt_state state)
3084{
3085 u32 reg;
3086
3087 if (type >= adev->mode_info.num_crtc) {
3088 DRM_ERROR("invalid pageflip crtc %d\n", type);
3089 return -EINVAL;
3090 }
3091
3092 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3093 if (state == AMDGPU_IRQ_STATE_DISABLE)
3094 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3095 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3096 else
3097 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3098 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3099
3100 return 0;
3101}
3102
3103static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3104 struct amdgpu_irq_src *source,
3105 struct amdgpu_iv_entry *entry)
3106{
3107 unsigned long flags;
3108 unsigned crtc_id;
3109 struct amdgpu_crtc *amdgpu_crtc;
3110 struct amdgpu_flip_work *works;
3111
3112 crtc_id = (entry->src_id - 8) >> 1;
3113 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3114
3115 if (crtc_id >= adev->mode_info.num_crtc) {
3116 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3117 return -EINVAL;
3118 }
3119
3120 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3121 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3122 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3123 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3124
3125 /* IRQ could occur when in initial stage */
3126 if (amdgpu_crtc == NULL)
3127 return 0;
3128
3129 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3130 works = amdgpu_crtc->pflip_works;
3131 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3132 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3133 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3134 amdgpu_crtc->pflip_status,
3135 AMDGPU_FLIP_SUBMITTED);
3136 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3137 return 0;
3138 }
3139
3140 /* page flip completed. clean up */
3141 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3142 amdgpu_crtc->pflip_works = NULL;
3143
3144 /* wakeup usersapce */
3145 if (works->event)
3146 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3147
3148 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3149
3150 drm_crtc_vblank_put(&amdgpu_crtc->base);
3151 schedule_work(&works->unpin_work);
3152
3153 return 0;
3154}
3155
3156static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3157 struct amdgpu_irq_src *source,
3158 struct amdgpu_iv_entry *entry)
3159{
3160 uint32_t disp_int, mask, tmp;
3161 unsigned hpd;
3162
3163 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3164 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3165 return 0;
3166 }
3167
3168 hpd = entry->src_data[0];
3169 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3170 mask = interrupt_status_offsets[hpd].hpd;
3171
3172 if (disp_int & mask) {
3173 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3174 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3175 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3176 schedule_work(&adev->hotplug_work);
3177 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3178 }
3179
3180 return 0;
3181
3182}
3183
3184static int dce_v8_0_set_clockgating_state(void *handle,
3185 enum amd_clockgating_state state)
3186{
3187 return 0;
3188}
3189
3190static int dce_v8_0_set_powergating_state(void *handle,
3191 enum amd_powergating_state state)
3192{
3193 return 0;
3194}
3195
3196static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3197 .name = "dce_v8_0",
3198 .early_init = dce_v8_0_early_init,
3199 .late_init = NULL,
3200 .sw_init = dce_v8_0_sw_init,
3201 .sw_fini = dce_v8_0_sw_fini,
3202 .hw_init = dce_v8_0_hw_init,
3203 .hw_fini = dce_v8_0_hw_fini,
3204 .suspend = dce_v8_0_suspend,
3205 .resume = dce_v8_0_resume,
3206 .is_idle = dce_v8_0_is_idle,
3207 .wait_for_idle = dce_v8_0_wait_for_idle,
3208 .soft_reset = dce_v8_0_soft_reset,
3209 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3210 .set_powergating_state = dce_v8_0_set_powergating_state,
3211};
3212
3213static void
3214dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3215 struct drm_display_mode *mode,
3216 struct drm_display_mode *adjusted_mode)
3217{
3218 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3219
3220 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3221
3222 /* need to call this here rather than in prepare() since we need some crtc info */
3223 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3224
3225 /* set scaler clears this on some chips */
3226 dce_v8_0_set_interleave(encoder->crtc, mode);
3227
3228 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3229 dce_v8_0_afmt_enable(encoder, true);
3230 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3231 }
3232}
3233
3234static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3235{
3236 struct amdgpu_device *adev = encoder->dev->dev_private;
3237 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3238 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3239
3240 if ((amdgpu_encoder->active_device &
3241 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3242 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3243 ENCODER_OBJECT_ID_NONE)) {
3244 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3245 if (dig) {
3246 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3247 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3248 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3249 }
3250 }
3251
3252 amdgpu_atombios_scratch_regs_lock(adev, true);
3253
3254 if (connector) {
3255 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3256
3257 /* select the clock/data port if it uses a router */
3258 if (amdgpu_connector->router.cd_valid)
3259 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3260
3261 /* turn eDP panel on for mode set */
3262 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3263 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3264 ATOM_TRANSMITTER_ACTION_POWER_ON);
3265 }
3266
3267 /* this is needed for the pll/ss setup to work correctly in some cases */
3268 amdgpu_atombios_encoder_set_crtc_source(encoder);
3269 /* set up the FMT blocks */
3270 dce_v8_0_program_fmt(encoder);
3271}
3272
3273static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3274{
3275 struct drm_device *dev = encoder->dev;
3276 struct amdgpu_device *adev = dev->dev_private;
3277
3278 /* need to call this here as we need the crtc set up */
3279 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3280 amdgpu_atombios_scratch_regs_lock(adev, false);
3281}
3282
3283static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3284{
3285 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3286 struct amdgpu_encoder_atom_dig *dig;
3287
3288 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3289
3290 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3291 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3292 dce_v8_0_afmt_enable(encoder, false);
3293 dig = amdgpu_encoder->enc_priv;
3294 dig->dig_encoder = -1;
3295 }
3296 amdgpu_encoder->active_device = 0;
3297}
3298
3299/* these are handled by the primary encoders */
3300static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3301{
3302
3303}
3304
3305static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3306{
3307
3308}
3309
3310static void
3311dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3312 struct drm_display_mode *mode,
3313 struct drm_display_mode *adjusted_mode)
3314{
3315
3316}
3317
3318static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3319{
3320
3321}
3322
3323static void
3324dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3325{
3326
3327}
3328
3329static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3330 .dpms = dce_v8_0_ext_dpms,
3331 .prepare = dce_v8_0_ext_prepare,
3332 .mode_set = dce_v8_0_ext_mode_set,
3333 .commit = dce_v8_0_ext_commit,
3334 .disable = dce_v8_0_ext_disable,
3335 /* no detect for TMDS/LVDS yet */
3336};
3337
3338static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3339 .dpms = amdgpu_atombios_encoder_dpms,
3340 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3341 .prepare = dce_v8_0_encoder_prepare,
3342 .mode_set = dce_v8_0_encoder_mode_set,
3343 .commit = dce_v8_0_encoder_commit,
3344 .disable = dce_v8_0_encoder_disable,
3345 .detect = amdgpu_atombios_encoder_dig_detect,
3346};
3347
3348static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3349 .dpms = amdgpu_atombios_encoder_dpms,
3350 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3351 .prepare = dce_v8_0_encoder_prepare,
3352 .mode_set = dce_v8_0_encoder_mode_set,
3353 .commit = dce_v8_0_encoder_commit,
3354 .detect = amdgpu_atombios_encoder_dac_detect,
3355};
3356
3357static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3358{
3359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3360 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3361 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3362 kfree(amdgpu_encoder->enc_priv);
3363 drm_encoder_cleanup(encoder);
3364 kfree(amdgpu_encoder);
3365}
3366
3367static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3368 .destroy = dce_v8_0_encoder_destroy,
3369};
3370
3371static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3372 uint32_t encoder_enum,
3373 uint32_t supported_device,
3374 u16 caps)
3375{
3376 struct drm_device *dev = adev->ddev;
3377 struct drm_encoder *encoder;
3378 struct amdgpu_encoder *amdgpu_encoder;
3379
3380 /* see if we already added it */
3381 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3382 amdgpu_encoder = to_amdgpu_encoder(encoder);
3383 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3384 amdgpu_encoder->devices |= supported_device;
3385 return;
3386 }
3387
3388 }
3389
3390 /* add a new one */
3391 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3392 if (!amdgpu_encoder)
3393 return;
3394
3395 encoder = &amdgpu_encoder->base;
3396 switch (adev->mode_info.num_crtc) {
3397 case 1:
3398 encoder->possible_crtcs = 0x1;
3399 break;
3400 case 2:
3401 default:
3402 encoder->possible_crtcs = 0x3;
3403 break;
3404 case 4:
3405 encoder->possible_crtcs = 0xf;
3406 break;
3407 case 6:
3408 encoder->possible_crtcs = 0x3f;
3409 break;
3410 }
3411
3412 amdgpu_encoder->enc_priv = NULL;
3413
3414 amdgpu_encoder->encoder_enum = encoder_enum;
3415 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3416 amdgpu_encoder->devices = supported_device;
3417 amdgpu_encoder->rmx_type = RMX_OFF;
3418 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3419 amdgpu_encoder->is_ext_encoder = false;
3420 amdgpu_encoder->caps = caps;
3421
3422 switch (amdgpu_encoder->encoder_id) {
3423 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3424 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3425 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3426 DRM_MODE_ENCODER_DAC, NULL);
3427 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3428 break;
3429 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3430 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3431 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3432 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3433 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3434 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3435 amdgpu_encoder->rmx_type = RMX_FULL;
3436 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3437 DRM_MODE_ENCODER_LVDS, NULL);
3438 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3439 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3440 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3441 DRM_MODE_ENCODER_DAC, NULL);
3442 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3443 } else {
3444 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3445 DRM_MODE_ENCODER_TMDS, NULL);
3446 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3447 }
3448 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3449 break;
3450 case ENCODER_OBJECT_ID_SI170B:
3451 case ENCODER_OBJECT_ID_CH7303:
3452 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3453 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3454 case ENCODER_OBJECT_ID_TITFP513:
3455 case ENCODER_OBJECT_ID_VT1623:
3456 case ENCODER_OBJECT_ID_HDMI_SI1930:
3457 case ENCODER_OBJECT_ID_TRAVIS:
3458 case ENCODER_OBJECT_ID_NUTMEG:
3459 /* these are handled by the primary encoders */
3460 amdgpu_encoder->is_ext_encoder = true;
3461 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3462 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3463 DRM_MODE_ENCODER_LVDS, NULL);
3464 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3465 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3466 DRM_MODE_ENCODER_DAC, NULL);
3467 else
3468 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3469 DRM_MODE_ENCODER_TMDS, NULL);
3470 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3471 break;
3472 }
3473}
3474
3475static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3476 .bandwidth_update = &dce_v8_0_bandwidth_update,
3477 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3478 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3479 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3480 .hpd_sense = &dce_v8_0_hpd_sense,
3481 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3482 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3483 .page_flip = &dce_v8_0_page_flip,
3484 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3485 .add_encoder = &dce_v8_0_encoder_add,
3486 .add_connector = &amdgpu_connector_add,
3487};
3488
3489static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3490{
3491 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3492}
3493
3494static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3495 .set = dce_v8_0_set_crtc_interrupt_state,
3496 .process = dce_v8_0_crtc_irq,
3497};
3498
3499static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3500 .set = dce_v8_0_set_pageflip_interrupt_state,
3501 .process = dce_v8_0_pageflip_irq,
3502};
3503
3504static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3505 .set = dce_v8_0_set_hpd_interrupt_state,
3506 .process = dce_v8_0_hpd_irq,
3507};
3508
3509static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3510{
3511 if (adev->mode_info.num_crtc > 0)
3512 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3513 else
3514 adev->crtc_irq.num_types = 0;
3515 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3516
3517 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3518 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3519
3520 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3521 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3522}
3523
3524const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3525{
3526 .type = AMD_IP_BLOCK_TYPE_DCE,
3527 .major = 8,
3528 .minor = 0,
3529 .rev = 0,
3530 .funcs = &dce_v8_0_ip_funcs,
3531};
3532
3533const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3534{
3535 .type = AMD_IP_BLOCK_TYPE_DCE,
3536 .major = 8,
3537 .minor = 1,
3538 .rev = 0,
3539 .funcs = &dce_v8_0_ip_funcs,
3540};
3541
3542const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3543{
3544 .type = AMD_IP_BLOCK_TYPE_DCE,
3545 .major = 8,
3546 .minor = 2,
3547 .rev = 0,
3548 .funcs = &dce_v8_0_ip_funcs,
3549};
3550
3551const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3552{
3553 .type = AMD_IP_BLOCK_TYPE_DCE,
3554 .major = 8,
3555 .minor = 3,
3556 .rev = 0,
3557 .funcs = &dce_v8_0_ip_funcs,
3558};
3559
3560const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3561{
3562 .type = AMD_IP_BLOCK_TYPE_DCE,
3563 .major = 8,
3564 .minor = 5,
3565 .rev = 0,
3566 .funcs = &dce_v8_0_ip_funcs,
3567};