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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
4 */
5
6#include <linux/module.h>
7#include <linux/siox.h>
8#include <linux/gpio/driver.h>
9#include <linux/of.h>
10
11struct gpio_siox_ddata {
12 struct gpio_chip gchip;
13 struct mutex lock;
14 u8 setdata[1];
15 u8 getdata[3];
16
17 raw_spinlock_t irqlock;
18 u32 irq_enable;
19 u32 irq_status;
20 u32 irq_type[20];
21};
22
23/*
24 * Note that this callback only sets the value that is clocked out in the next
25 * cycle.
26 */
27static int gpio_siox_set_data(struct siox_device *sdevice, u8 status, u8 buf[])
28{
29 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
30
31 mutex_lock(&ddata->lock);
32 buf[0] = ddata->setdata[0];
33 mutex_unlock(&ddata->lock);
34
35 return 0;
36}
37
38static int gpio_siox_get_data(struct siox_device *sdevice, const u8 buf[])
39{
40 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
41 size_t offset;
42 u32 trigger;
43
44 mutex_lock(&ddata->lock);
45
46 raw_spin_lock_irq(&ddata->irqlock);
47
48 for (offset = 0; offset < 12; ++offset) {
49 unsigned int bitpos = 11 - offset;
50 unsigned int gpiolevel = buf[bitpos / 8] & (1 << bitpos % 8);
51 unsigned int prev_level =
52 ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
53 u32 irq_type = ddata->irq_type[offset];
54
55 if (gpiolevel) {
56 if ((irq_type & IRQ_TYPE_LEVEL_HIGH) ||
57 ((irq_type & IRQ_TYPE_EDGE_RISING) && !prev_level))
58 ddata->irq_status |= 1 << offset;
59 } else {
60 if ((irq_type & IRQ_TYPE_LEVEL_LOW) ||
61 ((irq_type & IRQ_TYPE_EDGE_FALLING) && prev_level))
62 ddata->irq_status |= 1 << offset;
63 }
64 }
65
66 trigger = ddata->irq_status & ddata->irq_enable;
67
68 raw_spin_unlock_irq(&ddata->irqlock);
69
70 ddata->getdata[0] = buf[0];
71 ddata->getdata[1] = buf[1];
72 ddata->getdata[2] = buf[2];
73
74 mutex_unlock(&ddata->lock);
75
76 for (offset = 0; offset < 12; ++offset) {
77 if (trigger & (1 << offset)) {
78 struct irq_domain *irqdomain = ddata->gchip.irq.domain;
79 unsigned int irq = irq_find_mapping(irqdomain, offset);
80
81 /*
82 * Conceptually handle_nested_irq should call the flow
83 * handler of the irq chip. But it doesn't, so we have
84 * to clean the irq_status here.
85 */
86 raw_spin_lock_irq(&ddata->irqlock);
87 ddata->irq_status &= ~(1 << offset);
88 raw_spin_unlock_irq(&ddata->irqlock);
89
90 handle_nested_irq(irq);
91 }
92 }
93
94 return 0;
95}
96
97static void gpio_siox_irq_ack(struct irq_data *d)
98{
99 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
100 struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
101
102 raw_spin_lock(&ddata->irqlock);
103 ddata->irq_status &= ~(1 << d->hwirq);
104 raw_spin_unlock(&ddata->irqlock);
105}
106
107static void gpio_siox_irq_mask(struct irq_data *d)
108{
109 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
110 struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
111
112 raw_spin_lock(&ddata->irqlock);
113 ddata->irq_enable &= ~(1 << d->hwirq);
114 raw_spin_unlock(&ddata->irqlock);
115 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
116}
117
118static void gpio_siox_irq_unmask(struct irq_data *d)
119{
120 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
121 struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
122
123 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
124 raw_spin_lock(&ddata->irqlock);
125 ddata->irq_enable |= 1 << d->hwirq;
126 raw_spin_unlock(&ddata->irqlock);
127}
128
129static int gpio_siox_irq_set_type(struct irq_data *d, u32 type)
130{
131 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
132 struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
133
134 raw_spin_lock(&ddata->irqlock);
135 ddata->irq_type[d->hwirq] = type;
136 raw_spin_unlock(&ddata->irqlock);
137
138 return 0;
139}
140
141static int gpio_siox_get(struct gpio_chip *chip, unsigned int offset)
142{
143 struct gpio_siox_ddata *ddata = gpiochip_get_data(chip);
144 int ret;
145
146 mutex_lock(&ddata->lock);
147
148 if (offset >= 12) {
149 unsigned int bitpos = 19 - offset;
150
151 ret = ddata->setdata[0] & (1 << bitpos);
152 } else {
153 unsigned int bitpos = 11 - offset;
154
155 ret = ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
156 }
157
158 mutex_unlock(&ddata->lock);
159
160 return ret;
161}
162
163static void gpio_siox_set(struct gpio_chip *chip,
164 unsigned int offset, int value)
165{
166 struct gpio_siox_ddata *ddata = gpiochip_get_data(chip);
167 u8 mask = 1 << (19 - offset);
168
169 mutex_lock(&ddata->lock);
170
171 if (value)
172 ddata->setdata[0] |= mask;
173 else
174 ddata->setdata[0] &= ~mask;
175
176 mutex_unlock(&ddata->lock);
177}
178
179static int gpio_siox_direction_input(struct gpio_chip *chip,
180 unsigned int offset)
181{
182 if (offset >= 12)
183 return -EINVAL;
184
185 return 0;
186}
187
188static int gpio_siox_direction_output(struct gpio_chip *chip,
189 unsigned int offset, int value)
190{
191 if (offset < 12)
192 return -EINVAL;
193
194 gpio_siox_set(chip, offset, value);
195 return 0;
196}
197
198static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset)
199{
200 if (offset < 12)
201 return GPIO_LINE_DIRECTION_IN;
202 else
203 return GPIO_LINE_DIRECTION_OUT;
204}
205
206static const struct irq_chip gpio_siox_irq_chip = {
207 .name = "siox-gpio",
208 .irq_ack = gpio_siox_irq_ack,
209 .irq_mask = gpio_siox_irq_mask,
210 .irq_unmask = gpio_siox_irq_unmask,
211 .irq_set_type = gpio_siox_irq_set_type,
212 .flags = IRQCHIP_IMMUTABLE,
213 GPIOCHIP_IRQ_RESOURCE_HELPERS,
214};
215
216static int gpio_siox_probe(struct siox_device *sdevice)
217{
218 struct gpio_siox_ddata *ddata;
219 struct gpio_irq_chip *girq;
220 struct device *dev = &sdevice->dev;
221 struct gpio_chip *gc;
222 int ret;
223
224 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
225 if (!ddata)
226 return -ENOMEM;
227
228 dev_set_drvdata(dev, ddata);
229
230 mutex_init(&ddata->lock);
231 raw_spin_lock_init(&ddata->irqlock);
232
233 gc = &ddata->gchip;
234 gc->base = -1;
235 gc->can_sleep = 1;
236 gc->parent = dev;
237 gc->owner = THIS_MODULE;
238 gc->get = gpio_siox_get;
239 gc->set = gpio_siox_set;
240 gc->direction_input = gpio_siox_direction_input;
241 gc->direction_output = gpio_siox_direction_output;
242 gc->get_direction = gpio_siox_get_direction;
243 gc->ngpio = 20;
244
245 girq = &gc->irq;
246 gpio_irq_chip_set_chip(girq, &gpio_siox_irq_chip);
247 girq->default_type = IRQ_TYPE_NONE;
248 girq->handler = handle_level_irq;
249 girq->threaded = true;
250
251 ret = devm_gpiochip_add_data(dev, gc, ddata);
252 if (ret)
253 dev_err(dev, "Failed to register gpio chip (%d)\n", ret);
254
255 return ret;
256}
257
258static struct siox_driver gpio_siox_driver = {
259 .probe = gpio_siox_probe,
260 .set_data = gpio_siox_set_data,
261 .get_data = gpio_siox_get_data,
262 .driver = {
263 .name = "gpio-siox",
264 },
265};
266module_siox_driver(gpio_siox_driver);
267
268MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
269MODULE_DESCRIPTION("SIOX gpio driver");
270MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
4 */
5
6#include <linux/module.h>
7#include <linux/siox.h>
8#include <linux/gpio/driver.h>
9#include <linux/of.h>
10
11struct gpio_siox_ddata {
12 struct gpio_chip gchip;
13 struct irq_chip ichip;
14 struct mutex lock;
15 u8 setdata[1];
16 u8 getdata[3];
17
18 raw_spinlock_t irqlock;
19 u32 irq_enable;
20 u32 irq_status;
21 u32 irq_type[20];
22};
23
24/*
25 * Note that this callback only sets the value that is clocked out in the next
26 * cycle.
27 */
28static int gpio_siox_set_data(struct siox_device *sdevice, u8 status, u8 buf[])
29{
30 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
31
32 mutex_lock(&ddata->lock);
33 buf[0] = ddata->setdata[0];
34 mutex_unlock(&ddata->lock);
35
36 return 0;
37}
38
39static int gpio_siox_get_data(struct siox_device *sdevice, const u8 buf[])
40{
41 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
42 size_t offset;
43 u32 trigger;
44
45 mutex_lock(&ddata->lock);
46
47 raw_spin_lock_irq(&ddata->irqlock);
48
49 for (offset = 0; offset < 12; ++offset) {
50 unsigned int bitpos = 11 - offset;
51 unsigned int gpiolevel = buf[bitpos / 8] & (1 << bitpos % 8);
52 unsigned int prev_level =
53 ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
54 u32 irq_type = ddata->irq_type[offset];
55
56 if (gpiolevel) {
57 if ((irq_type & IRQ_TYPE_LEVEL_HIGH) ||
58 ((irq_type & IRQ_TYPE_EDGE_RISING) && !prev_level))
59 ddata->irq_status |= 1 << offset;
60 } else {
61 if ((irq_type & IRQ_TYPE_LEVEL_LOW) ||
62 ((irq_type & IRQ_TYPE_EDGE_FALLING) && prev_level))
63 ddata->irq_status |= 1 << offset;
64 }
65 }
66
67 trigger = ddata->irq_status & ddata->irq_enable;
68
69 raw_spin_unlock_irq(&ddata->irqlock);
70
71 ddata->getdata[0] = buf[0];
72 ddata->getdata[1] = buf[1];
73 ddata->getdata[2] = buf[2];
74
75 mutex_unlock(&ddata->lock);
76
77 for (offset = 0; offset < 12; ++offset) {
78 if (trigger & (1 << offset)) {
79 struct irq_domain *irqdomain = ddata->gchip.irq.domain;
80 unsigned int irq = irq_find_mapping(irqdomain, offset);
81
82 /*
83 * Conceptually handle_nested_irq should call the flow
84 * handler of the irq chip. But it doesn't, so we have
85 * to clean the irq_status here.
86 */
87 raw_spin_lock_irq(&ddata->irqlock);
88 ddata->irq_status &= ~(1 << offset);
89 raw_spin_unlock_irq(&ddata->irqlock);
90
91 handle_nested_irq(irq);
92 }
93 }
94
95 return 0;
96}
97
98static void gpio_siox_irq_ack(struct irq_data *d)
99{
100 struct irq_chip *ic = irq_data_get_irq_chip(d);
101 struct gpio_siox_ddata *ddata =
102 container_of(ic, struct gpio_siox_ddata, ichip);
103
104 raw_spin_lock(&ddata->irqlock);
105 ddata->irq_status &= ~(1 << d->hwirq);
106 raw_spin_unlock(&ddata->irqlock);
107}
108
109static void gpio_siox_irq_mask(struct irq_data *d)
110{
111 struct irq_chip *ic = irq_data_get_irq_chip(d);
112 struct gpio_siox_ddata *ddata =
113 container_of(ic, struct gpio_siox_ddata, ichip);
114
115 raw_spin_lock(&ddata->irqlock);
116 ddata->irq_enable &= ~(1 << d->hwirq);
117 raw_spin_unlock(&ddata->irqlock);
118}
119
120static void gpio_siox_irq_unmask(struct irq_data *d)
121{
122 struct irq_chip *ic = irq_data_get_irq_chip(d);
123 struct gpio_siox_ddata *ddata =
124 container_of(ic, struct gpio_siox_ddata, ichip);
125
126 raw_spin_lock(&ddata->irqlock);
127 ddata->irq_enable |= 1 << d->hwirq;
128 raw_spin_unlock(&ddata->irqlock);
129}
130
131static int gpio_siox_irq_set_type(struct irq_data *d, u32 type)
132{
133 struct irq_chip *ic = irq_data_get_irq_chip(d);
134 struct gpio_siox_ddata *ddata =
135 container_of(ic, struct gpio_siox_ddata, ichip);
136
137 raw_spin_lock(&ddata->irqlock);
138 ddata->irq_type[d->hwirq] = type;
139 raw_spin_unlock(&ddata->irqlock);
140
141 return 0;
142}
143
144static int gpio_siox_get(struct gpio_chip *chip, unsigned int offset)
145{
146 struct gpio_siox_ddata *ddata =
147 container_of(chip, struct gpio_siox_ddata, gchip);
148 int ret;
149
150 mutex_lock(&ddata->lock);
151
152 if (offset >= 12) {
153 unsigned int bitpos = 19 - offset;
154
155 ret = ddata->setdata[0] & (1 << bitpos);
156 } else {
157 unsigned int bitpos = 11 - offset;
158
159 ret = ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
160 }
161
162 mutex_unlock(&ddata->lock);
163
164 return ret;
165}
166
167static void gpio_siox_set(struct gpio_chip *chip,
168 unsigned int offset, int value)
169{
170 struct gpio_siox_ddata *ddata =
171 container_of(chip, struct gpio_siox_ddata, gchip);
172 u8 mask = 1 << (19 - offset);
173
174 mutex_lock(&ddata->lock);
175
176 if (value)
177 ddata->setdata[0] |= mask;
178 else
179 ddata->setdata[0] &= ~mask;
180
181 mutex_unlock(&ddata->lock);
182}
183
184static int gpio_siox_direction_input(struct gpio_chip *chip,
185 unsigned int offset)
186{
187 if (offset >= 12)
188 return -EINVAL;
189
190 return 0;
191}
192
193static int gpio_siox_direction_output(struct gpio_chip *chip,
194 unsigned int offset, int value)
195{
196 if (offset < 12)
197 return -EINVAL;
198
199 gpio_siox_set(chip, offset, value);
200 return 0;
201}
202
203static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset)
204{
205 if (offset < 12)
206 return GPIO_LINE_DIRECTION_IN;
207 else
208 return GPIO_LINE_DIRECTION_OUT;
209}
210
211static int gpio_siox_probe(struct siox_device *sdevice)
212{
213 struct gpio_siox_ddata *ddata;
214 struct gpio_irq_chip *girq;
215 struct device *dev = &sdevice->dev;
216 int ret;
217
218 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
219 if (!ddata)
220 return -ENOMEM;
221
222 dev_set_drvdata(dev, ddata);
223
224 mutex_init(&ddata->lock);
225 raw_spin_lock_init(&ddata->irqlock);
226
227 ddata->gchip.base = -1;
228 ddata->gchip.can_sleep = 1;
229 ddata->gchip.parent = dev;
230 ddata->gchip.owner = THIS_MODULE;
231 ddata->gchip.get = gpio_siox_get;
232 ddata->gchip.set = gpio_siox_set;
233 ddata->gchip.direction_input = gpio_siox_direction_input;
234 ddata->gchip.direction_output = gpio_siox_direction_output;
235 ddata->gchip.get_direction = gpio_siox_get_direction;
236 ddata->gchip.ngpio = 20;
237
238 ddata->ichip.name = "siox-gpio";
239 ddata->ichip.irq_ack = gpio_siox_irq_ack;
240 ddata->ichip.irq_mask = gpio_siox_irq_mask;
241 ddata->ichip.irq_unmask = gpio_siox_irq_unmask;
242 ddata->ichip.irq_set_type = gpio_siox_irq_set_type;
243
244 girq = &ddata->gchip.irq;
245 girq->chip = &ddata->ichip;
246 girq->default_type = IRQ_TYPE_NONE;
247 girq->handler = handle_level_irq;
248 girq->threaded = true;
249
250 ret = devm_gpiochip_add_data(dev, &ddata->gchip, NULL);
251 if (ret)
252 dev_err(dev, "Failed to register gpio chip (%d)\n", ret);
253
254 return ret;
255}
256
257static struct siox_driver gpio_siox_driver = {
258 .probe = gpio_siox_probe,
259 .set_data = gpio_siox_set_data,
260 .get_data = gpio_siox_get_data,
261 .driver = {
262 .name = "gpio-siox",
263 },
264};
265module_siox_driver(gpio_siox_driver);
266
267MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
268MODULE_DESCRIPTION("SIOX gpio driver");
269MODULE_LICENSE("GPL v2");