1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (c) 2014 MediaTek Inc.
 4 * Author: Shunli Wang <shunli.wang@mediatek.com>
 5 */
 6
 7#include <linux/clk-provider.h>
 8#include <linux/platform_device.h>
 9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt2701-clk.h>
14
15static const struct mtk_gate_regs vdec0_cg_regs = {
16	.set_ofs = 0x0000,
17	.clr_ofs = 0x0004,
18	.sta_ofs = 0x0000,
19};
20
21static const struct mtk_gate_regs vdec1_cg_regs = {
22	.set_ofs = 0x0008,
23	.clr_ofs = 0x000c,
24	.sta_ofs = 0x0008,
25};
26
27#define GATE_VDEC0(_id, _name, _parent, _shift)				\
28	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
 
 
 
 
 
 
29
30#define GATE_VDEC1(_id, _name, _parent, _shift)				\
31	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
 
 
 
 
 
 
32
33static const struct mtk_gate vdec_clks[] = {
34	GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
35	GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
36};
37
38static const struct mtk_clk_desc vdec_desc = {
39	.clks = vdec_clks,
40	.num_clks = ARRAY_SIZE(vdec_clks),
41};
42
43static const struct of_device_id of_match_clk_mt2701_vdec[] = {
44	{
45		.compatible = "mediatek,mt2701-vdecsys",
46		.data = &vdec_desc,
47	}, {
48		/* sentinel */
49	}
50};
51MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_vdec);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
52
53static struct platform_driver clk_mt2701_vdec_drv = {
54	.probe = mtk_clk_simple_probe,
55	.remove_new = mtk_clk_simple_remove,
56	.driver = {
57		.name = "clk-mt2701-vdec",
58		.of_match_table = of_match_clk_mt2701_vdec,
59	},
60};
61module_platform_driver(clk_mt2701_vdec_drv);
62MODULE_LICENSE("GPL");

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (c) 2014 MediaTek Inc.
 4 * Author: Shunli Wang <shunli.wang@mediatek.com>
 5 */
 6
 7#include <linux/clk-provider.h>
 8#include <linux/platform_device.h>
 9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt2701-clk.h>
14
15static const struct mtk_gate_regs vdec0_cg_regs = {
16	.set_ofs = 0x0000,
17	.clr_ofs = 0x0004,
18	.sta_ofs = 0x0000,
19};
20
21static const struct mtk_gate_regs vdec1_cg_regs = {
22	.set_ofs = 0x0008,
23	.clr_ofs = 0x000c,
24	.sta_ofs = 0x0008,
25};
26
27#define GATE_VDEC0(_id, _name, _parent, _shift) {	\
28		.id = _id,				\
29		.name = _name,				\
30		.parent_name = _parent,			\
31		.regs = &vdec0_cg_regs,			\
32		.shift = _shift,			\
33		.ops = &mtk_clk_gate_ops_setclr_inv,	\
34	}
35
36#define GATE_VDEC1(_id, _name, _parent, _shift) {	\
37		.id = _id,				\
38		.name = _name,				\
39		.parent_name = _parent,			\
40		.regs = &vdec1_cg_regs,			\
41		.shift = _shift,			\
42		.ops = &mtk_clk_gate_ops_setclr_inv,	\
43	}
44
45static const struct mtk_gate vdec_clks[] = {
46	GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
47	GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
48};
49
 
 
 
 
 
50static const struct of_device_id of_match_clk_mt2701_vdec[] = {
51	{ .compatible = "mediatek,mt2701-vdecsys", },
52	{}
 
 
 
 
53};
54
55static int clk_mt2701_vdec_probe(struct platform_device *pdev)
56{
57	struct clk_onecell_data *clk_data;
58	int r;
59	struct device_node *node = pdev->dev.of_node;
60
61	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
62
63	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
64						clk_data);
65
66	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
67	if (r)
68		dev_err(&pdev->dev,
69			"could not register clock provider: %s: %d\n",
70			pdev->name, r);
71
72	return r;
73}
74
75static struct platform_driver clk_mt2701_vdec_drv = {
76	.probe = clk_mt2701_vdec_probe,
 
77	.driver = {
78		.name = "clk-mt2701-vdec",
79		.of_match_table = of_match_clk_mt2701_vdec,
80	},
81};
82
83builtin_platform_driver(clk_mt2701_vdec_drv);