1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Performance counter support for POWER10 processors.
 4 *
 5 * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
 6 * Copyright 2020 Athira Rajeev, IBM Corporation.
 7 */
 8
 9/*
10 * Power10 event codes.
11 */
12EVENT(PM_CYC,				0x600f4);
13EVENT(PM_DISP_STALL_CYC,			0x100f8);
14EVENT(PM_EXEC_STALL,				0x30008);
15EVENT(PM_INST_CMPL,				0x500fa);
16EVENT(PM_BR_CMPL,                               0x4d05e);
17EVENT(PM_BR_MPRED_CMPL,                         0x400f6);
18EVENT(PM_BR_FIN,				0x2f04a);
19EVENT(PM_MPRED_BR_FIN,				0x3e098);
20EVENT(PM_LD_DEMAND_MISS_L1_FIN,			0x400f0);
21
22/* All L1 D cache load references counted at finish, gated by reject */
23EVENT(PM_LD_REF_L1,				0x100fc);
24/* Load Missed L1 */
25EVENT(PM_LD_MISS_L1,				0x3e054);
26/* Store Missed L1 */
27EVENT(PM_ST_MISS_L1,				0x300f0);
28/* L1 cache data prefetches */
29EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS,		0x1002c);
30/* Demand iCache Miss */
31EVENT(PM_L1_ICACHE_MISS,			0x200fc);
32/* Instruction fetches from L1 */
33EVENT(PM_INST_FROM_L1,				0x04080);
34/* Instruction Demand sectors wriittent into IL1 */
35EVENT(PM_INST_FROM_L1MISS,			0x03f00000001c040);
36/* Instruction prefetch written into IL1 */
37EVENT(PM_IC_PREF_REQ,				0x040a0);
38/* The data cache was reloaded from local core's L3 due to a demand load */
39EVENT(PM_DATA_FROM_L3,				0x01340000001c040);
40/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
41EVENT(PM_DATA_FROM_L3MISS,			0x300fe);
42/* All successful D-side store dispatches for this thread */
43EVENT(PM_L2_ST,					0x010000046080);
44/* All successful D-side store dispatches for this thread that were L2 Miss */
45EVENT(PM_L2_ST_MISS,				0x26880);
46/* Total HW L3 prefetches(Load+store) */
47EVENT(PM_L3_PF_MISS_L3,				0x100000016080);
48/* Data PTEG reload */
49EVENT(PM_DTLB_MISS,				0x300fc);
50/* ITLB Reloaded */
51EVENT(PM_ITLB_MISS,				0x400fc);
52
53EVENT(PM_CYC_ALT,				0x0001e);
54EVENT(PM_INST_CMPL_ALT,				0x00002);
55
56/*
57 * Memory Access Events
58 *
59 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
60 * To enable capturing of memory profiling, these MMCRA bits
61 * needs to be programmed and corresponding raw event format
62 * encoding.
63 *
64 * MMCRA bits encoding needed are
65 *     SM (Sampling Mode)
66 *     EM (Eligibility for Random Sampling)
67 *     TECE (Threshold Event Counter Event)
68 *     TS (Threshold Start Event)
69 *     TE (Threshold End Event)
70 *
71 * Corresponding Raw Encoding bits:
72 *     sample [EM,SM]
73 *     thresh_sel (TECE)
74 *     thresh start (TS)
75 *     thresh end (TE)
76 */
77
78EVENT(MEM_LOADS,				0x35340401e0);
79EVENT(MEM_STORES,				0x353c0401e0);

 1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Performance counter support for POWER10 processors.
 4 *
 5 * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
 6 * Copyright 2020 Athira Rajeev, IBM Corporation.
 7 */
 8
 9/*
10 * Power10 event codes.
11 */
12EVENT(PM_RUN_CYC,				0x600f4);
13EVENT(PM_DISP_STALL_CYC,			0x100f8);
14EVENT(PM_EXEC_STALL,				0x30008);
15EVENT(PM_RUN_INST_CMPL,				0x500fa);
16EVENT(PM_BR_CMPL,                               0x4d05e);
17EVENT(PM_BR_MPRED_CMPL,                         0x400f6);
 
 
 
18
19/* All L1 D cache load references counted at finish, gated by reject */
20EVENT(PM_LD_REF_L1,				0x100fc);
21/* Load Missed L1 */
22EVENT(PM_LD_MISS_L1,				0x3e054);
23/* Store Missed L1 */
24EVENT(PM_ST_MISS_L1,				0x300f0);
25/* L1 cache data prefetches */
26EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS,		0x1002c);
27/* Demand iCache Miss */
28EVENT(PM_L1_ICACHE_MISS,			0x200fc);
29/* Instruction fetches from L1 */
30EVENT(PM_INST_FROM_L1,				0x04080);
31/* Instruction Demand sectors wriittent into IL1 */
32EVENT(PM_INST_FROM_L1MISS,			0x03f00000001c040);
33/* Instruction prefetch written into IL1 */
34EVENT(PM_IC_PREF_REQ,				0x040a0);
35/* The data cache was reloaded from local core's L3 due to a demand load */
36EVENT(PM_DATA_FROM_L3,				0x01340000001c040);
37/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
38EVENT(PM_DATA_FROM_L3MISS,			0x300fe);
 
 
 
 
 
 
39/* Data PTEG reload */
40EVENT(PM_DTLB_MISS,				0x300fc);
41/* ITLB Reloaded */
42EVENT(PM_ITLB_MISS,				0x400fc);
43
44EVENT(PM_RUN_CYC_ALT,				0x0001e);
45EVENT(PM_RUN_INST_CMPL_ALT,			0x00002);
46
47/*
48 * Memory Access Events
49 *
50 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
51 * To enable capturing of memory profiling, these MMCRA bits
52 * needs to be programmed and corresponding raw event format
53 * encoding.
54 *
55 * MMCRA bits encoding needed are
56 *     SM (Sampling Mode)
57 *     EM (Eligibility for Random Sampling)
58 *     TECE (Threshold Event Counter Event)
59 *     TS (Threshold Start Event)
60 *     TE (Threshold End Event)
61 *
62 * Corresponding Raw Encoding bits:
63 *     sample [EM,SM]
64 *     thresh_sel (TECE)
65 *     thresh start (TS)
66 *     thresh end (TE)
67 */
68
69EVENT(MEM_LOADS,				0x34340401e0);
70EVENT(MEM_STORES,				0x343c0401e0);