1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef _ASM_IA64_HW_IRQ_H
  3#define _ASM_IA64_HW_IRQ_H
  4
  5/*
  6 * Copyright (C) 2001-2003 Hewlett-Packard Co
  7 *	David Mosberger-Tang <davidm@hpl.hp.com>
  8 */
  9
 10#include <linux/interrupt.h>
 11#include <linux/sched.h>
 12#include <linux/types.h>
 13#include <linux/profile.h>
 14
 15#include <asm/ptrace.h>
 16#include <asm/smp.h>
 17
 18typedef u8 ia64_vector;
 19
 20/*
 21 * 0 special
 22 *
 23 * 1,3-14 are reserved from firmware
 24 *
 25 * 16-255 (vectored external interrupts) are available
 26 *
 27 * 15 spurious interrupt (see IVR)
 28 *
 29 * 16 lowest priority, 255 highest priority
 30 *
 31 * 15 classes of 16 interrupts each.
 32 */
 33#define IA64_MIN_VECTORED_IRQ		 16
 34#define IA64_MAX_VECTORED_IRQ		255
 35#define IA64_NUM_VECTORS		256
 36
 37#define AUTO_ASSIGN			-1
 38
 39#define IA64_SPURIOUS_INT_VECTOR	0x0f
 40
 41/*
 42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
 43 */
 44#define IA64_CPEP_VECTOR		0x1c	/* corrected platform error polling vector */
 45#define IA64_CMCP_VECTOR		0x1d	/* corrected machine-check polling vector */
 46#define IA64_CPE_VECTOR			0x1e	/* corrected platform error interrupt vector */
 47#define IA64_CMC_VECTOR			0x1f	/* corrected machine-check interrupt vector */
 48/*
 49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
 50 * Use vectors 0x30-0xe7 as the default device vector range for ia64.
 51 * Platforms may choose to reduce this range in platform_irq_setup, but the
 52 * platform range must fall within
 53 *	[IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR]
 54 */
 55extern int ia64_first_device_vector;
 56extern int ia64_last_device_vector;
 57
 58#ifdef CONFIG_SMP
 59/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */
 60#define IA64_IRQ_MOVE_VECTOR		0x30	/* "move IRQ" IPI */
 61#define IA64_DEF_FIRST_DEVICE_VECTOR	0x31
 62#else
 63#define IA64_DEF_FIRST_DEVICE_VECTOR	0x30
 64#endif
 65#define IA64_DEF_LAST_DEVICE_VECTOR	0xe7
 66#define IA64_FIRST_DEVICE_VECTOR	ia64_first_device_vector
 67#define IA64_LAST_DEVICE_VECTOR		ia64_last_device_vector
 68#define IA64_MAX_DEVICE_VECTORS		(IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1)
 69#define IA64_NUM_DEVICE_VECTORS		(IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
 70
 71#define IA64_MCA_RENDEZ_VECTOR		0xe8	/* MCA rendez interrupt */
 72#define IA64_PERFMON_VECTOR		0xee	/* performance monitor interrupt vector */
 73#define IA64_TIMER_VECTOR		0xef	/* use highest-prio group 15 interrupt for timer */
 74#define	IA64_MCA_WAKEUP_VECTOR		0xf0	/* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
 75#define IA64_IPI_LOCAL_TLB_FLUSH	0xfc	/* SMP flush local TLB */
 76#define IA64_IPI_RESCHEDULE		0xfd	/* SMP reschedule */
 77#define IA64_IPI_VECTOR			0xfe	/* inter-processor interrupt vector */
 78
 79/* Used for encoding redirected irqs */
 80
 81#define IA64_IRQ_REDIRECTED		(1 << 31)
 82
 83/* IA64 inter-cpu interrupt related definitions */
 84
 85#define IA64_IPI_DEFAULT_BASE_ADDR	0xfee00000
 86
 87/* Delivery modes for inter-cpu interrupts */
 88enum {
 89        IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
 90        IA64_IPI_DM_PMI =       0x2,    /* pend a PMI */
 91        IA64_IPI_DM_NMI =       0x4,    /* pend an NMI (vector 2) */
 92        IA64_IPI_DM_INIT =      0x5,    /* pend an INIT interrupt */
 93        IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
 94};
 95
 96extern __u8 isa_irq_to_vector_map[16];
 97#define isa_irq_to_vector(x)	isa_irq_to_vector_map[(x)]
 98
 99struct irq_cfg {
100	ia64_vector vector;
101	cpumask_t domain;
102	cpumask_t old_domain;
103	unsigned move_cleanup_count;
104	u8 move_in_progress : 1;
105};
106extern spinlock_t vector_lock;
107extern struct irq_cfg irq_cfg[NR_IRQS];
108#define irq_to_domain(x)	irq_cfg[(x)].domain
109DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq);
110
111extern struct irq_chip irq_type_ia64_lsapic;	/* CPU-internal interrupt controller */
112
113#define ia64_register_ipi	ia64_native_register_ipi
114#define assign_irq_vector	ia64_native_assign_irq_vector
115#define free_irq_vector		ia64_native_free_irq_vector
116#define ia64_resend_irq		ia64_native_resend_irq
117
118extern void ia64_native_register_ipi(void);
119extern int bind_irq_vector(int irq, int vector, cpumask_t domain);
120extern int ia64_native_assign_irq_vector (int irq);	/* allocate a free vector */
121extern void ia64_native_free_irq_vector (int vector);
122extern int reserve_irq_vector (int vector);
123extern void __setup_vector_irq(int cpu);
124extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
125extern void destroy_and_reserve_irq (unsigned int irq);
126
127#ifdef CONFIG_SMP
128extern int irq_prepare_move(int irq, int cpu);
129extern void irq_complete_move(unsigned int irq);
130#else
131static inline int irq_prepare_move(int irq, int cpu) { return 0; }
132static inline void irq_complete_move(unsigned int irq) {}
133#endif
134
135static inline void ia64_native_resend_irq(unsigned int vector)
136{
137	ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
138}
139
140/*
141 * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
142 * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
143 * vectors and the Linux irq numbers.  However, larger systems may have multiple interrupt
144 * domains meaning that the translation from vector number to irq number depends on the
145 * interrupt domain that a CPU belongs to.  This API abstracts such platform-dependent
146 * differences and provides a uniform means to translate between vector and irq numbers
147 * and to obtain the irq descriptor for a given irq number.
148 */
149
150/* Extract the IA-64 vector that corresponds to IRQ.  */
151static inline ia64_vector
152irq_to_vector (int irq)
153{
154	return irq_cfg[irq].vector;
155}
156
157/*
158 * Convert the local IA-64 vector to the corresponding irq number.  This translation is
159 * done in the context of the interrupt domain that the currently executing CPU belongs
160 * to.
161 */
162static inline unsigned int
163local_vector_to_irq (ia64_vector vec)
164{
165	return __this_cpu_read(vector_irq[vec]);
166}
167
168#endif /* _ASM_IA64_HW_IRQ_H */