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1// SPDX-License-Identifier: GPL-2.0-or-later
2/***************************************************************************
3 * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
4 * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> *
5 * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> *
6 * *
7 ***************************************************************************/
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/watchdog.h>
18
19#define DRVNAME "f71808e_wdt"
20
21#define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
22#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
23#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
24
25#define SIO_REG_LDSEL 0x07 /* Logical device select */
26#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
27#define SIO_REG_DEVREV 0x22 /* Device revision */
28#define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
29#define SIO_REG_CLOCK_SEL 0x26 /* Clock select */
30#define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
31#define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
32#define SIO_REG_TSI_LEVEL_SEL 0x28 /* TSI Level select */
33#define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */
34#define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */
35#define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */
36#define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */
37#define SIO_REG_ENABLE 0x30 /* Logical device enable */
38#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
39
40#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
41#define SIO_F71808_ID 0x0901 /* Chipset ID */
42#define SIO_F71858_ID 0x0507 /* Chipset ID */
43#define SIO_F71862_ID 0x0601 /* Chipset ID */
44#define SIO_F71868_ID 0x1106 /* Chipset ID */
45#define SIO_F71869_ID 0x0814 /* Chipset ID */
46#define SIO_F71869A_ID 0x1007 /* Chipset ID */
47#define SIO_F71882_ID 0x0541 /* Chipset ID */
48#define SIO_F71889_ID 0x0723 /* Chipset ID */
49#define SIO_F81803_ID 0x1210 /* Chipset ID */
50#define SIO_F81865_ID 0x0704 /* Chipset ID */
51#define SIO_F81866_ID 0x1010 /* Chipset ID */
52#define SIO_F81966_ID 0x1502 /* F81804 chipset ID, same for f81966 */
53
54#define F71808FG_REG_WDO_CONF 0xf0
55#define F71808FG_REG_WDT_CONF 0xf5
56#define F71808FG_REG_WD_TIME 0xf6
57
58#define F71808FG_FLAG_WDOUT_EN 7
59
60#define F71808FG_FLAG_WDTMOUT_STS 6
61#define F71808FG_FLAG_WD_EN 5
62#define F71808FG_FLAG_WD_PULSE 4
63#define F71808FG_FLAG_WD_UNIT 3
64
65#define F81865_REG_WDO_CONF 0xfa
66#define F81865_FLAG_WDOUT_EN 0
67
68/* Default values */
69#define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */
70#define WATCHDOG_MAX_TIMEOUT (60 * 255)
71#define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for
72 watchdog signal */
73#define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output
74 pin number 63 */
75
76static unsigned short force_id;
77module_param(force_id, ushort, 0);
78MODULE_PARM_DESC(force_id, "Override the detected device ID");
79
80static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */
81module_param(timeout, int, 0);
82MODULE_PARM_DESC(timeout,
83 "Watchdog timeout in seconds. 1<= timeout <="
84 __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default="
85 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
86
87static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH;
88module_param(pulse_width, uint, 0);
89MODULE_PARM_DESC(pulse_width,
90 "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
91 " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")");
92
93static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN;
94module_param(f71862fg_pin, uint, 0);
95MODULE_PARM_DESC(f71862fg_pin,
96 "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
97 " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")");
98
99static bool nowayout = WATCHDOG_NOWAYOUT;
100module_param(nowayout, bool, 0444);
101MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
102
103static unsigned int start_withtimeout;
104module_param(start_withtimeout, uint, 0);
105MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
106 " given initial timeout. Zero (default) disables this feature.");
107
108enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
109 f81803, f81865, f81866, f81966};
110
111static const char * const fintek_wdt_names[] = {
112 "f71808fg",
113 "f71858fg",
114 "f71862fg",
115 "f71868",
116 "f71869",
117 "f71882fg",
118 "f71889fg",
119 "f81803",
120 "f81865",
121 "f81866",
122 "f81966"
123};
124
125/* Super-I/O Function prototypes */
126static inline int superio_inb(int base, int reg);
127static inline int superio_inw(int base, int reg);
128static inline void superio_outb(int base, int reg, u8 val);
129static inline void superio_set_bit(int base, int reg, int bit);
130static inline void superio_clear_bit(int base, int reg, int bit);
131static inline int superio_enter(int base);
132static inline void superio_select(int base, int ld);
133static inline void superio_exit(int base);
134
135struct fintek_wdt {
136 struct watchdog_device wdd;
137 unsigned short sioaddr;
138 enum chips type;
139 struct watchdog_info ident;
140
141 u8 timer_val; /* content for the wd_time register */
142 char minutes_mode;
143 u8 pulse_val; /* pulse width flag */
144 char pulse_mode; /* enable pulse output mode? */
145};
146
147struct fintek_wdt_pdata {
148 enum chips type;
149};
150
151/* Super I/O functions */
152static inline int superio_inb(int base, int reg)
153{
154 outb(reg, base);
155 return inb(base + 1);
156}
157
158static int superio_inw(int base, int reg)
159{
160 int val;
161 val = superio_inb(base, reg) << 8;
162 val |= superio_inb(base, reg + 1);
163 return val;
164}
165
166static inline void superio_outb(int base, int reg, u8 val)
167{
168 outb(reg, base);
169 outb(val, base + 1);
170}
171
172static inline void superio_set_bit(int base, int reg, int bit)
173{
174 unsigned long val = superio_inb(base, reg);
175 __set_bit(bit, &val);
176 superio_outb(base, reg, val);
177}
178
179static inline void superio_clear_bit(int base, int reg, int bit)
180{
181 unsigned long val = superio_inb(base, reg);
182 __clear_bit(bit, &val);
183 superio_outb(base, reg, val);
184}
185
186static inline int superio_enter(int base)
187{
188 /* Don't step on other drivers' I/O space by accident */
189 if (!request_muxed_region(base, 2, DRVNAME)) {
190 pr_err("I/O address 0x%04x already in use\n", (int)base);
191 return -EBUSY;
192 }
193
194 /* according to the datasheet the key must be sent twice! */
195 outb(SIO_UNLOCK_KEY, base);
196 outb(SIO_UNLOCK_KEY, base);
197
198 return 0;
199}
200
201static inline void superio_select(int base, int ld)
202{
203 outb(SIO_REG_LDSEL, base);
204 outb(ld, base + 1);
205}
206
207static inline void superio_exit(int base)
208{
209 outb(SIO_LOCK_KEY, base);
210 release_region(base, 2);
211}
212
213static int fintek_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
214{
215 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
216
217 if (timeout > 0xff) {
218 wd->timer_val = DIV_ROUND_UP(timeout, 60);
219 wd->minutes_mode = true;
220 timeout = wd->timer_val * 60;
221 } else {
222 wd->timer_val = timeout;
223 wd->minutes_mode = false;
224 }
225
226 wdd->timeout = timeout;
227
228 return 0;
229}
230
231static int fintek_wdt_set_pulse_width(struct fintek_wdt *wd, unsigned int pw)
232{
233 unsigned int t1 = 25, t2 = 125, t3 = 5000;
234
235 if (wd->type == f71868) {
236 t1 = 30;
237 t2 = 150;
238 t3 = 6000;
239 }
240
241 if (pw <= 1) {
242 wd->pulse_val = 0;
243 } else if (pw <= t1) {
244 wd->pulse_val = 1;
245 } else if (pw <= t2) {
246 wd->pulse_val = 2;
247 } else if (pw <= t3) {
248 wd->pulse_val = 3;
249 } else {
250 pr_err("pulse width out of range\n");
251 return -EINVAL;
252 }
253
254 wd->pulse_mode = pw;
255
256 return 0;
257}
258
259static int fintek_wdt_keepalive(struct watchdog_device *wdd)
260{
261 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
262 int err;
263
264 err = superio_enter(wd->sioaddr);
265 if (err)
266 return err;
267 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
268
269 if (wd->minutes_mode)
270 /* select minutes for timer units */
271 superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
272 F71808FG_FLAG_WD_UNIT);
273 else
274 /* select seconds for timer units */
275 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
276 F71808FG_FLAG_WD_UNIT);
277
278 /* Set timer value */
279 superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME,
280 wd->timer_val);
281
282 superio_exit(wd->sioaddr);
283
284 return 0;
285}
286
287static int fintek_wdt_start(struct watchdog_device *wdd)
288{
289 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
290 int err;
291 u8 tmp;
292
293 /* Make sure we don't die as soon as the watchdog is enabled below */
294 err = fintek_wdt_keepalive(wdd);
295 if (err)
296 return err;
297
298 err = superio_enter(wd->sioaddr);
299 if (err)
300 return err;
301 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
302
303 /* Watchdog pin configuration */
304 switch (wd->type) {
305 case f71808fg:
306 /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
307 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3);
308 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3);
309 break;
310
311 case f71862fg:
312 if (f71862fg_pin == 63) {
313 /* SPI must be disabled first to use this pin! */
314 superio_clear_bit(wd->sioaddr, SIO_REG_ROM_ADDR_SEL, 6);
315 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT3, 4);
316 } else if (f71862fg_pin == 56) {
317 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
318 }
319 break;
320
321 case f71868:
322 case f71869:
323 /* GPIO14 --> WDTRST# */
324 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4);
325 break;
326
327 case f71882fg:
328 /* Set pin 56 to WDTRST# */
329 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
330 break;
331
332 case f71889fg:
333 /* set pin 40 to WDTRST# */
334 superio_outb(wd->sioaddr, SIO_REG_MFUNCT3,
335 superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);
336 break;
337
338 case f81803:
339 /* Enable TSI Level register bank */
340 superio_clear_bit(wd->sioaddr, SIO_REG_CLOCK_SEL, 3);
341 /* Set pin 27 to WDTRST# */
342 superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &
343 superio_inb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL));
344 break;
345
346 case f81865:
347 /* Set pin 70 to WDTRST# */
348 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5);
349 break;
350
351 case f81866:
352 case f81966:
353 /*
354 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
355 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
356 * BIT5: 0 -> WDTRST#
357 * 1 -> GPIO15
358 */
359 tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL);
360 tmp &= ~(BIT(3) | BIT(0));
361 tmp |= BIT(2);
362 superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
363
364 superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5);
365 break;
366
367 default:
368 /*
369 * 'default' label to shut up the compiler and catch
370 * programmer errors
371 */
372 err = -ENODEV;
373 goto exit_superio;
374 }
375
376 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
377 superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);
378
379 if (wd->type == f81865 || wd->type == f81866 || wd->type == f81966)
380 superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,
381 F81865_FLAG_WDOUT_EN);
382 else
383 superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF,
384 F71808FG_FLAG_WDOUT_EN);
385
386 superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
387 F71808FG_FLAG_WD_EN);
388
389 if (wd->pulse_mode) {
390 /* Select "pulse" output mode with given duration */
391 u8 wdt_conf = superio_inb(wd->sioaddr,
392 F71808FG_REG_WDT_CONF);
393
394 /* Set WD_PSWIDTH bits (1:0) */
395 wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_val & 0x03);
396 /* Set WD_PULSE to "pulse" mode */
397 wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
398
399 superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF,
400 wdt_conf);
401 } else {
402 /* Select "level" output mode */
403 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
404 F71808FG_FLAG_WD_PULSE);
405 }
406
407exit_superio:
408 superio_exit(wd->sioaddr);
409
410 return err;
411}
412
413static int fintek_wdt_stop(struct watchdog_device *wdd)
414{
415 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
416 int err;
417
418 err = superio_enter(wd->sioaddr);
419 if (err)
420 return err;
421 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
422
423 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
424 F71808FG_FLAG_WD_EN);
425
426 superio_exit(wd->sioaddr);
427
428 return 0;
429}
430
431static bool fintek_wdt_is_running(struct fintek_wdt *wd, u8 wdt_conf)
432{
433 return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0))
434 && (wdt_conf & BIT(F71808FG_FLAG_WD_EN));
435}
436
437static const struct watchdog_ops fintek_wdt_ops = {
438 .owner = THIS_MODULE,
439 .start = fintek_wdt_start,
440 .stop = fintek_wdt_stop,
441 .ping = fintek_wdt_keepalive,
442 .set_timeout = fintek_wdt_set_timeout,
443};
444
445static int fintek_wdt_probe(struct platform_device *pdev)
446{
447 struct device *dev = &pdev->dev;
448 struct fintek_wdt_pdata *pdata;
449 struct watchdog_device *wdd;
450 struct fintek_wdt *wd;
451 int wdt_conf, err = 0;
452 struct resource *res;
453 int sioaddr;
454
455 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
456 if (!res)
457 return -ENXIO;
458
459 sioaddr = res->start;
460
461 wd = devm_kzalloc(dev, sizeof(*wd), GFP_KERNEL);
462 if (!wd)
463 return -ENOMEM;
464
465 pdata = dev->platform_data;
466
467 wd->type = pdata->type;
468 wd->sioaddr = sioaddr;
469 wd->ident.options = WDIOF_SETTIMEOUT
470 | WDIOF_MAGICCLOSE
471 | WDIOF_KEEPALIVEPING
472 | WDIOF_CARDRESET;
473
474 snprintf(wd->ident.identity,
475 sizeof(wd->ident.identity), "%s watchdog",
476 fintek_wdt_names[wd->type]);
477
478 err = superio_enter(sioaddr);
479 if (err)
480 return err;
481 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
482
483 wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
484
485 /*
486 * We don't want WDTMOUT_STS to stick around till regular reboot.
487 * Write 1 to the bit to clear it to zero.
488 */
489 superio_outb(sioaddr, F71808FG_REG_WDT_CONF,
490 wdt_conf | BIT(F71808FG_FLAG_WDTMOUT_STS));
491
492 wdd = &wd->wdd;
493
494 if (fintek_wdt_is_running(wd, wdt_conf))
495 set_bit(WDOG_HW_RUNNING, &wdd->status);
496
497 superio_exit(sioaddr);
498
499 wdd->parent = dev;
500 wdd->info = &wd->ident;
501 wdd->ops = &fintek_wdt_ops;
502 wdd->min_timeout = 1;
503 wdd->max_timeout = WATCHDOG_MAX_TIMEOUT;
504
505 watchdog_set_drvdata(wdd, wd);
506 watchdog_set_nowayout(wdd, nowayout);
507 watchdog_stop_on_unregister(wdd);
508 watchdog_stop_on_reboot(wdd);
509 watchdog_init_timeout(wdd, start_withtimeout ?: timeout, NULL);
510
511 if (wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS))
512 wdd->bootstatus = WDIOF_CARDRESET;
513
514 /*
515 * WATCHDOG_HANDLE_BOOT_ENABLED can result in keepalive being directly
516 * called without a set_timeout before, so it needs to be done here
517 * unconditionally.
518 */
519 fintek_wdt_set_timeout(wdd, wdd->timeout);
520 fintek_wdt_set_pulse_width(wd, pulse_width);
521
522 if (start_withtimeout) {
523 err = fintek_wdt_start(wdd);
524 if (err) {
525 dev_err(dev, "cannot start watchdog timer\n");
526 return err;
527 }
528
529 set_bit(WDOG_HW_RUNNING, &wdd->status);
530 dev_info(dev, "watchdog started with initial timeout of %u sec\n",
531 start_withtimeout);
532 }
533
534 return devm_watchdog_register_device(dev, wdd);
535}
536
537static int __init fintek_wdt_find(int sioaddr)
538{
539 enum chips type;
540 u16 devid;
541 int err = superio_enter(sioaddr);
542 if (err)
543 return err;
544
545 devid = superio_inw(sioaddr, SIO_REG_MANID);
546 if (devid != SIO_FINTEK_ID) {
547 pr_debug("Not a Fintek device\n");
548 err = -ENODEV;
549 goto exit;
550 }
551
552 devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
553 switch (devid) {
554 case SIO_F71808_ID:
555 type = f71808fg;
556 break;
557 case SIO_F71862_ID:
558 type = f71862fg;
559 break;
560 case SIO_F71868_ID:
561 type = f71868;
562 break;
563 case SIO_F71869_ID:
564 case SIO_F71869A_ID:
565 type = f71869;
566 break;
567 case SIO_F71882_ID:
568 type = f71882fg;
569 break;
570 case SIO_F71889_ID:
571 type = f71889fg;
572 break;
573 case SIO_F71858_ID:
574 /* Confirmed (by datasheet) not to have a watchdog. */
575 err = -ENODEV;
576 goto exit;
577 case SIO_F81803_ID:
578 type = f81803;
579 break;
580 case SIO_F81865_ID:
581 type = f81865;
582 break;
583 case SIO_F81866_ID:
584 type = f81866;
585 break;
586 case SIO_F81966_ID:
587 type = f81966;
588 break;
589 default:
590 pr_info("Unrecognized Fintek device: %04x\n",
591 (unsigned int)devid);
592 err = -ENODEV;
593 goto exit;
594 }
595
596 pr_info("Found %s watchdog chip, revision %d\n",
597 fintek_wdt_names[type],
598 (int)superio_inb(sioaddr, SIO_REG_DEVREV));
599
600exit:
601 superio_exit(sioaddr);
602 return err ? err : type;
603}
604
605static struct platform_driver fintek_wdt_driver = {
606 .probe = fintek_wdt_probe,
607 .driver = {
608 .name = DRVNAME,
609 },
610};
611
612static struct platform_device *fintek_wdt_pdev;
613
614static int __init fintek_wdt_init(void)
615{
616 static const unsigned short addrs[] = { 0x2e, 0x4e };
617 struct fintek_wdt_pdata pdata;
618 struct resource wdt_res = {};
619 int ret;
620 int i;
621
622 if (f71862fg_pin != 63 && f71862fg_pin != 56) {
623 pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin);
624 return -EINVAL;
625 }
626
627 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
628 ret = fintek_wdt_find(addrs[i]);
629 if (ret >= 0)
630 break;
631 }
632 if (i == ARRAY_SIZE(addrs))
633 return ret;
634
635 pdata.type = ret;
636
637 ret = platform_driver_register(&fintek_wdt_driver);
638 if (ret)
639 return ret;
640
641 wdt_res.name = "superio port";
642 wdt_res.flags = IORESOURCE_IO;
643 wdt_res.start = addrs[i];
644 wdt_res.end = addrs[i] + 1;
645
646 fintek_wdt_pdev = platform_device_register_resndata(NULL, DRVNAME, -1,
647 &wdt_res, 1,
648 &pdata, sizeof(pdata));
649 if (IS_ERR(fintek_wdt_pdev)) {
650 platform_driver_unregister(&fintek_wdt_driver);
651 return PTR_ERR(fintek_wdt_pdev);
652 }
653
654 return 0;
655}
656
657static void __exit fintek_wdt_exit(void)
658{
659 platform_device_unregister(fintek_wdt_pdev);
660 platform_driver_unregister(&fintek_wdt_driver);
661}
662
663MODULE_DESCRIPTION("F71808E Watchdog Driver");
664MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>");
665MODULE_LICENSE("GPL");
666
667module_init(fintek_wdt_init);
668module_exit(fintek_wdt_exit);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/***************************************************************************
3 * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
4 * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> *
5 * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> *
6 * *
7 ***************************************************************************/
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/err.h>
12#include <linux/fs.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/miscdevice.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/notifier.h>
20#include <linux/reboot.h>
21#include <linux/uaccess.h>
22#include <linux/watchdog.h>
23
24#define DRVNAME "f71808e_wdt"
25
26#define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
27#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
28#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
29
30#define SIO_REG_LDSEL 0x07 /* Logical device select */
31#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
32#define SIO_REG_DEVREV 0x22 /* Device revision */
33#define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
34#define SIO_REG_CLOCK_SEL 0x26 /* Clock select */
35#define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
36#define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
37#define SIO_REG_TSI_LEVEL_SEL 0x28 /* TSI Level select */
38#define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */
39#define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */
40#define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */
41#define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */
42#define SIO_REG_ENABLE 0x30 /* Logical device enable */
43#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
44
45#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
46#define SIO_F71808_ID 0x0901 /* Chipset ID */
47#define SIO_F71858_ID 0x0507 /* Chipset ID */
48#define SIO_F71862_ID 0x0601 /* Chipset ID */
49#define SIO_F71868_ID 0x1106 /* Chipset ID */
50#define SIO_F71869_ID 0x0814 /* Chipset ID */
51#define SIO_F71869A_ID 0x1007 /* Chipset ID */
52#define SIO_F71882_ID 0x0541 /* Chipset ID */
53#define SIO_F71889_ID 0x0723 /* Chipset ID */
54#define SIO_F81803_ID 0x1210 /* Chipset ID */
55#define SIO_F81865_ID 0x0704 /* Chipset ID */
56#define SIO_F81866_ID 0x1010 /* Chipset ID */
57
58#define F71808FG_REG_WDO_CONF 0xf0
59#define F71808FG_REG_WDT_CONF 0xf5
60#define F71808FG_REG_WD_TIME 0xf6
61
62#define F71808FG_FLAG_WDOUT_EN 7
63
64#define F71808FG_FLAG_WDTMOUT_STS 6
65#define F71808FG_FLAG_WD_EN 5
66#define F71808FG_FLAG_WD_PULSE 4
67#define F71808FG_FLAG_WD_UNIT 3
68
69#define F81865_REG_WDO_CONF 0xfa
70#define F81865_FLAG_WDOUT_EN 0
71
72/* Default values */
73#define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */
74#define WATCHDOG_MAX_TIMEOUT (60 * 255)
75#define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for
76 watchdog signal */
77#define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output
78 pin number 63 */
79
80static unsigned short force_id;
81module_param(force_id, ushort, 0);
82MODULE_PARM_DESC(force_id, "Override the detected device ID");
83
84static const int max_timeout = WATCHDOG_MAX_TIMEOUT;
85static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */
86module_param(timeout, int, 0);
87MODULE_PARM_DESC(timeout,
88 "Watchdog timeout in seconds. 1<= timeout <="
89 __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default="
90 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
91
92static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH;
93module_param(pulse_width, uint, 0);
94MODULE_PARM_DESC(pulse_width,
95 "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
96 " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")");
97
98static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN;
99module_param(f71862fg_pin, uint, 0);
100MODULE_PARM_DESC(f71862fg_pin,
101 "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
102 " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")");
103
104static bool nowayout = WATCHDOG_NOWAYOUT;
105module_param(nowayout, bool, 0444);
106MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
107
108static unsigned int start_withtimeout;
109module_param(start_withtimeout, uint, 0);
110MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
111 " given initial timeout. Zero (default) disables this feature.");
112
113enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
114 f81803, f81865, f81866};
115
116static const char *f71808e_names[] = {
117 "f71808fg",
118 "f71858fg",
119 "f71862fg",
120 "f71868",
121 "f71869",
122 "f71882fg",
123 "f71889fg",
124 "f81803",
125 "f81865",
126 "f81866",
127};
128
129/* Super-I/O Function prototypes */
130static inline int superio_inb(int base, int reg);
131static inline int superio_inw(int base, int reg);
132static inline void superio_outb(int base, int reg, u8 val);
133static inline void superio_set_bit(int base, int reg, int bit);
134static inline void superio_clear_bit(int base, int reg, int bit);
135static inline int superio_enter(int base);
136static inline void superio_select(int base, int ld);
137static inline void superio_exit(int base);
138
139struct watchdog_data {
140 unsigned short sioaddr;
141 enum chips type;
142 unsigned long opened;
143 struct mutex lock;
144 char expect_close;
145 struct watchdog_info ident;
146
147 unsigned short timeout;
148 u8 timer_val; /* content for the wd_time register */
149 char minutes_mode;
150 u8 pulse_val; /* pulse width flag */
151 char pulse_mode; /* enable pulse output mode? */
152 char caused_reboot; /* last reboot was by the watchdog */
153};
154
155static struct watchdog_data watchdog = {
156 .lock = __MUTEX_INITIALIZER(watchdog.lock),
157};
158
159/* Super I/O functions */
160static inline int superio_inb(int base, int reg)
161{
162 outb(reg, base);
163 return inb(base + 1);
164}
165
166static int superio_inw(int base, int reg)
167{
168 int val;
169 val = superio_inb(base, reg) << 8;
170 val |= superio_inb(base, reg + 1);
171 return val;
172}
173
174static inline void superio_outb(int base, int reg, u8 val)
175{
176 outb(reg, base);
177 outb(val, base + 1);
178}
179
180static inline void superio_set_bit(int base, int reg, int bit)
181{
182 unsigned long val = superio_inb(base, reg);
183 __set_bit(bit, &val);
184 superio_outb(base, reg, val);
185}
186
187static inline void superio_clear_bit(int base, int reg, int bit)
188{
189 unsigned long val = superio_inb(base, reg);
190 __clear_bit(bit, &val);
191 superio_outb(base, reg, val);
192}
193
194static inline int superio_enter(int base)
195{
196 /* Don't step on other drivers' I/O space by accident */
197 if (!request_muxed_region(base, 2, DRVNAME)) {
198 pr_err("I/O address 0x%04x already in use\n", (int)base);
199 return -EBUSY;
200 }
201
202 /* according to the datasheet the key must be sent twice! */
203 outb(SIO_UNLOCK_KEY, base);
204 outb(SIO_UNLOCK_KEY, base);
205
206 return 0;
207}
208
209static inline void superio_select(int base, int ld)
210{
211 outb(SIO_REG_LDSEL, base);
212 outb(ld, base + 1);
213}
214
215static inline void superio_exit(int base)
216{
217 outb(SIO_LOCK_KEY, base);
218 release_region(base, 2);
219}
220
221static int watchdog_set_timeout(int timeout)
222{
223 if (timeout <= 0
224 || timeout > max_timeout) {
225 pr_err("watchdog timeout out of range\n");
226 return -EINVAL;
227 }
228
229 mutex_lock(&watchdog.lock);
230
231 watchdog.timeout = timeout;
232 if (timeout > 0xff) {
233 watchdog.timer_val = DIV_ROUND_UP(timeout, 60);
234 watchdog.minutes_mode = true;
235 } else {
236 watchdog.timer_val = timeout;
237 watchdog.minutes_mode = false;
238 }
239
240 mutex_unlock(&watchdog.lock);
241
242 return 0;
243}
244
245static int watchdog_set_pulse_width(unsigned int pw)
246{
247 int err = 0;
248 unsigned int t1 = 25, t2 = 125, t3 = 5000;
249
250 if (watchdog.type == f71868) {
251 t1 = 30;
252 t2 = 150;
253 t3 = 6000;
254 }
255
256 mutex_lock(&watchdog.lock);
257
258 if (pw <= 1) {
259 watchdog.pulse_val = 0;
260 } else if (pw <= t1) {
261 watchdog.pulse_val = 1;
262 } else if (pw <= t2) {
263 watchdog.pulse_val = 2;
264 } else if (pw <= t3) {
265 watchdog.pulse_val = 3;
266 } else {
267 pr_err("pulse width out of range\n");
268 err = -EINVAL;
269 goto exit_unlock;
270 }
271
272 watchdog.pulse_mode = pw;
273
274exit_unlock:
275 mutex_unlock(&watchdog.lock);
276 return err;
277}
278
279static int watchdog_keepalive(void)
280{
281 int err = 0;
282
283 mutex_lock(&watchdog.lock);
284 err = superio_enter(watchdog.sioaddr);
285 if (err)
286 goto exit_unlock;
287 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
288
289 if (watchdog.minutes_mode)
290 /* select minutes for timer units */
291 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
292 F71808FG_FLAG_WD_UNIT);
293 else
294 /* select seconds for timer units */
295 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
296 F71808FG_FLAG_WD_UNIT);
297
298 /* Set timer value */
299 superio_outb(watchdog.sioaddr, F71808FG_REG_WD_TIME,
300 watchdog.timer_val);
301
302 superio_exit(watchdog.sioaddr);
303
304exit_unlock:
305 mutex_unlock(&watchdog.lock);
306 return err;
307}
308
309static int f71862fg_pin_configure(unsigned short ioaddr)
310{
311 /* When ioaddr is non-zero the calling function has to take care of
312 mutex handling and superio preparation! */
313
314 if (f71862fg_pin == 63) {
315 if (ioaddr) {
316 /* SPI must be disabled first to use this pin! */
317 superio_clear_bit(ioaddr, SIO_REG_ROM_ADDR_SEL, 6);
318 superio_set_bit(ioaddr, SIO_REG_MFUNCT3, 4);
319 }
320 } else if (f71862fg_pin == 56) {
321 if (ioaddr)
322 superio_set_bit(ioaddr, SIO_REG_MFUNCT1, 1);
323 } else {
324 pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin);
325 return -EINVAL;
326 }
327 return 0;
328}
329
330static int watchdog_start(void)
331{
332 int err;
333 u8 tmp;
334
335 /* Make sure we don't die as soon as the watchdog is enabled below */
336 err = watchdog_keepalive();
337 if (err)
338 return err;
339
340 mutex_lock(&watchdog.lock);
341 err = superio_enter(watchdog.sioaddr);
342 if (err)
343 goto exit_unlock;
344 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
345
346 /* Watchdog pin configuration */
347 switch (watchdog.type) {
348 case f71808fg:
349 /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
350 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT2, 3);
351 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 3);
352 break;
353
354 case f71862fg:
355 err = f71862fg_pin_configure(watchdog.sioaddr);
356 if (err)
357 goto exit_superio;
358 break;
359
360 case f71868:
361 case f71869:
362 /* GPIO14 --> WDTRST# */
363 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4);
364 break;
365
366 case f71882fg:
367 /* Set pin 56 to WDTRST# */
368 superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1);
369 break;
370
371 case f71889fg:
372 /* set pin 40 to WDTRST# */
373 superio_outb(watchdog.sioaddr, SIO_REG_MFUNCT3,
374 superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf);
375 break;
376
377 case f81803:
378 /* Enable TSI Level register bank */
379 superio_clear_bit(watchdog.sioaddr, SIO_REG_CLOCK_SEL, 3);
380 /* Set pin 27 to WDTRST# */
381 superio_outb(watchdog.sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &
382 superio_inb(watchdog.sioaddr, SIO_REG_TSI_LEVEL_SEL));
383 break;
384
385 case f81865:
386 /* Set pin 70 to WDTRST# */
387 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5);
388 break;
389
390 case f81866:
391 /*
392 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
393 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
394 * BIT5: 0 -> WDTRST#
395 * 1 -> GPIO15
396 */
397 tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL);
398 tmp &= ~(BIT(3) | BIT(0));
399 tmp |= BIT(2);
400 superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
401
402 superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);
403 break;
404
405 default:
406 /*
407 * 'default' label to shut up the compiler and catch
408 * programmer errors
409 */
410 err = -ENODEV;
411 goto exit_superio;
412 }
413
414 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
415 superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0);
416
417 if (watchdog.type == f81865 || watchdog.type == f81866)
418 superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF,
419 F81865_FLAG_WDOUT_EN);
420 else
421 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
422 F71808FG_FLAG_WDOUT_EN);
423
424 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
425 F71808FG_FLAG_WD_EN);
426
427 if (watchdog.pulse_mode) {
428 /* Select "pulse" output mode with given duration */
429 u8 wdt_conf = superio_inb(watchdog.sioaddr,
430 F71808FG_REG_WDT_CONF);
431
432 /* Set WD_PSWIDTH bits (1:0) */
433 wdt_conf = (wdt_conf & 0xfc) | (watchdog.pulse_val & 0x03);
434 /* Set WD_PULSE to "pulse" mode */
435 wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
436
437 superio_outb(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
438 wdt_conf);
439 } else {
440 /* Select "level" output mode */
441 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
442 F71808FG_FLAG_WD_PULSE);
443 }
444
445exit_superio:
446 superio_exit(watchdog.sioaddr);
447exit_unlock:
448 mutex_unlock(&watchdog.lock);
449
450 return err;
451}
452
453static int watchdog_stop(void)
454{
455 int err = 0;
456
457 mutex_lock(&watchdog.lock);
458 err = superio_enter(watchdog.sioaddr);
459 if (err)
460 goto exit_unlock;
461 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
462
463 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
464 F71808FG_FLAG_WD_EN);
465
466 superio_exit(watchdog.sioaddr);
467
468exit_unlock:
469 mutex_unlock(&watchdog.lock);
470
471 return err;
472}
473
474static int watchdog_get_status(void)
475{
476 int status = 0;
477
478 mutex_lock(&watchdog.lock);
479 status = (watchdog.caused_reboot) ? WDIOF_CARDRESET : 0;
480 mutex_unlock(&watchdog.lock);
481
482 return status;
483}
484
485static bool watchdog_is_running(void)
486{
487 /*
488 * if we fail to determine the watchdog's status assume it to be
489 * running to be on the safe side
490 */
491 bool is_running = true;
492
493 mutex_lock(&watchdog.lock);
494 if (superio_enter(watchdog.sioaddr))
495 goto exit_unlock;
496 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
497
498 is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
499 && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
500 & BIT(F71808FG_FLAG_WD_EN));
501
502 superio_exit(watchdog.sioaddr);
503
504exit_unlock:
505 mutex_unlock(&watchdog.lock);
506 return is_running;
507}
508
509/* /dev/watchdog api */
510
511static int watchdog_open(struct inode *inode, struct file *file)
512{
513 int err;
514
515 /* If the watchdog is alive we don't need to start it again */
516 if (test_and_set_bit(0, &watchdog.opened))
517 return -EBUSY;
518
519 err = watchdog_start();
520 if (err) {
521 clear_bit(0, &watchdog.opened);
522 return err;
523 }
524
525 if (nowayout)
526 __module_get(THIS_MODULE);
527
528 watchdog.expect_close = 0;
529 return stream_open(inode, file);
530}
531
532static int watchdog_release(struct inode *inode, struct file *file)
533{
534 clear_bit(0, &watchdog.opened);
535
536 if (!watchdog.expect_close) {
537 watchdog_keepalive();
538 pr_crit("Unexpected close, not stopping watchdog!\n");
539 } else if (!nowayout) {
540 watchdog_stop();
541 }
542 return 0;
543}
544
545/*
546 * watchdog_write:
547 * @file: file handle to the watchdog
548 * @buf: buffer to write
549 * @count: count of bytes
550 * @ppos: pointer to the position to write. No seeks allowed
551 *
552 * A write to a watchdog device is defined as a keepalive signal. Any
553 * write of data will do, as we we don't define content meaning.
554 */
555
556static ssize_t watchdog_write(struct file *file, const char __user *buf,
557 size_t count, loff_t *ppos)
558{
559 if (count) {
560 if (!nowayout) {
561 size_t i;
562
563 /* In case it was set long ago */
564 bool expect_close = false;
565
566 for (i = 0; i != count; i++) {
567 char c;
568 if (get_user(c, buf + i))
569 return -EFAULT;
570 if (c == 'V')
571 expect_close = true;
572 }
573
574 /* Properly order writes across fork()ed processes */
575 mutex_lock(&watchdog.lock);
576 watchdog.expect_close = expect_close;
577 mutex_unlock(&watchdog.lock);
578 }
579
580 /* someone wrote to us, we should restart timer */
581 watchdog_keepalive();
582 }
583 return count;
584}
585
586/*
587 * watchdog_ioctl:
588 * @inode: inode of the device
589 * @file: file handle to the device
590 * @cmd: watchdog command
591 * @arg: argument pointer
592 *
593 * The watchdog API defines a common set of functions for all watchdogs
594 * according to their available features.
595 */
596static long watchdog_ioctl(struct file *file, unsigned int cmd,
597 unsigned long arg)
598{
599 int status;
600 int new_options;
601 int new_timeout;
602 union {
603 struct watchdog_info __user *ident;
604 int __user *i;
605 } uarg;
606
607 uarg.i = (int __user *)arg;
608
609 switch (cmd) {
610 case WDIOC_GETSUPPORT:
611 return copy_to_user(uarg.ident, &watchdog.ident,
612 sizeof(watchdog.ident)) ? -EFAULT : 0;
613
614 case WDIOC_GETSTATUS:
615 status = watchdog_get_status();
616 if (status < 0)
617 return status;
618 return put_user(status, uarg.i);
619
620 case WDIOC_GETBOOTSTATUS:
621 return put_user(0, uarg.i);
622
623 case WDIOC_SETOPTIONS:
624 if (get_user(new_options, uarg.i))
625 return -EFAULT;
626
627 if (new_options & WDIOS_DISABLECARD)
628 watchdog_stop();
629
630 if (new_options & WDIOS_ENABLECARD)
631 return watchdog_start();
632 /* fall through */
633
634 case WDIOC_KEEPALIVE:
635 watchdog_keepalive();
636 return 0;
637
638 case WDIOC_SETTIMEOUT:
639 if (get_user(new_timeout, uarg.i))
640 return -EFAULT;
641
642 if (watchdog_set_timeout(new_timeout))
643 return -EINVAL;
644
645 watchdog_keepalive();
646 /* fall through */
647
648 case WDIOC_GETTIMEOUT:
649 return put_user(watchdog.timeout, uarg.i);
650
651 default:
652 return -ENOTTY;
653
654 }
655}
656
657static int watchdog_notify_sys(struct notifier_block *this, unsigned long code,
658 void *unused)
659{
660 if (code == SYS_DOWN || code == SYS_HALT)
661 watchdog_stop();
662 return NOTIFY_DONE;
663}
664
665static const struct file_operations watchdog_fops = {
666 .owner = THIS_MODULE,
667 .llseek = no_llseek,
668 .open = watchdog_open,
669 .release = watchdog_release,
670 .write = watchdog_write,
671 .unlocked_ioctl = watchdog_ioctl,
672};
673
674static struct miscdevice watchdog_miscdev = {
675 .minor = WATCHDOG_MINOR,
676 .name = "watchdog",
677 .fops = &watchdog_fops,
678};
679
680static struct notifier_block watchdog_notifier = {
681 .notifier_call = watchdog_notify_sys,
682};
683
684static int __init watchdog_init(int sioaddr)
685{
686 int wdt_conf, err = 0;
687
688 /* No need to lock watchdog.lock here because no entry points
689 * into the module have been registered yet.
690 */
691 watchdog.sioaddr = sioaddr;
692 watchdog.ident.options = WDIOC_SETTIMEOUT
693 | WDIOF_MAGICCLOSE
694 | WDIOF_KEEPALIVEPING;
695
696 snprintf(watchdog.ident.identity,
697 sizeof(watchdog.ident.identity), "%s watchdog",
698 f71808e_names[watchdog.type]);
699
700 err = superio_enter(sioaddr);
701 if (err)
702 return err;
703 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
704
705 wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
706 watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS);
707
708 superio_exit(sioaddr);
709
710 err = watchdog_set_timeout(timeout);
711 if (err)
712 return err;
713 err = watchdog_set_pulse_width(pulse_width);
714 if (err)
715 return err;
716
717 err = register_reboot_notifier(&watchdog_notifier);
718 if (err)
719 return err;
720
721 err = misc_register(&watchdog_miscdev);
722 if (err) {
723 pr_err("cannot register miscdev on minor=%d\n",
724 watchdog_miscdev.minor);
725 goto exit_reboot;
726 }
727
728 if (start_withtimeout) {
729 if (start_withtimeout <= 0
730 || start_withtimeout > max_timeout) {
731 pr_err("starting timeout out of range\n");
732 err = -EINVAL;
733 goto exit_miscdev;
734 }
735
736 err = watchdog_start();
737 if (err) {
738 pr_err("cannot start watchdog timer\n");
739 goto exit_miscdev;
740 }
741
742 mutex_lock(&watchdog.lock);
743 err = superio_enter(sioaddr);
744 if (err)
745 goto exit_unlock;
746 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
747
748 if (start_withtimeout > 0xff) {
749 /* select minutes for timer units */
750 superio_set_bit(sioaddr, F71808FG_REG_WDT_CONF,
751 F71808FG_FLAG_WD_UNIT);
752 superio_outb(sioaddr, F71808FG_REG_WD_TIME,
753 DIV_ROUND_UP(start_withtimeout, 60));
754 } else {
755 /* select seconds for timer units */
756 superio_clear_bit(sioaddr, F71808FG_REG_WDT_CONF,
757 F71808FG_FLAG_WD_UNIT);
758 superio_outb(sioaddr, F71808FG_REG_WD_TIME,
759 start_withtimeout);
760 }
761
762 superio_exit(sioaddr);
763 mutex_unlock(&watchdog.lock);
764
765 if (nowayout)
766 __module_get(THIS_MODULE);
767
768 pr_info("watchdog started with initial timeout of %u sec\n",
769 start_withtimeout);
770 }
771
772 return 0;
773
774exit_unlock:
775 mutex_unlock(&watchdog.lock);
776exit_miscdev:
777 misc_deregister(&watchdog_miscdev);
778exit_reboot:
779 unregister_reboot_notifier(&watchdog_notifier);
780
781 return err;
782}
783
784static int __init f71808e_find(int sioaddr)
785{
786 u16 devid;
787 int err = superio_enter(sioaddr);
788 if (err)
789 return err;
790
791 devid = superio_inw(sioaddr, SIO_REG_MANID);
792 if (devid != SIO_FINTEK_ID) {
793 pr_debug("Not a Fintek device\n");
794 err = -ENODEV;
795 goto exit;
796 }
797
798 devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
799 switch (devid) {
800 case SIO_F71808_ID:
801 watchdog.type = f71808fg;
802 break;
803 case SIO_F71862_ID:
804 watchdog.type = f71862fg;
805 err = f71862fg_pin_configure(0); /* validate module parameter */
806 break;
807 case SIO_F71868_ID:
808 watchdog.type = f71868;
809 break;
810 case SIO_F71869_ID:
811 case SIO_F71869A_ID:
812 watchdog.type = f71869;
813 break;
814 case SIO_F71882_ID:
815 watchdog.type = f71882fg;
816 break;
817 case SIO_F71889_ID:
818 watchdog.type = f71889fg;
819 break;
820 case SIO_F71858_ID:
821 /* Confirmed (by datasheet) not to have a watchdog. */
822 err = -ENODEV;
823 goto exit;
824 case SIO_F81803_ID:
825 watchdog.type = f81803;
826 break;
827 case SIO_F81865_ID:
828 watchdog.type = f81865;
829 break;
830 case SIO_F81866_ID:
831 watchdog.type = f81866;
832 break;
833 default:
834 pr_info("Unrecognized Fintek device: %04x\n",
835 (unsigned int)devid);
836 err = -ENODEV;
837 goto exit;
838 }
839
840 pr_info("Found %s watchdog chip, revision %d\n",
841 f71808e_names[watchdog.type],
842 (int)superio_inb(sioaddr, SIO_REG_DEVREV));
843exit:
844 superio_exit(sioaddr);
845 return err;
846}
847
848static int __init f71808e_init(void)
849{
850 static const unsigned short addrs[] = { 0x2e, 0x4e };
851 int err = -ENODEV;
852 int i;
853
854 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
855 err = f71808e_find(addrs[i]);
856 if (err == 0)
857 break;
858 }
859 if (i == ARRAY_SIZE(addrs))
860 return err;
861
862 return watchdog_init(addrs[i]);
863}
864
865static void __exit f71808e_exit(void)
866{
867 if (watchdog_is_running()) {
868 pr_warn("Watchdog timer still running, stopping it\n");
869 watchdog_stop();
870 }
871 misc_deregister(&watchdog_miscdev);
872 unregister_reboot_notifier(&watchdog_notifier);
873}
874
875MODULE_DESCRIPTION("F71808E Watchdog Driver");
876MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>");
877MODULE_LICENSE("GPL");
878
879module_init(f71808e_init);
880module_exit(f71808e_exit);