1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
  4 *
  5 * Copyright (C) 2015 Intel Corporation
  6 *
  7 * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
  8 */
  9
 10#include <linux/delay.h>
 11#include <linux/time64.h>
 12#include <linux/ulpi/regs.h>
 13
 14#include "core.h"
 15#include "io.h"
 16
 17#define DWC3_ULPI_ADDR(a) \
 18		((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
 19		DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
 20		DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
 21
 22#define DWC3_ULPI_BASE_DELAY	DIV_ROUND_UP(NSEC_PER_SEC, 60000000L)
 23
 24static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read)
 25{
 26	unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY;
 27	unsigned int count = 10000;
 28	u32 reg;
 29
 30	if (addr >= ULPI_EXT_VENDOR_SPECIFIC)
 31		ns += DWC3_ULPI_BASE_DELAY;
 32
 33	if (read)
 34		ns += DWC3_ULPI_BASE_DELAY;
 35
 36	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 37	if (reg & DWC3_GUSB2PHYCFG_SUSPHY)
 38		usleep_range(1000, 1200);
 39
 40	while (count--) {
 41		ndelay(ns);
 42		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
 43		if (reg & DWC3_GUSB2PHYACC_DONE)
 44			return 0;
 45		cpu_relax();
 46	}
 47
 48	return -ETIMEDOUT;
 49}
 50
 51static int dwc3_ulpi_read(struct device *dev, u8 addr)
 52{
 53	struct dwc3 *dwc = dev_get_drvdata(dev);
 54	u32 reg;
 55	int ret;
 56
 
 
 
 
 
 
 57	reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
 58	dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
 59
 60	ret = dwc3_ulpi_busyloop(dwc, addr, true);
 61	if (ret)
 62		return ret;
 63
 64	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
 65
 66	return DWC3_GUSB2PHYACC_DATA(reg);
 67}
 68
 69static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
 70{
 71	struct dwc3 *dwc = dev_get_drvdata(dev);
 72	u32 reg;
 73
 
 
 
 
 
 
 74	reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
 75	reg |= DWC3_GUSB2PHYACC_WRITE | val;
 76	dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
 77
 78	return dwc3_ulpi_busyloop(dwc, addr, false);
 79}
 80
 81static const struct ulpi_ops dwc3_ulpi_ops = {
 82	.read = dwc3_ulpi_read,
 83	.write = dwc3_ulpi_write,
 84};
 85
 86int dwc3_ulpi_init(struct dwc3 *dwc)
 87{
 88	/* Register the interface */
 89	dwc->ulpi = ulpi_register_interface(dwc->dev, &dwc3_ulpi_ops);
 90	if (IS_ERR(dwc->ulpi)) {
 91		dev_err(dwc->dev, "failed to register ULPI interface");
 92		return PTR_ERR(dwc->ulpi);
 93	}
 94
 95	return 0;
 96}
 97
 98void dwc3_ulpi_exit(struct dwc3 *dwc)
 99{
100	if (dwc->ulpi) {
101		ulpi_unregister_interface(dwc->ulpi);
102		dwc->ulpi = NULL;
103	}
104}

  1// SPDX-License-Identifier: GPL-2.0
  2/**
  3 * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
  4 *
  5 * Copyright (C) 2015 Intel Corporation
  6 *
  7 * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
  8 */
  9
 
 
 10#include <linux/ulpi/regs.h>
 11
 12#include "core.h"
 13#include "io.h"
 14
 15#define DWC3_ULPI_ADDR(a) \
 16		((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
 17		DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
 18		DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
 19
 20static int dwc3_ulpi_busyloop(struct dwc3 *dwc)
 
 
 21{
 22	unsigned count = 1000;
 
 23	u32 reg;
 24
 
 
 
 
 
 
 
 
 
 
 25	while (count--) {
 
 26		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
 27		if (!(reg & DWC3_GUSB2PHYACC_BUSY))
 28			return 0;
 29		cpu_relax();
 30	}
 31
 32	return -ETIMEDOUT;
 33}
 34
 35static int dwc3_ulpi_read(struct device *dev, u8 addr)
 36{
 37	struct dwc3 *dwc = dev_get_drvdata(dev);
 38	u32 reg;
 39	int ret;
 40
 41	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 42	if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
 43		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 44		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 45	}
 46
 47	reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
 48	dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
 49
 50	ret = dwc3_ulpi_busyloop(dwc);
 51	if (ret)
 52		return ret;
 53
 54	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
 55
 56	return DWC3_GUSB2PHYACC_DATA(reg);
 57}
 58
 59static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
 60{
 61	struct dwc3 *dwc = dev_get_drvdata(dev);
 62	u32 reg;
 63
 64	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 65	if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
 66		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 67		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 68	}
 69
 70	reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
 71	reg |= DWC3_GUSB2PHYACC_WRITE | val;
 72	dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
 73
 74	return dwc3_ulpi_busyloop(dwc);
 75}
 76
 77static const struct ulpi_ops dwc3_ulpi_ops = {
 78	.read = dwc3_ulpi_read,
 79	.write = dwc3_ulpi_write,
 80};
 81
 82int dwc3_ulpi_init(struct dwc3 *dwc)
 83{
 84	/* Register the interface */
 85	dwc->ulpi = ulpi_register_interface(dwc->dev, &dwc3_ulpi_ops);
 86	if (IS_ERR(dwc->ulpi)) {
 87		dev_err(dwc->dev, "failed to register ULPI interface");
 88		return PTR_ERR(dwc->ulpi);
 89	}
 90
 91	return 0;
 92}
 93
 94void dwc3_ulpi_exit(struct dwc3 *dwc)
 95{
 96	if (dwc->ulpi) {
 97		ulpi_unregister_interface(dwc->ulpi);
 98		dwc->ulpi = NULL;
 99	}
100}